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Overview
| Comment: | First stage of integrating the Silcon Labs bluetooth stack with the micca run-time is working. Am able to build a minimal (almost empty) GATT application and connect to it and resolve all the services in the same way as the Thundersense 2 demo worked (modulo the added services the demo has). There seems to be some reliablity issue and there is much more tweeking to be done, but it seems that the strategy for running the BLE stack through micca works. |
|---|---|
| Downloads: | Tarball | ZIP archive | SQL archive |
| Timelines: | family | ancestors | descendants | both | trunk |
| Files: | files | file ages | folders |
| SHA3-256: |
7608c6da088333516b21524099344949 |
| User & Date: | andrewm 2019-02-10 16:56:26 |
Context
|
2019-02-10
| ||
| 22:18 | Flesh out gattdb with an option to preload attributes. check-in: f81b92ef95 user: glenl tags: trunk | |
| 16:56 | First stage of integrating the Silcon Labs bluetooth stack with the micca run-time is working. Am able to build a minimal (almost empty) GATT application and connect to it and resolve all the services in the same way as the Thundersense 2 demo worked (modulo the added services the demo has). There seems to be some reliablity issue and there is much more tweeking to be done, but it seems that the strategy for running the BLE stack through micca works. check-in: 7608c6da08 user: andrewm tags: trunk | |
| 12:15 | Additional work on the integration of micca run-time and bluetooth stack. check-in: 1e37f91afb user: andrewm tags: trunk | |
Changes
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/.cproject.
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Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/.project.
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Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/app.c.
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/***************************************************************************//** * @file app.c * @brief Silicon Labs Empty Example Project * * This example demonstrates the bare minimum needed for a Blue Gecko C application * that allows Over-the-Air Device Firmware Upgrading (OTA DFU). The application * starts advertising after boot and restarts advertising after a connection is closed. ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * The licensor of this software is Silicon Laboratories Inc. Your use of this * software is governed by the terms of Silicon Labs Master Software License * Agreement (MSLA) available at * www.silabs.com/about-us/legal/master-software-license-agreement. This * software is distributed to you in Source Code format and is governed by the * sections of the MSLA applicable to Source Code. * ******************************************************************************/ /* Bluetooth stack headers */ #include "bg_types.h" #include "micca_gecko.h" #include "gatt_db.h" #include "micca_rt.h" #include "app.h" /* Print boot message */ static void bootMessage(struct gecko_msg_system_boot_evt_t *bootevt); /* Flag for indicating DFU Reset must be performed */ static uint8_t boot_to_dfu = 0; /* Main application */ void appMain(gecko_configuration_t *pconfig) { #if DISABLE_SLEEP > 0 pconfig->sleep.flags = 0; #endif /* Initialize debug prints. Note: debug prints are off by default. See DEBUG_LEVEL in app.h */ initLog(); mrt_Initialize() ; /* Initialize stack */ gecko_init(pconfig); mrt_EventLoop() ; } /* Print stack version and local Bluetooth address as boot message */ static void bootMessage(struct gecko_msg_system_boot_evt_t *bootevt) { #if DEBUG_LEVEL bd_addr local_addr; int i; printLog("stack version: %u.%u.%u\r\n", bootevt->major, bootevt->minor, bootevt->patch); local_addr = gecko_cmd_system_get_bt_address()->address; printLog("local BT device address: "); for (i = 0; i < 5; i++) { printLog("%2.2x:", local_addr.addr[5 - i]); } printLog("%2.2x\r\n", local_addr.addr[0]); #endif } void handle_bluetooth_event( struct gecko_cmd_packet *evt) { /* Handle events */ switch (BGLIB_MSG_ID(evt->header)) { /* This boot event is generated when the system boots up after reset. * Do not call any stack commands before receiving the boot event. * Here the system is set to start advertising immediately after boot procedure. */ case gecko_evt_system_boot_id: bootMessage(&(evt->data.evt_system_boot)); printLog("boot event - starting advertising\r\n"); /* Set advertising parameters. 100ms advertisement interval. * The first parameter is advertising set handle * The next two parameters are minimum and maximum advertising interval, both in * units of (milliseconds * 1.6). * The last two parameters are duration and maxevents left as default. */ gecko_cmd_le_gap_set_advertise_timing(0, 160, 160, 0, 0); /* Start general advertising and enable connections. */ gecko_cmd_le_gap_start_advertising(0, le_gap_general_discoverable, le_gap_connectable_scannable); break; case gecko_evt_le_connection_opened_id: printLog("connection opened\r\n"); gecko_cmd_le_gap_stop_advertising(0) ; break; case gecko_evt_le_connection_closed_id: printLog("connection closed, reason: 0x%2.2x\r\n", evt->data.evt_le_connection_closed.reason); /* Check if need to boot to OTA DFU mode */ if (boot_to_dfu) { /* Enter to OTA DFU mode */ gecko_cmd_system_reset(2); } else { /* Restart advertising after client has disconnected */ gecko_cmd_le_gap_start_advertising(0, le_gap_general_discoverable, le_gap_connectable_scannable); } break; /* Events related to OTA upgrading ----------------------------------------------------------------------------- */ /* Check if the user-type OTA Control Characteristic was written. * If ota_control was written, boot the device into Device Firmware Upgrade (DFU) mode. */ case gecko_evt_gatt_server_user_write_request_id: if (evt->data.evt_gatt_server_user_write_request.characteristic == gattdb_ota_control) { /* Set flag to enter to OTA mode */ boot_to_dfu = 1; /* Send response to Write Request */ gecko_cmd_gatt_server_send_user_write_response( evt->data.evt_gatt_server_user_write_request.connection, gattdb_ota_control, bg_err_success); /* Close connection to enter to DFU OTA mode */ gecko_cmd_le_connection_close(evt->data.evt_gatt_server_user_write_request.connection); } break; /* Add additional event handlers as your application requires */ default: break; } } static void service_ble_link( MRT_SyncParams const *params) // not used { gecko_priority_handle() ; } void micca_schedule_link(void) { mrt_SyncRequest(service_ble_link) ; } #include "ble.h" static void service_ble_stack( MRT_SyncParams const *params) // not used { ble_stack_update(BLE_SEQUENCER_SEQ1_INSTID) ; } void micca_schedule_stack(void) { mrt_SyncRequest(service_ble_stack) ; } |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/app.h.
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/***************************************************************************//** * @brief app.h ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * The licensor of this software is Silicon Laboratories Inc. Your use of this * software is governed by the terms of Silicon Labs Master Software License * Agreement (MSLA) available at * www.silabs.com/about-us/legal/master-software-license-agreement. This * software is distributed to you in Source Code format and is governed by the * sections of the MSLA applicable to Source Code. * ******************************************************************************/ #ifndef APP_H_ #define APP_H_ #include "gecko_configuration.h" /* DEBUG_LEVEL is used to enable/disable debug prints. Set DEBUG_LEVEL to 1 to enable debug prints */ #define DEBUG_LEVEL 1 /* Set this value to 1 if you want to disable deep sleep completely */ #define DISABLE_SLEEP 0 #if DEBUG_LEVEL #include "retargetserial.h" #include <stdio.h> #endif #if DEBUG_LEVEL #define initLog() RETARGET_SerialInit() #define flushLog() RETARGET_SerialFlush() #define printLog(...) printf(__VA_ARGS__) #else #define initLog() #define flushLog() #define printLog(...) #endif /* Main application */ void appMain(gecko_configuration_t *pconfig); #endif |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/app/bluetooth/common/util/infrastructure.c.
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/***************************************************************************//** * @file * @brief infrastructure.c ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * The licensor of this software is Silicon Laboratories Inc. Your use of this * software is governed by the terms of Silicon Labs Master Software License * Agreement (MSLA) available at * www.silabs.com/about-us/legal/master-software-license-agreement. This * software is distributed to you in Source Code format and is governed by the * sections of the MSLA applicable to Source Code. * ******************************************************************************/ #include <stdint.h> #include <stdio.h> #include "infrastructure.h" #if defined(DEBUG_APP) void appAssertDebug(uint32_t val, const char* file, int line) { while (1) { // printf("F: %s, L: %u; E: %u\n", file, line, (unsigned int)(val)); } } #endif // DEBUG_APP #if defined(LOG_APP) void appLog(char* msg) { // printf("%s", msg); } #endif // LOG_APP |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/app/bluetooth/common/util/infrastructure.h.
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/***************************************************************************//** * @file * @brief Infrastructure for code development, macros for type conversion ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * The licensor of this software is Silicon Laboratories Inc. Your use of this * software is governed by the terms of Silicon Labs Master Software License * Agreement (MSLA) available at * www.silabs.com/about-us/legal/master-software-license-agreement. This * software is distributed to you in Source Code format and is governed by the * sections of the MSLA applicable to Source Code. * ******************************************************************************/ #ifndef INFRASTRUCTURE_H #define INFRASTRUCTURE_H /************************************************************************************************** * Macros for type conversion *************************************************************************************************/ #define FLT_TO_UINT32(m, e) (((uint32_t)(m) & 0x00FFFFFFU) | (uint32_t)((int32_t)(e) << 24)) #define UINT16_TO_BITSTREAM(p, n) { *(p)++ = (uint8_t)(n); *(p)++ = (uint8_t)((n) >> 8); } #define UINT8_TO_BITSTREAM(p, n) { *(p)++ = (uint8_t)(n); } #define UINT16_TO_BYTES(n) ((uint8_t) (n)), ((uint8_t)((n) >> 8)) #define UINT32_TO_BITSTREAM(p, n) { *(p)++ = (uint8_t)(n); *(p)++ = (uint8_t)((n) >> 8); \ *(p)++ = (uint8_t)((n) >> 16); *(p)++ = (uint8_t)((n) >> 24); } #define UINT16_TO_BYTE0(n) ((uint8_t) (n)) #define UINT16_TO_BYTE1(n) ((uint8_t) ((n) >> 8)) #define UINT32_TO_BYTE0(n) ((uint8_t) (n)) #define UINT32_TO_BYTE1(n) ((uint8_t) ((n) >> 8)) #define UINT32_TO_BYTE2(n) ((uint8_t) ((n) >> 16)) #define UINT32_TO_BYTE3(n) ((uint8_t) ((n) >> 24)) #define BYTES_TO_UINT16(byte0, byte1) ((((uint16_t)(byte1)) << 8) + ((uint16_t)(byte0))) #define BYTES_TO_UINT32(byte0, byte1, byte2, byte3) \ ((((uint32_t)(byte3)) << 24) \ + (((uint32_t)(byte2)) << 16) \ + (((uint32_t)(byte1)) << 8) \ + ((uint32_t)(byte0))) #define MIN(a, b) (((a) < (b)) ? (a) : (b)) #define MAX(a, b) (((a) > (b)) ? (a) : (b)) #define COUNTOF(x) ((sizeof (x)) / (sizeof ((x)[0]))) #if defined(DEBUG_APP) void appAssertDebug(uint32_t val, const char* file, int line); #define APP_ASSERT_DBG(expr, val) ((expr) ? ((void)0) : appAssertDebug((uint32_t)(val), __FILE__, __LINE__)) #else /* DEBUG_APP */ #define APP_ASSERT_DBG(expr, val) ((void)(expr)) #endif /* DEBUG_APP */ #if defined(LOG_APP) void appLog(char* msg); #define APP_LOG(msg) (appLog(msg)) #else /* LOG_APP */ #define APP_LOG(msg) ((void)(msg)) #endif /* LOG_APP */ #endif /* INFRASTRUCTURE_H */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/application_properties.c.
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/***************************************************************************//** * @file * @brief Template for Application Properties * @version 1.0.0 ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * The licensor of this software is Silicon Laboratories Inc. Your use of this * software is governed by the terms of Silicon Labs Master Software License * Agreement (MSLA) available at * www.silabs.com/about-us/legal/master-software-license-agreement. This * software is distributed to you in Source Code format and is governed by the * sections of the MSLA applicable to Source Code. * ******************************************************************************/ #include <application_properties.h> #if defined(__IAR_SYSTEMS_ICC__) /* IAR ICC */ #define KEEP_SYMBOL _Pragma("location=\".application_properties\"") __root #elif defined(__GNUC__) /* GNU GCC */ #define KEEP_SYMBOL __attribute__ ((section(".application_properties"))) #else #define KEEP_SYMBOL #endif /// Version number for this application (uint32_t) #define APP_PROPERTIES_VERSION 1 /// Unique ID (e.g. UUID or GUID) for the product this application is built for (uint8_t[16]) #define APP_PROPERTIES_ID { 0 } KEEP_SYMBOL const ApplicationProperties_t applicationProperties = { /// @brief Magic value indicating that this is an ApplicationProperties_t struct. /// Must equal @ref APPLICATION_PROPERTIES_MAGIC .magic = APPLICATION_PROPERTIES_MAGIC, /// Version number of this struct .structVersion = APPLICATION_PROPERTIES_VERSION, /// Type of signature this application is signed with .signatureType = APPLICATION_SIGNATURE_NONE, /// Location of the signature. Typically a pointer to the end of the application .signatureLocation = 0, /// Information about the application .app = { /// Bitfield representing type of application, e.g. @ref APPLICATION_TYPE_BLUETOOTH_APP .type = APPLICATION_TYPE_BLUETOOTH_APP, /// Version number for this application .version = APP_PROPERTIES_VERSION, /// Capabilities of this application .capabilities = 0, /// Unique ID (e.g. UUID or GUID) for the product this application is built for .productId = APP_PROPERTIES_ID, }, }; |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/ble-configuration.h.
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/***************************************************************************//** * @file * @brief ble-configuration.h ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * The licensor of this software is Silicon Laboratories Inc. Your use of this * software is governed by the terms of Silicon Labs Master Software License * Agreement (MSLA) available at * www.silabs.com/about-us/legal/master-software-license-agreement. This * software is distributed to you in Source Code format and is governed by the * sections of the MSLA applicable to Source Code. * ******************************************************************************/// This file is generated by Simplicity Studio. Please do not edit manually. // // // Enclosing macro to prevent multiple inclusion #ifndef __BLE_CONFIG__ #define __BLE_CONFIG__ // Top level macros #define SILABS_AF_DEVICE_NAME "soc-empty" // Generated plugin macros // Custom macros #define BRD4166A 1 #ifdef EMBER_AF_BOARD_TYPE #undef EMBER_AF_BOARD_TYPE #endif #define EMBER_AF_BOARD_TYPE BRD4166A #endif // __BLE_CONFIG__ |
Changes to Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/ble.micca.
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# This behavior exploits the delayed event with delay time of 0 behavior
# of the micca run-time (which was designed just for such circumstances).
domain ble {
prologue {
#include "micca_gecko.h"
extern void handle_bluetooth_event(struct gecko_cmd_packet *) ;
}
domainop void stack_update {seqId MRT_InstID} {
<% Sequencer idtoref seqId seq %>
<% instance seq signal Ble_event %>
} {
This function is to be used to handle bluetooth stack updates when
events are pending. It is intended to be invoked from the sync function
that is queue when the stack update callback is run by the stack.
}
................................................................................
struct gecko_cmd_packet *bluetooth_event = gecko_peek_event() ;
if (bluetooth_event != NULL) {
/*
* Toss handling bluetooth events off to an external
* function for now.
*/
<% my assign Event_count %>
Event_count++
<% my update Event_count Event_count %>
handle_bluetooth_event(bluetooth_event) ;
/*
* Return of 0 ==> needs immediate attention
* Return of UINT32_MAX ==> sleep indefinitely.
* Return of anything else is number of ms that can sleep.
*/
uint35_t timeout = gecko_can_sleep_ms() ;
if (timeout != UINT32_MAX) {
<% my delaysignal timeout Ble_event %>
}
}
}
}
}
}
population ble {
class Sequencer {
instance seq1 Event_count 0
}
}
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# This behavior exploits the delayed event with delay time of 0 behavior
# of the micca run-time (which was designed just for such circumstances).
domain ble {
prologue {
#include "micca_gecko.h"
#define BLUETOOTH_TICK_FREQ 32786
extern void handle_bluetooth_event(struct gecko_cmd_packet *) ;
}
domainop void stack_update {seqId MRT_InstId} {
<% Sequencer idtoref seqId seq %>
<% instance seq signal Ble_event %>
} {
This function is to be used to handle bluetooth stack updates when
events are pending. It is intended to be invoked from the sync function
that is queue when the stack update callback is run by the stack.
}
................................................................................
struct gecko_cmd_packet *bluetooth_event = gecko_peek_event() ;
if (bluetooth_event != NULL) {
/*
* Toss handling bluetooth events off to an external
* function for now.
*/
<% my assign Event_count %>
Event_count++ ;
<% my update Event_count Event_count %>
handle_bluetooth_event(bluetooth_event) ;
/*
* Return of 0 ==> needs immediate attention
* Return of UINT32_MAX ==> sleep indefinitely.
* Return of anything else is number of ticks to sleep.
* We use the "ticks" version of this call rather than
* the "ms" version because the test for UINT32_MAX
* works best. The constant for the "ms" version is only
* documented in a header file. So, we also have to
* scale to ms and know the frequency of the bluetooth
* ticks.
*/
uint32_t timeout = gecko_can_sleep_ticks() ;
if (timeout != UINT32_MAX) {
timeout = ((uint64_t)timeout * 1000ULL) /
(uint64_t)BLUETOOTH_TICK_FREQ ; // scale ticks to ms
<% my delaysignal timeout Ble_event %>
}
}
}
}
}
}
population ble {
class Sequencer {
instance seq1 Event_count 0
}
}
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Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/board_features.h.
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/***************************************************************************//** * @file * @brief board_features.h ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * The licensor of this software is Silicon Laboratories Inc. Your use of this * software is governed by the terms of Silicon Labs Master Software License * Agreement (MSLA) available at * www.silabs.com/about-us/legal/master-software-license-agreement. This * software is distributed to you in Source Code format and is governed by the * sections of the MSLA applicable to Source Code. * ******************************************************************************/ #ifndef BOARD_FEATURES_H #define BOARD_FEATURES_H #include "ble-configuration.h" /* Indicate if LCD is supported */ #if (EMBER_AF_BOARD_TYPE == BRD4100A)\ || (EMBER_AF_BOARD_TYPE == BRD4101B)\ || (EMBER_AF_BOARD_TYPE == BRD4103A)\ || (EMBER_AF_BOARD_TYPE == BRD4104A)\ || (EMBER_AF_BOARD_TYPE == BRD4105A)\ || (EMBER_AF_BOARD_TYPE == BRD4150A)\ || (EMBER_AF_BOARD_TYPE == BRD4150B)\ || (EMBER_AF_BOARD_TYPE == BRD4150C)\ || (EMBER_AF_BOARD_TYPE == BRD4151A)\ || (EMBER_AF_BOARD_TYPE == BRD4153A)\ || (EMBER_AF_BOARD_TYPE == BRD4158A)\ || (EMBER_AF_BOARD_TYPE == BRD4159A)\ || (EMBER_AF_BOARD_TYPE == BRD4161A)\ || (EMBER_AF_BOARD_TYPE == BRD4162A)\ || (EMBER_AF_BOARD_TYPE == BRD4163A)\ || (EMBER_AF_BOARD_TYPE == BRD4164A)\ || (EMBER_AF_BOARD_TYPE == BRD4165B)\ || (EMBER_AF_BOARD_TYPE == BRD4167A)\ || (EMBER_AF_BOARD_TYPE == BRD4168A)\ || (EMBER_AF_BOARD_TYPE == BRD4169A)\ || (EMBER_AF_BOARD_TYPE == BRD4169B)\ || (EMBER_AF_BOARD_TYPE == BRD4170A)\ || (EMBER_AF_BOARD_TYPE == BRD4171A)\ || (EMBER_AF_BOARD_TYPE == BRD4172A)\ || (EMBER_AF_BOARD_TYPE == BRD4172B)\ || (EMBER_AF_BOARD_TYPE == BRD4173A)\ || (EMBER_AF_BOARD_TYPE == BRD4174A)\ || (EMBER_AF_BOARD_TYPE == BRD4174B)\ || (EMBER_AF_BOARD_TYPE == BRD4175A)\ || (EMBER_AF_BOARD_TYPE == BRD4180A)\ || (EMBER_AF_BOARD_TYPE == BRD4181A)\ || (EMBER_AF_BOARD_TYPE == BRD4300A)\ || (EMBER_AF_BOARD_TYPE == BRD4300C)\ || (EMBER_AF_BOARD_TYPE == BRD4300D)\ || (EMBER_AF_BOARD_TYPE == BRD4302A)\ || (EMBER_AF_BOARD_TYPE == BRD4303A)\ || (EMBER_AF_BOARD_TYPE == BRD4304A)\ || (EMBER_AF_BOARD_TYPE == BRD4305A)\ || (EMBER_AF_BOARD_TYPE == BRD4305C)\ || (EMBER_AF_BOARD_TYPE == BRD4305D)\ || (EMBER_AF_BOARD_TYPE == BRD4305E)\ || (EMBER_AF_BOARD_TYPE == BRD4306A)\ || (EMBER_AF_BOARD_TYPE == BRD4306B)\ || (EMBER_AF_BOARD_TYPE == BRD4306C)\ || (EMBER_AF_BOARD_TYPE == BRD4306D) #define FEATURE_LCD_SUPPORT #endif /* Indicate if the same pins are used for LEDs and Buttons on the WSTK */ #if (EMBER_AF_BOARD_TYPE == BRD4101B)\ || (EMBER_AF_BOARD_TYPE == BRD4300A)\ || (EMBER_AF_BOARD_TYPE == BRD4300C)\ || (EMBER_AF_BOARD_TYPE == BRD4300D)\ || (EMBER_AF_BOARD_TYPE == BRD4301A)\ || (EMBER_AF_BOARD_TYPE == BRD4304A)\ || (EMBER_AF_BOARD_TYPE == BRD4306A)\ || (EMBER_AF_BOARD_TYPE == BRD4306B)\ || (EMBER_AF_BOARD_TYPE == BRD4306C)\ || (EMBER_AF_BOARD_TYPE == BRD4306D) #define FEATURE_LED_BUTTON_ON_SAME_PIN #endif #if (EMBER_AF_BOARD_TYPE == BRD4100A)\ || (EMBER_AF_BOARD_TYPE == BRD4101B)\ || (EMBER_AF_BOARD_TYPE == BRD4103A)\ || (EMBER_AF_BOARD_TYPE == BRD4104A)\ || (EMBER_AF_BOARD_TYPE == BRD4105A)\ || (EMBER_AF_BOARD_TYPE == BRD4150A)\ || (EMBER_AF_BOARD_TYPE == BRD4150B)\ || (EMBER_AF_BOARD_TYPE == BRD4150C)\ || (EMBER_AF_BOARD_TYPE == BRD4151A)\ || (EMBER_AF_BOARD_TYPE == BRD4153A)\ || (EMBER_AF_BOARD_TYPE == BRD4158A)\ || (EMBER_AF_BOARD_TYPE == BRD4159A)\ || (EMBER_AF_BOARD_TYPE == BRD4160A)\ || (EMBER_AF_BOARD_TYPE == BRD4161A)\ || (EMBER_AF_BOARD_TYPE == BRD4162A)\ || (EMBER_AF_BOARD_TYPE == BRD4163A)\ || (EMBER_AF_BOARD_TYPE == BRD4164A)\ || (EMBER_AF_BOARD_TYPE == BRD4166A)\ || (EMBER_AF_BOARD_TYPE == BRD4167A)\ || (EMBER_AF_BOARD_TYPE == BRD4168A)\ || (EMBER_AF_BOARD_TYPE == BRD4169A)\ || (EMBER_AF_BOARD_TYPE == BRD4169B)\ || (EMBER_AF_BOARD_TYPE == BRD4170A)\ || (EMBER_AF_BOARD_TYPE == BRD4171A)\ || (EMBER_AF_BOARD_TYPE == BRD4172A)\ || (EMBER_AF_BOARD_TYPE == BRD4172B)\ || (EMBER_AF_BOARD_TYPE == BRD4173A)\ || (EMBER_AF_BOARD_TYPE == BRD4174A)\ || (EMBER_AF_BOARD_TYPE == BRD4174B)\ || (EMBER_AF_BOARD_TYPE == BRD4175A)\ || (EMBER_AF_BOARD_TYPE == BRD4300C)\ || (EMBER_AF_BOARD_TYPE == BRD4300D)\ || (EMBER_AF_BOARD_TYPE == BRD4301A)\ || (EMBER_AF_BOARD_TYPE == BRD4302A)\ || (EMBER_AF_BOARD_TYPE == BRD4303A)\ || (EMBER_AF_BOARD_TYPE == BRD4304A)\ || (EMBER_AF_BOARD_TYPE == BRD4305A)\ || (EMBER_AF_BOARD_TYPE == BRD4305C)\ || (EMBER_AF_BOARD_TYPE == BRD4305D)\ || (EMBER_AF_BOARD_TYPE == BRD4305E)\ || (EMBER_AF_BOARD_TYPE == BRD4306A)\ || (EMBER_AF_BOARD_TYPE == BRD4306B)\ || (EMBER_AF_BOARD_TYPE == BRD4306C)\ || (EMBER_AF_BOARD_TYPE == BRD4306D) #define FEATURE_SPI_FLASH #endif #if (EMBER_AF_BOARD_TYPE == BRD4101B) #define FEATURE_IOEXPANDER #endif #if (EMBER_AF_BOARD_TYPE == BRD4304A) #define FEATURE_FEM #endif #if (EMBER_AF_BOARD_TYPE == BRD4150B)\ || (EMBER_AF_BOARD_TYPE == BRD4151A)\ || (EMBER_AF_BOARD_TYPE == BRD4158A)\ || (EMBER_AF_BOARD_TYPE == BRD4161A)\ || (EMBER_AF_BOARD_TYPE == BRD4164A)\ || (EMBER_AF_BOARD_TYPE == BRD4168A)\ || (EMBER_AF_BOARD_TYPE == BRD4169B)\ || (EMBER_AF_BOARD_TYPE == BRD4170A)\ || (EMBER_AF_BOARD_TYPE == BRD4172A)\ || (EMBER_AF_BOARD_TYPE == BRD4172B)\ || (EMBER_AF_BOARD_TYPE == BRD4174A)\ || (EMBER_AF_BOARD_TYPE == BRD4174B)\ || (EMBER_AF_BOARD_TYPE == BRD4304A)\ || (EMBER_AF_BOARD_TYPE == BRD4305A)\ || (EMBER_AF_BOARD_TYPE == BRD4305E)\ || (EMBER_AF_BOARD_TYPE == BRD4306B)\ || (EMBER_AF_BOARD_TYPE == BRD4306D) #define FEATURE_PA_INPUT_FROM_VBAT #endif #if (EMBER_AF_BOARD_TYPE == BRD4103A)\ || (EMBER_AF_BOARD_TYPE == BRD4161A)\ || (EMBER_AF_BOARD_TYPE == BRD4162A)\ || (EMBER_AF_BOARD_TYPE == BRD4163A)\ || (EMBER_AF_BOARD_TYPE == BRD4164A)\ || (EMBER_AF_BOARD_TYPE == BRD4170A) #define FEATURE_EXP_HEADER_USART3 #endif #if (EMBER_AF_BOARD_TYPE == BRD4100A)\ || (EMBER_AF_BOARD_TYPE == BRD4101B)\ || (EMBER_AF_BOARD_TYPE == BRD4103A)\ || (EMBER_AF_BOARD_TYPE == BRD4104A)\ || (EMBER_AF_BOARD_TYPE == BRD4105A)\ || (EMBER_AF_BOARD_TYPE == BRD4150A)\ || (EMBER_AF_BOARD_TYPE == BRD4150B)\ || (EMBER_AF_BOARD_TYPE == BRD4150C)\ || (EMBER_AF_BOARD_TYPE == BRD4151A)\ || (EMBER_AF_BOARD_TYPE == BRD4153A)\ || (EMBER_AF_BOARD_TYPE == BRD4158A)\ || (EMBER_AF_BOARD_TYPE == BRD4159A)\ || (EMBER_AF_BOARD_TYPE == BRD4160A)\ || (EMBER_AF_BOARD_TYPE == BRD4161A)\ || (EMBER_AF_BOARD_TYPE == BRD4162A)\ || (EMBER_AF_BOARD_TYPE == BRD4163A)\ || (EMBER_AF_BOARD_TYPE == BRD4164A)\ || (EMBER_AF_BOARD_TYPE == BRD4165B)\ || (EMBER_AF_BOARD_TYPE == BRD4166A)\ || (EMBER_AF_BOARD_TYPE == BRD4167A)\ || (EMBER_AF_BOARD_TYPE == BRD4168A)\ || (EMBER_AF_BOARD_TYPE == BRD4169A)\ || (EMBER_AF_BOARD_TYPE == BRD4169B)\ || (EMBER_AF_BOARD_TYPE == BRD4170A)\ || (EMBER_AF_BOARD_TYPE == BRD4171A)\ || (EMBER_AF_BOARD_TYPE == BRD4172A)\ || (EMBER_AF_BOARD_TYPE == BRD4172B)\ || (EMBER_AF_BOARD_TYPE == BRD4173A)\ || (EMBER_AF_BOARD_TYPE == BRD4174A)\ || (EMBER_AF_BOARD_TYPE == BRD4174B)\ || (EMBER_AF_BOARD_TYPE == BRD4175A)\ || (EMBER_AF_BOARD_TYPE == BRD4180A)\ || (EMBER_AF_BOARD_TYPE == BRD4181A)\ || (EMBER_AF_BOARD_TYPE == BRD4300A)\ || (EMBER_AF_BOARD_TYPE == BRD4300C)\ || (EMBER_AF_BOARD_TYPE == BRD4300D)\ || (EMBER_AF_BOARD_TYPE == BRD4301A)\ || (EMBER_AF_BOARD_TYPE == BRD4302A)\ || (EMBER_AF_BOARD_TYPE == BRD4303A)\ || (EMBER_AF_BOARD_TYPE == BRD4304A)\ || (EMBER_AF_BOARD_TYPE == BRD4305A)\ || (EMBER_AF_BOARD_TYPE == BRD4305C)\ || (EMBER_AF_BOARD_TYPE == BRD4305D)\ || (EMBER_AF_BOARD_TYPE == BRD4305E)\ || (EMBER_AF_BOARD_TYPE == BRD4306A)\ || (EMBER_AF_BOARD_TYPE == BRD4306B)\ || (EMBER_AF_BOARD_TYPE == BRD4306C)\ || (EMBER_AF_BOARD_TYPE == BRD4306D) #define FEATURE_PTI_SUPPORT #endif #if (EMBER_AF_BOARD_TYPE == BRD4100A)\ || (EMBER_AF_BOARD_TYPE == BRD4101B)\ || (EMBER_AF_BOARD_TYPE == BRD4103A)\ || (EMBER_AF_BOARD_TYPE == BRD4104A)\ || (EMBER_AF_BOARD_TYPE == BRD4105A)\ || (EMBER_AF_BOARD_TYPE == BRD4150A)\ || (EMBER_AF_BOARD_TYPE == BRD4150B)\ || (EMBER_AF_BOARD_TYPE == BRD4150C)\ || (EMBER_AF_BOARD_TYPE == BRD4151A)\ || (EMBER_AF_BOARD_TYPE == BRD4153A)\ || (EMBER_AF_BOARD_TYPE == BRD4158A)\ || (EMBER_AF_BOARD_TYPE == BRD4159A)\ || (EMBER_AF_BOARD_TYPE == BRD4161A)\ || (EMBER_AF_BOARD_TYPE == BRD4162A)\ || (EMBER_AF_BOARD_TYPE == BRD4163A)\ || (EMBER_AF_BOARD_TYPE == BRD4164A)\ || (EMBER_AF_BOARD_TYPE == BRD4165B)\ || (EMBER_AF_BOARD_TYPE == BRD4167A)\ || (EMBER_AF_BOARD_TYPE == BRD4168A)\ || (EMBER_AF_BOARD_TYPE == BRD4169A)\ || (EMBER_AF_BOARD_TYPE == BRD4169B)\ || (EMBER_AF_BOARD_TYPE == BRD4170A)\ || (EMBER_AF_BOARD_TYPE == BRD4172A)\ || (EMBER_AF_BOARD_TYPE == BRD4172B)\ || (EMBER_AF_BOARD_TYPE == BRD4173A)\ || (EMBER_AF_BOARD_TYPE == BRD4174A)\ || (EMBER_AF_BOARD_TYPE == BRD4174B)\ || (EMBER_AF_BOARD_TYPE == BRD4175A)\ || (EMBER_AF_BOARD_TYPE == BRD4180A)\ || (EMBER_AF_BOARD_TYPE == BRD4181A)\ || (EMBER_AF_BOARD_TYPE == BRD4300A)\ || (EMBER_AF_BOARD_TYPE == BRD4300C)\ || (EMBER_AF_BOARD_TYPE == BRD4300D)\ || (EMBER_AF_BOARD_TYPE == BRD4301A)\ || (EMBER_AF_BOARD_TYPE == BRD4302A)\ || (EMBER_AF_BOARD_TYPE == BRD4303A)\ || (EMBER_AF_BOARD_TYPE == BRD4304A)\ || (EMBER_AF_BOARD_TYPE == BRD4305A)\ || (EMBER_AF_BOARD_TYPE == BRD4305C)\ || (EMBER_AF_BOARD_TYPE == BRD4305D)\ || (EMBER_AF_BOARD_TYPE == BRD4305E)\ || (EMBER_AF_BOARD_TYPE == BRD4306A)\ || (EMBER_AF_BOARD_TYPE == BRD4306B)\ || (EMBER_AF_BOARD_TYPE == BRD4306C)\ || (EMBER_AF_BOARD_TYPE == BRD4306D) #define FEATURE_HW_FLOW_CONTROL #endif #if (EMBER_AF_BOARD_TYPE == BRD4100A)\ || (EMBER_AF_BOARD_TYPE == BRD4101B)\ || (EMBER_AF_BOARD_TYPE == BRD4103A)\ || (EMBER_AF_BOARD_TYPE == BRD4104A)\ || (EMBER_AF_BOARD_TYPE == BRD4105A)\ || (EMBER_AF_BOARD_TYPE == BRD4150A)\ || (EMBER_AF_BOARD_TYPE == BRD4150B)\ || (EMBER_AF_BOARD_TYPE == BRD4150C)\ || (EMBER_AF_BOARD_TYPE == BRD4151A)\ || (EMBER_AF_BOARD_TYPE == BRD4153A)\ || (EMBER_AF_BOARD_TYPE == BRD4158A)\ || (EMBER_AF_BOARD_TYPE == BRD4159A)\ || (EMBER_AF_BOARD_TYPE == BRD4160A)\ || (EMBER_AF_BOARD_TYPE == BRD4161A)\ || (EMBER_AF_BOARD_TYPE == BRD4162A)\ || (EMBER_AF_BOARD_TYPE == BRD4163A)\ || (EMBER_AF_BOARD_TYPE == BRD4164A)\ || (EMBER_AF_BOARD_TYPE == BRD4165B)\ || (EMBER_AF_BOARD_TYPE == BRD4166A)\ || (EMBER_AF_BOARD_TYPE == BRD4167A)\ || (EMBER_AF_BOARD_TYPE == BRD4168A)\ || (EMBER_AF_BOARD_TYPE == BRD4169A)\ || (EMBER_AF_BOARD_TYPE == BRD4169B)\ || (EMBER_AF_BOARD_TYPE == BRD4170A)\ || (EMBER_AF_BOARD_TYPE == BRD4171A)\ || (EMBER_AF_BOARD_TYPE == BRD4172A)\ || (EMBER_AF_BOARD_TYPE == BRD4172B)\ || (EMBER_AF_BOARD_TYPE == BRD4173A)\ || (EMBER_AF_BOARD_TYPE == BRD4174A)\ || (EMBER_AF_BOARD_TYPE == BRD4174B)\ || (EMBER_AF_BOARD_TYPE == BRD4175A)\ || (EMBER_AF_BOARD_TYPE == BRD4300A)\ || (EMBER_AF_BOARD_TYPE == BRD4300C)\ || (EMBER_AF_BOARD_TYPE == BRD4300D)\ || (EMBER_AF_BOARD_TYPE == BRD4301A)\ || (EMBER_AF_BOARD_TYPE == BRD4302A)\ || (EMBER_AF_BOARD_TYPE == BRD4303A)\ || (EMBER_AF_BOARD_TYPE == BRD4304A)\ || (EMBER_AF_BOARD_TYPE == BRD4305A)\ || (EMBER_AF_BOARD_TYPE == BRD4305C)\ || (EMBER_AF_BOARD_TYPE == BRD4305D)\ || (EMBER_AF_BOARD_TYPE == BRD4305E)\ || (EMBER_AF_BOARD_TYPE == BRD4306A)\ || (EMBER_AF_BOARD_TYPE == BRD4306B)\ || (EMBER_AF_BOARD_TYPE == BRD4306C)\ || (EMBER_AF_BOARD_TYPE == BRD4306D) #define FEATURE_I2C_SENSOR #endif #if (EMBER_AF_BOARD_TYPE == BRD4100A)\ || (EMBER_AF_BOARD_TYPE == BRD4101B)\ || (EMBER_AF_BOARD_TYPE == BRD4103A)\ || (EMBER_AF_BOARD_TYPE == BRD4104A)\ || (EMBER_AF_BOARD_TYPE == BRD4105A)\ || (EMBER_AF_BOARD_TYPE == BRD4150A)\ || (EMBER_AF_BOARD_TYPE == BRD4150B)\ || (EMBER_AF_BOARD_TYPE == BRD4150C)\ || (EMBER_AF_BOARD_TYPE == BRD4151A)\ || (EMBER_AF_BOARD_TYPE == BRD4153A)\ || (EMBER_AF_BOARD_TYPE == BRD4158A)\ || (EMBER_AF_BOARD_TYPE == BRD4159A)\ || (EMBER_AF_BOARD_TYPE == BRD4160A)\ || (EMBER_AF_BOARD_TYPE == BRD4161A)\ || (EMBER_AF_BOARD_TYPE == BRD4162A)\ || (EMBER_AF_BOARD_TYPE == BRD4163A)\ || (EMBER_AF_BOARD_TYPE == BRD4164A)\ || (EMBER_AF_BOARD_TYPE == BRD4165B)\ || (EMBER_AF_BOARD_TYPE == BRD4166A)\ || (EMBER_AF_BOARD_TYPE == BRD4167A)\ || (EMBER_AF_BOARD_TYPE == BRD4168A)\ || (EMBER_AF_BOARD_TYPE == BRD4169A)\ || (EMBER_AF_BOARD_TYPE == BRD4169B)\ || (EMBER_AF_BOARD_TYPE == BRD4170A)\ || (EMBER_AF_BOARD_TYPE == BRD4172A)\ || (EMBER_AF_BOARD_TYPE == BRD4172B)\ || (EMBER_AF_BOARD_TYPE == BRD4173A)\ || (EMBER_AF_BOARD_TYPE == BRD4174A)\ || (EMBER_AF_BOARD_TYPE == BRD4174B)\ || (EMBER_AF_BOARD_TYPE == BRD4175A)\ || (EMBER_AF_BOARD_TYPE == BRD4180A)\ || (EMBER_AF_BOARD_TYPE == BRD4181A)\ || (EMBER_AF_BOARD_TYPE == BRD4300A)\ || (EMBER_AF_BOARD_TYPE == BRD4300C)\ || (EMBER_AF_BOARD_TYPE == BRD4300D)\ || (EMBER_AF_BOARD_TYPE == BRD4301A)\ || (EMBER_AF_BOARD_TYPE == BRD4302A)\ || (EMBER_AF_BOARD_TYPE == BRD4303A)\ || (EMBER_AF_BOARD_TYPE == BRD4304A)\ || (EMBER_AF_BOARD_TYPE == BRD4305A)\ || (EMBER_AF_BOARD_TYPE == BRD4305C)\ || (EMBER_AF_BOARD_TYPE == BRD4305D)\ || (EMBER_AF_BOARD_TYPE == BRD4305E)\ || (EMBER_AF_BOARD_TYPE == BRD4306A)\ || (EMBER_AF_BOARD_TYPE == BRD4306B)\ || (EMBER_AF_BOARD_TYPE == BRD4306C)\ || (EMBER_AF_BOARD_TYPE == BRD4306D) #define FEATURE_LFXO #endif #if (EMBER_AF_BOARD_TYPE == BRD4100A)\ || (EMBER_AF_BOARD_TYPE == BRD4101B)\ || (EMBER_AF_BOARD_TYPE == BRD4103A)\ || (EMBER_AF_BOARD_TYPE == BRD4104A)\ || (EMBER_AF_BOARD_TYPE == BRD4105A)\ || (EMBER_AF_BOARD_TYPE == BRD4150A)\ || (EMBER_AF_BOARD_TYPE == BRD4150B)\ || (EMBER_AF_BOARD_TYPE == BRD4150C)\ || (EMBER_AF_BOARD_TYPE == BRD4151A)\ || (EMBER_AF_BOARD_TYPE == BRD4153A)\ || (EMBER_AF_BOARD_TYPE == BRD4158A)\ || (EMBER_AF_BOARD_TYPE == BRD4159A)\ || (EMBER_AF_BOARD_TYPE == BRD4160A)\ || (EMBER_AF_BOARD_TYPE == BRD4161A)\ || (EMBER_AF_BOARD_TYPE == BRD4162A)\ || (EMBER_AF_BOARD_TYPE == BRD4163A)\ || (EMBER_AF_BOARD_TYPE == BRD4164A)\ || (EMBER_AF_BOARD_TYPE == BRD4165B)\ || (EMBER_AF_BOARD_TYPE == BRD4166A)\ || (EMBER_AF_BOARD_TYPE == BRD4167A)\ || (EMBER_AF_BOARD_TYPE == BRD4168A)\ || (EMBER_AF_BOARD_TYPE == BRD4169A)\ || (EMBER_AF_BOARD_TYPE == BRD4169B)\ || (EMBER_AF_BOARD_TYPE == BRD4170A)\ || (EMBER_AF_BOARD_TYPE == BRD4171A)\ || (EMBER_AF_BOARD_TYPE == BRD4172A)\ || (EMBER_AF_BOARD_TYPE == BRD4172B)\ || (EMBER_AF_BOARD_TYPE == BRD4173A)\ || (EMBER_AF_BOARD_TYPE == BRD4174A)\ || (EMBER_AF_BOARD_TYPE == BRD4174B)\ || (EMBER_AF_BOARD_TYPE == BRD4175A)\ || (EMBER_AF_BOARD_TYPE == BRD4180A)\ || (EMBER_AF_BOARD_TYPE == BRD4181A)\ || (EMBER_AF_BOARD_TYPE == BRD4300A)\ || (EMBER_AF_BOARD_TYPE == BRD4300C)\ || (EMBER_AF_BOARD_TYPE == BRD4300D)\ || (EMBER_AF_BOARD_TYPE == BRD4301A)\ || (EMBER_AF_BOARD_TYPE == BRD4302A)\ || (EMBER_AF_BOARD_TYPE == BRD4303A)\ || (EMBER_AF_BOARD_TYPE == BRD4304A)\ || (EMBER_AF_BOARD_TYPE == BRD4305A)\ || (EMBER_AF_BOARD_TYPE == BRD4305C)\ || (EMBER_AF_BOARD_TYPE == BRD4305D)\ || (EMBER_AF_BOARD_TYPE == BRD4305E)\ || (EMBER_AF_BOARD_TYPE == BRD4306A)\ || (EMBER_AF_BOARD_TYPE == BRD4306B)\ || (EMBER_AF_BOARD_TYPE == BRD4306C)\ || (EMBER_AF_BOARD_TYPE == BRD4306D)\ || (EMBER_AF_BOARD_TYPE == RD_0057_0101) #define FEATURE_BOARD_DETECTED #endif #if (EMBER_AF_BOARD_TYPE == CUSTOM_BOARD) // Uncomment the corresponding line in case of using Silicon Labs board feature in your design. // For using the selected feature you may need additional drivers. Check an appropriate SDK example for reference. // #define FEATURE_LCD_SUPPORT // #define FEATURE_LED_BUTTON_ON_SAME_PIN // #define FEATURE_SPI_FLASH // #define FEATURE_IOEXPANDER // #define FEATURE_FEM // #define FEATURE_PA_HIGH_POWER // #define FEATURE_EXP_HEADER_USART3 // #define FEATURE_PTI_SUPPORT // #define FEATURE_HW_FLOW_CONTROL // #define FEATURE_BOARD_DETECTED #endif #endif /* BOARD_FEATURES_H */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/dmadrv_config.h.
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/***************************************************************************//** * @file * @brief DMADRV configuration file. ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * The licensor of this software is Silicon Laboratories Inc. Your use of this * software is governed by the terms of Silicon Labs Master Software License * Agreement (MSLA) available at * www.silabs.com/about-us/legal/master-software-license-agreement. This * software is distributed to you in Source Code format and is governed by the * sections of the MSLA applicable to Source Code. * ******************************************************************************/ #ifndef __SILICON_LABS_DMADRV_CONFIG_H__ #define __SILICON_LABS_DMADRV_CONFIG_H__ #include "em_device.h" /***************************************************************************//** * @addtogroup emdrv * @{ ******************************************************************************/ /***************************************************************************//** * @addtogroup DMADRV * @{ ******************************************************************************/ /// DMADRV DMA interrupt priority configuration option. /// Set DMA interrupt priority. Range is 0..7, 0 is highest priority. #ifndef EMDRV_DMADRV_DMA_IRQ_PRIORITY #if (__NVIC_PRIO_BITS == 2) #define EMDRV_DMADRV_DMA_IRQ_PRIORITY 3 #else #define EMDRV_DMADRV_DMA_IRQ_PRIORITY 4 #endif #endif /// DMADRV DMA channel priority configuration option. /// Set DMA channel priority. Range 0..EMDRV_DMADRV_DMA_CH_COUNT. /// On LDMA, this will configure channel 0 to CH_PRIORITY - 1 as fixed priority, /// and CH_PRIORITY to CH_COUNT as round-robin. /// On DMA, this will have no impact, since high priority is unuseable with /// peripherals. #ifndef EMDRV_DMADRV_DMA_CH_PRIORITY #define EMDRV_DMADRV_DMA_CH_PRIORITY 0 #endif /// DMADRV channel count configuration option. /// Number of DMA channels to support. A lower DMA channel count will reduce /// ram memory footprint. #ifndef EMDRV_DMADRV_DMA_CH_COUNT #define EMDRV_DMADRV_DMA_CH_COUNT DMA_CHAN_COUNT #endif /// DMADRV native API configuration option. /// Use the native emlib api of the DMA controller, but still use DMADRV /// housekeeping functions as AllocateChannel/FreeChannel etc. #if defined(DOXY_DOC_ONLY) #define EMDRV_DMADRV_USE_NATIVE_API #else //#define EMDRV_DMADRV_USE_NATIVE_API #endif /** @} (end addtogroup DMADRV) */ /** @} (end addtogroup emdrv) */ #endif /* __SILICON_LABS_DMADRV_CONFIG_H__ */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/efr32mg12p332f1024gl125.ld.
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/* Linker script for Silicon Labs EFR32MG1P devices */ /* */ /* This file is subject to the license terms as defined in ARM's */ /* CMSIS END USER LICENSE AGREEMENT.pdf, governing the use of */ /* Example Code. */ /* */ /* Silicon Laboratories, Inc. 2015 */ /* */ /* Version 4.1.1 */ /* */ MEMORY { FLASH_BOOTLOADER (rx) : ORIGIN = 0x0FE10000, LENGTH = 0x4000 FLASH (rx) : ORIGIN = 0x0000, LENGTH = 0x00100000-0x0000 RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00040000 } /* Linker script to place sections and symbol values. Should be used together * with other linker script that defines memory regions FLASH and RAM. * It references following symbols, which must be defined in code: * Reset_Handler : Entry of reset handler * * It defines following symbols, which code can use without definition: * __exidx_start * __exidx_end * __copy_table_start__ * __copy_table_end__ * __zero_table_start__ * __zero_table_end__ * __etext * __data_start__ * __preinit_array_start * __preinit_array_end * __init_array_start * __init_array_end * __fini_array_start * __fini_array_end * __data_end__ * __bss_start__ * __bss_end__ * __end__ * end * __HeapLimit * __StackLimit * __StackTop * __stack * __Vectors_End * __Vectors_Size */ ENTRY(Reset_Handler) SECTIONS { .text_bootloader : { KEEP(*(.binbootloader*)) /* Align to flash page boundary*/ . = ALIGN(0x4000); }> FLASH_BOOTLOADER .text_apploader : { KEEP(*(.binapploader*)) }> FLASH .text_signature : { . = ALIGN(2048); }> FLASH __text_start__ = .; .text_application : { KEEP(*(.vectors)) __Vectors_End = .; __Vectors_Size = __Vectors_End - __Vectors; __end__ = .; KEEP(*(.application_properties)) KEEP(*(.gecko_configuration)) KEEP(*(.xo_configuration)) KEEP(*(.gatt_header)) KEEP(*(.gatt_data)) *(.text*) KEEP(*(.init)) KEEP(*(.fini)) /* .ctors */ *crtbegin.o(.ctors) *crtbegin?.o(.ctors) *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) *(SORT(.ctors.*)) *(.ctors) /* .dtors */ *crtbegin.o(.dtors) *crtbegin?.o(.dtors) *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) *(SORT(.dtors.*)) *(.dtors) *(.rodata*) KEEP(*(.eh_frame*)) . = ALIGN(4); } > FLASH .text_application_ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } > FLASH __exidx_start = .; .text_application_ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) } > FLASH __exidx_end = .; __etext = .; /* .stack_dummy section doesn't contains any symbols. It is only * used for linker to calculate size of stack sections, and assign * values to stack symbols later */ .stack_dummy (COPY): { KEEP(*(.stack*)) } > RAM /* Set stack top to end of RAM, and stack limit move down by * size of stack_dummy section */ __StackTop = ORIGIN(RAM) + SIZEOF(.stack_dummy); __StackLimit = ORIGIN(RAM); PROVIDE(__stack = __StackTop); .text_application_data : AT (__etext) { __data_start__ = .; *(vtable) *(.data*) . = ALIGN (4); *(.ram) . = ALIGN(4); /* preinit data */ PROVIDE_HIDDEN (__preinit_array_start = .); KEEP(*(.preinit_array)) PROVIDE_HIDDEN (__preinit_array_end = .); . = ALIGN(4); /* init data */ PROVIDE_HIDDEN (__init_array_start = .); KEEP(*(SORT(.init_array.*))) KEEP(*(.init_array)) PROVIDE_HIDDEN (__init_array_end = .); . = ALIGN(4); /* finit data */ PROVIDE_HIDDEN (__fini_array_start = .); KEEP(*(SORT(.fini_array.*))) KEEP(*(.fini_array)) PROVIDE_HIDDEN (__fini_array_end = .); KEEP(*(.jcr*)) . = ALIGN(4); /* All data end */ __data_end__ = .; } > RAM .bss : { . = ALIGN(4); __bss_start__ = .; *(.bss*) *(COMMON) . = ALIGN(4); __bss_end__ = .; } > RAM .heap (COPY): { __HeapBase = .; __end__ = .; end = __end__; _end = __end__; KEEP(*(.heap*)) __HeapLimit = .; } > RAM /* .nvm_dummy section doesn't contains any symbols. It is only * used for linker to calculate size of nvm section, and assign * values to nvm symbols later */ .nvm_dummy (DSECT): { KEEP(*(.simee)); } > FLASH /* Set NVM to end of FLASH*/ __nvm3Base = 0x00100000- SIZEOF(.nvm_dummy); ASSERT((__etext + SIZEOF(.text_application_data)) <= __nvm3Base, "FLASH memory overlapped with NVM section.") } |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/hal-config-app-common.h.
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/***************************************************************************//** * @file * @brief hal-config-app-common.h ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * The licensor of this software is Silicon Laboratories Inc. Your use of this * software is governed by the terms of Silicon Labs Master Software License * Agreement (MSLA) available at * www.silabs.com/about-us/legal/master-software-license-agreement. This * software is distributed to you in Source Code format and is governed by the * sections of the MSLA applicable to Source Code. * ******************************************************************************/ #ifndef HAL_CONFIG_APP_COMMON_H #define HAL_CONFIG_APP_COMMON_H #include "em_device.h" #include "hal-config-types.h" #if defined(FEATURE_IOEXPANDER) #include "hal-config-ioexp.h" #endif #if defined(FEATURE_FEM) #include "hal-config-fem.h" #endif #define HAL_EXTFLASH_FREQUENCY (1000000) #define HAL_PA_ENABLE (1) #define HAL_PTI_ENABLE (1) #define HAL_PTI_MODE (HAL_PTI_MODE_UART) #define HAL_PTI_BAUD_RATE (1600000) #ifdef BSP_CLK_LFXO_CTUNE #undef BSP_CLK_LFXO_CTUNE #endif #define BSP_CLK_LFXO_CTUNE (32) #if (HAL_PA_ENABLE) #define HAL_PA_RAMP (10) #define HAL_PA_2P4_LOWPOWER (0) #define HAL_PA_POWER (252) #define HAL_PA_CURVE_HEADER "pa_curves_efr32.h" #endif #ifdef FEATURE_PA_HIGH_POWER #define HAL_PA_VOLTAGE (3300) #else // FEATURE_PA_HIGH_POWER #define HAL_PA_VOLTAGE (1800) #endif // FEATURE_PA_HIGH_POWER #endif /* HAL_CONFIG_APP_COMMON_H */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/hal-config.h.
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/***************************************************************************//** * @file * @brief hal-config.h ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * The licensor of this software is Silicon Laboratories Inc. Your use of this * software is governed by the terms of Silicon Labs Master Software License * Agreement (MSLA) available at * www.silabs.com/about-us/legal/master-software-license-agreement. This * software is distributed to you in Source Code format and is governed by the * sections of the MSLA applicable to Source Code. * ******************************************************************************/ #ifndef HAL_CONFIG_H #define HAL_CONFIG_H #include "board_features.h" #include "hal-config-board.h" #include "hal-config-app-common.h" #ifndef HAL_VCOM_ENABLE #define HAL_VCOM_ENABLE (1) #endif #define HAL_I2CSENSOR_ENABLE (0) #define HAL_SPIDISPLAY_ENABLE (0) #endif |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/hardware/kit/EFR32MG12_BRD4166A/config/hal-config-board.h.
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#ifndef HAL_CONFIG_BOARD_H #define HAL_CONFIG_BOARD_H #include "em_device.h" #include "hal-config-types.h" // This file is auto-generated by Hardware Configurator in Simplicity Studio. // Any content between $[ and ]$ will be replaced whenever the file is regenerated. // Content outside these regions will be preserved. // $[ACMP0] // [ACMP0]$ // $[ACMP1] // [ACMP1]$ // $[ADC0] // [ADC0]$ // $[ANTDIV] // [ANTDIV]$ // $[BATTERYMON] // [BATTERYMON]$ // $[BTL_BUTTON] #define BSP_BTL_BUTTON_PIN (14U) #define BSP_BTL_BUTTON_PORT (gpioPortD) // [BTL_BUTTON]$ // $[BULBPWM] // [BULBPWM]$ // $[BULBPWM_COLOR] // [BULBPWM_COLOR]$ // $[BUTTON] #define BSP_BUTTON_PRESENT (1) #define BSP_BUTTON0_PIN (14U) #define BSP_BUTTON0_PORT (gpioPortD) #define BSP_BUTTON1_PIN (15U) #define BSP_BUTTON1_PORT (gpioPortD) #define BSP_BUTTON_COUNT (2U) #define BSP_BUTTON_INIT { { BSP_BUTTON0_PORT, BSP_BUTTON0_PIN }, { BSP_BUTTON1_PORT, BSP_BUTTON1_PIN } } #define BSP_BUTTON_GPIO_DOUT (HAL_GPIO_DOUT_LOW) #define BSP_BUTTON_GPIO_MODE (HAL_GPIO_MODE_INPUT) // [BUTTON]$ // $[CMU] #define BSP_CLK_LFXO_PRESENT (1) #define BSP_CLK_HFXO_PRESENT (1) #define BSP_CLK_LFXO_INIT CMU_LFXOINIT_DEFAULT #define BSP_CLK_LFXO_CTUNE (32U) #define BSP_CLK_LFXO_FREQ (32768U) #define BSP_CLK_HFXO_FREQ (38400000UL) #define BSP_CLK_HFXO_CTUNE (332) #define BSP_CLK_HFXO_INIT CMU_HFXOINIT_DEFAULT // [CMU]$ // $[COEX] // [COEX]$ // $[CS5463] // [CS5463]$ // $[CSEN] // [CSEN]$ // $[DCDC] #define BSP_DCDC_PRESENT (1) #define BSP_DCDC_INIT EMU_DCDCINIT_DEFAULT // [DCDC]$ // $[EMU] // [EMU]$ // $[EXTFLASH] #define BSP_EXTFLASH_CS_PIN (1U) #define BSP_EXTFLASH_CS_PORT (gpioPortK) #define BSP_EXTFLASH_USART (HAL_SPI_PORT_USART2) #define BSP_EXTFLASH_INTERNAL (0) #define BSP_EXTFLASH_CLK_PIN (7U) #define BSP_EXTFLASH_CLK_PORT (gpioPortF) #define BSP_EXTFLASH_CLK_LOC (18U) #define BSP_EXTFLASH_MISO_PIN (2U) #define BSP_EXTFLASH_MISO_PORT (gpioPortK) #define BSP_EXTFLASH_MISO_LOC (30U) #define BSP_EXTFLASH_MOSI_PIN (0U) #define BSP_EXTFLASH_MOSI_PORT (gpioPortK) #define BSP_EXTFLASH_MOSI_LOC (29U) // [EXTFLASH]$ // $[EZRADIOPRO] // [EZRADIOPRO]$ // $[FEM] // [FEM]$ // $[GPIO] #define PORTIO_GPIO_SWV_PIN (2U) #define PORTIO_GPIO_SWV_PORT (gpioPortF) #define PORTIO_GPIO_SWV_LOC (0U) #define BSP_TRACE_SWO_PIN (2U) #define BSP_TRACE_SWO_PORT (gpioPortF) #define BSP_TRACE_SWO_LOC (0U) // [GPIO]$ // $[I2C0] #define PORTIO_I2C0_SCL_PIN (11U) #define PORTIO_I2C0_SCL_PORT (gpioPortC) #define PORTIO_I2C0_SCL_LOC (15U) #define PORTIO_I2C0_SDA_PIN (10U) #define PORTIO_I2C0_SDA_PORT (gpioPortC) #define PORTIO_I2C0_SDA_LOC (15U) #define BSP_I2C0_SDA_PIN (10U) #define BSP_I2C0_SDA_PORT (gpioPortC) #define BSP_I2C0_SDA_LOC (15U) #define BSP_I2C0_SCL_PIN (11U) #define BSP_I2C0_SCL_PORT (gpioPortC) #define BSP_I2C0_SCL_LOC (15U) // [I2C0]$ // $[I2C1] #define PORTIO_I2C1_SCL_PIN (5U) #define PORTIO_I2C1_SCL_PORT (gpioPortC) #define PORTIO_I2C1_SCL_LOC (17U) #define PORTIO_I2C1_SDA_PIN (4U) #define PORTIO_I2C1_SDA_PORT (gpioPortC) #define PORTIO_I2C1_SDA_LOC (17U) #define BSP_I2C1_SDA_PIN (4U) #define BSP_I2C1_SDA_PORT (gpioPortC) #define BSP_I2C1_SDA_LOC (17U) #define BSP_I2C1_SCL_PIN (5U) #define BSP_I2C1_SCL_PORT (gpioPortC) #define BSP_I2C1_SCL_LOC (17U) // [I2C1]$ // $[I2CSENSOR] #define BSP_I2CSENSOR_PERIPHERAL (HAL_I2C_PORT_I2C0) #define BSP_I2CSENSOR_SDA_PIN (10U) #define BSP_I2CSENSOR_SDA_PORT (gpioPortC) #define BSP_I2CSENSOR_SDA_LOC (15U) #define BSP_I2CSENSOR_SCL_PIN (11U) #define BSP_I2CSENSOR_SCL_PORT (gpioPortC) #define BSP_I2CSENSOR_SCL_LOC (15U) // [I2CSENSOR]$ // $[IDAC0] // [IDAC0]$ // $[IOEXP] // [IOEXP]$ // $[LED] #define BSP_LED_PRESENT (1) #define BSP_LED0_PIN (8U) #define BSP_LED0_PORT (gpioPortD) #define BSP_LED1_PIN (9U) #define BSP_LED1_PORT (gpioPortD) #define BSP_LED_POLARITY (1) #define BSP_LED_COUNT (2U) #define BSP_LED_INIT { { BSP_LED0_PORT, BSP_LED0_PIN }, { BSP_LED1_PORT, BSP_LED1_PIN } } // [LED]$ // $[LESENSE] // [LESENSE]$ // $[LETIMER0] // [LETIMER0]$ // $[LEUART0] // [LEUART0]$ // $[LFXO] // [LFXO]$ // $[MODEM] // [MODEM]$ // $[PA] #define BSP_PA_VOLTAGE (1800U) // [PA]$ // $[PCNT0] // [PCNT0]$ // $[PCNT1] // [PCNT1]$ // $[PCNT2] // [PCNT2]$ // $[PORTIO] // [PORTIO]$ // $[PRS] // [PRS]$ // $[PTI] #define PORTIO_PTI_DCLK_PIN (11U) #define PORTIO_PTI_DCLK_PORT (gpioPortB) #define PORTIO_PTI_DCLK_LOC (6U) #define PORTIO_PTI_DFRAME_PIN (13U) #define PORTIO_PTI_DFRAME_PORT (gpioPortB) #define PORTIO_PTI_DFRAME_LOC (6U) #define PORTIO_PTI_DOUT_PIN (12U) #define PORTIO_PTI_DOUT_PORT (gpioPortB) #define PORTIO_PTI_DOUT_LOC (6U) #define BSP_PTI_DFRAME_PIN (13U) #define BSP_PTI_DFRAME_PORT (gpioPortB) #define BSP_PTI_DFRAME_LOC (6U) #define BSP_PTI_DOUT_PIN (12U) #define BSP_PTI_DOUT_PORT (gpioPortB) #define BSP_PTI_DOUT_LOC (6U) // [PTI]$ // $[PYD1698] // [PYD1698]$ // $[SERIAL] #define BSP_SERIAL_APP_PORT (HAL_SERIAL_PORT_USART0) #define BSP_SERIAL_APP_CTS_PIN (2U) #define BSP_SERIAL_APP_CTS_PORT (gpioPortA) #define BSP_SERIAL_APP_CTS_LOC (30U) #define BSP_SERIAL_APP_RX_PIN (1U) #define BSP_SERIAL_APP_RX_PORT (gpioPortA) #define BSP_SERIAL_APP_RX_LOC (0U) #define BSP_SERIAL_APP_TX_PIN (0U) #define BSP_SERIAL_APP_TX_PORT (gpioPortA) #define BSP_SERIAL_APP_TX_LOC (0U) #define BSP_SERIAL_APP_RTS_PIN (3U) #define BSP_SERIAL_APP_RTS_PORT (gpioPortA) #define BSP_SERIAL_APP_RTS_LOC (30U) // [SERIAL]$ // $[SPIDISPLAY] // [SPIDISPLAY]$ // $[SPINCP] #define BSP_SPINCP_NWAKE_PIN (7U) #define BSP_SPINCP_NWAKE_PORT (gpioPortA) #define BSP_SPINCP_NHOSTINT_PIN (6U) #define BSP_SPINCP_NHOSTINT_PORT (gpioPortA) #define BSP_SPINCP_USART_PORT (HAL_SPI_PORT_USART2) #define BSP_SPINCP_CS_PIN (5U) #define BSP_SPINCP_CS_PORT (gpioPortA) #define BSP_SPINCP_CS_LOC (29U) #define BSP_SPINCP_CLK_PIN (7U) #define BSP_SPINCP_CLK_PORT (gpioPortF) #define BSP_SPINCP_CLK_LOC (18U) #define BSP_SPINCP_MISO_PIN (2U) #define BSP_SPINCP_MISO_PORT (gpioPortK) #define BSP_SPINCP_MISO_LOC (30U) #define BSP_SPINCP_MOSI_PIN (0U) #define BSP_SPINCP_MOSI_PORT (gpioPortK) #define BSP_SPINCP_MOSI_LOC (29U) // [SPINCP]$ // $[TIMER0] #define PORTIO_TIMER0_CC0_PIN (11U) #define PORTIO_TIMER0_CC0_PORT (gpioPortD) #define PORTIO_TIMER0_CC0_LOC (19U) #define PORTIO_TIMER0_CC1_PIN (12U) #define PORTIO_TIMER0_CC1_PORT (gpioPortD) #define PORTIO_TIMER0_CC1_LOC (19U) #define PORTIO_TIMER0_CC2_PIN (13U) #define PORTIO_TIMER0_CC2_PORT (gpioPortD) #define PORTIO_TIMER0_CC2_LOC (19U) #define BSP_TIMER0_CC1_PIN (12U) #define BSP_TIMER0_CC1_PORT (gpioPortD) #define BSP_TIMER0_CC1_LOC (19U) #define BSP_TIMER0_CC0_PIN (11U) #define BSP_TIMER0_CC0_PORT (gpioPortD) #define BSP_TIMER0_CC0_LOC (19U) #define BSP_TIMER0_CC2_PIN (13U) #define BSP_TIMER0_CC2_PORT (gpioPortD) #define BSP_TIMER0_CC2_LOC (19U) // [TIMER0]$ // $[TIMER1] // [TIMER1]$ // $[UARTNCP] #define BSP_UARTNCP_USART_PORT (HAL_SERIAL_PORT_USART0) #define BSP_UARTNCP_CTS_PIN (2U) #define BSP_UARTNCP_CTS_PORT (gpioPortA) #define BSP_UARTNCP_CTS_LOC (30U) #define BSP_UARTNCP_RX_PIN (1U) #define BSP_UARTNCP_RX_PORT (gpioPortA) #define BSP_UARTNCP_RX_LOC (0U) #define BSP_UARTNCP_TX_PIN (0U) #define BSP_UARTNCP_TX_PORT (gpioPortA) #define BSP_UARTNCP_TX_LOC (0U) #define BSP_UARTNCP_RTS_PIN (3U) #define BSP_UARTNCP_RTS_PORT (gpioPortA) #define BSP_UARTNCP_RTS_LOC (30U) // [UARTNCP]$ // $[USART0] #define PORTIO_USART0_CTS_PIN (2U) #define PORTIO_USART0_CTS_PORT (gpioPortA) #define PORTIO_USART0_CTS_LOC (30U) #define PORTIO_USART0_RTS_PIN (3U) #define PORTIO_USART0_RTS_PORT (gpioPortA) #define PORTIO_USART0_RTS_LOC (30U) #define PORTIO_USART0_RX_PIN (1U) #define PORTIO_USART0_RX_PORT (gpioPortA) #define PORTIO_USART0_RX_LOC (0U) #define PORTIO_USART0_TX_PIN (0U) #define PORTIO_USART0_TX_PORT (gpioPortA) #define PORTIO_USART0_TX_LOC (0U) #define BSP_USART0_CTS_PIN (2U) #define BSP_USART0_CTS_PORT (gpioPortA) #define BSP_USART0_CTS_LOC (30U) #define BSP_USART0_RX_PIN (1U) #define BSP_USART0_RX_PORT (gpioPortA) #define BSP_USART0_RX_LOC (0U) #define BSP_USART0_TX_PIN (0U) #define BSP_USART0_TX_PORT (gpioPortA) #define BSP_USART0_TX_LOC (0U) #define BSP_USART0_RTS_PIN (3U) #define BSP_USART0_RTS_PORT (gpioPortA) #define BSP_USART0_RTS_LOC (30U) // [USART0]$ // $[USART1] #define PORTIO_USART1_CLK_PIN (8U) #define PORTIO_USART1_CLK_PORT (gpioPortC) #define PORTIO_USART1_CLK_LOC (11U) #define PORTIO_USART1_CS_PIN (9U) #define PORTIO_USART1_CS_PORT (gpioPortC) #define PORTIO_USART1_CS_LOC (11U) #define PORTIO_USART1_RX_PIN (7U) #define PORTIO_USART1_RX_PORT (gpioPortC) #define PORTIO_USART1_RX_LOC (11U) #define PORTIO_USART1_TX_PIN (6U) #define PORTIO_USART1_TX_PORT (gpioPortC) #define PORTIO_USART1_TX_LOC (11U) #define BSP_USART1_CS_PIN (9U) #define BSP_USART1_CS_PORT (gpioPortC) #define BSP_USART1_CS_LOC (11U) #define BSP_USART1_CLK_PIN (8U) #define BSP_USART1_CLK_PORT (gpioPortC) #define BSP_USART1_CLK_LOC (11U) #define BSP_USART1_MISO_PIN (7U) #define BSP_USART1_MISO_PORT (gpioPortC) #define BSP_USART1_MISO_LOC (11U) #define BSP_USART1_MOSI_PIN (6U) #define BSP_USART1_MOSI_PORT (gpioPortC) #define BSP_USART1_MOSI_LOC (11U) // [USART1]$ // $[USART2] #define PORTIO_USART2_CLK_PIN (7U) #define PORTIO_USART2_CLK_PORT (gpioPortF) #define PORTIO_USART2_CLK_LOC (18U) #define PORTIO_USART2_CS_PIN (5U) #define PORTIO_USART2_CS_PORT (gpioPortA) #define PORTIO_USART2_CS_LOC (29U) #define PORTIO_USART2_RX_PIN (2U) #define PORTIO_USART2_RX_PORT (gpioPortK) #define PORTIO_USART2_RX_LOC (30U) #define PORTIO_USART2_TX_PIN (0U) #define PORTIO_USART2_TX_PORT (gpioPortK) #define PORTIO_USART2_TX_LOC (29U) #define BSP_USART2_CS_PIN (5U) #define BSP_USART2_CS_PORT (gpioPortA) #define BSP_USART2_CS_LOC (29U) #define BSP_USART2_CLK_PIN (7U) #define BSP_USART2_CLK_PORT (gpioPortF) #define BSP_USART2_CLK_LOC (18U) #define BSP_USART2_MISO_PIN (2U) #define BSP_USART2_MISO_PORT (gpioPortK) #define BSP_USART2_MISO_LOC (30U) #define BSP_USART2_MOSI_PIN (0U) #define BSP_USART2_MOSI_PORT (gpioPortK) #define BSP_USART2_MOSI_LOC (29U) // [USART2]$ // $[USART3] #define PORTIO_USART3_CLK_PIN (2U) #define PORTIO_USART3_CLK_PORT (gpioPortC) #define PORTIO_USART3_CLK_LOC (18U) #define PORTIO_USART3_CS_PIN (3U) #define PORTIO_USART3_CS_PORT (gpioPortC) #define PORTIO_USART3_CS_LOC (18U) #define PORTIO_USART3_RX_PIN (1U) #define PORTIO_USART3_RX_PORT (gpioPortC) #define PORTIO_USART3_RX_LOC (18U) #define PORTIO_USART3_TX_PIN (0U) #define PORTIO_USART3_TX_PORT (gpioPortC) #define PORTIO_USART3_TX_LOC (18U) #define BSP_USART3_CS_PIN (3U) #define BSP_USART3_CS_PORT (gpioPortC) #define BSP_USART3_CS_LOC (18U) #define BSP_USART3_CLK_PIN (2U) #define BSP_USART3_CLK_PORT (gpioPortC) #define BSP_USART3_CLK_LOC (18U) #define BSP_USART3_MISO_PIN (1U) #define BSP_USART3_MISO_PORT (gpioPortC) #define BSP_USART3_MISO_LOC (18U) #define BSP_USART3_MOSI_PIN (0U) #define BSP_USART3_MOSI_PORT (gpioPortC) #define BSP_USART3_MOSI_LOC (18U) // [USART3]$ // $[VCOM] // [VCOM]$ // $[VDAC0] // [VDAC0]$ // $[VUART] // [VUART]$ // $[WDOG] // [WDOG]$ // $[WTIMER0] // [WTIMER0]$ // $[WTIMER1] // [WTIMER1]$ // $[Custom pin names] #define HALL_ENABLE_PIN (10U) #define HALL_ENABLE_PORT (gpioPortB) #define HALL_OUT1_PIN (11U) #define HALL_OUT1_PORT (gpioPortB) #define IMU_ENABLE_PIN (8U) #define IMU_ENABLE_PORT (gpioPortF) #define ENV_SENSE_ENABLE_PIN (9U) #define ENV_SENSE_ENABLE_PORT (gpioPortF) #define MIC_ENABLE_PIN (10U) #define MIC_ENABLE_PORT (gpioPortF) #define UV_ALS_INT_PIN (11U) #define UV_ALS_INT_PORT (gpioPortF) #define IMU_INT_PIN (12U) #define IMU_INT_PORT (gpioPortF) #define CCS811_INT_PIN (13U) #define CCS811_INT_PORT (gpioPortF) #define CCS811_ENABLE_PIN (14U) #define CCS811_ENABLE_PORT (gpioPortF) #define CCS811_WAKE_PIN (15U) #define CCS811_WAKE_PORT (gpioPortF) #define RGB_LED_ENABLE_PIN (14U) #define RGB_LED_ENABLE_PORT (gpioPortJ) // [Custom pin names]$ #if defined(_SILICON_LABS_MODULE) #include "sl_module.h" #endif #endif /* HAL_CONFIG_BOARD_H */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/hardware/kit/EFR32MG12_BRD4166A/config/mx25flash_config.h.
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/***************************************************************************//** * @file * @brief MX25R8035F NOR flash configuration file ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * The licensor of this software is Silicon Laboratories Inc. Your use of this * software is governed by the terms of Silicon Labs Master Software License * Agreement (MSLA) available at * www.silabs.com/about-us/legal/master-software-license-agreement. This * software is distributed to you in Source Code format and is governed by the * sections of the MSLA applicable to Source Code. * ******************************************************************************/ #ifndef MX25_CONFIG_H #define MX25_CONFIG_H #include "em_device.h" #include "em_gpio.h" #define MX25_PORT_MOSI gpioPortK #define MX25_PIN_MOSI 0 #define MX25_PORT_MISO gpioPortK #define MX25_PIN_MISO 2 #define MX25_PORT_SCLK gpioPortF #define MX25_PIN_SCLK 7 #define MX25_PORT_CS gpioPortK #define MX25_PIN_CS 1 #define MX25_USART USART2 #define MX25_USART_CLK cmuClock_USART2 #define MX25_USART_LOC_MOSI USART_ROUTELOC0_TXLOC_LOC29 #define MX25_USART_LOC_MISO USART_ROUTELOC0_RXLOC_LOC30 #define MX25_USART_LOC_SCLK USART_ROUTELOC0_CLKLOC_LOC18 #endif // MX25_CONFIG_H |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/hardware/kit/common/bsp/bsp.h.
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/***************************************************************************//** * @file * @brief Board support package API definitions. ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * The licensor of this software is Silicon Laboratories Inc. Your use of this * software is governed by the terms of Silicon Labs Master Software License * Agreement (MSLA) available at * www.silabs.com/about-us/legal/master-software-license-agreement. This * software is distributed to you in Source Code format and is governed by the * sections of the MSLA applicable to Source Code. * ******************************************************************************/ #ifndef BSP_H #define BSP_H #include <stdbool.h> #if defined(HAL_CONFIG) #include "bsphalconfig.h" #else #include "bspconfig.h" #endif #if defined(BSP_STK) || defined(BSP_WSTK) #include "em_usart.h" #endif #ifdef __cplusplus extern "C" { #endif /***************************************************************************//** * @addtogroup BSP * @brief Board Support Package * @details * The BSP provides an API for board controllers, I/O control for buttons, * LEDs, etc and trace control for EFM32, EZR32 and EFR32 kits. * * @{ ******************************************************************************/ /***************************************************************************//** * @addtogroup BSPCOMMON Common BSP for all kits * @{ ******************************************************************************/ #define BSP_STATUS_OK 0 /**< BSP API return code, no errors. */ #define BSP_STATUS_ILLEGAL_PARAM (-1) /**< BSP API return code, illegal input parameter. */ #define BSP_STATUS_NOT_IMPLEMENTED (-2) /**< BSP API return code, function not implemented (dummy). */ #define BSP_STATUS_UNSUPPORTED_MODE (-3) /**< BSP API return code, unsupported BSP mode. */ #define BSP_STATUS_IOEXP_FAILURE (-4) /**< BSP API return code, io-expander communication failed */ /* Initialization flag bitmasks for BSP_Init(). */ #define BSP_INIT_DK_SPI 0x01 /**< Mode flag for @ref BSP_Init(), init DK in SPI mode (DK3x50 only). */ #define BSP_INIT_DK_EBI 0x02 /**< Mode flag for @ref BSP_Init(), init DK in EBI mode (DK3x50 only). */ #define BSP_INIT_BCC 0x04 /**< Mode flag for @ref BSP_Init(), init board controller communication. */ #define BSP_INIT_IOEXP 0x08 /**< Mode flag for @ref BSP_Init(), init io-expander on some radio boards */ /** @} (end BSPCOMMON) */ #if defined(BSP_DK) /** @addtogroup BSP_DK API for DKs * @{ */ /** Display Control */ typedef enum { BSP_Display_EBI, /**< SSD2119 TFT controller driven by EFM32 EBI interface */ BSP_Display_SPI, /**< SSD2119 TFT controller driven by EFM32 SPI interface */ BSP_Display_BC, /**< SSD2119 TFT controller driven by board controller (AEM) */ BSP_Display_PowerEnable, /**< SSD2119 Enable power */ BSP_Display_PowerDisable, /**< SSD2119 Disable power */ BSP_Display_ResetAssert, /**< Hold SSD2119 in reset */ BSP_Display_ResetRelease, /**< Release SSD2119 in reset */ BSP_Display_Mode8080, /**< Configure SSD2119 for 8080 mode of operation */ BSP_Display_ModeGeneric, /**< Configure SSD2119 for Generic+SPI mode of operation */ } BSP_Display_TypeDef; /** Bus control access mode */ typedef enum { BSP_BusControl_Undefined = 0, /**< Board control mode unknown (not set) */ BSP_BusControl_OFF, /**< Board control disable */ BSP_BusControl_DIRECT, /**< GPIO direct drive (n/a) */ BSP_BusControl_SPI, /**< Configure Board controller for SPI mode */ BSP_BusControl_EBI, /**< Configure Board controller for EBI mode */ } BSP_BusControl_TypeDef; #if defined(BSP_DK_BRD3200) /* Gxxx_DK */ /** Peripherals control structure for Gxxx_DK's. */ typedef enum { BSP_ACCEL = BC_PERCTRL_ACCEL, /**< Accelerometer */ BSP_AMBIENT = BC_PERCTRL_AMBIENT, /**< Light sensor */ BSP_POTMETER = BC_PERCTRL_POTMETER, /**< Potentiometer */ BSP_RS232A = BC_PERCTRL_RS232A, /**< Serial port A */ BSP_RS232B = BC_PERCTRL_RS232B, /**< Serial port B */ BSP_SPI = BC_PERCTRL_SPI, /**< SPI interface */ BSP_I2C = BC_PERCTRL_I2C, /**< I2C interface */ BSP_IRDA = BC_PERCTRL_IRDA, /**< IrDA interface */ BSP_ANALOG_SE = BC_PERCTRL_ANALOG_SE, /**< Single ended analog input */ BSP_ANALOG_DIFF = BC_PERCTRL_ANALOG_DIFF, /**< Differential analog input */ BSP_AUDIO_OUT = BC_PERCTRL_AUDIO_OUT, /**< Audio Out */ BSP_AUDIO_IN = BC_PERCTRL_AUDIO_IN, /**< Audio In */ BSP_ACCEL_GSEL = BC_PERCTRL_ACCEL_GSEL, /**< Accelerometer range select */ BSP_ACCEL_SELFTEST = BC_PERCTRL_ACCEL_SELFTEST, /**< Accelerometer selftest mode */ BSP_RS232_SHUTDOWN = BC_PERCTRL_RS232_SHUTDOWN, /**< Disable RS232 */ BSP_IRDA_SHUTDOWN = BC_PERCTRL_IRDA_SHUTDOWN /**< Disable IrDA */ #ifdef DOXY_DOC_ONLY } BSP_Peripheral_Typedef; /* Hack for doxygen doc ! */ #else } BSP_Peripheral_TypeDef; #endif #endif /* BSP_DK_BRD3200 */ #if defined(BSP_DK_BRD3201) /* DK3x50 DK's */ /** Peripherals control structure for DK3x50 DK's. */ typedef enum { BSP_RS232_SHUTDOWN, /**< Disable RS232 */ BSP_RS232_UART, /**< UART control of RS232 */ BSP_RS232_LEUART, /**< LEUART control of RS232 */ BSP_I2C, /**< I2C interface */ BSP_ETH, /**< Ethernet */ BSP_I2S, /**< Audio I2S */ BSP_TRACE, /**< ETM Trace */ BSP_TOUCH, /**< Display touch interface */ BSP_AUDIO_IN, /**< Audio In */ BSP_AUDIO_OUT, /**< Audio Out */ BSP_ANALOG_DIFF, /**< Differential analog input */ BSP_ANALOG_SE, /**< Single ended analog input */ BSP_MICROSD, /**< MicroSD SPI interace */ BSP_TFT, /**< SSD2119 TFT controller */ } BSP_Peripheral_TypeDef; #endif /* BSP_DK_BRD3201 */ /** @} */ #endif /* BSP_DK */ #if defined(BSP_STK) /** @addtogroup BSP_STK API for STKs and WSTKs * @{ */ /** Peripherals control structure for STK's, WSTK's and similar. */ typedef enum { BSP_IOEXP_LEDS, /**< I/O expander LED control */ BSP_IOEXP_SENSORS, /**< I/O expander Humidity & temperature sensor control */ BSP_IOEXP_DISPLAY, /**< I/O expander Memory LCD control */ BSP_IOEXP_VCOM, /**< I/O expander VCOM (virtual com port) control */ BSP_VCOM, /**< VCOM (virtual com port) control */ } BSP_Peripheral_TypeDef; /** @} */ #endif /* BSP_STK */ /************************** The BSP API *******************************/ /***************************************************************************//** * @addtogroup BSPCOMMON Common BSP for all kits * @{ ******************************************************************************/ int BSP_Disable (void); int BSP_Init (uint32_t flags); #if defined(BSP_GPIO_EXTLEDARRAY_INIT) uint32_t BSP_ExtLedGet (int ledNo); void BSP_ExtLedSet (int ledNo, uint32_t subLeds); #endif int BSP_LedClear (int ledNo); int BSP_LedGet (int ledNo); int BSP_LedSet (int ledNo); uint32_t BSP_LedsGet (void); int BSP_LedsInit (void); int BSP_LedsSet (uint32_t leds); int BSP_LedToggle (int ledNo); int BSP_PeripheralAccess (BSP_Peripheral_TypeDef perf, bool enable); /** @} */ /* endgroup BSPCOMMON */ #if defined(BSP_DK) /***************************************************************************//** * @addtogroup BSP_DK * @{ ******************************************************************************/ BSP_BusControl_TypeDef BSP_BusControlModeGet(void); int BSP_BusControlModeSet (BSP_BusControl_TypeDef mode); uint32_t BSP_DipSwitchGet (void); int BSP_DisplayControl (BSP_Display_TypeDef option); int BSP_EbiExtendedAddressRange (bool enable); int BSP_EnergyModeSet (uint16_t energyMode); int BSP_InterruptDisable (uint16_t flags); int BSP_InterruptEnable (uint16_t flags); int BSP_InterruptFlagsClear (uint16_t flags); int BSP_InterruptFlagsSet (uint16_t flags); uint16_t BSP_InterruptFlagsGet (void); uint16_t BSP_JoystickGet (void); int BSP_McuBoard_DeInit (void); int BSP_McuBoard_Init (void); int BSP_McuBoard_UsbStatusLedEnable (bool enable); bool BSP_McuBoard_UsbVbusOcFlagGet (void); int BSP_McuBoard_UsbVbusPowerEnable (bool enable); uint16_t BSP_PushButtonsGet (void); uint16_t BSP_RegisterRead (volatile uint16_t *addr); int BSP_RegisterWrite (volatile uint16_t *addr, uint16_t data); /** @} */ /* endgroup BSP_DK */ #endif #if defined(BSP_STK) || defined(BSP_WSTK) /***************************************************************************//** * @addtogroup BSP_STK * @{ ******************************************************************************/ int BSP_BccDeInit (void); int BSP_BccInit (void); bool BSP_BccPacketReceive (BCP_Packet *pkt); int BSP_BccPacketSend (BCP_Packet *pkt); void BSP_BccPinsEnable (bool enable); float BSP_CurrentGet (void); int BSP_EbiDeInit (void); int BSP_EbiInit (void); float BSP_VoltageGet (void); uint32_t BSP_IOExpGetDeviceId (void); /** @} */ /* endgroup BSP_STK */ #endif /** @} */ /* endgroup BSP */ #ifdef __cplusplus } #endif #endif /* BSP_H */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/hardware/kit/common/bsp/bsp_bcp.h.
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/***************************************************************************//** * @file * @brief Board Controller Communications Protocol (BCP) definitions ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * The licensor of this software is Silicon Laboratories Inc. Your use of this * software is governed by the terms of Silicon Labs Master Software License * Agreement (MSLA) available at * www.silabs.com/about-us/legal/master-software-license-agreement. This * software is distributed to you in Source Code format and is governed by the * sections of the MSLA applicable to Source Code. * ******************************************************************************/ #ifndef __BSP_BCP_H #define __BSP_BCP_H #include <stdint.h> #if defined(HAL_CONFIG) #include "bsphalconfig.h" #else #include "bspconfig.h" #endif #ifdef __cplusplus extern "C" { #endif /***************************************************************************//** * @addtogroup BSP * @{ ******************************************************************************/ /***************************************************************************//** * @addtogroup BSP_STK API for STKs and WSTKs * @{ ******************************************************************************/ /* BCP Packet Types */ #define BSP_BCP_INVALID 0 /**< Invalid packet received */ #define BSP_BCP_FIRST 1 /**< Smallest numerical value of message type */ #define BSP_BCP_ACK 5 /**< Generic ACK for one way packages */ #define BSP_BCP_ECHO_REQ 10 /**< EFM32 BC alive request */ #define BSP_BCP_ECHO_REPLY 11 /**< BC alive response */ #define BSP_BCP_CURRENT_REQ 14 /**< EFM32 Request AEM current */ #define BSP_BCP_CURRENT_REPLY 16 /**< BC Response AEM current */ #define BSP_BCP_VOLTAGE_REQ 18 /**< EFM32 Request AEM voltage */ #define BSP_BCP_VOLTAGE_REPLY 20 /**< BC Response AEM voltage */ #define BSP_BCP_ENERGYMODE 22 /**< EFM32 Report Energy Mode (for AEM) */ #define BSP_BCP_STDOUT 24 /**< Debug packet (not used) */ #define BSP_BCP_STDERR 26 /**< Debug packet (not used) */ #define BSP_BCP_TEST 32 /**< Reserved type for test */ #define BSP_BCP_TEST_REPLY 33 /**< Reserved type for test (reply) */ #define BSP_BCP_NET_REQUEST 64 /**< Net gateway request packet */ #define BSP_BCP_NET_REPLY 65 /**< Net gateway reply packet */ #define BSP_BCP_LAST 100 /**< Last defined message type */ #define BSP_BCP_MAGIC 0xF1 /**< Magic byte to indicate start of packet */ #if ( (BSP_BCP_VERSION == 1) || defined(DOXY_DOC_ONLY)) #ifdef DOXY_DOC_ONLY /* Hack for doxygen doc ! */ #define BSP_BCP_PACKET_SIZe 30 /**< Max packet size for version 1 of the protocol. */ #else #define BSP_BCP_PACKET_SIZE 30 /**< Max packet size for version 1 of the protocol. */ #endif /** @brief BCP Packet Structure - Board controller communication protocol version 1. */ typedef struct { uint8_t magic; /**< Magic - start of packet - must be BSP_BCP_MAGIC */ uint8_t type; /**< Type of packet */ uint8_t payloadLength; /**< Length of data segment >=0 and <=BSP_BCP_PACKET_SIZE */ uint8_t data[BSP_BCP_PACKET_SIZE]; /**< BCP Packet Data payload */ #ifdef DOXY_DOC_ONLY } BCP_Packet_; /* Hack for doxygen doc ! */ #else } BCP_Packet; #endif #endif #if ( (BSP_BCP_VERSION == 2) || DOXY_DOC_ONLY) #define BSP_BCP_PACKET_SIZE 132 /**< Max packet size for version 2 of the protocol. */ /** @brief BCP Packet Structure - Board controller communication protocol version 2. */ typedef struct { uint8_t magic; /**< Magic - start of packet - must be BSP_BCP_MAGIC */ uint8_t type; /**< Type - packet type */ uint8_t payloadLength; /**< Length of data segment >=0 and <=BSP_BCP_PACKET_SIZE */ uint8_t reserved; /**< Reserved for future expansion */ uint8_t data[BSP_BCP_PACKET_SIZE]; /**< BCP Packet Data payload */ } BCP_Packet; /** @brief BCP Packet Header definition */ typedef struct { uint8_t magic; /**< Magic - start of packet - must be BSP_BCP_MAGIC */ uint8_t type; /**< Type - packet type */ uint8_t payloadLength; /**< Length of data segment >=0 and <=BSP_BCP_PACKET_SIZE */ uint8_t reserved; /**< Reserved for future expansion */ } BCP_PacketHeader; #endif #if ( (BSP_BCP_VERSION != 1) && (BSP_BCP_VERSION != 2) ) #error "BSP BCP Board Controller communications protocol version error." #endif #if (BSP_BCP_PACKET_SIZE >= 255) #error "BSP BCP Board Controller communications packets must be less than 255 bytes in size!" #endif /** @} (end group BSP_STK) */ /** @} (end group BSP) */ #ifdef __cplusplus } #endif #endif /* __BSP_BCP_H */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/hardware/kit/common/bsp/bsp_stk.c.
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/***************************************************************************//** * @file * @brief Board support package API implementation STK's. ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * The licensor of this software is Silicon Laboratories Inc. Your use of this * software is governed by the terms of Silicon Labs Master Software License * Agreement (MSLA) available at * www.silabs.com/about-us/legal/master-software-license-agreement. This * software is distributed to you in Source Code format and is governed by the * sections of the MSLA applicable to Source Code. * ******************************************************************************/ #include <string.h> #include "em_device.h" #include "em_cmu.h" #include "em_gpio.h" #include "bsp.h" #if defined(BSP_STK_USE_EBI) #include "em_ebi.h" #endif #if defined(BSP_IO_EXPANDER) #include "bsp_stk_ioexp.h" #endif #if defined(BSP_STK) /***************************************************************************//** * @addtogroup BSP * @{ ******************************************************************************/ /***************************************************************************//** * @addtogroup BSP_STK API for STKs and WSTKs * @{ ******************************************************************************/ /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ /**************************************************************************//** * @brief Deinitialize board support package functionality. * Reverse actions performed by @ref BSP_Init(). * * @return @ref BSP_STATUS_OK. *****************************************************************************/ int BSP_Disable(void) { #if defined(BSP_BCC_USART) || defined(BSP_BCC_LEUART) BSP_BccDeInit(); #endif BSP_EbiDeInit(); #if defined(BSP_IO_EXPANDER) ioexpDisable(); #endif return BSP_STATUS_OK; } /** @endcond */ /**************************************************************************//** * @brief Initialize the EBI interface for accessing the onboard nandflash. * * @note This function is not relevant for Gxxx_STK's. * * @return * @ref BSP_STATUS_OK or @ref BSP_STATUS_NOT_IMPLEMENTED *****************************************************************************/ int BSP_EbiInit(void) { #if defined(BSP_STK_USE_EBI) /* ------------------------------------------ */ /* NAND Flash, Bank0, Base Address 0x80000000 */ /* Micron flash NAND256W3A */ /* ------------------------------------------ */ EBI_Init_TypeDef ebiConfig = { ebiModeD8A8, /* 8 bit address, 8 bit data */ ebiActiveLow, /* ARDY polarity */ ebiActiveLow, /* ALE polarity */ ebiActiveLow, /* WE polarity */ ebiActiveLow, /* RE polarity */ ebiActiveLow, /* CS polarity */ ebiActiveLow, /* BL polarity */ false, /* disble BL */ true, /* enable NOIDLE */ false, /* disable ARDY */ true, /* disable ARDY timeout */ EBI_BANK0, /* enable bank 0 */ 0, /* no chip select */ 0, /* addr setup cycles */ 0, /* addr hold cycles */ false, /* disable half cycle ALE strobe */ 0, /* read setup cycles */ 2, /* read strobe cycles */ 1, /* read hold cycles */ false, /* disable page mode */ false, /* disable prefetch */ false, /* disable half cycle REn strobe */ 0, /* write setup cycles */ 2, /* write strobe cycles */ 1, /* write hold cycles */ false, /* enable the write buffer */ false, /* disable half cycle WEn strobe */ ebiALowA24, /* ALB - Low bound, address lines */ ebiAHighA26, /* APEN - High bound, address lines */ ebiLocation1, /* Use Location 1 */ true, /* enable EBI */ }; /* Enable clocks */ CMU_ClockEnable(cmuClock_HFPER, true); CMU_ClockEnable(cmuClock_GPIO, true); CMU_ClockEnable(cmuClock_EBI, true); /* Enable GPIO's */ /* ALE and CLE */ GPIO_PinModeSet(gpioPortC, 1, gpioModePushPull, 0); GPIO_PinModeSet(gpioPortC, 2, gpioModePushPull, 0); /* WP, CE and R/B */ GPIO_PinModeSet(gpioPortD, 13, gpioModePushPull, 0); /* active low write-protect */ GPIO_PinModeSet(gpioPortD, 14, gpioModePushPull, 1); /* active low chip-enable */ GPIO_PinModeSet(gpioPortD, 15, gpioModeInput, 0); /* ready/busy */ /* IO pins */ GPIO_PinModeSet(gpioPortE, 8, gpioModePushPull, 0); GPIO_PinModeSet(gpioPortE, 9, gpioModePushPull, 0); GPIO_PinModeSet(gpioPortE, 10, gpioModePushPull, 0); GPIO_PinModeSet(gpioPortE, 11, gpioModePushPull, 0); GPIO_PinModeSet(gpioPortE, 12, gpioModePushPull, 0); GPIO_PinModeSet(gpioPortE, 13, gpioModePushPull, 0); GPIO_PinModeSet(gpioPortE, 14, gpioModePushPull, 0); GPIO_PinModeSet(gpioPortE, 15, gpioModePushPull, 0); /* WE and RE */ GPIO_PinModeSet(gpioPortF, 8, gpioModePushPull, 1); GPIO_PinModeSet(gpioPortF, 9, gpioModePushPull, 1); /* NAND Power Enable */ GPIO_PinModeSet(gpioPortB, 15, gpioModePushPull, 1); EBI_Init(&ebiConfig); EBI->NANDCTRL = (EBI_NANDCTRL_BANKSEL_BANK0 | EBI_NANDCTRL_EN); return BSP_STATUS_OK; #else return BSP_STATUS_NOT_IMPLEMENTED; #endif } /**************************************************************************//** * @brief Deinitialize the EBI interface for accessing the onboard nandflash. * * @note This function is not relevant for Gxxx_STK's. * This function is provided for API completeness, it does not perform * an actual EBI deinitialization. * * @return * @ref BSP_STATUS_OK or @ref BSP_STATUS_NOT_IMPLEMENTED *****************************************************************************/ int BSP_EbiDeInit(void) { #if defined(BSP_STK_USE_EBI) return BSP_STATUS_OK; #else return BSP_STATUS_NOT_IMPLEMENTED; #endif } /**************************************************************************//** * @brief Get IO Expander Device id. * * @return * The device id of a connected IO Expander Device id or 0 if no IO expander * is connected. *****************************************************************************/ uint32_t BSP_IOExpGetDeviceId(void) { #if defined(BSP_IO_EXPANDER) return ioexpGetDeviceId(); #else return 0; #endif } /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ /**************************************************************************//** * @brief Initialize board support package functionality. * * @param[in] flags Initialization mask, use 0 or @ref BSP_INIT_BCC. * * @return * @ref BSP_STATUS_OK or BSP_STATUS_IOEXP_FAILURE *****************************************************************************/ int BSP_Init(uint32_t flags) { (void) flags; #if defined(BSP_IO_EXPANDER) int status; #endif #if defined(BSP_BCC_USART) || defined(BSP_BCC_LEUART) if ( flags & BSP_INIT_BCC ) { BSP_BccInit(); } #endif #if defined(BSP_IO_EXPANDER) if (flags & BSP_INIT_IOEXP) { status = ioexpEnable(); if (status != BSP_STATUS_OK) { return status; } } #endif return BSP_STATUS_OK; } /** @endcond */ /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ /**************************************************************************//** * @brief STK Peripheral Access Control * Enable or disable access to on-board peripherals using the IO-expander. * * @param[in] perf * Which peripheral to configure. Use enum @ref BSP_Peripheral_TypeDef. * * @param[in] enable * If true, set up access to peripheral, if false disable access. * * @return * @ref BSP_STATUS_OK, @ref BSP_STATUS_NOT_IMPLEMENTED * or @ref BSP_STATUS_IOEXP_FAILURE *****************************************************************************/ int BSP_PeripheralAccess(BSP_Peripheral_TypeDef perf, bool enable) { #if defined(BSP_IO_EXPANDER) || defined(BSP_BCC_ENABLE_PORT) int status = BSP_STATUS_OK; if (enable) { switch (perf) { #if defined(BSP_IO_EXPANDER) case BSP_IOEXP_LEDS: status = ioexpWriteReg(BSP_IOEXP_REG_LED_CTRL, BSP_IOEXP_REG_LED_CTRL_DIRECT); break; case BSP_IOEXP_SENSORS: status = ioexpWriteReg(BSP_IOEXP_REG_SENSOR_CTRL, 1); break; case BSP_IOEXP_DISPLAY: /* Cant use VCOM together with the display. */ status = ioexpWriteReg(BSP_IOEXP_REG_VCOM_CTRL, 0); if (status == BSP_STATUS_OK) { status = ioexpWriteReg(BSP_IOEXP_REG_DISP_CTRL, BSP_IOEXP_REG_DISP_CTRL_ENABLE | BSP_IOEXP_REG_DISP_CTRL_AUTO_EXTCOMIN); } break; case BSP_VCOM: case BSP_IOEXP_VCOM: /* Cant use the display together with VCOM. */ status = ioexpWriteReg(BSP_IOEXP_REG_DISP_CTRL, 0); if (status == BSP_STATUS_OK) { status = ioexpWriteReg(BSP_IOEXP_REG_VCOM_CTRL, 1); } break; #elif defined(BSP_BCC_ENABLE_PORT) case BSP_VCOM: GPIO_PinModeSet(BSP_BCC_ENABLE_PORT, BSP_BCC_ENABLE_PIN, gpioModePushPull, 1); break; default: status = BSP_STATUS_NOT_IMPLEMENTED; break; #endif } } else { switch (perf) { #if defined(BSP_IO_EXPANDER) case BSP_IOEXP_LEDS: status = ioexpWriteReg(BSP_IOEXP_REG_LED_CTRL, 0); break; case BSP_IOEXP_SENSORS: status = ioexpWriteReg(BSP_IOEXP_REG_SENSOR_CTRL, 0); break; case BSP_IOEXP_DISPLAY: status = ioexpWriteReg(BSP_IOEXP_REG_DISP_CTRL, 0); break; case BSP_VCOM: case BSP_IOEXP_VCOM: status = ioexpWriteReg(BSP_IOEXP_REG_VCOM_CTRL, 0); break; #elif defined(BSP_BCC_ENABLE_PORT) case BSP_VCOM: GPIO_PinModeSet(BSP_BCC_ENABLE_PORT, BSP_BCC_ENABLE_PIN, gpioModePushPull, 0); break; default: status = BSP_STATUS_NOT_IMPLEMENTED; break; #endif } } return status; #else (void)perf; (void)enable; return BSP_STATUS_NOT_IMPLEMENTED; #endif } /** @endcond */ /**************************************************************************//** * @brief Request AEM (Advanced Energy Monitoring) current from board controller. * * @note Assumes that BSP_Init() has been called with @ref BSP_INIT_BCC * bitmask. * * @return * The current expressed in milliamperes. Returns 0.0 on board controller * communication error. *****************************************************************************/ float BSP_CurrentGet(void) { #if defined(BSP_BCC_USART) || defined(BSP_BCC_LEUART) BCP_Packet pkt; float *pcurrent; pkt.type = BSP_BCP_CURRENT_REQ; pkt.payloadLength = 0; /* Send Request/Get reply */ BSP_BccPacketSend(&pkt); BSP_BccPacketReceive(&pkt); /* Process reply */ pcurrent = (float *)pkt.data; if ( pkt.type != BSP_BCP_CURRENT_REPLY ) { *pcurrent = 0.0f; } return *pcurrent; #else return 0.0f; #endif } /**************************************************************************//** * @brief Request AEM (Advanced Energy Monitoring) voltage from board controller. * * @note Assumes that BSP_Init() has been called with @ref BSP_INIT_BCC * bitmask. * * @return * The voltage. Returns 0.0 on board controller communication * error. *****************************************************************************/ float BSP_VoltageGet(void) { #if defined(BSP_BCC_USART) || defined(BSP_BCC_LEUART) BCP_Packet pkt; float *pvoltage; pkt.type = BSP_BCP_VOLTAGE_REQ; pkt.payloadLength = 0; /* Send Request/Get reply */ BSP_BccPacketSend(&pkt); BSP_BccPacketReceive(&pkt); /* Process reply */ pvoltage = (float *)pkt.data; if ( pkt.type != BSP_BCP_VOLTAGE_REPLY ) { *pvoltage = 0.0f; } return *pvoltage; #else return 0.0f; #endif } /** @} (end group BSP_STK) */ /** @} (end group BSP) */ #endif /* BSP_STK */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/hardware/kit/common/drivers/i2cspm.h.
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/***************************************************************************//** * @file * @brief I2C simple poll-based master mode driver for the DK/STK. ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * The licensor of this software is Silicon Laboratories Inc. Your use of this * software is governed by the terms of Silicon Labs Master Software License * Agreement (MSLA) available at * www.silabs.com/about-us/legal/master-software-license-agreement. This * software is distributed to you in Source Code format and is governed by the * sections of the MSLA applicable to Source Code. * ******************************************************************************/ #ifndef __SILICON_LABS_I2CSPM_H__ #define __SILICON_LABS_I2CSPM_H__ #if defined(HAL_CONFIG) #include "i2cspmhalconfig.h" #else #include "i2cspmconfig.h" #endif #include "em_gpio.h" #include "em_i2c.h" /***************************************************************************//** * @defgroup kitdrv Kit Drivers * @brief Kit support and drivers * @details * Drivers and support modules for board components such as displays, sensors and * memory components on EFM32, EZR32 and EFR32 kits. * * For display device support, see section @ref display_doc for more information. * @{ ******************************************************************************/ /***************************************************************************//** * @addtogroup I2CSPM * @{ ******************************************************************************/ #ifdef __cplusplus extern "C" { #endif /******************************************************************************* ******************************** STRUCTS ********************************** ******************************************************************************/ /** I2C driver instance initialization structure. This data structure contains a number of I2C configuration options required for driver instance initialization. This struct is passed to @ref I2CSPM_Init() when initializing a I2CSPM instance. */ typedef struct { I2C_TypeDef *port; /**< Peripheral port */ GPIO_Port_TypeDef sclPort; /**< SCL pin port number */ uint8_t sclPin; /**< SCL pin number */ GPIO_Port_TypeDef sdaPort; /**< SDA pin port number */ uint8_t sdaPin; /**< SDA pin number */ #if defined(_SILICON_LABS_32B_SERIES_0) uint8_t portLocation; /**< Port location */ #elif defined(_SILICON_LABS_32B_SERIES_1) uint8_t portLocationScl; /**< Port location of SCL signal */ uint8_t portLocationSda; /**< Port location of SDA signal */ #endif uint32_t i2cRefFreq; /**< I2C reference clock */ uint32_t i2cMaxFreq; /**< I2C max bus frequency to use */ I2C_ClockHLR_TypeDef i2cClhr; /**< Clock low/high ratio control */ } I2CSPM_Init_TypeDef; /** Default config for I2C init structure. The default may be overridden by a i2cspmconfig.h file. */ #if !defined(I2CSPM_INIT_DEFAULT) #if defined(_SILICON_LABS_32B_SERIES_0) #define I2CSPM_INIT_DEFAULT \ { I2C0, /* Use I2C instance 0 */ \ gpioPortC, /* SCL port */ \ 5, /* SCL pin */ \ gpioPortC, /* SDA port */ \ 4, /* SDA pin */ \ 0, /* Location */ \ 0, /* Use currently configured reference clock */ \ I2C_FREQ_STANDARD_MAX, /* Set to standard rate */ \ i2cClockHLRStandard, /* Set to use 4:4 low/high duty cycle */ \ } #elif defined(_SILICON_LABS_32B_SERIES_1) #define I2CSPM_INIT_DEFAULT \ { I2C0, /* Use I2C instance 0 */ \ gpioPortC, /* SCL port */ \ 11, /* SCL pin */ \ gpioPortC, /* SDA port */ \ 10, /* SDA pin */ \ 15, /* Location of SCL */ \ 15, /* Location of SDA */ \ 0, /* Use currently configured reference clock */ \ I2C_FREQ_STANDARD_MAX, /* Set to standard rate */ \ i2cClockHLRStandard, /* Set to use 4:4 low/high duty cycle */ \ } #elif defined(_SILICON_LABS_32B_SERIES_2) #define I2CSPM_INIT_DEFAULT \ { I2C0, /* Use I2C instance 0 */ \ gpioPortC, /* SCL port */ \ 11, /* SCL pin */ \ gpioPortC, /* SDA port */ \ 10, /* SDA pin */ \ 0, /* Use currently configured reference clock */ \ I2C_FREQ_STANDARD_MAX, /* Set to standard rate */ \ i2cClockHLRStandard, /* Set to use 4:4 low/high duty cycle */ \ } #endif #endif /******************************************************************************* ***************************** PROTOTYPES ********************************** ******************************************************************************/ void I2CSPM_Init(I2CSPM_Init_TypeDef *init); I2C_TransferReturn_TypeDef I2CSPM_Transfer(I2C_TypeDef *i2c, I2C_TransferSeq_TypeDef *seq); #ifdef __cplusplus } #endif /** @} (end group I2CSPM) */ /** @} (end group kitdrv) */ #endif /* __SILICON_LABS_I2CSPM_H__ */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/hardware/kit/common/drivers/mx25flash_spi.c.
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/***************************************************************************//** * # License * * The licensor of this software is Silicon Laboratories Inc. Your use of this * software is governed by the terms of Silicon Labs Master Software License * Agreement (MSLA) available at * www.silabs.com/about-us/legal/master-software-license-agreement. This * software is Third Party Software licensed by Silicon Labs from a third party * and is governed by the sections of the MSLA applicable to Third Party * Software and the additional terms set forth below. * ******************************************************************************/ /* * COPYRIGHT (c) 2010-2015 MACRONIX INTERNATIONAL CO., LTD * SPI Flash Low Level Driver (LLD) Sample Code * * SPI interface command set * * $Id: MX25_CMD.c,v 1.31 2015/03/24 01:06:33 mxclldb1 Exp $ */ #include "mx25flash_spi.h" #include "em_gpio.h" #include "em_usart.h" #include "em_cmu.h" /* If the USART for the MX25 driver is not defined, these functions are unavailable */ #ifdef MX25_USART /* Fallback to loc 11 if no location is defined for backwards compatibility */ #ifndef MX25_LOC_RX #define MX25_LOC_RX _USART_ROUTELOC0_RXLOC_LOC11 #endif #ifndef MX25_LOC_SCLK #define MX25_LOC_SCLK _USART_ROUTELOC0_CLKLOC_LOC11 #endif #ifndef MX25_LOC_TX #define MX25_LOC_TX _USART_ROUTELOC0_TXLOC_LOC11 #endif /* Fallback to baudrate of 8 MHz if not defined for backwards compatibility */ #ifndef MX25_BAUDRATE #define MX25_BAUDRATE 8000000 #endif /* Local functions */ /* Basic functions */ void CS_High( void ); void CS_Low( void ); void InsertDummyCycle( uint8_t dummy_cycle ); void SendByte( uint8_t byte_value, uint8_t transfer_type ); uint8_t GetByte( uint8_t transfer_type ); /* Utility functions */ void Wait_Flash_WarmUp( void ); void Initial_Spi( void ); bool WaitFlashReady( uint32_t ExpectTime ); bool WaitRYBYReady( uint32_t ExpectTime ); bool IsFlashBusy( void ); bool IsFlashQIO( void ); bool IsFlash4Byte( void ); void SendFlashAddr( uint32_t flash_address, uint8_t io_mode, bool addr_4byte_mode ); uint8_t GetDummyCycle( uint32_t default_cycle ); void MX25_init( void ) { USART_InitSync_TypeDef init = USART_INITSYNC_DEFAULT; CMU_ClockEnable( cmuClock_GPIO, true ); CMU_ClockEnable( MX25_USART_CLK, true ); init.msbf = true; init.baudrate = MX25_BAUDRATE; USART_InitSync( MX25_USART, &init ); /* IO config */ GPIO_PinModeSet( MX25_PORT_MOSI, MX25_PIN_MOSI, gpioModePushPull, 1 ); GPIO_PinModeSet( MX25_PORT_MISO, MX25_PIN_MISO, gpioModeInput, 0 ); GPIO_PinModeSet( MX25_PORT_SCLK, MX25_PIN_SCLK, gpioModePushPull, 1 ); GPIO_PinModeSet( MX25_PORT_CS, MX25_PIN_CS, gpioModePushPull, 1 ); #ifdef _GPIO_USART_ROUTEEN_MASK MX25_USART_ROUTE.CLKROUTE = ( (MX25_PORT_SCLK << _GPIO_USART_CLKROUTE_PORT_SHIFT) | (MX25_PIN_SCLK << _GPIO_USART_CLKROUTE_PIN_SHIFT) ); MX25_USART_ROUTE.RXROUTE = ( (MX25_PORT_MISO << _GPIO_USART_RXROUTE_PORT_SHIFT) | (MX25_PIN_MISO << _GPIO_USART_RXROUTE_PIN_SHIFT) ); MX25_USART_ROUTE.TXROUTE = ( (MX25_PORT_MOSI << _GPIO_USART_TXROUTE_PORT_SHIFT) | (MX25_PIN_MOSI << _GPIO_USART_TXROUTE_PIN_SHIFT) ); MX25_USART_ROUTE.ROUTEEN = ( GPIO_USART_ROUTEEN_RXPEN | GPIO_USART_ROUTEEN_TXPEN | GPIO_USART_ROUTEEN_CLKPEN ); #else MX25_USART->ROUTELOC0 = ( (MX25_LOC_RX << _USART_ROUTELOC0_RXLOC_SHIFT) | (MX25_LOC_TX << _USART_ROUTELOC0_TXLOC_SHIFT) | (MX25_LOC_SCLK << _USART_ROUTELOC0_CLKLOC_SHIFT) ); MX25_USART->ROUTEPEN = ( USART_ROUTEPEN_RXPEN | USART_ROUTEPEN_TXPEN | USART_ROUTEPEN_CLKPEN ); #endif /* Wait for flash warm-up */ Initial_Spi(); } void MX25_deinit( void ) { GPIO_PinModeSet( MX25_PORT_MOSI, MX25_PIN_MOSI, gpioModeDisabled, 0); GPIO_PinModeSet( MX25_PORT_MISO, MX25_PIN_MISO, gpioModeDisabled, 0); GPIO_PinModeSet( MX25_PORT_SCLK, MX25_PIN_SCLK, gpioModeDisabled, 1); GPIO_PinModeSet( MX25_PORT_CS, MX25_PIN_CS, gpioModeDisabled, 1); USART_Reset(MX25_USART); #ifdef _GPIO_USART_ROUTEEN_MASK MX25_USART_ROUTE.CLKROUTE = _GPIO_USART_CLKROUTE_RESETVALUE; MX25_USART_ROUTE.RXROUTE = _GPIO_USART_RXROUTE_RESETVALUE; MX25_USART_ROUTE.TXROUTE = _GPIO_USART_TXROUTE_RESETVALUE; MX25_USART_ROUTE.ROUTEEN = _GPIO_USART_ROUTEEN_RESETVALUE; #else MX25_USART->ROUTELOC0 = _USART_ROUTELOC0_RESETVALUE; MX25_USART->ROUTEPEN = _USART_ROUTEPEN_RESETVALUE; #endif CMU_ClockEnable( MX25_USART_CLK, false ); } /* --Common functions */ /* * Function: Wait_Flash_WarmUp * Arguments: None. * Description: Wait some time until flash read / write enable. * Return Message: None. */ void Wait_Flash_WarmUp() { volatile int time_cnt = FlashFullAccessTime; while( time_cnt > 0 ) { time_cnt--; } } /* * Function: Initial_Spi * Arguments: None * Description: Initial spi flash state and wait flash warm-up * (enable read/write). * Return Message: None */ void Initial_Spi() { // Wait flash warm-up Wait_Flash_WarmUp(); } /* * Function: CS_Low, CS_High * Arguments: None. * Description: Chip select go low / high. * Return Message: None. */ void CS_Low() { GPIO_PinOutClear( MX25_PORT_CS, MX25_PIN_CS ); } void CS_High() { GPIO_PinOutSet( MX25_PORT_CS, MX25_PIN_CS ); } /* * Function: InsertDummyCycle * Arguments: dummy_cycle, number of dummy clock cycle * Description: Insert dummy cycle of SCLK * Return Message: None. */ void InsertDummyCycle( uint8_t dummy_cycle ) { int i; for( i = 0; i < dummy_cycle/8; i++ ) { USART_SpiTransfer( MX25_USART, 0xff ); } } /* * Function: SendByte * Arguments: byte_value, data transfer to flash * transfer_type, select different type of I/O mode. * Seven mode: * SIO, single IO * DIO, dual IO * QIO, quad IO * PIO, parallel * DTSIO, double transfer rate SIO * DTDIO, double transfer rate DIO * DTQIO, double transfer rate QIO * Description: Send one byte data to flash * Return Message: None. */ void SendByte( uint8_t byte_value, uint8_t transfer_type ) { switch( transfer_type ) { #ifdef SIO case SIO: // Single I/O USART_SpiTransfer( MX25_USART, byte_value ); break; #endif #ifdef DIO case DIO: // Dual I/O //--- IO mode not supported! ---// break; #endif #ifdef QIO case QIO: // Quad I/O //--- IO mode not supported! ---// break; #endif #ifdef PIO case PIO: // Parallel I/O //--- IO mode not supported! ---// break; #endif #ifdef DTSIO case DTSIO: // Double transfer rate Single I/O //--- IO mode not supported! ---// break; #endif #ifdef DTDIO case DTDIO: // Double transfer rate Dual I/O //--- IO mode not supported! ---// break; #endif #ifdef DTQIO case DTQIO: // Double transfer rate Quad I/O //--- IO mode not supported! ---// break; #endif default: break; } } /* * Function: GetByte * Arguments: byte_value, data receive from flash * transfer_type, select different type of I/O mode. * Seven mode: * SIO, single IO * DIO, dual IO * QIO, quad IO * PIO, parallel IO * DTSIO, double transfer rate SIO * DTDIO, double transfer rate DIO * DTQIO, double transfer rate QIO * Description: Get one byte data to flash * Return Message: 8 bit data */ uint8_t GetByte( uint8_t transfer_type ) { uint8_t data_buf = 0; switch( transfer_type ) { #ifdef SIO case SIO: // Single I/O //--- insert your code here for single IO receive. ---// data_buf = USART_SpiTransfer( MX25_USART, 0xff ); break; #endif #ifdef DIO case DIO: // Dual I/O //--- IO mode not supported! ---// break; #endif #ifdef QIO case QIO: // Quad I/O //--- IO mode not supported! ---// break; #endif #ifdef PIO case PIO: // Parallel I/O //--- IO mode not supported! ---// break; #endif #ifdef DTSIO case DTSIO: // Double transfer rate Single I/O //--- IO mode not supported! ---// break; #endif #ifdef DTDIO case DTDIO: // Double transfer rate Dual I/O //--- IO mode not supported! ---// break; #endif #ifdef DTQIO case DTQIO: // Double transfer rate Qual I/O //--- IO mode not supported! ---// #endif default: break; } return data_buf; } /* * Function: WaitFlashReady * Arguments: ExpectTime, expected time-out value of flash operations. * No use at non-synchronous IO mode. * Description: Synchronous IO: * If flash is ready return TRUE. * If flash is time-out return FALSE. * Non-synchronous IO: * Always return TRUE * Return Message: TRUE, FALSE */ bool WaitFlashReady( uint32_t ExpectTime ) { #ifndef NON_SYNCHRONOUS_IO volatile uint32_t temp = 0; while( IsFlashBusy() ) { if( temp > ExpectTime ) { return FALSE; } temp = temp + 1; } return TRUE; #else return TRUE; #endif } /* * Function: WaitRYBYReady * Arguments: ExpectTime, expected time-out value of flash operations. * No use at non-synchronous IO mode. * Description: Synchronous IO: * If flash is ready return TRUE. * If flash is time-out return FALSE. * Non-synchronous IO: * Always return TRUE * Return Message: TRUE, FALSE */ bool WaitRYBYReady( uint32_t ExpectTime ) { #ifndef NON_SYNCHRONOUS_IO uint32_t temp = 0; #ifdef GPIO_SPI while( SO == 0 ) #else while(GPIO_PinInGet(MX25_PORT_MISO, MX25_PIN_MISO) == 0) #endif { if( temp > ExpectTime ) { return FALSE; } temp = temp + 1; } return TRUE; #else return TRUE; #endif } /* * Function: IsFlashBusy * Arguments: None. * Description: Check status register WIP bit. * If WIP bit = 1: return TRUE ( Busy ) * = 0: return FALSE ( Ready ). * Return Message: TRUE, FALSE */ bool IsFlashBusy( void ) { uint8_t gDataBuffer; MX25_RDSR( &gDataBuffer ); if( (gDataBuffer & FLASH_WIP_MASK) == FLASH_WIP_MASK ) return TRUE; else return FALSE; } /* * Function: IsFlashQIO * Arguments: None. * Description: If flash QE bit = 1: return TRUE * = 0: return FALSE. * Return Message: TRUE, FALSE */ bool IsFlashQIO( void ) { #ifdef FLASH_NO_QE_BIT return TRUE; #else uint8_t gDataBuffer; MX25_RDSR( &gDataBuffer ); if( (gDataBuffer & FLASH_QE_MASK) == FLASH_QE_MASK ) return TRUE; else return FALSE; #endif } /* * Function: IsFlash4Byte * Arguments: None * Description: Check flash address is 3-byte or 4-byte. * If flash 4BYTE bit = 1: return TRUE * = 0: return FALSE. * Return Message: TRUE, FALSE */ bool IsFlash4Byte( void ) { #ifdef FLASH_CMD_RDSCUR #ifdef FLASH_4BYTE_ONLY return TRUE; #elif FLASH_3BYTE_ONLY return FALSE; #else uint8_t gDataBuffer; MX25_RDSCUR( &gDataBuffer ); if( (gDataBuffer & FLASH_4BYTE_MASK) == FLASH_4BYTE_MASK ) return TRUE; else return FALSE; #endif #else return FALSE; #endif } /* * Function: SendFlashAddr * Arguments: flash_address, 32 bit flash memory address * io_mode, I/O mode to transfer address * addr_4byte_mode, * Description: Send flash address with 3-byte or 4-byte mode. * Return Message: None */ void SendFlashAddr( uint32_t flash_address, uint8_t io_mode, bool addr_4byte_mode ) { /* Check flash is 3-byte or 4-byte mode. 4-byte mode: Send 4-byte address (A31-A0) 3-byte mode: Send 3-byte address (A23-A0) */ if( addr_4byte_mode == TRUE ){ SendByte( (flash_address >> 24), io_mode ); // A31-A24 } /* A23-A0 */ SendByte( (flash_address >> 16), io_mode ); SendByte( (flash_address >> 8), io_mode ); SendByte( (flash_address), io_mode ); } /* * Function: GetDummyCycle * Arguments: default_cycle, default dummy cycle * fsptr, pointer of flash status structure * Description: Get dummy cycle for different condition * default_cycle: Byte3 | Byte2 | Byte1 | Byte0 * DC 1 bit: x 1 x 0 * DC 2 bit: 11 10 01 00 * Note: the variable dummy cycle only support in some product. * Return Message: Dummy cycle value */ uint8_t GetDummyCycle( uint32_t default_cycle ) { #ifdef FLASH_CMD_RDCR uint8_t gDataBuffer; uint8_t dummy_cycle = default_cycle; MX25_RDCR( &gDataBuffer ); #ifdef SUPPORT_CR_DC // product support 1-bit dummy cycle configuration if( (gDataBuffer & FLASH_DC_MASK) == FLASH_DC_MASK ) dummy_cycle = default_cycle >> 16; else dummy_cycle = default_cycle; #elif SUPPORT_CR_DC_2bit // product support 2-bit dummy cycle configuration switch( gDataBuffer & FLASH_DC_2BIT_MASK ){ case 0x00: dummy_cycle = default_cycle; break; case 0x40: dummy_cycle = default_cycle >> 8; break; case 0x80: dummy_cycle = default_cycle >> 16; break; case 0xC0: dummy_cycle = default_cycle >> 24; break; } #else // configuration register not support dummy configuration dummy_cycle = default_cycle; #endif return dummy_cycle; #else // default case: return default dummy cycle return default_cycle; #endif } /* * ID Command */ /* * Function: MX25_RDID * Arguments: Identification, 32 bit buffer to store id * Description: The RDID instruction is to read the manufacturer ID * of 1-byte and followed by Device ID of 2-byte. * Return Message: FlashOperationSuccess */ ReturnMsg MX25_RDID( uint32_t *Identification ) { uint32_t temp; uint8_t gDataBuffer[3]; // Chip select go low to start a flash command CS_Low(); // Send command SendByte( FLASH_CMD_RDID, SIO ); // Get manufacturer identification, device identification gDataBuffer[0] = GetByte( SIO ); gDataBuffer[1] = GetByte( SIO ); gDataBuffer[2] = GetByte( SIO ); // Chip select go high to end a command CS_High(); // Store identification temp = gDataBuffer[0]; temp = (temp << 8) | gDataBuffer[1]; *Identification = (temp << 8) | gDataBuffer[2]; return FlashOperationSuccess; } /* * Function: MX25_RES * Arguments: ElectricIdentification, 8 bit buffer to store electric id * Description: The RES instruction is to read the Device * electric identification of 1-byte. * Return Message: FlashOperationSuccess */ ReturnMsg MX25_RES( uint8_t *ElectricIdentification ) { // Chip select go low to start a flash command CS_Low(); // Send flash command and insert dummy cycle SendByte( FLASH_CMD_RES, SIO ); InsertDummyCycle( 24 ); // Get electric identification *ElectricIdentification = GetByte( SIO ); // Chip select go high to end a flash command CS_High(); return FlashOperationSuccess; } /* * Function: MX25_REMS * Arguments: REMS_Identification, 16 bit buffer to store id * fsptr, pointer of flash status structure * Description: The REMS instruction is to read the Device * manufacturer ID and electric ID of 1-byte. * Return Message: FlashOperationSuccess */ ReturnMsg MX25_REMS( uint16_t *REMS_Identification, FlashStatus *fsptr ) { uint8_t gDataBuffer[2]; // Chip select go low to start a flash command CS_Low(); // Send flash command and insert dummy cycle ( if need ) // ArrangeOpt = 0x00 will output the manufacturer's ID first // = 0x01 will output electric ID first SendByte( FLASH_CMD_REMS, SIO ); InsertDummyCycle( 16 ); SendByte( fsptr->ArrangeOpt, SIO ); // Get ID gDataBuffer[0] = GetByte( SIO ); gDataBuffer[1] = GetByte( SIO ); // Store identification informaion *REMS_Identification = (gDataBuffer[0] << 8) | gDataBuffer[1]; // Chip select go high to end a flash command CS_High(); return FlashOperationSuccess; } /* * Register Command */ /* * Function: MX25_RDSR * Arguments: StatusReg, 8 bit buffer to store status register value * Description: The RDSR instruction is for reading Status Register Bits. * Return Message: FlashOperationSuccess */ ReturnMsg MX25_RDSR( uint8_t *StatusReg ) { uint8_t gDataBuffer; // Chip select go low to start a flash command CS_Low(); // Send command SendByte( FLASH_CMD_RDSR, SIO ); gDataBuffer = GetByte( SIO ); // Chip select go high to end a flash command CS_High(); *StatusReg = gDataBuffer; return FlashOperationSuccess; } /* * Function: MX25_WRSR * Arguments: UpdateValue, 8/16 bit status register value to updata * Description: The WRSR instruction is for changing the values of * Status Register Bits (and configuration register) * Return Message: FlashIsBusy, FlashTimeOut, FlashOperationSuccess */ #ifdef SUPPORT_WRSR_CR ReturnMsg MX25_WRSR( uint16_t UpdateValue ) #else ReturnMsg MX25_WRSR( uint8_t UpdateValue ) #endif { // Check flash is busy or not if( IsFlashBusy() ) return FlashIsBusy; // Setting Write Enable Latch bit MX25_WREN(); // Chip select go low to start a flash command CS_Low(); // Send command and update value SendByte( FLASH_CMD_WRSR, SIO ); SendByte( UpdateValue, SIO ); #ifdef SUPPORT_WRSR_CR SendByte( UpdateValue >> 8, SIO ); // write configuration register #endif // Chip select go high to end a flash command CS_High(); if( WaitFlashReady( WriteStatusRegCycleTime ) ) return FlashOperationSuccess; else return FlashTimeOut; } /* * Function: MX25_RDSCUR * Arguments: SecurityReg, 8 bit buffer to store security register value * Description: The RDSCUR instruction is for reading the value of * Security Register bits. * Return Message: FlashOperationSuccess */ ReturnMsg MX25_RDSCUR( uint8_t *SecurityReg ) { uint8_t gDataBuffer; // Chip select go low to start a flash command CS_Low(); //Send command SendByte( FLASH_CMD_RDSCUR, SIO ); gDataBuffer = GetByte( SIO ); // Chip select go high to end a flash command CS_High(); *SecurityReg = gDataBuffer; return FlashOperationSuccess; } /* * Function: MX25_WRSCUR * Arguments: None. * Description: The WRSCUR instruction is for changing the values of * Security Register Bits. * Return Message: FlashIsBusy, FlashOperationSuccess, FlashWriteRegFailed, * FlashTimeOut */ ReturnMsg MX25_WRSCUR( void ) { uint8_t gDataBuffer; // Check flash is busy or not if( IsFlashBusy() ) return FlashIsBusy; // Setting Write Enable Latch bit MX25_WREN(); // Chip select go low to start a flash command CS_Low(); // Write WRSCUR command SendByte( FLASH_CMD_WRSCUR, SIO ); // Chip select go high to end a flash command CS_High(); if( WaitFlashReady( WriteSecuRegCycleTime ) ){ MX25_RDSCUR( &gDataBuffer ); // Check security register LDSO bit if( (gDataBuffer & FLASH_LDSO_MASK) == FLASH_LDSO_MASK ) return FlashOperationSuccess; else return FlashWriteRegFailed; } else return FlashTimeOut; } /* * Function: MX25_RDCR * Arguments: ConfigReg, 8 bit buffer to store Configuration register value * Description: The RDCR instruction is for reading Configuration Register Bits. * Return Message: FlashOperationSuccess */ ReturnMsg MX25_RDCR( uint8_t *ConfigReg ) { uint8_t gDataBuffer; // Chip select go low to start a flash command CS_Low(); // Send command SendByte( FLASH_CMD_RDCR, SIO ); gDataBuffer = GetByte( SIO ); // Chip select go high to end a flash command CS_High(); *ConfigReg = gDataBuffer; return FlashOperationSuccess; } /* * Read Command */ /* * Function: MX25_READ * Arguments: flash_address, 32 bit flash memory address * target_address, buffer address to store returned data * byte_length, length of returned data in byte unit * Description: The READ instruction is for reading data out. * Return Message: FlashAddressInvalid, FlashOperationSuccess */ ReturnMsg MX25_READ( uint32_t flash_address, uint8_t *target_address, uint32_t byte_length ) { uint32_t index; uint8_t addr_4byte_mode; // Check flash address if( flash_address > FlashSize ) return FlashAddressInvalid; // Check 3-byte or 4-byte mode if( IsFlash4Byte() ) addr_4byte_mode = TRUE; // 4-byte mode else addr_4byte_mode = FALSE; // 3-byte mode // Chip select go low to start a flash command CS_Low(); // Write READ command and address SendByte( FLASH_CMD_READ, SIO ); SendFlashAddr( flash_address, SIO, addr_4byte_mode ); // Set a loop to read data into buffer for( index=0; index < byte_length; index++ ) { // Read data one byte at a time *(target_address + index) = GetByte( SIO ); } // Chip select go high to end a flash command CS_High(); return FlashOperationSuccess; } /* * Function: MX25_2READ * Arguments: flash_address, 32 bit flash memory address * target_address, buffer address to store returned data * byte_length, length of returned data in byte unit * Description: The 2READ instruction enable double throughput of Serial * Flash in read mode * Return Message: FlashAddressInvalid, FlashOperationSuccess */ ReturnMsg MX25_2READ( uint32_t flash_address, uint8_t *target_address, uint32_t byte_length ) { uint32_t index; uint8_t addr_4byte_mode; uint8_t dc; // Check flash address if( flash_address > FlashSize ) return FlashAddressInvalid; // Check 3-byte or 4-byte mode if( IsFlash4Byte() ) addr_4byte_mode = TRUE; // 4-byte mode else addr_4byte_mode = FALSE; // 3-byte mode dc = GetDummyCycle( DUMMY_CONF_2READ ); // Chip select go low to start a flash command CS_Low(); // Write 2-I/O Read command and address SendByte( FLASH_CMD_2READ, SIO ); SendFlashAddr( flash_address, DIO, addr_4byte_mode ); InsertDummyCycle( dc ); // Wait 4 dummy cycle // Set a loop to read data into data buffer for( index=0; index < byte_length; index++ ) { *(target_address + index) = GetByte( DIO ); } // Chip select go high to end a flash command CS_High(); return FlashOperationSuccess; } /* * Function: MX25_4READ * Arguments: flash_address, 32 bit flash memory address * target_address, buffer address to store returned data * byte_length, length of returned data in byte unit * Description: The 4READ instruction enable quad throughput of * Serial Flash in read mode. * Return Message: FlashAddressInvalid, FlashQuadNotEnable, FlashOperationSuccess */ ReturnMsg MX25_4READ( uint32_t flash_address, uint8_t *target_address, uint32_t byte_length ) { uint32_t index=0; uint8_t addr_4byte_mode; uint8_t dc; // Check flash address if( flash_address > FlashSize ) return FlashAddressInvalid; #ifndef NO_QE_BIT // Check QE bit if( IsFlashQIO() != TRUE ) return FlashQuadNotEnable; #endif // Check 3-byte or 4-byte mode if( IsFlash4Byte() ) addr_4byte_mode = TRUE; // 4-byte mode else addr_4byte_mode = FALSE; // 3-byte mode // get dummy cycle number dc = GetDummyCycle( DUMMY_CONF_4READ ); // Chip select go low to start a flash command CS_Low(); // Write 4-I/O Read Array command SendByte( FLASH_CMD_4READ, SIO ); SendFlashAddr( flash_address, QIO, addr_4byte_mode ); InsertDummyCycle ( dc ); // Wait 6 or 8 dummy cycle // Set a loop to read data into flash's buffer for( index=0; index < byte_length; index=index + 1 ) { *(target_address + index) = GetByte( QIO ); } // Chip select go high to end a flash command CS_High(); return FlashOperationSuccess; } /* * Function: MX25_DREAD * Arguments: flash_address, 32 bit flash memory address * target_address, buffer address to store returned data * byte_length, length of returned data in byte unit * Description: The DREAD instruction enable double throughput of Serial * Flash in read mode * Return Message: FlashAddressInvalid, FlashOperationSuccess */ ReturnMsg MX25_DREAD( uint32_t flash_address, uint8_t *target_address, uint32_t byte_length ) { uint32_t index; uint8_t addr_4byte_mode; uint8_t dc; // Check flash address if( flash_address > FlashSize ) return FlashAddressInvalid; // Check 3-byte or 4-byte mode if( IsFlash4Byte() ) addr_4byte_mode = TRUE; // 4-byte mode else addr_4byte_mode = FALSE; // 3-byte mode // get dummy cycle number dc = GetDummyCycle( DUMMY_CONF_DREAD ); // Chip select go low to start a flash command CS_Low(); // Write 2-I/O Read command and address SendByte( FLASH_CMD_DREAD, SIO ); SendFlashAddr( flash_address, SIO, addr_4byte_mode ); InsertDummyCycle( dc ); // Wait 8 dummy cycle // Set a loop to read data into data buffer for( index=0; index < byte_length; index++ ) { *(target_address + index) = GetByte( DIO ); } // Chip select go high to end a flash command CS_High(); return FlashOperationSuccess; } /* * Function: MX25_QREAD * Arguments: flash_address, 32 bit flash memory address * target_address, buffer address to store returned data * byte_length, length of returned data in byte unit * Description: The QREAD instruction enable quad throughput of * Serial Flash in read mode. * Return Message: FlashAddressInvalid, FlashQuadNotEnable, FlashOperationSuccess */ ReturnMsg MX25_QREAD( uint32_t flash_address, uint8_t *target_address, uint32_t byte_length ) { uint32_t index=0; uint8_t addr_4byte_mode; uint8_t dc; // Check flash address if( flash_address > FlashSize ) return FlashAddressInvalid; // Check QE bit if( IsFlashQIO() != TRUE ) return FlashQuadNotEnable; // Check 3-byte or 4-byte mode if( IsFlash4Byte() ) addr_4byte_mode = TRUE; // 4-byte mode else addr_4byte_mode = FALSE; // 3-byte mode // get dummy cycle number dc = GetDummyCycle( DUMMY_CONF_QREAD ); // Chip select go low to start a flash command CS_Low(); // Write 4-I/O Read Array command SendByte( FLASH_CMD_QREAD, SIO ); SendFlashAddr( flash_address, SIO, addr_4byte_mode ); InsertDummyCycle ( dc ); // Wait 8 dummy cycle // Set a loop to read data into flash's buffer for( index=0; index < byte_length; index=index+1) { *(target_address + index) = GetByte( QIO ); } // Chip select go high to end a flash command CS_High(); return FlashOperationSuccess; } /* * Function: MX25_FASTREAD * Arguments: flash_address, 32 bit flash memory address * target_address, buffer address to store returned data * byte_length, length of returned data in byte unit * Description: The FASTREAD instruction is for quickly reading data out. * Return Message: FlashAddressInvalid, FlashOperationSuccess */ ReturnMsg MX25_FASTREAD( uint32_t flash_address, uint8_t *target_address, uint32_t byte_length ) { uint32_t index; uint8_t addr_4byte_mode; uint8_t dc; // Check flash address if( flash_address > FlashSize ) return FlashAddressInvalid; // Check 3-byte or 4-byte mode if( IsFlash4Byte() ) addr_4byte_mode = TRUE; // 4-byte mode else addr_4byte_mode = FALSE; // 3-byte mode dc = GetDummyCycle( DUMMY_CONF_FASTREAD ); // Chip select go low to start a flash command CS_Low(); // Write Fast Read command, address and dummy cycle SendByte( FLASH_CMD_FASTREAD, SIO ); SendFlashAddr( flash_address, SIO, addr_4byte_mode ); InsertDummyCycle ( dc ); // Wait dummy cycle // Set a loop to read data into data buffer for( index=0; index < byte_length; index++ ) { *(target_address + index) = GetByte( SIO ); } // Chip select go high to end a flash command CS_High(); return FlashOperationSuccess; } /* * Function: MX25_RDSFDP * Arguments: flash_address, 32 bit flash memory address * target_address, buffer address to store returned data * byte_length, length of returned data in byte unit * Description: RDSFDP can retrieve the operating characteristics, structure * and vendor-specified information such as identifying information, * memory size, operating voltages and timinginformation of device * Return Message: FlashAddressInvalid, FlashOperationSuccess */ ReturnMsg MX25_RDSFDP( uint32_t flash_address, uint8_t *target_address, uint32_t byte_length ) { uint32_t index; uint8_t addr_4byte_mode; // Check flash address if( flash_address > FlashSize ) return FlashAddressInvalid; // Check 3-byte or 4-byte mode if( IsFlash4Byte() ) addr_4byte_mode = TRUE; // 4-byte mode else addr_4byte_mode = FALSE; // 3-byte mode // Chip select go low to start a flash command CS_Low(); // Write Read SFDP command SendByte( FLASH_CMD_RDSFDP, SIO ); SendFlashAddr( flash_address, SIO, addr_4byte_mode ); InsertDummyCycle ( 8 ); // Insert dummy cycle // Set a loop to read data into data buffer for( index=0; index < byte_length; index++ ) { *(target_address + index) = GetByte( SIO ); } // Chip select go high to end a flash command CS_High(); return FlashOperationSuccess; } /* * Program Command */ /* * Function: MX25_WREN * Arguments: None. * Description: The WREN instruction is for setting * Write Enable Latch (WEL) bit. * Return Message: FlashOperationSuccess */ ReturnMsg MX25_WREN( void ) { // Chip select go low to start a flash command CS_Low(); // Write Enable command = 0x06, Setting Write Enable Latch Bit SendByte( FLASH_CMD_WREN, SIO ); // Chip select go high to end a flash command CS_High(); return FlashOperationSuccess; } /* * Function: MX25_WRDI * Arguments: None. * Description: The WRDI instruction is to reset * Write Enable Latch (WEL) bit. * Return Message: FlashOperationSuccess */ ReturnMsg MX25_WRDI( void ) { // Chip select go low to start a flash command CS_Low(); // Write Disable command = 0x04, resets Write Enable Latch Bit SendByte( FLASH_CMD_WRDI, SIO ); CS_High(); return FlashOperationSuccess; } /* * Function: MX25_PP * Arguments: flash_address, 32 bit flash memory address * source_address, buffer address of source data to program * byte_length, byte length of data to programm * Description: The PP instruction is for programming * the memory to be "0". * The device only accept the last 256 byte ( or 32 byte ) to program. * If the page address ( flash_address[7:0] ) reach 0xFF, it will * program next at 0x00 of the same page. * Some products have smaller page size ( 32 byte ) * Return Message: FlashAddressInvalid, FlashIsBusy, FlashOperationSuccess, * FlashTimeOut */ ReturnMsg MX25_PP( uint32_t flash_address, uint8_t *source_address, uint32_t byte_length ) { uint32_t index; uint8_t addr_4byte_mode; // Check flash address if( flash_address > FlashSize ) return FlashAddressInvalid; // Check flash is busy or not if( IsFlashBusy() ) return FlashIsBusy; // Check 3-byte or 4-byte mode if( IsFlash4Byte() ) addr_4byte_mode = TRUE; // 4-byte mode else addr_4byte_mode = FALSE; // 3-byte mode // Setting Write Enable Latch bit MX25_WREN(); // Chip select go low to start a flash command CS_Low(); // Write Page Program command SendByte( FLASH_CMD_PP, SIO ); SendFlashAddr( flash_address, SIO, addr_4byte_mode ); // Set a loop to down load whole page data into flash's buffer // Note: only last 256 byte ( or 32 byte ) will be programmed for( index=0; index < byte_length; index++ ) { SendByte( *(source_address + index), SIO ); } // Chip select go high to end a flash command CS_High(); if( WaitFlashReady( PageProgramCycleTime ) ) return FlashOperationSuccess; else return FlashTimeOut; } /* * Function: MX25_4PP * Arguments: flash_address, 32 bit flash memory address * source_address, buffer address of source data to program * byte_length, byte length of data to programm * Description: The 4PP instruction is for programming * the memory to be "0". * The device only accept the last 256 byte ( one page ) to program. * If the page address ( flash_address[7:0] ) reach 0xFF, it will * program next at 0x00 of the same page. * The different between QPP and 4PP is the IO number during sending address * Return Message: FlashQuadNotEnable, FlashAddressInvalid, FlashIsBusy, * FlashOperationSuccess, FlashTimeOut */ ReturnMsg MX25_4PP( uint32_t flash_address, uint8_t *source_address, uint32_t byte_length ) { uint32_t index; uint8_t addr_4byte_mode; // Check QE bit if( !IsFlashQIO() ) return FlashQuadNotEnable; // Check flash address if( flash_address > FlashSize ) return FlashAddressInvalid; // Check flash is busy or not if( IsFlashBusy() ) return FlashIsBusy; // Check 3-byte or 4-byte mode if( IsFlash4Byte() ) addr_4byte_mode = TRUE; // 4-byte mode else addr_4byte_mode = FALSE; // 3-byte mode // Setting Write Enable Latch bit MX25_WREN(); // Chip select go low to start a flash command CS_Low(); // Write 4-I/O Page Program command SendByte( FLASH_CMD_4PP, SIO ); SendFlashAddr( flash_address, QIO, addr_4byte_mode ); // Send source data to flash. for( index=0; index < byte_length; index++ ) { SendByte( *(source_address + index), QIO ); } // Chip select go high to end a flash command CS_High(); if( WaitFlashReady( PageProgramCycleTime ) ) return FlashOperationSuccess; else return FlashTimeOut; } /* * Erase Command */ /* * Function: MX25_SE * Arguments: flash_address, 32 bit flash memory address * Description: The SE instruction is for erasing the data * of the chosen sector (4KB) to be "1". * Return Message: FlashAddressInvalid, FlashIsBusy, FlashOperationSuccess, * FlashTimeOut */ ReturnMsg MX25_SE( uint32_t flash_address ) { uint8_t addr_4byte_mode; // Check flash address if( flash_address > FlashSize ) return FlashAddressInvalid; // Check flash is busy or not if( IsFlashBusy() ) return FlashIsBusy; // Check 3-byte or 4-byte mode if( IsFlash4Byte() ) addr_4byte_mode = TRUE; // 4-byte mode else addr_4byte_mode = FALSE; // 3-byte mode // Setting Write Enable Latch bit MX25_WREN(); // Chip select go low to start a flash command CS_Low(); //Write Sector Erase command = 0x20; SendByte( FLASH_CMD_SE, SIO ); SendFlashAddr( flash_address, SIO, addr_4byte_mode ); // Chip select go high to end a flash command CS_High(); if( WaitFlashReady( SectorEraseCycleTime ) ) return FlashOperationSuccess; else return FlashTimeOut; } /* * Function: MX25_BE32K * Arguments: flash_address, 32 bit flash memory address * Description: The BE32K instruction is for erasing the data * of the chosen sector (32KB) to be "1". * Return Message: FlashAddressInvalid, FlashIsBusy, FlashOperationSuccess, * FlashTimeOut */ ReturnMsg MX25_BE32K( uint32_t flash_address ) { uint8_t addr_4byte_mode; // Check flash address if( flash_address > FlashSize ) return FlashAddressInvalid; // Check flash is busy or not if( IsFlashBusy() ) return FlashIsBusy; // Check 3-byte or 4-byte mode if( IsFlash4Byte() ) addr_4byte_mode = TRUE; // 4-byte mode else addr_4byte_mode = FALSE; // 3-byte mode // Setting Write Enable Latch bit MX25_WREN(); // Chip select go low to start a flash command CS_Low(); //Write Block Erase32KB command; SendByte( FLASH_CMD_BE32K, SIO ); SendFlashAddr( flash_address, SIO, addr_4byte_mode ); // Chip select go high to end a flash command CS_High(); if( WaitFlashReady( BlockErase32KCycleTime ) ) return FlashOperationSuccess; else return FlashTimeOut; } /* * Function: MX25_BE * Arguments: flash_address, 32 bit flash memory address * Description: The BE instruction is for erasing the data * of the chosen sector (64KB) to be "1". * Return Message: FlashAddressInvalid, FlashIsBusy, FlashOperationSuccess, * FlashTimeOut */ ReturnMsg MX25_BE( uint32_t flash_address ) { uint8_t addr_4byte_mode; // Check flash address if( flash_address > FlashSize ) return FlashAddressInvalid; // Check flash is busy or not if( IsFlashBusy() ) return FlashIsBusy; // Check 3-byte or 4-byte mode if( IsFlash4Byte() ) addr_4byte_mode = TRUE; // 4-byte mode else addr_4byte_mode = FALSE; // 3-byte mode // Setting Write Enable Latch bit MX25_WREN(); // Chip select go low to start a flash command CS_Low(); //Write Block Erase command = 0xD8; SendByte( FLASH_CMD_BE, SIO ); SendFlashAddr( flash_address, SIO, addr_4byte_mode ); // Chip select go high to end a flash command CS_High(); if( WaitFlashReady( BlockEraseCycleTime ) ) return FlashOperationSuccess; else return FlashTimeOut; } /* * Function: MX25_CE * Arguments: None. * Description: The CE instruction is for erasing the data * of the whole chip to be "1". * Return Message: FlashIsBusy, FlashOperationSuccess, FlashTimeOut */ ReturnMsg MX25_CE( void ) { // Check flash is busy or not if( IsFlashBusy() ) return FlashIsBusy; // Setting Write Enable Latch bit MX25_WREN(); // Chip select go low to start a flash command CS_Low(); //Write Chip Erase command = 0x60; SendByte( FLASH_CMD_CE, SIO ); // Chip select go high to end a flash command CS_High(); if( WaitFlashReady( ChipEraseCycleTime ) ) return FlashOperationSuccess; else return FlashTimeOut; } /* * Mode setting Command */ /* * Function: MX25_DP * Arguments: None. * Description: The DP instruction is for setting the * device on the minimizing the power consumption. * Return Message: FlashOperationSuccess */ ReturnMsg MX25_DP( void ) { // Wake up flash in case the device is in deep power down mode already. CS_Low(); InsertDummyCycle ( 20*8 ); // wait for tCRDP=20us (20 x 8 bit / 8Mbps) CS_High(); InsertDummyCycle ( 30*8 ); // wait for tRDP=35us (20 x 8 bit / 8Mbps) InsertDummyCycle ( 5*8 ); // Chip select go low to start a flash command CS_Low(); // Deep Power Down Mode command SendByte( FLASH_CMD_DP, SIO ); // Chip select go high to end a flash command CS_High(); return FlashOperationSuccess; } /* * Function: MX25_ENSO * Arguments: None. * Description: The ENSO instruction is for entering the secured OTP mode. * Return Message: FlashOperationSuccess */ ReturnMsg MX25_ENSO( void ) { // Chip select go low to start a flash command CS_Low(); // Write ENSO command SendByte( FLASH_CMD_ENSO, SIO ); // Chip select go high to end a flash command CS_High(); return FlashOperationSuccess; } /* * Function: MX25_EXSO * Arguments: None. * Description: The EXSO instruction is for exiting the secured OTP mode. * Return Message: FlashOperationSuccess */ ReturnMsg MX25_EXSO( void ) { // Chip select go low to start a flash command CS_Low(); // Write EXSO command = 0xC1 SendByte( FLASH_CMD_EXSO, SIO ); // Chip select go high to end a flash command CS_High(); return FlashOperationSuccess; } /* * Function: MX25_SBL * Arguments: burstconfig, burst length configuration * Description: To set the Burst length * Return Message: FlashOperationSuccess */ ReturnMsg MX25_SBL( uint8_t burstconfig ) { // Chip select go low to start a flash command CS_Low(); // Send SBL command and config data SendByte( FLASH_CMD_SBL, SIO ); SendByte( burstconfig, SIO ); // Chip select go high to end a flash command CS_High(); return FlashOperationSuccess; } /* * Reset setting Command */ /* * Function: MX25_RSTEN * Arguments: None. * Description: Enable RST command * Return Message: FlashOperationSuccess */ ReturnMsg MX25_RSTEN( void ) { // Chip select go low to start a flash command CS_Low(); // Write RSTEN command SendByte( FLASH_CMD_RSTEN, SIO ); // Chip select go high to end a flash command CS_High(); return FlashOperationSuccess; } /* * Function: MX25_RST * Arguments: fsptr, pointer of flash status structure * Description: The RST instruction is used as a system (software) reset that * puts the device in normal operating Ready mode. * Return Message: FlashOperationSuccess */ ReturnMsg MX25_RST( FlashStatus *fsptr ) { // Chip select go low to start a flash command CS_Low(); // Write RST command = 0x99 SendByte( FLASH_CMD_RST, SIO ); // Chip select go high to end a flash command CS_High(); // Reset current state fsptr->ArrangeOpt = FALSE; fsptr->ModeReg = 0x00; return FlashOperationSuccess; } /* * Security Command */ /* * Suspend/Resume Command */ /* * Function: MX25_PGM_ERS_S * Arguments: None * Description: The PGM_ERS_S suspend Sector-Erase, Block-Erase or * Page-Program operations and conduct other operations. * Return Message: FlashOperationSuccess */ ReturnMsg MX25_PGM_ERS_S( void ) { // Chip select go low to start a flash command CS_Low(); // Send program/erase suspend command SendByte( FLASH_CMD_PGM_ERS_S, SIO ); // Chip select go high to end a flash command CS_High(); return FlashOperationSuccess; } /* * Function: MX25_PGM_ERS_R * Arguments: None * Description: The PGM_ERS_R resume Sector-Erase, Block-Erase or * Page-Program operations. * Return Message: FlashOperationSuccess */ ReturnMsg MX25_PGM_ERS_R( void ) { // Chip select go low to start a flash command CS_Low(); // Send resume command SendByte( FLASH_CMD_PGM_ERS_R, SIO ); // Chip select go high to end a flash command CS_High(); return FlashOperationSuccess; } /* * Function: MX25_NOP * Arguments: None. * Description: The NOP instruction is null operation of flash. * Return Message: FlashOperationSuccess */ ReturnMsg MX25_NOP( void ) { // Chip select go low to start a flash command CS_Low(); // Write NOP command = 0x00 SendByte( FLASH_CMD_NOP, SIO ); // Chip select go high to end a flash command CS_High(); return FlashOperationSuccess; } #endif //MX25_USART |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/hardware/kit/common/drivers/mx25flash_spi.h.
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/***************************************************************************//** * # License * * The licensor of this software is Silicon Laboratories Inc. Your use of this * software is governed by the terms of Silicon Labs Master Software License * Agreement (MSLA) available at * www.silabs.com/about-us/legal/master-software-license-agreement. This * software is Third Party Software licensed by Silicon Labs from a third party * and is governed by the sections of the MSLA applicable to Third Party * Software and the additional terms set forth below. * ******************************************************************************/ /* * COPYRIGHT (c) 2010-2015 MACRONIX INTERNATIONAL CO., LTD * SPI Flash Low Level Driver (LLD) Sample Code * * Flash device information define * * $Id: MX25_DEF.h,v 1.420 2015/04/09 03:26:05 mxclldb1 Exp $ */ #ifndef __MX25_DEF_H__ #define __MX25_DEF_H__ #include <stdbool.h> #include <stdint.h> #ifdef HAL_CONFIG #include "mx25flashhalconfig.h" #else #include "mx25flash_config.h" #endif #define MX25R8035F /* Note: Synchronous IO : MCU will polling WIP bit after sending prgram/erase command Non-synchronous IO : MCU can do other operation after sending prgram/erase command Default is synchronous IO */ //#define NON_SYNCHRONOUS_IO // variable #define TRUE 1 #define FALSE 0 #define BYTE_LEN 8 #define IO_MASK 0x80 #define HALF_WORD_MASK 0x0000ffff /* Flash Related Parameter Define */ #define Block_Offset 0x10000 // 64K Block size #define Block32K_Offset 0x8000 // 32K Block size #define Sector_Offset 0x1000 // 4K Sector size #define Page_Offset 0x0100 // 256 Byte Page size #define Page32_Offset 0x0020 // 32 Byte Page size (some products have smaller page size) #define Block_Num (FlashSize / Block_Offset) // Flash control register mask define // status register #define FLASH_WIP_MASK 0x01 #define FLASH_LDSO_MASK 0x02 #define FLASH_QE_MASK 0x40 // security register #define FLASH_OTPLOCK_MASK 0x03 #define FLASH_4BYTE_MASK 0x04 #define FLASH_WPSEL_MASK 0x80 // configuration reigster #define FLASH_DC_MASK 0x80 #define FLASH_DC_2BIT_MASK 0xC0 // other #define BLOCK_PROTECT_MASK 0xff #define BLOCK_LOCK_MASK 0x01 /* System Information Define */ #define CLK_PERIOD 26 // unit: ns #define Min_Cycle_Per_Inst 1 // cycle count of one instruction #define One_Loop_Inst 10 // instruction count of one loop (estimate) /* Flash ID, Timing Information Define (The following information could get from device specification) */ #ifdef MX25R8035F #define FlashID 0xc22814 #define ElectronicID 0x14 #define RESID0 0xc214 #define RESID1 0x14c2 #define FlashSize 0x100000 // 1 MB #define CE_period 15625000 // tCE / ( CLK_PERIOD * Min_Cycle_Per_Inst *One_Loop_Inst) #define tW 40000000 // 40ms #define tDP 10000 // 10us #define tBP 100000 // 100us #define tPP 10000000 // 10ms #define tSE 240000000 // 240ms #define tBE32 1750000000 // 1.75s #define tBE 3500000000 // 3.5s #define tPUW 10000000 // 10ms #define tWSR tBP // Support I/O mode #define SIO 0 #define DIO 1 #define QIO 2 #endif // dummy cycle configration #ifdef DUMMY_CONF_2 #define DUMMY_CONF_2READ 0x08040804 #define DUMMY_CONF_4READ 0x0A080406 #define DUMMY_CONF_FASTREAD 0x08080808 #define DUMMY_CONF_DREAD 0x08080808 #define DUMMY_CONF_QREAD 0x08080808 #else #define DUMMY_CONF_2READ 0x0A080604 #define DUMMY_CONF_4READ 0x0A080406 #define DUMMY_CONF_FASTREAD 0x0A080608 #define DUMMY_CONF_DREAD 0x0A080608 #define DUMMY_CONF_QREAD 0x0A080608 #endif // Flash information define #define WriteStatusRegCycleTime tW / (CLK_PERIOD * Min_Cycle_Per_Inst * One_Loop_Inst) #define PageProgramCycleTime tPP / (CLK_PERIOD * Min_Cycle_Per_Inst * One_Loop_Inst) #define SectorEraseCycleTime tSE / (CLK_PERIOD * Min_Cycle_Per_Inst * One_Loop_Inst) #define BlockEraseCycleTime tBE / (CLK_PERIOD * Min_Cycle_Per_Inst * One_Loop_Inst) #define ChipEraseCycleTime CE_period #define FlashFullAccessTime tPUW / (CLK_PERIOD * Min_Cycle_Per_Inst * One_Loop_Inst) #ifdef tBP #define ByteProgramCycleTime tBP / (CLK_PERIOD * Min_Cycle_Per_Inst * One_Loop_Inst) #endif #ifdef tWSR #define WriteSecuRegCycleTime tWSR / (CLK_PERIOD * Min_Cycle_Per_Inst * One_Loop_Inst) #endif #ifdef tBE32 #define BlockErase32KCycleTime tBE32 / (CLK_PERIOD * Min_Cycle_Per_Inst * One_Loop_Inst) #endif #ifdef tWREAW #define WriteExtRegCycleTime tWREAW / (CLK_PERIOD * Min_Cycle_Per_Inst * One_Loop_Inst) #endif /*** MX25 series command hex code definition ***/ //ID comands #define FLASH_CMD_RDID 0x9F //RDID (Read Identification) #define FLASH_CMD_RES 0xAB //RES (Read Electronic ID) #define FLASH_CMD_REMS 0x90 //REMS (Read Electronic & Device ID) //Register comands #define FLASH_CMD_WRSR 0x01 //WRSR (Write Status Register) #define FLASH_CMD_RDSR 0x05 //RDSR (Read Status Register) #define FLASH_CMD_WRSCUR 0x2F //WRSCUR (Write Security Register) #define FLASH_CMD_RDSCUR 0x2B //RDSCUR (Read Security Register) #define FLASH_CMD_RDCR 0x15 //RDCR (Read Configuration Register) //READ comands #define FLASH_CMD_READ 0x03 //READ (1 x I/O) #define FLASH_CMD_2READ 0xBB //2READ (2 x I/O) #define FLASH_CMD_4READ 0xEB //4READ (4 x I/O) #define FLASH_CMD_FASTREAD 0x0B //FAST READ (Fast read data) #define FLASH_CMD_DREAD 0x3B //DREAD (1In/2 Out fast read) #define FLASH_CMD_QREAD 0x6B //QREAD (1In/4 Out fast read) #define FLASH_CMD_RDSFDP 0x5A //RDSFDP (Read SFDP) //Program comands #define FLASH_CMD_WREN 0x06 //WREN (Write Enable) #define FLASH_CMD_WRDI 0x04 //WRDI (Write Disable) #define FLASH_CMD_PP 0x02 //PP (page program) #define FLASH_CMD_4PP 0x38 //4PP (Quad page program) //Erase comands #define FLASH_CMD_SE 0x20 //SE (Sector Erase) #define FLASH_CMD_BE32K 0x52 //BE32K (Block Erase 32kb) #define FLASH_CMD_BE 0xD8 //BE (Block Erase) #define FLASH_CMD_CE 0x60 //CE (Chip Erase) hex code: 60 or C7 //Mode setting comands #define FLASH_CMD_DP 0xB9 //DP (Deep Power Down) #define FLASH_CMD_ENSO 0xB1 //ENSO (Enter Secured OTP) #define FLASH_CMD_EXSO 0xC1 //EXSO (Exit Secured OTP) #ifdef SBL_CMD_0x77 #define FLASH_CMD_SBL 0x77 //SBL (Set Burst Length) new: 0x77 #else #define FLASH_CMD_SBL 0xC0 //SBL (Set Burst Length) Old: 0xC0 #endif //Reset comands #define FLASH_CMD_RSTEN 0x66 //RSTEN (Reset Enable) #define FLASH_CMD_RST 0x99 //RST (Reset Memory) //Security comands #ifdef LCR_CMD_0xDD_0xD5 #else #endif //Suspend/Resume comands #define FLASH_CMD_PGM_ERS_S 0xB0 //PGM/ERS Suspend (Suspends Program/Erase) #define FLASH_CMD_PGM_ERS_R 0x30 //PGM/ERS Erase (Resumes Program/Erase) #define FLASH_CMD_NOP 0x00 //NOP (No Operation) // Return Message typedef enum { FlashOperationSuccess, FlashWriteRegFailed, FlashTimeOut, FlashIsBusy, FlashQuadNotEnable, FlashAddressInvalid }ReturnMsg; // Flash status structure define struct sFlashStatus{ /* Mode Register: * Bit Description * ------------------------- * 7 RYBY enable * 6 Reserved * 5 Reserved * 4 Reserved * 3 Reserved * 2 Reserved * 1 Parallel mode enable * 0 QPI mode enable */ uint8_t ModeReg; bool ArrangeOpt; }; typedef struct sFlashStatus FlashStatus; void MX25_init( void ); void MX25_deinit( void ); /* Flash commands */ ReturnMsg MX25_RDID( uint32_t *Identification ); ReturnMsg MX25_RES( uint8_t *ElectricIdentification ); ReturnMsg MX25_REMS( uint16_t *REMS_Identification, FlashStatus *fsptr ); ReturnMsg MX25_RDSR( uint8_t *StatusReg ); #ifdef SUPPORT_WRSR_CR ReturnMsg MX25_WRSR( uint16_t UpdateValue ); #else ReturnMsg MX25_WRSR( uint8_t UpdateValue ); #endif ReturnMsg MX25_RDSCUR( uint8_t *SecurityReg ); ReturnMsg MX25_WRSCUR( void ); ReturnMsg MX25_RDCR( uint8_t *ConfigReg ); ReturnMsg MX25_READ( uint32_t flash_address, uint8_t *target_address, uint32_t byte_length ); ReturnMsg MX25_2READ( uint32_t flash_address, uint8_t *target_address, uint32_t byte_length ); ReturnMsg MX25_4READ( uint32_t flash_address, uint8_t *target_address, uint32_t byte_length ); ReturnMsg MX25_FASTREAD( uint32_t flash_address, uint8_t *target_address, uint32_t byte_length ); ReturnMsg MX25_DREAD( uint32_t flash_address, uint8_t *target_address, uint32_t byte_length ); ReturnMsg MX25_QREAD( uint32_t flash_address, uint8_t *target_address, uint32_t byte_length ); ReturnMsg MX25_RDSFDP( uint32_t flash_address, uint8_t *target_address, uint32_t byte_length ); ReturnMsg MX25_WREN( void ); ReturnMsg MX25_WRDI( void ); ReturnMsg MX25_PP( uint32_t flash_address, uint8_t *source_address, uint32_t byte_length ); ReturnMsg MX25_4PP( uint32_t flash_address, uint8_t *source_address, uint32_t byte_length ); ReturnMsg MX25_SE( uint32_t flash_address ); ReturnMsg MX25_BE32K( uint32_t flash_address ); ReturnMsg MX25_BE( uint32_t flash_address ); ReturnMsg MX25_CE( void ); ReturnMsg MX25_DP( void ); ReturnMsg MX25_ENSO( void ); ReturnMsg MX25_EXSO( void ); ReturnMsg MX25_SBL( uint8_t burstconfig ); ReturnMsg MX25_RSTEN( void ); ReturnMsg MX25_RST( FlashStatus *fsptr ); ReturnMsg MX25_PGM_ERS_S( void ); ReturnMsg MX25_PGM_ERS_R( void ); ReturnMsg MX25_NOP( void ); #endif /* end of __MX25_DEF_H__ */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/hardware/kit/common/drivers/retargetio.c.
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/***************************************************************************//** * @file * @brief Provide stdio retargeting for all supported toolchains. ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * The licensor of this software is Silicon Laboratories Inc. Your use of this * software is governed by the terms of Silicon Labs Master Software License * Agreement (MSLA) available at * www.silabs.com/about-us/legal/master-software-license-agreement. This * software is distributed to you in Source Code format and is governed by the * sections of the MSLA applicable to Source Code. * ******************************************************************************/ /***************************************************************************//** * @addtogroup kitdrv * @{ ******************************************************************************/ /***************************************************************************//** * @addtogroup RetargetIo * @{ ******************************************************************************/ extern int RETARGET_ReadChar(void); extern int RETARGET_WriteChar(char c); #if !defined(__CROSSWORKS_ARM) && defined(__GNUC__) #include <sys/stat.h> #include <stdio.h> #include <stdlib.h> #include <string.h> #include "em_device.h" /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ int fileno(FILE *); /** @endcond */ int _close(int file); int _fstat(int file, struct stat *st); int _isatty(int file); int _lseek(int file, int ptr, int dir); int _read(int file, char *ptr, int len); caddr_t _sbrk(int incr); int _write(int file, const char *ptr, int len); extern char _end; /**< Defined by the linker */ /**************************************************************************//** * @brief * Close a file. * * @param[in] file * File you want to close. * * @return * Returns 0 when the file is closed. *****************************************************************************/ int _close(int file) { (void) file; return 0; } /**************************************************************************//** * @brief Exit the program. * @param[in] status The value to return to the parent process as the * exit status (not used). *****************************************************************************/ void _exit(int status) { (void) status; while (1) { } /* Hang here forever... */ } /**************************************************************************//** * @brief * Status of an open file. * * @param[in] file * Check status for this file. * * @param[in] st * Status information. * * @return * Returns 0 when st_mode is set to character special. *****************************************************************************/ int _fstat(int file, struct stat *st) { (void) file; st->st_mode = S_IFCHR; return 0; } /**************************************************************************//** * @brief Get process ID. *****************************************************************************/ int _getpid(void) { return 1; } /**************************************************************************//** * @brief * Query whether output stream is a terminal. * * @param[in] file * Descriptor for the file. * * @return * Returns 1 when query is done. *****************************************************************************/ int _isatty(int file) { (void) file; return 1; } /**************************************************************************//** * @brief Send signal to process. * @param[in] pid Process id (not used). * @param[in] sig Signal to send (not used). *****************************************************************************/ int _kill(int pid, int sig) { (void)pid; (void)sig; return -1; } /**************************************************************************//** * @brief * Set position in a file. * * @param[in] file * Descriptor for the file. * * @param[in] ptr * Poiter to the argument offset. * * @param[in] dir * Directory whence. * * @return * Returns 0 when position is set. *****************************************************************************/ int _lseek(int file, int ptr, int dir) { (void) file; (void) ptr; (void) dir; return 0; } /**************************************************************************//** * @brief * Read from a file. * * @param[in] file * Descriptor for the file you want to read from. * * @param[in] ptr * Pointer to the chacaters that are beeing read. * * @param[in] len * Number of characters to be read. * * @return * Number of characters that have been read. *****************************************************************************/ int _read(int file, char *ptr, int len) { int c, rxCount = 0; (void) file; while (len--) { if ((c = RETARGET_ReadChar()) != -1) { *ptr++ = c; rxCount++; } else { break; } } if (rxCount <= 0) { return -1; /* Error exit */ } return rxCount; } /**************************************************************************//** * @brief * Increase heap. * * @param[in] incr * Number of bytes you want increment the program's data space. * * @return * Rsturns a pointer to the start of the new area. *****************************************************************************/ caddr_t _sbrk(int incr) { static char *heap_end; char *prev_heap_end; if (heap_end == 0) { heap_end = &_end; } prev_heap_end = heap_end; heap_end += incr; return (caddr_t) prev_heap_end; } /**************************************************************************//** * @brief * Write to a file. * * @param[in] file * Descriptor for the file you want to write to. * * @param[in] ptr * Pointer to the text you want to write * * @param[in] len * Number of characters to be written. * * @return * Number of characters that have been written. *****************************************************************************/ int _write(int file, const char *ptr, int len) { int txCount; (void) file; for (txCount = 0; txCount < len; txCount++) { RETARGET_WriteChar(*ptr++); } return len; } #endif /* !defined( __CROSSWORKS_ARM ) && defined( __GNUC__ ) */ #if defined(__ICCARM__) /******************* * * Copyright 1998-2003 IAR Systems. All rights reserved. * * $Revision: 38614 $ * * This is a template implementation of the "__write" function used by * the standard library. Replace it with a system-specific * implementation. * * The "__write" function should output "size" number of bytes from * "buffer" in some application-specific way. It should return the * number of characters written, or _LLIO_ERROR on failure. * * If "buffer" is zero then __write should perform flushing of * internal buffers, if any. In this case "handle" can be -1 to * indicate that all handles should be flushed. * * The template implementation below assumes that the application * provides the function "MyLowLevelPutchar". It should return the * character written, or -1 on failure. * ********************/ #include <yfuns.h> #include <stdint.h> #include "em_common.h" _STD_BEGIN /**************************************************************************//** * @brief Transmit buffer to USART1 * @param buffer Array of characters to send * @param nbytes Number of bytes to transmit * @return Number of bytes sent *****************************************************************************/ static int TxBuf(uint8_t *buffer, int nbytes) { int i; for (i = 0; i < nbytes; i++) { RETARGET_WriteChar(*buffer++); } return nbytes; } /* * If the __write implementation uses internal buffering, uncomment * the following line to ensure that we are called with "buffer" as 0 * (i.e. flush) when the application terminates. */ size_t __write(int handle, const unsigned char * buffer, size_t size) { /* Remove the #if #endif pair to enable the implementation */ size_t nChars = 0; if (buffer == 0) { /* * This means that we should flush internal buffers. Since we * don't we just return. (Remember, "handle" == -1 means that all * handles should be flushed.) */ return 0; } /* This template only writes to "standard out" and "standard err", * for all other file handles it returns failure. */ if (handle != _LLIO_STDOUT && handle != _LLIO_STDERR) { return _LLIO_ERROR; } /* Hook into USART1 transmit function here */ if (TxBuf((uint8_t *) buffer, size) != size) { return _LLIO_ERROR; } else { nChars = size; } return nChars; } size_t __read(int handle, unsigned char * buffer, size_t size) { /* Remove the #if #endif pair to enable the implementation */ int nChars = 0; /* This template only reads from "standard in", for all other file * handles it returns failure. */ if (handle != _LLIO_STDIN) { return _LLIO_ERROR; } for (/* Empty */; size > 0; --size) { int c = RETARGET_ReadChar(); if (c < 0) { break; } *buffer++ = c; ++nChars; } return nChars; } _STD_END #endif /* defined( __ICCARM__ ) */ #if defined(__CROSSWORKS_ARM) /* Pass each of these function straight to the USART */ int __putchar(int ch) { return(RETARGET_WriteChar(ch)); } int __getchar(void) { return(RETARGET_ReadChar()); } #endif /* defined( __CROSSWORKS_ARM ) */ #if defined(__CC_ARM) /******************************************************************************/ /* RETARGET.C: 'Retarget' layer for target-dependent low-level functions */ /******************************************************************************/ /* This file is part of the uVision/ARM development tools. */ /* Copyright (c) 2005-2006 Keil Software. All rights reserved. */ /* This software may only be used under the terms of a valid, current, */ /* end user licence from KEIL for a compatible version of KEIL software */ /* development tools. Nothing else gives you the right to use this software. */ /******************************************************************************/ #include <stdio.h> /* #pragma import(__use_no_semihosting_swi) */ struct __FILE{ int handle; }; /**Standard output stream*/ FILE __stdout; /**************************************************************************//** * @brief * Writes character to file * * @param[in] f * File * * @param[in] ch * Character * * @return * Written character *****************************************************************************/ int fputc(int ch, FILE *f) { return(RETARGET_WriteChar(ch)); } /**************************************************************************//** * @brief * Reads character from file * * @param[in] f * File * * @return * Character *****************************************************************************/ int fgetc(FILE *f) { return(RETARGET_ReadChar()); } /**************************************************************************//** * @brief * Tests the error indicator for the stream pointed * to by file * * @param[in] f * File * * @return * Returns non-zero if it is set *****************************************************************************/ int ferror(FILE *f) { /* Your implementation of ferror */ return EOF; } /**************************************************************************//** * @brief * Writes a character to the console * * @param[in] ch * Input character *****************************************************************************/ void _ttywrch(int ch) { RETARGET_WriteChar(ch); } /**************************************************************************//** * @brief * Library exit function. This function is called if stack * overflow occurs. * * @param[in] return_code * Return code *****************************************************************************/ void _sys_exit(int return_code) { label: goto label;/* endless loop */ } #endif /* defined( __CC_ARM ) */ /** @} (end group RetargetIo) */ /** @} (end group kitdrv) */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/hardware/kit/common/drivers/retargetserial.c.
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/***************************************************************************//** * @file * @brief Provide stdio retargeting to USART/UART or LEUART. ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * The licensor of this software is Silicon Laboratories Inc. Your use of this * software is governed by the terms of Silicon Labs Master Software License * Agreement (MSLA) available at * www.silabs.com/about-us/legal/master-software-license-agreement. This * software is distributed to you in Source Code format and is governed by the * sections of the MSLA applicable to Source Code. * ******************************************************************************/ #include <stdio.h> #include "em_device.h" #include "em_cmu.h" #include "em_core.h" #include "em_gpio.h" #include "retargetserial.h" #if defined(HAL_CONFIG) #include "retargetserialhalconfig.h" #else #include "retargetserialconfig.h" #endif /***************************************************************************//** * @addtogroup kitdrv * @{ ******************************************************************************/ /***************************************************************************//** * @addtogroup RetargetIo * @{ ******************************************************************************/ #if defined(RETARGET_USART) #include "em_usart.h" #endif #if defined(RETARGET_LEUART) #include "em_leuart.h" #endif /* Receive buffer */ #ifndef RXBUFSIZE #define RXBUFSIZE 8 /**< Buffer size for RX */ #endif static volatile int rxReadIndex = 0; /**< Index in buffer to be read */ static volatile int rxWriteIndex = 0; /**< Index in buffer to be written to */ static volatile int rxCount = 0; /**< Keeps track of how much data which are stored in the buffer */ static volatile uint8_t rxBuffer[RXBUFSIZE]; /**< Buffer to store data */ static uint8_t LFtoCRLF = 0; /**< LF to CRLF conversion disabled */ static bool initialized = false; /**< Initialize UART/LEUART */ /**************************************************************************//** * @brief Disable RX interrupt *****************************************************************************/ static void disableRxInterrupt() { #if defined(RETARGET_USART) USART_IntDisable(RETARGET_UART, USART_IF_RXDATAV); #else LEUART_IntDisable(RETARGET_UART, LEUART_IF_RXDATAV); #endif } /**************************************************************************//** * @brief Enable RX interrupt *****************************************************************************/ static void enableRxInterrupt() { #if defined(RETARGET_USART) USART_IntEnable(RETARGET_UART, USART_IF_RXDATAV); #else LEUART_IntEnable(RETARGET_UART, LEUART_IF_RXDATAV); #endif } /**************************************************************************//** * @brief UART/LEUART IRQ Handler *****************************************************************************/ void RETARGET_IRQ_NAME(void) { #if defined(RETARGET_USART) if (RETARGET_UART->STATUS & USART_STATUS_RXDATAV) { #else if (RETARGET_UART->IF & LEUART_IF_RXDATAV) { #endif if (rxCount < RXBUFSIZE) { /* There is room for data in the RX buffer so we store the data. */ rxBuffer[rxWriteIndex] = RETARGET_RX(RETARGET_UART); rxWriteIndex++; rxCount++; if (rxWriteIndex == RXBUFSIZE) { rxWriteIndex = 0; } } else { /* The RX buffer is full so we must wait for the RETARGET_ReadChar() * function to make some more room in the buffer. RX interrupts are * disabled to let the ISR exit. The RX interrupt will be enabled in * RETARGET_ReadChar(). */ disableRxInterrupt(); } } } /**************************************************************************//** * @brief UART/LEUART toggle LF to CRLF conversion * @param on If non-zero, automatic LF to CRLF conversion will be enabled *****************************************************************************/ void RETARGET_SerialCrLf(int on) { if (on) { LFtoCRLF = 1; } else { LFtoCRLF = 0; } } /**************************************************************************//** * @brief Intializes UART/LEUART *****************************************************************************/ void RETARGET_SerialInit(void) { /* Enable peripheral clocks */ #if defined(_CMU_HFPERCLKEN0_MASK) CMU_ClockEnable(cmuClock_HFPER, true); #endif /* Configure GPIO pins */ CMU_ClockEnable(cmuClock_GPIO, true); /* To avoid false start, configure output as high */ GPIO_PinModeSet(RETARGET_TXPORT, RETARGET_TXPIN, gpioModePushPull, 1); GPIO_PinModeSet(RETARGET_RXPORT, RETARGET_RXPIN, gpioModeInputPull, 1); #if defined(RETARGET_USART) USART_TypeDef *usart = RETARGET_UART; USART_InitAsync_TypeDef init = USART_INITASYNC_DEFAULT; /* Enable DK RS232/UART switch */ RETARGET_PERIPHERAL_ENABLE(); CMU_ClockEnable(RETARGET_CLK, true); /* Configure USART for basic async operation */ init.enable = usartDisable; USART_InitAsync(usart, &init); #if defined(GPIO_USART_ROUTEEN_TXPEN) /* Enable pins at correct UART/USART location. */ GPIO->USARTROUTE[RETARGET_UART_INDEX].ROUTEEN = GPIO_USART_ROUTEEN_TXPEN | GPIO_USART_ROUTEEN_RXPEN; GPIO->USARTROUTE[RETARGET_UART_INDEX].TXROUTE = (RETARGET_TXPORT << _GPIO_USART_TXROUTE_PORT_SHIFT) | (RETARGET_TXPIN << _GPIO_USART_TXROUTE_PIN_SHIFT); GPIO->USARTROUTE[RETARGET_UART_INDEX].RXROUTE = (RETARGET_RXPORT << _GPIO_USART_RXROUTE_PORT_SHIFT) | (RETARGET_RXPIN << _GPIO_USART_RXROUTE_PIN_SHIFT); #else /* Enable pins at correct UART/USART location. */ #if defined(USART_ROUTEPEN_RXPEN) usart->ROUTEPEN = USART_ROUTEPEN_RXPEN | USART_ROUTEPEN_TXPEN; usart->ROUTELOC0 = (usart->ROUTELOC0 & ~(_USART_ROUTELOC0_TXLOC_MASK | _USART_ROUTELOC0_RXLOC_MASK) ) | (RETARGET_TX_LOCATION << _USART_ROUTELOC0_TXLOC_SHIFT) | (RETARGET_RX_LOCATION << _USART_ROUTELOC0_RXLOC_SHIFT); #else usart->ROUTE = USART_ROUTE_RXPEN | USART_ROUTE_TXPEN | RETARGET_LOCATION; #endif #endif /* Clear previous RX interrupts */ USART_IntClear(RETARGET_UART, USART_IF_RXDATAV); NVIC_ClearPendingIRQ(RETARGET_IRQn); /* Enable RX interrupts */ USART_IntEnable(RETARGET_UART, USART_IF_RXDATAV); NVIC_EnableIRQ(RETARGET_IRQn); /* Finally enable it */ USART_Enable(usart, usartEnable); #else LEUART_TypeDef *leuart = RETARGET_UART; LEUART_Init_TypeDef init = LEUART_INIT_DEFAULT; /* Enable DK LEUART/RS232 switch */ RETARGET_PERIPHERAL_ENABLE(); /* Enable CORE LE clock in order to access LE modules */ CMU_ClockEnable(cmuClock_CORELE, true); #if defined(RETARGET_VCOM) /* Select HFXO/2 for LEUARTs (and wait for it to stabilize) */ #if defined(_CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2) CMU_ClockSelectSet(cmuClock_LFB, cmuSelect_CORELEDIV2); #else CMU_ClockSelectSet(cmuClock_LFB, cmuSelect_HFCLKLE); #endif #else /* Select LFXO for LEUARTs (and wait for it to stabilize) */ CMU_ClockSelectSet(cmuClock_LFB, cmuSelect_LFXO); #endif CMU_ClockEnable(RETARGET_CLK, true); /* Do not prescale clock */ CMU_ClockDivSet(RETARGET_CLK, cmuClkDiv_1); /* Configure LEUART */ init.enable = leuartDisable; #if defined(RETARGET_VCOM) init.baudrate = 115200; #endif LEUART_Init(leuart, &init); /* Enable pins at default location */ #if defined(LEUART_ROUTEPEN_RXPEN) leuart->ROUTEPEN = USART_ROUTEPEN_RXPEN | USART_ROUTEPEN_TXPEN; leuart->ROUTELOC0 = (leuart->ROUTELOC0 & ~(_LEUART_ROUTELOC0_TXLOC_MASK | _LEUART_ROUTELOC0_RXLOC_MASK) ) | (RETARGET_TX_LOCATION << _LEUART_ROUTELOC0_TXLOC_SHIFT) | (RETARGET_RX_LOCATION << _LEUART_ROUTELOC0_RXLOC_SHIFT); #else leuart->ROUTE = LEUART_ROUTE_RXPEN | LEUART_ROUTE_TXPEN | RETARGET_LOCATION; #endif /* Clear previous RX interrupts */ LEUART_IntClear(RETARGET_UART, LEUART_IF_RXDATAV); NVIC_ClearPendingIRQ(RETARGET_IRQn); /* Enable RX interrupts */ LEUART_IntEnable(RETARGET_UART, LEUART_IF_RXDATAV); NVIC_EnableIRQ(RETARGET_IRQn); /* Finally enable it */ LEUART_Enable(leuart, leuartEnable); #endif #if !defined(__CROSSWORKS_ARM) && defined(__GNUC__) setvbuf(stdout, NULL, _IONBF, 0); /*Set unbuffered mode for stdout (newlib)*/ #endif initialized = true; } /**************************************************************************//** * @brief Receive a byte from USART/LEUART and put into global buffer * @return -1 on failure, or positive character integer on sucesss *****************************************************************************/ int RETARGET_ReadChar(void) { int c = -1; CORE_DECLARE_IRQ_STATE; if (initialized == false) { RETARGET_SerialInit(); } CORE_ENTER_ATOMIC(); if (rxCount > 0) { c = rxBuffer[rxReadIndex]; rxReadIndex++; if (rxReadIndex == RXBUFSIZE) { rxReadIndex = 0; } rxCount--; /* Unconditionally enable the RX interrupt. RX interrupts are disabled when * a buffer full condition is entered. This way flow control can be handled * automatically by the hardware. */ enableRxInterrupt(); } CORE_EXIT_ATOMIC(); return c; } /**************************************************************************//** * @brief Transmit single byte to USART/LEUART * @param c Character to transmit * @return Transmitted character *****************************************************************************/ int RETARGET_WriteChar(char c) { if (initialized == false) { RETARGET_SerialInit(); } /* Add CR or LF to CRLF if enabled */ if (LFtoCRLF && (c == '\n')) { RETARGET_TX(RETARGET_UART, '\r'); } RETARGET_TX(RETARGET_UART, c); return c; } /**************************************************************************//** * @brief Enable hardware flow control. (RTS + CTS) * @return true if hardware flow control was enabled and false otherwise. *****************************************************************************/ bool RETARGET_SerialEnableFlowControl(void) { #if defined(RETARGET_USART) \ && defined(_USART_ROUTEPEN_CTSPEN_MASK) \ && defined(RETARGET_CTSPORT) \ && defined(RETARGET_RTSPORT) GPIO_PinModeSet(RETARGET_CTSPORT, RETARGET_CTSPIN, gpioModeInputPull, 0); GPIO_PinModeSet(RETARGET_RTSPORT, RETARGET_RTSPIN, gpioModePushPull, 0); RETARGET_UART->ROUTELOC1 = (RETARGET_CTS_LOCATION << _USART_ROUTELOC1_CTSLOC_SHIFT) | (RETARGET_RTS_LOCATION << _USART_ROUTELOC1_RTSLOC_SHIFT); RETARGET_UART->ROUTEPEN |= (USART_ROUTEPEN_CTSPEN | USART_ROUTEPEN_RTSPEN); RETARGET_UART->CTRLX |= USART_CTRLX_CTSEN; return true; #else return false; #endif } /**************************************************************************//** * @brief Flush UART/LEUART *****************************************************************************/ void RETARGET_SerialFlush(void) { #if defined(RETARGET_USART) #if defined(USART_STATUS_TXIDLE) #define _GENERIC_UART_STATUS_IDLE USART_STATUS_TXIDLE #else #define _GENERIC_UART_STATUS_IDLE USART_STATUS_TXC #endif #else #if defined(LEUART_STATUS_TXIDLE) #define _GENERIC_UART_STATUS_IDLE LEUART_STATUS_TXIDLE #else #define _GENERIC_UART_STATUS_IDLE LEUART_STATUS_TXC #endif #endif while (!(RETARGET_UART->STATUS & _GENERIC_UART_STATUS_IDLE)) ; } /** @} (end group RetargetIo) */ /** @} (end group kitdrv) */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/hardware/kit/common/drivers/retargetserial.h.
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/***************************************************************************//** * @file * @brief Retarget stdout to a serial port. ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * The licensor of this software is Silicon Laboratories Inc. Your use of this * software is governed by the terms of Silicon Labs Master Software License * Agreement (MSLA) available at * www.silabs.com/about-us/legal/master-software-license-agreement. This * software is distributed to you in Source Code format and is governed by the * sections of the MSLA applicable to Source Code. * ******************************************************************************/ #ifndef __RETARGETSERIAL_H #define __RETARGETSERIAL_H #if defined(HAL_CONFIG) #include "retargetserialhalconfig.h" #else #include "retargetserialconfig.h" #endif #include <stdbool.h> /***************************************************************************//** * @addtogroup kitdrv * @{ ******************************************************************************/ /***************************************************************************//** * @addtogroup RetargetIo * @brief Standard I/O retargeting driver * @details * This module provide low-level retargeting of stdio for all * supported toolchains. * @{ ******************************************************************************/ #ifdef __cplusplus extern "C" { #endif #if defined(__CROSSWORKS_ARM) int __putchar(int ch); int __getchar(void); #endif int RETARGET_ReadChar(void); int RETARGET_WriteChar(char c); void RETARGET_SerialCrLf(int on); void RETARGET_SerialInit(void); bool RETARGET_SerialEnableFlowControl(void); void RETARGET_SerialFlush(void); #ifdef __cplusplus } #endif /** @} (end group RetargetIo) */ /** @} (end group kitdrv) */ #endif |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/hardware/kit/common/drivers/udelay.h.
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/***************************************************************************//** * @file * @brief Microsecond delay routine. ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * The licensor of this software is Silicon Laboratories Inc. Your use of this * software is governed by the terms of Silicon Labs Master Software License * Agreement (MSLA) available at * www.silabs.com/about-us/legal/master-software-license-agreement. This * software is distributed to you in Source Code format and is governed by the * sections of the MSLA applicable to Source Code. * ******************************************************************************/ #ifndef __UDELAY_H #define __UDELAY_H #include <stdint.h> /***************************************************************************//** * @addtogroup kitdrv * @{ ******************************************************************************/ /***************************************************************************//** * @addtogroup Udelay * @{ ******************************************************************************/ #ifdef __cplusplus extern "C" { #endif void UDELAY_Calibrate(void); void UDELAY_Delay(uint32_t usecs); #ifdef __cplusplus } #endif /** @} (end group Udelay) */ /** @} (end group kitdrv) */ #endif |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/hardware/kit/common/halconfig/bsphalconfig.h.
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#ifndef BSPHALCONFIG_H #define BSPHALCONFIG_H #include "hal-config.h" // HAL config is only supported on STK platform #define BSP_STK #ifdef BSP_LED_PRESENT // HAL Config LED module enabled #define BSP_GPIO_LEDS #define BSP_NO_OF_LEDS BSP_LED_COUNT #define BSP_GPIO_LEDARRAY_INIT BSP_LED_INIT #endif #ifdef BSP_EXTLED_PRESENT // HAL Config EXTLED module enabled #define BSP_GPIO_LEDS #define BSP_NO_OF_LEDS BSP_EXTLED_COUNT #define BSP_GPIO_EXTLEDARRAY_INIT BSP_EXTLED_INIT #endif #ifdef BSP_BUTTON_PRESENT // HAL Config Button module enabled #define BSP_GPIO_BUTTONS #define BSP_NO_OF_BUTTONS BSP_BUTTON_COUNT #define BSP_GPIO_BUTTONARRAY_INIT BSP_BUTTON_INIT #endif #ifdef HAL_IOEXP_ENABLE #define BSP_IO_EXPANDER 1 #if (BSP_IOEXP_PERIPHERAL == HAL_I2C_PORT_I2C0) #define BSP_IOEXP_I2C_DEVICE I2C0 #elif (BSP_IOEXP_PERIPHERAL == HAL_I2C_PORT_I2C1) #define BSP_IOEXP_I2C_DEVICE I2C1 #elif (BSP_IOEXP_PERIPHERAL == HAL_I2C_PORT_I2C2) #define BSP_IOEXP_I2C_DEVICE I2C2 #elif (BSP_IOEXP_PERIPHERAL == HAL_I2C_PORT_I2C3) #define BSP_IOEXP_I2C_DEVICE I2C3 #else #error "I2C expander peripheral not configured" #endif #endif #if HAL_PTI_ENABLE && !defined(RAIL_PTI_CONFIG) // Series 2 devices do not have LOC settings, so HWCONF will not define the // following macros for those devices. The RAIL structure, on the other hand, // stayed the same for backwards compatibility reasons. RAIL will ignore the // LOC setting for series 2 devices, so we give them any value here to avoid // compilation errors. #if defined(_SILICON_LABS_32B_SERIES_2) #define BSP_PTI_DFRAME_LOC 0 #define BSP_PTI_DOUT_LOC 0 #define BSP_PTI_DCLK_LOC 0 #endif #if HAL_PTI_MODE == HAL_PTI_MODE_SPI #define RAIL_PTI_CONFIG \ { \ RAIL_PTI_MODE_SPI, /* SPI mode */ \ HAL_PTI_BAUD_RATE, /* Baud rate */ \ BSP_PTI_DOUT_LOC, /* DOUT location */ \ BSP_PTI_DOUT_PORT, /* Get the port for this loc */ \ BSP_PTI_DOUT_PIN, /* Get the pin, location should match above */ \ BSP_PTI_DCLK_LOC, /* DCLK location */ \ BSP_PTI_DCLK_PORT, /* Get the port for this loc */ \ BSP_PTI_DCLK_PIN, /* Get the pin, location should match above */ \ BSP_PTI_DFRAME_LOC, /* DFRAME location */ \ BSP_PTI_DFRAME_PORT, /* Get the port for this loc */ \ BSP_PTI_DFRAME_PIN, /* Get the pin, location should match above */ \ } #elif HAL_PTI_MODE == HAL_PTI_MODE_UART #define RAIL_PTI_CONFIG \ { \ RAIL_PTI_MODE_UART, /* UART mode */ \ HAL_PTI_BAUD_RATE, /* Baud rate */ \ BSP_PTI_DOUT_LOC, /* DOUT location */ \ BSP_PTI_DOUT_PORT, /* Get the port for this loc */ \ BSP_PTI_DOUT_PIN, /* Get the pin, location should match above */ \ 0, /* No DCLK in UART mode */ \ 0, /* No DCLK in UART mode */ \ 0, /* No DCLK in UART mode */ \ BSP_PTI_DFRAME_LOC, /* DFRAME location */ \ BSP_PTI_DFRAME_PORT, /* Get the port for this loc */ \ BSP_PTI_DFRAME_PIN, /* Get the pin, location should match above */ \ } #elif HAL_PTI_MODE == HAL_PTI_MODE_UART_ONEWIRE #define RAIL_PTI_CONFIG \ { \ RAIL_PTI_MODE_UART_ONEWIRE, /* UART onewire mode */ \ HAL_PTI_BAUD_RATE, /* Baud rate */ \ BSP_PTI_DOUT_LOC, /* DOUT location */ \ BSP_PTI_DOUT_PORT, /* Get the port for this loc */ \ BSP_PTI_DOUT_PIN, /* Get the pin, location should match above */ \ 0, /* No DCLK in UART onewire mode */ \ 0, /* No DCLK in UART onewire mode */ \ 0, /* No DCLK in UART onewire mode */ \ 0, /* No DFRAME in UART onewire mode */ \ 0, /* No DFRAME in UART onewire mode */ \ 0, /* No DFRAME in UART onewire mode */ \ } #else #error "Invalid PTI mode (HAL_PTI_MODE)" #endif #endif #if !defined(RAIL_PA_2P4_CONFIG) // HAL Config 2.4 GHz PA configuration enabled #define RAIL_PA_2P4_CONFIG \ { \ RAIL_TX_POWER_MODE_2P4_HP, /* Power Amplifier mode */ \ BSP_PA_VOLTAGE, /* Power Amplifier vPA Voltage mode */ \ HAL_PA_RAMP, /* Desired ramp time in us */ \ } #endif #if !defined(RAIL_PA_SUBGIG_CONFIG) // HAL Config sub-GHz PA configuration enabled #define RAIL_PA_SUBGIG_CONFIG \ { \ RAIL_TX_POWER_MODE_SUBGIG, /* Power Amplifier mode */ \ BSP_PA_VOLTAGE, /* Power Amplifier vPA Voltage mode */ \ HAL_PA_RAMP, /* Desired ramp time in us */ \ } #endif #if defined(HAL_PA_POWER) && !defined(RAIL_PA_DEFAULT_POWER) #define RAIL_PA_DEFAULT_POWER HAL_PA_POWER #endif #if defined(HAL_PA_CURVE_HEADER) && !defined(RAIL_PA_CURVES) #define RAIL_PA_CURVES HAL_PA_CURVE_HEADER #endif #define BSP_BCP_VERSION 2 #include "bsp_bcp.h" #endif // BSPHALCONFIG_H |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/hardware/kit/common/halconfig/displayhalconfig.h.
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#ifndef DISPLAYHALCONFIG_H #define DISPLAYHALCONFIG_H #include "hal-config.h" // ----------------------------------------------------------------------------- // Peripheral/pin configuration #if BSP_SPIDISPLAY_USART == HAL_SPI_PORT_USART0 // USART0 #define PAL_SPI_USART_UNIT USART0 #define PAL_SPI_USART_INDEX 0 #define PAL_SPI_USART_CLOCK cmuClock_USART0 #elif BSP_SPIDISPLAY_USART == HAL_SPI_PORT_USART1 // USART1 #define PAL_SPI_USART_UNIT USART1 #define PAL_SPI_USART_INDEX 1 #define PAL_SPI_USART_CLOCK cmuClock_USART1 #elif BSP_SPIDISPLAY_USART == HAL_SPI_PORT_USART2 // USART2 #define PAL_SPI_USART_UNIT USART2 #define PAL_SPI_USART_INDEX 2 #define PAL_SPI_USART_CLOCK cmuClock_USART2 #elif BSP_SPIDISPLAY_USART == HAL_SPI_PORT_USART3 // USART3 #define PAL_SPI_USART_UNIT USART3 #define PAL_SPI_USART_INDEX 3 #define PAL_SPI_USART_CLOCK cmuClock_USART3 #elif BSP_SPIDISPLAY_USART == HAL_SPI_PORT_USART4 // USART4 #define PAL_SPI_USART_UNIT USART4 #define PAL_SPI_USART_INDEX 4 #define PAL_SPI_USART_CLOCK cmuClock_USART4 #elif BSP_SPIDISPLAY_USART == HAL_SPI_PORT_USART5 // USART5 #define PAL_SPI_USART_UNIT USART5 #define PAL_SPI_USART_INDEX 5 #define PAL_SPI_USART_CLOCK cmuClock_USART5 #else #error "Display config: Unknown USART selection" #endif #define LCD_PORT_SI BSP_SPIDISPLAY_MOSI_PORT #define LCD_PIN_SI BSP_SPIDISPLAY_MOSI_PIN #define PAL_SPI_USART_LOCATION_TX BSP_SPIDISPLAY_MOSI_LOC #define LCD_PORT_SCLK BSP_SPIDISPLAY_CLK_PORT #define LCD_PIN_SCLK BSP_SPIDISPLAY_CLK_PIN #define PAL_SPI_USART_LOCATION_SCLK BSP_SPIDISPLAY_CLK_LOC #define LCD_PORT_SCS BSP_SPIDISPLAY_CS_PORT #define LCD_PIN_SCS BSP_SPIDISPLAY_CS_PIN #define PAL_SPI_BAUDRATE HAL_SPIDISPLAY_FREQUENCY #if defined(BSP_SPIDISPLAY_ENABLE_PORT) // Use power/enable pin #define LCD_PORT_DISP_PWR BSP_SPIDISPLAY_ENABLE_PORT #define LCD_PIN_DISP_PWR BSP_SPIDISPLAY_ENABLE_PIN #endif #if defined(BSP_SPIDISPLAY_EXTMODE_PORT) // Use EXTMODE pin to toggle between SPI and EXTCOMIN polarity inversion #define LCD_PORT_EXTMODE BSP_SPIDISPLAY_EXTMODE_PORT #define LCD_PIN_EXTMODE BSP_SPIDISPLAY_EXTMODE_PIN #endif #if defined(RTCC_PRESENT) #if HAL_CLK_LFECLK_SOURCE == HAL_CLK_LFCLK_SOURCE_LFXO #define PAL_RTCC_CLOCK_LFXO #elif HAL_CLK_LFCLK_SOURCE == HAL_CLK_LFCLK_SOURCE_ULFRCO #define PAL_RTCC_CLOCK_ULFRCO #else #define PAL_RTCC_CLOCK_LFRCO #endif #endif #if defined(RTC_PRESENT) #if HAL_CLK_LFECLK_SOURCE == HAL_CLK_LFCLK_SOURCE_LFXO #define PAL_RTC_CLOCK_LFXO #elif HAL_CLK_LFCLK_SOURCE == HAL_CLK_LFCLK_SOURCE_ULFRCO #define PAL_RTC_CLOCK_ULFRCO #else #define PAL_RTC_CLOCK_LFRCO #endif #endif #if HAL_SPIDISPLAY_EXTMODE_SPI // -------------------------------- // EXTMODE is LOW, use SPI command for polarity inversion #elif HAL_SPIDISPLAY_EXTMODE_EXTCOMIN // -------------------------------- // EXTMODE is HIGH, use EXTCOMIN pin for polarity inversion // Configure DISPLAY driver for EXTCOMIN #define POLARITY_INVERSION_EXTCOMIN // Use hardware polarity inversion pin #define LCD_PORT_EXTCOMIN BSP_SPIDISPLAY_EXTCOMIN_PORT #define LCD_PIN_EXTCOMIN BSP_SPIDISPLAY_EXTCOMIN_PIN #if HAL_SPIDISPLAY_EXTCOMIN_USE_CALLBACK // Someone else owns the RTC(C), register a callback for EXTCOMIN toggling #define PAL_TIMER_REPEAT_FUNCTION (HAL_SPIDISPLAY_EXTCOMIN_CALLBACK) extern int HAL_SPIDISPLAY_EXTCOMIN_CALLBACK (void(*pFunction)(void*), void* argument, unsigned int frequency); #else // The DISPLAY PAL owns the RTC(C), and should auto-toggle the EXTCOMIN pin #define INCLUDE_PAL_GPIO_PIN_AUTO_TOGGLE #if HAL_SPIDISPLAY_EXTCOMIN_USE_PRS // Perform polarity inversion autonomously using RTC output on PRS #define INCLUDE_PAL_GPIO_PIN_AUTO_TOGGLE_HW_ONLY #define POLARITY_INVERSION_EXTCOMIN_PAL_AUTO_TOGGLE #define LCD_AUTO_TOGGLE_PRS_CH BSP_SPIDISPLAY_EXTCOMIN_CHANNEL #if BSP_SPIDISPLAY_EXTCOMIN_CHANNEL < 4 #define BSP_SPIDISPLAY_ROUTELOC PRS->ROUTELOC0 #elif BSP_SPIDISPLAY_EXTCOMIN_CHANNEL < 8 #define BSP_SPIDISPLAY_ROUTELOC PRS->ROUTELOC1 #elif BSP_SPIDISPLAY_EXTCOMIN_CHANNEL < 12 #define BSP_SPIDISPLAY_ROUTELOC PRS->ROUTELOC2 #elif BSP_SPIDISPLAY_EXTCOMIN_CHANNEL < 16 #define BSP_SPIDISPLAY_ROUTELOC PRS->ROUTELOC3 #elif BSP_SPIDISPLAY_EXTCOMIN_CHANNEL < 20 #define BSP_SPIDISPLAY_ROUTELOC PRS->ROUTELOC4 #elif BSP_SPIDISPLAY_EXTCOMIN_CHANNEL < 24 #define BSP_SPIDISPLAY_ROUTELOC PRS->ROUTELOC5 #else #error "Invalid SPIDISPLAY PRS channel" #endif // *INDENT-OFF* #define LCD_AUTO_TOGGLE_PRS_ROUTELOC() BSP_SPIDISPLAY_ROUTELOC = \ (BSP_SPIDISPLAY_ROUTELOC & ~0xFFU << ((BSP_SPIDISPLAY_EXTCOMIN_CHANNEL % 4U) * 8U)) \ | (BSP_SPIDISPLAY_EXTCOMIN_LOC << ((BSP_SPIDISPLAY_EXTCOMIN_CHANNEL % 4U) * 8U)) // *INDENT-ON* #define LCD_AUTO_TOGGLE_PRS_ROUTEPEN (1 << LCD_AUTO_TOGGLE_PRS_CH) #endif // HAL_SPIDISPLAY_EXTCOMIN_USE_PRS #endif // HAL_SPIDISPLAY_EXTCOMIN_USE_CALLBACK #else // -------------------------------- // No EXTMODE setting, assume manual EXTCOMIN control #define POLARITY_INVERSION_EXTCOMIN #define POLARITY_INVERSION_EXTCOMIN_PAL_AUTO_TOGGLE #define POLARITY_INVERSION_EXTCOMIN_MANUAL #endif // HAL_SPIDISPLAY_EXTMODE_SPI // ----------------------------------------------------------------------------- // Display configuration /** * Maximum number of display devices the display module is configured * to support. This number may be increased if the system includes more than * one display device. However, the number should be kept low in order to * save memory. */ #define DISPLAY_DEVICES_MAX (1) #if BSP_SPIDISPLAY_DISPLAY == HAL_DISPLAY_SHARP_LS013B7DH03 #define SHARP_MEMLCD_DEVICE_NAME "Sharp LS013B7DH03 #1" #define LS013B7DH03_POLARITY_INVERSION_FREQUENCY (64) /** * Geometry of display device #0 in the system (i.e. ls013b7dh03 on the WSTK) * These defines can be used to declare static framebuffers in order to save * extra memory consumed by malloc. */ #include "displayls013b7dh03.h" #define DISPLAY0_WIDTH (LS013B7DH03_WIDTH) #define DISPLAY0_HEIGHT (LS013B7DH03_HEIGHT) /** * Define all display device driver initialization functions here. */ #define DISPLAY_DEVICE_DRIVER_INIT_FUNCTIONS \ { \ DISPLAY_Ls013b7dh03Init, \ NULL \ } #elif BSP_SPIDISPLAY_DISPLAY == HAL_DISPLAY_SHARP_LS013B7DH06 #define SHARP_MEMLCD_DEVICE_NAME "Sharp LS013B7DH06 #1" #define LS013B7DH06_POLARITY_INVERSION_FREQUENCY (64) /* Define time for power supply to ramp after enabled */ #define SHARP_MEMLCD_POWER_RAMP_US 100 /** Display color mode */ #define DISPLAY_COLOUR_MODE_IS_RGB_3BIT /** * Geometry of display device #0 in the system (i.e. ls013b7dh06 on the STK) * These defines can be used to declare static framebuffers in order to save * extra memory consumed by malloc. */ #include "displayls013b7dh06.h" #define DISPLAY0_WIDTH (LS013B7DH06_WIDTH) #define DISPLAY0_HEIGHT (LS013B7DH06_HEIGHT) #define DISPLAY0_BITS_PER_PIXEL (LS013B7DH06_BITS_PER_PIXEL) /** * Define all display device driver initialization functions here. */ #define DISPLAY_DEVICE_DRIVER_INIT_FUNCTIONS \ { \ DISPLAY_Ls013b7dh06Init, \ NULL \ } #endif #include "displayconfigapp.h" #endif // DISPLAYHALCONFIG_H |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/hardware/kit/common/halconfig/i2cspmhalconfig.h.
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#ifndef I2CSPMHALCONFIG_H #define I2CSPMHALCONFIG_H #include "hal-config.h" #if HAL_IOEXP_ENABLE #if (BSP_IOEXP_PERIPHERAL == HAL_I2C_PORT_I2C0) #define I2CSPM_DEFAULT_PERIPHERAL I2C0 #elif (BSP_IOEXP_PERIPHERAL == HAL_I2C_PORT_I2C1) #define I2CSPM_DEFAULT_PERIPHERAL I2C1 #elif (BSP_IOEXP_PERIPHERAL == HAL_I2C_PORT_I2C2) #define I2CSPM_DEFAULT_PERIPHERAL I2C2 #elif (BSP_IOEXP_PERIPHERAL == HAL_I2C_PORT_I2C3) #define I2CSPM_DEFAULT_PERIPHERAL I2C3 #else #error "I2C expander peripheral not configured" #endif #if defined(_SILICON_LABS_32B_SERIES_0) #define I2CSPM_INIT_DEFAULT \ { \ I2CSPM_DEFAULT_PERIPHERAL, /* Use I2C instance */ \ BSP_IOEXP_SCL_PORT, /* SCL port */ \ BSP_IOEXP_SCL_PIN, /* SCL pin */ \ BSP_IOEXP_SDA_PORT, /* SDA port */ \ BSP_IOEXP_SDA_PIN, /* SDA pin */ \ BSP_IOEXP_ROUTE_LOC, /* Location */ \ 0, /* Use currently configured reference clock */ \ I2C_FREQ_STANDARD_MAX, /* Set to standard rate */ \ i2cClockHLRStandard, /* Set to use 4:4 low/high duty cycle */ \ } #elif defined(_SILICON_LABS_32B_SERIES_1) #define I2CSPM_INIT_DEFAULT \ { \ I2CSPM_DEFAULT_PERIPHERAL, /* Use I2C instance */ \ BSP_IOEXP_SCL_PORT, /* SCL port */ \ BSP_IOEXP_SCL_PIN, /* SCL pin */ \ BSP_IOEXP_SDA_PORT, /* SDA port */ \ BSP_IOEXP_SDA_PIN, /* SDA pin */ \ BSP_IOEXP_SCL_LOC, /* Location of SCL */ \ BSP_IOEXP_SDA_LOC, /* Location of SDA */ \ 0, /* Use currently configured reference clock */ \ I2C_FREQ_STANDARD_MAX, /* Set to standard rate */ \ i2cClockHLRStandard, /* Set to use 4:4 low/high duty cycle */ \ } #elif defined(_SILICON_LABS_32B_SERIES_2) #define I2CSPM_INIT_DEFAULT \ { \ I2CSPM_DEFAULT_PERIPHERAL, /* Use I2C instance */ \ BSP_IOEXP_SCL_PORT, /* SCL port */ \ BSP_IOEXP_SCL_PIN, /* SCL pin */ \ BSP_IOEXP_SDA_PORT, /* SDA port */ \ BSP_IOEXP_SDA_PIN, /* SDA pin */ \ 0, /* Use currently configured reference clock */ \ I2C_FREQ_STANDARD_MAX, /* Set to standard rate */ \ i2cClockHLRStandard, /* Set to use 4:4 low/high duty cycle */ \ } #endif #endif // BSP_IOEXP #if HAL_I2CSENSOR_ENABLE #if (BSP_I2CSENSOR_PERIPHERAL == HAL_I2C_PORT_I2C0) #define I2CSPM_SENSOR_PERIPHERAL I2C0 #elif (BSP_I2CSENSOR_PERIPHERAL == HAL_I2C_PORT_I2C1) #define I2CSPM_SENSOR_PERIPHERAL I2C1 #elif (BSP_I2CSENSOR_PERIPHERAL == HAL_I2C_PORT_I2C2) #define I2CSPM_SENSOR_PERIPHERAL I2C2 #elif (BSP_I2CSENSOR_PERIPHERAL == HAL_I2C_PORT_I2C3) #define I2CSPM_SENSOR_PERIPHERAL I2C3 #else #error "I2C sensor peripheral not configured" #endif #if defined(_SILICON_LABS_32B_SERIES_0) #define I2CSPM_INIT_SENSOR \ { \ I2CSPM_SENSOR_PERIPHERAL, /* Use I2C instance */ \ BSP_I2CSENSOR_SCL_PORT, /* SCL port */ \ BSP_I2CSENSOR_SCL_PIN, /* SCL pin */ \ BSP_I2CSENSOR_SDA_PORT, /* SDA port */ \ BSP_I2CSENSOR_SDA_PIN, /* SDA pin */ \ BSP_I2CSENSOR_ROUTE_LOC, /* Location */ \ 0, /* Use currently configured reference clock */ \ I2C_FREQ_STANDARD_MAX, /* Set to standard rate */ \ i2cClockHLRStandard, /* Set to use 4:4 low/high duty cycle */ \ } #elif defined(_SILICON_LABS_32B_SERIES_1) #define I2CSPM_INIT_SENSOR \ { \ I2CSPM_SENSOR_PERIPHERAL, /* Use I2C instance */ \ BSP_I2CSENSOR_SCL_PORT, /* SCL port */ \ BSP_I2CSENSOR_SCL_PIN, /* SCL pin */ \ BSP_I2CSENSOR_SDA_PORT, /* SDA port */ \ BSP_I2CSENSOR_SDA_PIN, /* SDA pin */ \ BSP_I2CSENSOR_SCL_LOC, /* Location of SCL */ \ BSP_I2CSENSOR_SDA_LOC, /* Location of SDA */ \ 0, /* Use currently configured reference clock */ \ I2C_FREQ_STANDARD_MAX, /* Set to standard rate */ \ i2cClockHLRStandard, /* Set to use 4:4 low/high duty cycle */ \ } #elif defined(_SILICON_LABS_32B_SERIES_2) #define I2CSPM_INIT_SENSOR \ { \ I2CSPM_SENSOR_PERIPHERAL, /* Use I2C instance */ \ BSP_I2CSENSOR_SCL_PORT, /* SCL port */ \ BSP_I2CSENSOR_SCL_PIN, /* SCL pin */ \ BSP_I2CSENSOR_SDA_PORT, /* SDA port */ \ BSP_I2CSENSOR_SDA_PIN, /* SDA pin */ \ 0, /* Use currently configured reference clock */ \ I2C_FREQ_STANDARD_MAX, /* Set to standard rate */ \ i2cClockHLRStandard, /* Set to use 4:4 low/high duty cycle */ \ } #endif #endif // BSP_I2CSENSOR #if !defined(I2CSPM_INIT_DEFAULT) && defined(I2CSPM_INIT_SENSOR) // Fall back to sensor define for default define #define I2CSPM_INIT_DEFAULT I2CSPM_INIT_SENSOR #endif #define I2CSPM_TRANSFER_TIMEOUT 300000 #endif // I2CSPMHALCONFIG_H |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/hardware/kit/common/halconfig/mx25flashhalconfig.h.
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#ifndef MX25FLASHHALCONFIG_H #define MX25FLASHHALCONFIG_H #include "hal-config.h" #ifdef BSP_EXTFLASH_USART #if BSP_EXTFLASH_USART == HAL_SPI_PORT_USART0 // USART0 #define MX25_USART USART0 #define MX25_USART_CLK cmuClock_USART0 #define MX25_USART_ROUTE GPIO->USARTROUTE[0] #elif BSP_EXTFLASH_USART == HAL_SPI_PORT_USART1 // USART1 #define MX25_USART USART1 #define MX25_USART_CLK cmuClock_USART1 #define MX25_USART_ROUTE GPIO->USARTROUTE[1] #elif BSP_EXTFLASH_USART == HAL_SPI_PORT_USART2 // USART2 #define MX25_USART USART2 #define MX25_USART_CLK cmuClock_USART2 #define MX25_USART_ROUTE GPIO->USARTROUTE[2] #elif BSP_EXTFLASH_USART == HAL_SPI_PORT_USART3 // USART3 #define MX25_USART USART3 #define MX25_USART_CLK cmuClock_USART3 #define MX25_USART_ROUTE GPIO->USARTROUTE[3] #elif BSP_EXTFLASH_USART == HAL_SPI_PORT_USART4 // USART4 #define MX25_USART USART4 #define MX25_USART_CLK cmuClock_USART4 #define MX25_USART_ROUTE GPIO->USARTROUTE[4] #elif BSP_EXTFLASH_USART == HAL_SPI_PORT_USART5 // USART5 #define MX25_USART USART5 #define MX25_USART_CLK cmuClock_USART5 #define MX25_USART_ROUTE GPIO->USARTROUTE[5] #else #error "SPI flash config: Unknown USART selection" #endif #define MX25_PORT_MOSI BSP_EXTFLASH_MOSI_PORT #define MX25_PIN_MOSI BSP_EXTFLASH_MOSI_PIN #define MX25_LOC_TX BSP_EXTFLASH_MOSI_LOC #define MX25_PORT_MISO BSP_EXTFLASH_MISO_PORT #define MX25_PIN_MISO BSP_EXTFLASH_MISO_PIN #define MX25_LOC_RX BSP_EXTFLASH_MISO_LOC #define MX25_PORT_SCLK BSP_EXTFLASH_CLK_PORT #define MX25_PIN_SCLK BSP_EXTFLASH_CLK_PIN #define MX25_LOC_SCLK BSP_EXTFLASH_CLK_LOC #define MX25_PORT_CS BSP_EXTFLASH_CS_PORT #define MX25_PIN_CS BSP_EXTFLASH_CS_PIN #define MX25_BAUDRATE HAL_EXTFLASH_FREQUENCY #endif //BSP_EXTFLASH_USART #endif // MX25FLASHHALCONFIG_H |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/hardware/kit/common/halconfig/retargetserialhalconfig.h.
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#ifndef RETARGETSERIALHALCONFIG_H #define RETARGETSERIALHALCONFIG_H #include "hal-config.h" #if BSP_SERIAL_APP_PORT == HAL_SERIAL_PORT_USART0 // USART0 #define RETARGET_UART USART0 #define RETARGET_CLK cmuClock_USART0 #define RETARGET_UART_INDEX 0 #if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_103) // EFM32TG11 has merged USART interrupts #define RETARGET_IRQ_NAME USART0_IRQHandler #define RETARGET_IRQn USART0_IRQn #else #define RETARGET_IRQ_NAME USART0_RX_IRQHandler #define RETARGET_IRQn USART0_RX_IRQn #endif #define RETARGET_USART 1 #elif BSP_SERIAL_APP_PORT == HAL_SERIAL_PORT_USART1 // USART1 #define RETARGET_UART USART1 #define RETARGET_CLK cmuClock_USART1 #define RETARGET_UART_INDEX 1 #if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_103) // EFM32TG11 has merged USART interrupts #define RETARGET_IRQ_NAME USART1_IRQHandler #define RETARGET_IRQn USART1_IRQn #else #define RETARGET_IRQ_NAME USART1_RX_IRQHandler #define RETARGET_IRQn USART1_RX_IRQn #endif #define RETARGET_USART 1 #elif BSP_SERIAL_APP_PORT == HAL_SERIAL_PORT_USART2 // USART2 #define RETARGET_UART USART2 #define RETARGET_CLK cmuClock_USART2 #define RETARGET_UART_INDEX 2 #if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_103) // EFM32TG11 has merged USART interrupts #define RETARGET_IRQ_NAME USART2_IRQHandler #define RETARGET_IRQn USART2_IRQn #else #define RETARGET_IRQ_NAME USART2_RX_IRQHandler #define RETARGET_IRQn USART2_RX_IRQn #endif #define RETARGET_USART 1 #elif BSP_SERIAL_APP_PORT == HAL_SERIAL_PORT_USART3 // USART3 #define RETARGET_UART USART3 #define RETARGET_CLK cmuClock_USART3 #define RETARGET_UART_INDEX 3 #if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_103) // EFM32TG11 has merged USART interrupts #define RETARGET_IRQ_NAME USART3_IRQHandler #define RETARGET_IRQn USART3_IRQn #else #define RETARGET_IRQ_NAME USART3_RX_IRQHandler #define RETARGET_IRQn USART3_RX_IRQn #endif #define RETARGET_USART 1 #elif BSP_SERIAL_APP_PORT == HAL_SERIAL_PORT_USART4 // USART4 #define RETARGET_UART USART4 #define RETARGET_CLK cmuClock_USART4 #define RETARGET_UART_INDEX 4 #define RETARGET_IRQ_NAME USART4_RX_IRQHandler #define RETARGET_IRQn USART4_RX_IRQn #define RETARGET_USART 1 #elif BSP_SERIAL_APP_PORT == HAL_SERIAL_PORT_USART5 // USART5 #define RETARGET_UART USART5 #define RETARGET_CLK cmuClock_USART5 #define RETARGET_UART_INDEX 5 #define RETARGET_IRQ_NAME USART5_RX_IRQHandler #define RETARGET_IRQn USART5_RX_IRQn #define RETARGET_USART 1 #elif BSP_SERIAL_APP_PORT == HAL_SERIAL_PORT_UART0 // UART0 #define RETARGET_UART UART0 #define RETARGET_CLK cmuClock_UART0 #define RETARGET_UART_INDEX 0 #if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_103) // EFM32TG11 has merged UART interrupts #define RETARGET_IRQ_NAME UART0_IRQHandler #define RETARGET_IRQn UART0_IRQn #else #define RETARGET_IRQ_NAME UART0_RX_IRQHandler #define RETARGET_IRQn UART0_RX_IRQn #endif #define RETARGET_USART 1 #elif BSP_SERIAL_APP_PORT == HAL_SERIAL_PORT_UART1 // UART1 #define RETARGET_UART UART1 #define RETARGET_CLK cmuClock_UART1 #define RETARGET_UART_INDEX 1 #if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_103) // EFM32TG11 has merged UART interrupts #define RETARGET_IRQ_NAME UART1_IRQHandler #define RETARGET_IRQn UART1_IRQn #else #define RETARGET_IRQ_NAME UART1_RX_IRQHandler #define RETARGET_IRQn UART1_RX_IRQn #endif #define RETARGET_USART 1 #elif BSP_SERIAL_APP_PORT == HAL_SERIAL_PORT_LEUART0 // LEUART0 #define RETARGET_UART LEUART0 #define RETARGET_CLK cmuClock_LEUART0 #define RETARGET_UART_INDEX 0 #define RETARGET_IRQ_NAME LEUART0_IRQHandler #define RETARGET_IRQn LEUART0_IRQn #define RETARGET_LEUART 1 #elif BSP_SERIAL_APP_PORT == HAL_SERIAL_PORT_LEUART1 // LEUART1 #define RETARGET_UART LEUART1 #define RETARGET_CLK cmuClock_LEUART1 #define RETARGET_UART_INDEX 1 #define RETARGET_IRQ_NAME LEUART1_IRQHandler #define RETARGET_IRQn LEUART1_IRQn #define RETARGET_LEUART 1 #endif #if defined(RETARGET_USART) // UART is an USART #define RETARGET_TX USART_Tx #define RETARGET_RX USART_Rx #elif defined(RETARGET_LEUART) // UART is a LEUART #define RETARGET_TX LEUART_Tx #define RETARGET_RX LEUART_Rx #else #error "Invalid UART type" #endif #define RETARGET_TXPORT BSP_SERIAL_APP_TX_PORT #define RETARGET_TXPIN BSP_SERIAL_APP_TX_PIN #define RETARGET_RXPORT BSP_SERIAL_APP_RX_PORT #define RETARGET_RXPIN BSP_SERIAL_APP_RX_PIN #if defined(_SILICON_LABS_32B_SERIES_0) // Series 0 devices only have one location #define RETARGET_LOCATION BSP_SERIAL_APP_ROUTE_LOC #else // Series 1 devices have one location per pin #define RETARGET_TX_LOCATION BSP_SERIAL_APP_TX_LOC #define RETARGET_RX_LOCATION BSP_SERIAL_APP_RX_LOC #endif #if defined(BSP_SERIAL_APP_CTS_PORT) // Only Series 1+ USARTs have CTS #define RETARGET_CTSPORT BSP_SERIAL_APP_CTS_PORT #define RETARGET_CTSPIN BSP_SERIAL_APP_CTS_PIN #define RETARGET_CTS_LOCATION BSP_SERIAL_APP_CTS_LOC #endif #if defined(BSP_SERIAL_APP_RTS_PORT) // Only Series 1+ USARTs have RTS #define RETARGET_RTSPORT BSP_SERIAL_APP_RTS_PORT #define RETARGET_RTSPIN BSP_SERIAL_APP_RTS_PIN #define RETARGET_RTS_LOCATION BSP_SERIAL_APP_RTS_LOC #endif #if HAL_VCOM_ENABLE && defined(BSP_VCOM_ENABLE_PORT) #define RETARGET_PERIPHERAL_ENABLE() \ GPIO_PinModeSet(BSP_VCOM_ENABLE_PORT, \ BSP_VCOM_ENABLE_PIN, \ gpioModePushPull, \ 1) #else #define RETARGET_PERIPHERAL_ENABLE() #endif #endif // RETARGETSERIALHALCONFIG_H |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/hardware/kit/common/halconfig/tracehalconfig.h.
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#ifndef TRACEHALCONFIG_H #define TRACEHALCONFIG_H #include "hal-config.h" #if defined(_SILICON_LABS_32B_SERIES_0) // Series 0 SWO pin is on DBG route location #define BSP_TRACE_SWO_LOCATION BSP_TRACE_DBGROUTE_LOC #else // Series 1 SWO pin has its own route location #define BSP_TRACE_SWO_LOCATION BSP_TRACE_SWO_LOC #endif /* Enable output on pin - GPIO Port F, Pin 2. */ #define TRACE_ENABLE_PINS() \ GPIO_PinModeSet(BSP_TRACE_SWO_PORT, \ BSP_TRACE_SWO_PIN, \ gpioModePushPull, \ 1) #endif // TRACEHALCONFIG_H |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/init_app.c.
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/***************************************************************************//** * @file * @brief init_app.c ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * The licensor of this software is Silicon Laboratories Inc. Your use of this * software is governed by the terms of Silicon Labs Master Software License * Agreement (MSLA) available at * www.silabs.com/about-us/legal/master-software-license-agreement. This * software is distributed to you in Source Code format and is governed by the * sections of the MSLA applicable to Source Code. * ******************************************************************************/ #if defined(HAL_CONFIG) #include "bsphalconfig.h" #include "hal-config.h" #include "hal-config-board.h" #else #include "bspconfig.h" #endif #include "bsp.h" #include "i2cspm.h" #include "pti.h" void initApp(void) { // Enable PTI configEnablePti(); #if (HAL_I2CSENSOR_ENABLE) // Initialize I2C peripheral I2CSPM_Init_TypeDef i2cInit = I2CSPM_INIT_DEFAULT; I2CSPM_Init(&i2cInit); #endif // HAL_I2CSENSOR_ENABLE #if defined(HAL_I2CSENSOR_ENABLE) // Note: I2C sensor is hardware enabled on this board. #endif // HAL_I2CSENSOR_ENABLE } |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/init_app.h.
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/***************************************************************************//** * @file * @brief init_app.h ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * The licensor of this software is Silicon Laboratories Inc. Your use of this * software is governed by the terms of Silicon Labs Master Software License * Agreement (MSLA) available at * www.silabs.com/about-us/legal/master-software-license-agreement. This * software is distributed to you in Source Code format and is governed by the * sections of the MSLA applicable to Source Code. * ******************************************************************************/ #ifndef INIT_APP_H #define INIT_APP_H #ifdef __cplusplus extern "C" { #endif void initApp(void); #ifdef __cplusplus } #endif #endif // INIT_APP_H |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/init_board.h.
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/***************************************************************************//** * @file * @brief init_board.h ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * The licensor of this software is Silicon Laboratories Inc. Your use of this * software is governed by the terms of Silicon Labs Master Software License * Agreement (MSLA) available at * www.silabs.com/about-us/legal/master-software-license-agreement. This * software is distributed to you in Source Code format and is governed by the * sections of the MSLA applicable to Source Code. * ******************************************************************************/ #ifndef INIT_BOARD_H #define INIT_BOARD_H #ifdef __cplusplus extern "C" { #endif #include "stdbool.h" void initBoard(void); #ifdef __cplusplus } #endif #endif // INIT_BOARD_H |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/init_board_efr32xg1.c.
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/***************************************************************************//** * @file * @brief init_board_efr32xg1.c ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * The licensor of this software is Silicon Laboratories Inc. Your use of this * software is governed by the terms of Silicon Labs Master Software License * Agreement (MSLA) available at * www.silabs.com/about-us/legal/master-software-license-agreement. This * software is distributed to you in Source Code format and is governed by the * sections of the MSLA applicable to Source Code. * ******************************************************************************/ #if defined(HAL_CONFIG) #include "bsphalconfig.h" #include "hal-config.h" #else #include "bspconfig.h" #endif #include "board_features.h" #include "em_cmu.h" #include "em_cmu.h" #include "em_usart.h" #include "mx25flash_spi.h" #include "bsp.h" void initBoard(void) { // Enable clock for CRYOTIMER CMU_ClockEnable(cmuClock_CRYOTIMER, true); // Enable clock for PRS CMU_ClockEnable(cmuClock_PRS, true); #ifdef FEATURE_EXP_HEADER_USART3 // Enable clock for USART3 CMU_ClockEnable(cmuClock_USART3, true); #else // Enable clock for USART0 CMU_ClockEnable(cmuClock_USART0, true); #endif // Enable GPIO clock source CMU_ClockEnable(cmuClock_GPIO, true); // Put the SPI flash into Deep Power Down mode for those radio boards where it is available MX25_init(); MX25_DP(); // We must disable SPI communication MX25_deinit(); } |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/init_mcu.h.
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/***************************************************************************//** * @file * @brief init_mcu.h ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * The licensor of this software is Silicon Laboratories Inc. Your use of this * software is governed by the terms of Silicon Labs Master Software License * Agreement (MSLA) available at * www.silabs.com/about-us/legal/master-software-license-agreement. This * software is distributed to you in Source Code format and is governed by the * sections of the MSLA applicable to Source Code. * ******************************************************************************/ #ifndef INIT_MCU_H #define INIT_MCU_H #ifdef __cplusplus extern "C" { #endif /* * If Studio is allowed to use the CTUNE value from EEPROM on board * it will store it in the User page memory on the MFG_CTUNE_ADDR address. * If Studio is not allowed to store this value on that address * for example user already storing a value there, then the MFG_CTUNE_EN * must be set to 0, to avoid wrong value read out. */ //Enable this to use CTUNE value form User page (0 DISABLE , 1 ENABLE) #define MFG_CTUNE_EN 1 //Address for CTUNE in User page #define MFG_CTUNE_ADDR 0x0FE00100UL //Value of the CTUNE in User page #define MFG_CTUNE_VAL (*((uint16_t *) (MFG_CTUNE_ADDR))) void initMcu(void); #ifdef __cplusplus } #endif #endif // INIT_MCU_H |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/init_mcu_efr32xg1.c.
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/***************************************************************************//** * @file * @brief init_mcu_efr32xg1.c ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * The licensor of this software is Silicon Laboratories Inc. Your use of this * software is governed by the terms of Silicon Labs Master Software License * Agreement (MSLA) available at * www.silabs.com/about-us/legal/master-software-license-agreement. This * software is distributed to you in Source Code format and is governed by the * sections of the MSLA applicable to Source Code. * ******************************************************************************/ #if defined(HAL_CONFIG) #include "bsphalconfig.h" #include "hal-config.h" #else #include "bspconfig.h" #endif #include "board_features.h" #include "em_chip.h" #include "em_cmu.h" #include "em_emu.h" #include "em_rtcc.h" #include "bsp.h" #include "init_mcu.h" // Bit [19] in MODULEINFO is the HFXOCALVAL: // 1=No factory cal, use default XO tunning value in FW // 0=Factory Cal, use XO tunning value in DI #define DEVINFO_MODULEINFO_HFXOCALVAL_MASK 0x00080000UL // Calibration value for HFXO CTUNE is at DEVINFO Offset 0x08 #define DEVINFO_MODULEINFO_CRYSTALOSCCALVAL (*((uint16_t *) (uint32_t)(DEVINFO_BASE+0x8UL))) // [15:9] : (LFXOTUNING) Calibration for LFXO TUNING // [8:0] : (HFXOCTUNE) Calibration for HFXO CTUNE #define DEVINFO_HFXOCTUNE_MASK 0x01FFUL static void initMcu_clocks(void); void initMcu(void) { // Device errata CHIP_Init(); // Set up DC-DC converter EMU_DCDCInit_TypeDef dcdcInit = BSP_DCDC_INIT; #if HAL_DCDC_BYPASS dcdcInit.dcdcMode = emuDcdcMode_Bypass; #endif EMU_DCDCInit(&dcdcInit); // Set up clocks initMcu_clocks(); RTCC_Init_TypeDef rtccInit = RTCC_INIT_DEFAULT; rtccInit.enable = true; rtccInit.debugRun = false; rtccInit.precntWrapOnCCV0 = false; rtccInit.cntWrapOnCCV1 = false; rtccInit.prescMode = rtccCntTickPresc; rtccInit.presc = rtccCntPresc_1; rtccInit.enaOSCFailDetect = false; rtccInit.cntMode = rtccCntModeNormal; RTCC_Init(&rtccInit); #if defined(_EMU_CMD_EM01VSCALE0_MASK) // Set up EM0, EM1 energy mode configuration EMU_EM01Init_TypeDef em01Init = EMU_EM01INIT_DEFAULT; EMU_EM01Init(&em01Init); #endif // _EMU_CMD_EM01VSCALE0_MASK #if defined(_EMU_CTRL_EM23VSCALE_MASK) // Set up EM2, EM3 energy mode configuration EMU_EM23Init_TypeDef em23init = EMU_EM23INIT_DEFAULT; em23init.vScaleEM23Voltage = emuVScaleEM23_LowPower; EMU_EM23Init(&em23init); #endif //_EMU_CTRL_EM23VSCALE_MASK #if defined(RMU_PRESENT) // Set reset mode for sysreset back to DEFAULT (extended), this might have // been changed by the bootloader to FULL reset. RMU->CTRL = (RMU->CTRL & ~_RMU_CTRL_SYSRMODE_MASK) | RMU_CTRL_SYSRMODE_DEFAULT; #endif } static void initMcu_clocks(void) { // Initialize HFXO // Use BSP_CLK_HFXO_INIT as last result (4th) CMU_HFXOInit_TypeDef hfxoInit = BSP_CLK_HFXO_INIT; // if Factory Cal exists in DEVINFO then use it above all (1st) if (0 == (DEVINFO->MODULEINFO & DEVINFO_MODULEINFO_HFXOCALVAL_MASK)) { hfxoInit.ctuneSteadyState = DEVINFO_MODULEINFO_CRYSTALOSCCALVAL & DEVINFO_HFXOCTUNE_MASK; } // if User page has CTUNE from studio use that in 2nd place #if defined(MFG_CTUNE_ADDR) && (MFG_CTUNE_EN == 1) else if (MFG_CTUNE_VAL != 0xFFFF) { hfxoInit.ctuneSteadyState = MFG_CTUNE_VAL; } #endif // 3rd option, get data from header defined for product/board #if defined(BSP_CLK_HFXO_CTUNE) && BSP_CLK_HFXO_CTUNE >= 0 else { hfxoInit.ctuneSteadyState = BSP_CLK_HFXO_CTUNE; } #endif CMU_HFXOInit(&hfxoInit); // Set system HFXO frequency SystemHFXOClockSet(BSP_CLK_HFXO_FREQ); // Enable HFXO oscillator, and wait for it to be stable CMU_OscillatorEnable(cmuOsc_HFXO, true, true); // Enable HFXO Autostart only if EM2 voltage scaling is disabled. // In 1.0 V mode the chip does not support frequencies > 21 MHz, // this is why HFXO autostart is not supported in this case. #if!defined(_EMU_CTRL_EM23VSCALE_MASK) // Automatically start and select HFXO CMU_HFXOAutostartEnable(0, true, true); #else CMU_ClockSelectSet(cmuClock_HF, cmuSelect_HFXO); #endif//_EMU_CTRL_EM23VSCALE_MASK // HFRCO not needed when using HFXO CMU_OscillatorEnable(cmuOsc_HFRCO, false, false); // Enabling HFBUSCLKLE clock for LE peripherals CMU_ClockEnable(cmuClock_HFLE, true); // Initialize LFXO CMU_LFXOInit_TypeDef lfxoInit = BSP_CLK_LFXO_INIT; lfxoInit.ctune = BSP_CLK_LFXO_CTUNE; CMU_LFXOInit(&lfxoInit); // Set system LFXO frequency SystemLFXOClockSet(BSP_CLK_LFXO_FREQ); // Set LFXO if selected as LFCLK CMU_ClockSelectSet(cmuClock_LFA, cmuSelect_LFXO); CMU_ClockSelectSet(cmuClock_LFB, cmuSelect_LFXO); CMU_ClockSelectSet(cmuClock_LFE, cmuSelect_LFXO); } |
Changes to Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/main.c.
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#include "init_board.h" #include "init_app.h" #include "ble-configuration.h" #include "board_features.h" /* Bluetooth stack headers */ #include "bg_types.h" #include "native_gecko.h" #include "gatt_db.h" /* Libraries containing default Gecko configuration values */ #include "em_emu.h" #include "em_cmu.h" /* Device initialization header */ ................................................................................ #ifndef MAX_CONNECTIONS #define MAX_CONNECTIONS 4 #endif uint8_t bluetooth_stack_heap[DEFAULT_BLUETOOTH_HEAP(MAX_CONNECTIONS)]; /* Bluetooth stack configuration parameters (see "UG136: Silicon Labs Bluetooth C Application Developer's Guide" for details on each parameter) */ static gecko_configuration_t config = { .config_flags = 0, /* Check flag options from UG136 */ #if defined(FEATURE_LFXO) .sleep.flags = SLEEP_FLAGS_DEEP_SLEEP_ENABLE, /* Sleep is enabled */ #else .sleep.flags = 0, #endif // LFXO .bluetooth.max_connections = MAX_CONNECTIONS, /* Maximum number of simultaneous connections */ .bluetooth.max_advertisers = MAX_ADVERTISERS, /* Maximum number of advertisement sets */ .bluetooth.heap = bluetooth_stack_heap, /* Bluetooth stack memory for connection management */ .bluetooth.heap_size = sizeof(bluetooth_stack_heap), /* Bluetooth stack memory for connection management */ .bluetooth.sleep_clock_accuracy = 100, /* Accuracy of the Low Frequency Crystal Oscillator in ppm. * * Do not modify if you are using a module */ .gattdb = &bg_gattdb_data, /* Pointer to GATT database */ .ota.flags = 0, /* Check flag options from UG136 */ .ota.device_name_len = 3, /* Length of the device name in OTA DFU mode */ .ota.device_name_ptr = "OTA", /* Device name in OTA DFU mode */ #if (HAL_PA_ENABLE) .pa.config_enable = 1, /* Set this to be a valid PA config */ #if defined(FEATURE_PA_INPUT_FROM_VBAT) .pa.input = GECKO_RADIO_PA_INPUT_VBAT, /* Configure PA input to VBAT */ |
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#include "init_board.h" #include "init_app.h" #include "ble-configuration.h" #include "board_features.h" /* Bluetooth stack headers */ #include "bg_types.h" #include "micca_gecko.h" #include "gatt_db.h" /* Libraries containing default Gecko configuration values */ #include "em_emu.h" #include "em_cmu.h" /* Device initialization header */ ................................................................................ #ifndef MAX_CONNECTIONS #define MAX_CONNECTIONS 4 #endif uint8_t bluetooth_stack_heap[DEFAULT_BLUETOOTH_HEAP(MAX_CONNECTIONS)]; extern void micca_schedule_link(void) ; extern void micca_schedule_stack(void) ; /* Bluetooth stack configuration parameters (see "UG136: Silicon Labs Bluetooth C Application Developer's Guide" for details on each parameter) */ static gecko_configuration_t config = { // .config_flags = GECKO_CONFIG_FLAG_RTOS, /* Check flag options from UG136 */ .config_flags = 0, /* * N.B. we are setting the RTOS flag because we are * running with the micca run-time (which is not * really and RTOS) and we don't want the bluetooth * stack to undertake additional configuration. */ #if defined(FEATURE_LFXO) .sleep.flags = SLEEP_FLAGS_DEEP_SLEEP_ENABLE, /* Sleep is enabled */ #else .sleep.flags = 0, #endif // LFXO .bluetooth.max_connections = MAX_CONNECTIONS, /* Maximum number of simultaneous connections */ .bluetooth.max_advertisers = MAX_ADVERTISERS, /* Maximum number of advertisement sets */ .bluetooth.heap = bluetooth_stack_heap, /* Bluetooth stack memory for connection management */ .bluetooth.heap_size = sizeof(bluetooth_stack_heap), /* Bluetooth stack memory for connection management */ .bluetooth.sleep_clock_accuracy = 100, /* Accuracy of the Low Frequency Crystal Oscillator in ppm. * * Do not modify if you are using a module */ .gattdb = &bg_gattdb_data, /* Pointer to GATT database */ .scheduler_callback = micca_schedule_link, /* IRQ level function to cause link handling */ .stack_schedule_callback = micca_schedule_stack, /* IRQ level function to cause stack handling */ .ota.flags = 0, /* Check flag options from UG136 */ .ota.device_name_len = 3, /* Length of the device name in OTA DFU mode */ .ota.device_name_ptr = "OTA", /* Device name in OTA DFU mode */ #if (HAL_PA_ENABLE) .pa.config_enable = 1, /* Set this to be a valid PA config */ #if defined(FEATURE_PA_INPUT_FROM_VBAT) .pa.input = GECKO_RADIO_PA_INPUT_VBAT, /* Configure PA input to VBAT */ |
Changes to Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/micca_rt.c.
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*/ #include "micca_rt.h" #include "micca_rt_internal.h" #include "em_device.h" #include "em_cmu.h" #include "em_letimer.h" #include "em_core.h" #include "sleep.h" /* * Constants */ #define MRT_DELAY_EXPIRED UINT32_MAX #define MRT_PENDSV_PRIORITY 0xff /* ................................................................................ #endif /* MRT_NO_NAMES */ #endif /* MRT_NO_STDIO */ static char const * mrtTimestamp(void) { static char tsbuf[16] ; uint32_t ts = 0 ; // HERE -- for now, no BURTC in EFR32MG snprintf(tsbuf, sizeof(tsbuf), "%03lu.%03lu", ts / 1000, ts % 1000) ; // <1> return tsbuf ; } # endif /* MRT_NO_TRACE */ static inline MRT_DelayTime ................................................................................ return (LETIMER_RepeatGet(LETIMER0, 0) << 16) | LETIMER_CounterGet(LETIMER0) ; } static bool mrtCheckEmptyEventQueue( SLEEP_EnergyMode_t emode) // not used { return mrtEventQueueEmpty(&tocEventQueue) ; } static void mrtPlatformInit(void) { SLEEP_Init_t sleepConfig = { .sleepCallback = mrtCheckEmptyEventQueue, .wakeupCallback = NULL, |
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*/ #include "micca_rt.h" #include "micca_rt_internal.h" #include "em_device.h" #include "em_cmu.h" #include "em_letimer.h" #include "em_rtcc.h" #include "em_core.h" #include "sleep.h" #if !(defined(MRT_NO_TRACE) || defined(MRT_NO_STDIO)) # include "retargetserial.h" #endif /* !defined(MRT_NO_TRACE) && !defined(MRT_NO_STDIO) */ /* * Constants */ #define MRT_DELAY_EXPIRED UINT32_MAX #define MRT_PENDSV_PRIORITY 0xff /* ................................................................................ #endif /* MRT_NO_NAMES */ #endif /* MRT_NO_STDIO */ static char const * mrtTimestamp(void) { static char tsbuf[16] ; uint32_t ts = RTCC_CounterGet() ; // just to have something snprintf(tsbuf, sizeof(tsbuf), "%03lu.%03lu", ts / 1000, ts % 1000) ; // <1> return tsbuf ; } # endif /* MRT_NO_TRACE */ static inline MRT_DelayTime ................................................................................ return (LETIMER_RepeatGet(LETIMER0, 0) << 16) | LETIMER_CounterGet(LETIMER0) ; } static bool mrtCheckEmptyEventQueue( SLEEP_EnergyMode_t emode) // not used { bool isEmpty = mrtEventQueueEmpty(&tocEventQueue) ; # if !(defined(MRT_NO_TRACE) || defined(MRT_NO_STDIO)) /* * Flush out traces before we go to sleep. */ if (isEmpty) { RETARGET_SerialFlush() ; } # endif /* !defined(MRT_NO_TRACE) && !defined(MRT_NO_STDIO) */ return isEmpty ; } static void mrtPlatformInit(void) { SLEEP_Init_t sleepConfig = { .sleepCallback = mrtCheckEmptyEventQueue, .wakeupCallback = NULL, |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/CMSIS/Include/arm_common_tables.h.
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/* ---------------------------------------------------------------------- * Project: CMSIS DSP Library * Title: arm_common_tables.h * Description: Extern declaration for common tables * * $Date: 27. January 2017 * $Revision: V.1.5.1 * * Target Processor: Cortex-M cores * -------------------------------------------------------------------- */ /* * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef _ARM_COMMON_TABLES_H #define _ARM_COMMON_TABLES_H #include "arm_math.h" extern const uint16_t armBitRevTable[1024]; extern const q15_t armRecipTableQ15[64]; extern const q31_t armRecipTableQ31[64]; extern const float32_t twiddleCoef_16[32]; extern const float32_t twiddleCoef_32[64]; extern const float32_t twiddleCoef_64[128]; extern const float32_t twiddleCoef_128[256]; extern const float32_t twiddleCoef_256[512]; extern const float32_t twiddleCoef_512[1024]; extern const float32_t twiddleCoef_1024[2048]; extern const float32_t twiddleCoef_2048[4096]; extern const float32_t twiddleCoef_4096[8192]; #define twiddleCoef twiddleCoef_4096 extern const q31_t twiddleCoef_16_q31[24]; extern const q31_t twiddleCoef_32_q31[48]; extern const q31_t twiddleCoef_64_q31[96]; extern const q31_t twiddleCoef_128_q31[192]; extern const q31_t twiddleCoef_256_q31[384]; extern const q31_t twiddleCoef_512_q31[768]; extern const q31_t twiddleCoef_1024_q31[1536]; extern const q31_t twiddleCoef_2048_q31[3072]; extern const q31_t twiddleCoef_4096_q31[6144]; extern const q15_t twiddleCoef_16_q15[24]; extern const q15_t twiddleCoef_32_q15[48]; extern const q15_t twiddleCoef_64_q15[96]; extern const q15_t twiddleCoef_128_q15[192]; extern const q15_t twiddleCoef_256_q15[384]; extern const q15_t twiddleCoef_512_q15[768]; extern const q15_t twiddleCoef_1024_q15[1536]; extern const q15_t twiddleCoef_2048_q15[3072]; extern const q15_t twiddleCoef_4096_q15[6144]; extern const float32_t twiddleCoef_rfft_32[32]; extern const float32_t twiddleCoef_rfft_64[64]; extern const float32_t twiddleCoef_rfft_128[128]; extern const float32_t twiddleCoef_rfft_256[256]; extern const float32_t twiddleCoef_rfft_512[512]; extern const float32_t twiddleCoef_rfft_1024[1024]; extern const float32_t twiddleCoef_rfft_2048[2048]; extern const float32_t twiddleCoef_rfft_4096[4096]; /* floating-point bit reversal tables */ #define ARMBITREVINDEXTABLE_16_TABLE_LENGTH ((uint16_t)20) #define ARMBITREVINDEXTABLE_32_TABLE_LENGTH ((uint16_t)48) #define ARMBITREVINDEXTABLE_64_TABLE_LENGTH ((uint16_t)56) #define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208) #define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440) #define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448) #define ARMBITREVINDEXTABLE_1024_TABLE_LENGTH ((uint16_t)1800) #define ARMBITREVINDEXTABLE_2048_TABLE_LENGTH ((uint16_t)3808) #define ARMBITREVINDEXTABLE_4096_TABLE_LENGTH ((uint16_t)4032) extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE_16_TABLE_LENGTH]; extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE_32_TABLE_LENGTH]; extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE_64_TABLE_LENGTH]; extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH]; extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH]; extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH]; extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE_1024_TABLE_LENGTH]; extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE_2048_TABLE_LENGTH]; extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE_4096_TABLE_LENGTH]; /* fixed-point bit reversal tables */ #define ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH ((uint16_t)12) #define ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH ((uint16_t)24) #define ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH ((uint16_t)56) #define ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH ((uint16_t)112) #define ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH ((uint16_t)240) #define ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH ((uint16_t)480) #define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992) #define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984) #define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032) extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH]; extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH]; extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH]; extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH]; extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH]; extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH]; extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH]; extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH]; extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH]; /* Tables for Fast Math Sine and Cosine */ extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1]; extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1]; extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1]; #endif /* ARM_COMMON_TABLES_H */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/CMSIS/Include/arm_const_structs.h.
> > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > |
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/* ---------------------------------------------------------------------- * Project: CMSIS DSP Library * Title: arm_const_structs.h * Description: Constant structs that are initialized for user convenience. * For example, some can be given as arguments to the arm_cfft_f32() function. * * $Date: 27. January 2017 * $Revision: V.1.5.1 * * Target Processor: Cortex-M cores * -------------------------------------------------------------------- */ /* * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef _ARM_CONST_STRUCTS_H #define _ARM_CONST_STRUCTS_H #include "arm_math.h" #include "arm_common_tables.h" extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16; extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32; extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64; extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128; extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256; extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512; extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024; extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048; extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096; extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16; extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32; extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64; extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128; extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256; extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512; extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024; extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048; extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096; extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16; extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32; extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64; extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128; extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256; extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512; extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024; extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048; extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096; #endif |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/CMSIS/Include/arm_math.h.
> > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > 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/****************************************************************************** * @file arm_math.h * @brief Public header file for CMSIS DSP LibraryU * @version V1.5.3 * @date 10. January 2018 ******************************************************************************/ /* * Copyright (c) 2010-2018 Arm Limited or its affiliates. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ /** \mainpage CMSIS DSP Software Library * * Introduction * ------------ * * This user manual describes the CMSIS DSP software library, * a suite of common signal processing functions for use on Cortex-M processor based devices. * * The library is divided into a number of functions each covering a specific category: * - Basic math functions * - Fast math functions * - Complex math functions * - Filters * - Matrix functions * - Transforms * - Motor control functions * - Statistical functions * - Support functions * - Interpolation functions * * The library has separate functions for operating on 8-bit integers, 16-bit integers, * 32-bit integer and 32-bit floating-point values. * * Using the Library * ------------ * * The library installer contains prebuilt versions of the libraries in the <code>Lib</code> folder. * - arm_cortexM7lfdp_math.lib (Cortex-M7, Little endian, Double Precision Floating Point Unit) * - arm_cortexM7bfdp_math.lib (Cortex-M7, Big endian, Double Precision Floating Point Unit) * - arm_cortexM7lfsp_math.lib (Cortex-M7, Little endian, Single Precision Floating Point Unit) * - arm_cortexM7bfsp_math.lib (Cortex-M7, Big endian and Single Precision Floating Point Unit on) * - arm_cortexM7l_math.lib (Cortex-M7, Little endian) * - arm_cortexM7b_math.lib (Cortex-M7, Big endian) * - arm_cortexM4lf_math.lib (Cortex-M4, Little endian, Floating Point Unit) * - arm_cortexM4bf_math.lib (Cortex-M4, Big endian, Floating Point Unit) * - arm_cortexM4l_math.lib (Cortex-M4, Little endian) * - arm_cortexM4b_math.lib (Cortex-M4, Big endian) * - arm_cortexM3l_math.lib (Cortex-M3, Little endian) * - arm_cortexM3b_math.lib (Cortex-M3, Big endian) * - arm_cortexM0l_math.lib (Cortex-M0 / Cortex-M0+, Little endian) * - arm_cortexM0b_math.lib (Cortex-M0 / Cortex-M0+, Big endian) * - arm_ARMv8MBLl_math.lib (Armv8-M Baseline, Little endian) * - arm_ARMv8MMLl_math.lib (Armv8-M Mainline, Little endian) * - arm_ARMv8MMLlfsp_math.lib (Armv8-M Mainline, Little endian, Single Precision Floating Point Unit) * - arm_ARMv8MMLld_math.lib (Armv8-M Mainline, Little endian, DSP instructions) * - arm_ARMv8MMLldfsp_math.lib (Armv8-M Mainline, Little endian, DSP instructions, Single Precision Floating Point Unit) * * The library functions are declared in the public file <code>arm_math.h</code> which is placed in the <code>Include</code> folder. * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single * public header file <code> arm_math.h</code> for Cortex-M cores with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. * Define the appropriate preprocessor macro ARM_MATH_CM7 or ARM_MATH_CM4 or ARM_MATH_CM3 or * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application. * For Armv8-M cores define preprocessor macro ARM_MATH_ARMV8MBL or ARM_MATH_ARMV8MML. * Set preprocessor macro __DSP_PRESENT if Armv8-M Mainline core supports DSP instructions. * * * Examples * -------- * * The library ships with a number of examples which demonstrate how to use the library functions. * * Toolchain Support * ------------ * * The library has been developed and tested with MDK version 5.14.0.0 * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly. * * Building the Library * ------------ * * The library installer contains a project file to rebuild libraries on MDK toolchain in the <code>CMSIS\\DSP_Lib\\Source\\ARM</code> folder. * - arm_cortexM_math.uvprojx * * * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional preprocessor macros detailed above. * * Preprocessor Macros * ------------ * * Each library project have different preprocessor macros. * * - UNALIGNED_SUPPORT_DISABLE: * * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access * * - ARM_MATH_BIG_ENDIAN: * * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets. * * - ARM_MATH_MATRIX_CHECK: * * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices * * - ARM_MATH_ROUNDING: * * Define macro ARM_MATH_ROUNDING for rounding on support functions * * - ARM_MATH_CMx: * * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target * and ARM_MATH_CM0 for building library on Cortex-M0 target, ARM_MATH_CM0PLUS for building library on Cortex-M0+ target, and * ARM_MATH_CM7 for building the library on cortex-M7. * * - ARM_MATH_ARMV8MxL: * * Define macro ARM_MATH_ARMV8MBL for building the library on Armv8-M Baseline target, ARM_MATH_ARMV8MML for building library * on Armv8-M Mainline target. * * - __FPU_PRESENT: * * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for floating point libraries. * * - __DSP_PRESENT: * * Initialize macro __DSP_PRESENT = 1 when Armv8-M Mainline core supports DSP instructions. * * <hr> * CMSIS-DSP in ARM::CMSIS Pack * ----------------------------- * * The following files relevant to CMSIS-DSP are present in the <b>ARM::CMSIS</b> Pack directories: * |File/Folder |Content | * |------------------------------|------------------------------------------------------------------------| * |\b CMSIS\\Documentation\\DSP | This documentation | * |\b CMSIS\\DSP_Lib | Software license agreement (license.txt) | * |\b CMSIS\\DSP_Lib\\Examples | Example projects demonstrating the usage of the library functions | * |\b CMSIS\\DSP_Lib\\Source | Source files for rebuilding the library | * * <hr> * Revision History of CMSIS-DSP * ------------ * Please refer to \ref ChangeLog_pg. * * Copyright Notice * ------------ * * Copyright (C) 2010-2015 Arm Limited. All rights reserved. */ /** * @defgroup groupMath Basic Math Functions */ /** * @defgroup groupFastMath Fast Math Functions * This set of functions provides a fast approximation to sine, cosine, and square root. * As compared to most of the other functions in the CMSIS math library, the fast math functions * operate on individual values and not arrays. * There are separate functions for Q15, Q31, and floating-point data. * */ /** * @defgroup groupCmplxMath Complex Math Functions * This set of functions operates on complex data vectors. * The data in the complex arrays is stored in an interleaved fashion * (real, imag, real, imag, ...). * In the API functions, the number of samples in a complex array refers * to the number of complex values; the array contains twice this number of * real values. */ /** * @defgroup groupFilters Filtering Functions */ /** * @defgroup groupMatrix Matrix Functions * * This set of functions provides basic matrix math operations. * The functions operate on matrix data structures. For example, * the type * definition for the floating-point matrix structure is shown * below: * <pre> * typedef struct * { * uint16_t numRows; // number of rows of the matrix. * uint16_t numCols; // number of columns of the matrix. * float32_t *pData; // points to the data of the matrix. * } arm_matrix_instance_f32; * </pre> * There are similar definitions for Q15 and Q31 data types. * * The structure specifies the size of the matrix and then points to * an array of data. The array is of size <code>numRows X numCols</code> * and the values are arranged in row order. That is, the * matrix element (i, j) is stored at: * <pre> * pData[i*numCols + j] * </pre> * * \par Init Functions * There is an associated initialization function for each type of matrix * data structure. * The initialization function sets the values of the internal structure fields. * Refer to the function <code>arm_mat_init_f32()</code>, <code>arm_mat_init_q31()</code> * and <code>arm_mat_init_q15()</code> for floating-point, Q31 and Q15 types, respectively. * * \par * Use of the initialization function is optional. However, if initialization function is used * then the instance structure cannot be placed into a const data section. * To place the instance structure in a const data * section, manually initialize the data structure. For example: * <pre> * <code>arm_matrix_instance_f32 S = {nRows, nColumns, pData};</code> * <code>arm_matrix_instance_q31 S = {nRows, nColumns, pData};</code> * <code>arm_matrix_instance_q15 S = {nRows, nColumns, pData};</code> * </pre> * where <code>nRows</code> specifies the number of rows, <code>nColumns</code> * specifies the number of columns, and <code>pData</code> points to the * data array. * * \par Size Checking * By default all of the matrix functions perform size checking on the input and * output matrices. For example, the matrix addition function verifies that the * two input matrices and the output matrix all have the same number of rows and * columns. If the size check fails the functions return: * <pre> * ARM_MATH_SIZE_MISMATCH * </pre> * Otherwise the functions return * <pre> * ARM_MATH_SUCCESS * </pre> * There is some overhead associated with this matrix size checking. * The matrix size checking is enabled via the \#define * <pre> * ARM_MATH_MATRIX_CHECK * </pre> * within the library project settings. By default this macro is defined * and size checking is enabled. By changing the project settings and * undefining this macro size checking is eliminated and the functions * run a bit faster. With size checking disabled the functions always * return <code>ARM_MATH_SUCCESS</code>. */ /** * @defgroup groupTransforms Transform Functions */ /** * @defgroup groupController Controller Functions */ /** * @defgroup groupStats Statistics Functions */ /** * @defgroup groupSupport Support Functions */ /** * @defgroup groupInterpolation Interpolation Functions * These functions perform 1- and 2-dimensional interpolation of data. * Linear interpolation is used for 1-dimensional data and * bilinear interpolation is used for 2-dimensional data. */ /** * @defgroup groupExamples Examples */ #ifndef _ARM_MATH_H #define _ARM_MATH_H /* Compiler specific diagnostic adjustment */ #if defined ( __CC_ARM ) #elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) #elif defined ( __GNUC__ ) #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wsign-conversion" #pragma GCC diagnostic ignored "-Wconversion" #pragma GCC diagnostic ignored "-Wunused-parameter" #elif defined ( __ICCARM__ ) #elif defined ( __TI_ARM__ ) #elif defined ( __CSMC__ ) #elif defined ( __TASKING__ ) #else #error Unknown compiler #endif #define __CMSIS_GENERIC /* disable NVIC and Systick functions */ #if defined(ARM_MATH_CM7) #include "core_cm7.h" #define ARM_MATH_DSP #elif defined (ARM_MATH_CM4) #include "core_cm4.h" #define ARM_MATH_DSP #elif defined (ARM_MATH_CM3) #include "core_cm3.h" #elif defined (ARM_MATH_CM0) #include "core_cm0.h" #define ARM_MATH_CM0_FAMILY #elif defined (ARM_MATH_CM0PLUS) #include "core_cm0plus.h" #define ARM_MATH_CM0_FAMILY #elif defined (ARM_MATH_ARMV8MBL) #include "core_armv8mbl.h" #define ARM_MATH_CM0_FAMILY #elif defined (ARM_MATH_ARMV8MML) #include "core_armv8mml.h" #if (defined (__DSP_PRESENT) && (__DSP_PRESENT == 1)) #define ARM_MATH_DSP #endif #else #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS, ARM_MATH_CM0, ARM_MATH_ARMV8MBL, ARM_MATH_ARMV8MML" #endif #undef __CMSIS_GENERIC /* enable NVIC and Systick functions */ #include "string.h" #include "math.h" #ifdef __cplusplus extern "C" { #endif /** * @brief Macros required for reciprocal calculation in Normalized LMS */ #define DELTA_Q31 (0x100) #define DELTA_Q15 0x5 #define INDEX_MASK 0x0000003F #ifndef PI #define PI 3.14159265358979f #endif /** * @brief Macros required for SINE and COSINE Fast math approximations */ #define FAST_MATH_TABLE_SIZE 512 #define FAST_MATH_Q31_SHIFT (32 - 10) #define FAST_MATH_Q15_SHIFT (16 - 10) #define CONTROLLER_Q31_SHIFT (32 - 9) #define TABLE_SPACING_Q31 0x400000 #define TABLE_SPACING_Q15 0x80 /** * @brief Macros required for SINE and COSINE Controller functions */ /* 1.31(q31) Fixed value of 2/360 */ /* -1 to +1 is divided into 360 values so total spacing is (2/360) */ #define INPUT_SPACING 0xB60B61 /** * @brief Macro for Unaligned Support */ #ifndef UNALIGNED_SUPPORT_DISABLE #define ALIGN4 #else #if defined (__GNUC__) #define ALIGN4 __attribute__((aligned(4))) #else #define ALIGN4 __align(4) #endif #endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */ /** * @brief Error status returned by some functions in the library. */ typedef enum { ARM_MATH_SUCCESS = 0, /**< No error */ ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */ ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */ ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */ } arm_status; /** * @brief 8-bit fractional data type in 1.7 format. */ typedef int8_t q7_t; /** * @brief 16-bit fractional data type in 1.15 format. */ typedef int16_t q15_t; /** * @brief 32-bit fractional data type in 1.31 format. */ typedef int32_t q31_t; /** * @brief 64-bit fractional data type in 1.63 format. */ typedef int64_t q63_t; /** * @brief 32-bit floating-point type definition. */ typedef float float32_t; /** * @brief 64-bit floating-point type definition. */ typedef double float64_t; /** * @brief definition to read/write two 16 bit values. */ #if defined ( __CC_ARM ) #define __SIMD32_TYPE int32_t __packed #define CMSIS_UNUSED __attribute__((unused)) #define CMSIS_INLINE __attribute__((always_inline)) #elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) #define __SIMD32_TYPE int32_t #define CMSIS_UNUSED __attribute__((unused)) #define CMSIS_INLINE __attribute__((always_inline)) #elif defined ( __GNUC__ ) #define __SIMD32_TYPE int32_t #define CMSIS_UNUSED __attribute__((unused)) #define CMSIS_INLINE __attribute__((always_inline)) #elif defined ( __ICCARM__ ) #define __SIMD32_TYPE int32_t __packed #define CMSIS_UNUSED #define CMSIS_INLINE #elif defined ( __TI_ARM__ ) #define __SIMD32_TYPE int32_t #define CMSIS_UNUSED __attribute__((unused)) #define CMSIS_INLINE #elif defined ( __CSMC__ ) #define __SIMD32_TYPE int32_t #define CMSIS_UNUSED #define CMSIS_INLINE #elif defined ( __TASKING__ ) #define __SIMD32_TYPE __unaligned int32_t #define CMSIS_UNUSED #define CMSIS_INLINE #else #error Unknown compiler #endif #define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr)) #define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr)) #define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr)) #define __SIMD64(addr) (*(int64_t **) & (addr)) #if !defined (ARM_MATH_DSP) /** * @brief definition to pack two 16 bit values. */ #define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) ) #define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \ (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) ) #endif /* !defined (ARM_MATH_DSP) */ /** * @brief definition to pack four 8 bit values. */ #ifndef ARM_MATH_BIG_ENDIAN #define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ (((int32_t)(v3) << 24) & (int32_t)0xFF000000) ) #else #define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \ (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ (((int32_t)(v0) << 24) & (int32_t)0xFF000000) ) #endif /** * @brief Clips Q63 to Q31 values. */ CMSIS_INLINE __STATIC_INLINE q31_t clip_q63_to_q31( q63_t x) { return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x; } /** * @brief Clips Q63 to Q15 values. */ CMSIS_INLINE __STATIC_INLINE q15_t clip_q63_to_q15( q63_t x) { return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15); } /** * @brief Clips Q31 to Q7 values. */ CMSIS_INLINE __STATIC_INLINE q7_t clip_q31_to_q7( q31_t x) { return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ? ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x; } /** * @brief Clips Q31 to Q15 values. */ CMSIS_INLINE __STATIC_INLINE q15_t clip_q31_to_q15( q31_t x) { return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ? ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x; } /** * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format. */ CMSIS_INLINE __STATIC_INLINE q63_t mult32x64( q63_t x, q31_t y) { return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) + (((q63_t) (x >> 32) * y))); } /** * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type. */ CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q31( q31_t in, q31_t * dst, q31_t * pRecipTable) { q31_t out; uint32_t tempVal; uint32_t index, i; uint32_t signBits; if (in > 0) { signBits = ((uint32_t) (__CLZ( in) - 1)); } else { signBits = ((uint32_t) (__CLZ(-in) - 1)); } /* Convert input sample to 1.31 format */ in = (in << signBits); /* calculation of index for initial approximated Val */ index = (uint32_t)(in >> 24); index = (index & INDEX_MASK); /* 1.31 with exp 1 */ out = pRecipTable[index]; /* calculation of reciprocal value */ /* running approximation for two iterations */ for (i = 0U; i < 2U; i++) { tempVal = (uint32_t) (((q63_t) in * out) >> 31); tempVal = 0x7FFFFFFFu - tempVal; /* 1.31 with exp 1 */ /* out = (q31_t) (((q63_t) out * tempVal) >> 30); */ out = clip_q63_to_q31(((q63_t) out * tempVal) >> 30); } /* write output */ *dst = out; /* return num of signbits of out = 1/in value */ return (signBits + 1U); } /** * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type. */ CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q15( q15_t in, q15_t * dst, q15_t * pRecipTable) { q15_t out = 0; uint32_t tempVal = 0; uint32_t index = 0, i = 0; uint32_t signBits = 0; if (in > 0) { signBits = ((uint32_t)(__CLZ( in) - 17)); } else { signBits = ((uint32_t)(__CLZ(-in) - 17)); } /* Convert input sample to 1.15 format */ in = (in << signBits); /* calculation of index for initial approximated Val */ index = (uint32_t)(in >> 8); index = (index & INDEX_MASK); /* 1.15 with exp 1 */ out = pRecipTable[index]; /* calculation of reciprocal value */ /* running approximation for two iterations */ for (i = 0U; i < 2U; i++) { tempVal = (uint32_t) (((q31_t) in * out) >> 15); tempVal = 0x7FFFu - tempVal; /* 1.15 with exp 1 */ out = (q15_t) (((q31_t) out * tempVal) >> 14); /* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */ } /* write output */ *dst = out; /* return num of signbits of out = 1/in value */ return (signBits + 1); } /* * @brief C custom defined intrinsic function for M3 and M0 processors */ #if !defined (ARM_MATH_DSP) /* * @brief C custom defined QADD8 for M3 and M0 processors */ CMSIS_INLINE __STATIC_INLINE uint32_t __QADD8( uint32_t x, uint32_t y) { q31_t r, s, t, u; r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; t = __SSAT(((((q31_t)x << 8) >> 24) + (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; u = __SSAT(((((q31_t)x ) >> 24) + (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); } /* * @brief C custom defined QSUB8 for M3 and M0 processors */ CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB8( uint32_t x, uint32_t y) { q31_t r, s, t, u; r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; t = __SSAT(((((q31_t)x << 8) >> 24) - (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; u = __SSAT(((((q31_t)x ) >> 24) - (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); } /* * @brief C custom defined QADD16 for M3 and M0 processors */ CMSIS_INLINE __STATIC_INLINE uint32_t __QADD16( uint32_t x, uint32_t y) { /* q31_t r, s; without initialisation 'arm_offset_q15 test' fails but 'intrinsic' tests pass! for armCC */ q31_t r = 0, s = 0; r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; return ((uint32_t)((s << 16) | (r ))); } /* * @brief C custom defined SHADD16 for M3 and M0 processors */ CMSIS_INLINE __STATIC_INLINE uint32_t __SHADD16( uint32_t x, uint32_t y) { q31_t r, s; r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; s = (((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; return ((uint32_t)((s << 16) | (r ))); } /* * @brief C custom defined QSUB16 for M3 and M0 processors */ CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB16( uint32_t x, uint32_t y) { q31_t r, s; r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; return ((uint32_t)((s << 16) | (r ))); } /* * @brief C custom defined SHSUB16 for M3 and M0 processors */ CMSIS_INLINE __STATIC_INLINE uint32_t __SHSUB16( uint32_t x, uint32_t y) { q31_t r, s; r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; s = (((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; return ((uint32_t)((s << 16) | (r ))); } /* * @brief C custom defined QASX for M3 and M0 processors */ CMSIS_INLINE __STATIC_INLINE uint32_t __QASX( uint32_t x, uint32_t y) { q31_t r, s; r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; return ((uint32_t)((s << 16) | (r ))); } /* * @brief C custom defined SHASX for M3 and M0 processors */ CMSIS_INLINE __STATIC_INLINE uint32_t __SHASX( uint32_t x, uint32_t y) { q31_t r, s; r = (((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; s = (((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; return ((uint32_t)((s << 16) | (r ))); } /* * @brief C custom defined QSAX for M3 and M0 processors */ CMSIS_INLINE __STATIC_INLINE uint32_t __QSAX( uint32_t x, uint32_t y) { q31_t r, s; r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; return ((uint32_t)((s << 16) | (r ))); } /* * @brief C custom defined SHSAX for M3 and M0 processors */ CMSIS_INLINE __STATIC_INLINE uint32_t __SHSAX( uint32_t x, uint32_t y) { q31_t r, s; r = (((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; s = (((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; return ((uint32_t)((s << 16) | (r ))); } /* * @brief C custom defined SMUSDX for M3 and M0 processors */ CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSDX( uint32_t x, uint32_t y) { return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); } /* * @brief C custom defined SMUADX for M3 and M0 processors */ CMSIS_INLINE __STATIC_INLINE uint32_t __SMUADX( uint32_t x, uint32_t y) { return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); } /* * @brief C custom defined QADD for M3 and M0 processors */ CMSIS_INLINE __STATIC_INLINE int32_t __QADD( int32_t x, int32_t y) { return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y))); } /* * @brief C custom defined QSUB for M3 and M0 processors */ CMSIS_INLINE __STATIC_INLINE int32_t __QSUB( int32_t x, int32_t y) { return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y))); } /* * @brief C custom defined SMLAD for M3 and M0 processors */ CMSIS_INLINE __STATIC_INLINE uint32_t __SMLAD( uint32_t x, uint32_t y, uint32_t sum) { return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + ( ((q31_t)sum ) ) )); } /* * @brief C custom defined SMLADX for M3 and M0 processors */ CMSIS_INLINE __STATIC_INLINE uint32_t __SMLADX( uint32_t x, uint32_t y, uint32_t sum) { return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + ( ((q31_t)sum ) ) )); } /* * @brief C custom defined SMLSDX for M3 and M0 processors */ CMSIS_INLINE __STATIC_INLINE uint32_t __SMLSDX( uint32_t x, uint32_t y, uint32_t sum) { return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + ( ((q31_t)sum ) ) )); } /* * @brief C custom defined SMLALD for M3 and M0 processors */ CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALD( uint32_t x, uint32_t y, uint64_t sum) { /* return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */ return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + ( ((q63_t)sum ) ) )); } /* * @brief C custom defined SMLALDX for M3 and M0 processors */ CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALDX( uint32_t x, uint32_t y, uint64_t sum) { /* return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */ return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + ( ((q63_t)sum ) ) )); } /* * @brief C custom defined SMUAD for M3 and M0 processors */ CMSIS_INLINE __STATIC_INLINE uint32_t __SMUAD( uint32_t x, uint32_t y) { return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); } /* * @brief C custom defined SMUSD for M3 and M0 processors */ CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSD( uint32_t x, uint32_t y) { return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) - ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); } /* * @brief C custom defined SXTB16 for M3 and M0 processors */ CMSIS_INLINE __STATIC_INLINE uint32_t __SXTB16( uint32_t x) { return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) | ((((q31_t)x << 8) >> 8) & (q31_t)0xFFFF0000) )); } /* * @brief C custom defined SMMLA for M3 and M0 processors */ CMSIS_INLINE __STATIC_INLINE int32_t __SMMLA( int32_t x, int32_t y, int32_t sum) { return (sum + (int32_t) (((int64_t) x * y) >> 32)); } #endif /* !defined (ARM_MATH_DSP) */ /** * @brief Instance structure for the Q7 FIR filter. */ typedef struct { uint16_t numTaps; /**< number of filter coefficients in the filter. */ q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ } arm_fir_instance_q7; /** * @brief Instance structure for the Q15 FIR filter. */ typedef struct { uint16_t numTaps; /**< number of filter coefficients in the filter. */ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ } arm_fir_instance_q15; /** * @brief Instance structure for the Q31 FIR filter. */ typedef struct { uint16_t numTaps; /**< number of filter coefficients in the filter. */ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ } arm_fir_instance_q31; /** * @brief Instance structure for the floating-point FIR filter. */ typedef struct { uint16_t numTaps; /**< number of filter coefficients in the filter. */ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ } arm_fir_instance_f32; /** * @brief Processing function for the Q7 FIR filter. * @param[in] S points to an instance of the Q7 FIR filter structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data. * @param[in] blockSize number of samples to process. */ void arm_fir_q7( const arm_fir_instance_q7 * S, q7_t * pSrc, q7_t * pDst, uint32_t blockSize); /** * @brief Initialization function for the Q7 FIR filter. * @param[in,out] S points to an instance of the Q7 FIR structure. * @param[in] numTaps Number of filter coefficients in the filter. * @param[in] pCoeffs points to the filter coefficients. * @param[in] pState points to the state buffer. * @param[in] blockSize number of samples that are processed. */ void arm_fir_init_q7( arm_fir_instance_q7 * S, uint16_t numTaps, q7_t * pCoeffs, q7_t * pState, uint32_t blockSize); /** * @brief Processing function for the Q15 FIR filter. * @param[in] S points to an instance of the Q15 FIR structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data. * @param[in] blockSize number of samples to process. */ void arm_fir_q15( const arm_fir_instance_q15 * S, q15_t * pSrc, q15_t * pDst, uint32_t blockSize); /** * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4. * @param[in] S points to an instance of the Q15 FIR filter structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data. * @param[in] blockSize number of samples to process. */ void arm_fir_fast_q15( const arm_fir_instance_q15 * S, q15_t * pSrc, q15_t * pDst, uint32_t blockSize); /** * @brief Initialization function for the Q15 FIR filter. * @param[in,out] S points to an instance of the Q15 FIR filter structure. * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4. * @param[in] pCoeffs points to the filter coefficients. * @param[in] pState points to the state buffer. * @param[in] blockSize number of samples that are processed at a time. * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if * <code>numTaps</code> is not a supported value. */ arm_status arm_fir_init_q15( arm_fir_instance_q15 * S, uint16_t numTaps, q15_t * pCoeffs, q15_t * pState, uint32_t blockSize); /** * @brief Processing function for the Q31 FIR filter. * @param[in] S points to an instance of the Q31 FIR filter structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data. * @param[in] blockSize number of samples to process. */ void arm_fir_q31( const arm_fir_instance_q31 * S, q31_t * pSrc, q31_t * pDst, uint32_t blockSize); /** * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4. * @param[in] S points to an instance of the Q31 FIR structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data. * @param[in] blockSize number of samples to process. */ void arm_fir_fast_q31( const arm_fir_instance_q31 * S, q31_t * pSrc, q31_t * pDst, uint32_t blockSize); /** * @brief Initialization function for the Q31 FIR filter. * @param[in,out] S points to an instance of the Q31 FIR structure. * @param[in] numTaps Number of filter coefficients in the filter. * @param[in] pCoeffs points to the filter coefficients. * @param[in] pState points to the state buffer. * @param[in] blockSize number of samples that are processed at a time. */ void arm_fir_init_q31( arm_fir_instance_q31 * S, uint16_t numTaps, q31_t * pCoeffs, q31_t * pState, uint32_t blockSize); /** * @brief Processing function for the floating-point FIR filter. * @param[in] S points to an instance of the floating-point FIR structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data. * @param[in] blockSize number of samples to process. */ void arm_fir_f32( const arm_fir_instance_f32 * S, float32_t * pSrc, float32_t * pDst, uint32_t blockSize); /** * @brief Initialization function for the floating-point FIR filter. * @param[in,out] S points to an instance of the floating-point FIR filter structure. * @param[in] numTaps Number of filter coefficients in the filter. * @param[in] pCoeffs points to the filter coefficients. * @param[in] pState points to the state buffer. * @param[in] blockSize number of samples that are processed at a time. */ void arm_fir_init_f32( arm_fir_instance_f32 * S, uint16_t numTaps, float32_t * pCoeffs, float32_t * pState, uint32_t blockSize); /** * @brief Instance structure for the Q15 Biquad cascade filter. */ typedef struct { int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ } arm_biquad_casd_df1_inst_q15; /** * @brief Instance structure for the Q31 Biquad cascade filter. */ typedef struct { uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ } arm_biquad_casd_df1_inst_q31; /** * @brief Instance structure for the floating-point Biquad cascade filter. */ typedef struct { uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ } arm_biquad_casd_df1_inst_f32; /** * @brief Processing function for the Q15 Biquad cascade filter. * @param[in] S points to an instance of the Q15 Biquad cascade structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data. * @param[in] blockSize number of samples to process. */ void arm_biquad_cascade_df1_q15( const arm_biquad_casd_df1_inst_q15 * S, q15_t * pSrc, q15_t * pDst, uint32_t blockSize); /** * @brief Initialization function for the Q15 Biquad cascade filter. * @param[in,out] S points to an instance of the Q15 Biquad cascade structure. * @param[in] numStages number of 2nd order stages in the filter. * @param[in] pCoeffs points to the filter coefficients. * @param[in] pState points to the state buffer. * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format */ void arm_biquad_cascade_df1_init_q15( arm_biquad_casd_df1_inst_q15 * S, uint8_t numStages, q15_t * pCoeffs, q15_t * pState, int8_t postShift); /** * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4. * @param[in] S points to an instance of the Q15 Biquad cascade structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data. * @param[in] blockSize number of samples to process. */ void arm_biquad_cascade_df1_fast_q15( const arm_biquad_casd_df1_inst_q15 * S, q15_t * pSrc, q15_t * pDst, uint32_t blockSize); /** * @brief Processing function for the Q31 Biquad cascade filter * @param[in] S points to an instance of the Q31 Biquad cascade structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data. * @param[in] blockSize number of samples to process. */ void arm_biquad_cascade_df1_q31( const arm_biquad_casd_df1_inst_q31 * S, q31_t * pSrc, q31_t * pDst, uint32_t blockSize); /** * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4. * @param[in] S points to an instance of the Q31 Biquad cascade structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data. * @param[in] blockSize number of samples to process. */ void arm_biquad_cascade_df1_fast_q31( const arm_biquad_casd_df1_inst_q31 * S, q31_t * pSrc, q31_t * pDst, uint32_t blockSize); /** * @brief Initialization function for the Q31 Biquad cascade filter. * @param[in,out] S points to an instance of the Q31 Biquad cascade structure. * @param[in] numStages number of 2nd order stages in the filter. * @param[in] pCoeffs points to the filter coefficients. * @param[in] pState points to the state buffer. * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format */ void arm_biquad_cascade_df1_init_q31( arm_biquad_casd_df1_inst_q31 * S, uint8_t numStages, q31_t * pCoeffs, q31_t * pState, int8_t postShift); /** * @brief Processing function for the floating-point Biquad cascade filter. * @param[in] S points to an instance of the floating-point Biquad cascade structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data. * @param[in] blockSize number of samples to process. */ void arm_biquad_cascade_df1_f32( const arm_biquad_casd_df1_inst_f32 * S, float32_t * pSrc, float32_t * pDst, uint32_t blockSize); /** * @brief Initialization function for the floating-point Biquad cascade filter. * @param[in,out] S points to an instance of the floating-point Biquad cascade structure. * @param[in] numStages number of 2nd order stages in the filter. * @param[in] pCoeffs points to the filter coefficients. * @param[in] pState points to the state buffer. */ void arm_biquad_cascade_df1_init_f32( arm_biquad_casd_df1_inst_f32 * S, uint8_t numStages, float32_t * pCoeffs, float32_t * pState); /** * @brief Instance structure for the floating-point matrix structure. */ typedef struct { uint16_t numRows; /**< number of rows of the matrix. */ uint16_t numCols; /**< number of columns of the matrix. */ float32_t *pData; /**< points to the data of the matrix. */ } arm_matrix_instance_f32; /** * @brief Instance structure for the floating-point matrix structure. */ typedef struct { uint16_t numRows; /**< number of rows of the matrix. */ uint16_t numCols; /**< number of columns of the matrix. */ float64_t *pData; /**< points to the data of the matrix. */ } arm_matrix_instance_f64; /** * @brief Instance structure for the Q15 matrix structure. */ typedef struct { uint16_t numRows; /**< number of rows of the matrix. */ uint16_t numCols; /**< number of columns of the matrix. */ q15_t *pData; /**< points to the data of the matrix. */ } arm_matrix_instance_q15; /** * @brief Instance structure for the Q31 matrix structure. */ typedef struct { uint16_t numRows; /**< number of rows of the matrix. */ uint16_t numCols; /**< number of columns of the matrix. */ q31_t *pData; /**< points to the data of the matrix. */ } arm_matrix_instance_q31; /** * @brief Floating-point matrix addition. * @param[in] pSrcA points to the first input matrix structure * @param[in] pSrcB points to the second input matrix structure * @param[out] pDst points to output matrix structure * @return The function returns either * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking. */ arm_status arm_mat_add_f32( const arm_matrix_instance_f32 * pSrcA, const arm_matrix_instance_f32 * pSrcB, arm_matrix_instance_f32 * pDst); /** * @brief Q15 matrix addition. * @param[in] pSrcA points to the first input matrix structure * @param[in] pSrcB points to the second input matrix structure * @param[out] pDst points to output matrix structure * @return The function returns either * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking. */ arm_status arm_mat_add_q15( const arm_matrix_instance_q15 * pSrcA, const arm_matrix_instance_q15 * pSrcB, arm_matrix_instance_q15 * pDst); /** * @brief Q31 matrix addition. * @param[in] pSrcA points to the first input matrix structure * @param[in] pSrcB points to the second input matrix structure * @param[out] pDst points to output matrix structure * @return The function returns either * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking. */ arm_status arm_mat_add_q31( const arm_matrix_instance_q31 * pSrcA, const arm_matrix_instance_q31 * pSrcB, arm_matrix_instance_q31 * pDst); /** * @brief Floating-point, complex, matrix multiplication. * @param[in] pSrcA points to the first input matrix structure * @param[in] pSrcB points to the second input matrix structure * @param[out] pDst points to output matrix structure * @return The function returns either * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking. */ arm_status arm_mat_cmplx_mult_f32( const arm_matrix_instance_f32 * pSrcA, const arm_matrix_instance_f32 * pSrcB, arm_matrix_instance_f32 * pDst); /** * @brief Q15, complex, matrix multiplication. * @param[in] pSrcA points to the first input matrix structure * @param[in] pSrcB points to the second input matrix structure * @param[out] pDst points to output matrix structure * @return The function returns either * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking. */ arm_status arm_mat_cmplx_mult_q15( const arm_matrix_instance_q15 * pSrcA, const arm_matrix_instance_q15 * pSrcB, arm_matrix_instance_q15 * pDst, q15_t * pScratch); /** * @brief Q31, complex, matrix multiplication. * @param[in] pSrcA points to the first input matrix structure * @param[in] pSrcB points to the second input matrix structure * @param[out] pDst points to output matrix structure * @return The function returns either * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking. */ arm_status arm_mat_cmplx_mult_q31( const arm_matrix_instance_q31 * pSrcA, const arm_matrix_instance_q31 * pSrcB, arm_matrix_instance_q31 * pDst); /** * @brief Floating-point matrix transpose. * @param[in] pSrc points to the input matrix * @param[out] pDst points to the output matrix * @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code> * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking. */ arm_status arm_mat_trans_f32( const arm_matrix_instance_f32 * pSrc, arm_matrix_instance_f32 * pDst); /** * @brief Q15 matrix transpose. * @param[in] pSrc points to the input matrix * @param[out] pDst points to the output matrix * @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code> * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking. */ arm_status arm_mat_trans_q15( const arm_matrix_instance_q15 * pSrc, arm_matrix_instance_q15 * pDst); /** * @brief Q31 matrix transpose. * @param[in] pSrc points to the input matrix * @param[out] pDst points to the output matrix * @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code> * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking. */ arm_status arm_mat_trans_q31( const arm_matrix_instance_q31 * pSrc, arm_matrix_instance_q31 * pDst); /** * @brief Floating-point matrix multiplication * @param[in] pSrcA points to the first input matrix structure * @param[in] pSrcB points to the second input matrix structure * @param[out] pDst points to output matrix structure * @return The function returns either * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking. */ arm_status arm_mat_mult_f32( const arm_matrix_instance_f32 * pSrcA, const arm_matrix_instance_f32 * pSrcB, arm_matrix_instance_f32 * pDst); /** * @brief Q15 matrix multiplication * @param[in] pSrcA points to the first input matrix structure * @param[in] pSrcB points to the second input matrix structure * @param[out] pDst points to output matrix structure * @param[in] pState points to the array for storing intermediate results * @return The function returns either * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking. */ arm_status arm_mat_mult_q15( const arm_matrix_instance_q15 * pSrcA, const arm_matrix_instance_q15 * pSrcB, arm_matrix_instance_q15 * pDst, q15_t * pState); /** * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 * @param[in] pSrcA points to the first input matrix structure * @param[in] pSrcB points to the second input matrix structure * @param[out] pDst points to output matrix structure * @param[in] pState points to the array for storing intermediate results * @return The function returns either * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking. */ arm_status arm_mat_mult_fast_q15( const arm_matrix_instance_q15 * pSrcA, const arm_matrix_instance_q15 * pSrcB, arm_matrix_instance_q15 * pDst, q15_t * pState); /** * @brief Q31 matrix multiplication * @param[in] pSrcA points to the first input matrix structure * @param[in] pSrcB points to the second input matrix structure * @param[out] pDst points to output matrix structure * @return The function returns either * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking. */ arm_status arm_mat_mult_q31( const arm_matrix_instance_q31 * pSrcA, const arm_matrix_instance_q31 * pSrcB, arm_matrix_instance_q31 * pDst); /** * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 * @param[in] pSrcA points to the first input matrix structure * @param[in] pSrcB points to the second input matrix structure * @param[out] pDst points to output matrix structure * @return The function returns either * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking. */ arm_status arm_mat_mult_fast_q31( const arm_matrix_instance_q31 * pSrcA, const arm_matrix_instance_q31 * pSrcB, arm_matrix_instance_q31 * pDst); /** * @brief Floating-point matrix subtraction * @param[in] pSrcA points to the first input matrix structure * @param[in] pSrcB points to the second input matrix structure * @param[out] pDst points to output matrix structure * @return The function returns either * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking. */ arm_status arm_mat_sub_f32( const arm_matrix_instance_f32 * pSrcA, const arm_matrix_instance_f32 * pSrcB, arm_matrix_instance_f32 * pDst); /** * @brief Q15 matrix subtraction * @param[in] pSrcA points to the first input matrix structure * @param[in] pSrcB points to the second input matrix structure * @param[out] pDst points to output matrix structure * @return The function returns either * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking. */ arm_status arm_mat_sub_q15( const arm_matrix_instance_q15 * pSrcA, const arm_matrix_instance_q15 * pSrcB, arm_matrix_instance_q15 * pDst); /** * @brief Q31 matrix subtraction * @param[in] pSrcA points to the first input matrix structure * @param[in] pSrcB points to the second input matrix structure * @param[out] pDst points to output matrix structure * @return The function returns either * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking. */ arm_status arm_mat_sub_q31( const arm_matrix_instance_q31 * pSrcA, const arm_matrix_instance_q31 * pSrcB, arm_matrix_instance_q31 * pDst); /** * @brief Floating-point matrix scaling. * @param[in] pSrc points to the input matrix * @param[in] scale scale factor * @param[out] pDst points to the output matrix * @return The function returns either * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking. */ arm_status arm_mat_scale_f32( const arm_matrix_instance_f32 * pSrc, float32_t scale, arm_matrix_instance_f32 * pDst); /** * @brief Q15 matrix scaling. * @param[in] pSrc points to input matrix * @param[in] scaleFract fractional portion of the scale factor * @param[in] shift number of bits to shift the result by * @param[out] pDst points to output matrix * @return The function returns either * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking. */ arm_status arm_mat_scale_q15( const arm_matrix_instance_q15 * pSrc, q15_t scaleFract, int32_t shift, arm_matrix_instance_q15 * pDst); /** * @brief Q31 matrix scaling. * @param[in] pSrc points to input matrix * @param[in] scaleFract fractional portion of the scale factor * @param[in] shift number of bits to shift the result by * @param[out] pDst points to output matrix structure * @return The function returns either * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking. */ arm_status arm_mat_scale_q31( const arm_matrix_instance_q31 * pSrc, q31_t scaleFract, int32_t shift, arm_matrix_instance_q31 * pDst); /** * @brief Q31 matrix initialization. * @param[in,out] S points to an instance of the floating-point matrix structure. * @param[in] nRows number of rows in the matrix. * @param[in] nColumns number of columns in the matrix. * @param[in] pData points to the matrix data array. */ void arm_mat_init_q31( arm_matrix_instance_q31 * S, uint16_t nRows, uint16_t nColumns, q31_t * pData); /** * @brief Q15 matrix initialization. * @param[in,out] S points to an instance of the floating-point matrix structure. * @param[in] nRows number of rows in the matrix. * @param[in] nColumns number of columns in the matrix. * @param[in] pData points to the matrix data array. */ void arm_mat_init_q15( arm_matrix_instance_q15 * S, uint16_t nRows, uint16_t nColumns, q15_t * pData); /** * @brief Floating-point matrix initialization. * @param[in,out] S points to an instance of the floating-point matrix structure. * @param[in] nRows number of rows in the matrix. * @param[in] nColumns number of columns in the matrix. * @param[in] pData points to the matrix data array. */ void arm_mat_init_f32( arm_matrix_instance_f32 * S, uint16_t nRows, uint16_t nColumns, float32_t * pData); /** * @brief Instance structure for the Q15 PID Control. */ typedef struct { q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ #if !defined (ARM_MATH_DSP) q15_t A1; q15_t A2; #else q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/ #endif q15_t state[3]; /**< The state array of length 3. */ q15_t Kp; /**< The proportional gain. */ q15_t Ki; /**< The integral gain. */ q15_t Kd; /**< The derivative gain. */ } arm_pid_instance_q15; /** * @brief Instance structure for the Q31 PID Control. */ typedef struct { q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ q31_t A2; /**< The derived gain, A2 = Kd . */ q31_t state[3]; /**< The state array of length 3. */ q31_t Kp; /**< The proportional gain. */ q31_t Ki; /**< The integral gain. */ q31_t Kd; /**< The derivative gain. */ } arm_pid_instance_q31; /** * @brief Instance structure for the floating-point PID Control. */ typedef struct { float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ float32_t A2; /**< The derived gain, A2 = Kd . */ float32_t state[3]; /**< The state array of length 3. */ float32_t Kp; /**< The proportional gain. */ float32_t Ki; /**< The integral gain. */ float32_t Kd; /**< The derivative gain. */ } arm_pid_instance_f32; /** * @brief Initialization function for the floating-point PID Control. * @param[in,out] S points to an instance of the PID structure. * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. */ void arm_pid_init_f32( arm_pid_instance_f32 * S, int32_t resetStateFlag); /** * @brief Reset function for the floating-point PID Control. * @param[in,out] S is an instance of the floating-point PID Control structure */ void arm_pid_reset_f32( arm_pid_instance_f32 * S); /** * @brief Initialization function for the Q31 PID Control. * @param[in,out] S points to an instance of the Q15 PID structure. * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. */ void arm_pid_init_q31( arm_pid_instance_q31 * S, int32_t resetStateFlag); /** * @brief Reset function for the Q31 PID Control. * @param[in,out] S points to an instance of the Q31 PID Control structure */ void arm_pid_reset_q31( arm_pid_instance_q31 * S); /** * @brief Initialization function for the Q15 PID Control. * @param[in,out] S points to an instance of the Q15 PID structure. * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. */ void arm_pid_init_q15( arm_pid_instance_q15 * S, int32_t resetStateFlag); /** * @brief Reset function for the Q15 PID Control. * @param[in,out] S points to an instance of the q15 PID Control structure */ void arm_pid_reset_q15( arm_pid_instance_q15 * S); /** * @brief Instance structure for the floating-point Linear Interpolate function. */ typedef struct { uint32_t nValues; /**< nValues */ float32_t x1; /**< x1 */ float32_t xSpacing; /**< xSpacing */ float32_t *pYData; /**< pointer to the table of Y values */ } arm_linear_interp_instance_f32; /** * @brief Instance structure for the floating-point bilinear interpolation function. */ typedef struct { uint16_t numRows; /**< number of rows in the data table. */ uint16_t numCols; /**< number of columns in the data table. */ float32_t *pData; /**< points to the data table. */ } arm_bilinear_interp_instance_f32; /** * @brief Instance structure for the Q31 bilinear interpolation function. */ typedef struct { uint16_t numRows; /**< number of rows in the data table. */ uint16_t numCols; /**< number of columns in the data table. */ q31_t *pData; /**< points to the data table. */ } arm_bilinear_interp_instance_q31; /** * @brief Instance structure for the Q15 bilinear interpolation function. */ typedef struct { uint16_t numRows; /**< number of rows in the data table. */ uint16_t numCols; /**< number of columns in the data table. */ q15_t *pData; /**< points to the data table. */ } arm_bilinear_interp_instance_q15; /** * @brief Instance structure for the Q15 bilinear interpolation function. */ typedef struct { uint16_t numRows; /**< number of rows in the data table. */ uint16_t numCols; /**< number of columns in the data table. */ q7_t *pData; /**< points to the data table. */ } arm_bilinear_interp_instance_q7; /** * @brief Q7 vector multiplication. * @param[in] pSrcA points to the first input vector * @param[in] pSrcB points to the second input vector * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in each vector */ void arm_mult_q7( q7_t * pSrcA, q7_t * pSrcB, q7_t * pDst, uint32_t blockSize); /** * @brief Q15 vector multiplication. * @param[in] pSrcA points to the first input vector * @param[in] pSrcB points to the second input vector * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in each vector */ void arm_mult_q15( q15_t * pSrcA, q15_t * pSrcB, q15_t * pDst, uint32_t blockSize); /** * @brief Q31 vector multiplication. * @param[in] pSrcA points to the first input vector * @param[in] pSrcB points to the second input vector * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in each vector */ void arm_mult_q31( q31_t * pSrcA, q31_t * pSrcB, q31_t * pDst, uint32_t blockSize); /** * @brief Floating-point vector multiplication. * @param[in] pSrcA points to the first input vector * @param[in] pSrcB points to the second input vector * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in each vector */ void arm_mult_f32( float32_t * pSrcA, float32_t * pSrcB, float32_t * pDst, uint32_t blockSize); /** * @brief Instance structure for the Q15 CFFT/CIFFT function. */ typedef struct { uint16_t fftLen; /**< length of the FFT. */ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */ uint16_t *pBitRevTable; /**< points to the bit reversal table. */ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ } arm_cfft_radix2_instance_q15; /* Deprecated */ arm_status arm_cfft_radix2_init_q15( arm_cfft_radix2_instance_q15 * S, uint16_t fftLen, uint8_t ifftFlag, uint8_t bitReverseFlag); /* Deprecated */ void arm_cfft_radix2_q15( const arm_cfft_radix2_instance_q15 * S, q15_t * pSrc); /** * @brief Instance structure for the Q15 CFFT/CIFFT function. */ typedef struct { uint16_t fftLen; /**< length of the FFT. */ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ q15_t *pTwiddle; /**< points to the twiddle factor table. */ uint16_t *pBitRevTable; /**< points to the bit reversal table. */ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ } arm_cfft_radix4_instance_q15; /* Deprecated */ arm_status arm_cfft_radix4_init_q15( arm_cfft_radix4_instance_q15 * S, uint16_t fftLen, uint8_t ifftFlag, uint8_t bitReverseFlag); /* Deprecated */ void arm_cfft_radix4_q15( const arm_cfft_radix4_instance_q15 * S, q15_t * pSrc); /** * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function. */ typedef struct { uint16_t fftLen; /**< length of the FFT. */ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ q31_t *pTwiddle; /**< points to the Twiddle factor table. */ uint16_t *pBitRevTable; /**< points to the bit reversal table. */ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ } arm_cfft_radix2_instance_q31; /* Deprecated */ arm_status arm_cfft_radix2_init_q31( arm_cfft_radix2_instance_q31 * S, uint16_t fftLen, uint8_t ifftFlag, uint8_t bitReverseFlag); /* Deprecated */ void arm_cfft_radix2_q31( const arm_cfft_radix2_instance_q31 * S, q31_t * pSrc); /** * @brief Instance structure for the Q31 CFFT/CIFFT function. */ typedef struct { uint16_t fftLen; /**< length of the FFT. */ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ q31_t *pTwiddle; /**< points to the twiddle factor table. */ uint16_t *pBitRevTable; /**< points to the bit reversal table. */ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ } arm_cfft_radix4_instance_q31; /* Deprecated */ void arm_cfft_radix4_q31( const arm_cfft_radix4_instance_q31 * S, q31_t * pSrc); /* Deprecated */ arm_status arm_cfft_radix4_init_q31( arm_cfft_radix4_instance_q31 * S, uint16_t fftLen, uint8_t ifftFlag, uint8_t bitReverseFlag); /** * @brief Instance structure for the floating-point CFFT/CIFFT function. */ typedef struct { uint16_t fftLen; /**< length of the FFT. */ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ float32_t *pTwiddle; /**< points to the Twiddle factor table. */ uint16_t *pBitRevTable; /**< points to the bit reversal table. */ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ float32_t onebyfftLen; /**< value of 1/fftLen. */ } arm_cfft_radix2_instance_f32; /* Deprecated */ arm_status arm_cfft_radix2_init_f32( arm_cfft_radix2_instance_f32 * S, uint16_t fftLen, uint8_t ifftFlag, uint8_t bitReverseFlag); /* Deprecated */ void arm_cfft_radix2_f32( const arm_cfft_radix2_instance_f32 * S, float32_t * pSrc); /** * @brief Instance structure for the floating-point CFFT/CIFFT function. */ typedef struct { uint16_t fftLen; /**< length of the FFT. */ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ float32_t *pTwiddle; /**< points to the Twiddle factor table. */ uint16_t *pBitRevTable; /**< points to the bit reversal table. */ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ float32_t onebyfftLen; /**< value of 1/fftLen. */ } arm_cfft_radix4_instance_f32; /* Deprecated */ arm_status arm_cfft_radix4_init_f32( arm_cfft_radix4_instance_f32 * S, uint16_t fftLen, uint8_t ifftFlag, uint8_t bitReverseFlag); /* Deprecated */ void arm_cfft_radix4_f32( const arm_cfft_radix4_instance_f32 * S, float32_t * pSrc); /** * @brief Instance structure for the fixed-point CFFT/CIFFT function. */ typedef struct { uint16_t fftLen; /**< length of the FFT. */ const q15_t *pTwiddle; /**< points to the Twiddle factor table. */ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ uint16_t bitRevLength; /**< bit reversal table length. */ } arm_cfft_instance_q15; void arm_cfft_q15( const arm_cfft_instance_q15 * S, q15_t * p1, uint8_t ifftFlag, uint8_t bitReverseFlag); /** * @brief Instance structure for the fixed-point CFFT/CIFFT function. */ typedef struct { uint16_t fftLen; /**< length of the FFT. */ const q31_t *pTwiddle; /**< points to the Twiddle factor table. */ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ uint16_t bitRevLength; /**< bit reversal table length. */ } arm_cfft_instance_q31; void arm_cfft_q31( const arm_cfft_instance_q31 * S, q31_t * p1, uint8_t ifftFlag, uint8_t bitReverseFlag); /** * @brief Instance structure for the floating-point CFFT/CIFFT function. */ typedef struct { uint16_t fftLen; /**< length of the FFT. */ const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ uint16_t bitRevLength; /**< bit reversal table length. */ } arm_cfft_instance_f32; void arm_cfft_f32( const arm_cfft_instance_f32 * S, float32_t * p1, uint8_t ifftFlag, uint8_t bitReverseFlag); /** * @brief Instance structure for the Q15 RFFT/RIFFT function. */ typedef struct { uint32_t fftLenReal; /**< length of the real FFT. */ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ const arm_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */ } arm_rfft_instance_q15; arm_status arm_rfft_init_q15( arm_rfft_instance_q15 * S, uint32_t fftLenReal, uint32_t ifftFlagR, uint32_t bitReverseFlag); void arm_rfft_q15( const arm_rfft_instance_q15 * S, q15_t * pSrc, q15_t * pDst); /** * @brief Instance structure for the Q31 RFFT/RIFFT function. */ typedef struct { uint32_t fftLenReal; /**< length of the real FFT. */ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ const arm_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */ } arm_rfft_instance_q31; arm_status arm_rfft_init_q31( arm_rfft_instance_q31 * S, uint32_t fftLenReal, uint32_t ifftFlagR, uint32_t bitReverseFlag); void arm_rfft_q31( const arm_rfft_instance_q31 * S, q31_t * pSrc, q31_t * pDst); /** * @brief Instance structure for the floating-point RFFT/RIFFT function. */ typedef struct { uint32_t fftLenReal; /**< length of the real FFT. */ uint16_t fftLenBy2; /**< length of the complex FFT. */ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ } arm_rfft_instance_f32; arm_status arm_rfft_init_f32( arm_rfft_instance_f32 * S, arm_cfft_radix4_instance_f32 * S_CFFT, uint32_t fftLenReal, uint32_t ifftFlagR, uint32_t bitReverseFlag); void arm_rfft_f32( const arm_rfft_instance_f32 * S, float32_t * pSrc, float32_t * pDst); /** * @brief Instance structure for the floating-point RFFT/RIFFT function. */ typedef struct { arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */ uint16_t fftLenRFFT; /**< length of the real sequence */ float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */ } arm_rfft_fast_instance_f32 ; arm_status arm_rfft_fast_init_f32 ( arm_rfft_fast_instance_f32 * S, uint16_t fftLen); void arm_rfft_fast_f32( arm_rfft_fast_instance_f32 * S, float32_t * p, float32_t * pOut, uint8_t ifftFlag); /** * @brief Instance structure for the floating-point DCT4/IDCT4 function. */ typedef struct { uint16_t N; /**< length of the DCT4. */ uint16_t Nby2; /**< half of the length of the DCT4. */ float32_t normalize; /**< normalizing factor. */ float32_t *pTwiddle; /**< points to the twiddle factor table. */ float32_t *pCosFactor; /**< points to the cosFactor table. */ arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */ arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ } arm_dct4_instance_f32; /** * @brief Initialization function for the floating-point DCT4/IDCT4. * @param[in,out] S points to an instance of floating-point DCT4/IDCT4 structure. * @param[in] S_RFFT points to an instance of floating-point RFFT/RIFFT structure. * @param[in] S_CFFT points to an instance of floating-point CFFT/CIFFT structure. * @param[in] N length of the DCT4. * @param[in] Nby2 half of the length of the DCT4. * @param[in] normalize normalizing factor. * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported transform length. */ arm_status arm_dct4_init_f32( arm_dct4_instance_f32 * S, arm_rfft_instance_f32 * S_RFFT, arm_cfft_radix4_instance_f32 * S_CFFT, uint16_t N, uint16_t Nby2, float32_t normalize); /** * @brief Processing function for the floating-point DCT4/IDCT4. * @param[in] S points to an instance of the floating-point DCT4/IDCT4 structure. * @param[in] pState points to state buffer. * @param[in,out] pInlineBuffer points to the in-place input and output buffer. */ void arm_dct4_f32( const arm_dct4_instance_f32 * S, float32_t * pState, float32_t * pInlineBuffer); /** * @brief Instance structure for the Q31 DCT4/IDCT4 function. */ typedef struct { uint16_t N; /**< length of the DCT4. */ uint16_t Nby2; /**< half of the length of the DCT4. */ q31_t normalize; /**< normalizing factor. */ q31_t *pTwiddle; /**< points to the twiddle factor table. */ q31_t *pCosFactor; /**< points to the cosFactor table. */ arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */ arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ } arm_dct4_instance_q31; /** * @brief Initialization function for the Q31 DCT4/IDCT4. * @param[in,out] S points to an instance of Q31 DCT4/IDCT4 structure. * @param[in] S_RFFT points to an instance of Q31 RFFT/RIFFT structure * @param[in] S_CFFT points to an instance of Q31 CFFT/CIFFT structure * @param[in] N length of the DCT4. * @param[in] Nby2 half of the length of the DCT4. * @param[in] normalize normalizing factor. * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length. */ arm_status arm_dct4_init_q31( arm_dct4_instance_q31 * S, arm_rfft_instance_q31 * S_RFFT, arm_cfft_radix4_instance_q31 * S_CFFT, uint16_t N, uint16_t Nby2, q31_t normalize); /** * @brief Processing function for the Q31 DCT4/IDCT4. * @param[in] S points to an instance of the Q31 DCT4 structure. * @param[in] pState points to state buffer. * @param[in,out] pInlineBuffer points to the in-place input and output buffer. */ void arm_dct4_q31( const arm_dct4_instance_q31 * S, q31_t * pState, q31_t * pInlineBuffer); /** * @brief Instance structure for the Q15 DCT4/IDCT4 function. */ typedef struct { uint16_t N; /**< length of the DCT4. */ uint16_t Nby2; /**< half of the length of the DCT4. */ q15_t normalize; /**< normalizing factor. */ q15_t *pTwiddle; /**< points to the twiddle factor table. */ q15_t *pCosFactor; /**< points to the cosFactor table. */ arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */ arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ } arm_dct4_instance_q15; /** * @brief Initialization function for the Q15 DCT4/IDCT4. * @param[in,out] S points to an instance of Q15 DCT4/IDCT4 structure. * @param[in] S_RFFT points to an instance of Q15 RFFT/RIFFT structure. * @param[in] S_CFFT points to an instance of Q15 CFFT/CIFFT structure. * @param[in] N length of the DCT4. * @param[in] Nby2 half of the length of the DCT4. * @param[in] normalize normalizing factor. * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length. */ arm_status arm_dct4_init_q15( arm_dct4_instance_q15 * S, arm_rfft_instance_q15 * S_RFFT, arm_cfft_radix4_instance_q15 * S_CFFT, uint16_t N, uint16_t Nby2, q15_t normalize); /** * @brief Processing function for the Q15 DCT4/IDCT4. * @param[in] S points to an instance of the Q15 DCT4 structure. * @param[in] pState points to state buffer. * @param[in,out] pInlineBuffer points to the in-place input and output buffer. */ void arm_dct4_q15( const arm_dct4_instance_q15 * S, q15_t * pState, q15_t * pInlineBuffer); /** * @brief Floating-point vector addition. * @param[in] pSrcA points to the first input vector * @param[in] pSrcB points to the second input vector * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in each vector */ void arm_add_f32( float32_t * pSrcA, float32_t * pSrcB, float32_t * pDst, uint32_t blockSize); /** * @brief Q7 vector addition. * @param[in] pSrcA points to the first input vector * @param[in] pSrcB points to the second input vector * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in each vector */ void arm_add_q7( q7_t * pSrcA, q7_t * pSrcB, q7_t * pDst, uint32_t blockSize); /** * @brief Q15 vector addition. * @param[in] pSrcA points to the first input vector * @param[in] pSrcB points to the second input vector * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in each vector */ void arm_add_q15( q15_t * pSrcA, q15_t * pSrcB, q15_t * pDst, uint32_t blockSize); /** * @brief Q31 vector addition. * @param[in] pSrcA points to the first input vector * @param[in] pSrcB points to the second input vector * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in each vector */ void arm_add_q31( q31_t * pSrcA, q31_t * pSrcB, q31_t * pDst, uint32_t blockSize); /** * @brief Floating-point vector subtraction. * @param[in] pSrcA points to the first input vector * @param[in] pSrcB points to the second input vector * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in each vector */ void arm_sub_f32( float32_t * pSrcA, float32_t * pSrcB, float32_t * pDst, uint32_t blockSize); /** * @brief Q7 vector subtraction. * @param[in] pSrcA points to the first input vector * @param[in] pSrcB points to the second input vector * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in each vector */ void arm_sub_q7( q7_t * pSrcA, q7_t * pSrcB, q7_t * pDst, uint32_t blockSize); /** * @brief Q15 vector subtraction. * @param[in] pSrcA points to the first input vector * @param[in] pSrcB points to the second input vector * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in each vector */ void arm_sub_q15( q15_t * pSrcA, q15_t * pSrcB, q15_t * pDst, uint32_t blockSize); /** * @brief Q31 vector subtraction. * @param[in] pSrcA points to the first input vector * @param[in] pSrcB points to the second input vector * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in each vector */ void arm_sub_q31( q31_t * pSrcA, q31_t * pSrcB, q31_t * pDst, uint32_t blockSize); /** * @brief Multiplies a floating-point vector by a scalar. * @param[in] pSrc points to the input vector * @param[in] scale scale factor to be applied * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in the vector */ void arm_scale_f32( float32_t * pSrc, float32_t scale, float32_t * pDst, uint32_t blockSize); /** * @brief Multiplies a Q7 vector by a scalar. * @param[in] pSrc points to the input vector * @param[in] scaleFract fractional portion of the scale value * @param[in] shift number of bits to shift the result by * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in the vector */ void arm_scale_q7( q7_t * pSrc, q7_t scaleFract, int8_t shift, q7_t * pDst, uint32_t blockSize); /** * @brief Multiplies a Q15 vector by a scalar. * @param[in] pSrc points to the input vector * @param[in] scaleFract fractional portion of the scale value * @param[in] shift number of bits to shift the result by * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in the vector */ void arm_scale_q15( q15_t * pSrc, q15_t scaleFract, int8_t shift, q15_t * pDst, uint32_t blockSize); /** * @brief Multiplies a Q31 vector by a scalar. * @param[in] pSrc points to the input vector * @param[in] scaleFract fractional portion of the scale value * @param[in] shift number of bits to shift the result by * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in the vector */ void arm_scale_q31( q31_t * pSrc, q31_t scaleFract, int8_t shift, q31_t * pDst, uint32_t blockSize); /** * @brief Q7 vector absolute value. * @param[in] pSrc points to the input buffer * @param[out] pDst points to the output buffer * @param[in] blockSize number of samples in each vector */ void arm_abs_q7( q7_t * pSrc, q7_t * pDst, uint32_t blockSize); /** * @brief Floating-point vector absolute value. * @param[in] pSrc points to the input buffer * @param[out] pDst points to the output buffer * @param[in] blockSize number of samples in each vector */ void arm_abs_f32( float32_t * pSrc, float32_t * pDst, uint32_t blockSize); /** * @brief Q15 vector absolute value. * @param[in] pSrc points to the input buffer * @param[out] pDst points to the output buffer * @param[in] blockSize number of samples in each vector */ void arm_abs_q15( q15_t * pSrc, q15_t * pDst, uint32_t blockSize); /** * @brief Q31 vector absolute value. * @param[in] pSrc points to the input buffer * @param[out] pDst points to the output buffer * @param[in] blockSize number of samples in each vector */ void arm_abs_q31( q31_t * pSrc, q31_t * pDst, uint32_t blockSize); /** * @brief Dot product of floating-point vectors. * @param[in] pSrcA points to the first input vector * @param[in] pSrcB points to the second input vector * @param[in] blockSize number of samples in each vector * @param[out] result output result returned here */ void arm_dot_prod_f32( float32_t * pSrcA, float32_t * pSrcB, uint32_t blockSize, float32_t * result); /** * @brief Dot product of Q7 vectors. * @param[in] pSrcA points to the first input vector * @param[in] pSrcB points to the second input vector * @param[in] blockSize number of samples in each vector * @param[out] result output result returned here */ void arm_dot_prod_q7( q7_t * pSrcA, q7_t * pSrcB, uint32_t blockSize, q31_t * result); /** * @brief Dot product of Q15 vectors. * @param[in] pSrcA points to the first input vector * @param[in] pSrcB points to the second input vector * @param[in] blockSize number of samples in each vector * @param[out] result output result returned here */ void arm_dot_prod_q15( q15_t * pSrcA, q15_t * pSrcB, uint32_t blockSize, q63_t * result); /** * @brief Dot product of Q31 vectors. * @param[in] pSrcA points to the first input vector * @param[in] pSrcB points to the second input vector * @param[in] blockSize number of samples in each vector * @param[out] result output result returned here */ void arm_dot_prod_q31( q31_t * pSrcA, q31_t * pSrcB, uint32_t blockSize, q63_t * result); /** * @brief Shifts the elements of a Q7 vector a specified number of bits. * @param[in] pSrc points to the input vector * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in the vector */ void arm_shift_q7( q7_t * pSrc, int8_t shiftBits, q7_t * pDst, uint32_t blockSize); /** * @brief Shifts the elements of a Q15 vector a specified number of bits. * @param[in] pSrc points to the input vector * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in the vector */ void arm_shift_q15( q15_t * pSrc, int8_t shiftBits, q15_t * pDst, uint32_t blockSize); /** * @brief Shifts the elements of a Q31 vector a specified number of bits. * @param[in] pSrc points to the input vector * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in the vector */ void arm_shift_q31( q31_t * pSrc, int8_t shiftBits, q31_t * pDst, uint32_t blockSize); /** * @brief Adds a constant offset to a floating-point vector. * @param[in] pSrc points to the input vector * @param[in] offset is the offset to be added * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in the vector */ void arm_offset_f32( float32_t * pSrc, float32_t offset, float32_t * pDst, uint32_t blockSize); /** * @brief Adds a constant offset to a Q7 vector. * @param[in] pSrc points to the input vector * @param[in] offset is the offset to be added * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in the vector */ void arm_offset_q7( q7_t * pSrc, q7_t offset, q7_t * pDst, uint32_t blockSize); /** * @brief Adds a constant offset to a Q15 vector. * @param[in] pSrc points to the input vector * @param[in] offset is the offset to be added * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in the vector */ void arm_offset_q15( q15_t * pSrc, q15_t offset, q15_t * pDst, uint32_t blockSize); /** * @brief Adds a constant offset to a Q31 vector. * @param[in] pSrc points to the input vector * @param[in] offset is the offset to be added * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in the vector */ void arm_offset_q31( q31_t * pSrc, q31_t offset, q31_t * pDst, uint32_t blockSize); /** * @brief Negates the elements of a floating-point vector. * @param[in] pSrc points to the input vector * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in the vector */ void arm_negate_f32( float32_t * pSrc, float32_t * pDst, uint32_t blockSize); /** * @brief Negates the elements of a Q7 vector. * @param[in] pSrc points to the input vector * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in the vector */ void arm_negate_q7( q7_t * pSrc, q7_t * pDst, uint32_t blockSize); /** * @brief Negates the elements of a Q15 vector. * @param[in] pSrc points to the input vector * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in the vector */ void arm_negate_q15( q15_t * pSrc, q15_t * pDst, uint32_t blockSize); /** * @brief Negates the elements of a Q31 vector. * @param[in] pSrc points to the input vector * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in the vector */ void arm_negate_q31( q31_t * pSrc, q31_t * pDst, uint32_t blockSize); /** * @brief Copies the elements of a floating-point vector. * @param[in] pSrc input pointer * @param[out] pDst output pointer * @param[in] blockSize number of samples to process */ void arm_copy_f32( float32_t * pSrc, float32_t * pDst, uint32_t blockSize); /** * @brief Copies the elements of a Q7 vector. * @param[in] pSrc input pointer * @param[out] pDst output pointer * @param[in] blockSize number of samples to process */ void arm_copy_q7( q7_t * pSrc, q7_t * pDst, uint32_t blockSize); /** * @brief Copies the elements of a Q15 vector. * @param[in] pSrc input pointer * @param[out] pDst output pointer * @param[in] blockSize number of samples to process */ void arm_copy_q15( q15_t * pSrc, q15_t * pDst, uint32_t blockSize); /** * @brief Copies the elements of a Q31 vector. * @param[in] pSrc input pointer * @param[out] pDst output pointer * @param[in] blockSize number of samples to process */ void arm_copy_q31( q31_t * pSrc, q31_t * pDst, uint32_t blockSize); /** * @brief Fills a constant value into a floating-point vector. * @param[in] value input value to be filled * @param[out] pDst output pointer * @param[in] blockSize number of samples to process */ void arm_fill_f32( float32_t value, float32_t * pDst, uint32_t blockSize); /** * @brief Fills a constant value into a Q7 vector. * @param[in] value input value to be filled * @param[out] pDst output pointer * @param[in] blockSize number of samples to process */ void arm_fill_q7( q7_t value, q7_t * pDst, uint32_t blockSize); /** * @brief Fills a constant value into a Q15 vector. * @param[in] value input value to be filled * @param[out] pDst output pointer * @param[in] blockSize number of samples to process */ void arm_fill_q15( q15_t value, q15_t * pDst, uint32_t blockSize); /** * @brief Fills a constant value into a Q31 vector. * @param[in] value input value to be filled * @param[out] pDst output pointer * @param[in] blockSize number of samples to process */ void arm_fill_q31( q31_t value, q31_t * pDst, uint32_t blockSize); /** * @brief Convolution of floating-point sequences. * @param[in] pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. */ void arm_conv_f32( float32_t * pSrcA, uint32_t srcALen, float32_t * pSrcB, uint32_t srcBLen, float32_t * pDst); /** * @brief Convolution of Q15 sequences. * @param[in] pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). */ void arm_conv_opt_q15( q15_t * pSrcA, uint32_t srcALen, q15_t * pSrcB, uint32_t srcBLen, q15_t * pDst, q15_t * pScratch1, q15_t * pScratch2); /** * @brief Convolution of Q15 sequences. * @param[in] pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. */ void arm_conv_q15( q15_t * pSrcA, uint32_t srcALen, q15_t * pSrcB, uint32_t srcBLen, q15_t * pDst); /** * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 * @param[in] pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. */ void arm_conv_fast_q15( q15_t * pSrcA, uint32_t srcALen, q15_t * pSrcB, uint32_t srcBLen, q15_t * pDst); /** * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 * @param[in] pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). */ void arm_conv_fast_opt_q15( q15_t * pSrcA, uint32_t srcALen, q15_t * pSrcB, uint32_t srcBLen, q15_t * pDst, q15_t * pScratch1, q15_t * pScratch2); /** * @brief Convolution of Q31 sequences. * @param[in] pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. */ void arm_conv_q31( q31_t * pSrcA, uint32_t srcALen, q31_t * pSrcB, uint32_t srcBLen, q31_t * pDst); /** * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 * @param[in] pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. */ void arm_conv_fast_q31( q31_t * pSrcA, uint32_t srcALen, q31_t * pSrcB, uint32_t srcBLen, q31_t * pDst); /** * @brief Convolution of Q7 sequences. * @param[in] pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). */ void arm_conv_opt_q7( q7_t * pSrcA, uint32_t srcALen, q7_t * pSrcB, uint32_t srcBLen, q7_t * pDst, q15_t * pScratch1, q15_t * pScratch2); /** * @brief Convolution of Q7 sequences. * @param[in] pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. */ void arm_conv_q7( q7_t * pSrcA, uint32_t srcALen, q7_t * pSrcB, uint32_t srcBLen, q7_t * pDst); /** * @brief Partial convolution of floating-point sequences. * @param[in] pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] pDst points to the block of output data * @param[in] firstIndex is the first output sample to start with. * @param[in] numPoints is the number of output points to be computed. * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. */ arm_status arm_conv_partial_f32( float32_t * pSrcA, uint32_t srcALen, float32_t * pSrcB, uint32_t srcBLen, float32_t * pDst, uint32_t firstIndex, uint32_t numPoints); /** * @brief Partial convolution of Q15 sequences. * @param[in] pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] pDst points to the block of output data * @param[in] firstIndex is the first output sample to start with. * @param[in] numPoints is the number of output points to be computed. * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. */ arm_status arm_conv_partial_opt_q15( q15_t * pSrcA, uint32_t srcALen, q15_t * pSrcB, uint32_t srcBLen, q15_t * pDst, uint32_t firstIndex, uint32_t numPoints, q15_t * pScratch1, q15_t * pScratch2); /** * @brief Partial convolution of Q15 sequences. * @param[in] pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] pDst points to the block of output data * @param[in] firstIndex is the first output sample to start with. * @param[in] numPoints is the number of output points to be computed. * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. */ arm_status arm_conv_partial_q15( q15_t * pSrcA, uint32_t srcALen, q15_t * pSrcB, uint32_t srcBLen, q15_t * pDst, uint32_t firstIndex, uint32_t numPoints); /** * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 * @param[in] pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] pDst points to the block of output data * @param[in] firstIndex is the first output sample to start with. * @param[in] numPoints is the number of output points to be computed. * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. */ arm_status arm_conv_partial_fast_q15( q15_t * pSrcA, uint32_t srcALen, q15_t * pSrcB, uint32_t srcBLen, q15_t * pDst, uint32_t firstIndex, uint32_t numPoints); /** * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 * @param[in] pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] pDst points to the block of output data * @param[in] firstIndex is the first output sample to start with. * @param[in] numPoints is the number of output points to be computed. * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. */ arm_status arm_conv_partial_fast_opt_q15( q15_t * pSrcA, uint32_t srcALen, q15_t * pSrcB, uint32_t srcBLen, q15_t * pDst, uint32_t firstIndex, uint32_t numPoints, q15_t * pScratch1, q15_t * pScratch2); /** * @brief Partial convolution of Q31 sequences. * @param[in] pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] pDst points to the block of output data * @param[in] firstIndex is the first output sample to start with. * @param[in] numPoints is the number of output points to be computed. * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. */ arm_status arm_conv_partial_q31( q31_t * pSrcA, uint32_t srcALen, q31_t * pSrcB, uint32_t srcBLen, q31_t * pDst, uint32_t firstIndex, uint32_t numPoints); /** * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 * @param[in] pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] pDst points to the block of output data * @param[in] firstIndex is the first output sample to start with. * @param[in] numPoints is the number of output points to be computed. * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. */ arm_status arm_conv_partial_fast_q31( q31_t * pSrcA, uint32_t srcALen, q31_t * pSrcB, uint32_t srcBLen, q31_t * pDst, uint32_t firstIndex, uint32_t numPoints); /** * @brief Partial convolution of Q7 sequences * @param[in] pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] pDst points to the block of output data * @param[in] firstIndex is the first output sample to start with. * @param[in] numPoints is the number of output points to be computed. * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. */ arm_status arm_conv_partial_opt_q7( q7_t * pSrcA, uint32_t srcALen, q7_t * pSrcB, uint32_t srcBLen, q7_t * pDst, uint32_t firstIndex, uint32_t numPoints, q15_t * pScratch1, q15_t * pScratch2); /** * @brief Partial convolution of Q7 sequences. * @param[in] pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] pDst points to the block of output data * @param[in] firstIndex is the first output sample to start with. * @param[in] numPoints is the number of output points to be computed. * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. */ arm_status arm_conv_partial_q7( q7_t * pSrcA, uint32_t srcALen, q7_t * pSrcB, uint32_t srcBLen, q7_t * pDst, uint32_t firstIndex, uint32_t numPoints); /** * @brief Instance structure for the Q15 FIR decimator. */ typedef struct { uint8_t M; /**< decimation factor. */ uint16_t numTaps; /**< number of coefficients in the filter. */ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ } arm_fir_decimate_instance_q15; /** * @brief Instance structure for the Q31 FIR decimator. */ typedef struct { uint8_t M; /**< decimation factor. */ uint16_t numTaps; /**< number of coefficients in the filter. */ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ } arm_fir_decimate_instance_q31; /** * @brief Instance structure for the floating-point FIR decimator. */ typedef struct { uint8_t M; /**< decimation factor. */ uint16_t numTaps; /**< number of coefficients in the filter. */ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ } arm_fir_decimate_instance_f32; /** * @brief Processing function for the floating-point FIR decimator. * @param[in] S points to an instance of the floating-point FIR decimator structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data * @param[in] blockSize number of input samples to process per call. */ void arm_fir_decimate_f32( const arm_fir_decimate_instance_f32 * S, float32_t * pSrc, float32_t * pDst, uint32_t blockSize); /** * @brief Initialization function for the floating-point FIR decimator. * @param[in,out] S points to an instance of the floating-point FIR decimator structure. * @param[in] numTaps number of coefficients in the filter. * @param[in] M decimation factor. * @param[in] pCoeffs points to the filter coefficients. * @param[in] pState points to the state buffer. * @param[in] blockSize number of input samples to process per call. * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if * <code>blockSize</code> is not a multiple of <code>M</code>. */ arm_status arm_fir_decimate_init_f32( arm_fir_decimate_instance_f32 * S, uint16_t numTaps, uint8_t M, float32_t * pCoeffs, float32_t * pState, uint32_t blockSize); /** * @brief Processing function for the Q15 FIR decimator. * @param[in] S points to an instance of the Q15 FIR decimator structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data * @param[in] blockSize number of input samples to process per call. */ void arm_fir_decimate_q15( const arm_fir_decimate_instance_q15 * S, q15_t * pSrc, q15_t * pDst, uint32_t blockSize); /** * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. * @param[in] S points to an instance of the Q15 FIR decimator structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data * @param[in] blockSize number of input samples to process per call. */ void arm_fir_decimate_fast_q15( const arm_fir_decimate_instance_q15 * S, q15_t * pSrc, q15_t * pDst, uint32_t blockSize); /** * @brief Initialization function for the Q15 FIR decimator. * @param[in,out] S points to an instance of the Q15 FIR decimator structure. * @param[in] numTaps number of coefficients in the filter. * @param[in] M decimation factor. * @param[in] pCoeffs points to the filter coefficients. * @param[in] pState points to the state buffer. * @param[in] blockSize number of input samples to process per call. * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if * <code>blockSize</code> is not a multiple of <code>M</code>. */ arm_status arm_fir_decimate_init_q15( arm_fir_decimate_instance_q15 * S, uint16_t numTaps, uint8_t M, q15_t * pCoeffs, q15_t * pState, uint32_t blockSize); /** * @brief Processing function for the Q31 FIR decimator. * @param[in] S points to an instance of the Q31 FIR decimator structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data * @param[in] blockSize number of input samples to process per call. */ void arm_fir_decimate_q31( const arm_fir_decimate_instance_q31 * S, q31_t * pSrc, q31_t * pDst, uint32_t blockSize); /** * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. * @param[in] S points to an instance of the Q31 FIR decimator structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data * @param[in] blockSize number of input samples to process per call. */ void arm_fir_decimate_fast_q31( arm_fir_decimate_instance_q31 * S, q31_t * pSrc, q31_t * pDst, uint32_t blockSize); /** * @brief Initialization function for the Q31 FIR decimator. * @param[in,out] S points to an instance of the Q31 FIR decimator structure. * @param[in] numTaps number of coefficients in the filter. * @param[in] M decimation factor. * @param[in] pCoeffs points to the filter coefficients. * @param[in] pState points to the state buffer. * @param[in] blockSize number of input samples to process per call. * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if * <code>blockSize</code> is not a multiple of <code>M</code>. */ arm_status arm_fir_decimate_init_q31( arm_fir_decimate_instance_q31 * S, uint16_t numTaps, uint8_t M, q31_t * pCoeffs, q31_t * pState, uint32_t blockSize); /** * @brief Instance structure for the Q15 FIR interpolator. */ typedef struct { uint8_t L; /**< upsample factor. */ uint16_t phaseLength; /**< length of each polyphase filter component. */ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ } arm_fir_interpolate_instance_q15; /** * @brief Instance structure for the Q31 FIR interpolator. */ typedef struct { uint8_t L; /**< upsample factor. */ uint16_t phaseLength; /**< length of each polyphase filter component. */ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ } arm_fir_interpolate_instance_q31; /** * @brief Instance structure for the floating-point FIR interpolator. */ typedef struct { uint8_t L; /**< upsample factor. */ uint16_t phaseLength; /**< length of each polyphase filter component. */ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ } arm_fir_interpolate_instance_f32; /** * @brief Processing function for the Q15 FIR interpolator. * @param[in] S points to an instance of the Q15 FIR interpolator structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data. * @param[in] blockSize number of input samples to process per call. */ void arm_fir_interpolate_q15( const arm_fir_interpolate_instance_q15 * S, q15_t * pSrc, q15_t * pDst, uint32_t blockSize); /** * @brief Initialization function for the Q15 FIR interpolator. * @param[in,out] S points to an instance of the Q15 FIR interpolator structure. * @param[in] L upsample factor. * @param[in] numTaps number of filter coefficients in the filter. * @param[in] pCoeffs points to the filter coefficient buffer. * @param[in] pState points to the state buffer. * @param[in] blockSize number of input samples to process per call. * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>. */ arm_status arm_fir_interpolate_init_q15( arm_fir_interpolate_instance_q15 * S, uint8_t L, uint16_t numTaps, q15_t * pCoeffs, q15_t * pState, uint32_t blockSize); /** * @brief Processing function for the Q31 FIR interpolator. * @param[in] S points to an instance of the Q15 FIR interpolator structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data. * @param[in] blockSize number of input samples to process per call. */ void arm_fir_interpolate_q31( const arm_fir_interpolate_instance_q31 * S, q31_t * pSrc, q31_t * pDst, uint32_t blockSize); /** * @brief Initialization function for the Q31 FIR interpolator. * @param[in,out] S points to an instance of the Q31 FIR interpolator structure. * @param[in] L upsample factor. * @param[in] numTaps number of filter coefficients in the filter. * @param[in] pCoeffs points to the filter coefficient buffer. * @param[in] pState points to the state buffer. * @param[in] blockSize number of input samples to process per call. * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>. */ arm_status arm_fir_interpolate_init_q31( arm_fir_interpolate_instance_q31 * S, uint8_t L, uint16_t numTaps, q31_t * pCoeffs, q31_t * pState, uint32_t blockSize); /** * @brief Processing function for the floating-point FIR interpolator. * @param[in] S points to an instance of the floating-point FIR interpolator structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data. * @param[in] blockSize number of input samples to process per call. */ void arm_fir_interpolate_f32( const arm_fir_interpolate_instance_f32 * S, float32_t * pSrc, float32_t * pDst, uint32_t blockSize); /** * @brief Initialization function for the floating-point FIR interpolator. * @param[in,out] S points to an instance of the floating-point FIR interpolator structure. * @param[in] L upsample factor. * @param[in] numTaps number of filter coefficients in the filter. * @param[in] pCoeffs points to the filter coefficient buffer. * @param[in] pState points to the state buffer. * @param[in] blockSize number of input samples to process per call. * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>. */ arm_status arm_fir_interpolate_init_f32( arm_fir_interpolate_instance_f32 * S, uint8_t L, uint16_t numTaps, float32_t * pCoeffs, float32_t * pState, uint32_t blockSize); /** * @brief Instance structure for the high precision Q31 Biquad cascade filter. */ typedef struct { uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ } arm_biquad_cas_df1_32x64_ins_q31; /** * @param[in] S points to an instance of the high precision Q31 Biquad cascade filter structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data * @param[in] blockSize number of samples to process. */ void arm_biquad_cas_df1_32x64_q31( const arm_biquad_cas_df1_32x64_ins_q31 * S, q31_t * pSrc, q31_t * pDst, uint32_t blockSize); /** * @param[in,out] S points to an instance of the high precision Q31 Biquad cascade filter structure. * @param[in] numStages number of 2nd order stages in the filter. * @param[in] pCoeffs points to the filter coefficients. * @param[in] pState points to the state buffer. * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format */ void arm_biquad_cas_df1_32x64_init_q31( arm_biquad_cas_df1_32x64_ins_q31 * S, uint8_t numStages, q31_t * pCoeffs, q63_t * pState, uint8_t postShift); /** * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. */ typedef struct { uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ } arm_biquad_cascade_df2T_instance_f32; /** * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. */ typedef struct { uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ } arm_biquad_cascade_stereo_df2T_instance_f32; /** * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. */ typedef struct { uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ } arm_biquad_cascade_df2T_instance_f64; /** * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. * @param[in] S points to an instance of the filter data structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data * @param[in] blockSize number of samples to process. */ void arm_biquad_cascade_df2T_f32( const arm_biquad_cascade_df2T_instance_f32 * S, float32_t * pSrc, float32_t * pDst, uint32_t blockSize); /** * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels * @param[in] S points to an instance of the filter data structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data * @param[in] blockSize number of samples to process. */ void arm_biquad_cascade_stereo_df2T_f32( const arm_biquad_cascade_stereo_df2T_instance_f32 * S, float32_t * pSrc, float32_t * pDst, uint32_t blockSize); /** * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. * @param[in] S points to an instance of the filter data structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data * @param[in] blockSize number of samples to process. */ void arm_biquad_cascade_df2T_f64( const arm_biquad_cascade_df2T_instance_f64 * S, float64_t * pSrc, float64_t * pDst, uint32_t blockSize); /** * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. * @param[in,out] S points to an instance of the filter data structure. * @param[in] numStages number of 2nd order stages in the filter. * @param[in] pCoeffs points to the filter coefficients. * @param[in] pState points to the state buffer. */ void arm_biquad_cascade_df2T_init_f32( arm_biquad_cascade_df2T_instance_f32 * S, uint8_t numStages, float32_t * pCoeffs, float32_t * pState); /** * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. * @param[in,out] S points to an instance of the filter data structure. * @param[in] numStages number of 2nd order stages in the filter. * @param[in] pCoeffs points to the filter coefficients. * @param[in] pState points to the state buffer. */ void arm_biquad_cascade_stereo_df2T_init_f32( arm_biquad_cascade_stereo_df2T_instance_f32 * S, uint8_t numStages, float32_t * pCoeffs, float32_t * pState); /** * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. * @param[in,out] S points to an instance of the filter data structure. * @param[in] numStages number of 2nd order stages in the filter. * @param[in] pCoeffs points to the filter coefficients. * @param[in] pState points to the state buffer. */ void arm_biquad_cascade_df2T_init_f64( arm_biquad_cascade_df2T_instance_f64 * S, uint8_t numStages, float64_t * pCoeffs, float64_t * pState); /** * @brief Instance structure for the Q15 FIR lattice filter. */ typedef struct { uint16_t numStages; /**< number of filter stages. */ q15_t *pState; /**< points to the state variable array. The array is of length numStages. */ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ } arm_fir_lattice_instance_q15; /** * @brief Instance structure for the Q31 FIR lattice filter. */ typedef struct { uint16_t numStages; /**< number of filter stages. */ q31_t *pState; /**< points to the state variable array. The array is of length numStages. */ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ } arm_fir_lattice_instance_q31; /** * @brief Instance structure for the floating-point FIR lattice filter. */ typedef struct { uint16_t numStages; /**< number of filter stages. */ float32_t *pState; /**< points to the state variable array. The array is of length numStages. */ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ } arm_fir_lattice_instance_f32; /** * @brief Initialization function for the Q15 FIR lattice filter. * @param[in] S points to an instance of the Q15 FIR lattice structure. * @param[in] numStages number of filter stages. * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. * @param[in] pState points to the state buffer. The array is of length numStages. */ void arm_fir_lattice_init_q15( arm_fir_lattice_instance_q15 * S, uint16_t numStages, q15_t * pCoeffs, q15_t * pState); /** * @brief Processing function for the Q15 FIR lattice filter. * @param[in] S points to an instance of the Q15 FIR lattice structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data. * @param[in] blockSize number of samples to process. */ void arm_fir_lattice_q15( const arm_fir_lattice_instance_q15 * S, q15_t * pSrc, q15_t * pDst, uint32_t blockSize); /** * @brief Initialization function for the Q31 FIR lattice filter. * @param[in] S points to an instance of the Q31 FIR lattice structure. * @param[in] numStages number of filter stages. * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. * @param[in] pState points to the state buffer. The array is of length numStages. */ void arm_fir_lattice_init_q31( arm_fir_lattice_instance_q31 * S, uint16_t numStages, q31_t * pCoeffs, q31_t * pState); /** * @brief Processing function for the Q31 FIR lattice filter. * @param[in] S points to an instance of the Q31 FIR lattice structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data * @param[in] blockSize number of samples to process. */ void arm_fir_lattice_q31( const arm_fir_lattice_instance_q31 * S, q31_t * pSrc, q31_t * pDst, uint32_t blockSize); /** * @brief Initialization function for the floating-point FIR lattice filter. * @param[in] S points to an instance of the floating-point FIR lattice structure. * @param[in] numStages number of filter stages. * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. * @param[in] pState points to the state buffer. The array is of length numStages. */ void arm_fir_lattice_init_f32( arm_fir_lattice_instance_f32 * S, uint16_t numStages, float32_t * pCoeffs, float32_t * pState); /** * @brief Processing function for the floating-point FIR lattice filter. * @param[in] S points to an instance of the floating-point FIR lattice structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data * @param[in] blockSize number of samples to process. */ void arm_fir_lattice_f32( const arm_fir_lattice_instance_f32 * S, float32_t * pSrc, float32_t * pDst, uint32_t blockSize); /** * @brief Instance structure for the Q15 IIR lattice filter. */ typedef struct { uint16_t numStages; /**< number of stages in the filter. */ q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ } arm_iir_lattice_instance_q15; /** * @brief Instance structure for the Q31 IIR lattice filter. */ typedef struct { uint16_t numStages; /**< number of stages in the filter. */ q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ } arm_iir_lattice_instance_q31; /** * @brief Instance structure for the floating-point IIR lattice filter. */ typedef struct { uint16_t numStages; /**< number of stages in the filter. */ float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ } arm_iir_lattice_instance_f32; /** * @brief Processing function for the floating-point IIR lattice filter. * @param[in] S points to an instance of the floating-point IIR lattice structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data. * @param[in] blockSize number of samples to process. */ void arm_iir_lattice_f32( const arm_iir_lattice_instance_f32 * S, float32_t * pSrc, float32_t * pDst, uint32_t blockSize); /** * @brief Initialization function for the floating-point IIR lattice filter. * @param[in] S points to an instance of the floating-point IIR lattice structure. * @param[in] numStages number of stages in the filter. * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. * @param[in] pState points to the state buffer. The array is of length numStages+blockSize-1. * @param[in] blockSize number of samples to process. */ void arm_iir_lattice_init_f32( arm_iir_lattice_instance_f32 * S, uint16_t numStages, float32_t * pkCoeffs, float32_t * pvCoeffs, float32_t * pState, uint32_t blockSize); /** * @brief Processing function for the Q31 IIR lattice filter. * @param[in] S points to an instance of the Q31 IIR lattice structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data. * @param[in] blockSize number of samples to process. */ void arm_iir_lattice_q31( const arm_iir_lattice_instance_q31 * S, q31_t * pSrc, q31_t * pDst, uint32_t blockSize); /** * @brief Initialization function for the Q31 IIR lattice filter. * @param[in] S points to an instance of the Q31 IIR lattice structure. * @param[in] numStages number of stages in the filter. * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. * @param[in] pState points to the state buffer. The array is of length numStages+blockSize. * @param[in] blockSize number of samples to process. */ void arm_iir_lattice_init_q31( arm_iir_lattice_instance_q31 * S, uint16_t numStages, q31_t * pkCoeffs, q31_t * pvCoeffs, q31_t * pState, uint32_t blockSize); /** * @brief Processing function for the Q15 IIR lattice filter. * @param[in] S points to an instance of the Q15 IIR lattice structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data. * @param[in] blockSize number of samples to process. */ void arm_iir_lattice_q15( const arm_iir_lattice_instance_q15 * S, q15_t * pSrc, q15_t * pDst, uint32_t blockSize); /** * @brief Initialization function for the Q15 IIR lattice filter. * @param[in] S points to an instance of the fixed-point Q15 IIR lattice structure. * @param[in] numStages number of stages in the filter. * @param[in] pkCoeffs points to reflection coefficient buffer. The array is of length numStages. * @param[in] pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1. * @param[in] pState points to state buffer. The array is of length numStages+blockSize. * @param[in] blockSize number of samples to process per call. */ void arm_iir_lattice_init_q15( arm_iir_lattice_instance_q15 * S, uint16_t numStages, q15_t * pkCoeffs, q15_t * pvCoeffs, q15_t * pState, uint32_t blockSize); /** * @brief Instance structure for the floating-point LMS filter. */ typedef struct { uint16_t numTaps; /**< number of coefficients in the filter. */ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ float32_t mu; /**< step size that controls filter coefficient updates. */ } arm_lms_instance_f32; /** * @brief Processing function for floating-point LMS filter. * @param[in] S points to an instance of the floating-point LMS filter structure. * @param[in] pSrc points to the block of input data. * @param[in] pRef points to the block of reference data. * @param[out] pOut points to the block of output data. * @param[out] pErr points to the block of error data. * @param[in] blockSize number of samples to process. */ void arm_lms_f32( const arm_lms_instance_f32 * S, float32_t * pSrc, float32_t * pRef, float32_t * pOut, float32_t * pErr, uint32_t blockSize); /** * @brief Initialization function for floating-point LMS filter. * @param[in] S points to an instance of the floating-point LMS filter structure. * @param[in] numTaps number of filter coefficients. * @param[in] pCoeffs points to the coefficient buffer. * @param[in] pState points to state buffer. * @param[in] mu step size that controls filter coefficient updates. * @param[in] blockSize number of samples to process. */ void arm_lms_init_f32( arm_lms_instance_f32 * S, uint16_t numTaps, float32_t * pCoeffs, float32_t * pState, float32_t mu, uint32_t blockSize); /** * @brief Instance structure for the Q15 LMS filter. */ typedef struct { uint16_t numTaps; /**< number of coefficients in the filter. */ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ q15_t mu; /**< step size that controls filter coefficient updates. */ uint32_t postShift; /**< bit shift applied to coefficients. */ } arm_lms_instance_q15; /** * @brief Initialization function for the Q15 LMS filter. * @param[in] S points to an instance of the Q15 LMS filter structure. * @param[in] numTaps number of filter coefficients. * @param[in] pCoeffs points to the coefficient buffer. * @param[in] pState points to the state buffer. * @param[in] mu step size that controls filter coefficient updates. * @param[in] blockSize number of samples to process. * @param[in] postShift bit shift applied to coefficients. */ void arm_lms_init_q15( arm_lms_instance_q15 * S, uint16_t numTaps, q15_t * pCoeffs, q15_t * pState, q15_t mu, uint32_t blockSize, uint32_t postShift); /** * @brief Processing function for Q15 LMS filter. * @param[in] S points to an instance of the Q15 LMS filter structure. * @param[in] pSrc points to the block of input data. * @param[in] pRef points to the block of reference data. * @param[out] pOut points to the block of output data. * @param[out] pErr points to the block of error data. * @param[in] blockSize number of samples to process. */ void arm_lms_q15( const arm_lms_instance_q15 * S, q15_t * pSrc, q15_t * pRef, q15_t * pOut, q15_t * pErr, uint32_t blockSize); /** * @brief Instance structure for the Q31 LMS filter. */ typedef struct { uint16_t numTaps; /**< number of coefficients in the filter. */ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ q31_t mu; /**< step size that controls filter coefficient updates. */ uint32_t postShift; /**< bit shift applied to coefficients. */ } arm_lms_instance_q31; /** * @brief Processing function for Q31 LMS filter. * @param[in] S points to an instance of the Q15 LMS filter structure. * @param[in] pSrc points to the block of input data. * @param[in] pRef points to the block of reference data. * @param[out] pOut points to the block of output data. * @param[out] pErr points to the block of error data. * @param[in] blockSize number of samples to process. */ void arm_lms_q31( const arm_lms_instance_q31 * S, q31_t * pSrc, q31_t * pRef, q31_t * pOut, q31_t * pErr, uint32_t blockSize); /** * @brief Initialization function for Q31 LMS filter. * @param[in] S points to an instance of the Q31 LMS filter structure. * @param[in] numTaps number of filter coefficients. * @param[in] pCoeffs points to coefficient buffer. * @param[in] pState points to state buffer. * @param[in] mu step size that controls filter coefficient updates. * @param[in] blockSize number of samples to process. * @param[in] postShift bit shift applied to coefficients. */ void arm_lms_init_q31( arm_lms_instance_q31 * S, uint16_t numTaps, q31_t * pCoeffs, q31_t * pState, q31_t mu, uint32_t blockSize, uint32_t postShift); /** * @brief Instance structure for the floating-point normalized LMS filter. */ typedef struct { uint16_t numTaps; /**< number of coefficients in the filter. */ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ float32_t mu; /**< step size that control filter coefficient updates. */ float32_t energy; /**< saves previous frame energy. */ float32_t x0; /**< saves previous input sample. */ } arm_lms_norm_instance_f32; /** * @brief Processing function for floating-point normalized LMS filter. * @param[in] S points to an instance of the floating-point normalized LMS filter structure. * @param[in] pSrc points to the block of input data. * @param[in] pRef points to the block of reference data. * @param[out] pOut points to the block of output data. * @param[out] pErr points to the block of error data. * @param[in] blockSize number of samples to process. */ void arm_lms_norm_f32( arm_lms_norm_instance_f32 * S, float32_t * pSrc, float32_t * pRef, float32_t * pOut, float32_t * pErr, uint32_t blockSize); /** * @brief Initialization function for floating-point normalized LMS filter. * @param[in] S points to an instance of the floating-point LMS filter structure. * @param[in] numTaps number of filter coefficients. * @param[in] pCoeffs points to coefficient buffer. * @param[in] pState points to state buffer. * @param[in] mu step size that controls filter coefficient updates. * @param[in] blockSize number of samples to process. */ void arm_lms_norm_init_f32( arm_lms_norm_instance_f32 * S, uint16_t numTaps, float32_t * pCoeffs, float32_t * pState, float32_t mu, uint32_t blockSize); /** * @brief Instance structure for the Q31 normalized LMS filter. */ typedef struct { uint16_t numTaps; /**< number of coefficients in the filter. */ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ q31_t mu; /**< step size that controls filter coefficient updates. */ uint8_t postShift; /**< bit shift applied to coefficients. */ q31_t *recipTable; /**< points to the reciprocal initial value table. */ q31_t energy; /**< saves previous frame energy. */ q31_t x0; /**< saves previous input sample. */ } arm_lms_norm_instance_q31; /** * @brief Processing function for Q31 normalized LMS filter. * @param[in] S points to an instance of the Q31 normalized LMS filter structure. * @param[in] pSrc points to the block of input data. * @param[in] pRef points to the block of reference data. * @param[out] pOut points to the block of output data. * @param[out] pErr points to the block of error data. * @param[in] blockSize number of samples to process. */ void arm_lms_norm_q31( arm_lms_norm_instance_q31 * S, q31_t * pSrc, q31_t * pRef, q31_t * pOut, q31_t * pErr, uint32_t blockSize); /** * @brief Initialization function for Q31 normalized LMS filter. * @param[in] S points to an instance of the Q31 normalized LMS filter structure. * @param[in] numTaps number of filter coefficients. * @param[in] pCoeffs points to coefficient buffer. * @param[in] pState points to state buffer. * @param[in] mu step size that controls filter coefficient updates. * @param[in] blockSize number of samples to process. * @param[in] postShift bit shift applied to coefficients. */ void arm_lms_norm_init_q31( arm_lms_norm_instance_q31 * S, uint16_t numTaps, q31_t * pCoeffs, q31_t * pState, q31_t mu, uint32_t blockSize, uint8_t postShift); /** * @brief Instance structure for the Q15 normalized LMS filter. */ typedef struct { uint16_t numTaps; /**< Number of coefficients in the filter. */ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ q15_t mu; /**< step size that controls filter coefficient updates. */ uint8_t postShift; /**< bit shift applied to coefficients. */ q15_t *recipTable; /**< Points to the reciprocal initial value table. */ q15_t energy; /**< saves previous frame energy. */ q15_t x0; /**< saves previous input sample. */ } arm_lms_norm_instance_q15; /** * @brief Processing function for Q15 normalized LMS filter. * @param[in] S points to an instance of the Q15 normalized LMS filter structure. * @param[in] pSrc points to the block of input data. * @param[in] pRef points to the block of reference data. * @param[out] pOut points to the block of output data. * @param[out] pErr points to the block of error data. * @param[in] blockSize number of samples to process. */ void arm_lms_norm_q15( arm_lms_norm_instance_q15 * S, q15_t * pSrc, q15_t * pRef, q15_t * pOut, q15_t * pErr, uint32_t blockSize); /** * @brief Initialization function for Q15 normalized LMS filter. * @param[in] S points to an instance of the Q15 normalized LMS filter structure. * @param[in] numTaps number of filter coefficients. * @param[in] pCoeffs points to coefficient buffer. * @param[in] pState points to state buffer. * @param[in] mu step size that controls filter coefficient updates. * @param[in] blockSize number of samples to process. * @param[in] postShift bit shift applied to coefficients. */ void arm_lms_norm_init_q15( arm_lms_norm_instance_q15 * S, uint16_t numTaps, q15_t * pCoeffs, q15_t * pState, q15_t mu, uint32_t blockSize, uint8_t postShift); /** * @brief Correlation of floating-point sequences. * @param[in] pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. */ void arm_correlate_f32( float32_t * pSrcA, uint32_t srcALen, float32_t * pSrcB, uint32_t srcBLen, float32_t * pDst); /** * @brief Correlation of Q15 sequences * @param[in] pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. */ void arm_correlate_opt_q15( q15_t * pSrcA, uint32_t srcALen, q15_t * pSrcB, uint32_t srcBLen, q15_t * pDst, q15_t * pScratch); /** * @brief Correlation of Q15 sequences. * @param[in] pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. */ void arm_correlate_q15( q15_t * pSrcA, uint32_t srcALen, q15_t * pSrcB, uint32_t srcBLen, q15_t * pDst); /** * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. * @param[in] pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. */ void arm_correlate_fast_q15( q15_t * pSrcA, uint32_t srcALen, q15_t * pSrcB, uint32_t srcBLen, q15_t * pDst); /** * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. * @param[in] pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. */ void arm_correlate_fast_opt_q15( q15_t * pSrcA, uint32_t srcALen, q15_t * pSrcB, uint32_t srcBLen, q15_t * pDst, q15_t * pScratch); /** * @brief Correlation of Q31 sequences. * @param[in] pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. */ void arm_correlate_q31( q31_t * pSrcA, uint32_t srcALen, q31_t * pSrcB, uint32_t srcBLen, q31_t * pDst); /** * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 * @param[in] pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. */ void arm_correlate_fast_q31( q31_t * pSrcA, uint32_t srcALen, q31_t * pSrcB, uint32_t srcBLen, q31_t * pDst); /** * @brief Correlation of Q7 sequences. * @param[in] pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). */ void arm_correlate_opt_q7( q7_t * pSrcA, uint32_t srcALen, q7_t * pSrcB, uint32_t srcBLen, q7_t * pDst, q15_t * pScratch1, q15_t * pScratch2); /** * @brief Correlation of Q7 sequences. * @param[in] pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. */ void arm_correlate_q7( q7_t * pSrcA, uint32_t srcALen, q7_t * pSrcB, uint32_t srcBLen, q7_t * pDst); /** * @brief Instance structure for the floating-point sparse FIR filter. */ typedef struct { uint16_t numTaps; /**< number of coefficients in the filter. */ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ } arm_fir_sparse_instance_f32; /** * @brief Instance structure for the Q31 sparse FIR filter. */ typedef struct { uint16_t numTaps; /**< number of coefficients in the filter. */ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ } arm_fir_sparse_instance_q31; /** * @brief Instance structure for the Q15 sparse FIR filter. */ typedef struct { uint16_t numTaps; /**< number of coefficients in the filter. */ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ } arm_fir_sparse_instance_q15; /** * @brief Instance structure for the Q7 sparse FIR filter. */ typedef struct { uint16_t numTaps; /**< number of coefficients in the filter. */ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ } arm_fir_sparse_instance_q7; /** * @brief Processing function for the floating-point sparse FIR filter. * @param[in] S points to an instance of the floating-point sparse FIR structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data * @param[in] pScratchIn points to a temporary buffer of size blockSize. * @param[in] blockSize number of input samples to process per call. */ void arm_fir_sparse_f32( arm_fir_sparse_instance_f32 * S, float32_t * pSrc, float32_t * pDst, float32_t * pScratchIn, uint32_t blockSize); /** * @brief Initialization function for the floating-point sparse FIR filter. * @param[in,out] S points to an instance of the floating-point sparse FIR structure. * @param[in] numTaps number of nonzero coefficients in the filter. * @param[in] pCoeffs points to the array of filter coefficients. * @param[in] pState points to the state buffer. * @param[in] pTapDelay points to the array of offset times. * @param[in] maxDelay maximum offset time supported. * @param[in] blockSize number of samples that will be processed per block. */ void arm_fir_sparse_init_f32( arm_fir_sparse_instance_f32 * S, uint16_t numTaps, float32_t * pCoeffs, float32_t * pState, int32_t * pTapDelay, uint16_t maxDelay, uint32_t blockSize); /** * @brief Processing function for the Q31 sparse FIR filter. * @param[in] S points to an instance of the Q31 sparse FIR structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data * @param[in] pScratchIn points to a temporary buffer of size blockSize. * @param[in] blockSize number of input samples to process per call. */ void arm_fir_sparse_q31( arm_fir_sparse_instance_q31 * S, q31_t * pSrc, q31_t * pDst, q31_t * pScratchIn, uint32_t blockSize); /** * @brief Initialization function for the Q31 sparse FIR filter. * @param[in,out] S points to an instance of the Q31 sparse FIR structure. * @param[in] numTaps number of nonzero coefficients in the filter. * @param[in] pCoeffs points to the array of filter coefficients. * @param[in] pState points to the state buffer. * @param[in] pTapDelay points to the array of offset times. * @param[in] maxDelay maximum offset time supported. * @param[in] blockSize number of samples that will be processed per block. */ void arm_fir_sparse_init_q31( arm_fir_sparse_instance_q31 * S, uint16_t numTaps, q31_t * pCoeffs, q31_t * pState, int32_t * pTapDelay, uint16_t maxDelay, uint32_t blockSize); /** * @brief Processing function for the Q15 sparse FIR filter. * @param[in] S points to an instance of the Q15 sparse FIR structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data * @param[in] pScratchIn points to a temporary buffer of size blockSize. * @param[in] pScratchOut points to a temporary buffer of size blockSize. * @param[in] blockSize number of input samples to process per call. */ void arm_fir_sparse_q15( arm_fir_sparse_instance_q15 * S, q15_t * pSrc, q15_t * pDst, q15_t * pScratchIn, q31_t * pScratchOut, uint32_t blockSize); /** * @brief Initialization function for the Q15 sparse FIR filter. * @param[in,out] S points to an instance of the Q15 sparse FIR structure. * @param[in] numTaps number of nonzero coefficients in the filter. * @param[in] pCoeffs points to the array of filter coefficients. * @param[in] pState points to the state buffer. * @param[in] pTapDelay points to the array of offset times. * @param[in] maxDelay maximum offset time supported. * @param[in] blockSize number of samples that will be processed per block. */ void arm_fir_sparse_init_q15( arm_fir_sparse_instance_q15 * S, uint16_t numTaps, q15_t * pCoeffs, q15_t * pState, int32_t * pTapDelay, uint16_t maxDelay, uint32_t blockSize); /** * @brief Processing function for the Q7 sparse FIR filter. * @param[in] S points to an instance of the Q7 sparse FIR structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data * @param[in] pScratchIn points to a temporary buffer of size blockSize. * @param[in] pScratchOut points to a temporary buffer of size blockSize. * @param[in] blockSize number of input samples to process per call. */ void arm_fir_sparse_q7( arm_fir_sparse_instance_q7 * S, q7_t * pSrc, q7_t * pDst, q7_t * pScratchIn, q31_t * pScratchOut, uint32_t blockSize); /** * @brief Initialization function for the Q7 sparse FIR filter. * @param[in,out] S points to an instance of the Q7 sparse FIR structure. * @param[in] numTaps number of nonzero coefficients in the filter. * @param[in] pCoeffs points to the array of filter coefficients. * @param[in] pState points to the state buffer. * @param[in] pTapDelay points to the array of offset times. * @param[in] maxDelay maximum offset time supported. * @param[in] blockSize number of samples that will be processed per block. */ void arm_fir_sparse_init_q7( arm_fir_sparse_instance_q7 * S, uint16_t numTaps, q7_t * pCoeffs, q7_t * pState, int32_t * pTapDelay, uint16_t maxDelay, uint32_t blockSize); /** * @brief Floating-point sin_cos function. * @param[in] theta input value in degrees * @param[out] pSinVal points to the processed sine output. * @param[out] pCosVal points to the processed cos output. */ void arm_sin_cos_f32( float32_t theta, float32_t * pSinVal, float32_t * pCosVal); /** * @brief Q31 sin_cos function. * @param[in] theta scaled input value in degrees * @param[out] pSinVal points to the processed sine output. * @param[out] pCosVal points to the processed cosine output. */ void arm_sin_cos_q31( q31_t theta, q31_t * pSinVal, q31_t * pCosVal); /** * @brief Floating-point complex conjugate. * @param[in] pSrc points to the input vector * @param[out] pDst points to the output vector * @param[in] numSamples number of complex samples in each vector */ void arm_cmplx_conj_f32( float32_t * pSrc, float32_t * pDst, uint32_t numSamples); /** * @brief Q31 complex conjugate. * @param[in] pSrc points to the input vector * @param[out] pDst points to the output vector * @param[in] numSamples number of complex samples in each vector */ void arm_cmplx_conj_q31( q31_t * pSrc, q31_t * pDst, uint32_t numSamples); /** * @brief Q15 complex conjugate. * @param[in] pSrc points to the input vector * @param[out] pDst points to the output vector * @param[in] numSamples number of complex samples in each vector */ void arm_cmplx_conj_q15( q15_t * pSrc, q15_t * pDst, uint32_t numSamples); /** * @brief Floating-point complex magnitude squared * @param[in] pSrc points to the complex input vector * @param[out] pDst points to the real output vector * @param[in] numSamples number of complex samples in the input vector */ void arm_cmplx_mag_squared_f32( float32_t * pSrc, float32_t * pDst, uint32_t numSamples); /** * @brief Q31 complex magnitude squared * @param[in] pSrc points to the complex input vector * @param[out] pDst points to the real output vector * @param[in] numSamples number of complex samples in the input vector */ void arm_cmplx_mag_squared_q31( q31_t * pSrc, q31_t * pDst, uint32_t numSamples); /** * @brief Q15 complex magnitude squared * @param[in] pSrc points to the complex input vector * @param[out] pDst points to the real output vector * @param[in] numSamples number of complex samples in the input vector */ void arm_cmplx_mag_squared_q15( q15_t * pSrc, q15_t * pDst, uint32_t numSamples); /** * @ingroup groupController */ /** * @defgroup PID PID Motor Control * * A Proportional Integral Derivative (PID) controller is a generic feedback control * loop mechanism widely used in industrial control systems. * A PID controller is the most commonly used type of feedback controller. * * This set of functions implements (PID) controllers * for Q15, Q31, and floating-point data types. The functions operate on a single sample * of data and each call to the function returns a single processed value. * <code>S</code> points to an instance of the PID control data structure. <code>in</code> * is the input sample value. The functions return the output value. * * \par Algorithm: * <pre> * y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] * A0 = Kp + Ki + Kd * A1 = (-Kp ) - (2 * Kd ) * A2 = Kd </pre> * * \par * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant * * \par * \image html PID.gif "Proportional Integral Derivative Controller" * * \par * The PID controller calculates an "error" value as the difference between * the measured output and the reference input. * The controller attempts to minimize the error by adjusting the process control inputs. * The proportional value determines the reaction to the current error, * the integral value determines the reaction based on the sum of recent errors, * and the derivative value determines the reaction based on the rate at which the error has been changing. * * \par Instance Structure * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. * A separate instance structure must be defined for each PID Controller. * There are separate instance structure declarations for each of the 3 supported data types. * * \par Reset Functions * There is also an associated reset function for each data type which clears the state array. * * \par Initialization Functions * There is also an associated initialization function for each data type. * The initialization function performs the following operations: * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains. * - Zeros out the values in the state buffer. * * \par * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. * * \par Fixed-Point Behavior * Care must be taken when using the fixed-point versions of the PID Controller functions. * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. * Refer to the function specific documentation below for usage guidelines. */ /** * @addtogroup PID * @{ */ /** * @brief Process function for the floating-point PID Control. * @param[in,out] S is an instance of the floating-point PID Control structure * @param[in] in input sample to process * @return out processed output sample. */ CMSIS_INLINE __STATIC_INLINE float32_t arm_pid_f32( arm_pid_instance_f32 * S, float32_t in) { float32_t out; /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ out = (S->A0 * in) + (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); /* Update state */ S->state[1] = S->state[0]; S->state[0] = in; S->state[2] = out; /* return to application */ return (out); } /** * @brief Process function for the Q31 PID Control. * @param[in,out] S points to an instance of the Q31 PID Control structure * @param[in] in input sample to process * @return out processed output sample. * * <b>Scaling and Overflow Behavior:</b> * \par * The function is implemented using an internal 64-bit accumulator. * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. * Thus, if the accumulator result overflows it wraps around rather than clip. * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. */ CMSIS_INLINE __STATIC_INLINE q31_t arm_pid_q31( arm_pid_instance_q31 * S, q31_t in) { q63_t acc; q31_t out; /* acc = A0 * x[n] */ acc = (q63_t) S->A0 * in; /* acc += A1 * x[n-1] */ acc += (q63_t) S->A1 * S->state[0]; /* acc += A2 * x[n-2] */ acc += (q63_t) S->A2 * S->state[1]; /* convert output to 1.31 format to add y[n-1] */ out = (q31_t) (acc >> 31U); /* out += y[n-1] */ out += S->state[2]; /* Update state */ S->state[1] = S->state[0]; S->state[0] = in; S->state[2] = out; /* return to application */ return (out); } /** * @brief Process function for the Q15 PID Control. * @param[in,out] S points to an instance of the Q15 PID Control structure * @param[in] in input sample to process * @return out processed output sample. * * <b>Scaling and Overflow Behavior:</b> * \par * The function is implemented using a 64-bit internal accumulator. * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. * Lastly, the accumulator is saturated to yield a result in 1.15 format. */ CMSIS_INLINE __STATIC_INLINE q15_t arm_pid_q15( arm_pid_instance_q15 * S, q15_t in) { q63_t acc; q15_t out; #if defined (ARM_MATH_DSP) __SIMD32_TYPE *vstate; /* Implementation of PID controller */ /* acc = A0 * x[n] */ acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in); /* acc += A1 * x[n-1] + A2 * x[n-2] */ vstate = __SIMD32_CONST(S->state); acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t)*vstate, (uint64_t)acc); #else /* acc = A0 * x[n] */ acc = ((q31_t) S->A0) * in; /* acc += A1 * x[n-1] + A2 * x[n-2] */ acc += (q31_t) S->A1 * S->state[0]; acc += (q31_t) S->A2 * S->state[1]; #endif /* acc += y[n-1] */ acc += (q31_t) S->state[2] << 15; /* saturate the output */ out = (q15_t) (__SSAT((acc >> 15), 16)); /* Update state */ S->state[1] = S->state[0]; S->state[0] = in; S->state[2] = out; /* return to application */ return (out); } /** * @} end of PID group */ /** * @brief Floating-point matrix inverse. * @param[in] src points to the instance of the input floating-point matrix structure. * @param[out] dst points to the instance of the output floating-point matrix structure. * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. */ arm_status arm_mat_inverse_f32( const arm_matrix_instance_f32 * src, arm_matrix_instance_f32 * dst); /** * @brief Floating-point matrix inverse. * @param[in] src points to the instance of the input floating-point matrix structure. * @param[out] dst points to the instance of the output floating-point matrix structure. * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. */ arm_status arm_mat_inverse_f64( const arm_matrix_instance_f64 * src, arm_matrix_instance_f64 * dst); /** * @ingroup groupController */ /** * @defgroup clarke Vector Clarke Transform * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. * Generally the Clarke transform uses three-phase currents <code>Ia, Ib and Ic</code> to calculate currents * in the two-phase orthogonal stator axis <code>Ialpha</code> and <code>Ibeta</code>. * When <code>Ialpha</code> is superposed with <code>Ia</code> as shown in the figure below * \image html clarke.gif Stator current space vector and its components in (a,b). * and <code>Ia + Ib + Ic = 0</code>, in this condition <code>Ialpha</code> and <code>Ibeta</code> * can be calculated using only <code>Ia</code> and <code>Ib</code>. * * The function operates on a single sample of data and each call to the function returns the processed output. * The library provides separate functions for Q31 and floating-point data types. * \par Algorithm * \image html clarkeFormula.gif * where <code>Ia</code> and <code>Ib</code> are the instantaneous stator phases and * <code>pIalpha</code> and <code>pIbeta</code> are the two coordinates of time invariant vector. * \par Fixed-Point Behavior * Care must be taken when using the Q31 version of the Clarke transform. * In particular, the overflow and saturation behavior of the accumulator used must be considered. * Refer to the function specific documentation below for usage guidelines. */ /** * @addtogroup clarke * @{ */ /** * * @brief Floating-point Clarke transform * @param[in] Ia input three-phase coordinate <code>a</code> * @param[in] Ib input three-phase coordinate <code>b</code> * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha * @param[out] pIbeta points to output two-phase orthogonal vector axis beta */ CMSIS_INLINE __STATIC_INLINE void arm_clarke_f32( float32_t Ia, float32_t Ib, float32_t * pIalpha, float32_t * pIbeta) { /* Calculate pIalpha using the equation, pIalpha = Ia */ *pIalpha = Ia; /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */ *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib); } /** * @brief Clarke transform for Q31 version * @param[in] Ia input three-phase coordinate <code>a</code> * @param[in] Ib input three-phase coordinate <code>b</code> * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha * @param[out] pIbeta points to output two-phase orthogonal vector axis beta * * <b>Scaling and Overflow Behavior:</b> * \par * The function is implemented using an internal 32-bit accumulator. * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. * There is saturation on the addition, hence there is no risk of overflow. */ CMSIS_INLINE __STATIC_INLINE void arm_clarke_q31( q31_t Ia, q31_t Ib, q31_t * pIalpha, q31_t * pIbeta) { q31_t product1, product2; /* Temporary variables used to store intermediate results */ /* Calculating pIalpha from Ia by equation pIalpha = Ia */ *pIalpha = Ia; /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30); /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30); /* pIbeta is calculated by adding the intermediate products */ *pIbeta = __QADD(product1, product2); } /** * @} end of clarke group */ /** * @brief Converts the elements of the Q7 vector to Q31 vector. * @param[in] pSrc input pointer * @param[out] pDst output pointer * @param[in] blockSize number of samples to process */ void arm_q7_to_q31( q7_t * pSrc, q31_t * pDst, uint32_t blockSize); /** * @ingroup groupController */ /** * @defgroup inv_clarke Vector Inverse Clarke Transform * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases. * * The function operates on a single sample of data and each call to the function returns the processed output. * The library provides separate functions for Q31 and floating-point data types. * \par Algorithm * \image html clarkeInvFormula.gif * where <code>pIa</code> and <code>pIb</code> are the instantaneous stator phases and * <code>Ialpha</code> and <code>Ibeta</code> are the two coordinates of time invariant vector. * \par Fixed-Point Behavior * Care must be taken when using the Q31 version of the Clarke transform. * In particular, the overflow and saturation behavior of the accumulator used must be considered. * Refer to the function specific documentation below for usage guidelines. */ /** * @addtogroup inv_clarke * @{ */ /** * @brief Floating-point Inverse Clarke transform * @param[in] Ialpha input two-phase orthogonal vector axis alpha * @param[in] Ibeta input two-phase orthogonal vector axis beta * @param[out] pIa points to output three-phase coordinate <code>a</code> * @param[out] pIb points to output three-phase coordinate <code>b</code> */ CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_f32( float32_t Ialpha, float32_t Ibeta, float32_t * pIa, float32_t * pIb) { /* Calculating pIa from Ialpha by equation pIa = Ialpha */ *pIa = Ialpha; /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */ *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta; } /** * @brief Inverse Clarke transform for Q31 version * @param[in] Ialpha input two-phase orthogonal vector axis alpha * @param[in] Ibeta input two-phase orthogonal vector axis beta * @param[out] pIa points to output three-phase coordinate <code>a</code> * @param[out] pIb points to output three-phase coordinate <code>b</code> * * <b>Scaling and Overflow Behavior:</b> * \par * The function is implemented using an internal 32-bit accumulator. * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. * There is saturation on the subtraction, hence there is no risk of overflow. */ CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_q31( q31_t Ialpha, q31_t Ibeta, q31_t * pIa, q31_t * pIb) { q31_t product1, product2; /* Temporary variables used to store intermediate results */ /* Calculating pIa from Ialpha by equation pIa = Ialpha */ *pIa = Ialpha; /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31); /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31); /* pIb is calculated by subtracting the products */ *pIb = __QSUB(product2, product1); } /** * @} end of inv_clarke group */ /** * @brief Converts the elements of the Q7 vector to Q15 vector. * @param[in] pSrc input pointer * @param[out] pDst output pointer * @param[in] blockSize number of samples to process */ void arm_q7_to_q15( q7_t * pSrc, q15_t * pDst, uint32_t blockSize); /** * @ingroup groupController */ /** * @defgroup park Vector Park Transform * * Forward Park transform converts the input two-coordinate vector to flux and torque components. * The Park transform can be used to realize the transformation of the <code>Ialpha</code> and the <code>Ibeta</code> currents * from the stationary to the moving reference frame and control the spatial relationship between * the stator vector current and rotor flux vector. * If we consider the d axis aligned with the rotor flux, the diagram below shows the * current vector and the relationship from the two reference frames: * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame" * * The function operates on a single sample of data and each call to the function returns the processed output. * The library provides separate functions for Q31 and floating-point data types. * \par Algorithm * \image html parkFormula.gif * where <code>Ialpha</code> and <code>Ibeta</code> are the stator vector components, * <code>pId</code> and <code>pIq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the * cosine and sine values of theta (rotor flux position). * \par Fixed-Point Behavior * Care must be taken when using the Q31 version of the Park transform. * In particular, the overflow and saturation behavior of the accumulator used must be considered. * Refer to the function specific documentation below for usage guidelines. */ /** * @addtogroup park * @{ */ /** * @brief Floating-point Park transform * @param[in] Ialpha input two-phase vector coordinate alpha * @param[in] Ibeta input two-phase vector coordinate beta * @param[out] pId points to output rotor reference frame d * @param[out] pIq points to output rotor reference frame q * @param[in] sinVal sine value of rotation angle theta * @param[in] cosVal cosine value of rotation angle theta * * The function implements the forward Park transform. * */ CMSIS_INLINE __STATIC_INLINE void arm_park_f32( float32_t Ialpha, float32_t Ibeta, float32_t * pId, float32_t * pIq, float32_t sinVal, float32_t cosVal) { /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */ *pId = Ialpha * cosVal + Ibeta * sinVal; /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */ *pIq = -Ialpha * sinVal + Ibeta * cosVal; } /** * @brief Park transform for Q31 version * @param[in] Ialpha input two-phase vector coordinate alpha * @param[in] Ibeta input two-phase vector coordinate beta * @param[out] pId points to output rotor reference frame d * @param[out] pIq points to output rotor reference frame q * @param[in] sinVal sine value of rotation angle theta * @param[in] cosVal cosine value of rotation angle theta * * <b>Scaling and Overflow Behavior:</b> * \par * The function is implemented using an internal 32-bit accumulator. * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. * There is saturation on the addition and subtraction, hence there is no risk of overflow. */ CMSIS_INLINE __STATIC_INLINE void arm_park_q31( q31_t Ialpha, q31_t Ibeta, q31_t * pId, q31_t * pIq, q31_t sinVal, q31_t cosVal) { q31_t product1, product2; /* Temporary variables used to store intermediate results */ q31_t product3, product4; /* Temporary variables used to store intermediate results */ /* Intermediate product is calculated by (Ialpha * cosVal) */ product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31); /* Intermediate product is calculated by (Ibeta * sinVal) */ product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31); /* Intermediate product is calculated by (Ialpha * sinVal) */ product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31); /* Intermediate product is calculated by (Ibeta * cosVal) */ product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31); /* Calculate pId by adding the two intermediate products 1 and 2 */ *pId = __QADD(product1, product2); /* Calculate pIq by subtracting the two intermediate products 3 from 4 */ *pIq = __QSUB(product4, product3); } /** * @} end of park group */ /** * @brief Converts the elements of the Q7 vector to floating-point vector. * @param[in] pSrc is input pointer * @param[out] pDst is output pointer * @param[in] blockSize is the number of samples to process */ void arm_q7_to_float( q7_t * pSrc, float32_t * pDst, uint32_t blockSize); /** * @ingroup groupController */ /** * @defgroup inv_park Vector Inverse Park transform * Inverse Park transform converts the input flux and torque components to two-coordinate vector. * * The function operates on a single sample of data and each call to the function returns the processed output. * The library provides separate functions for Q31 and floating-point data types. * \par Algorithm * \image html parkInvFormula.gif * where <code>pIalpha</code> and <code>pIbeta</code> are the stator vector components, * <code>Id</code> and <code>Iq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the * cosine and sine values of theta (rotor flux position). * \par Fixed-Point Behavior * Care must be taken when using the Q31 version of the Park transform. * In particular, the overflow and saturation behavior of the accumulator used must be considered. * Refer to the function specific documentation below for usage guidelines. */ /** * @addtogroup inv_park * @{ */ /** * @brief Floating-point Inverse Park transform * @param[in] Id input coordinate of rotor reference frame d * @param[in] Iq input coordinate of rotor reference frame q * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha * @param[out] pIbeta points to output two-phase orthogonal vector axis beta * @param[in] sinVal sine value of rotation angle theta * @param[in] cosVal cosine value of rotation angle theta */ CMSIS_INLINE __STATIC_INLINE void arm_inv_park_f32( float32_t Id, float32_t Iq, float32_t * pIalpha, float32_t * pIbeta, float32_t sinVal, float32_t cosVal) { /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */ *pIalpha = Id * cosVal - Iq * sinVal; /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */ *pIbeta = Id * sinVal + Iq * cosVal; } /** * @brief Inverse Park transform for Q31 version * @param[in] Id input coordinate of rotor reference frame d * @param[in] Iq input coordinate of rotor reference frame q * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha * @param[out] pIbeta points to output two-phase orthogonal vector axis beta * @param[in] sinVal sine value of rotation angle theta * @param[in] cosVal cosine value of rotation angle theta * * <b>Scaling and Overflow Behavior:</b> * \par * The function is implemented using an internal 32-bit accumulator. * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. * There is saturation on the addition, hence there is no risk of overflow. */ CMSIS_INLINE __STATIC_INLINE void arm_inv_park_q31( q31_t Id, q31_t Iq, q31_t * pIalpha, q31_t * pIbeta, q31_t sinVal, q31_t cosVal) { q31_t product1, product2; /* Temporary variables used to store intermediate results */ q31_t product3, product4; /* Temporary variables used to store intermediate results */ /* Intermediate product is calculated by (Id * cosVal) */ product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31); /* Intermediate product is calculated by (Iq * sinVal) */ product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31); /* Intermediate product is calculated by (Id * sinVal) */ product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31); /* Intermediate product is calculated by (Iq * cosVal) */ product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31); /* Calculate pIalpha by using the two intermediate products 1 and 2 */ *pIalpha = __QSUB(product1, product2); /* Calculate pIbeta by using the two intermediate products 3 and 4 */ *pIbeta = __QADD(product4, product3); } /** * @} end of Inverse park group */ /** * @brief Converts the elements of the Q31 vector to floating-point vector. * @param[in] pSrc is input pointer * @param[out] pDst is output pointer * @param[in] blockSize is the number of samples to process */ void arm_q31_to_float( q31_t * pSrc, float32_t * pDst, uint32_t blockSize); /** * @ingroup groupInterpolation */ /** * @defgroup LinearInterpolate Linear Interpolation * * Linear interpolation is a method of curve fitting using linear polynomials. * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line * * \par * \image html LinearInterp.gif "Linear interpolation" * * \par * A Linear Interpolate function calculates an output value(y), for the input(x) * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values) * * \par Algorithm: * <pre> * y = y0 + (x - x0) * ((y1 - y0)/(x1-x0)) * where x0, x1 are nearest values of input x * y0, y1 are nearest values to output y * </pre> * * \par * This set of functions implements Linear interpolation process * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single * sample of data and each call to the function returns a single processed value. * <code>S</code> points to an instance of the Linear Interpolate function data structure. * <code>x</code> is the input sample value. The functions returns the output value. * * \par * if x is outside of the table boundary, Linear interpolation returns first value of the table * if x is below input range and returns last value of table if x is above range. */ /** * @addtogroup LinearInterpolate * @{ */ /** * @brief Process function for the floating-point Linear Interpolation Function. * @param[in,out] S is an instance of the floating-point Linear Interpolation structure * @param[in] x input sample to process * @return y processed output sample. * */ CMSIS_INLINE __STATIC_INLINE float32_t arm_linear_interp_f32( arm_linear_interp_instance_f32 * S, float32_t x) { float32_t y; float32_t x0, x1; /* Nearest input values */ float32_t y0, y1; /* Nearest output values */ float32_t xSpacing = S->xSpacing; /* spacing between input values */ int32_t i; /* Index variable */ float32_t *pYData = S->pYData; /* pointer to output table */ /* Calculation of index */ i = (int32_t) ((x - S->x1) / xSpacing); if (i < 0) { /* Iniatilize output for below specified range as least output value of table */ y = pYData[0]; } else if ((uint32_t)i >= S->nValues) { /* Iniatilize output for above specified range as last output value of table */ y = pYData[S->nValues - 1]; } else { /* Calculation of nearest input values */ x0 = S->x1 + i * xSpacing; x1 = S->x1 + (i + 1) * xSpacing; /* Read of nearest output values */ y0 = pYData[i]; y1 = pYData[i + 1]; /* Calculation of output */ y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0)); } /* returns output value */ return (y); } /** * * @brief Process function for the Q31 Linear Interpolation Function. * @param[in] pYData pointer to Q31 Linear Interpolation table * @param[in] x input sample to process * @param[in] nValues number of table values * @return y processed output sample. * * \par * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. * This function can support maximum of table size 2^12. * */ CMSIS_INLINE __STATIC_INLINE q31_t arm_linear_interp_q31( q31_t * pYData, q31_t x, uint32_t nValues) { q31_t y; /* output */ q31_t y0, y1; /* Nearest output values */ q31_t fract; /* fractional part */ int32_t index; /* Index to read nearest output values */ /* Input is in 12.20 format */ /* 12 bits for the table index */ /* Index value calculation */ index = ((x & (q31_t)0xFFF00000) >> 20); if (index >= (int32_t)(nValues - 1)) { return (pYData[nValues - 1]); } else if (index < 0) { return (pYData[0]); } else { /* 20 bits for the fractional part */ /* shift left by 11 to keep fract in 1.31 format */ fract = (x & 0x000FFFFF) << 11; /* Read two nearest output values from the index in 1.31(q31) format */ y0 = pYData[index]; y1 = pYData[index + 1]; /* Calculation of y0 * (1-fract) and y is in 2.30 format */ y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32)); /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ y += ((q31_t) (((q63_t) y1 * fract) >> 32)); /* Convert y to 1.31 format */ return (y << 1U); } } /** * * @brief Process function for the Q15 Linear Interpolation Function. * @param[in] pYData pointer to Q15 Linear Interpolation table * @param[in] x input sample to process * @param[in] nValues number of table values * @return y processed output sample. * * \par * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. * This function can support maximum of table size 2^12. * */ CMSIS_INLINE __STATIC_INLINE q15_t arm_linear_interp_q15( q15_t * pYData, q31_t x, uint32_t nValues) { q63_t y; /* output */ q15_t y0, y1; /* Nearest output values */ q31_t fract; /* fractional part */ int32_t index; /* Index to read nearest output values */ /* Input is in 12.20 format */ /* 12 bits for the table index */ /* Index value calculation */ index = ((x & (int32_t)0xFFF00000) >> 20); if (index >= (int32_t)(nValues - 1)) { return (pYData[nValues - 1]); } else if (index < 0) { return (pYData[0]); } else { /* 20 bits for the fractional part */ /* fract is in 12.20 format */ fract = (x & 0x000FFFFF); /* Read two nearest output values from the index */ y0 = pYData[index]; y1 = pYData[index + 1]; /* Calculation of y0 * (1-fract) and y is in 13.35 format */ y = ((q63_t) y0 * (0xFFFFF - fract)); /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ y += ((q63_t) y1 * (fract)); /* convert y to 1.15 format */ return (q15_t) (y >> 20); } } /** * * @brief Process function for the Q7 Linear Interpolation Function. * @param[in] pYData pointer to Q7 Linear Interpolation table * @param[in] x input sample to process * @param[in] nValues number of table values * @return y processed output sample. * * \par * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. * This function can support maximum of table size 2^12. */ CMSIS_INLINE __STATIC_INLINE q7_t arm_linear_interp_q7( q7_t * pYData, q31_t x, uint32_t nValues) { q31_t y; /* output */ q7_t y0, y1; /* Nearest output values */ q31_t fract; /* fractional part */ uint32_t index; /* Index to read nearest output values */ /* Input is in 12.20 format */ /* 12 bits for the table index */ /* Index value calculation */ if (x < 0) { return (pYData[0]); } index = (x >> 20) & 0xfff; if (index >= (nValues - 1)) { return (pYData[nValues - 1]); } else { /* 20 bits for the fractional part */ /* fract is in 12.20 format */ fract = (x & 0x000FFFFF); /* Read two nearest output values from the index and are in 1.7(q7) format */ y0 = pYData[index]; y1 = pYData[index + 1]; /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */ y = ((y0 * (0xFFFFF - fract))); /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */ y += (y1 * fract); /* convert y to 1.7(q7) format */ return (q7_t) (y >> 20); } } /** * @} end of LinearInterpolate group */ /** * @brief Fast approximation to the trigonometric sine function for floating-point data. * @param[in] x input value in radians. * @return sin(x). */ float32_t arm_sin_f32( float32_t x); /** * @brief Fast approximation to the trigonometric sine function for Q31 data. * @param[in] x Scaled input value in radians. * @return sin(x). */ q31_t arm_sin_q31( q31_t x); /** * @brief Fast approximation to the trigonometric sine function for Q15 data. * @param[in] x Scaled input value in radians. * @return sin(x). */ q15_t arm_sin_q15( q15_t x); /** * @brief Fast approximation to the trigonometric cosine function for floating-point data. * @param[in] x input value in radians. * @return cos(x). */ float32_t arm_cos_f32( float32_t x); /** * @brief Fast approximation to the trigonometric cosine function for Q31 data. * @param[in] x Scaled input value in radians. * @return cos(x). */ q31_t arm_cos_q31( q31_t x); /** * @brief Fast approximation to the trigonometric cosine function for Q15 data. * @param[in] x Scaled input value in radians. * @return cos(x). */ q15_t arm_cos_q15( q15_t x); /** * @ingroup groupFastMath */ /** * @defgroup SQRT Square Root * * Computes the square root of a number. * There are separate functions for Q15, Q31, and floating-point data types. * The square root function is computed using the Newton-Raphson algorithm. * This is an iterative algorithm of the form: * <pre> * x1 = x0 - f(x0)/f'(x0) * </pre> * where <code>x1</code> is the current estimate, * <code>x0</code> is the previous estimate, and * <code>f'(x0)</code> is the derivative of <code>f()</code> evaluated at <code>x0</code>. * For the square root function, the algorithm reduces to: * <pre> * x0 = in/2 [initial guess] * x1 = 1/2 * ( x0 + in / x0) [each iteration] * </pre> */ /** * @addtogroup SQRT * @{ */ /** * @brief Floating-point square root function. * @param[in] in input value. * @param[out] pOut square root of input value. * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if * <code>in</code> is negative value and returns zero output for negative values. */ CMSIS_INLINE __STATIC_INLINE arm_status arm_sqrt_f32( float32_t in, float32_t * pOut) { if (in >= 0.0f) { #if (__FPU_USED == 1) && defined ( __CC_ARM ) *pOut = __sqrtf(in); #elif (__FPU_USED == 1) && (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) *pOut = __builtin_sqrtf(in); #elif (__FPU_USED == 1) && defined(__GNUC__) *pOut = __builtin_sqrtf(in); #elif (__FPU_USED == 1) && defined ( __ICCARM__ ) && (__VER__ >= 6040000) __ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in)); #else *pOut = sqrtf(in); #endif return (ARM_MATH_SUCCESS); } else { *pOut = 0.0f; return (ARM_MATH_ARGUMENT_ERROR); } } /** * @brief Q31 square root function. * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF. * @param[out] pOut square root of input value. * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if * <code>in</code> is negative value and returns zero output for negative values. */ arm_status arm_sqrt_q31( q31_t in, q31_t * pOut); /** * @brief Q15 square root function. * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF. * @param[out] pOut square root of input value. * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if * <code>in</code> is negative value and returns zero output for negative values. */ arm_status arm_sqrt_q15( q15_t in, q15_t * pOut); /** * @} end of SQRT group */ /** * @brief floating-point Circular write function. */ CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_f32( int32_t * circBuffer, int32_t L, uint16_t * writeOffset, int32_t bufferInc, const int32_t * src, int32_t srcInc, uint32_t blockSize) { uint32_t i = 0U; int32_t wOffset; /* Copy the value of Index pointer that points * to the current location where the input samples to be copied */ wOffset = *writeOffset; /* Loop over the blockSize */ i = blockSize; while (i > 0U) { /* copy the input sample to the circular buffer */ circBuffer[wOffset] = *src; /* Update the input pointer */ src += srcInc; /* Circularly update wOffset. Watch out for positive and negative value */ wOffset += bufferInc; if (wOffset >= L) wOffset -= L; /* Decrement the loop counter */ i--; } /* Update the index pointer */ *writeOffset = (uint16_t)wOffset; } /** * @brief floating-point Circular Read function. */ CMSIS_INLINE __STATIC_INLINE void arm_circularRead_f32( int32_t * circBuffer, int32_t L, int32_t * readOffset, int32_t bufferInc, int32_t * dst, int32_t * dst_base, int32_t dst_length, int32_t dstInc, uint32_t blockSize) { uint32_t i = 0U; int32_t rOffset, dst_end; /* Copy the value of Index pointer that points * to the current location from where the input samples to be read */ rOffset = *readOffset; dst_end = (int32_t) (dst_base + dst_length); /* Loop over the blockSize */ i = blockSize; while (i > 0U) { /* copy the sample from the circular buffer to the destination buffer */ *dst = circBuffer[rOffset]; /* Update the input pointer */ dst += dstInc; if (dst == (int32_t *) dst_end) { dst = dst_base; } /* Circularly update rOffset. Watch out for positive and negative value */ rOffset += bufferInc; if (rOffset >= L) { rOffset -= L; } /* Decrement the loop counter */ i--; } /* Update the index pointer */ *readOffset = rOffset; } /** * @brief Q15 Circular write function. */ CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q15( q15_t * circBuffer, int32_t L, uint16_t * writeOffset, int32_t bufferInc, const q15_t * src, int32_t srcInc, uint32_t blockSize) { uint32_t i = 0U; int32_t wOffset; /* Copy the value of Index pointer that points * to the current location where the input samples to be copied */ wOffset = *writeOffset; /* Loop over the blockSize */ i = blockSize; while (i > 0U) { /* copy the input sample to the circular buffer */ circBuffer[wOffset] = *src; /* Update the input pointer */ src += srcInc; /* Circularly update wOffset. Watch out for positive and negative value */ wOffset += bufferInc; if (wOffset >= L) wOffset -= L; /* Decrement the loop counter */ i--; } /* Update the index pointer */ *writeOffset = (uint16_t)wOffset; } /** * @brief Q15 Circular Read function. */ CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q15( q15_t * circBuffer, int32_t L, int32_t * readOffset, int32_t bufferInc, q15_t * dst, q15_t * dst_base, int32_t dst_length, int32_t dstInc, uint32_t blockSize) { uint32_t i = 0; int32_t rOffset, dst_end; /* Copy the value of Index pointer that points * to the current location from where the input samples to be read */ rOffset = *readOffset; dst_end = (int32_t) (dst_base + dst_length); /* Loop over the blockSize */ i = blockSize; while (i > 0U) { /* copy the sample from the circular buffer to the destination buffer */ *dst = circBuffer[rOffset]; /* Update the input pointer */ dst += dstInc; if (dst == (q15_t *) dst_end) { dst = dst_base; } /* Circularly update wOffset. Watch out for positive and negative value */ rOffset += bufferInc; if (rOffset >= L) { rOffset -= L; } /* Decrement the loop counter */ i--; } /* Update the index pointer */ *readOffset = rOffset; } /** * @brief Q7 Circular write function. */ CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q7( q7_t * circBuffer, int32_t L, uint16_t * writeOffset, int32_t bufferInc, const q7_t * src, int32_t srcInc, uint32_t blockSize) { uint32_t i = 0U; int32_t wOffset; /* Copy the value of Index pointer that points * to the current location where the input samples to be copied */ wOffset = *writeOffset; /* Loop over the blockSize */ i = blockSize; while (i > 0U) { /* copy the input sample to the circular buffer */ circBuffer[wOffset] = *src; /* Update the input pointer */ src += srcInc; /* Circularly update wOffset. Watch out for positive and negative value */ wOffset += bufferInc; if (wOffset >= L) wOffset -= L; /* Decrement the loop counter */ i--; } /* Update the index pointer */ *writeOffset = (uint16_t)wOffset; } /** * @brief Q7 Circular Read function. */ CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q7( q7_t * circBuffer, int32_t L, int32_t * readOffset, int32_t bufferInc, q7_t * dst, q7_t * dst_base, int32_t dst_length, int32_t dstInc, uint32_t blockSize) { uint32_t i = 0; int32_t rOffset, dst_end; /* Copy the value of Index pointer that points * to the current location from where the input samples to be read */ rOffset = *readOffset; dst_end = (int32_t) (dst_base + dst_length); /* Loop over the blockSize */ i = blockSize; while (i > 0U) { /* copy the sample from the circular buffer to the destination buffer */ *dst = circBuffer[rOffset]; /* Update the input pointer */ dst += dstInc; if (dst == (q7_t *) dst_end) { dst = dst_base; } /* Circularly update rOffset. Watch out for positive and negative value */ rOffset += bufferInc; if (rOffset >= L) { rOffset -= L; } /* Decrement the loop counter */ i--; } /* Update the index pointer */ *readOffset = rOffset; } /** * @brief Sum of the squares of the elements of a Q31 vector. * @param[in] pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] pResult is output value. */ void arm_power_q31( q31_t * pSrc, uint32_t blockSize, q63_t * pResult); /** * @brief Sum of the squares of the elements of a floating-point vector. * @param[in] pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] pResult is output value. */ void arm_power_f32( float32_t * pSrc, uint32_t blockSize, float32_t * pResult); /** * @brief Sum of the squares of the elements of a Q15 vector. * @param[in] pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] pResult is output value. */ void arm_power_q15( q15_t * pSrc, uint32_t blockSize, q63_t * pResult); /** * @brief Sum of the squares of the elements of a Q7 vector. * @param[in] pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] pResult is output value. */ void arm_power_q7( q7_t * pSrc, uint32_t blockSize, q31_t * pResult); /** * @brief Mean value of a Q7 vector. * @param[in] pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] pResult is output value. */ void arm_mean_q7( q7_t * pSrc, uint32_t blockSize, q7_t * pResult); /** * @brief Mean value of a Q15 vector. * @param[in] pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] pResult is output value. */ void arm_mean_q15( q15_t * pSrc, uint32_t blockSize, q15_t * pResult); /** * @brief Mean value of a Q31 vector. * @param[in] pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] pResult is output value. */ void arm_mean_q31( q31_t * pSrc, uint32_t blockSize, q31_t * pResult); /** * @brief Mean value of a floating-point vector. * @param[in] pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] pResult is output value. */ void arm_mean_f32( float32_t * pSrc, uint32_t blockSize, float32_t * pResult); /** * @brief Variance of the elements of a floating-point vector. * @param[in] pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] pResult is output value. */ void arm_var_f32( float32_t * pSrc, uint32_t blockSize, float32_t * pResult); /** * @brief Variance of the elements of a Q31 vector. * @param[in] pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] pResult is output value. */ void arm_var_q31( q31_t * pSrc, uint32_t blockSize, q31_t * pResult); /** * @brief Variance of the elements of a Q15 vector. * @param[in] pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] pResult is output value. */ void arm_var_q15( q15_t * pSrc, uint32_t blockSize, q15_t * pResult); /** * @brief Root Mean Square of the elements of a floating-point vector. * @param[in] pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] pResult is output value. */ void arm_rms_f32( float32_t * pSrc, uint32_t blockSize, float32_t * pResult); /** * @brief Root Mean Square of the elements of a Q31 vector. * @param[in] pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] pResult is output value. */ void arm_rms_q31( q31_t * pSrc, uint32_t blockSize, q31_t * pResult); /** * @brief Root Mean Square of the elements of a Q15 vector. * @param[in] pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] pResult is output value. */ void arm_rms_q15( q15_t * pSrc, uint32_t blockSize, q15_t * pResult); /** * @brief Standard deviation of the elements of a floating-point vector. * @param[in] pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] pResult is output value. */ void arm_std_f32( float32_t * pSrc, uint32_t blockSize, float32_t * pResult); /** * @brief Standard deviation of the elements of a Q31 vector. * @param[in] pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] pResult is output value. */ void arm_std_q31( q31_t * pSrc, uint32_t blockSize, q31_t * pResult); /** * @brief Standard deviation of the elements of a Q15 vector. * @param[in] pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] pResult is output value. */ void arm_std_q15( q15_t * pSrc, uint32_t blockSize, q15_t * pResult); /** * @brief Floating-point complex magnitude * @param[in] pSrc points to the complex input vector * @param[out] pDst points to the real output vector * @param[in] numSamples number of complex samples in the input vector */ void arm_cmplx_mag_f32( float32_t * pSrc, float32_t * pDst, uint32_t numSamples); /** * @brief Q31 complex magnitude * @param[in] pSrc points to the complex input vector * @param[out] pDst points to the real output vector * @param[in] numSamples number of complex samples in the input vector */ void arm_cmplx_mag_q31( q31_t * pSrc, q31_t * pDst, uint32_t numSamples); /** * @brief Q15 complex magnitude * @param[in] pSrc points to the complex input vector * @param[out] pDst points to the real output vector * @param[in] numSamples number of complex samples in the input vector */ void arm_cmplx_mag_q15( q15_t * pSrc, q15_t * pDst, uint32_t numSamples); /** * @brief Q15 complex dot product * @param[in] pSrcA points to the first input vector * @param[in] pSrcB points to the second input vector * @param[in] numSamples number of complex samples in each vector * @param[out] realResult real part of the result returned here * @param[out] imagResult imaginary part of the result returned here */ void arm_cmplx_dot_prod_q15( q15_t * pSrcA, q15_t * pSrcB, uint32_t numSamples, q31_t * realResult, q31_t * imagResult); /** * @brief Q31 complex dot product * @param[in] pSrcA points to the first input vector * @param[in] pSrcB points to the second input vector * @param[in] numSamples number of complex samples in each vector * @param[out] realResult real part of the result returned here * @param[out] imagResult imaginary part of the result returned here */ void arm_cmplx_dot_prod_q31( q31_t * pSrcA, q31_t * pSrcB, uint32_t numSamples, q63_t * realResult, q63_t * imagResult); /** * @brief Floating-point complex dot product * @param[in] pSrcA points to the first input vector * @param[in] pSrcB points to the second input vector * @param[in] numSamples number of complex samples in each vector * @param[out] realResult real part of the result returned here * @param[out] imagResult imaginary part of the result returned here */ void arm_cmplx_dot_prod_f32( float32_t * pSrcA, float32_t * pSrcB, uint32_t numSamples, float32_t * realResult, float32_t * imagResult); /** * @brief Q15 complex-by-real multiplication * @param[in] pSrcCmplx points to the complex input vector * @param[in] pSrcReal points to the real input vector * @param[out] pCmplxDst points to the complex output vector * @param[in] numSamples number of samples in each vector */ void arm_cmplx_mult_real_q15( q15_t * pSrcCmplx, q15_t * pSrcReal, q15_t * pCmplxDst, uint32_t numSamples); /** * @brief Q31 complex-by-real multiplication * @param[in] pSrcCmplx points to the complex input vector * @param[in] pSrcReal points to the real input vector * @param[out] pCmplxDst points to the complex output vector * @param[in] numSamples number of samples in each vector */ void arm_cmplx_mult_real_q31( q31_t * pSrcCmplx, q31_t * pSrcReal, q31_t * pCmplxDst, uint32_t numSamples); /** * @brief Floating-point complex-by-real multiplication * @param[in] pSrcCmplx points to the complex input vector * @param[in] pSrcReal points to the real input vector * @param[out] pCmplxDst points to the complex output vector * @param[in] numSamples number of samples in each vector */ void arm_cmplx_mult_real_f32( float32_t * pSrcCmplx, float32_t * pSrcReal, float32_t * pCmplxDst, uint32_t numSamples); /** * @brief Minimum value of a Q7 vector. * @param[in] pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] result is output pointer * @param[in] index is the array index of the minimum value in the input buffer. */ void arm_min_q7( q7_t * pSrc, uint32_t blockSize, q7_t * result, uint32_t * index); /** * @brief Minimum value of a Q15 vector. * @param[in] pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] pResult is output pointer * @param[in] pIndex is the array index of the minimum value in the input buffer. */ void arm_min_q15( q15_t * pSrc, uint32_t blockSize, q15_t * pResult, uint32_t * pIndex); /** * @brief Minimum value of a Q31 vector. * @param[in] pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] pResult is output pointer * @param[out] pIndex is the array index of the minimum value in the input buffer. */ void arm_min_q31( q31_t * pSrc, uint32_t blockSize, q31_t * pResult, uint32_t * pIndex); /** * @brief Minimum value of a floating-point vector. * @param[in] pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] pResult is output pointer * @param[out] pIndex is the array index of the minimum value in the input buffer. */ void arm_min_f32( float32_t * pSrc, uint32_t blockSize, float32_t * pResult, uint32_t * pIndex); /** * @brief Maximum value of a Q7 vector. * @param[in] pSrc points to the input buffer * @param[in] blockSize length of the input vector * @param[out] pResult maximum value returned here * @param[out] pIndex index of maximum value returned here */ void arm_max_q7( q7_t * pSrc, uint32_t blockSize, q7_t * pResult, uint32_t * pIndex); /** * @brief Maximum value of a Q15 vector. * @param[in] pSrc points to the input buffer * @param[in] blockSize length of the input vector * @param[out] pResult maximum value returned here * @param[out] pIndex index of maximum value returned here */ void arm_max_q15( q15_t * pSrc, uint32_t blockSize, q15_t * pResult, uint32_t * pIndex); /** * @brief Maximum value of a Q31 vector. * @param[in] pSrc points to the input buffer * @param[in] blockSize length of the input vector * @param[out] pResult maximum value returned here * @param[out] pIndex index of maximum value returned here */ void arm_max_q31( q31_t * pSrc, uint32_t blockSize, q31_t * pResult, uint32_t * pIndex); /** * @brief Maximum value of a floating-point vector. * @param[in] pSrc points to the input buffer * @param[in] blockSize length of the input vector * @param[out] pResult maximum value returned here * @param[out] pIndex index of maximum value returned here */ void arm_max_f32( float32_t * pSrc, uint32_t blockSize, float32_t * pResult, uint32_t * pIndex); /** * @brief Q15 complex-by-complex multiplication * @param[in] pSrcA points to the first input vector * @param[in] pSrcB points to the second input vector * @param[out] pDst points to the output vector * @param[in] numSamples number of complex samples in each vector */ void arm_cmplx_mult_cmplx_q15( q15_t * pSrcA, q15_t * pSrcB, q15_t * pDst, uint32_t numSamples); /** * @brief Q31 complex-by-complex multiplication * @param[in] pSrcA points to the first input vector * @param[in] pSrcB points to the second input vector * @param[out] pDst points to the output vector * @param[in] numSamples number of complex samples in each vector */ void arm_cmplx_mult_cmplx_q31( q31_t * pSrcA, q31_t * pSrcB, q31_t * pDst, uint32_t numSamples); /** * @brief Floating-point complex-by-complex multiplication * @param[in] pSrcA points to the first input vector * @param[in] pSrcB points to the second input vector * @param[out] pDst points to the output vector * @param[in] numSamples number of complex samples in each vector */ void arm_cmplx_mult_cmplx_f32( float32_t * pSrcA, float32_t * pSrcB, float32_t * pDst, uint32_t numSamples); /** * @brief Converts the elements of the floating-point vector to Q31 vector. * @param[in] pSrc points to the floating-point input vector * @param[out] pDst points to the Q31 output vector * @param[in] blockSize length of the input vector */ void arm_float_to_q31( float32_t * pSrc, q31_t * pDst, uint32_t blockSize); /** * @brief Converts the elements of the floating-point vector to Q15 vector. * @param[in] pSrc points to the floating-point input vector * @param[out] pDst points to the Q15 output vector * @param[in] blockSize length of the input vector */ void arm_float_to_q15( float32_t * pSrc, q15_t * pDst, uint32_t blockSize); /** * @brief Converts the elements of the floating-point vector to Q7 vector. * @param[in] pSrc points to the floating-point input vector * @param[out] pDst points to the Q7 output vector * @param[in] blockSize length of the input vector */ void arm_float_to_q7( float32_t * pSrc, q7_t * pDst, uint32_t blockSize); /** * @brief Converts the elements of the Q31 vector to Q15 vector. * @param[in] pSrc is input pointer * @param[out] pDst is output pointer * @param[in] blockSize is the number of samples to process */ void arm_q31_to_q15( q31_t * pSrc, q15_t * pDst, uint32_t blockSize); /** * @brief Converts the elements of the Q31 vector to Q7 vector. * @param[in] pSrc is input pointer * @param[out] pDst is output pointer * @param[in] blockSize is the number of samples to process */ void arm_q31_to_q7( q31_t * pSrc, q7_t * pDst, uint32_t blockSize); /** * @brief Converts the elements of the Q15 vector to floating-point vector. * @param[in] pSrc is input pointer * @param[out] pDst is output pointer * @param[in] blockSize is the number of samples to process */ void arm_q15_to_float( q15_t * pSrc, float32_t * pDst, uint32_t blockSize); /** * @brief Converts the elements of the Q15 vector to Q31 vector. * @param[in] pSrc is input pointer * @param[out] pDst is output pointer * @param[in] blockSize is the number of samples to process */ void arm_q15_to_q31( q15_t * pSrc, q31_t * pDst, uint32_t blockSize); /** * @brief Converts the elements of the Q15 vector to Q7 vector. * @param[in] pSrc is input pointer * @param[out] pDst is output pointer * @param[in] blockSize is the number of samples to process */ void arm_q15_to_q7( q15_t * pSrc, q7_t * pDst, uint32_t blockSize); /** * @ingroup groupInterpolation */ /** * @defgroup BilinearInterpolate Bilinear Interpolation * * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. * The underlying function <code>f(x, y)</code> is sampled on a regular grid and the interpolation process * determines values between the grid points. * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. * Bilinear interpolation is often used in image processing to rescale images. * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types. * * <b>Algorithm</b> * \par * The instance structure used by the bilinear interpolation functions describes a two dimensional data table. * For floating-point, the instance structure is defined as: * <pre> * typedef struct * { * uint16_t numRows; * uint16_t numCols; * float32_t *pData; * } arm_bilinear_interp_instance_f32; * </pre> * * \par * where <code>numRows</code> specifies the number of rows in the table; * <code>numCols</code> specifies the number of columns in the table; * and <code>pData</code> points to an array of size <code>numRows*numCols</code> values. * The data table <code>pTable</code> is organized in row order and the supplied data values fall on integer indexes. * That is, table element (x,y) is located at <code>pTable[x + y*numCols]</code> where x and y are integers. * * \par * Let <code>(x, y)</code> specify the desired interpolation point. Then define: * <pre> * XF = floor(x) * YF = floor(y) * </pre> * \par * The interpolated output point is computed as: * <pre> * f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF)) * + f(XF+1, YF) * (x-XF)*(1-(y-YF)) * + f(XF, YF+1) * (1-(x-XF))*(y-YF) * + f(XF+1, YF+1) * (x-XF)*(y-YF) * </pre> * Note that the coordinates (x, y) contain integer and fractional components. * The integer components specify which portion of the table to use while the * fractional components control the interpolation processor. * * \par * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. */ /** * @addtogroup BilinearInterpolate * @{ */ /** * * @brief Floating-point bilinear interpolation. * @param[in,out] S points to an instance of the interpolation structure. * @param[in] X interpolation coordinate. * @param[in] Y interpolation coordinate. * @return out interpolated value. */ CMSIS_INLINE __STATIC_INLINE float32_t arm_bilinear_interp_f32( const arm_bilinear_interp_instance_f32 * S, float32_t X, float32_t Y) { float32_t out; float32_t f00, f01, f10, f11; float32_t *pData = S->pData; int32_t xIndex, yIndex, index; float32_t xdiff, ydiff; float32_t b1, b2, b3, b4; xIndex = (int32_t) X; yIndex = (int32_t) Y; /* Care taken for table outside boundary */ /* Returns zero output when values are outside table boundary */ if (xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 || yIndex > (S->numCols - 1)) { return (0); } /* Calculation of index for two nearest points in X-direction */ index = (xIndex - 1) + (yIndex - 1) * S->numCols; /* Read two nearest points in X-direction */ f00 = pData[index]; f01 = pData[index + 1]; /* Calculation of index for two nearest points in Y-direction */ index = (xIndex - 1) + (yIndex) * S->numCols; /* Read two nearest points in Y-direction */ f10 = pData[index]; f11 = pData[index + 1]; /* Calculation of intermediate values */ b1 = f00; b2 = f01 - f00; b3 = f10 - f00; b4 = f00 - f01 - f10 + f11; /* Calculation of fractional part in X */ xdiff = X - xIndex; /* Calculation of fractional part in Y */ ydiff = Y - yIndex; /* Calculation of bi-linear interpolated output */ out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; /* return to application */ return (out); } /** * * @brief Q31 bilinear interpolation. * @param[in,out] S points to an instance of the interpolation structure. * @param[in] X interpolation coordinate in 12.20 format. * @param[in] Y interpolation coordinate in 12.20 format. * @return out interpolated value. */ CMSIS_INLINE __STATIC_INLINE q31_t arm_bilinear_interp_q31( arm_bilinear_interp_instance_q31 * S, q31_t X, q31_t Y) { q31_t out; /* Temporary output */ q31_t acc = 0; /* output */ q31_t xfract, yfract; /* X, Y fractional parts */ q31_t x1, x2, y1, y2; /* Nearest output values */ int32_t rI, cI; /* Row and column indices */ q31_t *pYData = S->pData; /* pointer to output table values */ uint32_t nCols = S->numCols; /* num of rows */ /* Input is in 12.20 format */ /* 12 bits for the table index */ /* Index value calculation */ rI = ((X & (q31_t)0xFFF00000) >> 20); /* Input is in 12.20 format */ /* 12 bits for the table index */ /* Index value calculation */ cI = ((Y & (q31_t)0xFFF00000) >> 20); /* Care taken for table outside boundary */ /* Returns zero output when values are outside table boundary */ if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) { return (0); } /* 20 bits for the fractional part */ /* shift left xfract by 11 to keep 1.31 format */ xfract = (X & 0x000FFFFF) << 11U; /* Read two nearest output values from the index */ x1 = pYData[(rI) + (int32_t)nCols * (cI) ]; x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1]; /* 20 bits for the fractional part */ /* shift left yfract by 11 to keep 1.31 format */ yfract = (Y & 0x000FFFFF) << 11U; /* Read two nearest output values from the index */ y1 = pYData[(rI) + (int32_t)nCols * (cI + 1) ]; y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1]; /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32)); acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32)); /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32)); acc += ((q31_t) ((q63_t) out * (xfract) >> 32)); /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32)); acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ out = ((q31_t) ((q63_t) y2 * (xfract) >> 32)); acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); /* Convert acc to 1.31(q31) format */ return ((q31_t)(acc << 2)); } /** * @brief Q15 bilinear interpolation. * @param[in,out] S points to an instance of the interpolation structure. * @param[in] X interpolation coordinate in 12.20 format. * @param[in] Y interpolation coordinate in 12.20 format. * @return out interpolated value. */ CMSIS_INLINE __STATIC_INLINE q15_t arm_bilinear_interp_q15( arm_bilinear_interp_instance_q15 * S, q31_t X, q31_t Y) { q63_t acc = 0; /* output */ q31_t out; /* Temporary output */ q15_t x1, x2, y1, y2; /* Nearest output values */ q31_t xfract, yfract; /* X, Y fractional parts */ int32_t rI, cI; /* Row and column indices */ q15_t *pYData = S->pData; /* pointer to output table values */ uint32_t nCols = S->numCols; /* num of rows */ /* Input is in 12.20 format */ /* 12 bits for the table index */ /* Index value calculation */ rI = ((X & (q31_t)0xFFF00000) >> 20); /* Input is in 12.20 format */ /* 12 bits for the table index */ /* Index value calculation */ cI = ((Y & (q31_t)0xFFF00000) >> 20); /* Care taken for table outside boundary */ /* Returns zero output when values are outside table boundary */ if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) { return (0); } /* 20 bits for the fractional part */ /* xfract should be in 12.20 format */ xfract = (X & 0x000FFFFF); /* Read two nearest output values from the index */ x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; /* 20 bits for the fractional part */ /* yfract should be in 12.20 format */ yfract = (Y & 0x000FFFFF); /* Read two nearest output values from the index */ y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4U); acc = ((q63_t) out * (0xFFFFF - yfract)); /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4U); acc += ((q63_t) out * (xfract)); /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4U); acc += ((q63_t) out * (yfract)); /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ out = (q31_t) (((q63_t) y2 * (xfract)) >> 4U); acc += ((q63_t) out * (yfract)); /* acc is in 13.51 format and down shift acc by 36 times */ /* Convert out to 1.15 format */ return ((q15_t)(acc >> 36)); } /** * @brief Q7 bilinear interpolation. * @param[in,out] S points to an instance of the interpolation structure. * @param[in] X interpolation coordinate in 12.20 format. * @param[in] Y interpolation coordinate in 12.20 format. * @return out interpolated value. */ CMSIS_INLINE __STATIC_INLINE q7_t arm_bilinear_interp_q7( arm_bilinear_interp_instance_q7 * S, q31_t X, q31_t Y) { q63_t acc = 0; /* output */ q31_t out; /* Temporary output */ q31_t xfract, yfract; /* X, Y fractional parts */ q7_t x1, x2, y1, y2; /* Nearest output values */ int32_t rI, cI; /* Row and column indices */ q7_t *pYData = S->pData; /* pointer to output table values */ uint32_t nCols = S->numCols; /* num of rows */ /* Input is in 12.20 format */ /* 12 bits for the table index */ /* Index value calculation */ rI = ((X & (q31_t)0xFFF00000) >> 20); /* Input is in 12.20 format */ /* 12 bits for the table index */ /* Index value calculation */ cI = ((Y & (q31_t)0xFFF00000) >> 20); /* Care taken for table outside boundary */ /* Returns zero output when values are outside table boundary */ if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) { return (0); } /* 20 bits for the fractional part */ /* xfract should be in 12.20 format */ xfract = (X & (q31_t)0x000FFFFF); /* Read two nearest output values from the index */ x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; /* 20 bits for the fractional part */ /* yfract should be in 12.20 format */ yfract = (Y & (q31_t)0x000FFFFF); /* Read two nearest output values from the index */ y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ out = ((x1 * (0xFFFFF - xfract))); acc = (((q63_t) out * (0xFFFFF - yfract))); /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ out = ((x2 * (0xFFFFF - yfract))); acc += (((q63_t) out * (xfract))); /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ out = ((y1 * (0xFFFFF - xfract))); acc += (((q63_t) out * (yfract))); /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ out = ((y2 * (yfract))); acc += (((q63_t) out * (xfract))); /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ return ((q7_t)(acc >> 40)); } /** * @} end of BilinearInterpolate group */ /* SMMLAR */ #define multAcc_32x32_keep32_R(a, x, y) \ a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32) /* SMMLSR */ #define multSub_32x32_keep32_R(a, x, y) \ a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32) /* SMMULR */ #define mult_32x32_keep32_R(a, x, y) \ a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32) /* SMMLA */ #define multAcc_32x32_keep32(a, x, y) \ a += (q31_t) (((q63_t) x * y) >> 32) /* SMMLS */ #define multSub_32x32_keep32(a, x, y) \ a -= (q31_t) (((q63_t) x * y) >> 32) /* SMMUL */ #define mult_32x32_keep32(a, x, y) \ a = (q31_t) (((q63_t) x * y ) >> 32) #if defined ( __CC_ARM ) /* Enter low optimization region - place directly above function definition */ #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7) #define LOW_OPTIMIZATION_ENTER \ _Pragma ("push") \ _Pragma ("O1") #else #define LOW_OPTIMIZATION_ENTER #endif /* Exit low optimization region - place directly after end of function definition */ #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 ) #define LOW_OPTIMIZATION_EXIT \ _Pragma ("pop") #else #define LOW_OPTIMIZATION_EXIT #endif /* Enter low optimization region - place directly above function definition */ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER /* Exit low optimization region - place directly after end of function definition */ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT #elif defined (__ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) #define LOW_OPTIMIZATION_ENTER #define LOW_OPTIMIZATION_EXIT #define IAR_ONLY_LOW_OPTIMIZATION_ENTER #define IAR_ONLY_LOW_OPTIMIZATION_EXIT #elif defined ( __GNUC__ ) #define LOW_OPTIMIZATION_ENTER \ __attribute__(( optimize("-O1") )) #define LOW_OPTIMIZATION_EXIT #define IAR_ONLY_LOW_OPTIMIZATION_ENTER #define IAR_ONLY_LOW_OPTIMIZATION_EXIT #elif defined ( __ICCARM__ ) /* Enter low optimization region - place directly above function definition */ #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 ) #define LOW_OPTIMIZATION_ENTER \ _Pragma ("optimize=low") #else #define LOW_OPTIMIZATION_ENTER #endif /* Exit low optimization region - place directly after end of function definition */ #define LOW_OPTIMIZATION_EXIT /* Enter low optimization region - place directly above function definition */ #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 ) #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \ _Pragma ("optimize=low") #else #define IAR_ONLY_LOW_OPTIMIZATION_ENTER #endif /* Exit low optimization region - place directly after end of function definition */ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT #elif defined ( __TI_ARM__ ) #define LOW_OPTIMIZATION_ENTER #define LOW_OPTIMIZATION_EXIT #define IAR_ONLY_LOW_OPTIMIZATION_ENTER #define IAR_ONLY_LOW_OPTIMIZATION_EXIT #elif defined ( __CSMC__ ) #define LOW_OPTIMIZATION_ENTER #define LOW_OPTIMIZATION_EXIT #define IAR_ONLY_LOW_OPTIMIZATION_ENTER #define IAR_ONLY_LOW_OPTIMIZATION_EXIT #elif defined ( __TASKING__ ) #define LOW_OPTIMIZATION_ENTER #define LOW_OPTIMIZATION_EXIT #define IAR_ONLY_LOW_OPTIMIZATION_ENTER #define IAR_ONLY_LOW_OPTIMIZATION_EXIT #endif #ifdef __cplusplus } #endif /* Compiler specific diagnostic adjustment */ #if defined ( __CC_ARM ) #elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) #elif defined ( __GNUC__ ) #pragma GCC diagnostic pop #elif defined ( __ICCARM__ ) #elif defined ( __TI_ARM__ ) #elif defined ( __CSMC__ ) #elif defined ( __TASKING__ ) #else #error Unknown compiler #endif #endif /* _ARM_MATH_H */ /** * * End of file. */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/CMSIS/Include/cmsis_armcc.h.
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/**************************************************************************//** * @file cmsis_armcc.h * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file * @version V5.0.4 * @date 10. January 2018 ******************************************************************************/ /* * Copyright (c) 2009-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef __CMSIS_ARMCC_H #define __CMSIS_ARMCC_H #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) #error "Please use Arm Compiler Toolchain V4.0.677 or later!" #endif /* CMSIS compiler control architecture macros */ #if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \ (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) ) #define __ARM_ARCH_6M__ 1 #endif #if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1)) #define __ARM_ARCH_7M__ 1 #endif #if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1)) #define __ARM_ARCH_7EM__ 1 #endif /* __ARM_ARCH_8M_BASE__ not applicable */ /* __ARM_ARCH_8M_MAIN__ not applicable */ /* CMSIS compiler specific defines */ #ifndef __ASM #define __ASM __asm #endif #ifndef __INLINE #define __INLINE __inline #endif #ifndef __STATIC_INLINE #define __STATIC_INLINE static __inline #endif #ifndef __STATIC_FORCEINLINE #define __STATIC_FORCEINLINE static __forceinline #endif #ifndef __NO_RETURN #define __NO_RETURN __declspec(noreturn) #endif #ifndef __USED #define __USED __attribute__((used)) #endif #ifndef __WEAK #define __WEAK __attribute__((weak)) #endif #ifndef __PACKED #define __PACKED __attribute__((packed)) #endif #ifndef __PACKED_STRUCT #define __PACKED_STRUCT __packed struct #endif #ifndef __PACKED_UNION #define __PACKED_UNION __packed union #endif #ifndef __UNALIGNED_UINT32 /* deprecated */ #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) #endif #ifndef __UNALIGNED_UINT16_WRITE #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) #endif #ifndef __UNALIGNED_UINT16_READ #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) #endif #ifndef __UNALIGNED_UINT32_WRITE #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) #endif #ifndef __UNALIGNED_UINT32_READ #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) #endif #ifndef __ALIGNED #define __ALIGNED(x) __attribute__((aligned(x))) #endif #ifndef __RESTRICT #define __RESTRICT __restrict #endif /* ########################### Core Function Access ########################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions @{ */ /** \brief Enable IRQ Interrupts \details Enables IRQ interrupts by clearing the I-bit in the CPSR. Can only be executed in Privileged modes. */ /* intrinsic void __enable_irq(); */ /** \brief Disable IRQ Interrupts \details Disables IRQ interrupts by setting the I-bit in the CPSR. Can only be executed in Privileged modes. */ /* intrinsic void __disable_irq(); */ /** \brief Get Control Register \details Returns the content of the Control Register. \return Control Register value */ __STATIC_INLINE uint32_t __get_CONTROL(void) { register uint32_t __regControl __ASM("control"); return(__regControl); } /** \brief Set Control Register \details Writes the given value to the Control Register. \param [in] control Control Register value to set */ __STATIC_INLINE void __set_CONTROL(uint32_t control) { register uint32_t __regControl __ASM("control"); __regControl = control; } /** \brief Get IPSR Register \details Returns the content of the IPSR Register. \return IPSR Register value */ __STATIC_INLINE uint32_t __get_IPSR(void) { register uint32_t __regIPSR __ASM("ipsr"); return(__regIPSR); } /** \brief Get APSR Register \details Returns the content of the APSR Register. \return APSR Register value */ __STATIC_INLINE uint32_t __get_APSR(void) { register uint32_t __regAPSR __ASM("apsr"); return(__regAPSR); } /** \brief Get xPSR Register \details Returns the content of the xPSR Register. \return xPSR Register value */ __STATIC_INLINE uint32_t __get_xPSR(void) { register uint32_t __regXPSR __ASM("xpsr"); return(__regXPSR); } /** \brief Get Process Stack Pointer \details Returns the current value of the Process Stack Pointer (PSP). \return PSP Register value */ __STATIC_INLINE uint32_t __get_PSP(void) { register uint32_t __regProcessStackPointer __ASM("psp"); return(__regProcessStackPointer); } /** \brief Set Process Stack Pointer \details Assigns the given value to the Process Stack Pointer (PSP). \param [in] topOfProcStack Process Stack Pointer value to set */ __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) { register uint32_t __regProcessStackPointer __ASM("psp"); __regProcessStackPointer = topOfProcStack; } /** \brief Get Main Stack Pointer \details Returns the current value of the Main Stack Pointer (MSP). \return MSP Register value */ __STATIC_INLINE uint32_t __get_MSP(void) { register uint32_t __regMainStackPointer __ASM("msp"); return(__regMainStackPointer); } /** \brief Set Main Stack Pointer \details Assigns the given value to the Main Stack Pointer (MSP). \param [in] topOfMainStack Main Stack Pointer value to set */ __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) { register uint32_t __regMainStackPointer __ASM("msp"); __regMainStackPointer = topOfMainStack; } /** \brief Get Priority Mask \details Returns the current state of the priority mask bit from the Priority Mask Register. \return Priority Mask value */ __STATIC_INLINE uint32_t __get_PRIMASK(void) { register uint32_t __regPriMask __ASM("primask"); return(__regPriMask); } /** \brief Set Priority Mask \details Assigns the given value to the Priority Mask Register. \param [in] priMask Priority Mask */ __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) { register uint32_t __regPriMask __ASM("primask"); __regPriMask = (priMask); } #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) /** \brief Enable FIQ \details Enables FIQ interrupts by clearing the F-bit in the CPSR. Can only be executed in Privileged modes. */ #define __enable_fault_irq __enable_fiq /** \brief Disable FIQ \details Disables FIQ interrupts by setting the F-bit in the CPSR. Can only be executed in Privileged modes. */ #define __disable_fault_irq __disable_fiq /** \brief Get Base Priority \details Returns the current value of the Base Priority register. \return Base Priority register value */ __STATIC_INLINE uint32_t __get_BASEPRI(void) { register uint32_t __regBasePri __ASM("basepri"); return(__regBasePri); } /** \brief Set Base Priority \details Assigns the given value to the Base Priority register. \param [in] basePri Base Priority value to set */ __STATIC_INLINE void __set_BASEPRI(uint32_t basePri) { register uint32_t __regBasePri __ASM("basepri"); __regBasePri = (basePri & 0xFFU); } /** \brief Set Base Priority with condition \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, or the new value increases the BASEPRI priority level. \param [in] basePri Base Priority value to set */ __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) { register uint32_t __regBasePriMax __ASM("basepri_max"); __regBasePriMax = (basePri & 0xFFU); } /** \brief Get Fault Mask \details Returns the current value of the Fault Mask register. \return Fault Mask register value */ __STATIC_INLINE uint32_t __get_FAULTMASK(void) { register uint32_t __regFaultMask __ASM("faultmask"); return(__regFaultMask); } /** \brief Set Fault Mask \details Assigns the given value to the Fault Mask register. \param [in] faultMask Fault Mask value to set */ __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) { register uint32_t __regFaultMask __ASM("faultmask"); __regFaultMask = (faultMask & (uint32_t)1U); } #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ #if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) /** \brief Get FPSCR \details Returns the current value of the Floating Point Status/Control register. \return Floating Point Status/Control register value */ __STATIC_INLINE uint32_t __get_FPSCR(void) { #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) register uint32_t __regfpscr __ASM("fpscr"); return(__regfpscr); #else return(0U); #endif } /** \brief Set FPSCR \details Assigns the given value to the Floating Point Status/Control register. \param [in] fpscr Floating Point Status/Control value to set */ __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) { #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) register uint32_t __regfpscr __ASM("fpscr"); __regfpscr = (fpscr); #else (void)fpscr; #endif } #endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ /*@} end of CMSIS_Core_RegAccFunctions */ /* ########################## Core Instruction Access ######################### */ /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface Access to dedicated instructions @{ */ /** \brief No Operation \details No Operation does nothing. This instruction can be used for code alignment purposes. */ #define __NOP __nop /** \brief Wait For Interrupt \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. */ #define __WFI __wfi /** \brief Wait For Event \details Wait For Event is a hint instruction that permits the processor to enter a low-power state until one of a number of events occurs. */ #define __WFE __wfe /** \brief Send Event \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. */ #define __SEV __sev /** \brief Instruction Synchronization Barrier \details Instruction Synchronization Barrier flushes the pipeline in the processor, so that all instructions following the ISB are fetched from cache or memory, after the instruction has been completed. */ #define __ISB() do {\ __schedule_barrier();\ __isb(0xF);\ __schedule_barrier();\ } while (0U) /** \brief Data Synchronization Barrier \details Acts as a special kind of Data Memory Barrier. It completes when all explicit memory accesses before this instruction complete. */ #define __DSB() do {\ __schedule_barrier();\ __dsb(0xF);\ __schedule_barrier();\ } while (0U) /** \brief Data Memory Barrier \details Ensures the apparent order of the explicit memory operations before and after the instruction, without ensuring their completion. */ #define __DMB() do {\ __schedule_barrier();\ __dmb(0xF);\ __schedule_barrier();\ } while (0U) /** \brief Reverse byte order (32 bit) \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. \param [in] value Value to reverse \return Reversed value */ #define __REV __rev /** \brief Reverse byte order (16 bit) \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. \param [in] value Value to reverse \return Reversed value */ #ifndef __NO_EMBEDDED_ASM __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) { rev16 r0, r0 bx lr } #endif /** \brief Reverse byte order (16 bit) \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. \param [in] value Value to reverse \return Reversed value */ #ifndef __NO_EMBEDDED_ASM __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) { revsh r0, r0 bx lr } #endif /** \brief Rotate Right in unsigned value (32 bit) \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. \param [in] op1 Value to rotate \param [in] op2 Number of Bits to rotate \return Rotated value */ #define __ROR __ror /** \brief Breakpoint \details Causes the processor to enter Debug state. Debug tools can use this to investigate system state when the instruction at a particular address is reached. \param [in] value is ignored by the processor. If required, a debugger can use it to store additional information about the breakpoint. */ #define __BKPT(value) __breakpoint(value) /** \brief Reverse bit order of value \details Reverses the bit order of the given value. \param [in] value Value to reverse \return Reversed value */ #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) #define __RBIT __rbit #else __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) { uint32_t result; uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ result = value; /* r will be reversed bits of v; first get LSB of v */ for (value >>= 1U; value != 0U; value >>= 1U) { result <<= 1U; result |= value & 1U; s--; } result <<= s; /* shift when v's highest bits are zero */ return result; } #endif /** \brief Count leading zeros \details Counts the number of leading zeros of a data value. \param [in] value Value to count the leading zeros \return number of leading zeros in value */ #define __CLZ __clz #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) /** \brief LDR Exclusive (8 bit) \details Executes a exclusive LDR instruction for 8 bit value. \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) #else #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") #endif /** \brief LDR Exclusive (16 bit) \details Executes a exclusive LDR instruction for 16 bit values. \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) #else #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") #endif /** \brief LDR Exclusive (32 bit) \details Executes a exclusive LDR instruction for 32 bit values. \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) #else #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") #endif /** \brief STR Exclusive (8 bit) \details Executes a exclusive STR instruction for 8 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) #define __STREXB(value, ptr) __strex(value, ptr) #else #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") #endif /** \brief STR Exclusive (16 bit) \details Executes a exclusive STR instruction for 16 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) #define __STREXH(value, ptr) __strex(value, ptr) #else #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") #endif /** \brief STR Exclusive (32 bit) \details Executes a exclusive STR instruction for 32 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) #define __STREXW(value, ptr) __strex(value, ptr) #else #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") #endif /** \brief Remove the exclusive lock \details Removes the exclusive lock which is created by LDREX. */ #define __CLREX __clrex /** \brief Signed Saturate \details Saturates a signed value. \param [in] value Value to be saturated \param [in] sat Bit position to saturate to (1..32) \return Saturated value */ #define __SSAT __ssat /** \brief Unsigned Saturate \details Saturates an unsigned value. \param [in] value Value to be saturated \param [in] sat Bit position to saturate to (0..31) \return Saturated value */ #define __USAT __usat /** \brief Rotate Right with Extend (32 bit) \details Moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring. \param [in] value Value to rotate \return Rotated value */ #ifndef __NO_EMBEDDED_ASM __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) { rrx r0, r0 bx lr } #endif /** \brief LDRT Unprivileged (8 bit) \details Executes a Unprivileged LDRT instruction for 8 bit value. \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ #define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) /** \brief LDRT Unprivileged (16 bit) \details Executes a Unprivileged LDRT instruction for 16 bit values. \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ #define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) /** \brief LDRT Unprivileged (32 bit) \details Executes a Unprivileged LDRT instruction for 32 bit values. \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ #define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) /** \brief STRT Unprivileged (8 bit) \details Executes a Unprivileged STRT instruction for 8 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ #define __STRBT(value, ptr) __strt(value, ptr) /** \brief STRT Unprivileged (16 bit) \details Executes a Unprivileged STRT instruction for 16 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ #define __STRHT(value, ptr) __strt(value, ptr) /** \brief STRT Unprivileged (32 bit) \details Executes a Unprivileged STRT instruction for 32 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ #define __STRT(value, ptr) __strt(value, ptr) #else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ /** \brief Signed Saturate \details Saturates a signed value. \param [in] value Value to be saturated \param [in] sat Bit position to saturate to (1..32) \return Saturated value */ __attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) { if ((sat >= 1U) && (sat <= 32U)) { const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); const int32_t min = -1 - max ; if (val > max) { return max; } else if (val < min) { return min; } } return val; } /** \brief Unsigned Saturate \details Saturates an unsigned value. \param [in] value Value to be saturated \param [in] sat Bit position to saturate to (0..31) \return Saturated value */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) { if (sat <= 31U) { const uint32_t max = ((1U << sat) - 1U); if (val > (int32_t)max) { return max; } else if (val < 0) { return 0U; } } return (uint32_t)val; } #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ /*@}*/ /* end of group CMSIS_Core_InstructionInterface */ /* ################### Compiler specific Intrinsics ########################### */ /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics Access to dedicated SIMD instructions @{ */ #if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) #define __SADD8 __sadd8 #define __QADD8 __qadd8 #define __SHADD8 __shadd8 #define __UADD8 __uadd8 #define __UQADD8 __uqadd8 #define __UHADD8 __uhadd8 #define __SSUB8 __ssub8 #define __QSUB8 __qsub8 #define __SHSUB8 __shsub8 #define __USUB8 __usub8 #define __UQSUB8 __uqsub8 #define __UHSUB8 __uhsub8 #define __SADD16 __sadd16 #define __QADD16 __qadd16 #define __SHADD16 __shadd16 #define __UADD16 __uadd16 #define __UQADD16 __uqadd16 #define __UHADD16 __uhadd16 #define __SSUB16 __ssub16 #define __QSUB16 __qsub16 #define __SHSUB16 __shsub16 #define __USUB16 __usub16 #define __UQSUB16 __uqsub16 #define __UHSUB16 __uhsub16 #define __SASX __sasx #define __QASX __qasx #define __SHASX __shasx #define __UASX __uasx #define __UQASX __uqasx #define __UHASX __uhasx #define __SSAX __ssax #define __QSAX __qsax #define __SHSAX __shsax #define __USAX __usax #define __UQSAX __uqsax #define __UHSAX __uhsax #define __USAD8 __usad8 #define __USADA8 __usada8 #define __SSAT16 __ssat16 #define __USAT16 __usat16 #define __UXTB16 __uxtb16 #define __UXTAB16 __uxtab16 #define __SXTB16 __sxtb16 #define __SXTAB16 __sxtab16 #define __SMUAD __smuad #define __SMUADX __smuadx #define __SMLAD __smlad #define __SMLADX __smladx #define __SMLALD __smlald #define __SMLALDX __smlaldx #define __SMUSD __smusd #define __SMUSDX __smusdx #define __SMLSD __smlsd #define __SMLSDX __smlsdx #define __SMLSLD __smlsld #define __SMLSLDX __smlsldx #define __SEL __sel #define __QADD __qadd #define __QSUB __qsub #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) #define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ ((int64_t)(ARG3) << 32U) ) >> 32U)) #endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ /*@} end of group CMSIS_SIMD_intrinsics */ #endif /* __CMSIS_ARMCC_H */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/CMSIS/Include/cmsis_armclang.h.
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/**************************************************************************//** * @file cmsis_armclang.h * @brief CMSIS compiler armclang (Arm Compiler 6) header file * @version V5.0.4 * @date 10. January 2018 ******************************************************************************/ /* * Copyright (c) 2009-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ /*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ #ifndef __CMSIS_ARMCLANG_H #define __CMSIS_ARMCLANG_H #pragma clang system_header /* treat file as system include file */ #ifndef __ARM_COMPAT_H #include <arm_compat.h> /* Compatibility header for Arm Compiler 5 intrinsics */ #endif /* CMSIS compiler specific defines */ #ifndef __ASM #define __ASM __asm #endif #ifndef __INLINE #define __INLINE __inline #endif #ifndef __STATIC_INLINE #define __STATIC_INLINE static __inline #endif #ifndef __STATIC_FORCEINLINE #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline #endif #ifndef __NO_RETURN #define __NO_RETURN __attribute__((__noreturn__)) #endif #ifndef __USED #define __USED __attribute__((used)) #endif #ifndef __WEAK #define __WEAK __attribute__((weak)) #endif #ifndef __PACKED #define __PACKED __attribute__((packed, aligned(1))) #endif #ifndef __PACKED_STRUCT #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) #endif #ifndef __PACKED_UNION #define __PACKED_UNION union __attribute__((packed, aligned(1))) #endif #ifndef __UNALIGNED_UINT32 /* deprecated */ #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wpacked" /*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ struct __attribute__((packed)) T_UINT32 { uint32_t v; }; #pragma clang diagnostic pop #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) #endif #ifndef __UNALIGNED_UINT16_WRITE #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wpacked" /*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; #pragma clang diagnostic pop #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) #endif #ifndef __UNALIGNED_UINT16_READ #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wpacked" /*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; #pragma clang diagnostic pop #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) #endif #ifndef __UNALIGNED_UINT32_WRITE #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wpacked" /*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; #pragma clang diagnostic pop #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) #endif #ifndef __UNALIGNED_UINT32_READ #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wpacked" /*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; #pragma clang diagnostic pop #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) #endif #ifndef __ALIGNED #define __ALIGNED(x) __attribute__((aligned(x))) #endif #ifndef __RESTRICT #define __RESTRICT __restrict #endif /* ########################### Core Function Access ########################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions @{ */ /** \brief Enable IRQ Interrupts \details Enables IRQ interrupts by clearing the I-bit in the CPSR. Can only be executed in Privileged modes. */ /* intrinsic void __enable_irq(); see arm_compat.h */ /** \brief Disable IRQ Interrupts \details Disables IRQ interrupts by setting the I-bit in the CPSR. Can only be executed in Privileged modes. */ /* intrinsic void __disable_irq(); see arm_compat.h */ /** \brief Get Control Register \details Returns the content of the Control Register. \return Control Register value */ __STATIC_FORCEINLINE uint32_t __get_CONTROL(void) { uint32_t result; __ASM volatile ("MRS %0, control" : "=r" (result) ); return(result); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Control Register (non-secure) \details Returns the content of the non-secure Control Register when in secure mode. \return non-secure Control Register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) { uint32_t result; __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); return(result); } #endif /** \brief Set Control Register \details Writes the given value to the Control Register. \param [in] control Control Register value to set */ __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) { __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Control Register (non-secure) \details Writes the given value to the non-secure Control Register when in secure state. \param [in] control Control Register value to set */ __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) { __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); } #endif /** \brief Get IPSR Register \details Returns the content of the IPSR Register. \return IPSR Register value */ __STATIC_FORCEINLINE uint32_t __get_IPSR(void) { uint32_t result; __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); return(result); } /** \brief Get APSR Register \details Returns the content of the APSR Register. \return APSR Register value */ __STATIC_FORCEINLINE uint32_t __get_APSR(void) { uint32_t result; __ASM volatile ("MRS %0, apsr" : "=r" (result) ); return(result); } /** \brief Get xPSR Register \details Returns the content of the xPSR Register. \return xPSR Register value */ __STATIC_FORCEINLINE uint32_t __get_xPSR(void) { uint32_t result; __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); return(result); } /** \brief Get Process Stack Pointer \details Returns the current value of the Process Stack Pointer (PSP). \return PSP Register value */ __STATIC_FORCEINLINE uint32_t __get_PSP(void) { register uint32_t result; __ASM volatile ("MRS %0, psp" : "=r" (result) ); return(result); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Process Stack Pointer (non-secure) \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. \return PSP Register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) { register uint32_t result; __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); return(result); } #endif /** \brief Set Process Stack Pointer \details Assigns the given value to the Process Stack Pointer (PSP). \param [in] topOfProcStack Process Stack Pointer value to set */ __STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) { __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Process Stack Pointer (non-secure) \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. \param [in] topOfProcStack Process Stack Pointer value to set */ __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) { __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); } #endif /** \brief Get Main Stack Pointer \details Returns the current value of the Main Stack Pointer (MSP). \return MSP Register value */ __STATIC_FORCEINLINE uint32_t __get_MSP(void) { register uint32_t result; __ASM volatile ("MRS %0, msp" : "=r" (result) ); return(result); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Main Stack Pointer (non-secure) \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. \return MSP Register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) { register uint32_t result; __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); return(result); } #endif /** \brief Set Main Stack Pointer \details Assigns the given value to the Main Stack Pointer (MSP). \param [in] topOfMainStack Main Stack Pointer value to set */ __STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) { __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Main Stack Pointer (non-secure) \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. \param [in] topOfMainStack Main Stack Pointer value to set */ __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) { __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); } #endif #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Stack Pointer (non-secure) \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. \return SP Register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) { register uint32_t result; __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); return(result); } /** \brief Set Stack Pointer (non-secure) \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. \param [in] topOfStack Stack Pointer value to set */ __STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) { __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); } #endif /** \brief Get Priority Mask \details Returns the current state of the priority mask bit from the Priority Mask Register. \return Priority Mask value */ __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) { uint32_t result; __ASM volatile ("MRS %0, primask" : "=r" (result) ); return(result); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Priority Mask (non-secure) \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. \return Priority Mask value */ __STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) { uint32_t result; __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); return(result); } #endif /** \brief Set Priority Mask \details Assigns the given value to the Priority Mask Register. \param [in] priMask Priority Mask */ __STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) { __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Priority Mask (non-secure) \details Assigns the given value to the non-secure Priority Mask Register when in secure state. \param [in] priMask Priority Mask */ __STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) { __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); } #endif #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) /** \brief Enable FIQ \details Enables FIQ interrupts by clearing the F-bit in the CPSR. Can only be executed in Privileged modes. */ #define __enable_fault_irq __enable_fiq /* see arm_compat.h */ /** \brief Disable FIQ \details Disables FIQ interrupts by setting the F-bit in the CPSR. Can only be executed in Privileged modes. */ #define __disable_fault_irq __disable_fiq /* see arm_compat.h */ /** \brief Get Base Priority \details Returns the current value of the Base Priority register. \return Base Priority register value */ __STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) { uint32_t result; __ASM volatile ("MRS %0, basepri" : "=r" (result) ); return(result); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Base Priority (non-secure) \details Returns the current value of the non-secure Base Priority register when in secure state. \return Base Priority register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) { uint32_t result; __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); return(result); } #endif /** \brief Set Base Priority \details Assigns the given value to the Base Priority register. \param [in] basePri Base Priority value to set */ __STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) { __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Base Priority (non-secure) \details Assigns the given value to the non-secure Base Priority register when in secure state. \param [in] basePri Base Priority value to set */ __STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) { __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); } #endif /** \brief Set Base Priority with condition \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, or the new value increases the BASEPRI priority level. \param [in] basePri Base Priority value to set */ __STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) { __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); } /** \brief Get Fault Mask \details Returns the current value of the Fault Mask register. \return Fault Mask register value */ __STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) { uint32_t result; __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); return(result); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Fault Mask (non-secure) \details Returns the current value of the non-secure Fault Mask register when in secure state. \return Fault Mask register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) { uint32_t result; __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); return(result); } #endif /** \brief Set Fault Mask \details Assigns the given value to the Fault Mask register. \param [in] faultMask Fault Mask value to set */ __STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) { __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Fault Mask (non-secure) \details Assigns the given value to the non-secure Fault Mask register when in secure state. \param [in] faultMask Fault Mask value to set */ __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) { __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); } #endif #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) /** \brief Get Process Stack Pointer Limit Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence zero is returned always in non-secure mode. \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). \return PSPLIM Register value */ __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure PSPLIM is RAZ/WI return 0U; #else register uint32_t result; __ASM volatile ("MRS %0, psplim" : "=r" (result) ); return result; #endif } #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Process Stack Pointer Limit (non-secure) Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence zero is returned always in non-secure mode. \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. \return PSPLIM Register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) // without main extensions, the non-secure PSPLIM is RAZ/WI return 0U; #else register uint32_t result; __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); return result; #endif } #endif /** \brief Set Process Stack Pointer Limit Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence the write is silently ignored in non-secure mode. \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set */ __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure PSPLIM is RAZ/WI (void)ProcStackPtrLimit; #else __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); #endif } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Process Stack Pointer (non-secure) Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence the write is silently ignored in non-secure mode. \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set */ __STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) // without main extensions, the non-secure PSPLIM is RAZ/WI (void)ProcStackPtrLimit; #else __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); #endif } #endif /** \brief Get Main Stack Pointer Limit Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence zero is returned always. \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). \return MSPLIM Register value */ __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure MSPLIM is RAZ/WI return 0U; #else register uint32_t result; __ASM volatile ("MRS %0, msplim" : "=r" (result) ); return result; #endif } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Main Stack Pointer Limit (non-secure) Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence zero is returned always. \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. \return MSPLIM Register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) // without main extensions, the non-secure MSPLIM is RAZ/WI return 0U; #else register uint32_t result; __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); return result; #endif } #endif /** \brief Set Main Stack Pointer Limit Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence the write is silently ignored. \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set */ __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure MSPLIM is RAZ/WI (void)MainStackPtrLimit; #else __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); #endif } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Main Stack Pointer Limit (non-secure) Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence the write is silently ignored. \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. \param [in] MainStackPtrLimit Main Stack Pointer value to set */ __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) // without main extensions, the non-secure MSPLIM is RAZ/WI (void)MainStackPtrLimit; #else __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); #endif } #endif #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ #if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) /** \brief Get FPSCR \details Returns the current value of the Floating Point Status/Control register. \return Floating Point Status/Control register value */ #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) #define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr #else #define __get_FPSCR() ((uint32_t)0U) #endif /** \brief Set FPSCR \details Assigns the given value to the Floating Point Status/Control register. \param [in] fpscr Floating Point Status/Control value to set */ #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) #define __set_FPSCR __builtin_arm_set_fpscr #else #define __set_FPSCR(x) ((void)(x)) #endif #endif /* ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ /*@} end of CMSIS_Core_RegAccFunctions */ /* ########################## Core Instruction Access ######################### */ /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface Access to dedicated instructions @{ */ /* Define macros for porting to both thumb1 and thumb2. * For thumb1, use low register (r0-r7), specified by constraint "l" * Otherwise, use general registers, specified by constraint "r" */ #if defined (__thumb__) && !defined (__thumb2__) #define __CMSIS_GCC_OUT_REG(r) "=l" (r) #define __CMSIS_GCC_USE_REG(r) "l" (r) #else #define __CMSIS_GCC_OUT_REG(r) "=r" (r) #define __CMSIS_GCC_USE_REG(r) "r" (r) #endif /** \brief No Operation \details No Operation does nothing. This instruction can be used for code alignment purposes. */ #define __NOP __builtin_arm_nop /** \brief Wait For Interrupt \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. */ #define __WFI __builtin_arm_wfi /** \brief Wait For Event \details Wait For Event is a hint instruction that permits the processor to enter a low-power state until one of a number of events occurs. */ #define __WFE __builtin_arm_wfe /** \brief Send Event \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. */ #define __SEV __builtin_arm_sev /** \brief Instruction Synchronization Barrier \details Instruction Synchronization Barrier flushes the pipeline in the processor, so that all instructions following the ISB are fetched from cache or memory, after the instruction has been completed. */ #define __ISB() __builtin_arm_isb(0xF); /** \brief Data Synchronization Barrier \details Acts as a special kind of Data Memory Barrier. It completes when all explicit memory accesses before this instruction complete. */ #define __DSB() __builtin_arm_dsb(0xF); /** \brief Data Memory Barrier \details Ensures the apparent order of the explicit memory operations before and after the instruction, without ensuring their completion. */ #define __DMB() __builtin_arm_dmb(0xF); /** \brief Reverse byte order (32 bit) \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. \param [in] value Value to reverse \return Reversed value */ #define __REV(value) __builtin_bswap32(value) /** \brief Reverse byte order (16 bit) \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. \param [in] value Value to reverse \return Reversed value */ #define __REV16(value) __ROR(__REV(value), 16) /** \brief Reverse byte order (16 bit) \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. \param [in] value Value to reverse \return Reversed value */ #define __REVSH(value) (int16_t)__builtin_bswap16(value) /** \brief Rotate Right in unsigned value (32 bit) \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. \param [in] op1 Value to rotate \param [in] op2 Number of Bits to rotate \return Rotated value */ __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) { op2 %= 32U; if (op2 == 0U) { return op1; } return (op1 >> op2) | (op1 << (32U - op2)); } /** \brief Breakpoint \details Causes the processor to enter Debug state. Debug tools can use this to investigate system state when the instruction at a particular address is reached. \param [in] value is ignored by the processor. If required, a debugger can use it to store additional information about the breakpoint. */ #define __BKPT(value) __ASM volatile ("bkpt "#value) /** \brief Reverse bit order of value \details Reverses the bit order of the given value. \param [in] value Value to reverse \return Reversed value */ #define __RBIT __builtin_arm_rbit /** \brief Count leading zeros \details Counts the number of leading zeros of a data value. \param [in] value Value to count the leading zeros \return number of leading zeros in value */ #define __CLZ (uint8_t)__builtin_clz #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) /** \brief LDR Exclusive (8 bit) \details Executes a exclusive LDR instruction for 8 bit value. \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ #define __LDREXB (uint8_t)__builtin_arm_ldrex /** \brief LDR Exclusive (16 bit) \details Executes a exclusive LDR instruction for 16 bit values. \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ #define __LDREXH (uint16_t)__builtin_arm_ldrex /** \brief LDR Exclusive (32 bit) \details Executes a exclusive LDR instruction for 32 bit values. \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ #define __LDREXW (uint32_t)__builtin_arm_ldrex /** \brief STR Exclusive (8 bit) \details Executes a exclusive STR instruction for 8 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ #define __STREXB (uint32_t)__builtin_arm_strex /** \brief STR Exclusive (16 bit) \details Executes a exclusive STR instruction for 16 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ #define __STREXH (uint32_t)__builtin_arm_strex /** \brief STR Exclusive (32 bit) \details Executes a exclusive STR instruction for 32 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ #define __STREXW (uint32_t)__builtin_arm_strex /** \brief Remove the exclusive lock \details Removes the exclusive lock which is created by LDREX. */ #define __CLREX __builtin_arm_clrex #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) /** \brief Signed Saturate \details Saturates a signed value. \param [in] value Value to be saturated \param [in] sat Bit position to saturate to (1..32) \return Saturated value */ #define __SSAT __builtin_arm_ssat /** \brief Unsigned Saturate \details Saturates an unsigned value. \param [in] value Value to be saturated \param [in] sat Bit position to saturate to (0..31) \return Saturated value */ #define __USAT __builtin_arm_usat /** \brief Rotate Right with Extend (32 bit) \details Moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring. \param [in] value Value to rotate \return Rotated value */ __STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) { uint32_t result; __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); return(result); } /** \brief LDRT Unprivileged (8 bit) \details Executes a Unprivileged LDRT instruction for 8 bit value. \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ __STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) { uint32_t result; __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); return ((uint8_t) result); /* Add explicit type cast here */ } /** \brief LDRT Unprivileged (16 bit) \details Executes a Unprivileged LDRT instruction for 16 bit values. \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ __STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) { uint32_t result; __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); return ((uint16_t) result); /* Add explicit type cast here */ } /** \brief LDRT Unprivileged (32 bit) \details Executes a Unprivileged LDRT instruction for 32 bit values. \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ __STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) { uint32_t result; __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); return(result); } /** \brief STRT Unprivileged (8 bit) \details Executes a Unprivileged STRT instruction for 8 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) { __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); } /** \brief STRT Unprivileged (16 bit) \details Executes a Unprivileged STRT instruction for 16 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) { __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); } /** \brief STRT Unprivileged (32 bit) \details Executes a Unprivileged STRT instruction for 32 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) { __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); } #else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ /** \brief Signed Saturate \details Saturates a signed value. \param [in] value Value to be saturated \param [in] sat Bit position to saturate to (1..32) \return Saturated value */ __STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) { if ((sat >= 1U) && (sat <= 32U)) { const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); const int32_t min = -1 - max ; if (val > max) { return max; } else if (val < min) { return min; } } return val; } /** \brief Unsigned Saturate \details Saturates an unsigned value. \param [in] value Value to be saturated \param [in] sat Bit position to saturate to (0..31) \return Saturated value */ __STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) { if (sat <= 31U) { const uint32_t max = ((1U << sat) - 1U); if (val > (int32_t)max) { return max; } else if (val < 0) { return 0U; } } return (uint32_t)val; } #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) /** \brief Load-Acquire (8 bit) \details Executes a LDAB instruction for 8 bit value. \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ __STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) { uint32_t result; __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); return ((uint8_t) result); } /** \brief Load-Acquire (16 bit) \details Executes a LDAH instruction for 16 bit values. \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ __STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) { uint32_t result; __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); return ((uint16_t) result); } /** \brief Load-Acquire (32 bit) \details Executes a LDA instruction for 32 bit values. \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ __STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) { uint32_t result; __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); return(result); } /** \brief Store-Release (8 bit) \details Executes a STLB instruction for 8 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) { __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); } /** \brief Store-Release (16 bit) \details Executes a STLH instruction for 16 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) { __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); } /** \brief Store-Release (32 bit) \details Executes a STL instruction for 32 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) { __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); } /** \brief Load-Acquire Exclusive (8 bit) \details Executes a LDAB exclusive instruction for 8 bit value. \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ #define __LDAEXB (uint8_t)__builtin_arm_ldaex /** \brief Load-Acquire Exclusive (16 bit) \details Executes a LDAH exclusive instruction for 16 bit values. \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ #define __LDAEXH (uint16_t)__builtin_arm_ldaex /** \brief Load-Acquire Exclusive (32 bit) \details Executes a LDA exclusive instruction for 32 bit values. \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ #define __LDAEX (uint32_t)__builtin_arm_ldaex /** \brief Store-Release Exclusive (8 bit) \details Executes a STLB exclusive instruction for 8 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ #define __STLEXB (uint32_t)__builtin_arm_stlex /** \brief Store-Release Exclusive (16 bit) \details Executes a STLH exclusive instruction for 16 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ #define __STLEXH (uint32_t)__builtin_arm_stlex /** \brief Store-Release Exclusive (32 bit) \details Executes a STL exclusive instruction for 32 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ #define __STLEX (uint32_t)__builtin_arm_stlex #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ /*@}*/ /* end of group CMSIS_Core_InstructionInterface */ /* ################### Compiler specific Intrinsics ########################### */ /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics Access to dedicated SIMD instructions @{ */ #if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) __STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) { uint32_t result; __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); return(result); } #define __SSAT16(ARG1,ARG2) \ ({ \ int32_t __RES, __ARG1 = (ARG1); \ __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ __RES; \ }) #define __USAT16(ARG1,ARG2) \ ({ \ uint32_t __RES, __ARG1 = (ARG1); \ __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ __RES; \ }) __STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) { uint32_t result; __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); return(result); } __STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) { uint32_t result; __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); return(result); } __STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) { uint32_t result; __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); return(result); } __STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) { uint32_t result; __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); return(result); } __STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) { union llreg_u{ uint32_t w32[2]; uint64_t w64; } llr; llr.w64 = acc; #ifndef __ARMEB__ /* Little endian */ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); #else /* Big endian */ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); #endif return(llr.w64); } __STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) { union llreg_u{ uint32_t w32[2]; uint64_t w64; } llr; llr.w64 = acc; #ifndef __ARMEB__ /* Little endian */ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); #else /* Big endian */ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); #endif return(llr.w64); } __STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) { uint32_t result; __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); return(result); } __STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) { uint32_t result; __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); return(result); } __STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) { union llreg_u{ uint32_t w32[2]; uint64_t w64; } llr; llr.w64 = acc; #ifndef __ARMEB__ /* Little endian */ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); #else /* Big endian */ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); #endif return(llr.w64); } __STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) { union llreg_u{ uint32_t w32[2]; uint64_t w64; } llr; llr.w64 = acc; #ifndef __ARMEB__ /* Little endian */ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); #else /* Big endian */ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); #endif return(llr.w64); } __STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) { int32_t result; __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) { int32_t result; __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } #if 0 #define __PKHBT(ARG1,ARG2,ARG3) \ ({ \ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ __RES; \ }) #define __PKHTB(ARG1,ARG2,ARG3) \ ({ \ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ if (ARG3 == 0) \ __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ else \ __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ __RES; \ }) #endif #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) __STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) { int32_t result; __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); return(result); } #endif /* (__ARM_FEATURE_DSP == 1) */ /*@} end of group CMSIS_SIMD_intrinsics */ #endif /* __CMSIS_ARMCLANG_H */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/CMSIS/Include/cmsis_compiler.h.
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/**************************************************************************//** * @file cmsis_compiler.h * @brief CMSIS compiler generic header file * @version V5.0.4 * @date 10. January 2018 ******************************************************************************/ /* * Copyright (c) 2009-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef __CMSIS_COMPILER_H #define __CMSIS_COMPILER_H #include <stdint.h> /* * Arm Compiler 4/5 */ #if defined ( __CC_ARM ) #include "cmsis_armcc.h" /* * Arm Compiler 6 (armclang) */ #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #include "cmsis_armclang.h" /* * GNU Compiler */ #elif defined ( __GNUC__ ) #include "cmsis_gcc.h" /* * IAR Compiler */ #elif defined ( __ICCARM__ ) #include <cmsis_iccarm.h> /* * TI Arm Compiler */ #elif defined ( __TI_ARM__ ) #include <cmsis_ccs.h> #ifndef __ASM #define __ASM __asm #endif #ifndef __INLINE #define __INLINE inline #endif #ifndef __STATIC_INLINE #define __STATIC_INLINE static inline #endif #ifndef __STATIC_FORCEINLINE #define __STATIC_FORCEINLINE __STATIC_INLINE #endif #ifndef __NO_RETURN #define __NO_RETURN __attribute__((noreturn)) #endif #ifndef __USED #define __USED __attribute__((used)) #endif #ifndef __WEAK #define __WEAK __attribute__((weak)) #endif #ifndef __PACKED #define __PACKED __attribute__((packed)) #endif #ifndef __PACKED_STRUCT #define __PACKED_STRUCT struct __attribute__((packed)) #endif #ifndef __PACKED_UNION #define __PACKED_UNION union __attribute__((packed)) #endif #ifndef __UNALIGNED_UINT32 /* deprecated */ struct __attribute__((packed)) T_UINT32 { uint32_t v; }; #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) #endif #ifndef __UNALIGNED_UINT16_WRITE __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) #endif #ifndef __UNALIGNED_UINT16_READ __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) #endif #ifndef __UNALIGNED_UINT32_WRITE __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) #endif #ifndef __UNALIGNED_UINT32_READ __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) #endif #ifndef __ALIGNED #define __ALIGNED(x) __attribute__((aligned(x))) #endif #ifndef __RESTRICT #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. #define __RESTRICT #endif /* * TASKING Compiler */ #elif defined ( __TASKING__ ) /* * The CMSIS functions have been implemented as intrinsics in the compiler. * Please use "carm -?i" to get an up to date list of all intrinsics, * Including the CMSIS ones. */ #ifndef __ASM #define __ASM __asm #endif #ifndef __INLINE #define __INLINE inline #endif #ifndef __STATIC_INLINE #define __STATIC_INLINE static inline #endif #ifndef __STATIC_FORCEINLINE #define __STATIC_FORCEINLINE __STATIC_INLINE #endif #ifndef __NO_RETURN #define __NO_RETURN __attribute__((noreturn)) #endif #ifndef __USED #define __USED __attribute__((used)) #endif #ifndef __WEAK #define __WEAK __attribute__((weak)) #endif #ifndef __PACKED #define __PACKED __packed__ #endif #ifndef __PACKED_STRUCT #define __PACKED_STRUCT struct __packed__ #endif #ifndef __PACKED_UNION #define __PACKED_UNION union __packed__ #endif #ifndef __UNALIGNED_UINT32 /* deprecated */ struct __packed__ T_UINT32 { uint32_t v; }; #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) #endif #ifndef __UNALIGNED_UINT16_WRITE __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) #endif #ifndef __UNALIGNED_UINT16_READ __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) #endif #ifndef __UNALIGNED_UINT32_WRITE __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) #endif #ifndef __UNALIGNED_UINT32_READ __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) #endif #ifndef __ALIGNED #define __ALIGNED(x) __align(x) #endif #ifndef __RESTRICT #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. #define __RESTRICT #endif /* * COSMIC Compiler */ #elif defined ( __CSMC__ ) #include <cmsis_csm.h> #ifndef __ASM #define __ASM _asm #endif #ifndef __INLINE #define __INLINE inline #endif #ifndef __STATIC_INLINE #define __STATIC_INLINE static inline #endif #ifndef __STATIC_FORCEINLINE #define __STATIC_FORCEINLINE __STATIC_INLINE #endif #ifndef __NO_RETURN // NO RETURN is automatically detected hence no warning here #define __NO_RETURN #endif #ifndef __USED #warning No compiler specific solution for __USED. __USED is ignored. #define __USED #endif #ifndef __WEAK #define __WEAK __weak #endif #ifndef __PACKED #define __PACKED @packed #endif #ifndef __PACKED_STRUCT #define __PACKED_STRUCT @packed struct #endif #ifndef __PACKED_UNION #define __PACKED_UNION @packed union #endif #ifndef __UNALIGNED_UINT32 /* deprecated */ @packed struct T_UINT32 { uint32_t v; }; #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) #endif #ifndef __UNALIGNED_UINT16_WRITE __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) #endif #ifndef __UNALIGNED_UINT16_READ __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) #endif #ifndef __UNALIGNED_UINT32_WRITE __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) #endif #ifndef __UNALIGNED_UINT32_READ __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) #endif #ifndef __ALIGNED #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. #define __ALIGNED(x) #endif #ifndef __RESTRICT #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. #define __RESTRICT #endif #else #error Unknown compiler. #endif #endif /* __CMSIS_COMPILER_H */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/CMSIS/Include/cmsis_gcc.h.
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/**************************************************************************//** * @file cmsis_gcc.h * @brief CMSIS compiler GCC header file * @version V5.0.3 * @date 16. January 2018 ******************************************************************************/ /* * Copyright (c) 2009-2017 ARM Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef __CMSIS_GCC_H #define __CMSIS_GCC_H /* ignore some GCC warnings */ #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wsign-conversion" #pragma GCC diagnostic ignored "-Wconversion" #pragma GCC diagnostic ignored "-Wunused-parameter" /* Fallback for __has_builtin */ #ifndef __has_builtin #define __has_builtin(x) (0) #endif /* CMSIS compiler specific defines */ #ifndef __ASM #define __ASM __asm #endif #ifndef __INLINE #define __INLINE inline #endif #ifndef __STATIC_INLINE #define __STATIC_INLINE static inline #endif #ifndef __STATIC_FORCEINLINE #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline #endif #ifndef __NO_RETURN #define __NO_RETURN __attribute__((__noreturn__)) #endif #ifndef __USED #define __USED __attribute__((used)) #endif #ifndef __WEAK #define __WEAK __attribute__((weak)) #endif #ifndef __PACKED #define __PACKED __attribute__((packed, aligned(1))) #endif #ifndef __PACKED_STRUCT #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) #endif #ifndef __PACKED_UNION #define __PACKED_UNION union __attribute__((packed, aligned(1))) #endif #ifndef __UNALIGNED_UINT32 /* deprecated */ #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wpacked" #pragma GCC diagnostic ignored "-Wattributes" struct __attribute__((packed)) T_UINT32 { uint32_t v; }; #pragma GCC diagnostic pop #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) #endif #ifndef __UNALIGNED_UINT16_WRITE #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wpacked" #pragma GCC diagnostic ignored "-Wattributes" __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; #pragma GCC diagnostic pop #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) #endif #ifndef __UNALIGNED_UINT16_READ #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wpacked" #pragma GCC diagnostic ignored "-Wattributes" __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; #pragma GCC diagnostic pop #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) #endif #ifndef __UNALIGNED_UINT32_WRITE #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wpacked" #pragma GCC diagnostic ignored "-Wattributes" __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; #pragma GCC diagnostic pop #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) #endif #ifndef __UNALIGNED_UINT32_READ #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wpacked" #pragma GCC diagnostic ignored "-Wattributes" __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; #pragma GCC diagnostic pop #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) #endif #ifndef __ALIGNED #define __ALIGNED(x) __attribute__((aligned(x))) #endif #ifndef __RESTRICT #define __RESTRICT __restrict #endif /* ########################### Core Function Access ########################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions @{ */ /** \brief Enable IRQ Interrupts \details Enables IRQ interrupts by clearing the I-bit in the CPSR. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __enable_irq(void) { __ASM volatile ("cpsie i" : : : "memory"); } /** \brief Disable IRQ Interrupts \details Disables IRQ interrupts by setting the I-bit in the CPSR. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __disable_irq(void) { __ASM volatile ("cpsid i" : : : "memory"); } /** \brief Get Control Register \details Returns the content of the Control Register. \return Control Register value */ __STATIC_FORCEINLINE uint32_t __get_CONTROL(void) { uint32_t result; __ASM volatile ("MRS %0, control" : "=r" (result) ); return(result); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Control Register (non-secure) \details Returns the content of the non-secure Control Register when in secure mode. \return non-secure Control Register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) { uint32_t result; __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); return(result); } #endif /** \brief Set Control Register \details Writes the given value to the Control Register. \param [in] control Control Register value to set */ __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) { __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Control Register (non-secure) \details Writes the given value to the non-secure Control Register when in secure state. \param [in] control Control Register value to set */ __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) { __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); } #endif /** \brief Get IPSR Register \details Returns the content of the IPSR Register. \return IPSR Register value */ __STATIC_FORCEINLINE uint32_t __get_IPSR(void) { uint32_t result; __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); return(result); } /** \brief Get APSR Register \details Returns the content of the APSR Register. \return APSR Register value */ __STATIC_FORCEINLINE uint32_t __get_APSR(void) { uint32_t result; __ASM volatile ("MRS %0, apsr" : "=r" (result) ); return(result); } /** \brief Get xPSR Register \details Returns the content of the xPSR Register. \return xPSR Register value */ __STATIC_FORCEINLINE uint32_t __get_xPSR(void) { uint32_t result; __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); return(result); } /** \brief Get Process Stack Pointer \details Returns the current value of the Process Stack Pointer (PSP). \return PSP Register value */ __STATIC_FORCEINLINE uint32_t __get_PSP(void) { register uint32_t result; __ASM volatile ("MRS %0, psp" : "=r" (result) ); return(result); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Process Stack Pointer (non-secure) \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. \return PSP Register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) { register uint32_t result; __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); return(result); } #endif /** \brief Set Process Stack Pointer \details Assigns the given value to the Process Stack Pointer (PSP). \param [in] topOfProcStack Process Stack Pointer value to set */ __STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) { __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Process Stack Pointer (non-secure) \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. \param [in] topOfProcStack Process Stack Pointer value to set */ __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) { __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); } #endif /** \brief Get Main Stack Pointer \details Returns the current value of the Main Stack Pointer (MSP). \return MSP Register value */ __STATIC_FORCEINLINE uint32_t __get_MSP(void) { register uint32_t result; __ASM volatile ("MRS %0, msp" : "=r" (result) ); return(result); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Main Stack Pointer (non-secure) \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. \return MSP Register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) { register uint32_t result; __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); return(result); } #endif /** \brief Set Main Stack Pointer \details Assigns the given value to the Main Stack Pointer (MSP). \param [in] topOfMainStack Main Stack Pointer value to set */ __STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) { __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Main Stack Pointer (non-secure) \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. \param [in] topOfMainStack Main Stack Pointer value to set */ __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) { __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); } #endif #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Stack Pointer (non-secure) \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. \return SP Register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) { register uint32_t result; __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); return(result); } /** \brief Set Stack Pointer (non-secure) \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. \param [in] topOfStack Stack Pointer value to set */ __STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) { __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); } #endif /** \brief Get Priority Mask \details Returns the current state of the priority mask bit from the Priority Mask Register. \return Priority Mask value */ __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) { uint32_t result; __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); return(result); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Priority Mask (non-secure) \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. \return Priority Mask value */ __STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) { uint32_t result; __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory"); return(result); } #endif /** \brief Set Priority Mask \details Assigns the given value to the Priority Mask Register. \param [in] priMask Priority Mask */ __STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) { __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Priority Mask (non-secure) \details Assigns the given value to the non-secure Priority Mask Register when in secure state. \param [in] priMask Priority Mask */ __STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) { __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); } #endif #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) /** \brief Enable FIQ \details Enables FIQ interrupts by clearing the F-bit in the CPSR. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __enable_fault_irq(void) { __ASM volatile ("cpsie f" : : : "memory"); } /** \brief Disable FIQ \details Disables FIQ interrupts by setting the F-bit in the CPSR. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __disable_fault_irq(void) { __ASM volatile ("cpsid f" : : : "memory"); } /** \brief Get Base Priority \details Returns the current value of the Base Priority register. \return Base Priority register value */ __STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) { uint32_t result; __ASM volatile ("MRS %0, basepri" : "=r" (result) ); return(result); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Base Priority (non-secure) \details Returns the current value of the non-secure Base Priority register when in secure state. \return Base Priority register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) { uint32_t result; __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); return(result); } #endif /** \brief Set Base Priority \details Assigns the given value to the Base Priority register. \param [in] basePri Base Priority value to set */ __STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) { __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Base Priority (non-secure) \details Assigns the given value to the non-secure Base Priority register when in secure state. \param [in] basePri Base Priority value to set */ __STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) { __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); } #endif /** \brief Set Base Priority with condition \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, or the new value increases the BASEPRI priority level. \param [in] basePri Base Priority value to set */ __STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) { __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); } /** \brief Get Fault Mask \details Returns the current value of the Fault Mask register. \return Fault Mask register value */ __STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) { uint32_t result; __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); return(result); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Fault Mask (non-secure) \details Returns the current value of the non-secure Fault Mask register when in secure state. \return Fault Mask register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) { uint32_t result; __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); return(result); } #endif /** \brief Set Fault Mask \details Assigns the given value to the Fault Mask register. \param [in] faultMask Fault Mask value to set */ __STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) { __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Fault Mask (non-secure) \details Assigns the given value to the non-secure Fault Mask register when in secure state. \param [in] faultMask Fault Mask value to set */ __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) { __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); } #endif #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) /** \brief Get Process Stack Pointer Limit Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence zero is returned always in non-secure mode. \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). \return PSPLIM Register value */ __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure PSPLIM is RAZ/WI return 0U; #else register uint32_t result; __ASM volatile ("MRS %0, psplim" : "=r" (result) ); return result; #endif } #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Process Stack Pointer Limit (non-secure) Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence zero is returned always. \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. \return PSPLIM Register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) // without main extensions, the non-secure PSPLIM is RAZ/WI return 0U; #else register uint32_t result; __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); return result; #endif } #endif /** \brief Set Process Stack Pointer Limit Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence the write is silently ignored in non-secure mode. \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set */ __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure PSPLIM is RAZ/WI (void)ProcStackPtrLimit; #else __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); #endif } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Process Stack Pointer (non-secure) Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence the write is silently ignored. \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set */ __STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) // without main extensions, the non-secure PSPLIM is RAZ/WI (void)ProcStackPtrLimit; #else __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); #endif } #endif /** \brief Get Main Stack Pointer Limit Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence zero is returned always in non-secure mode. \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). \return MSPLIM Register value */ __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure MSPLIM is RAZ/WI return 0U; #else register uint32_t result; __ASM volatile ("MRS %0, msplim" : "=r" (result) ); return result; #endif } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Main Stack Pointer Limit (non-secure) Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence zero is returned always. \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. \return MSPLIM Register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) // without main extensions, the non-secure MSPLIM is RAZ/WI return 0U; #else register uint32_t result; __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); return result; #endif } #endif /** \brief Set Main Stack Pointer Limit Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence the write is silently ignored in non-secure mode. \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set */ __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure MSPLIM is RAZ/WI (void)MainStackPtrLimit; #else __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); #endif } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Main Stack Pointer Limit (non-secure) Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence the write is silently ignored. \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. \param [in] MainStackPtrLimit Main Stack Pointer value to set */ __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) // without main extensions, the non-secure MSPLIM is RAZ/WI (void)MainStackPtrLimit; #else __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); #endif } #endif #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ #if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) /** \brief Get FPSCR \details Returns the current value of the Floating Point Status/Control register. \return Floating Point Status/Control register value */ __STATIC_FORCEINLINE uint32_t __get_FPSCR(void) { #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) #if __has_builtin(__builtin_arm_get_fpscr) || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ return __builtin_arm_get_fpscr(); #else uint32_t result; __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); return(result); #endif #else return(0U); #endif } /** \brief Set FPSCR \details Assigns the given value to the Floating Point Status/Control register. \param [in] fpscr Floating Point Status/Control value to set */ __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) { #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) #if __has_builtin(__builtin_arm_set_fpscr) || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ __builtin_arm_set_fpscr(fpscr); #else __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); #endif #else (void)fpscr; #endif } #endif /* ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ /*@} end of CMSIS_Core_RegAccFunctions */ /* ########################## Core Instruction Access ######################### */ /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface Access to dedicated instructions @{ */ /* Define macros for porting to both thumb1 and thumb2. * For thumb1, use low register (r0-r7), specified by constraint "l" * Otherwise, use general registers, specified by constraint "r" */ #if defined (__thumb__) && !defined (__thumb2__) #define __CMSIS_GCC_OUT_REG(r) "=l" (r) #define __CMSIS_GCC_RW_REG(r) "+l" (r) #define __CMSIS_GCC_USE_REG(r) "l" (r) #else #define __CMSIS_GCC_OUT_REG(r) "=r" (r) #define __CMSIS_GCC_RW_REG(r) "+r" (r) #define __CMSIS_GCC_USE_REG(r) "r" (r) #endif /** \brief No Operation \details No Operation does nothing. This instruction can be used for code alignment purposes. */ #define __NOP() __ASM volatile ("nop") /** \brief Wait For Interrupt \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. */ #define __WFI() __ASM volatile ("wfi") /** \brief Wait For Event \details Wait For Event is a hint instruction that permits the processor to enter a low-power state until one of a number of events occurs. */ #define __WFE() __ASM volatile ("wfe") /** \brief Send Event \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. */ #define __SEV() __ASM volatile ("sev") /** \brief Instruction Synchronization Barrier \details Instruction Synchronization Barrier flushes the pipeline in the processor, so that all instructions following the ISB are fetched from cache or memory, after the instruction has been completed. */ __STATIC_FORCEINLINE void __ISB(void) { __ASM volatile ("isb 0xF":::"memory"); } /** \brief Data Synchronization Barrier \details Acts as a special kind of Data Memory Barrier. It completes when all explicit memory accesses before this instruction complete. */ __STATIC_FORCEINLINE void __DSB(void) { __ASM volatile ("dsb 0xF":::"memory"); } /** \brief Data Memory Barrier \details Ensures the apparent order of the explicit memory operations before and after the instruction, without ensuring their completion. */ __STATIC_FORCEINLINE void __DMB(void) { __ASM volatile ("dmb 0xF":::"memory"); } /** \brief Reverse byte order (32 bit) \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. \param [in] value Value to reverse \return Reversed value */ __STATIC_FORCEINLINE uint32_t __REV(uint32_t value) { #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) return __builtin_bswap32(value); #else uint32_t result; __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); return result; #endif } /** \brief Reverse byte order (16 bit) \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. \param [in] value Value to reverse \return Reversed value */ __STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) { uint32_t result; __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); return result; } /** \brief Reverse byte order (16 bit) \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. \param [in] value Value to reverse \return Reversed value */ __STATIC_FORCEINLINE int16_t __REVSH(int16_t value) { #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) return (int16_t)__builtin_bswap16(value); #else int16_t result; __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); return result; #endif } /** \brief Rotate Right in unsigned value (32 bit) \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. \param [in] op1 Value to rotate \param [in] op2 Number of Bits to rotate \return Rotated value */ __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) { op2 %= 32U; if (op2 == 0U) { return op1; } return (op1 >> op2) | (op1 << (32U - op2)); } /** \brief Breakpoint \details Causes the processor to enter Debug state. Debug tools can use this to investigate system state when the instruction at a particular address is reached. \param [in] value is ignored by the processor. If required, a debugger can use it to store additional information about the breakpoint. */ #define __BKPT(value) __ASM volatile ("bkpt "#value) /** \brief Reverse bit order of value \details Reverses the bit order of the given value. \param [in] value Value to reverse \return Reversed value */ __STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) { uint32_t result; #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); #else uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ result = value; /* r will be reversed bits of v; first get LSB of v */ for (value >>= 1U; value != 0U; value >>= 1U) { result <<= 1U; result |= value & 1U; s--; } result <<= s; /* shift when v's highest bits are zero */ #endif return result; } /** \brief Count leading zeros \details Counts the number of leading zeros of a data value. \param [in] value Value to count the leading zeros \return number of leading zeros in value */ #define __CLZ (uint8_t)__builtin_clz #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) /** \brief LDR Exclusive (8 bit) \details Executes a exclusive LDR instruction for 8 bit value. \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ __STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) { uint32_t result; #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); #else /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not accepted by assembler. So has to use following less efficient pattern. */ __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); #endif return ((uint8_t) result); /* Add explicit type cast here */ } /** \brief LDR Exclusive (16 bit) \details Executes a exclusive LDR instruction for 16 bit values. \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ __STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) { uint32_t result; #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); #else /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not accepted by assembler. So has to use following less efficient pattern. */ __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); #endif return ((uint16_t) result); /* Add explicit type cast here */ } /** \brief LDR Exclusive (32 bit) \details Executes a exclusive LDR instruction for 32 bit values. \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ __STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) { uint32_t result; __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); return(result); } /** \brief STR Exclusive (8 bit) \details Executes a exclusive STR instruction for 8 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ __STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) { uint32_t result; __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); return(result); } /** \brief STR Exclusive (16 bit) \details Executes a exclusive STR instruction for 16 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ __STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) { uint32_t result; __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); return(result); } /** \brief STR Exclusive (32 bit) \details Executes a exclusive STR instruction for 32 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ __STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) { uint32_t result; __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); return(result); } /** \brief Remove the exclusive lock \details Removes the exclusive lock which is created by LDREX. */ __STATIC_FORCEINLINE void __CLREX(void) { __ASM volatile ("clrex" ::: "memory"); } #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) /** \brief Signed Saturate \details Saturates a signed value. \param [in] ARG1 Value to be saturated \param [in] ARG2 Bit position to saturate to (1..32) \return Saturated value */ #define __SSAT(ARG1,ARG2) \ __extension__ \ ({ \ int32_t __RES, __ARG1 = (ARG1); \ __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ __RES; \ }) /** \brief Unsigned Saturate \details Saturates an unsigned value. \param [in] ARG1 Value to be saturated \param [in] ARG2 Bit position to saturate to (0..31) \return Saturated value */ #define __USAT(ARG1,ARG2) \ __extension__ \ ({ \ uint32_t __RES, __ARG1 = (ARG1); \ __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ __RES; \ }) /** \brief Rotate Right with Extend (32 bit) \details Moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring. \param [in] value Value to rotate \return Rotated value */ __STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) { uint32_t result; __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); return(result); } /** \brief LDRT Unprivileged (8 bit) \details Executes a Unprivileged LDRT instruction for 8 bit value. \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ __STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) { uint32_t result; #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); #else /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not accepted by assembler. So has to use following less efficient pattern. */ __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); #endif return ((uint8_t) result); /* Add explicit type cast here */ } /** \brief LDRT Unprivileged (16 bit) \details Executes a Unprivileged LDRT instruction for 16 bit values. \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ __STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) { uint32_t result; #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); #else /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not accepted by assembler. So has to use following less efficient pattern. */ __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); #endif return ((uint16_t) result); /* Add explicit type cast here */ } /** \brief LDRT Unprivileged (32 bit) \details Executes a Unprivileged LDRT instruction for 32 bit values. \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ __STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) { uint32_t result; __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); return(result); } /** \brief STRT Unprivileged (8 bit) \details Executes a Unprivileged STRT instruction for 8 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) { __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); } /** \brief STRT Unprivileged (16 bit) \details Executes a Unprivileged STRT instruction for 16 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) { __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); } /** \brief STRT Unprivileged (32 bit) \details Executes a Unprivileged STRT instruction for 32 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) { __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); } #else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ /** \brief Signed Saturate \details Saturates a signed value. \param [in] value Value to be saturated \param [in] sat Bit position to saturate to (1..32) \return Saturated value */ __STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) { if ((sat >= 1U) && (sat <= 32U)) { const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); const int32_t min = -1 - max ; if (val > max) { return max; } else if (val < min) { return min; } } return val; } /** \brief Unsigned Saturate \details Saturates an unsigned value. \param [in] value Value to be saturated \param [in] sat Bit position to saturate to (0..31) \return Saturated value */ __STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) { if (sat <= 31U) { const uint32_t max = ((1U << sat) - 1U); if (val > (int32_t)max) { return max; } else if (val < 0) { return 0U; } } return (uint32_t)val; } #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) /** \brief Load-Acquire (8 bit) \details Executes a LDAB instruction for 8 bit value. \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ __STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) { uint32_t result; __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); return ((uint8_t) result); } /** \brief Load-Acquire (16 bit) \details Executes a LDAH instruction for 16 bit values. \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ __STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) { uint32_t result; __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); return ((uint16_t) result); } /** \brief Load-Acquire (32 bit) \details Executes a LDA instruction for 32 bit values. \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ __STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) { uint32_t result; __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); return(result); } /** \brief Store-Release (8 bit) \details Executes a STLB instruction for 8 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) { __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); } /** \brief Store-Release (16 bit) \details Executes a STLH instruction for 16 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) { __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); } /** \brief Store-Release (32 bit) \details Executes a STL instruction for 32 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) { __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); } /** \brief Load-Acquire Exclusive (8 bit) \details Executes a LDAB exclusive instruction for 8 bit value. \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ __STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) { uint32_t result; __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) ); return ((uint8_t) result); } /** \brief Load-Acquire Exclusive (16 bit) \details Executes a LDAH exclusive instruction for 16 bit values. \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ __STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) { uint32_t result; __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) ); return ((uint16_t) result); } /** \brief Load-Acquire Exclusive (32 bit) \details Executes a LDA exclusive instruction for 32 bit values. \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ __STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) { uint32_t result; __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) ); return(result); } /** \brief Store-Release Exclusive (8 bit) \details Executes a STLB exclusive instruction for 8 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ __STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) { uint32_t result; __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); return(result); } /** \brief Store-Release Exclusive (16 bit) \details Executes a STLH exclusive instruction for 16 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ __STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) { uint32_t result; __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); return(result); } /** \brief Store-Release Exclusive (32 bit) \details Executes a STL exclusive instruction for 32 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ __STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) { uint32_t result; __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); return(result); } #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ /*@}*/ /* end of group CMSIS_Core_InstructionInterface */ /* ################### Compiler specific Intrinsics ########################### */ /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics Access to dedicated SIMD instructions @{ */ #if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) __STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) { uint32_t result; __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); return(result); } #define __SSAT16(ARG1,ARG2) \ ({ \ int32_t __RES, __ARG1 = (ARG1); \ __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ __RES; \ }) #define __USAT16(ARG1,ARG2) \ ({ \ uint32_t __RES, __ARG1 = (ARG1); \ __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ __RES; \ }) __STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) { uint32_t result; __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); return(result); } __STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) { uint32_t result; __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); return(result); } __STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) { uint32_t result; __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); return(result); } __STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) { uint32_t result; __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); return(result); } __STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) { union llreg_u{ uint32_t w32[2]; uint64_t w64; } llr; llr.w64 = acc; #ifndef __ARMEB__ /* Little endian */ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); #else /* Big endian */ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); #endif return(llr.w64); } __STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) { union llreg_u{ uint32_t w32[2]; uint64_t w64; } llr; llr.w64 = acc; #ifndef __ARMEB__ /* Little endian */ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); #else /* Big endian */ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); #endif return(llr.w64); } __STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) { uint32_t result; __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); return(result); } __STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) { uint32_t result; __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); return(result); } __STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) { union llreg_u{ uint32_t w32[2]; uint64_t w64; } llr; llr.w64 = acc; #ifndef __ARMEB__ /* Little endian */ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); #else /* Big endian */ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); #endif return(llr.w64); } __STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) { union llreg_u{ uint32_t w32[2]; uint64_t w64; } llr; llr.w64 = acc; #ifndef __ARMEB__ /* Little endian */ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); #else /* Big endian */ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); #endif return(llr.w64); } __STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) { int32_t result; __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) { int32_t result; __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } #if 0 #define __PKHBT(ARG1,ARG2,ARG3) \ ({ \ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ __RES; \ }) #define __PKHTB(ARG1,ARG2,ARG3) \ ({ \ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ if (ARG3 == 0) \ __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ else \ __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ __RES; \ }) #endif #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) __STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) { int32_t result; __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); return(result); } #endif /* (__ARM_FEATURE_DSP == 1) */ /*@} end of group CMSIS_SIMD_intrinsics */ #pragma GCC diagnostic pop #endif /* __CMSIS_GCC_H */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/CMSIS/Include/cmsis_iccarm.h.
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/**************************************************************************//** * @file cmsis_iccarm.h * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file * @version V5.0.5 * @date 10. January 2018 ******************************************************************************/ //------------------------------------------------------------------------------ // // Copyright (c) 2017-2018 IAR Systems // // Licensed under the Apache License, Version 2.0 (the "License") // you may not use this file except in compliance with the License. // You may obtain a copy of the License at // http://www.apache.org/licenses/LICENSE-2.0 // // Unless required by applicable law or agreed to in writing, software // distributed under the License is distributed on an "AS IS" BASIS, // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. // //------------------------------------------------------------------------------ #ifndef __CMSIS_ICCARM_H__ #define __CMSIS_ICCARM_H__ #ifndef __ICCARM__ #error This file should only be compiled by ICCARM #endif #pragma system_include #define __IAR_FT _Pragma("inline=forced") __intrinsic #if (__VER__ >= 8000000) #define __ICCARM_V8 1 #else #define __ICCARM_V8 0 #endif #ifndef __ALIGNED #if __ICCARM_V8 #define __ALIGNED(x) __attribute__((aligned(x))) #elif (__VER__ >= 7080000) /* Needs IAR language extensions */ #define __ALIGNED(x) __attribute__((aligned(x))) #else #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. #define __ALIGNED(x) #endif #endif /* Define compiler macros for CPU architecture, used in CMSIS 5. */ #if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ /* Macros already defined */ #else #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) #define __ARM_ARCH_8M_MAIN__ 1 #elif defined(__ARM8M_BASELINE__) #define __ARM_ARCH_8M_BASE__ 1 #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' #if __ARM_ARCH == 6 #define __ARM_ARCH_6M__ 1 #elif __ARM_ARCH == 7 #if __ARM_FEATURE_DSP #define __ARM_ARCH_7EM__ 1 #else #define __ARM_ARCH_7M__ 1 #endif #endif /* __ARM_ARCH */ #endif /* __ARM_ARCH_PROFILE == 'M' */ #endif /* Alternativ core deduction for older ICCARM's */ #if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) #define __ARM_ARCH_6M__ 1 #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) #define __ARM_ARCH_7M__ 1 #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) #define __ARM_ARCH_7EM__ 1 #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) #define __ARM_ARCH_8M_BASE__ 1 #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) #define __ARM_ARCH_8M_MAIN__ 1 #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) #define __ARM_ARCH_8M_MAIN__ 1 #else #error "Unknown target." #endif #endif #if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 #define __IAR_M0_FAMILY 1 #elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 #define __IAR_M0_FAMILY 1 #else #define __IAR_M0_FAMILY 0 #endif #ifndef __ASM #define __ASM __asm #endif #ifndef __INLINE #define __INLINE inline #endif #ifndef __NO_RETURN #if __ICCARM_V8 #define __NO_RETURN __attribute__((__noreturn__)) #else #define __NO_RETURN _Pragma("object_attribute=__noreturn") #endif #endif #ifndef __PACKED #if __ICCARM_V8 #define __PACKED __attribute__((packed, aligned(1))) #else /* Needs IAR language extensions */ #define __PACKED __packed #endif #endif #ifndef __PACKED_STRUCT #if __ICCARM_V8 #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) #else /* Needs IAR language extensions */ #define __PACKED_STRUCT __packed struct #endif #endif #ifndef __PACKED_UNION #if __ICCARM_V8 #define __PACKED_UNION union __attribute__((packed, aligned(1))) #else /* Needs IAR language extensions */ #define __PACKED_UNION __packed union #endif #endif #ifndef __RESTRICT #define __RESTRICT restrict #endif #ifndef __STATIC_INLINE #define __STATIC_INLINE static inline #endif #ifndef __FORCEINLINE #define __FORCEINLINE _Pragma("inline=forced") #endif #ifndef __STATIC_FORCEINLINE #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE #endif #ifndef __UNALIGNED_UINT16_READ #pragma language=save #pragma language=extended __IAR_FT uint16_t __iar_uint16_read(void const *ptr) { return *(__packed uint16_t*)(ptr); } #pragma language=restore #define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) #endif #ifndef __UNALIGNED_UINT16_WRITE #pragma language=save #pragma language=extended __IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) { *(__packed uint16_t*)(ptr) = val;; } #pragma language=restore #define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) #endif #ifndef __UNALIGNED_UINT32_READ #pragma language=save #pragma language=extended __IAR_FT uint32_t __iar_uint32_read(void const *ptr) { return *(__packed uint32_t*)(ptr); } #pragma language=restore #define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) #endif #ifndef __UNALIGNED_UINT32_WRITE #pragma language=save #pragma language=extended __IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) { *(__packed uint32_t*)(ptr) = val;; } #pragma language=restore #define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) #endif #ifndef __UNALIGNED_UINT32 /* deprecated */ #pragma language=save #pragma language=extended __packed struct __iar_u32 { uint32_t v; }; #pragma language=restore #define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) #endif #ifndef __USED #if __ICCARM_V8 #define __USED __attribute__((used)) #else #define __USED _Pragma("__root") #endif #endif #ifndef __WEAK #if __ICCARM_V8 #define __WEAK __attribute__((weak)) #else #define __WEAK _Pragma("__weak") #endif #endif #ifndef __ICCARM_INTRINSICS_VERSION__ #define __ICCARM_INTRINSICS_VERSION__ 0 #endif #if __ICCARM_INTRINSICS_VERSION__ == 2 #if defined(__CLZ) #undef __CLZ #endif #if defined(__REVSH) #undef __REVSH #endif #if defined(__RBIT) #undef __RBIT #endif #if defined(__SSAT) #undef __SSAT #endif #if defined(__USAT) #undef __USAT #endif #include "iccarm_builtin.h" #define __disable_fault_irq __iar_builtin_disable_fiq #define __disable_irq __iar_builtin_disable_interrupt #define __enable_fault_irq __iar_builtin_enable_fiq #define __enable_irq __iar_builtin_enable_interrupt #define __arm_rsr __iar_builtin_rsr #define __arm_wsr __iar_builtin_wsr #define __get_APSR() (__arm_rsr("APSR")) #define __get_BASEPRI() (__arm_rsr("BASEPRI")) #define __get_CONTROL() (__arm_rsr("CONTROL")) #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) #define __get_FPSCR() (__arm_rsr("FPSCR")) #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) #else #define __get_FPSCR() ( 0 ) #define __set_FPSCR(VALUE) ((void)VALUE) #endif #define __get_IPSR() (__arm_rsr("IPSR")) #define __get_MSP() (__arm_rsr("MSP")) #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure MSPLIM is RAZ/WI #define __get_MSPLIM() (0U) #else #define __get_MSPLIM() (__arm_rsr("MSPLIM")) #endif #define __get_PRIMASK() (__arm_rsr("PRIMASK")) #define __get_PSP() (__arm_rsr("PSP")) #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure PSPLIM is RAZ/WI #define __get_PSPLIM() (0U) #else #define __get_PSPLIM() (__arm_rsr("PSPLIM")) #endif #define __get_xPSR() (__arm_rsr("xPSR")) #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) #define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE))) #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure MSPLIM is RAZ/WI #define __set_MSPLIM(VALUE) ((void)(VALUE)) #else #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) #endif #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure PSPLIM is RAZ/WI #define __set_PSPLIM(VALUE) ((void)(VALUE)) #else #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) #endif #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) #define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE))) #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) #define __NOP __iar_builtin_no_operation #define __CLZ __iar_builtin_CLZ #define __CLREX __iar_builtin_CLREX #define __DMB __iar_builtin_DMB #define __DSB __iar_builtin_DSB #define __ISB __iar_builtin_ISB #define __LDREXB __iar_builtin_LDREXB #define __LDREXH __iar_builtin_LDREXH #define __LDREXW __iar_builtin_LDREX #define __RBIT __iar_builtin_RBIT #define __REV __iar_builtin_REV #define __REV16 __iar_builtin_REV16 __IAR_FT int16_t __REVSH(int16_t val) { return (int16_t) __iar_builtin_REVSH(val); } #define __ROR __iar_builtin_ROR #define __RRX __iar_builtin_RRX #define __SEV __iar_builtin_SEV #if !__IAR_M0_FAMILY #define __SSAT __iar_builtin_SSAT #endif #define __STREXB __iar_builtin_STREXB #define __STREXH __iar_builtin_STREXH #define __STREXW __iar_builtin_STREX #if !__IAR_M0_FAMILY #define __USAT __iar_builtin_USAT #endif #define __WFE __iar_builtin_WFE #define __WFI __iar_builtin_WFI #if __ARM_MEDIA__ #define __SADD8 __iar_builtin_SADD8 #define __QADD8 __iar_builtin_QADD8 #define __SHADD8 __iar_builtin_SHADD8 #define __UADD8 __iar_builtin_UADD8 #define __UQADD8 __iar_builtin_UQADD8 #define __UHADD8 __iar_builtin_UHADD8 #define __SSUB8 __iar_builtin_SSUB8 #define __QSUB8 __iar_builtin_QSUB8 #define __SHSUB8 __iar_builtin_SHSUB8 #define __USUB8 __iar_builtin_USUB8 #define __UQSUB8 __iar_builtin_UQSUB8 #define __UHSUB8 __iar_builtin_UHSUB8 #define __SADD16 __iar_builtin_SADD16 #define __QADD16 __iar_builtin_QADD16 #define __SHADD16 __iar_builtin_SHADD16 #define __UADD16 __iar_builtin_UADD16 #define __UQADD16 __iar_builtin_UQADD16 #define __UHADD16 __iar_builtin_UHADD16 #define __SSUB16 __iar_builtin_SSUB16 #define __QSUB16 __iar_builtin_QSUB16 #define __SHSUB16 __iar_builtin_SHSUB16 #define __USUB16 __iar_builtin_USUB16 #define __UQSUB16 __iar_builtin_UQSUB16 #define __UHSUB16 __iar_builtin_UHSUB16 #define __SASX __iar_builtin_SASX #define __QASX __iar_builtin_QASX #define __SHASX __iar_builtin_SHASX #define __UASX __iar_builtin_UASX #define __UQASX __iar_builtin_UQASX #define __UHASX __iar_builtin_UHASX #define __SSAX __iar_builtin_SSAX #define __QSAX __iar_builtin_QSAX #define __SHSAX __iar_builtin_SHSAX #define __USAX __iar_builtin_USAX #define __UQSAX __iar_builtin_UQSAX #define __UHSAX __iar_builtin_UHSAX #define __USAD8 __iar_builtin_USAD8 #define __USADA8 __iar_builtin_USADA8 #define __SSAT16 __iar_builtin_SSAT16 #define __USAT16 __iar_builtin_USAT16 #define __UXTB16 __iar_builtin_UXTB16 #define __UXTAB16 __iar_builtin_UXTAB16 #define __SXTB16 __iar_builtin_SXTB16 #define __SXTAB16 __iar_builtin_SXTAB16 #define __SMUAD __iar_builtin_SMUAD #define __SMUADX __iar_builtin_SMUADX #define __SMMLA __iar_builtin_SMMLA #define __SMLAD __iar_builtin_SMLAD #define __SMLADX __iar_builtin_SMLADX #define __SMLALD __iar_builtin_SMLALD #define __SMLALDX __iar_builtin_SMLALDX #define __SMUSD __iar_builtin_SMUSD #define __SMUSDX __iar_builtin_SMUSDX #define __SMLSD __iar_builtin_SMLSD #define __SMLSDX __iar_builtin_SMLSDX #define __SMLSLD __iar_builtin_SMLSLD #define __SMLSLDX __iar_builtin_SMLSLDX #define __SEL __iar_builtin_SEL #define __QADD __iar_builtin_QADD #define __QSUB __iar_builtin_QSUB #define __PKHBT __iar_builtin_PKHBT #define __PKHTB __iar_builtin_PKHTB #endif #else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ #if __IAR_M0_FAMILY /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ #define __CLZ __cmsis_iar_clz_not_active #define __SSAT __cmsis_iar_ssat_not_active #define __USAT __cmsis_iar_usat_not_active #define __RBIT __cmsis_iar_rbit_not_active #define __get_APSR __cmsis_iar_get_APSR_not_active #endif #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) #define __get_FPSCR __cmsis_iar_get_FPSR_not_active #define __set_FPSCR __cmsis_iar_set_FPSR_not_active #endif #ifdef __INTRINSICS_INCLUDED #error intrinsics.h is already included previously! #endif #include <intrinsics.h> #if __IAR_M0_FAMILY /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ #undef __CLZ #undef __SSAT #undef __USAT #undef __RBIT #undef __get_APSR __STATIC_INLINE uint8_t __CLZ(uint32_t data) { if (data == 0U) { return 32U; } uint32_t count = 0U; uint32_t mask = 0x80000000U; while ((data & mask) == 0U) { count += 1U; mask = mask >> 1U; } return count; } __STATIC_INLINE uint32_t __RBIT(uint32_t v) { uint8_t sc = 31U; uint32_t r = v; for (v >>= 1U; v; v >>= 1U) { r <<= 1U; r |= v & 1U; sc--; } return (r << sc); } __STATIC_INLINE uint32_t __get_APSR(void) { uint32_t res; __asm("MRS %0,APSR" : "=r" (res)); return res; } #endif #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) #undef __get_FPSCR #undef __set_FPSCR #define __get_FPSCR() (0) #define __set_FPSCR(VALUE) ((void)VALUE) #endif #pragma diag_suppress=Pe940 #pragma diag_suppress=Pe177 #define __enable_irq __enable_interrupt #define __disable_irq __disable_interrupt #define __NOP __no_operation #define __get_xPSR __get_PSR #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) { return __LDREX((unsigned long *)ptr); } __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) { return __STREX(value, (unsigned long *)ptr); } #endif /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ #if (__CORTEX_M >= 0x03) __IAR_FT uint32_t __RRX(uint32_t value) { uint32_t result; __ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc"); return(result); } __IAR_FT void __set_BASEPRI_MAX(uint32_t value) { __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); } #define __enable_fault_irq __enable_fiq #define __disable_fault_irq __disable_fiq #endif /* (__CORTEX_M >= 0x03) */ __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) { return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); } #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) __IAR_FT uint32_t __get_MSPLIM(void) { uint32_t res; #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure MSPLIM is RAZ/WI res = 0U; #else __asm volatile("MRS %0,MSPLIM" : "=r" (res)); #endif return res; } __IAR_FT void __set_MSPLIM(uint32_t value) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure MSPLIM is RAZ/WI (void)value; #else __asm volatile("MSR MSPLIM,%0" :: "r" (value)); #endif } __IAR_FT uint32_t __get_PSPLIM(void) { uint32_t res; #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure PSPLIM is RAZ/WI res = 0U; #else __asm volatile("MRS %0,PSPLIM" : "=r" (res)); #endif return res; } __IAR_FT void __set_PSPLIM(uint32_t value) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure PSPLIM is RAZ/WI (void)value; #else __asm volatile("MSR PSPLIM,%0" :: "r" (value)); #endif } __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) { uint32_t res; __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); return res; } __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) { __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); } __IAR_FT uint32_t __TZ_get_PSP_NS(void) { uint32_t res; __asm volatile("MRS %0,PSP_NS" : "=r" (res)); return res; } __IAR_FT void __TZ_set_PSP_NS(uint32_t value) { __asm volatile("MSR PSP_NS,%0" :: "r" (value)); } __IAR_FT uint32_t __TZ_get_MSP_NS(void) { uint32_t res; __asm volatile("MRS %0,MSP_NS" : "=r" (res)); return res; } __IAR_FT void __TZ_set_MSP_NS(uint32_t value) { __asm volatile("MSR MSP_NS,%0" :: "r" (value)); } __IAR_FT uint32_t __TZ_get_SP_NS(void) { uint32_t res; __asm volatile("MRS %0,SP_NS" : "=r" (res)); return res; } __IAR_FT void __TZ_set_SP_NS(uint32_t value) { __asm volatile("MSR SP_NS,%0" :: "r" (value)); } __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) { uint32_t res; __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); return res; } __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) { __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); } __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) { uint32_t res; __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); return res; } __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) { __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); } __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) { uint32_t res; __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); return res; } __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) { __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); } __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) { uint32_t res; __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); return res; } __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) { __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); } __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) { uint32_t res; __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); return res; } __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) { __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); } #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ #endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ #define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) #if __IAR_M0_FAMILY __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) { if ((sat >= 1U) && (sat <= 32U)) { const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); const int32_t min = -1 - max ; if (val > max) { return max; } else if (val < min) { return min; } } return val; } __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) { if (sat <= 31U) { const uint32_t max = ((1U << sat) - 1U); if (val > (int32_t)max) { return max; } else if (val < 0) { return 0U; } } return (uint32_t)val; } #endif #if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) { uint32_t res; __ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); return ((uint8_t)res); } __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) { uint32_t res; __ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); return ((uint16_t)res); } __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) { uint32_t res; __ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); return res; } __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) { __ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); } __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) { __ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); } __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) { __ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); } #endif /* (__CORTEX_M >= 0x03) */ #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) { uint32_t res; __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); return ((uint8_t)res); } __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) { uint32_t res; __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); return ((uint16_t)res); } __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) { uint32_t res; __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); return res; } __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) { __ASM volatile ("STLB %1, [%0]" :: "r" (*ptr), "r" (value) : "memory"); } __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) { __ASM volatile ("STLH %1, [%0]" :: "r" (*ptr), "r" (value) : "memory"); } __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) { __ASM volatile ("STL %1, [%0]" :: "r" (*ptr), "r" (value) : "memory"); } __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) { uint32_t res; __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); return ((uint8_t)res); } __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) { uint32_t res; __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); return ((uint16_t)res); } __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) { uint32_t res; __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); return res; } __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) { uint32_t res; __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (*ptr), "r" (value) : "memory"); return res; } __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) { uint32_t res; __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (*ptr), "r" (value) : "memory"); return res; } __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) { uint32_t res; __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (*ptr), "r" (value) : "memory"); return res; } #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ #undef __IAR_FT #undef __IAR_M0_FAMILY #undef __ICCARM_V8 #pragma diag_default=Pe940 #pragma diag_default=Pe177 #endif /* __CMSIS_ICCARM_H__ */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/CMSIS/Include/cmsis_version.h.
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/**************************************************************************//** * @file cmsis_version.h * @brief CMSIS Core(M) Version definitions * @version V5.0.2 * @date 19. April 2017 ******************************************************************************/ /* * Copyright (c) 2009-2017 ARM Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__clang__) #pragma clang system_header /* treat file as system include file */ #endif #ifndef __CMSIS_VERSION_H #define __CMSIS_VERSION_H /* CMSIS Version definitions */ #define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ #define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */ #define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ #endif |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/CMSIS/Include/core_armv8mbl.h.
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/**************************************************************************//** * @file core_armv8mbl.h * @brief CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File * @version V5.0.4 * @date 10. January 2018 ******************************************************************************/ /* * Copyright (c) 2009-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__clang__) #pragma clang system_header /* treat file as system include file */ #endif #ifndef __CORE_ARMV8MBL_H_GENERIC #define __CORE_ARMV8MBL_H_GENERIC #include <stdint.h> #ifdef __cplusplus extern "C" { #endif /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions CMSIS violates the following MISRA-C:2004 rules: \li Required Rule 8.5, object/function definition in header file.<br> Function definitions in header files are used to allow 'inlining'. \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br> Unions are used for effective representation of core registers. \li Advisory Rule 19.7, Function-like macro defined.<br> Function-like macros are used to allow more efficient code. */ /******************************************************************************* * CMSIS definitions ******************************************************************************/ /** \ingroup Cortex_ARMv8MBL @{ */ #include "cmsis_version.h" /* CMSIS definitions */ #define __ARMv8MBL_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ #define __ARMv8MBL_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ #define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \ __ARMv8MBL_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ #define __CORTEX_M ( 2U) /*!< Cortex-M Core */ /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all */ #define __FPU_USED 0U #if defined ( __CC_ARM ) #if defined __TARGET_FPU_VFP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #if defined __ARM_PCS_VFP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __GNUC__ ) #if defined (__VFP_FP__) && !defined(__SOFTFP__) #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __ICCARM__ ) #if defined __ARMVFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __TI_ARM__ ) #if defined __TI_VFP_SUPPORT__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __TASKING__ ) #if defined __FPU_VFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __CSMC__ ) #if ( __CSMC__ & 0x400U) #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #endif #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ #ifdef __cplusplus } #endif #endif /* __CORE_ARMV8MBL_H_GENERIC */ #ifndef __CMSIS_GENERIC #ifndef __CORE_ARMV8MBL_H_DEPENDANT #define __CORE_ARMV8MBL_H_DEPENDANT #ifdef __cplusplus extern "C" { #endif /* check device defines and use defaults */ #if defined __CHECK_DEVICE_DEFINES #ifndef __ARMv8MBL_REV #define __ARMv8MBL_REV 0x0000U #warning "__ARMv8MBL_REV not defined in device header file; using default!" #endif #ifndef __FPU_PRESENT #define __FPU_PRESENT 0U #warning "__FPU_PRESENT not defined in device header file; using default!" #endif #ifndef __MPU_PRESENT #define __MPU_PRESENT 0U #warning "__MPU_PRESENT not defined in device header file; using default!" #endif #ifndef __SAUREGION_PRESENT #define __SAUREGION_PRESENT 0U #warning "__SAUREGION_PRESENT not defined in device header file; using default!" #endif #ifndef __VTOR_PRESENT #define __VTOR_PRESENT 0U #warning "__VTOR_PRESENT not defined in device header file; using default!" #endif #ifndef __NVIC_PRIO_BITS #define __NVIC_PRIO_BITS 2U #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" #endif #ifndef __Vendor_SysTickConfig #define __Vendor_SysTickConfig 0U #warning "__Vendor_SysTickConfig not defined in device header file; using default!" #endif #ifndef __ETM_PRESENT #define __ETM_PRESENT 0U #warning "__ETM_PRESENT not defined in device header file; using default!" #endif #ifndef __MTB_PRESENT #define __MTB_PRESENT 0U #warning "__MTB_PRESENT not defined in device header file; using default!" #endif #endif /* IO definitions (access restrictions to peripheral registers) */ /** \defgroup CMSIS_glob_defs CMSIS Global Defines <strong>IO Type Qualifiers</strong> are used \li to specify the access to peripheral variables. \li for automatic generation of peripheral register debug information. */ #ifdef __cplusplus #define __I volatile /*!< Defines 'read only' permissions */ #else #define __I volatile const /*!< Defines 'read only' permissions */ #endif #define __O volatile /*!< Defines 'write only' permissions */ #define __IO volatile /*!< Defines 'read / write' permissions */ /* following defines should be used for structure members */ #define __IM volatile const /*! Defines 'read only' structure member permissions */ #define __OM volatile /*! Defines 'write only' structure member permissions */ #define __IOM volatile /*! Defines 'read / write' structure member permissions */ /*@} end of group ARMv8MBL */ /******************************************************************************* * Register Abstraction Core Register contain: - Core Register - Core NVIC Register - Core SCB Register - Core SysTick Register - Core Debug Register - Core MPU Register - Core SAU Register ******************************************************************************/ /** \defgroup CMSIS_core_register Defines and Type Definitions \brief Type definitions and defines for Cortex-M processor based devices. */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CORE Status and Control Registers \brief Core Register type definitions. @{ */ /** \brief Union type to access the Application Program Status Register (APSR). */ typedef union { struct { uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } APSR_Type; /* APSR Register Definitions */ #define APSR_N_Pos 31U /*!< APSR: N Position */ #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ #define APSR_Z_Pos 30U /*!< APSR: Z Position */ #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ #define APSR_C_Pos 29U /*!< APSR: C Position */ #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ #define APSR_V_Pos 28U /*!< APSR: V Position */ #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } IPSR_Type; /* IPSR Register Definitions */ #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } xPSR_Type; /* xPSR Register Definitions */ #define xPSR_N_Pos 31U /*!< xPSR: N Position */ #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ #define xPSR_C_Pos 29U /*!< xPSR: C Position */ #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ #define xPSR_V_Pos 28U /*!< xPSR: V Position */ #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ #define xPSR_T_Pos 24U /*!< xPSR: T Position */ #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ /** \brief Union type to access the Control Registers (CONTROL). */ typedef union { struct { uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } CONTROL_Type; /* CONTROL Register Definitions */ #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ /*@} end of group CMSIS_CORE */ /** \ingroup CMSIS_core_register \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \brief Type definitions for the NVIC Registers @{ */ /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). */ typedef struct { __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ uint32_t RESERVED0[16U]; __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ uint32_t RSERVED1[16U]; __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ uint32_t RESERVED2[16U]; __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ uint32_t RESERVED3[16U]; __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ uint32_t RESERVED4[16U]; __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ uint32_t RESERVED5[16U]; __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ } NVIC_Type; /*@} end of group CMSIS_NVIC */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCB System Control Block (SCB) \brief Type definitions for the System Control Block Registers @{ */ /** \brief Structure type to access the System Control Block (SCB). */ typedef struct { __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ #else uint32_t RESERVED0; #endif __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ uint32_t RESERVED1; __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ } SCB_Type; /* SCB CPUID Register Definitions */ #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ #define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ #define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ #define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) /* SCB Vector Table Offset Register Definitions */ #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ #endif /* SCB Application Interrupt and Reset Control Register Definitions */ #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ #define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ #define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ #define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ #define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ #define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ #define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ /* SCB System Control Register Definitions */ #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ #define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ #define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ /* SCB Configuration Control Register Definitions */ #define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ #define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ #define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ #define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ #define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ /* SCB System Handler Control and State Register Definitions */ #define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ #define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ #define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ #define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ #define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ #define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ /*@} end of group CMSIS_SCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SysTick System Tick Timer (SysTick) \brief Type definitions for the System Timer Registers. @{ */ /** \brief Structure type to access the System Timer (SysTick). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ } SysTick_Type; /* SysTick Control / Status Register Definitions */ #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ /*@} end of group CMSIS_SysTick */ /** \ingroup CMSIS_core_register \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) \brief Type definitions for the Data Watchpoint and Trace (DWT) @{ */ /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ uint32_t RESERVED0[6U]; __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ uint32_t RESERVED1[1U]; __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ uint32_t RESERVED2[1U]; __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ uint32_t RESERVED3[1U]; __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ uint32_t RESERVED4[1U]; __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ uint32_t RESERVED5[1U]; __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ uint32_t RESERVED6[1U]; __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ uint32_t RESERVED7[1U]; __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ uint32_t RESERVED8[1U]; __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ uint32_t RESERVED9[1U]; __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ uint32_t RESERVED10[1U]; __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ uint32_t RESERVED11[1U]; __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ uint32_t RESERVED12[1U]; __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ uint32_t RESERVED13[1U]; __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ uint32_t RESERVED14[1U]; __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ uint32_t RESERVED15[1U]; __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ uint32_t RESERVED16[1U]; __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ uint32_t RESERVED17[1U]; __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ uint32_t RESERVED18[1U]; __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ uint32_t RESERVED19[1U]; __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ uint32_t RESERVED20[1U]; __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ uint32_t RESERVED21[1U]; __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ uint32_t RESERVED22[1U]; __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ uint32_t RESERVED23[1U]; __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ uint32_t RESERVED24[1U]; __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ uint32_t RESERVED25[1U]; __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ uint32_t RESERVED26[1U]; __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ uint32_t RESERVED27[1U]; __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ uint32_t RESERVED28[1U]; __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ uint32_t RESERVED29[1U]; __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ uint32_t RESERVED30[1U]; __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ uint32_t RESERVED31[1U]; __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ } DWT_Type; /* DWT Control Register Definitions */ #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ /* DWT Comparator Function Register Definitions */ #define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ #define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ #define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ #define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ #define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ #define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ /*@}*/ /* end of group CMSIS_DWT */ /** \ingroup CMSIS_core_register \defgroup CMSIS_TPI Trace Port Interface (TPI) \brief Type definitions for the Trace Port Interface (TPI) @{ */ /** \brief Structure type to access the Trace Port Interface Register (TPI). */ typedef struct { __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ uint32_t RESERVED0[2U]; __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ uint32_t RESERVED1[55U]; __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ uint32_t RESERVED2[131U]; __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ uint32_t RESERVED3[759U]; __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ uint32_t RESERVED4[1U]; __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ uint32_t RESERVED5[39U]; __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ uint32_t RESERVED7[8U]; __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ } TPI_Type; /* TPI Asynchronous Clock Prescaler Register Definitions */ #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ /* TPI Selected Pin Protocol Register Definitions */ #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ /* TPI Formatter and Flush Status Register Definitions */ #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ /* TPI Formatter and Flush Control Register Definitions */ #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ /* TPI TRIGGER Register Definitions */ #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ /* TPI Integration ETM Data Register Definitions (FIFO0) */ #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ /* TPI ITATBCTR2 Register Definitions */ #define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ /* TPI Integration ITM Data Register Definitions (FIFO1) */ #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ /* TPI ITATBCTR0 Register Definitions */ #define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ /* TPI Integration Mode Control Register Definitions */ #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ /* TPI DEVID Register Definitions */ #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ /* TPI DEVTYPE Register Definitions */ #define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ #define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ /*@}*/ /* end of group CMSIS_TPI */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) /** \ingroup CMSIS_core_register \defgroup CMSIS_MPU Memory Protection Unit (MPU) \brief Type definitions for the Memory Protection Unit (MPU) @{ */ /** \brief Structure type to access the Memory Protection Unit (MPU). */ typedef struct { __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ uint32_t RESERVED0[7U]; union { __IOM uint32_t MAIR[2]; struct { __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ }; }; } MPU_Type; #define MPU_TYPE_RALIASES 1U /* MPU Type Register Definitions */ #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ /* MPU Control Register Definitions */ #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ /* MPU Region Number Register Definitions */ #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ /* MPU Region Base Address Register Definitions */ #define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ #define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ #define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ #define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ #define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ #define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ #define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ #define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ /* MPU Region Limit Address Register Definitions */ #define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ #define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ #define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ #define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ #define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ #define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ /* MPU Memory Attribute Indirection Register 0 Definitions */ #define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ #define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ #define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ #define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ #define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ #define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ #define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ #define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ /* MPU Memory Attribute Indirection Register 1 Definitions */ #define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ #define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ #define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ #define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ #define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ #define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ #define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ #define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ /*@} end of group CMSIS_MPU */ #endif #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \ingroup CMSIS_core_register \defgroup CMSIS_SAU Security Attribution Unit (SAU) \brief Type definitions for the Security Attribution Unit (SAU) @{ */ /** \brief Structure type to access the Security Attribution Unit (SAU). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ #endif } SAU_Type; /* SAU Control Register Definitions */ #define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ #define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ #define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ #define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ /* SAU Type Register Definitions */ #define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ #define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) /* SAU Region Number Register Definitions */ #define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ #define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ /* SAU Region Base Address Register Definitions */ #define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ #define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ /* SAU Region Limit Address Register Definitions */ #define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ #define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ #define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ #define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ #define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ #define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ /*@} end of group CMSIS_SAU */ #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \brief Type definitions for the Core Debug Registers @{ */ /** \brief Structure type to access the Core Debug Register (CoreDebug). */ typedef struct { __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ uint32_t RESERVED4[1U]; __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ } CoreDebug_Type; /* Debug Halting Control and Status Register Definitions */ #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ /* Debug Core Register Selector Register Definitions */ #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ /* Debug Exception and Monitor Control Register */ #define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ #define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ /* Debug Authentication Control Register Definitions */ #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ #define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ #define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ #define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ #define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ /* Debug Security Control and Status Register Definitions */ #define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ #define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ #define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ #define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ #define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ #define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ /*@} end of group CMSIS_CoreDebug */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_bitfield Core register bit field macros \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). @{ */ /** \brief Mask and shift a bit field value for use in a register bit range. \param[in] field Name of the register bit field. \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. \return Masked and shifted value. */ #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) /** \brief Mask and shift a register value to extract a bit filed value. \param[in] field Name of the register bit field. \param[in] value Value of register. This parameter is interpreted as an uint32_t type. \return Masked and shifted bit field value. */ #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) /*@} end of group CMSIS_core_bitfield */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_base Core Definitions \brief Definitions for base addresses, unions, and structures. @{ */ /* Memory mapping of Core Hardware */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ #endif #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ #endif #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ #endif #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /*@} */ /******************************************************************************* * Hardware Abstraction Layer Core Function Interface contains: - Core NVIC Functions - Core SysTick Functions - Core Register Access Functions ******************************************************************************/ /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference */ /* ########################## NVIC functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_NVICFunctions NVIC Functions \brief Functions that manage interrupts and exceptions via the NVIC. @{ */ #ifdef CMSIS_NVIC_VIRTUAL #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" #endif #include CMSIS_NVIC_VIRTUAL_HEADER_FILE #else /*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Armv8-M Baseline */ /*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Armv8-M Baseline */ #define NVIC_EnableIRQ __NVIC_EnableIRQ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ #define NVIC_DisableIRQ __NVIC_DisableIRQ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ #define NVIC_GetActive __NVIC_GetActive #define NVIC_SetPriority __NVIC_SetPriority #define NVIC_GetPriority __NVIC_GetPriority #define NVIC_SystemReset __NVIC_SystemReset #endif /* CMSIS_NVIC_VIRTUAL */ #ifdef CMSIS_VECTAB_VIRTUAL #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" #endif #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE #else #define NVIC_SetVector __NVIC_SetVector #define NVIC_GetVector __NVIC_GetVector #endif /* (CMSIS_VECTAB_VIRTUAL) */ #define NVIC_USER_IRQ_OFFSET 16 /* Interrupt Priorities are WORD accessible only under Armv6-M */ /* The following MACROS handle generation of the register offset and byte masks */ #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) /** \brief Enable Interrupt \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Interrupt Enable status \details Returns a device specific interrupt enable status from the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt is not enabled. \return 1 Interrupt is enabled. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Disable Interrupt \details Disables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __DSB(); __ISB(); } } /** \brief Get Pending Interrupt \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Pending Interrupt \details Sets the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Clear Pending Interrupt \details Clears the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Active Interrupt \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not active. \return 1 Interrupt status is active. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief Get Interrupt Target State \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 if interrupt is assigned to Secure \return 1 if interrupt is assigned to Non Secure \note IRQn must not be negative. */ __STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Interrupt Target State \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 if interrupt is assigned to Secure 1 if interrupt is assigned to Non Secure \note IRQn must not be negative. */ __STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Clear Interrupt Target State \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 if interrupt is assigned to Secure 1 if interrupt is assigned to Non Secure \note IRQn must not be negative. */ __STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /** \brief Set Interrupt Priority \details Sets the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) { NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } else { SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } } /** \brief Get Interrupt Priority \details Reads the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); } else { return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); } } /** \brief Set Interrupt Vector \details Sets an interrupt vector in SRAM based interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. VTOR must been relocated to SRAM before. If VTOR is not present address 0 must be mapped to SRAM. \param [in] IRQn Interrupt number \param [in] vector Address of interrupt handler function */ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) uint32_t *vectors = (uint32_t *)SCB->VTOR; #else uint32_t *vectors = (uint32_t *)0x0U; #endif vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; } /** \brief Get Interrupt Vector \details Reads an interrupt vector from interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Address of interrupt handler function */ __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) { #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) uint32_t *vectors = (uint32_t *)SCB->VTOR; #else uint32_t *vectors = (uint32_t *)0x0U; #endif return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; } /** \brief System Reset \details Initiates a system reset request to reset the MCU. */ __STATIC_INLINE void __NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | SCB_AIRCR_SYSRESETREQ_Msk); __DSB(); /* Ensure completion of memory access */ for(;;) /* wait until reset */ { __NOP(); } } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief Enable Interrupt (non-secure) \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Interrupt Enable status (non-secure) \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt is not enabled. \return 1 Interrupt is enabled. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Disable Interrupt (non-secure) \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Pending Interrupt (non-secure) \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Pending Interrupt (non-secure) \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Clear Pending Interrupt (non-secure) \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Active Interrupt (non-secure) \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not active. \return 1 Interrupt status is active. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Interrupt Priority (non-secure) \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every non-secure processor exception. */ __STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } else { SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } } /** \brief Get Interrupt Priority (non-secure) \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); } else { return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); } } #endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ /*@} end of CMSIS_Core_NVICFunctions */ /* ########################## MPU functions #################################### */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #include "mpu_armv8.h" #endif /* ########################## FPU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_FpuFunctions FPU Functions \brief Function that provides FPU type. @{ */ /** \brief get FPU type \details returns the FPU type \returns - \b 0: No FPU - \b 1: Single precision FPU - \b 2: Double + Single precision FPU */ __STATIC_INLINE uint32_t SCB_GetFPUType(void) { return 0U; /* No FPU */ } /*@} end of CMSIS_Core_FpuFunctions */ /* ########################## SAU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SAUFunctions SAU Functions \brief Functions that configure the SAU. @{ */ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief Enable SAU \details Enables the Security Attribution Unit (SAU). */ __STATIC_INLINE void TZ_SAU_Enable(void) { SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); } /** \brief Disable SAU \details Disables the Security Attribution Unit (SAU). */ __STATIC_INLINE void TZ_SAU_Disable(void) { SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); } #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /*@} end of CMSIS_Core_SAUFunctions */ /* ################################## SysTick function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SysTickFunctions SysTick Functions \brief Functions that configure the System. @{ */ #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) /** \brief System Tick Configuration \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief System Tick Configuration (non-secure) \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b> must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ #endif /*@} end of CMSIS_Core_SysTickFunctions */ #ifdef __cplusplus } #endif #endif /* __CORE_ARMV8MBL_H_DEPENDANT */ #endif /* __CMSIS_GENERIC */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/CMSIS/Include/core_armv8mml.h.
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/**************************************************************************//** * @file core_armv8mml.h * @brief CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File * @version V5.0.4 * @date 10. January 2018 ******************************************************************************/ /* * Copyright (c) 2009-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__clang__) #pragma clang system_header /* treat file as system include file */ #endif #ifndef __CORE_ARMV8MML_H_GENERIC #define __CORE_ARMV8MML_H_GENERIC #include <stdint.h> #ifdef __cplusplus extern "C" { #endif /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions CMSIS violates the following MISRA-C:2004 rules: \li Required Rule 8.5, object/function definition in header file.<br> Function definitions in header files are used to allow 'inlining'. \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br> Unions are used for effective representation of core registers. \li Advisory Rule 19.7, Function-like macro defined.<br> Function-like macros are used to allow more efficient code. */ /******************************************************************************* * CMSIS definitions ******************************************************************************/ /** \ingroup Cortex_ARMv8MML @{ */ #include "cmsis_version.h" /* CMSIS Armv8MML definitions */ #define __ARMv8MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ #define __ARMv8MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ #define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \ __ARMv8MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ #define __CORTEX_M (81U) /*!< Cortex-M Core */ /** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. */ #if defined ( __CC_ARM ) #if defined __TARGET_FPU_VFP #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #if defined(__ARM_FEATURE_DSP) #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" #define __DSP_USED 0U #endif #else #define __DSP_USED 0U #endif #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #if defined __ARM_PCS_VFP #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #if defined(__ARM_FEATURE_DSP) #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" #define __DSP_USED 0U #endif #else #define __DSP_USED 0U #endif #elif defined ( __GNUC__ ) #if defined (__VFP_FP__) && !defined(__SOFTFP__) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #if defined(__ARM_FEATURE_DSP) #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" #define __DSP_USED 0U #endif #else #define __DSP_USED 0U #endif #elif defined ( __ICCARM__ ) #if defined __ARMVFP__ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #if defined(__ARM_FEATURE_DSP) #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" #define __DSP_USED 0U #endif #else #define __DSP_USED 0U #endif #elif defined ( __TI_ARM__ ) #if defined __TI_VFP_SUPPORT__ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined ( __TASKING__ ) #if defined __FPU_VFP__ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined ( __CSMC__ ) #if ( __CSMC__ & 0x400U) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #endif #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ #ifdef __cplusplus } #endif #endif /* __CORE_ARMV8MML_H_GENERIC */ #ifndef __CMSIS_GENERIC #ifndef __CORE_ARMV8MML_H_DEPENDANT #define __CORE_ARMV8MML_H_DEPENDANT #ifdef __cplusplus extern "C" { #endif /* check device defines and use defaults */ #if defined __CHECK_DEVICE_DEFINES #ifndef __ARMv8MML_REV #define __ARMv8MML_REV 0x0000U #warning "__ARMv8MML_REV not defined in device header file; using default!" #endif #ifndef __FPU_PRESENT #define __FPU_PRESENT 0U #warning "__FPU_PRESENT not defined in device header file; using default!" #endif #ifndef __MPU_PRESENT #define __MPU_PRESENT 0U #warning "__MPU_PRESENT not defined in device header file; using default!" #endif #ifndef __SAUREGION_PRESENT #define __SAUREGION_PRESENT 0U #warning "__SAUREGION_PRESENT not defined in device header file; using default!" #endif #ifndef __DSP_PRESENT #define __DSP_PRESENT 0U #warning "__DSP_PRESENT not defined in device header file; using default!" #endif #ifndef __NVIC_PRIO_BITS #define __NVIC_PRIO_BITS 3U #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" #endif #ifndef __Vendor_SysTickConfig #define __Vendor_SysTickConfig 0U #warning "__Vendor_SysTickConfig not defined in device header file; using default!" #endif #endif /* IO definitions (access restrictions to peripheral registers) */ /** \defgroup CMSIS_glob_defs CMSIS Global Defines <strong>IO Type Qualifiers</strong> are used \li to specify the access to peripheral variables. \li for automatic generation of peripheral register debug information. */ #ifdef __cplusplus #define __I volatile /*!< Defines 'read only' permissions */ #else #define __I volatile const /*!< Defines 'read only' permissions */ #endif #define __O volatile /*!< Defines 'write only' permissions */ #define __IO volatile /*!< Defines 'read / write' permissions */ /* following defines should be used for structure members */ #define __IM volatile const /*! Defines 'read only' structure member permissions */ #define __OM volatile /*! Defines 'write only' structure member permissions */ #define __IOM volatile /*! Defines 'read / write' structure member permissions */ /*@} end of group ARMv8MML */ /******************************************************************************* * Register Abstraction Core Register contain: - Core Register - Core NVIC Register - Core SCB Register - Core SysTick Register - Core Debug Register - Core MPU Register - Core SAU Register - Core FPU Register ******************************************************************************/ /** \defgroup CMSIS_core_register Defines and Type Definitions \brief Type definitions and defines for Cortex-M processor based devices. */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CORE Status and Control Registers \brief Core Register type definitions. @{ */ /** \brief Union type to access the Application Program Status Register (APSR). */ typedef union { struct { uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } APSR_Type; /* APSR Register Definitions */ #define APSR_N_Pos 31U /*!< APSR: N Position */ #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ #define APSR_Z_Pos 30U /*!< APSR: Z Position */ #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ #define APSR_C_Pos 29U /*!< APSR: C Position */ #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ #define APSR_V_Pos 28U /*!< APSR: V Position */ #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ #define APSR_Q_Pos 27U /*!< APSR: Q Position */ #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ #define APSR_GE_Pos 16U /*!< APSR: GE Position */ #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } IPSR_Type; /* IPSR Register Definitions */ #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } xPSR_Type; /* xPSR Register Definitions */ #define xPSR_N_Pos 31U /*!< xPSR: N Position */ #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ #define xPSR_C_Pos 29U /*!< xPSR: C Position */ #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ #define xPSR_V_Pos 28U /*!< xPSR: V Position */ #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ #define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ #define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ #define xPSR_T_Pos 24U /*!< xPSR: T Position */ #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ #define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ /** \brief Union type to access the Control Registers (CONTROL). */ typedef union { struct { uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } CONTROL_Type; /* CONTROL Register Definitions */ #define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ #define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ #define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ /*@} end of group CMSIS_CORE */ /** \ingroup CMSIS_core_register \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \brief Type definitions for the NVIC Registers @{ */ /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). */ typedef struct { __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ uint32_t RESERVED0[16U]; __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ uint32_t RSERVED1[16U]; __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ uint32_t RESERVED2[16U]; __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ uint32_t RESERVED3[16U]; __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ uint32_t RESERVED4[16U]; __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ uint32_t RESERVED5[16U]; __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ uint32_t RESERVED6[580U]; __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ } NVIC_Type; /* Software Triggered Interrupt Register Definitions */ #define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ /*@} end of group CMSIS_NVIC */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCB System Control Block (SCB) \brief Type definitions for the System Control Block Registers @{ */ /** \brief Structure type to access the System Control Block (SCB). */ typedef struct { __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ uint32_t RESERVED3[92U]; __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ uint32_t RESERVED4[15U]; __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ uint32_t RESERVED5[1U]; __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ uint32_t RESERVED6[1U]; __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ uint32_t RESERVED7[6U]; __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ uint32_t RESERVED8[1U]; __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ } SCB_Type; /* SCB CPUID Register Definitions */ #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ #define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ #define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ #define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ /* SCB Vector Table Offset Register Definitions */ #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ /* SCB Application Interrupt and Reset Control Register Definitions */ #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ #define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ #define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ #define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ #define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ #define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ #define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ /* SCB System Control Register Definitions */ #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ #define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ #define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ /* SCB Configuration Control Register Definitions */ #define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ #define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ #define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ #define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ #define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ /* SCB System Handler Control and State Register Definitions */ #define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ #define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ #define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ #define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ #define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ #define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ #define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ #define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ #define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ #define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ #define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ #define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ /* SCB Configurable Fault Status Register Definitions */ #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ #define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ #define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ #define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ #define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ #define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ /* BusFault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ #define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ #define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ /* SCB Hard Fault Status Register Definitions */ #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ #define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ /* SCB Debug Fault Status Register Definitions */ #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ /* SCB Non-Secure Access Control Register Definitions */ #define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ #define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ #define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ #define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ #define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ #define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ /* SCB Cache Level ID Register Definitions */ #define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ #define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ /* SCB Cache Type Register Definitions */ #define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ #define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ #define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ #define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ #define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ #define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ /* SCB Cache Size ID Register Definitions */ #define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ #define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ #define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ #define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ #define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ #define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ #define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ #define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ #define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ #define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ #define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ /* SCB Cache Size Selection Register Definitions */ #define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ #define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ /* SCB Software Triggered Interrupt Register Definitions */ #define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ #define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ /* SCB D-Cache Invalidate by Set-way Register Definitions */ #define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ #define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ #define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ #define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ /* SCB D-Cache Clean by Set-way Register Definitions */ #define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ #define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ #define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ #define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ /* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ #define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ #define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ #define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ #define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ /* Instruction Tightly-Coupled Memory Control Register Definitions */ #define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ #define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ #define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ #define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ #define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ #define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ #define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ #define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ /* Data Tightly-Coupled Memory Control Register Definitions */ #define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ #define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ #define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ #define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ #define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ #define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ #define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ #define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ /* AHBP Control Register Definitions */ #define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ #define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ #define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ #define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ /* L1 Cache Control Register Definitions */ #define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ #define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ #define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ #define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ #define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ #define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ /* AHBS Control Register Definitions */ #define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ #define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ #define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ #define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ #define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ #define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ /* Auxiliary Bus Fault Status Register Definitions */ #define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ #define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ #define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ #define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ #define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ #define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ #define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ #define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ #define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ #define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ #define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ #define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ /*@} end of group CMSIS_SCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) \brief Type definitions for the System Control and ID Register not in the SCB @{ */ /** \brief Structure type to access the System Control and ID Register not in the SCB. */ typedef struct { uint32_t RESERVED0[1U]; __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ } SCnSCB_Type; /* Interrupt Controller Type Register Definitions */ #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ /*@} end of group CMSIS_SCnotSCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SysTick System Tick Timer (SysTick) \brief Type definitions for the System Timer Registers. @{ */ /** \brief Structure type to access the System Timer (SysTick). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ } SysTick_Type; /* SysTick Control / Status Register Definitions */ #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ /*@} end of group CMSIS_SysTick */ /** \ingroup CMSIS_core_register \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) \brief Type definitions for the Instrumentation Trace Macrocell (ITM) @{ */ /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). */ typedef struct { __OM union { __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ uint32_t RESERVED0[864U]; __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ uint32_t RESERVED1[15U]; __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ uint32_t RESERVED2[15U]; __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ uint32_t RESERVED3[29U]; __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ uint32_t RESERVED4[43U]; __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ uint32_t RESERVED5[1U]; __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ uint32_t RESERVED6[4U]; __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ } ITM_Type; /* ITM Stimulus Port Register Definitions */ #define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ #define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ #define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ #define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ /* ITM Trace Privilege Register Definitions */ #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ /* ITM Trace Control Register Definitions */ #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ #define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ #define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ #define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ #define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ #define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ #define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ #define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ #define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ #define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ /* ITM Integration Write Register Definitions */ #define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ /* ITM Integration Read Register Definitions */ #define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ /* ITM Integration Mode Control Register Definitions */ #define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ /* ITM Lock Status Register Definitions */ #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ #define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ #define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ /*@}*/ /* end of group CMSIS_ITM */ /** \ingroup CMSIS_core_register \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) \brief Type definitions for the Data Watchpoint and Trace (DWT) @{ */ /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ uint32_t RESERVED1[1U]; __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ uint32_t RESERVED2[1U]; __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ uint32_t RESERVED3[1U]; __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ uint32_t RESERVED4[1U]; __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ uint32_t RESERVED5[1U]; __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ uint32_t RESERVED6[1U]; __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ uint32_t RESERVED7[1U]; __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ uint32_t RESERVED8[1U]; __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ uint32_t RESERVED9[1U]; __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ uint32_t RESERVED10[1U]; __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ uint32_t RESERVED11[1U]; __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ uint32_t RESERVED12[1U]; __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ uint32_t RESERVED13[1U]; __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ uint32_t RESERVED14[1U]; __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ uint32_t RESERVED15[1U]; __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ uint32_t RESERVED16[1U]; __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ uint32_t RESERVED17[1U]; __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ uint32_t RESERVED18[1U]; __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ uint32_t RESERVED19[1U]; __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ uint32_t RESERVED20[1U]; __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ uint32_t RESERVED21[1U]; __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ uint32_t RESERVED22[1U]; __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ uint32_t RESERVED23[1U]; __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ uint32_t RESERVED24[1U]; __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ uint32_t RESERVED25[1U]; __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ uint32_t RESERVED26[1U]; __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ uint32_t RESERVED27[1U]; __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ uint32_t RESERVED28[1U]; __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ uint32_t RESERVED29[1U]; __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ uint32_t RESERVED30[1U]; __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ uint32_t RESERVED31[1U]; __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ uint32_t RESERVED32[934U]; __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ uint32_t RESERVED33[1U]; __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ } DWT_Type; /* DWT Control Register Definitions */ #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ #define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ #define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ /* DWT CPI Count Register Definitions */ #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ /* DWT Exception Overhead Count Register Definitions */ #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ /* DWT Sleep Count Register Definitions */ #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ /* DWT LSU Count Register Definitions */ #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ /* DWT Folded-instruction Count Register Definitions */ #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ /* DWT Comparator Function Register Definitions */ #define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ #define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ #define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ #define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ #define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ #define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ /*@}*/ /* end of group CMSIS_DWT */ /** \ingroup CMSIS_core_register \defgroup CMSIS_TPI Trace Port Interface (TPI) \brief Type definitions for the Trace Port Interface (TPI) @{ */ /** \brief Structure type to access the Trace Port Interface Register (TPI). */ typedef struct { __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ uint32_t RESERVED0[2U]; __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ uint32_t RESERVED1[55U]; __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ uint32_t RESERVED2[131U]; __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ uint32_t RESERVED3[759U]; __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ uint32_t RESERVED4[1U]; __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ uint32_t RESERVED5[39U]; __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ uint32_t RESERVED7[8U]; __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ } TPI_Type; /* TPI Asynchronous Clock Prescaler Register Definitions */ #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ /* TPI Selected Pin Protocol Register Definitions */ #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ /* TPI Formatter and Flush Status Register Definitions */ #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ /* TPI Formatter and Flush Control Register Definitions */ #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ /* TPI TRIGGER Register Definitions */ #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ /* TPI Integration ETM Data Register Definitions (FIFO0) */ #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ /* TPI ITATBCTR2 Register Definitions */ #define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ /* TPI Integration ITM Data Register Definitions (FIFO1) */ #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ /* TPI ITATBCTR0 Register Definitions */ #define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ /* TPI Integration Mode Control Register Definitions */ #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ /* TPI DEVID Register Definitions */ #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ /* TPI DEVTYPE Register Definitions */ #define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ #define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ /*@}*/ /* end of group CMSIS_TPI */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) /** \ingroup CMSIS_core_register \defgroup CMSIS_MPU Memory Protection Unit (MPU) \brief Type definitions for the Memory Protection Unit (MPU) @{ */ /** \brief Structure type to access the Memory Protection Unit (MPU). */ typedef struct { __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ uint32_t RESERVED0[1]; union { __IOM uint32_t MAIR[2]; struct { __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ }; }; } MPU_Type; #define MPU_TYPE_RALIASES 4U /* MPU Type Register Definitions */ #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ /* MPU Control Register Definitions */ #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ /* MPU Region Number Register Definitions */ #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ /* MPU Region Base Address Register Definitions */ #define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ #define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ #define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ #define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ #define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ #define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ #define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ /* MPU Region Limit Address Register Definitions */ #define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ #define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ #define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ #define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ #define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ #define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ /* MPU Memory Attribute Indirection Register 0 Definitions */ #define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ #define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ #define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ #define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ #define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ #define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ #define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ #define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ /* MPU Memory Attribute Indirection Register 1 Definitions */ #define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ #define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ #define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ #define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ #define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ #define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ #define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ #define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ /*@} end of group CMSIS_MPU */ #endif #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \ingroup CMSIS_core_register \defgroup CMSIS_SAU Security Attribution Unit (SAU) \brief Type definitions for the Security Attribution Unit (SAU) @{ */ /** \brief Structure type to access the Security Attribution Unit (SAU). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ #else uint32_t RESERVED0[3]; #endif __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ } SAU_Type; /* SAU Control Register Definitions */ #define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ #define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ #define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ #define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ /* SAU Type Register Definitions */ #define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ #define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) /* SAU Region Number Register Definitions */ #define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ #define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ /* SAU Region Base Address Register Definitions */ #define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ #define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ /* SAU Region Limit Address Register Definitions */ #define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ #define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ #define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ #define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ #define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ #define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ /* Secure Fault Status Register Definitions */ #define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ #define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ #define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ #define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ #define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ #define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ #define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ #define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ #define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ #define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ #define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ #define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ #define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ #define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ #define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ #define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ /*@} end of group CMSIS_SAU */ #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /** \ingroup CMSIS_core_register \defgroup CMSIS_FPU Floating Point Unit (FPU) \brief Type definitions for the Floating Point Unit (FPU) @{ */ /** \brief Structure type to access the Floating Point Unit (FPU). */ typedef struct { uint32_t RESERVED0[1U]; __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ } FPU_Type; /* Floating-Point Context Control Register Definitions */ #define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ #define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ #define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ #define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ #define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ #define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ #define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ #define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ #define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ #define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ #define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ #define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ #define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ #define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ #define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ #define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ #define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ #define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ #define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ #define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ #define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ #define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ #define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ #define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ #define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ /* Floating-Point Context Address Register Definitions */ #define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ /* Floating-Point Default Status Control Register Definitions */ #define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ #define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ #define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ #define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ /* Media and FP Feature Register 0 Definitions */ #define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ #define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ #define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ #define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ #define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ #define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ #define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ #define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ /* Media and FP Feature Register 1 Definitions */ #define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ #define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ #define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ #define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ /*@} end of group CMSIS_FPU */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \brief Type definitions for the Core Debug Registers @{ */ /** \brief Structure type to access the Core Debug Register (CoreDebug). */ typedef struct { __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ uint32_t RESERVED4[1U]; __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ } CoreDebug_Type; /* Debug Halting Control and Status Register Definitions */ #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ /* Debug Core Register Selector Register Definitions */ #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ /* Debug Exception and Monitor Control Register Definitions */ #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ /* Debug Authentication Control Register Definitions */ #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ #define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ #define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ #define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ #define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ /* Debug Security Control and Status Register Definitions */ #define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ #define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ #define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ #define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ #define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ #define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ /*@} end of group CMSIS_CoreDebug */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_bitfield Core register bit field macros \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). @{ */ /** \brief Mask and shift a bit field value for use in a register bit range. \param[in] field Name of the register bit field. \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. \return Masked and shifted value. */ #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) /** \brief Mask and shift a register value to extract a bit filed value. \param[in] field Name of the register bit field. \param[in] value Value of register. This parameter is interpreted as an uint32_t type. \return Masked and shifted bit field value. */ #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) /*@} end of group CMSIS_core_bitfield */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_base Core Definitions \brief Definitions for base addresses, unions, and structures. @{ */ /* Memory mapping of Core Hardware */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ #endif #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ #endif #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ #endif #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /*@} */ /******************************************************************************* * Hardware Abstraction Layer Core Function Interface contains: - Core NVIC Functions - Core SysTick Functions - Core Debug Functions - Core Register Access Functions ******************************************************************************/ /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference */ /* ########################## NVIC functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_NVICFunctions NVIC Functions \brief Functions that manage interrupts and exceptions via the NVIC. @{ */ #ifdef CMSIS_NVIC_VIRTUAL #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" #endif #include CMSIS_NVIC_VIRTUAL_HEADER_FILE #else #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping #define NVIC_EnableIRQ __NVIC_EnableIRQ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ #define NVIC_DisableIRQ __NVIC_DisableIRQ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ #define NVIC_GetActive __NVIC_GetActive #define NVIC_SetPriority __NVIC_SetPriority #define NVIC_GetPriority __NVIC_GetPriority #define NVIC_SystemReset __NVIC_SystemReset #endif /* CMSIS_NVIC_VIRTUAL */ #ifdef CMSIS_VECTAB_VIRTUAL #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" #endif #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE #else #define NVIC_SetVector __NVIC_SetVector #define NVIC_GetVector __NVIC_GetVector #endif /* (CMSIS_VECTAB_VIRTUAL) */ #define NVIC_USER_IRQ_OFFSET 16 /** \brief Set Priority Grouping \details Sets the priority grouping field using the required unlock sequence. The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ reg_value = SCB->AIRCR; /* read old register configuration */ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ SCB->AIRCR = reg_value; } /** \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); } /** \brief Enable Interrupt \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Interrupt Enable status \details Returns a device specific interrupt enable status from the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt is not enabled. \return 1 Interrupt is enabled. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Disable Interrupt \details Disables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __DSB(); __ISB(); } } /** \brief Get Pending Interrupt \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Pending Interrupt \details Sets the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Clear Pending Interrupt \details Clears the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Active Interrupt \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not active. \return 1 Interrupt status is active. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief Get Interrupt Target State \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 if interrupt is assigned to Secure \return 1 if interrupt is assigned to Non Secure \note IRQn must not be negative. */ __STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Interrupt Target State \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 if interrupt is assigned to Secure 1 if interrupt is assigned to Non Secure \note IRQn must not be negative. */ __STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Clear Interrupt Target State \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 if interrupt is assigned to Secure 1 if interrupt is assigned to Non Secure \note IRQn must not be negative. */ __STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /** \brief Set Interrupt Priority \details Sets the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) { NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } else { SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } /** \brief Get Interrupt Priority \details Reads the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); } else { return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); } } /** \brief Encode Priority \details Encodes the priority for an interrupt with the given priority group, preemptive priority value, and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Used priority group. \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) ); } /** \brief Decode Priority \details Decodes an interrupt priority value with a given priority group to preemptive priority value and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). \param [in] PriorityGroup Used priority group. \param [out] pPreemptPriority Preemptive priority value (starting from 0). \param [out] pSubPriority Subpriority value (starting from 0). */ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); } /** \brief Set Interrupt Vector \details Sets an interrupt vector in SRAM based interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. VTOR must been relocated to SRAM before. \param [in] IRQn Interrupt number \param [in] vector Address of interrupt handler function */ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { uint32_t *vectors = (uint32_t *)SCB->VTOR; vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; } /** \brief Get Interrupt Vector \details Reads an interrupt vector from interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Address of interrupt handler function */ __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) { uint32_t *vectors = (uint32_t *)SCB->VTOR; return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; } /** \brief System Reset \details Initiates a system reset request to reset the MCU. */ __STATIC_INLINE void __NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ __DSB(); /* Ensure completion of memory access */ for(;;) /* wait until reset */ { __NOP(); } } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief Set Priority Grouping (non-secure) \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) { uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ reg_value = SCB_NS->AIRCR; /* read old register configuration */ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ SCB_NS->AIRCR = reg_value; } /** \brief Get Priority Grouping (non-secure) \details Reads the priority grouping field from the non-secure NVIC when in secure state. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) { return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); } /** \brief Enable Interrupt (non-secure) \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Interrupt Enable status (non-secure) \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt is not enabled. \return 1 Interrupt is enabled. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Disable Interrupt (non-secure) \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Pending Interrupt (non-secure) \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Pending Interrupt (non-secure) \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Clear Pending Interrupt (non-secure) \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Active Interrupt (non-secure) \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not active. \return 1 Interrupt status is active. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Interrupt Priority (non-secure) \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every non-secure processor exception. */ __STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } else { SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } /** \brief Get Interrupt Priority (non-secure) \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); } else { return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); } } #endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ /*@} end of CMSIS_Core_NVICFunctions */ /* ########################## MPU functions #################################### */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #include "mpu_armv8.h" #endif /* ########################## FPU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_FpuFunctions FPU Functions \brief Function that provides FPU type. @{ */ /** \brief get FPU type \details returns the FPU type \returns - \b 0: No FPU - \b 1: Single precision FPU - \b 2: Double + Single precision FPU */ __STATIC_INLINE uint32_t SCB_GetFPUType(void) { uint32_t mvfr0; mvfr0 = FPU->MVFR0; if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) { return 2U; /* Double + Single precision FPU */ } else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) { return 1U; /* Single precision FPU */ } else { return 0U; /* No FPU */ } } /*@} end of CMSIS_Core_FpuFunctions */ /* ########################## SAU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SAUFunctions SAU Functions \brief Functions that configure the SAU. @{ */ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief Enable SAU \details Enables the Security Attribution Unit (SAU). */ __STATIC_INLINE void TZ_SAU_Enable(void) { SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); } /** \brief Disable SAU \details Disables the Security Attribution Unit (SAU). */ __STATIC_INLINE void TZ_SAU_Disable(void) { SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); } #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /*@} end of CMSIS_Core_SAUFunctions */ /* ################################## SysTick function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SysTickFunctions SysTick Functions \brief Functions that configure the System. @{ */ #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) /** \brief System Tick Configuration \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief System Tick Configuration (non-secure) \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b> must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ #endif /*@} end of CMSIS_Core_SysTickFunctions */ /* ##################################### Debug In/Output function ########################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_core_DebugFunctions ITM Functions \brief Functions that access the ITM debug interface. @{ */ extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ /** \brief ITM Send Character \details Transmits a character via the ITM channel 0, and \li Just returns when no debugger is connected that has booked the output. \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. \param [in] ch Character to transmit. \returns Character to transmit. */ __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) { if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ { while (ITM->PORT[0U].u32 == 0UL) { __NOP(); } ITM->PORT[0U].u8 = (uint8_t)ch; } return (ch); } /** \brief ITM Receive Character \details Inputs a character via the external variable \ref ITM_RxBuffer. \return Received character. \return -1 No character pending. */ __STATIC_INLINE int32_t ITM_ReceiveChar (void) { int32_t ch = -1; /* no character available */ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { ch = ITM_RxBuffer; ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ } return (ch); } /** \brief ITM Check Character \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. \return 0 No character available. \return 1 Character available. */ __STATIC_INLINE int32_t ITM_CheckChar (void) { if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { return (0); /* no character available */ } else { return (1); /* character available */ } } /*@} end of CMSIS_core_DebugFunctions */ #ifdef __cplusplus } #endif #endif /* __CORE_ARMV8MML_H_DEPENDANT */ #endif /* __CMSIS_GENERIC */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/CMSIS/Include/core_cm0.h.
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/**************************************************************************//** * @file core_cm0.h * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File * @version V5.0.3 * @date 10. January 2018 ******************************************************************************/ /* * Copyright (c) 2009-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__clang__) #pragma clang system_header /* treat file as system include file */ #endif #ifndef __CORE_CM0_H_GENERIC #define __CORE_CM0_H_GENERIC #include <stdint.h> #ifdef __cplusplus extern "C" { #endif /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions CMSIS violates the following MISRA-C:2004 rules: \li Required Rule 8.5, object/function definition in header file.<br> Function definitions in header files are used to allow 'inlining'. \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br> Unions are used for effective representation of core registers. \li Advisory Rule 19.7, Function-like macro defined.<br> Function-like macros are used to allow more efficient code. */ /******************************************************************************* * CMSIS definitions ******************************************************************************/ /** \ingroup Cortex_M0 @{ */ #include "cmsis_version.h" /* CMSIS CM0 definitions */ #define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ #define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ #define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ __CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ #define __CORTEX_M (0U) /*!< Cortex-M Core */ /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all */ #define __FPU_USED 0U #if defined ( __CC_ARM ) #if defined __TARGET_FPU_VFP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #if defined __ARM_PCS_VFP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __GNUC__ ) #if defined (__VFP_FP__) && !defined(__SOFTFP__) #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __ICCARM__ ) #if defined __ARMVFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __TI_ARM__ ) #if defined __TI_VFP_SUPPORT__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __TASKING__ ) #if defined __FPU_VFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __CSMC__ ) #if ( __CSMC__ & 0x400U) #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #endif #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ #ifdef __cplusplus } #endif #endif /* __CORE_CM0_H_GENERIC */ #ifndef __CMSIS_GENERIC #ifndef __CORE_CM0_H_DEPENDANT #define __CORE_CM0_H_DEPENDANT #ifdef __cplusplus extern "C" { #endif /* check device defines and use defaults */ #if defined __CHECK_DEVICE_DEFINES #ifndef __CM0_REV #define __CM0_REV 0x0000U #warning "__CM0_REV not defined in device header file; using default!" #endif #ifndef __NVIC_PRIO_BITS #define __NVIC_PRIO_BITS 2U #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" #endif #ifndef __Vendor_SysTickConfig #define __Vendor_SysTickConfig 0U #warning "__Vendor_SysTickConfig not defined in device header file; using default!" #endif #endif /* IO definitions (access restrictions to peripheral registers) */ /** \defgroup CMSIS_glob_defs CMSIS Global Defines <strong>IO Type Qualifiers</strong> are used \li to specify the access to peripheral variables. \li for automatic generation of peripheral register debug information. */ #ifdef __cplusplus #define __I volatile /*!< Defines 'read only' permissions */ #else #define __I volatile const /*!< Defines 'read only' permissions */ #endif #define __O volatile /*!< Defines 'write only' permissions */ #define __IO volatile /*!< Defines 'read / write' permissions */ /* following defines should be used for structure members */ #define __IM volatile const /*! Defines 'read only' structure member permissions */ #define __OM volatile /*! Defines 'write only' structure member permissions */ #define __IOM volatile /*! Defines 'read / write' structure member permissions */ /*@} end of group Cortex_M0 */ /******************************************************************************* * Register Abstraction Core Register contain: - Core Register - Core NVIC Register - Core SCB Register - Core SysTick Register ******************************************************************************/ /** \defgroup CMSIS_core_register Defines and Type Definitions \brief Type definitions and defines for Cortex-M processor based devices. */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CORE Status and Control Registers \brief Core Register type definitions. @{ */ /** \brief Union type to access the Application Program Status Register (APSR). */ typedef union { struct { uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } APSR_Type; /* APSR Register Definitions */ #define APSR_N_Pos 31U /*!< APSR: N Position */ #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ #define APSR_Z_Pos 30U /*!< APSR: Z Position */ #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ #define APSR_C_Pos 29U /*!< APSR: C Position */ #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ #define APSR_V_Pos 28U /*!< APSR: V Position */ #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } IPSR_Type; /* IPSR Register Definitions */ #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } xPSR_Type; /* xPSR Register Definitions */ #define xPSR_N_Pos 31U /*!< xPSR: N Position */ #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ #define xPSR_C_Pos 29U /*!< xPSR: C Position */ #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ #define xPSR_V_Pos 28U /*!< xPSR: V Position */ #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ #define xPSR_T_Pos 24U /*!< xPSR: T Position */ #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ /** \brief Union type to access the Control Registers (CONTROL). */ typedef union { struct { uint32_t _reserved0:1; /*!< bit: 0 Reserved */ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } CONTROL_Type; /* CONTROL Register Definitions */ #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ /*@} end of group CMSIS_CORE */ /** \ingroup CMSIS_core_register \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \brief Type definitions for the NVIC Registers @{ */ /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). */ typedef struct { __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ uint32_t RESERVED0[31U]; __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ uint32_t RSERVED1[31U]; __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ uint32_t RESERVED2[31U]; __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ uint32_t RESERVED3[31U]; uint32_t RESERVED4[64U]; __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ } NVIC_Type; /*@} end of group CMSIS_NVIC */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCB System Control Block (SCB) \brief Type definitions for the System Control Block Registers @{ */ /** \brief Structure type to access the System Control Block (SCB). */ typedef struct { __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ uint32_t RESERVED0; __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ uint32_t RESERVED1; __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ } SCB_Type; /* SCB CPUID Register Definitions */ #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ /* SCB Application Interrupt and Reset Control Register Definitions */ #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ /* SCB System Control Register Definitions */ #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ /* SCB Configuration Control Register Definitions */ #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ /* SCB System Handler Control and State Register Definitions */ #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ /*@} end of group CMSIS_SCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SysTick System Tick Timer (SysTick) \brief Type definitions for the System Timer Registers. @{ */ /** \brief Structure type to access the System Timer (SysTick). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ } SysTick_Type; /* SysTick Control / Status Register Definitions */ #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ /*@} end of group CMSIS_SysTick */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. Therefore they are not covered by the Cortex-M0 header file. @{ */ /*@} end of group CMSIS_CoreDebug */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_bitfield Core register bit field macros \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). @{ */ /** \brief Mask and shift a bit field value for use in a register bit range. \param[in] field Name of the register bit field. \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. \return Masked and shifted value. */ #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) /** \brief Mask and shift a register value to extract a bit filed value. \param[in] field Name of the register bit field. \param[in] value Value of register. This parameter is interpreted as an uint32_t type. \return Masked and shifted bit field value. */ #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) /*@} end of group CMSIS_core_bitfield */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_base Core Definitions \brief Definitions for base addresses, unions, and structures. @{ */ /* Memory mapping of Core Hardware */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ /*@} */ /******************************************************************************* * Hardware Abstraction Layer Core Function Interface contains: - Core NVIC Functions - Core SysTick Functions - Core Register Access Functions ******************************************************************************/ /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference */ /* ########################## NVIC functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_NVICFunctions NVIC Functions \brief Functions that manage interrupts and exceptions via the NVIC. @{ */ #ifdef CMSIS_NVIC_VIRTUAL #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" #endif #include CMSIS_NVIC_VIRTUAL_HEADER_FILE #else /*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M0 */ /*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M0 */ #define NVIC_EnableIRQ __NVIC_EnableIRQ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ #define NVIC_DisableIRQ __NVIC_DisableIRQ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ /*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */ #define NVIC_SetPriority __NVIC_SetPriority #define NVIC_GetPriority __NVIC_GetPriority #define NVIC_SystemReset __NVIC_SystemReset #endif /* CMSIS_NVIC_VIRTUAL */ #ifdef CMSIS_VECTAB_VIRTUAL #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" #endif #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE #else #define NVIC_SetVector __NVIC_SetVector #define NVIC_GetVector __NVIC_GetVector #endif /* (CMSIS_VECTAB_VIRTUAL) */ #define NVIC_USER_IRQ_OFFSET 16 /* Interrupt Priorities are WORD accessible only under Armv6-M */ /* The following MACROS handle generation of the register offset and byte masks */ #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) /** \brief Enable Interrupt \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Interrupt Enable status \details Returns a device specific interrupt enable status from the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt is not enabled. \return 1 Interrupt is enabled. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Disable Interrupt \details Disables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __DSB(); __ISB(); } } /** \brief Get Pending Interrupt \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Pending Interrupt \details Sets the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Clear Pending Interrupt \details Clears the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Set Interrupt Priority \details Sets the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) { NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } else { SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } } /** \brief Get Interrupt Priority \details Reads the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); } else { return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); } } /** \brief Set Interrupt Vector \details Sets an interrupt vector in SRAM based interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. Address 0 must be mapped to SRAM. \param [in] IRQn Interrupt number \param [in] vector Address of interrupt handler function */ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { uint32_t *vectors = (uint32_t *)0x0U; vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; } /** \brief Get Interrupt Vector \details Reads an interrupt vector from interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Address of interrupt handler function */ __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) { uint32_t *vectors = (uint32_t *)0x0U; return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; } /** \brief System Reset \details Initiates a system reset request to reset the MCU. */ __STATIC_INLINE void __NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | SCB_AIRCR_SYSRESETREQ_Msk); __DSB(); /* Ensure completion of memory access */ for(;;) /* wait until reset */ { __NOP(); } } /*@} end of CMSIS_Core_NVICFunctions */ /* ########################## FPU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_FpuFunctions FPU Functions \brief Function that provides FPU type. @{ */ /** \brief get FPU type \details returns the FPU type \returns - \b 0: No FPU - \b 1: Single precision FPU - \b 2: Double + Single precision FPU */ __STATIC_INLINE uint32_t SCB_GetFPUType(void) { return 0U; /* No FPU */ } /*@} end of CMSIS_Core_FpuFunctions */ /* ################################## SysTick function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SysTickFunctions SysTick Functions \brief Functions that configure the System. @{ */ #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) /** \brief System Tick Configuration \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #endif /*@} end of CMSIS_Core_SysTickFunctions */ #ifdef __cplusplus } #endif #endif /* __CORE_CM0_H_DEPENDANT */ #endif /* __CMSIS_GENERIC */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/CMSIS/Include/core_cm0plus.h.
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/**************************************************************************//** * @file core_cm0plus.h * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File * @version V5.0.4 * @date 10. January 2018 ******************************************************************************/ /* * Copyright (c) 2009-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__clang__) #pragma clang system_header /* treat file as system include file */ #endif #ifndef __CORE_CM0PLUS_H_GENERIC #define __CORE_CM0PLUS_H_GENERIC #include <stdint.h> #ifdef __cplusplus extern "C" { #endif /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions CMSIS violates the following MISRA-C:2004 rules: \li Required Rule 8.5, object/function definition in header file.<br> Function definitions in header files are used to allow 'inlining'. \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br> Unions are used for effective representation of core registers. \li Advisory Rule 19.7, Function-like macro defined.<br> Function-like macros are used to allow more efficient code. */ /******************************************************************************* * CMSIS definitions ******************************************************************************/ /** \ingroup Cortex-M0+ @{ */ #include "cmsis_version.h" /* CMSIS CM0+ definitions */ #define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ #define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ #define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ __CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ #define __CORTEX_M (0U) /*!< Cortex-M Core */ /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all */ #define __FPU_USED 0U #if defined ( __CC_ARM ) #if defined __TARGET_FPU_VFP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #if defined __ARM_PCS_VFP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __GNUC__ ) #if defined (__VFP_FP__) && !defined(__SOFTFP__) #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __ICCARM__ ) #if defined __ARMVFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __TI_ARM__ ) #if defined __TI_VFP_SUPPORT__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __TASKING__ ) #if defined __FPU_VFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __CSMC__ ) #if ( __CSMC__ & 0x400U) #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #endif #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ #ifdef __cplusplus } #endif #endif /* __CORE_CM0PLUS_H_GENERIC */ #ifndef __CMSIS_GENERIC #ifndef __CORE_CM0PLUS_H_DEPENDANT #define __CORE_CM0PLUS_H_DEPENDANT #ifdef __cplusplus extern "C" { #endif /* check device defines and use defaults */ #if defined __CHECK_DEVICE_DEFINES #ifndef __CM0PLUS_REV #define __CM0PLUS_REV 0x0000U #warning "__CM0PLUS_REV not defined in device header file; using default!" #endif #ifndef __MPU_PRESENT #define __MPU_PRESENT 0U #warning "__MPU_PRESENT not defined in device header file; using default!" #endif #ifndef __VTOR_PRESENT #define __VTOR_PRESENT 0U #warning "__VTOR_PRESENT not defined in device header file; using default!" #endif #ifndef __NVIC_PRIO_BITS #define __NVIC_PRIO_BITS 2U #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" #endif #ifndef __Vendor_SysTickConfig #define __Vendor_SysTickConfig 0U #warning "__Vendor_SysTickConfig not defined in device header file; using default!" #endif #endif /* IO definitions (access restrictions to peripheral registers) */ /** \defgroup CMSIS_glob_defs CMSIS Global Defines <strong>IO Type Qualifiers</strong> are used \li to specify the access to peripheral variables. \li for automatic generation of peripheral register debug information. */ #ifdef __cplusplus #define __I volatile /*!< Defines 'read only' permissions */ #else #define __I volatile const /*!< Defines 'read only' permissions */ #endif #define __O volatile /*!< Defines 'write only' permissions */ #define __IO volatile /*!< Defines 'read / write' permissions */ /* following defines should be used for structure members */ #define __IM volatile const /*! Defines 'read only' structure member permissions */ #define __OM volatile /*! Defines 'write only' structure member permissions */ #define __IOM volatile /*! Defines 'read / write' structure member permissions */ /*@} end of group Cortex-M0+ */ /******************************************************************************* * Register Abstraction Core Register contain: - Core Register - Core NVIC Register - Core SCB Register - Core SysTick Register - Core MPU Register ******************************************************************************/ /** \defgroup CMSIS_core_register Defines and Type Definitions \brief Type definitions and defines for Cortex-M processor based devices. */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CORE Status and Control Registers \brief Core Register type definitions. @{ */ /** \brief Union type to access the Application Program Status Register (APSR). */ typedef union { struct { uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } APSR_Type; /* APSR Register Definitions */ #define APSR_N_Pos 31U /*!< APSR: N Position */ #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ #define APSR_Z_Pos 30U /*!< APSR: Z Position */ #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ #define APSR_C_Pos 29U /*!< APSR: C Position */ #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ #define APSR_V_Pos 28U /*!< APSR: V Position */ #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } IPSR_Type; /* IPSR Register Definitions */ #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } xPSR_Type; /* xPSR Register Definitions */ #define xPSR_N_Pos 31U /*!< xPSR: N Position */ #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ #define xPSR_C_Pos 29U /*!< xPSR: C Position */ #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ #define xPSR_V_Pos 28U /*!< xPSR: V Position */ #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ #define xPSR_T_Pos 24U /*!< xPSR: T Position */ #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ /** \brief Union type to access the Control Registers (CONTROL). */ typedef union { struct { uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } CONTROL_Type; /* CONTROL Register Definitions */ #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ /*@} end of group CMSIS_CORE */ /** \ingroup CMSIS_core_register \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \brief Type definitions for the NVIC Registers @{ */ /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). */ typedef struct { __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ uint32_t RESERVED0[31U]; __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ uint32_t RSERVED1[31U]; __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ uint32_t RESERVED2[31U]; __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ uint32_t RESERVED3[31U]; uint32_t RESERVED4[64U]; __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ } NVIC_Type; /*@} end of group CMSIS_NVIC */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCB System Control Block (SCB) \brief Type definitions for the System Control Block Registers @{ */ /** \brief Structure type to access the System Control Block (SCB). */ typedef struct { __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ #else uint32_t RESERVED0; #endif __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ uint32_t RESERVED1; __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ } SCB_Type; /* SCB CPUID Register Definitions */ #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) /* SCB Interrupt Control State Register Definitions */ #define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ #define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ #endif /* SCB Application Interrupt and Reset Control Register Definitions */ #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ /* SCB System Control Register Definitions */ #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ /* SCB Configuration Control Register Definitions */ #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ /* SCB System Handler Control and State Register Definitions */ #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ /*@} end of group CMSIS_SCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SysTick System Tick Timer (SysTick) \brief Type definitions for the System Timer Registers. @{ */ /** \brief Structure type to access the System Timer (SysTick). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ } SysTick_Type; /* SysTick Control / Status Register Definitions */ #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ /*@} end of group CMSIS_SysTick */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) /** \ingroup CMSIS_core_register \defgroup CMSIS_MPU Memory Protection Unit (MPU) \brief Type definitions for the Memory Protection Unit (MPU) @{ */ /** \brief Structure type to access the Memory Protection Unit (MPU). */ typedef struct { __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ } MPU_Type; #define MPU_TYPE_RALIASES 1U /* MPU Type Register Definitions */ #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ /* MPU Control Register Definitions */ #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ /* MPU Region Number Register Definitions */ #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ /* MPU Region Base Address Register Definitions */ #define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ /* MPU Region Attribute and Size Register Definitions */ #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ /*@} end of group CMSIS_MPU */ #endif /** \ingroup CMSIS_core_register \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. Therefore they are not covered by the Cortex-M0+ header file. @{ */ /*@} end of group CMSIS_CoreDebug */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_bitfield Core register bit field macros \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). @{ */ /** \brief Mask and shift a bit field value for use in a register bit range. \param[in] field Name of the register bit field. \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. \return Masked and shifted value. */ #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) /** \brief Mask and shift a register value to extract a bit filed value. \param[in] field Name of the register bit field. \param[in] value Value of register. This parameter is interpreted as an uint32_t type. \return Masked and shifted bit field value. */ #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) /*@} end of group CMSIS_core_bitfield */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_base Core Definitions \brief Definitions for base addresses, unions, and structures. @{ */ /* Memory mapping of Core Hardware */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ #endif /*@} */ /******************************************************************************* * Hardware Abstraction Layer Core Function Interface contains: - Core NVIC Functions - Core SysTick Functions - Core Register Access Functions ******************************************************************************/ /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference */ /* ########################## NVIC functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_NVICFunctions NVIC Functions \brief Functions that manage interrupts and exceptions via the NVIC. @{ */ #ifdef CMSIS_NVIC_VIRTUAL #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" #endif #include CMSIS_NVIC_VIRTUAL_HEADER_FILE #else /*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M0+ */ /*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M0+ */ #define NVIC_EnableIRQ __NVIC_EnableIRQ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ #define NVIC_DisableIRQ __NVIC_DisableIRQ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ /*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */ #define NVIC_SetPriority __NVIC_SetPriority #define NVIC_GetPriority __NVIC_GetPriority #define NVIC_SystemReset __NVIC_SystemReset #endif /* CMSIS_NVIC_VIRTUAL */ #ifdef CMSIS_VECTAB_VIRTUAL #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" #endif #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE #else #define NVIC_SetVector __NVIC_SetVector #define NVIC_GetVector __NVIC_GetVector #endif /* (CMSIS_VECTAB_VIRTUAL) */ #define NVIC_USER_IRQ_OFFSET 16 /* Interrupt Priorities are WORD accessible only under Armv6-M */ /* The following MACROS handle generation of the register offset and byte masks */ #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) /** \brief Enable Interrupt \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Interrupt Enable status \details Returns a device specific interrupt enable status from the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt is not enabled. \return 1 Interrupt is enabled. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Disable Interrupt \details Disables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __DSB(); __ISB(); } } /** \brief Get Pending Interrupt \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Pending Interrupt \details Sets the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Clear Pending Interrupt \details Clears the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Set Interrupt Priority \details Sets the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) { NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } else { SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } } /** \brief Get Interrupt Priority \details Reads the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); } else { return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); } } /** \brief Set Interrupt Vector \details Sets an interrupt vector in SRAM based interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. VTOR must been relocated to SRAM before. If VTOR is not present address 0 must be mapped to SRAM. \param [in] IRQn Interrupt number \param [in] vector Address of interrupt handler function */ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) uint32_t *vectors = (uint32_t *)SCB->VTOR; #else uint32_t *vectors = (uint32_t *)0x0U; #endif vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; } /** \brief Get Interrupt Vector \details Reads an interrupt vector from interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Address of interrupt handler function */ __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) { #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) uint32_t *vectors = (uint32_t *)SCB->VTOR; #else uint32_t *vectors = (uint32_t *)0x0U; #endif return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; } /** \brief System Reset \details Initiates a system reset request to reset the MCU. */ __STATIC_INLINE void __NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | SCB_AIRCR_SYSRESETREQ_Msk); __DSB(); /* Ensure completion of memory access */ for(;;) /* wait until reset */ { __NOP(); } } /*@} end of CMSIS_Core_NVICFunctions */ /* ########################## MPU functions #################################### */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #include "mpu_armv7.h" #endif /* ########################## FPU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_FpuFunctions FPU Functions \brief Function that provides FPU type. @{ */ /** \brief get FPU type \details returns the FPU type \returns - \b 0: No FPU - \b 1: Single precision FPU - \b 2: Double + Single precision FPU */ __STATIC_INLINE uint32_t SCB_GetFPUType(void) { return 0U; /* No FPU */ } /*@} end of CMSIS_Core_FpuFunctions */ /* ################################## SysTick function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SysTickFunctions SysTick Functions \brief Functions that configure the System. @{ */ #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) /** \brief System Tick Configuration \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #endif /*@} end of CMSIS_Core_SysTickFunctions */ #ifdef __cplusplus } #endif #endif /* __CORE_CM0PLUS_H_DEPENDANT */ #endif /* __CMSIS_GENERIC */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/CMSIS/Include/core_cm23.h.
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/**************************************************************************//** * @file core_cm23.h * @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File * @version V5.0.4 * @date 10. January 2018 ******************************************************************************/ /* * Copyright (c) 2009-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__clang__) #pragma clang system_header /* treat file as system include file */ #endif #ifndef __CORE_CM23_H_GENERIC #define __CORE_CM23_H_GENERIC #include <stdint.h> #ifdef __cplusplus extern "C" { #endif /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions CMSIS violates the following MISRA-C:2004 rules: \li Required Rule 8.5, object/function definition in header file.<br> Function definitions in header files are used to allow 'inlining'. \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br> Unions are used for effective representation of core registers. \li Advisory Rule 19.7, Function-like macro defined.<br> Function-like macros are used to allow more efficient code. */ /******************************************************************************* * CMSIS definitions ******************************************************************************/ /** \ingroup Cortex_M23 @{ */ #include "cmsis_version.h" /* CMSIS definitions */ #define __CM23_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ #define __CM23_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ #define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) | \ __CM23_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ #define __CORTEX_M (23U) /*!< Cortex-M Core */ /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all */ #define __FPU_USED 0U #if defined ( __CC_ARM ) #if defined __TARGET_FPU_VFP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #if defined __ARM_PCS_VFP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __GNUC__ ) #if defined (__VFP_FP__) && !defined(__SOFTFP__) #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __ICCARM__ ) #if defined __ARMVFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __TI_ARM__ ) #if defined __TI_VFP_SUPPORT__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __TASKING__ ) #if defined __FPU_VFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __CSMC__ ) #if ( __CSMC__ & 0x400U) #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #endif #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ #ifdef __cplusplus } #endif #endif /* __CORE_CM23_H_GENERIC */ #ifndef __CMSIS_GENERIC #ifndef __CORE_CM23_H_DEPENDANT #define __CORE_CM23_H_DEPENDANT #ifdef __cplusplus extern "C" { #endif /* check device defines and use defaults */ #if defined __CHECK_DEVICE_DEFINES #ifndef __CM23_REV #define __CM23_REV 0x0000U #warning "__CM23_REV not defined in device header file; using default!" #endif #ifndef __FPU_PRESENT #define __FPU_PRESENT 0U #warning "__FPU_PRESENT not defined in device header file; using default!" #endif #ifndef __MPU_PRESENT #define __MPU_PRESENT 0U #warning "__MPU_PRESENT not defined in device header file; using default!" #endif #ifndef __SAUREGION_PRESENT #define __SAUREGION_PRESENT 0U #warning "__SAUREGION_PRESENT not defined in device header file; using default!" #endif #ifndef __VTOR_PRESENT #define __VTOR_PRESENT 0U #warning "__VTOR_PRESENT not defined in device header file; using default!" #endif #ifndef __NVIC_PRIO_BITS #define __NVIC_PRIO_BITS 2U #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" #endif #ifndef __Vendor_SysTickConfig #define __Vendor_SysTickConfig 0U #warning "__Vendor_SysTickConfig not defined in device header file; using default!" #endif #ifndef __ETM_PRESENT #define __ETM_PRESENT 0U #warning "__ETM_PRESENT not defined in device header file; using default!" #endif #ifndef __MTB_PRESENT #define __MTB_PRESENT 0U #warning "__MTB_PRESENT not defined in device header file; using default!" #endif #endif /* IO definitions (access restrictions to peripheral registers) */ /** \defgroup CMSIS_glob_defs CMSIS Global Defines <strong>IO Type Qualifiers</strong> are used \li to specify the access to peripheral variables. \li for automatic generation of peripheral register debug information. */ #ifdef __cplusplus #define __I volatile /*!< Defines 'read only' permissions */ #else #define __I volatile const /*!< Defines 'read only' permissions */ #endif #define __O volatile /*!< Defines 'write only' permissions */ #define __IO volatile /*!< Defines 'read / write' permissions */ /* following defines should be used for structure members */ #define __IM volatile const /*! Defines 'read only' structure member permissions */ #define __OM volatile /*! Defines 'write only' structure member permissions */ #define __IOM volatile /*! Defines 'read / write' structure member permissions */ /*@} end of group Cortex_M23 */ /******************************************************************************* * Register Abstraction Core Register contain: - Core Register - Core NVIC Register - Core SCB Register - Core SysTick Register - Core Debug Register - Core MPU Register - Core SAU Register ******************************************************************************/ /** \defgroup CMSIS_core_register Defines and Type Definitions \brief Type definitions and defines for Cortex-M processor based devices. */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CORE Status and Control Registers \brief Core Register type definitions. @{ */ /** \brief Union type to access the Application Program Status Register (APSR). */ typedef union { struct { uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } APSR_Type; /* APSR Register Definitions */ #define APSR_N_Pos 31U /*!< APSR: N Position */ #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ #define APSR_Z_Pos 30U /*!< APSR: Z Position */ #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ #define APSR_C_Pos 29U /*!< APSR: C Position */ #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ #define APSR_V_Pos 28U /*!< APSR: V Position */ #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } IPSR_Type; /* IPSR Register Definitions */ #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } xPSR_Type; /* xPSR Register Definitions */ #define xPSR_N_Pos 31U /*!< xPSR: N Position */ #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ #define xPSR_C_Pos 29U /*!< xPSR: C Position */ #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ #define xPSR_V_Pos 28U /*!< xPSR: V Position */ #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ #define xPSR_T_Pos 24U /*!< xPSR: T Position */ #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ /** \brief Union type to access the Control Registers (CONTROL). */ typedef union { struct { uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } CONTROL_Type; /* CONTROL Register Definitions */ #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ /*@} end of group CMSIS_CORE */ /** \ingroup CMSIS_core_register \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \brief Type definitions for the NVIC Registers @{ */ /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). */ typedef struct { __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ uint32_t RESERVED0[16U]; __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ uint32_t RSERVED1[16U]; __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ uint32_t RESERVED2[16U]; __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ uint32_t RESERVED3[16U]; __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ uint32_t RESERVED4[16U]; __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ uint32_t RESERVED5[16U]; __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ } NVIC_Type; /*@} end of group CMSIS_NVIC */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCB System Control Block (SCB) \brief Type definitions for the System Control Block Registers @{ */ /** \brief Structure type to access the System Control Block (SCB). */ typedef struct { __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ #else uint32_t RESERVED0; #endif __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ uint32_t RESERVED1; __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ } SCB_Type; /* SCB CPUID Register Definitions */ #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ #define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ #define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ #define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) /* SCB Vector Table Offset Register Definitions */ #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ #endif /* SCB Application Interrupt and Reset Control Register Definitions */ #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ #define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ #define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ #define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ #define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ #define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ #define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ /* SCB System Control Register Definitions */ #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ #define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ #define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ /* SCB Configuration Control Register Definitions */ #define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ #define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ #define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ #define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ #define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ /* SCB System Handler Control and State Register Definitions */ #define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ #define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ #define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ #define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ #define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ #define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ /*@} end of group CMSIS_SCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SysTick System Tick Timer (SysTick) \brief Type definitions for the System Timer Registers. @{ */ /** \brief Structure type to access the System Timer (SysTick). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ } SysTick_Type; /* SysTick Control / Status Register Definitions */ #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ /*@} end of group CMSIS_SysTick */ /** \ingroup CMSIS_core_register \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) \brief Type definitions for the Data Watchpoint and Trace (DWT) @{ */ /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ uint32_t RESERVED0[6U]; __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ uint32_t RESERVED1[1U]; __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ uint32_t RESERVED2[1U]; __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ uint32_t RESERVED3[1U]; __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ uint32_t RESERVED4[1U]; __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ uint32_t RESERVED5[1U]; __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ uint32_t RESERVED6[1U]; __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ uint32_t RESERVED7[1U]; __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ uint32_t RESERVED8[1U]; __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ uint32_t RESERVED9[1U]; __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ uint32_t RESERVED10[1U]; __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ uint32_t RESERVED11[1U]; __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ uint32_t RESERVED12[1U]; __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ uint32_t RESERVED13[1U]; __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ uint32_t RESERVED14[1U]; __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ uint32_t RESERVED15[1U]; __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ uint32_t RESERVED16[1U]; __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ uint32_t RESERVED17[1U]; __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ uint32_t RESERVED18[1U]; __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ uint32_t RESERVED19[1U]; __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ uint32_t RESERVED20[1U]; __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ uint32_t RESERVED21[1U]; __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ uint32_t RESERVED22[1U]; __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ uint32_t RESERVED23[1U]; __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ uint32_t RESERVED24[1U]; __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ uint32_t RESERVED25[1U]; __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ uint32_t RESERVED26[1U]; __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ uint32_t RESERVED27[1U]; __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ uint32_t RESERVED28[1U]; __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ uint32_t RESERVED29[1U]; __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ uint32_t RESERVED30[1U]; __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ uint32_t RESERVED31[1U]; __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ } DWT_Type; /* DWT Control Register Definitions */ #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ /* DWT Comparator Function Register Definitions */ #define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ #define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ #define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ #define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ #define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ #define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ /*@}*/ /* end of group CMSIS_DWT */ /** \ingroup CMSIS_core_register \defgroup CMSIS_TPI Trace Port Interface (TPI) \brief Type definitions for the Trace Port Interface (TPI) @{ */ /** \brief Structure type to access the Trace Port Interface Register (TPI). */ typedef struct { __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ uint32_t RESERVED0[2U]; __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ uint32_t RESERVED1[55U]; __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ uint32_t RESERVED2[131U]; __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ uint32_t RESERVED3[759U]; __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ uint32_t RESERVED4[1U]; __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ uint32_t RESERVED5[39U]; __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ uint32_t RESERVED7[8U]; __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ } TPI_Type; /* TPI Asynchronous Clock Prescaler Register Definitions */ #define TPI_ACPR_PRESCALER_Pos 0U /*!< @Deprecated TPI ACPR: PRESCALER Position */ #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< @Deprecated TPI ACPR: PRESCALER Mask */ #define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ #define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ /* TPI Selected Pin Protocol Register Definitions */ #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ /* TPI Formatter and Flush Status Register Definitions */ #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ /* TPI Formatter and Flush Control Register Definitions */ #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ /* TPI TRIGGER Register Definitions */ #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ /* TPI Integration ETM Data Register Definitions (FIFO0) */ #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ /* TPI ITATBCTR2 Register Definitions */ #define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ /* TPI Integration ITM Data Register Definitions (FIFO1) */ #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ /* TPI ITATBCTR0 Register Definitions */ #define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ /* TPI Integration Mode Control Register Definitions */ #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ /* TPI DEVID Register Definitions */ #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ /* TPI DEVTYPE Register Definitions */ #define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ #define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ /*@}*/ /* end of group CMSIS_TPI */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) /** \ingroup CMSIS_core_register \defgroup CMSIS_MPU Memory Protection Unit (MPU) \brief Type definitions for the Memory Protection Unit (MPU) @{ */ /** \brief Structure type to access the Memory Protection Unit (MPU). */ typedef struct { __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ uint32_t RESERVED0[7U]; union { __IOM uint32_t MAIR[2]; struct { __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ }; }; } MPU_Type; #define MPU_TYPE_RALIASES 1U /* MPU Type Register Definitions */ #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ /* MPU Control Register Definitions */ #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ /* MPU Region Number Register Definitions */ #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ /* MPU Region Base Address Register Definitions */ #define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ #define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ #define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ #define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ #define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ #define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ #define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ #define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ /* MPU Region Limit Address Register Definitions */ #define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ #define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ #define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ #define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ #define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ #define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ /* MPU Memory Attribute Indirection Register 0 Definitions */ #define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ #define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ #define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ #define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ #define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ #define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ #define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ #define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ /* MPU Memory Attribute Indirection Register 1 Definitions */ #define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ #define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ #define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ #define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ #define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ #define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ #define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ #define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ /*@} end of group CMSIS_MPU */ #endif #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \ingroup CMSIS_core_register \defgroup CMSIS_SAU Security Attribution Unit (SAU) \brief Type definitions for the Security Attribution Unit (SAU) @{ */ /** \brief Structure type to access the Security Attribution Unit (SAU). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ #endif } SAU_Type; /* SAU Control Register Definitions */ #define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ #define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ #define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ #define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ /* SAU Type Register Definitions */ #define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ #define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) /* SAU Region Number Register Definitions */ #define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ #define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ /* SAU Region Base Address Register Definitions */ #define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ #define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ /* SAU Region Limit Address Register Definitions */ #define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ #define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ #define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ #define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ #define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ #define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ /*@} end of group CMSIS_SAU */ #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \brief Type definitions for the Core Debug Registers @{ */ /** \brief Structure type to access the Core Debug Register (CoreDebug). */ typedef struct { __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ uint32_t RESERVED4[1U]; __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ } CoreDebug_Type; /* Debug Halting Control and Status Register Definitions */ #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ /* Debug Core Register Selector Register Definitions */ #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ /* Debug Exception and Monitor Control Register */ #define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ #define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ /* Debug Authentication Control Register Definitions */ #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ #define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ #define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ #define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ #define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ /* Debug Security Control and Status Register Definitions */ #define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ #define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ #define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ #define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ #define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ #define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ /*@} end of group CMSIS_CoreDebug */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_bitfield Core register bit field macros \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). @{ */ /** \brief Mask and shift a bit field value for use in a register bit range. \param[in] field Name of the register bit field. \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. \return Masked and shifted value. */ #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) /** \brief Mask and shift a register value to extract a bit filed value. \param[in] field Name of the register bit field. \param[in] value Value of register. This parameter is interpreted as an uint32_t type. \return Masked and shifted bit field value. */ #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) /*@} end of group CMSIS_core_bitfield */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_base Core Definitions \brief Definitions for base addresses, unions, and structures. @{ */ /* Memory mapping of Core Hardware */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ #endif #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ #endif #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ #endif #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /*@} */ /******************************************************************************* * Hardware Abstraction Layer Core Function Interface contains: - Core NVIC Functions - Core SysTick Functions - Core Register Access Functions ******************************************************************************/ /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference */ /* ########################## NVIC functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_NVICFunctions NVIC Functions \brief Functions that manage interrupts and exceptions via the NVIC. @{ */ #ifdef CMSIS_NVIC_VIRTUAL #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" #endif #include CMSIS_NVIC_VIRTUAL_HEADER_FILE #else /*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 */ /*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 */ #define NVIC_EnableIRQ __NVIC_EnableIRQ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ #define NVIC_DisableIRQ __NVIC_DisableIRQ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ #define NVIC_GetActive __NVIC_GetActive #define NVIC_SetPriority __NVIC_SetPriority #define NVIC_GetPriority __NVIC_GetPriority #define NVIC_SystemReset __NVIC_SystemReset #endif /* CMSIS_NVIC_VIRTUAL */ #ifdef CMSIS_VECTAB_VIRTUAL #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" #endif #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE #else #define NVIC_SetVector __NVIC_SetVector #define NVIC_GetVector __NVIC_GetVector #endif /* (CMSIS_VECTAB_VIRTUAL) */ #define NVIC_USER_IRQ_OFFSET 16 /* Interrupt Priorities are WORD accessible only under Armv6-M */ /* The following MACROS handle generation of the register offset and byte masks */ #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) /** \brief Enable Interrupt \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Interrupt Enable status \details Returns a device specific interrupt enable status from the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt is not enabled. \return 1 Interrupt is enabled. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Disable Interrupt \details Disables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __DSB(); __ISB(); } } /** \brief Get Pending Interrupt \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Pending Interrupt \details Sets the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Clear Pending Interrupt \details Clears the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Active Interrupt \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not active. \return 1 Interrupt status is active. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief Get Interrupt Target State \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 if interrupt is assigned to Secure \return 1 if interrupt is assigned to Non Secure \note IRQn must not be negative. */ __STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Interrupt Target State \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 if interrupt is assigned to Secure 1 if interrupt is assigned to Non Secure \note IRQn must not be negative. */ __STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Clear Interrupt Target State \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 if interrupt is assigned to Secure 1 if interrupt is assigned to Non Secure \note IRQn must not be negative. */ __STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /** \brief Set Interrupt Priority \details Sets the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) { NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } else { SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } } /** \brief Get Interrupt Priority \details Reads the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); } else { return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); } } /** \brief Set Interrupt Vector \details Sets an interrupt vector in SRAM based interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. VTOR must been relocated to SRAM before. If VTOR is not present address 0 must be mapped to SRAM. \param [in] IRQn Interrupt number \param [in] vector Address of interrupt handler function */ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) uint32_t *vectors = (uint32_t *)SCB->VTOR; #else uint32_t *vectors = (uint32_t *)0x0U; #endif vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; } /** \brief Get Interrupt Vector \details Reads an interrupt vector from interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Address of interrupt handler function */ __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) { #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) uint32_t *vectors = (uint32_t *)SCB->VTOR; #else uint32_t *vectors = (uint32_t *)0x0U; #endif return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; } /** \brief System Reset \details Initiates a system reset request to reset the MCU. */ __STATIC_INLINE void __NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | SCB_AIRCR_SYSRESETREQ_Msk); __DSB(); /* Ensure completion of memory access */ for(;;) /* wait until reset */ { __NOP(); } } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief Enable Interrupt (non-secure) \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Interrupt Enable status (non-secure) \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt is not enabled. \return 1 Interrupt is enabled. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Disable Interrupt (non-secure) \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Pending Interrupt (non-secure) \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Pending Interrupt (non-secure) \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Clear Pending Interrupt (non-secure) \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Active Interrupt (non-secure) \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not active. \return 1 Interrupt status is active. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Interrupt Priority (non-secure) \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every non-secure processor exception. */ __STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } else { SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } } /** \brief Get Interrupt Priority (non-secure) \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); } else { return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); } } #endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ /*@} end of CMSIS_Core_NVICFunctions */ /* ########################## MPU functions #################################### */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #include "mpu_armv8.h" #endif /* ########################## FPU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_FpuFunctions FPU Functions \brief Function that provides FPU type. @{ */ /** \brief get FPU type \details returns the FPU type \returns - \b 0: No FPU - \b 1: Single precision FPU - \b 2: Double + Single precision FPU */ __STATIC_INLINE uint32_t SCB_GetFPUType(void) { return 0U; /* No FPU */ } /*@} end of CMSIS_Core_FpuFunctions */ /* ########################## SAU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SAUFunctions SAU Functions \brief Functions that configure the SAU. @{ */ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief Enable SAU \details Enables the Security Attribution Unit (SAU). */ __STATIC_INLINE void TZ_SAU_Enable(void) { SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); } /** \brief Disable SAU \details Disables the Security Attribution Unit (SAU). */ __STATIC_INLINE void TZ_SAU_Disable(void) { SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); } #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /*@} end of CMSIS_Core_SAUFunctions */ /* ################################## SysTick function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SysTickFunctions SysTick Functions \brief Functions that configure the System. @{ */ #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) /** \brief System Tick Configuration \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief System Tick Configuration (non-secure) \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b> must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ #endif /*@} end of CMSIS_Core_SysTickFunctions */ #ifdef __cplusplus } #endif #endif /* __CORE_CM23_H_DEPENDANT */ #endif /* __CMSIS_GENERIC */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/CMSIS/Include/core_cm3.h.
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/**************************************************************************//** * @file core_cm3.h * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File * @version V5.0.5 * @date 08. January 2018 ******************************************************************************/ /* * Copyright (c) 2009-2017 ARM Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__clang__) #pragma clang system_header /* treat file as system include file */ #endif #ifndef __CORE_CM3_H_GENERIC #define __CORE_CM3_H_GENERIC #include <stdint.h> #ifdef __cplusplus extern "C" { #endif /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions CMSIS violates the following MISRA-C:2004 rules: \li Required Rule 8.5, object/function definition in header file.<br> Function definitions in header files are used to allow 'inlining'. \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br> Unions are used for effective representation of core registers. \li Advisory Rule 19.7, Function-like macro defined.<br> Function-like macros are used to allow more efficient code. */ /******************************************************************************* * CMSIS definitions ******************************************************************************/ /** \ingroup Cortex_M3 @{ */ #include "cmsis_version.h" /* CMSIS CM3 definitions */ #define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ #define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ #define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ __CM3_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ #define __CORTEX_M (3U) /*!< Cortex-M Core */ /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all */ #define __FPU_USED 0U #if defined ( __CC_ARM ) #if defined __TARGET_FPU_VFP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #if defined __ARM_PCS_VFP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __GNUC__ ) #if defined (__VFP_FP__) && !defined(__SOFTFP__) #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __ICCARM__ ) #if defined __ARMVFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __TI_ARM__ ) #if defined __TI_VFP_SUPPORT__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __TASKING__ ) #if defined __FPU_VFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __CSMC__ ) #if ( __CSMC__ & 0x400U) #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #endif #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ #ifdef __cplusplus } #endif #endif /* __CORE_CM3_H_GENERIC */ #ifndef __CMSIS_GENERIC #ifndef __CORE_CM3_H_DEPENDANT #define __CORE_CM3_H_DEPENDANT #ifdef __cplusplus extern "C" { #endif /* check device defines and use defaults */ #if defined __CHECK_DEVICE_DEFINES #ifndef __CM3_REV #define __CM3_REV 0x0200U #warning "__CM3_REV not defined in device header file; using default!" #endif #ifndef __MPU_PRESENT #define __MPU_PRESENT 0U #warning "__MPU_PRESENT not defined in device header file; using default!" #endif #ifndef __NVIC_PRIO_BITS #define __NVIC_PRIO_BITS 3U #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" #endif #ifndef __Vendor_SysTickConfig #define __Vendor_SysTickConfig 0U #warning "__Vendor_SysTickConfig not defined in device header file; using default!" #endif #endif /* IO definitions (access restrictions to peripheral registers) */ /** \defgroup CMSIS_glob_defs CMSIS Global Defines <strong>IO Type Qualifiers</strong> are used \li to specify the access to peripheral variables. \li for automatic generation of peripheral register debug information. */ #ifdef __cplusplus #define __I volatile /*!< Defines 'read only' permissions */ #else #define __I volatile const /*!< Defines 'read only' permissions */ #endif #define __O volatile /*!< Defines 'write only' permissions */ #define __IO volatile /*!< Defines 'read / write' permissions */ /* following defines should be used for structure members */ #define __IM volatile const /*! Defines 'read only' structure member permissions */ #define __OM volatile /*! Defines 'write only' structure member permissions */ #define __IOM volatile /*! Defines 'read / write' structure member permissions */ /*@} end of group Cortex_M3 */ /******************************************************************************* * Register Abstraction Core Register contain: - Core Register - Core NVIC Register - Core SCB Register - Core SysTick Register - Core Debug Register - Core MPU Register ******************************************************************************/ /** \defgroup CMSIS_core_register Defines and Type Definitions \brief Type definitions and defines for Cortex-M processor based devices. */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CORE Status and Control Registers \brief Core Register type definitions. @{ */ /** \brief Union type to access the Application Program Status Register (APSR). */ typedef union { struct { uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } APSR_Type; /* APSR Register Definitions */ #define APSR_N_Pos 31U /*!< APSR: N Position */ #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ #define APSR_Z_Pos 30U /*!< APSR: Z Position */ #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ #define APSR_C_Pos 29U /*!< APSR: C Position */ #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ #define APSR_V_Pos 28U /*!< APSR: V Position */ #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ #define APSR_Q_Pos 27U /*!< APSR: Q Position */ #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } IPSR_Type; /* IPSR Register Definitions */ #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:1; /*!< bit: 9 Reserved */ uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ uint32_t T:1; /*!< bit: 24 Thumb bit */ uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } xPSR_Type; /* xPSR Register Definitions */ #define xPSR_N_Pos 31U /*!< xPSR: N Position */ #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ #define xPSR_C_Pos 29U /*!< xPSR: C Position */ #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ #define xPSR_V_Pos 28U /*!< xPSR: V Position */ #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ #define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ #define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ #define xPSR_T_Pos 24U /*!< xPSR: T Position */ #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ #define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ #define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ /** \brief Union type to access the Control Registers (CONTROL). */ typedef union { struct { uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } CONTROL_Type; /* CONTROL Register Definitions */ #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ /*@} end of group CMSIS_CORE */ /** \ingroup CMSIS_core_register \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \brief Type definitions for the NVIC Registers @{ */ /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). */ typedef struct { __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ uint32_t RESERVED0[24U]; __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ uint32_t RSERVED1[24U]; __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ uint32_t RESERVED2[24U]; __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ uint32_t RESERVED3[24U]; __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ uint32_t RESERVED4[56U]; __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ uint32_t RESERVED5[644U]; __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ } NVIC_Type; /* Software Triggered Interrupt Register Definitions */ #define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ /*@} end of group CMSIS_NVIC */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCB System Control Block (SCB) \brief Type definitions for the System Control Block Registers @{ */ /** \brief Structure type to access the System Control Block (SCB). */ typedef struct { __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ uint32_t RESERVED0[5U]; __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ } SCB_Type; /* SCB CPUID Register Definitions */ #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ /* SCB Vector Table Offset Register Definitions */ #if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */ #define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ #define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ #define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ #else #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ #endif /* SCB Application Interrupt and Reset Control Register Definitions */ #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ #define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ /* SCB System Control Register Definitions */ #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ /* SCB Configuration Control Register Definitions */ #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ #define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ /* SCB System Handler Control and State Register Definitions */ #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ /* SCB Configurable Fault Status Register Definitions */ #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ #define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ #define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ #define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ #define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ /* BusFault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ /* SCB Hard Fault Status Register Definitions */ #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ #define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ /* SCB Debug Fault Status Register Definitions */ #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ /*@} end of group CMSIS_SCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) \brief Type definitions for the System Control and ID Register not in the SCB @{ */ /** \brief Structure type to access the System Control and ID Register not in the SCB. */ typedef struct { uint32_t RESERVED0[1U]; __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ #if defined (__CM3_REV) && (__CM3_REV >= 0x200U) __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ #else uint32_t RESERVED1[1U]; #endif } SCnSCB_Type; /* Interrupt Controller Type Register Definitions */ #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ /* Auxiliary Control Register Definitions */ #define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ /*@} end of group CMSIS_SCnotSCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SysTick System Tick Timer (SysTick) \brief Type definitions for the System Timer Registers. @{ */ /** \brief Structure type to access the System Timer (SysTick). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ } SysTick_Type; /* SysTick Control / Status Register Definitions */ #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ /*@} end of group CMSIS_SysTick */ /** \ingroup CMSIS_core_register \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) \brief Type definitions for the Instrumentation Trace Macrocell (ITM) @{ */ /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). */ typedef struct { __OM union { __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ uint32_t RESERVED0[864U]; __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ uint32_t RESERVED1[15U]; __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ uint32_t RESERVED2[15U]; __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ uint32_t RESERVED3[29U]; __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ uint32_t RESERVED4[43U]; __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ uint32_t RESERVED5[6U]; __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ } ITM_Type; /* ITM Trace Privilege Register Definitions */ #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ #define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ /* ITM Trace Control Register Definitions */ #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ #define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ #define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ #define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ #define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ #define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ /* ITM Integration Write Register Definitions */ #define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ /* ITM Integration Read Register Definitions */ #define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ /* ITM Integration Mode Control Register Definitions */ #define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ /* ITM Lock Status Register Definitions */ #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ #define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ #define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ /*@}*/ /* end of group CMSIS_ITM */ /** \ingroup CMSIS_core_register \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) \brief Type definitions for the Data Watchpoint and Trace (DWT) @{ */ /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ uint32_t RESERVED0[1U]; __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ uint32_t RESERVED1[1U]; __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ uint32_t RESERVED2[1U]; __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ } DWT_Type; /* DWT Control Register Definitions */ #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ /* DWT CPI Count Register Definitions */ #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ /* DWT Exception Overhead Count Register Definitions */ #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ /* DWT Sleep Count Register Definitions */ #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ /* DWT LSU Count Register Definitions */ #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ /* DWT Folded-instruction Count Register Definitions */ #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ /* DWT Comparator Mask Register Definitions */ #define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ /* DWT Comparator Function Register Definitions */ #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ #define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ #define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ #define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ #define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ #define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ #define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ #define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ /*@}*/ /* end of group CMSIS_DWT */ /** \ingroup CMSIS_core_register \defgroup CMSIS_TPI Trace Port Interface (TPI) \brief Type definitions for the Trace Port Interface (TPI) @{ */ /** \brief Structure type to access the Trace Port Interface Register (TPI). */ typedef struct { __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ uint32_t RESERVED0[2U]; __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ uint32_t RESERVED1[55U]; __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ uint32_t RESERVED2[131U]; __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ uint32_t RESERVED3[759U]; __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ uint32_t RESERVED4[1U]; __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ uint32_t RESERVED5[39U]; __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ uint32_t RESERVED7[8U]; __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ } TPI_Type; /* TPI Asynchronous Clock Prescaler Register Definitions */ #define TPI_ACPR_PRESCALER_Pos 0U /*!< @Deprecated TPI ACPR: PRESCALER Position */ #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< @Deprecated TPI ACPR: PRESCALER Mask */ #define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ #define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ /* TPI Selected Pin Protocol Register Definitions */ #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ /* TPI Formatter and Flush Status Register Definitions */ #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ /* TPI Formatter and Flush Control Register Definitions */ #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ /* TPI TRIGGER Register Definitions */ #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ /* TPI Integration ETM Data Register Definitions (FIFO0) */ #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ /* TPI ITATBCTR2 Register Definitions */ #define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ /* TPI Integration ITM Data Register Definitions (FIFO1) */ #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ /* TPI ITATBCTR0 Register Definitions */ #define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ /* TPI Integration Mode Control Register Definitions */ #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ /* TPI DEVID Register Definitions */ #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ /* TPI DEVTYPE Register Definitions */ #define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ #define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ /*@}*/ /* end of group CMSIS_TPI */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) /** \ingroup CMSIS_core_register \defgroup CMSIS_MPU Memory Protection Unit (MPU) \brief Type definitions for the Memory Protection Unit (MPU) @{ */ /** \brief Structure type to access the Memory Protection Unit (MPU). */ typedef struct { __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ } MPU_Type; #define MPU_TYPE_RALIASES 4U /* MPU Type Register Definitions */ #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ /* MPU Control Register Definitions */ #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ /* MPU Region Number Register Definitions */ #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ /* MPU Region Base Address Register Definitions */ #define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ /* MPU Region Attribute and Size Register Definitions */ #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ /*@} end of group CMSIS_MPU */ #endif /** \ingroup CMSIS_core_register \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \brief Type definitions for the Core Debug Registers @{ */ /** \brief Structure type to access the Core Debug Register (CoreDebug). */ typedef struct { __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ } CoreDebug_Type; /* Debug Halting Control and Status Register Definitions */ #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ /* Debug Core Register Selector Register Definitions */ #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ /* Debug Exception and Monitor Control Register Definitions */ #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ /*@} end of group CMSIS_CoreDebug */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_bitfield Core register bit field macros \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). @{ */ /** \brief Mask and shift a bit field value for use in a register bit range. \param[in] field Name of the register bit field. \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. \return Masked and shifted value. */ #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) /** \brief Mask and shift a register value to extract a bit filed value. \param[in] field Name of the register bit field. \param[in] value Value of register. This parameter is interpreted as an uint32_t type. \return Masked and shifted bit field value. */ #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) /*@} end of group CMSIS_core_bitfield */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_base Core Definitions \brief Definitions for base addresses, unions, and structures. @{ */ /* Memory mapping of Core Hardware */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ #endif /*@} */ /******************************************************************************* * Hardware Abstraction Layer Core Function Interface contains: - Core NVIC Functions - Core SysTick Functions - Core Debug Functions - Core Register Access Functions ******************************************************************************/ /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference */ /* ########################## NVIC functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_NVICFunctions NVIC Functions \brief Functions that manage interrupts and exceptions via the NVIC. @{ */ #ifdef CMSIS_NVIC_VIRTUAL #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" #endif #include CMSIS_NVIC_VIRTUAL_HEADER_FILE #else #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping #define NVIC_EnableIRQ __NVIC_EnableIRQ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ #define NVIC_DisableIRQ __NVIC_DisableIRQ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ #define NVIC_GetActive __NVIC_GetActive #define NVIC_SetPriority __NVIC_SetPriority #define NVIC_GetPriority __NVIC_GetPriority #define NVIC_SystemReset __NVIC_SystemReset #endif /* CMSIS_NVIC_VIRTUAL */ #ifdef CMSIS_VECTAB_VIRTUAL #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" #endif #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE #else #define NVIC_SetVector __NVIC_SetVector #define NVIC_GetVector __NVIC_GetVector #endif /* (CMSIS_VECTAB_VIRTUAL) */ #define NVIC_USER_IRQ_OFFSET 16 /** \brief Set Priority Grouping \details Sets the priority grouping field using the required unlock sequence. The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ reg_value = SCB->AIRCR; /* read old register configuration */ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ SCB->AIRCR = reg_value; } /** \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); } /** \brief Enable Interrupt \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Interrupt Enable status \details Returns a device specific interrupt enable status from the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt is not enabled. \return 1 Interrupt is enabled. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Disable Interrupt \details Disables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __DSB(); __ISB(); } } /** \brief Get Pending Interrupt \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Pending Interrupt \details Sets the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Clear Pending Interrupt \details Clears the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Active Interrupt \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not active. \return 1 Interrupt status is active. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Interrupt Priority \details Sets the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) { NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } else { SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } /** \brief Get Interrupt Priority \details Reads the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); } else { return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); } } /** \brief Encode Priority \details Encodes the priority for an interrupt with the given priority group, preemptive priority value, and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Used priority group. \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) ); } /** \brief Decode Priority \details Decodes an interrupt priority value with a given priority group to preemptive priority value and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). \param [in] PriorityGroup Used priority group. \param [out] pPreemptPriority Preemptive priority value (starting from 0). \param [out] pSubPriority Subpriority value (starting from 0). */ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); } /** \brief Set Interrupt Vector \details Sets an interrupt vector in SRAM based interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. VTOR must been relocated to SRAM before. \param [in] IRQn Interrupt number \param [in] vector Address of interrupt handler function */ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { uint32_t *vectors = (uint32_t *)SCB->VTOR; vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; } /** \brief Get Interrupt Vector \details Reads an interrupt vector from interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Address of interrupt handler function */ __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) { uint32_t *vectors = (uint32_t *)SCB->VTOR; return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; } /** \brief System Reset \details Initiates a system reset request to reset the MCU. */ __STATIC_INLINE void __NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ __DSB(); /* Ensure completion of memory access */ for(;;) /* wait until reset */ { __NOP(); } } /*@} end of CMSIS_Core_NVICFunctions */ /* ########################## MPU functions #################################### */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #include "mpu_armv7.h" #endif /* ########################## FPU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_FpuFunctions FPU Functions \brief Function that provides FPU type. @{ */ /** \brief get FPU type \details returns the FPU type \returns - \b 0: No FPU - \b 1: Single precision FPU - \b 2: Double + Single precision FPU */ __STATIC_INLINE uint32_t SCB_GetFPUType(void) { return 0U; /* No FPU */ } /*@} end of CMSIS_Core_FpuFunctions */ /* ################################## SysTick function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SysTickFunctions SysTick Functions \brief Functions that configure the System. @{ */ #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) /** \brief System Tick Configuration \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #endif /*@} end of CMSIS_Core_SysTickFunctions */ /* ##################################### Debug In/Output function ########################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_core_DebugFunctions ITM Functions \brief Functions that access the ITM debug interface. @{ */ extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ /** \brief ITM Send Character \details Transmits a character via the ITM channel 0, and \li Just returns when no debugger is connected that has booked the output. \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. \param [in] ch Character to transmit. \returns Character to transmit. */ __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) { if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ { while (ITM->PORT[0U].u32 == 0UL) { __NOP(); } ITM->PORT[0U].u8 = (uint8_t)ch; } return (ch); } /** \brief ITM Receive Character \details Inputs a character via the external variable \ref ITM_RxBuffer. \return Received character. \return -1 No character pending. */ __STATIC_INLINE int32_t ITM_ReceiveChar (void) { int32_t ch = -1; /* no character available */ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { ch = ITM_RxBuffer; ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ } return (ch); } /** \brief ITM Check Character \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. \return 0 No character available. \return 1 Character available. */ __STATIC_INLINE int32_t ITM_CheckChar (void) { if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { return (0); /* no character available */ } else { return (1); /* character available */ } } /*@} end of CMSIS_core_DebugFunctions */ #ifdef __cplusplus } #endif #endif /* __CORE_CM3_H_DEPENDANT */ #endif /* __CMSIS_GENERIC */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/CMSIS/Include/core_cm33.h.
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/**************************************************************************//** * @file core_cm33.h * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File * @version V5.0.5 * @date 08. January 2018 ******************************************************************************/ /* * Copyright (c) 2009-2017 ARM Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__clang__) #pragma clang system_header /* treat file as system include file */ #endif #ifndef __CORE_CM33_H_GENERIC #define __CORE_CM33_H_GENERIC #include <stdint.h> #ifdef __cplusplus extern "C" { #endif /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions CMSIS violates the following MISRA-C:2004 rules: \li Required Rule 8.5, object/function definition in header file.<br> Function definitions in header files are used to allow 'inlining'. \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br> Unions are used for effective representation of core registers. \li Advisory Rule 19.7, Function-like macro defined.<br> Function-like macros are used to allow more efficient code. */ /******************************************************************************* * CMSIS definitions ******************************************************************************/ /** \ingroup Cortex_M33 @{ */ #include "cmsis_version.h" /* CMSIS CM33 definitions */ #define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ #define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ #define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \ __CM33_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ #define __CORTEX_M (33U) /*!< Cortex-M Core */ /** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. */ #if defined ( __CC_ARM ) #if defined (__TARGET_FPU_VFP) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" #define __DSP_USED 0U #endif #else #define __DSP_USED 0U #endif #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #if defined (__ARM_PCS_VFP) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" #define __DSP_USED 0U #endif #else #define __DSP_USED 0U #endif #elif defined ( __GNUC__ ) #if defined (__VFP_FP__) && !defined(__SOFTFP__) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" #define __DSP_USED 0U #endif #else #define __DSP_USED 0U #endif #elif defined ( __ICCARM__ ) #if defined (__ARMVFP__) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" #define __DSP_USED 0U #endif #else #define __DSP_USED 0U #endif #elif defined ( __TI_ARM__ ) #if defined (__TI_VFP_SUPPORT__) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined ( __TASKING__ ) #if defined (__FPU_VFP__) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined ( __CSMC__ ) #if ( __CSMC__ & 0x400U) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #endif #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ #ifdef __cplusplus } #endif #endif /* __CORE_CM33_H_GENERIC */ #ifndef __CMSIS_GENERIC #ifndef __CORE_CM33_H_DEPENDANT #define __CORE_CM33_H_DEPENDANT #ifdef __cplusplus extern "C" { #endif /* check device defines and use defaults */ #if defined __CHECK_DEVICE_DEFINES #ifndef __CM33_REV #define __CM33_REV 0x0000U #warning "__CM33_REV not defined in device header file; using default!" #endif #ifndef __FPU_PRESENT #define __FPU_PRESENT 0U #warning "__FPU_PRESENT not defined in device header file; using default!" #endif #ifndef __MPU_PRESENT #define __MPU_PRESENT 0U #warning "__MPU_PRESENT not defined in device header file; using default!" #endif #ifndef __SAUREGION_PRESENT #define __SAUREGION_PRESENT 0U #warning "__SAUREGION_PRESENT not defined in device header file; using default!" #endif #ifndef __DSP_PRESENT #define __DSP_PRESENT 0U #warning "__DSP_PRESENT not defined in device header file; using default!" #endif #ifndef __NVIC_PRIO_BITS #define __NVIC_PRIO_BITS 3U #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" #endif #ifndef __Vendor_SysTickConfig #define __Vendor_SysTickConfig 0U #warning "__Vendor_SysTickConfig not defined in device header file; using default!" #endif #endif /* IO definitions (access restrictions to peripheral registers) */ /** \defgroup CMSIS_glob_defs CMSIS Global Defines <strong>IO Type Qualifiers</strong> are used \li to specify the access to peripheral variables. \li for automatic generation of peripheral register debug information. */ #ifdef __cplusplus #define __I volatile /*!< Defines 'read only' permissions */ #else #define __I volatile const /*!< Defines 'read only' permissions */ #endif #define __O volatile /*!< Defines 'write only' permissions */ #define __IO volatile /*!< Defines 'read / write' permissions */ /* following defines should be used for structure members */ #define __IM volatile const /*! Defines 'read only' structure member permissions */ #define __OM volatile /*! Defines 'write only' structure member permissions */ #define __IOM volatile /*! Defines 'read / write' structure member permissions */ /*@} end of group Cortex_M33 */ /******************************************************************************* * Register Abstraction Core Register contain: - Core Register - Core NVIC Register - Core SCB Register - Core SysTick Register - Core Debug Register - Core MPU Register - Core SAU Register - Core FPU Register ******************************************************************************/ /** \defgroup CMSIS_core_register Defines and Type Definitions \brief Type definitions and defines for Cortex-M processor based devices. */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CORE Status and Control Registers \brief Core Register type definitions. @{ */ /** \brief Union type to access the Application Program Status Register (APSR). */ typedef union { struct { uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } APSR_Type; /* APSR Register Definitions */ #define APSR_N_Pos 31U /*!< APSR: N Position */ #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ #define APSR_Z_Pos 30U /*!< APSR: Z Position */ #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ #define APSR_C_Pos 29U /*!< APSR: C Position */ #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ #define APSR_V_Pos 28U /*!< APSR: V Position */ #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ #define APSR_Q_Pos 27U /*!< APSR: Q Position */ #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ #define APSR_GE_Pos 16U /*!< APSR: GE Position */ #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } IPSR_Type; /* IPSR Register Definitions */ #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } xPSR_Type; /* xPSR Register Definitions */ #define xPSR_N_Pos 31U /*!< xPSR: N Position */ #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ #define xPSR_C_Pos 29U /*!< xPSR: C Position */ #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ #define xPSR_V_Pos 28U /*!< xPSR: V Position */ #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ #define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ #define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ #define xPSR_T_Pos 24U /*!< xPSR: T Position */ #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ #define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ /** \brief Union type to access the Control Registers (CONTROL). */ typedef union { struct { uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } CONTROL_Type; /* CONTROL Register Definitions */ #define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ #define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ #define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ /*@} end of group CMSIS_CORE */ /** \ingroup CMSIS_core_register \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \brief Type definitions for the NVIC Registers @{ */ /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). */ typedef struct { __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ uint32_t RESERVED0[16U]; __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ uint32_t RSERVED1[16U]; __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ uint32_t RESERVED2[16U]; __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ uint32_t RESERVED3[16U]; __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ uint32_t RESERVED4[16U]; __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ uint32_t RESERVED5[16U]; __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ uint32_t RESERVED6[580U]; __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ } NVIC_Type; /* Software Triggered Interrupt Register Definitions */ #define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ /*@} end of group CMSIS_NVIC */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCB System Control Block (SCB) \brief Type definitions for the System Control Block Registers @{ */ /** \brief Structure type to access the System Control Block (SCB). */ typedef struct { __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ uint32_t RESERVED3[92U]; __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ uint32_t RESERVED4[15U]; __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ uint32_t RESERVED5[1U]; __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ uint32_t RESERVED6[1U]; __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ uint32_t RESERVED7[6U]; __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ uint32_t RESERVED8[1U]; __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ } SCB_Type; /* SCB CPUID Register Definitions */ #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ #define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ #define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ #define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ /* SCB Vector Table Offset Register Definitions */ #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ /* SCB Application Interrupt and Reset Control Register Definitions */ #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ #define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ #define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ #define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ #define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ #define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ #define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ /* SCB System Control Register Definitions */ #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ #define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ #define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ /* SCB Configuration Control Register Definitions */ #define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ #define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ #define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ #define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ #define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ /* SCB System Handler Control and State Register Definitions */ #define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ #define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ #define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ #define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ #define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ #define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ #define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ #define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ #define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ #define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ #define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ #define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ /* SCB Configurable Fault Status Register Definitions */ #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ #define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ #define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ #define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ #define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ #define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ /* BusFault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ #define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ #define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ /* SCB Hard Fault Status Register Definitions */ #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ #define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ /* SCB Debug Fault Status Register Definitions */ #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ /* SCB Non-Secure Access Control Register Definitions */ #define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ #define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ #define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ #define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ #define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ #define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ /* SCB Cache Level ID Register Definitions */ #define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ #define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ /* SCB Cache Type Register Definitions */ #define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ #define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ #define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ #define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ #define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ #define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ /* SCB Cache Size ID Register Definitions */ #define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ #define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ #define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ #define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ #define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ #define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ #define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ #define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ #define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ #define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ #define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ /* SCB Cache Size Selection Register Definitions */ #define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ #define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ /* SCB Software Triggered Interrupt Register Definitions */ #define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ #define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ /* SCB D-Cache Invalidate by Set-way Register Definitions */ #define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ #define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ #define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ #define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ /* SCB D-Cache Clean by Set-way Register Definitions */ #define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ #define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ #define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ #define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ /* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ #define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ #define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ #define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ #define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ /* Instruction Tightly-Coupled Memory Control Register Definitions */ #define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ #define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ #define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ #define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ #define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ #define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ #define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ #define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ /* Data Tightly-Coupled Memory Control Register Definitions */ #define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ #define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ #define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ #define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ #define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ #define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ #define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ #define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ /* AHBP Control Register Definitions */ #define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ #define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ #define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ #define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ /* L1 Cache Control Register Definitions */ #define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ #define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ #define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ #define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ #define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ #define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ /* AHBS Control Register Definitions */ #define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ #define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ #define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ #define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ #define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ #define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ /* Auxiliary Bus Fault Status Register Definitions */ #define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ #define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ #define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ #define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ #define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ #define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ #define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ #define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ #define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ #define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ #define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ #define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ /*@} end of group CMSIS_SCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) \brief Type definitions for the System Control and ID Register not in the SCB @{ */ /** \brief Structure type to access the System Control and ID Register not in the SCB. */ typedef struct { uint32_t RESERVED0[1U]; __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ } SCnSCB_Type; /* Interrupt Controller Type Register Definitions */ #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ /*@} end of group CMSIS_SCnotSCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SysTick System Tick Timer (SysTick) \brief Type definitions for the System Timer Registers. @{ */ /** \brief Structure type to access the System Timer (SysTick). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ } SysTick_Type; /* SysTick Control / Status Register Definitions */ #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ /*@} end of group CMSIS_SysTick */ /** \ingroup CMSIS_core_register \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) \brief Type definitions for the Instrumentation Trace Macrocell (ITM) @{ */ /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). */ typedef struct { __OM union { __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ uint32_t RESERVED0[864U]; __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ uint32_t RESERVED1[15U]; __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ uint32_t RESERVED2[15U]; __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ uint32_t RESERVED3[29U]; __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ uint32_t RESERVED4[43U]; __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ uint32_t RESERVED5[1U]; __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ uint32_t RESERVED6[4U]; __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ } ITM_Type; /* ITM Stimulus Port Register Definitions */ #define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ #define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ #define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ #define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ /* ITM Trace Privilege Register Definitions */ #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ #define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ /* ITM Trace Control Register Definitions */ #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ #define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ #define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ #define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ #define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ #define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ #define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ #define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ #define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ #define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ /* ITM Integration Write Register Definitions */ #define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ /* ITM Integration Read Register Definitions */ #define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ /* ITM Integration Mode Control Register Definitions */ #define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ /* ITM Lock Status Register Definitions */ #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ #define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ #define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ /*@}*/ /* end of group CMSIS_ITM */ /** \ingroup CMSIS_core_register \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) \brief Type definitions for the Data Watchpoint and Trace (DWT) @{ */ /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ uint32_t RESERVED1[1U]; __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ uint32_t RESERVED2[1U]; __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ uint32_t RESERVED3[1U]; __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ uint32_t RESERVED4[1U]; __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ uint32_t RESERVED5[1U]; __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ uint32_t RESERVED6[1U]; __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ uint32_t RESERVED7[1U]; __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ uint32_t RESERVED8[1U]; __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ uint32_t RESERVED9[1U]; __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ uint32_t RESERVED10[1U]; __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ uint32_t RESERVED11[1U]; __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ uint32_t RESERVED12[1U]; __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ uint32_t RESERVED13[1U]; __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ uint32_t RESERVED14[1U]; __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ uint32_t RESERVED15[1U]; __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ uint32_t RESERVED16[1U]; __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ uint32_t RESERVED17[1U]; __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ uint32_t RESERVED18[1U]; __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ uint32_t RESERVED19[1U]; __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ uint32_t RESERVED20[1U]; __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ uint32_t RESERVED21[1U]; __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ uint32_t RESERVED22[1U]; __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ uint32_t RESERVED23[1U]; __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ uint32_t RESERVED24[1U]; __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ uint32_t RESERVED25[1U]; __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ uint32_t RESERVED26[1U]; __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ uint32_t RESERVED27[1U]; __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ uint32_t RESERVED28[1U]; __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ uint32_t RESERVED29[1U]; __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ uint32_t RESERVED30[1U]; __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ uint32_t RESERVED31[1U]; __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ uint32_t RESERVED32[934U]; __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ uint32_t RESERVED33[1U]; __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ } DWT_Type; /* DWT Control Register Definitions */ #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ #define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ #define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ /* DWT CPI Count Register Definitions */ #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ /* DWT Exception Overhead Count Register Definitions */ #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ /* DWT Sleep Count Register Definitions */ #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ /* DWT LSU Count Register Definitions */ #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ /* DWT Folded-instruction Count Register Definitions */ #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ /* DWT Comparator Function Register Definitions */ #define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ #define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ #define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ #define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ #define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ #define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ /*@}*/ /* end of group CMSIS_DWT */ /** \ingroup CMSIS_core_register \defgroup CMSIS_TPI Trace Port Interface (TPI) \brief Type definitions for the Trace Port Interface (TPI) @{ */ /** \brief Structure type to access the Trace Port Interface Register (TPI). */ typedef struct { __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ uint32_t RESERVED0[2U]; __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ uint32_t RESERVED1[55U]; __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ uint32_t RESERVED2[131U]; __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ uint32_t RESERVED3[759U]; __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ uint32_t RESERVED4[1U]; __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ uint32_t RESERVED5[39U]; __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ uint32_t RESERVED7[8U]; __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ } TPI_Type; /* TPI Asynchronous Clock Prescaler Register Definitions */ #define TPI_ACPR_PRESCALER_Pos 0U /*!< @Deprecated TPI ACPR: PRESCALER Position */ #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< @Deprecated TPI ACPR: PRESCALER Mask */ #define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ #define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ /* TPI Selected Pin Protocol Register Definitions */ #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ /* TPI Formatter and Flush Status Register Definitions */ #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ /* TPI Formatter and Flush Control Register Definitions */ #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ /* TPI TRIGGER Register Definitions */ #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ /* TPI Integration ETM Data Register Definitions (FIFO0) */ #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ /* TPI ITATBCTR2 Register Definitions */ #define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ /* TPI Integration ITM Data Register Definitions (FIFO1) */ #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ /* TPI ITATBCTR0 Register Definitions */ #define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ /* TPI Integration Mode Control Register Definitions */ #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ /* TPI DEVID Register Definitions */ #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ /* TPI DEVTYPE Register Definitions */ #define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ #define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ /*@}*/ /* end of group CMSIS_TPI */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) /** \ingroup CMSIS_core_register \defgroup CMSIS_MPU Memory Protection Unit (MPU) \brief Type definitions for the Memory Protection Unit (MPU) @{ */ /** \brief Structure type to access the Memory Protection Unit (MPU). */ typedef struct { __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ uint32_t RESERVED0[1]; union { __IOM uint32_t MAIR[2]; struct { __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ }; }; } MPU_Type; #define MPU_TYPE_RALIASES 4U /* MPU Type Register Definitions */ #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ /* MPU Control Register Definitions */ #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ /* MPU Region Number Register Definitions */ #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ /* MPU Region Base Address Register Definitions */ #define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: ADDR Position */ #define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: ADDR Mask */ #define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ #define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ #define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ #define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ #define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ #define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ /* MPU Region Limit Address Register Definitions */ #define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ #define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ #define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ #define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ #define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ #define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ /* MPU Memory Attribute Indirection Register 0 Definitions */ #define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ #define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ #define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ #define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ #define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ #define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ #define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ #define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ /* MPU Memory Attribute Indirection Register 1 Definitions */ #define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ #define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ #define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ #define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ #define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ #define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ #define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ #define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ /*@} end of group CMSIS_MPU */ #endif #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \ingroup CMSIS_core_register \defgroup CMSIS_SAU Security Attribution Unit (SAU) \brief Type definitions for the Security Attribution Unit (SAU) @{ */ /** \brief Structure type to access the Security Attribution Unit (SAU). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ #else uint32_t RESERVED0[3]; #endif __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ } SAU_Type; /* SAU Control Register Definitions */ #define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ #define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ #define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ #define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ /* SAU Type Register Definitions */ #define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ #define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) /* SAU Region Number Register Definitions */ #define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ #define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ /* SAU Region Base Address Register Definitions */ #define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ #define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ /* SAU Region Limit Address Register Definitions */ #define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ #define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ #define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ #define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ #define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ #define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ /* Secure Fault Status Register Definitions */ #define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ #define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ #define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ #define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ #define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ #define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ #define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ #define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ #define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ #define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ #define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ #define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ #define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ #define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ #define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ #define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ /*@} end of group CMSIS_SAU */ #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /** \ingroup CMSIS_core_register \defgroup CMSIS_FPU Floating Point Unit (FPU) \brief Type definitions for the Floating Point Unit (FPU) @{ */ /** \brief Structure type to access the Floating Point Unit (FPU). */ typedef struct { uint32_t RESERVED0[1U]; __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ } FPU_Type; /* Floating-Point Context Control Register Definitions */ #define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ #define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ #define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ #define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ #define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ #define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ #define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ #define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ #define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ #define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ #define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ #define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ #define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ #define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ #define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ #define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ #define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ #define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ #define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ #define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ #define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ #define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ #define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ #define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ #define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ /* Floating-Point Context Address Register Definitions */ #define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ /* Floating-Point Default Status Control Register Definitions */ #define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ #define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ #define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ #define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ /* Media and FP Feature Register 0 Definitions */ #define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ #define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ #define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ #define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ #define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ #define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ #define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ #define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ /* Media and FP Feature Register 1 Definitions */ #define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ #define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ #define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ #define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ /*@} end of group CMSIS_FPU */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \brief Type definitions for the Core Debug Registers @{ */ /** \brief Structure type to access the Core Debug Register (CoreDebug). */ typedef struct { __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ uint32_t RESERVED4[1U]; __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ } CoreDebug_Type; /* Debug Halting Control and Status Register Definitions */ #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ /* Debug Core Register Selector Register Definitions */ #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ /* Debug Exception and Monitor Control Register Definitions */ #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ /* Debug Authentication Control Register Definitions */ #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ #define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ #define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ #define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ #define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ /* Debug Security Control and Status Register Definitions */ #define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ #define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ #define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ #define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ #define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ #define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ /*@} end of group CMSIS_CoreDebug */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_bitfield Core register bit field macros \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). @{ */ /** \brief Mask and shift a bit field value for use in a register bit range. \param[in] field Name of the register bit field. \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. \return Masked and shifted value. */ #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) /** \brief Mask and shift a register value to extract a bit filed value. \param[in] field Name of the register bit field. \param[in] value Value of register. This parameter is interpreted as an uint32_t type. \return Masked and shifted bit field value. */ #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) /*@} end of group CMSIS_core_bitfield */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_base Core Definitions \brief Definitions for base addresses, unions, and structures. @{ */ /* Memory mapping of Core Hardware */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ #endif #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ #endif #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ #endif #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /*@} */ /******************************************************************************* * Hardware Abstraction Layer Core Function Interface contains: - Core NVIC Functions - Core SysTick Functions - Core Debug Functions - Core Register Access Functions ******************************************************************************/ /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference */ /* ########################## NVIC functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_NVICFunctions NVIC Functions \brief Functions that manage interrupts and exceptions via the NVIC. @{ */ #ifdef CMSIS_NVIC_VIRTUAL #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" #endif #include CMSIS_NVIC_VIRTUAL_HEADER_FILE #else #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping #define NVIC_EnableIRQ __NVIC_EnableIRQ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ #define NVIC_DisableIRQ __NVIC_DisableIRQ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ #define NVIC_GetActive __NVIC_GetActive #define NVIC_SetPriority __NVIC_SetPriority #define NVIC_GetPriority __NVIC_GetPriority #define NVIC_SystemReset __NVIC_SystemReset #endif /* CMSIS_NVIC_VIRTUAL */ #ifdef CMSIS_VECTAB_VIRTUAL #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" #endif #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE #else #define NVIC_SetVector __NVIC_SetVector #define NVIC_GetVector __NVIC_GetVector #endif /* (CMSIS_VECTAB_VIRTUAL) */ #define NVIC_USER_IRQ_OFFSET 16 /** \brief Set Priority Grouping \details Sets the priority grouping field using the required unlock sequence. The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ reg_value = SCB->AIRCR; /* read old register configuration */ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << 8U) ); /* Insert write key and priority group */ SCB->AIRCR = reg_value; } /** \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); } /** \brief Enable Interrupt \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Interrupt Enable status \details Returns a device specific interrupt enable status from the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt is not enabled. \return 1 Interrupt is enabled. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Disable Interrupt \details Disables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __DSB(); __ISB(); } } /** \brief Get Pending Interrupt \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Pending Interrupt \details Sets the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Clear Pending Interrupt \details Clears the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Active Interrupt \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not active. \return 1 Interrupt status is active. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief Get Interrupt Target State \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 if interrupt is assigned to Secure \return 1 if interrupt is assigned to Non Secure \note IRQn must not be negative. */ __STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Interrupt Target State \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 if interrupt is assigned to Secure 1 if interrupt is assigned to Non Secure \note IRQn must not be negative. */ __STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Clear Interrupt Target State \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 if interrupt is assigned to Secure 1 if interrupt is assigned to Non Secure \note IRQn must not be negative. */ __STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /** \brief Set Interrupt Priority \details Sets the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) { NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } else { SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } /** \brief Get Interrupt Priority \details Reads the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); } else { return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); } } /** \brief Encode Priority \details Encodes the priority for an interrupt with the given priority group, preemptive priority value, and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Used priority group. \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) ); } /** \brief Decode Priority \details Decodes an interrupt priority value with a given priority group to preemptive priority value and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). \param [in] PriorityGroup Used priority group. \param [out] pPreemptPriority Preemptive priority value (starting from 0). \param [out] pSubPriority Subpriority value (starting from 0). */ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); } /** \brief Set Interrupt Vector \details Sets an interrupt vector in SRAM based interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. VTOR must been relocated to SRAM before. \param [in] IRQn Interrupt number \param [in] vector Address of interrupt handler function */ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { uint32_t *vectors = (uint32_t *)SCB->VTOR; vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; } /** \brief Get Interrupt Vector \details Reads an interrupt vector from interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Address of interrupt handler function */ __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) { uint32_t *vectors = (uint32_t *)SCB->VTOR; return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; } /** \brief System Reset \details Initiates a system reset request to reset the MCU. */ __STATIC_INLINE void __NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ __DSB(); /* Ensure completion of memory access */ for(;;) /* wait until reset */ { __NOP(); } } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief Set Priority Grouping (non-secure) \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) { uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ reg_value = SCB_NS->AIRCR; /* read old register configuration */ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ SCB_NS->AIRCR = reg_value; } /** \brief Get Priority Grouping (non-secure) \details Reads the priority grouping field from the non-secure NVIC when in secure state. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) { return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); } /** \brief Enable Interrupt (non-secure) \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Interrupt Enable status (non-secure) \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt is not enabled. \return 1 Interrupt is enabled. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Disable Interrupt (non-secure) \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Pending Interrupt (non-secure) \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Pending Interrupt (non-secure) \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Clear Pending Interrupt (non-secure) \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Active Interrupt (non-secure) \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not active. \return 1 Interrupt status is active. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Interrupt Priority (non-secure) \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every non-secure processor exception. */ __STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } else { SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } /** \brief Get Interrupt Priority (non-secure) \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); } else { return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); } } #endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ /*@} end of CMSIS_Core_NVICFunctions */ /* ########################## MPU functions #################################### */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #include "mpu_armv8.h" #endif /* ########################## FPU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_FpuFunctions FPU Functions \brief Function that provides FPU type. @{ */ /** \brief get FPU type \details returns the FPU type \returns - \b 0: No FPU - \b 1: Single precision FPU - \b 2: Double + Single precision FPU */ __STATIC_INLINE uint32_t SCB_GetFPUType(void) { uint32_t mvfr0; mvfr0 = FPU->MVFR0; if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) { return 2U; /* Double + Single precision FPU */ } else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) { return 1U; /* Single precision FPU */ } else { return 0U; /* No FPU */ } } /*@} end of CMSIS_Core_FpuFunctions */ /* ########################## SAU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SAUFunctions SAU Functions \brief Functions that configure the SAU. @{ */ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief Enable SAU \details Enables the Security Attribution Unit (SAU). */ __STATIC_INLINE void TZ_SAU_Enable(void) { SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); } /** \brief Disable SAU \details Disables the Security Attribution Unit (SAU). */ __STATIC_INLINE void TZ_SAU_Disable(void) { SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); } #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /*@} end of CMSIS_Core_SAUFunctions */ /* ################################## SysTick function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SysTickFunctions SysTick Functions \brief Functions that configure the System. @{ */ #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) /** \brief System Tick Configuration \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief System Tick Configuration (non-secure) \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b> must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ #endif /*@} end of CMSIS_Core_SysTickFunctions */ /* ##################################### Debug In/Output function ########################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_core_DebugFunctions ITM Functions \brief Functions that access the ITM debug interface. @{ */ extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ /** \brief ITM Send Character \details Transmits a character via the ITM channel 0, and \li Just returns when no debugger is connected that has booked the output. \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. \param [in] ch Character to transmit. \returns Character to transmit. */ __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) { if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ { while (ITM->PORT[0U].u32 == 0UL) { __NOP(); } ITM->PORT[0U].u8 = (uint8_t)ch; } return (ch); } /** \brief ITM Receive Character \details Inputs a character via the external variable \ref ITM_RxBuffer. \return Received character. \return -1 No character pending. */ __STATIC_INLINE int32_t ITM_ReceiveChar (void) { int32_t ch = -1; /* no character available */ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { ch = ITM_RxBuffer; ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ } return (ch); } /** \brief ITM Check Character \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. \return 0 No character available. \return 1 Character available. */ __STATIC_INLINE int32_t ITM_CheckChar (void) { if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { return (0); /* no character available */ } else { return (1); /* character available */ } } /*@} end of CMSIS_core_DebugFunctions */ #ifdef __cplusplus } #endif #endif /* __CORE_CM33_H_DEPENDANT */ #endif /* __CMSIS_GENERIC */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/CMSIS/Include/core_cm4.h.
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/**************************************************************************//** * @file core_cm4.h * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File * @version V5.0.5 * @date 08. January 2018 ******************************************************************************/ /* * Copyright (c) 2009-2017 ARM Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__clang__) #pragma clang system_header /* treat file as system include file */ #endif #ifndef __CORE_CM4_H_GENERIC #define __CORE_CM4_H_GENERIC #include <stdint.h> #ifdef __cplusplus extern "C" { #endif /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions CMSIS violates the following MISRA-C:2004 rules: \li Required Rule 8.5, object/function definition in header file.<br> Function definitions in header files are used to allow 'inlining'. \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br> Unions are used for effective representation of core registers. \li Advisory Rule 19.7, Function-like macro defined.<br> Function-like macros are used to allow more efficient code. */ /******************************************************************************* * CMSIS definitions ******************************************************************************/ /** \ingroup Cortex_M4 @{ */ #include "cmsis_version.h" /* CMSIS CM4 definitions */ #define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ #define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ #define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ #define __CORTEX_M (4U) /*!< Cortex-M Core */ /** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. */ #if defined ( __CC_ARM ) #if defined __TARGET_FPU_VFP #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #if defined __ARM_PCS_VFP #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined ( __GNUC__ ) #if defined (__VFP_FP__) && !defined(__SOFTFP__) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined ( __ICCARM__ ) #if defined __ARMVFP__ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined ( __TI_ARM__ ) #if defined __TI_VFP_SUPPORT__ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined ( __TASKING__ ) #if defined __FPU_VFP__ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined ( __CSMC__ ) #if ( __CSMC__ & 0x400U) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #endif #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ #ifdef __cplusplus } #endif #endif /* __CORE_CM4_H_GENERIC */ #ifndef __CMSIS_GENERIC #ifndef __CORE_CM4_H_DEPENDANT #define __CORE_CM4_H_DEPENDANT #ifdef __cplusplus extern "C" { #endif /* check device defines and use defaults */ #if defined __CHECK_DEVICE_DEFINES #ifndef __CM4_REV #define __CM4_REV 0x0000U #warning "__CM4_REV not defined in device header file; using default!" #endif #ifndef __FPU_PRESENT #define __FPU_PRESENT 0U #warning "__FPU_PRESENT not defined in device header file; using default!" #endif #ifndef __MPU_PRESENT #define __MPU_PRESENT 0U #warning "__MPU_PRESENT not defined in device header file; using default!" #endif #ifndef __NVIC_PRIO_BITS #define __NVIC_PRIO_BITS 3U #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" #endif #ifndef __Vendor_SysTickConfig #define __Vendor_SysTickConfig 0U #warning "__Vendor_SysTickConfig not defined in device header file; using default!" #endif #endif /* IO definitions (access restrictions to peripheral registers) */ /** \defgroup CMSIS_glob_defs CMSIS Global Defines <strong>IO Type Qualifiers</strong> are used \li to specify the access to peripheral variables. \li for automatic generation of peripheral register debug information. */ #ifdef __cplusplus #define __I volatile /*!< Defines 'read only' permissions */ #else #define __I volatile const /*!< Defines 'read only' permissions */ #endif #define __O volatile /*!< Defines 'write only' permissions */ #define __IO volatile /*!< Defines 'read / write' permissions */ /* following defines should be used for structure members */ #define __IM volatile const /*! Defines 'read only' structure member permissions */ #define __OM volatile /*! Defines 'write only' structure member permissions */ #define __IOM volatile /*! Defines 'read / write' structure member permissions */ /*@} end of group Cortex_M4 */ /******************************************************************************* * Register Abstraction Core Register contain: - Core Register - Core NVIC Register - Core SCB Register - Core SysTick Register - Core Debug Register - Core MPU Register - Core FPU Register ******************************************************************************/ /** \defgroup CMSIS_core_register Defines and Type Definitions \brief Type definitions and defines for Cortex-M processor based devices. */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CORE Status and Control Registers \brief Core Register type definitions. @{ */ /** \brief Union type to access the Application Program Status Register (APSR). */ typedef union { struct { uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } APSR_Type; /* APSR Register Definitions */ #define APSR_N_Pos 31U /*!< APSR: N Position */ #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ #define APSR_Z_Pos 30U /*!< APSR: Z Position */ #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ #define APSR_C_Pos 29U /*!< APSR: C Position */ #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ #define APSR_V_Pos 28U /*!< APSR: V Position */ #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ #define APSR_Q_Pos 27U /*!< APSR: Q Position */ #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ #define APSR_GE_Pos 16U /*!< APSR: GE Position */ #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } IPSR_Type; /* IPSR Register Definitions */ #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:1; /*!< bit: 9 Reserved */ uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ uint32_t T:1; /*!< bit: 24 Thumb bit */ uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } xPSR_Type; /* xPSR Register Definitions */ #define xPSR_N_Pos 31U /*!< xPSR: N Position */ #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ #define xPSR_C_Pos 29U /*!< xPSR: C Position */ #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ #define xPSR_V_Pos 28U /*!< xPSR: V Position */ #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ #define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ #define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ #define xPSR_T_Pos 24U /*!< xPSR: T Position */ #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ #define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ #define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ #define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ /** \brief Union type to access the Control Registers (CONTROL). */ typedef union { struct { uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } CONTROL_Type; /* CONTROL Register Definitions */ #define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ /*@} end of group CMSIS_CORE */ /** \ingroup CMSIS_core_register \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \brief Type definitions for the NVIC Registers @{ */ /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). */ typedef struct { __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ uint32_t RESERVED0[24U]; __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ uint32_t RSERVED1[24U]; __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ uint32_t RESERVED2[24U]; __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ uint32_t RESERVED3[24U]; __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ uint32_t RESERVED4[56U]; __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ uint32_t RESERVED5[644U]; __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ } NVIC_Type; /* Software Triggered Interrupt Register Definitions */ #define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ /*@} end of group CMSIS_NVIC */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCB System Control Block (SCB) \brief Type definitions for the System Control Block Registers @{ */ /** \brief Structure type to access the System Control Block (SCB). */ typedef struct { __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ uint32_t RESERVED0[5U]; __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ } SCB_Type; /* SCB CPUID Register Definitions */ #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ /* SCB Vector Table Offset Register Definitions */ #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ /* SCB Application Interrupt and Reset Control Register Definitions */ #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ #define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ /* SCB System Control Register Definitions */ #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ /* SCB Configuration Control Register Definitions */ #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ #define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ /* SCB System Handler Control and State Register Definitions */ #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ /* SCB Configurable Fault Status Register Definitions */ #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ #define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ #define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ #define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ #define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ #define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ /* BusFault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ /* SCB Hard Fault Status Register Definitions */ #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ #define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ /* SCB Debug Fault Status Register Definitions */ #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ /*@} end of group CMSIS_SCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) \brief Type definitions for the System Control and ID Register not in the SCB @{ */ /** \brief Structure type to access the System Control and ID Register not in the SCB. */ typedef struct { uint32_t RESERVED0[1U]; __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ } SCnSCB_Type; /* Interrupt Controller Type Register Definitions */ #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ /* Auxiliary Control Register Definitions */ #define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ #define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ #define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ #define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ #define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ /*@} end of group CMSIS_SCnotSCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SysTick System Tick Timer (SysTick) \brief Type definitions for the System Timer Registers. @{ */ /** \brief Structure type to access the System Timer (SysTick). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ } SysTick_Type; /* SysTick Control / Status Register Definitions */ #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ /*@} end of group CMSIS_SysTick */ /** \ingroup CMSIS_core_register \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) \brief Type definitions for the Instrumentation Trace Macrocell (ITM) @{ */ /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). */ typedef struct { __OM union { __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ uint32_t RESERVED0[864U]; __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ uint32_t RESERVED1[15U]; __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ uint32_t RESERVED2[15U]; __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ uint32_t RESERVED3[29U]; __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ uint32_t RESERVED4[43U]; __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ uint32_t RESERVED5[6U]; __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ } ITM_Type; /* ITM Trace Privilege Register Definitions */ #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ #define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ /* ITM Trace Control Register Definitions */ #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ #define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ #define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ #define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ #define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ #define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ /* ITM Integration Write Register Definitions */ #define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ /* ITM Integration Read Register Definitions */ #define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ /* ITM Integration Mode Control Register Definitions */ #define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ /* ITM Lock Status Register Definitions */ #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ #define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ #define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ /*@}*/ /* end of group CMSIS_ITM */ /** \ingroup CMSIS_core_register \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) \brief Type definitions for the Data Watchpoint and Trace (DWT) @{ */ /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ uint32_t RESERVED0[1U]; __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ uint32_t RESERVED1[1U]; __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ uint32_t RESERVED2[1U]; __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ } DWT_Type; /* DWT Control Register Definitions */ #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ /* DWT CPI Count Register Definitions */ #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ /* DWT Exception Overhead Count Register Definitions */ #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ /* DWT Sleep Count Register Definitions */ #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ /* DWT LSU Count Register Definitions */ #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ /* DWT Folded-instruction Count Register Definitions */ #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ /* DWT Comparator Mask Register Definitions */ #define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ /* DWT Comparator Function Register Definitions */ #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ #define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ #define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ #define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ #define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ #define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ #define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ #define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ /*@}*/ /* end of group CMSIS_DWT */ /** \ingroup CMSIS_core_register \defgroup CMSIS_TPI Trace Port Interface (TPI) \brief Type definitions for the Trace Port Interface (TPI) @{ */ /** \brief Structure type to access the Trace Port Interface Register (TPI). */ typedef struct { __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ uint32_t RESERVED0[2U]; __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ uint32_t RESERVED1[55U]; __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ uint32_t RESERVED2[131U]; __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ uint32_t RESERVED3[759U]; __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ uint32_t RESERVED4[1U]; __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ uint32_t RESERVED5[39U]; __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ uint32_t RESERVED7[8U]; __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ } TPI_Type; /* TPI Asynchronous Clock Prescaler Register Definitions */ #define TPI_ACPR_PRESCALER_Pos 0U /*!< @Deprecated TPI ACPR: PRESCALER Position */ #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< @Deprecated TPI ACPR: PRESCALER Mask */ #define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ #define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ /* TPI Selected Pin Protocol Register Definitions */ #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ /* TPI Formatter and Flush Status Register Definitions */ #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ /* TPI Formatter and Flush Control Register Definitions */ #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ /* TPI TRIGGER Register Definitions */ #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ /* TPI Integration ETM Data Register Definitions (FIFO0) */ #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ /* TPI ITATBCTR2 Register Definitions */ #define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ /* TPI Integration ITM Data Register Definitions (FIFO1) */ #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ /* TPI ITATBCTR0 Register Definitions */ #define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ /* TPI Integration Mode Control Register Definitions */ #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ /* TPI DEVID Register Definitions */ #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ /* TPI DEVTYPE Register Definitions */ #define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ #define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ /*@}*/ /* end of group CMSIS_TPI */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) /** \ingroup CMSIS_core_register \defgroup CMSIS_MPU Memory Protection Unit (MPU) \brief Type definitions for the Memory Protection Unit (MPU) @{ */ /** \brief Structure type to access the Memory Protection Unit (MPU). */ typedef struct { __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ } MPU_Type; #define MPU_TYPE_RALIASES 4U /* MPU Type Register Definitions */ #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ /* MPU Control Register Definitions */ #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ /* MPU Region Number Register Definitions */ #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ /* MPU Region Base Address Register Definitions */ #define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ /* MPU Region Attribute and Size Register Definitions */ #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ /*@} end of group CMSIS_MPU */ #endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ /** \ingroup CMSIS_core_register \defgroup CMSIS_FPU Floating Point Unit (FPU) \brief Type definitions for the Floating Point Unit (FPU) @{ */ /** \brief Structure type to access the Floating Point Unit (FPU). */ typedef struct { uint32_t RESERVED0[1U]; __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ } FPU_Type; /* Floating-Point Context Control Register Definitions */ #define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ #define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ #define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ #define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ #define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ #define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ #define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ #define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ #define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ /* Floating-Point Context Address Register Definitions */ #define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ /* Floating-Point Default Status Control Register Definitions */ #define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ #define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ #define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ #define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ /* Media and FP Feature Register 0 Definitions */ #define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ #define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ #define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ #define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ #define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ #define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ #define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ #define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ /* Media and FP Feature Register 1 Definitions */ #define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ #define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ #define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ #define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ /*@} end of group CMSIS_FPU */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \brief Type definitions for the Core Debug Registers @{ */ /** \brief Structure type to access the Core Debug Register (CoreDebug). */ typedef struct { __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ } CoreDebug_Type; /* Debug Halting Control and Status Register Definitions */ #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ /* Debug Core Register Selector Register Definitions */ #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ /* Debug Exception and Monitor Control Register Definitions */ #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ /*@} end of group CMSIS_CoreDebug */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_bitfield Core register bit field macros \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). @{ */ /** \brief Mask and shift a bit field value for use in a register bit range. \param[in] field Name of the register bit field. \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. \return Masked and shifted value. */ #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) /** \brief Mask and shift a register value to extract a bit filed value. \param[in] field Name of the register bit field. \param[in] value Value of register. This parameter is interpreted as an uint32_t type. \return Masked and shifted bit field value. */ #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) /*@} end of group CMSIS_core_bitfield */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_base Core Definitions \brief Definitions for base addresses, unions, and structures. @{ */ /* Memory mapping of Core Hardware */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ #endif #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ /*@} */ /******************************************************************************* * Hardware Abstraction Layer Core Function Interface contains: - Core NVIC Functions - Core SysTick Functions - Core Debug Functions - Core Register Access Functions ******************************************************************************/ /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference */ /* ########################## NVIC functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_NVICFunctions NVIC Functions \brief Functions that manage interrupts and exceptions via the NVIC. @{ */ #ifdef CMSIS_NVIC_VIRTUAL #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" #endif #include CMSIS_NVIC_VIRTUAL_HEADER_FILE #else #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping #define NVIC_EnableIRQ __NVIC_EnableIRQ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ #define NVIC_DisableIRQ __NVIC_DisableIRQ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ #define NVIC_GetActive __NVIC_GetActive #define NVIC_SetPriority __NVIC_SetPriority #define NVIC_GetPriority __NVIC_GetPriority #define NVIC_SystemReset __NVIC_SystemReset #endif /* CMSIS_NVIC_VIRTUAL */ #ifdef CMSIS_VECTAB_VIRTUAL #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" #endif #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE #else #define NVIC_SetVector __NVIC_SetVector #define NVIC_GetVector __NVIC_GetVector #endif /* (CMSIS_VECTAB_VIRTUAL) */ #define NVIC_USER_IRQ_OFFSET 16 /** \brief Set Priority Grouping \details Sets the priority grouping field using the required unlock sequence. The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ reg_value = SCB->AIRCR; /* read old register configuration */ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ SCB->AIRCR = reg_value; } /** \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); } /** \brief Enable Interrupt \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Interrupt Enable status \details Returns a device specific interrupt enable status from the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt is not enabled. \return 1 Interrupt is enabled. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Disable Interrupt \details Disables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __DSB(); __ISB(); } } /** \brief Get Pending Interrupt \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Pending Interrupt \details Sets the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Clear Pending Interrupt \details Clears the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Active Interrupt \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not active. \return 1 Interrupt status is active. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Interrupt Priority \details Sets the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) { NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } else { SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } /** \brief Get Interrupt Priority \details Reads the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); } else { return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); } } /** \brief Encode Priority \details Encodes the priority for an interrupt with the given priority group, preemptive priority value, and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Used priority group. \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) ); } /** \brief Decode Priority \details Decodes an interrupt priority value with a given priority group to preemptive priority value and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). \param [in] PriorityGroup Used priority group. \param [out] pPreemptPriority Preemptive priority value (starting from 0). \param [out] pSubPriority Subpriority value (starting from 0). */ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); } /** \brief Set Interrupt Vector \details Sets an interrupt vector in SRAM based interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. VTOR must been relocated to SRAM before. \param [in] IRQn Interrupt number \param [in] vector Address of interrupt handler function */ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { uint32_t *vectors = (uint32_t *)SCB->VTOR; vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; } /** \brief Get Interrupt Vector \details Reads an interrupt vector from interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Address of interrupt handler function */ __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) { uint32_t *vectors = (uint32_t *)SCB->VTOR; return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; } /** \brief System Reset \details Initiates a system reset request to reset the MCU. */ __STATIC_INLINE void __NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ __DSB(); /* Ensure completion of memory access */ for(;;) /* wait until reset */ { __NOP(); } } /*@} end of CMSIS_Core_NVICFunctions */ /* ########################## MPU functions #################################### */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #include "mpu_armv7.h" #endif /* ########################## FPU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_FpuFunctions FPU Functions \brief Function that provides FPU type. @{ */ /** \brief get FPU type \details returns the FPU type \returns - \b 0: No FPU - \b 1: Single precision FPU - \b 2: Double + Single precision FPU */ __STATIC_INLINE uint32_t SCB_GetFPUType(void) { uint32_t mvfr0; mvfr0 = FPU->MVFR0; if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) { return 1U; /* Single precision FPU */ } else { return 0U; /* No FPU */ } } /*@} end of CMSIS_Core_FpuFunctions */ /* ################################## SysTick function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SysTickFunctions SysTick Functions \brief Functions that configure the System. @{ */ #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) /** \brief System Tick Configuration \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #endif /*@} end of CMSIS_Core_SysTickFunctions */ /* ##################################### Debug In/Output function ########################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_core_DebugFunctions ITM Functions \brief Functions that access the ITM debug interface. @{ */ extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ /** \brief ITM Send Character \details Transmits a character via the ITM channel 0, and \li Just returns when no debugger is connected that has booked the output. \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. \param [in] ch Character to transmit. \returns Character to transmit. */ __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) { if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ { while (ITM->PORT[0U].u32 == 0UL) { __NOP(); } ITM->PORT[0U].u8 = (uint8_t)ch; } return (ch); } /** \brief ITM Receive Character \details Inputs a character via the external variable \ref ITM_RxBuffer. \return Received character. \return -1 No character pending. */ __STATIC_INLINE int32_t ITM_ReceiveChar (void) { int32_t ch = -1; /* no character available */ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { ch = ITM_RxBuffer; ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ } return (ch); } /** \brief ITM Check Character \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. \return 0 No character available. \return 1 Character available. */ __STATIC_INLINE int32_t ITM_CheckChar (void) { if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { return (0); /* no character available */ } else { return (1); /* character available */ } } /*@} end of CMSIS_core_DebugFunctions */ #ifdef __cplusplus } #endif #endif /* __CORE_CM4_H_DEPENDANT */ #endif /* __CMSIS_GENERIC */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/CMSIS/Include/core_cm7.h.
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/**************************************************************************//** * @file core_cm7.h * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File * @version V5.0.5 * @date 08. January 2018 ******************************************************************************/ /* * Copyright (c) 2009-2017 ARM Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__clang__) #pragma clang system_header /* treat file as system include file */ #endif #ifndef __CORE_CM7_H_GENERIC #define __CORE_CM7_H_GENERIC #include <stdint.h> #ifdef __cplusplus extern "C" { #endif /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions CMSIS violates the following MISRA-C:2004 rules: \li Required Rule 8.5, object/function definition in header file.<br> Function definitions in header files are used to allow 'inlining'. \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br> Unions are used for effective representation of core registers. \li Advisory Rule 19.7, Function-like macro defined.<br> Function-like macros are used to allow more efficient code. */ /******************************************************************************* * CMSIS definitions ******************************************************************************/ /** \ingroup Cortex_M7 @{ */ #include "cmsis_version.h" /* CMSIS CM7 definitions */ #define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ #define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ #define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ __CM7_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ #define __CORTEX_M (7U) /*!< Cortex-M Core */ /** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. */ #if defined ( __CC_ARM ) #if defined __TARGET_FPU_VFP #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #if defined __ARM_PCS_VFP #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined ( __GNUC__ ) #if defined (__VFP_FP__) && !defined(__SOFTFP__) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined ( __ICCARM__ ) #if defined __ARMVFP__ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined ( __TI_ARM__ ) #if defined __TI_VFP_SUPPORT__ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined ( __TASKING__ ) #if defined __FPU_VFP__ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined ( __CSMC__ ) #if ( __CSMC__ & 0x400U) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #endif #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ #ifdef __cplusplus } #endif #endif /* __CORE_CM7_H_GENERIC */ #ifndef __CMSIS_GENERIC #ifndef __CORE_CM7_H_DEPENDANT #define __CORE_CM7_H_DEPENDANT #ifdef __cplusplus extern "C" { #endif /* check device defines and use defaults */ #if defined __CHECK_DEVICE_DEFINES #ifndef __CM7_REV #define __CM7_REV 0x0000U #warning "__CM7_REV not defined in device header file; using default!" #endif #ifndef __FPU_PRESENT #define __FPU_PRESENT 0U #warning "__FPU_PRESENT not defined in device header file; using default!" #endif #ifndef __MPU_PRESENT #define __MPU_PRESENT 0U #warning "__MPU_PRESENT not defined in device header file; using default!" #endif #ifndef __ICACHE_PRESENT #define __ICACHE_PRESENT 0U #warning "__ICACHE_PRESENT not defined in device header file; using default!" #endif #ifndef __DCACHE_PRESENT #define __DCACHE_PRESENT 0U #warning "__DCACHE_PRESENT not defined in device header file; using default!" #endif #ifndef __DTCM_PRESENT #define __DTCM_PRESENT 0U #warning "__DTCM_PRESENT not defined in device header file; using default!" #endif #ifndef __NVIC_PRIO_BITS #define __NVIC_PRIO_BITS 3U #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" #endif #ifndef __Vendor_SysTickConfig #define __Vendor_SysTickConfig 0U #warning "__Vendor_SysTickConfig not defined in device header file; using default!" #endif #endif /* IO definitions (access restrictions to peripheral registers) */ /** \defgroup CMSIS_glob_defs CMSIS Global Defines <strong>IO Type Qualifiers</strong> are used \li to specify the access to peripheral variables. \li for automatic generation of peripheral register debug information. */ #ifdef __cplusplus #define __I volatile /*!< Defines 'read only' permissions */ #else #define __I volatile const /*!< Defines 'read only' permissions */ #endif #define __O volatile /*!< Defines 'write only' permissions */ #define __IO volatile /*!< Defines 'read / write' permissions */ /* following defines should be used for structure members */ #define __IM volatile const /*! Defines 'read only' structure member permissions */ #define __OM volatile /*! Defines 'write only' structure member permissions */ #define __IOM volatile /*! Defines 'read / write' structure member permissions */ /*@} end of group Cortex_M7 */ /******************************************************************************* * Register Abstraction Core Register contain: - Core Register - Core NVIC Register - Core SCB Register - Core SysTick Register - Core Debug Register - Core MPU Register - Core FPU Register ******************************************************************************/ /** \defgroup CMSIS_core_register Defines and Type Definitions \brief Type definitions and defines for Cortex-M processor based devices. */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CORE Status and Control Registers \brief Core Register type definitions. @{ */ /** \brief Union type to access the Application Program Status Register (APSR). */ typedef union { struct { uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } APSR_Type; /* APSR Register Definitions */ #define APSR_N_Pos 31U /*!< APSR: N Position */ #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ #define APSR_Z_Pos 30U /*!< APSR: Z Position */ #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ #define APSR_C_Pos 29U /*!< APSR: C Position */ #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ #define APSR_V_Pos 28U /*!< APSR: V Position */ #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ #define APSR_Q_Pos 27U /*!< APSR: Q Position */ #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ #define APSR_GE_Pos 16U /*!< APSR: GE Position */ #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } IPSR_Type; /* IPSR Register Definitions */ #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:1; /*!< bit: 9 Reserved */ uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ uint32_t T:1; /*!< bit: 24 Thumb bit */ uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } xPSR_Type; /* xPSR Register Definitions */ #define xPSR_N_Pos 31U /*!< xPSR: N Position */ #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ #define xPSR_C_Pos 29U /*!< xPSR: C Position */ #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ #define xPSR_V_Pos 28U /*!< xPSR: V Position */ #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ #define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ #define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ #define xPSR_T_Pos 24U /*!< xPSR: T Position */ #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ #define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ #define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ #define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ /** \brief Union type to access the Control Registers (CONTROL). */ typedef union { struct { uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } CONTROL_Type; /* CONTROL Register Definitions */ #define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ /*@} end of group CMSIS_CORE */ /** \ingroup CMSIS_core_register \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \brief Type definitions for the NVIC Registers @{ */ /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). */ typedef struct { __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ uint32_t RESERVED0[24U]; __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ uint32_t RSERVED1[24U]; __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ uint32_t RESERVED2[24U]; __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ uint32_t RESERVED3[24U]; __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ uint32_t RESERVED4[56U]; __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ uint32_t RESERVED5[644U]; __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ } NVIC_Type; /* Software Triggered Interrupt Register Definitions */ #define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ /*@} end of group CMSIS_NVIC */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCB System Control Block (SCB) \brief Type definitions for the System Control Block Registers @{ */ /** \brief Structure type to access the System Control Block (SCB). */ typedef struct { __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ uint32_t RESERVED0[1U]; __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ uint32_t RESERVED3[93U]; __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ uint32_t RESERVED4[15U]; __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ uint32_t RESERVED5[1U]; __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ uint32_t RESERVED6[1U]; __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ uint32_t RESERVED7[6U]; __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ uint32_t RESERVED8[1U]; __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ } SCB_Type; /* SCB CPUID Register Definitions */ #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ /* SCB Vector Table Offset Register Definitions */ #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ /* SCB Application Interrupt and Reset Control Register Definitions */ #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ #define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ /* SCB System Control Register Definitions */ #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ /* SCB Configuration Control Register Definitions */ #define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */ #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ #define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */ #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ #define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */ #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ #define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ /* SCB System Handler Control and State Register Definitions */ #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ /* SCB Configurable Fault Status Register Definitions */ #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ #define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ #define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ #define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ #define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ #define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ /* BusFault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ /* SCB Hard Fault Status Register Definitions */ #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ #define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ /* SCB Debug Fault Status Register Definitions */ #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ /* SCB Cache Level ID Register Definitions */ #define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ #define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ /* SCB Cache Type Register Definitions */ #define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ #define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ #define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ #define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ #define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ #define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ /* SCB Cache Size ID Register Definitions */ #define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ #define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ #define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ #define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ #define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ #define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ #define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ #define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ #define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ #define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ #define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ /* SCB Cache Size Selection Register Definitions */ #define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ #define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ /* SCB Software Triggered Interrupt Register Definitions */ #define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ #define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ /* SCB D-Cache Invalidate by Set-way Register Definitions */ #define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ #define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ #define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ #define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ /* SCB D-Cache Clean by Set-way Register Definitions */ #define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ #define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ #define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ #define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ /* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ #define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ #define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ #define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ #define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ /* Instruction Tightly-Coupled Memory Control Register Definitions */ #define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ #define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ #define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ #define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ #define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ #define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ #define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ #define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ /* Data Tightly-Coupled Memory Control Register Definitions */ #define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ #define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ #define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ #define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ #define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ #define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ #define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ #define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ /* AHBP Control Register Definitions */ #define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ #define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ #define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ #define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ /* L1 Cache Control Register Definitions */ #define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ #define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ #define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ #define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ #define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ #define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ /* AHBS Control Register Definitions */ #define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ #define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ #define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ #define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ #define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ #define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ /* Auxiliary Bus Fault Status Register Definitions */ #define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ #define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ #define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ #define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ #define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ #define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ #define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ #define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ #define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ #define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ #define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ #define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ /*@} end of group CMSIS_SCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) \brief Type definitions for the System Control and ID Register not in the SCB @{ */ /** \brief Structure type to access the System Control and ID Register not in the SCB. */ typedef struct { uint32_t RESERVED0[1U]; __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ } SCnSCB_Type; /* Interrupt Controller Type Register Definitions */ #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ /* Auxiliary Control Register Definitions */ #define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ #define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ #define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */ #define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ #define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ #define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ #define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ /*@} end of group CMSIS_SCnotSCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SysTick System Tick Timer (SysTick) \brief Type definitions for the System Timer Registers. @{ */ /** \brief Structure type to access the System Timer (SysTick). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ } SysTick_Type; /* SysTick Control / Status Register Definitions */ #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ /*@} end of group CMSIS_SysTick */ /** \ingroup CMSIS_core_register \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) \brief Type definitions for the Instrumentation Trace Macrocell (ITM) @{ */ /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). */ typedef struct { __OM union { __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ uint32_t RESERVED0[864U]; __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ uint32_t RESERVED1[15U]; __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ uint32_t RESERVED2[15U]; __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ uint32_t RESERVED3[29U]; __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ uint32_t RESERVED4[43U]; __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ uint32_t RESERVED5[6U]; __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ } ITM_Type; /* ITM Trace Privilege Register Definitions */ #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ #define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ /* ITM Trace Control Register Definitions */ #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ #define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ #define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ #define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ #define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ #define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ /* ITM Integration Write Register Definitions */ #define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ /* ITM Integration Read Register Definitions */ #define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ /* ITM Integration Mode Control Register Definitions */ #define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ /* ITM Lock Status Register Definitions */ #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ #define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ #define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ /*@}*/ /* end of group CMSIS_ITM */ /** \ingroup CMSIS_core_register \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) \brief Type definitions for the Data Watchpoint and Trace (DWT) @{ */ /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ uint32_t RESERVED0[1U]; __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ uint32_t RESERVED1[1U]; __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ uint32_t RESERVED2[1U]; __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ uint32_t RESERVED3[981U]; __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ } DWT_Type; /* DWT Control Register Definitions */ #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ /* DWT CPI Count Register Definitions */ #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ /* DWT Exception Overhead Count Register Definitions */ #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ /* DWT Sleep Count Register Definitions */ #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ /* DWT LSU Count Register Definitions */ #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ /* DWT Folded-instruction Count Register Definitions */ #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ /* DWT Comparator Mask Register Definitions */ #define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ /* DWT Comparator Function Register Definitions */ #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ #define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ #define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ #define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ #define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ #define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ #define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ #define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ /*@}*/ /* end of group CMSIS_DWT */ /** \ingroup CMSIS_core_register \defgroup CMSIS_TPI Trace Port Interface (TPI) \brief Type definitions for the Trace Port Interface (TPI) @{ */ /** \brief Structure type to access the Trace Port Interface Register (TPI). */ typedef struct { __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ uint32_t RESERVED0[2U]; __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ uint32_t RESERVED1[55U]; __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ uint32_t RESERVED2[131U]; __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ uint32_t RESERVED3[759U]; __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ uint32_t RESERVED4[1U]; __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ uint32_t RESERVED5[39U]; __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ uint32_t RESERVED7[8U]; __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ } TPI_Type; /* TPI Asynchronous Clock Prescaler Register Definitions */ #define TPI_ACPR_PRESCALER_Pos 0U /*!< @Deprecated TPI ACPR: PRESCALER Position */ #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< @Deprecated TPI ACPR: PRESCALER Mask */ #define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ #define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ /* TPI Selected Pin Protocol Register Definitions */ #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ /* TPI Formatter and Flush Status Register Definitions */ #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ /* TPI Formatter and Flush Control Register Definitions */ #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ /* TPI TRIGGER Register Definitions */ #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ /* TPI Integration ETM Data Register Definitions (FIFO0) */ #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ /* TPI ITATBCTR2 Register Definitions */ #define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ /* TPI Integration ITM Data Register Definitions (FIFO1) */ #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ /* TPI ITATBCTR0 Register Definitions */ #define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ /* TPI Integration Mode Control Register Definitions */ #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ /* TPI DEVID Register Definitions */ #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ /* TPI DEVTYPE Register Definitions */ #define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ #define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ /*@}*/ /* end of group CMSIS_TPI */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) /** \ingroup CMSIS_core_register \defgroup CMSIS_MPU Memory Protection Unit (MPU) \brief Type definitions for the Memory Protection Unit (MPU) @{ */ /** \brief Structure type to access the Memory Protection Unit (MPU). */ typedef struct { __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ } MPU_Type; #define MPU_TYPE_RALIASES 4U /* MPU Type Register Definitions */ #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ /* MPU Control Register Definitions */ #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ /* MPU Region Number Register Definitions */ #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ /* MPU Region Base Address Register Definitions */ #define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ /* MPU Region Attribute and Size Register Definitions */ #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ /*@} end of group CMSIS_MPU */ #endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ /** \ingroup CMSIS_core_register \defgroup CMSIS_FPU Floating Point Unit (FPU) \brief Type definitions for the Floating Point Unit (FPU) @{ */ /** \brief Structure type to access the Floating Point Unit (FPU). */ typedef struct { uint32_t RESERVED0[1U]; __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ } FPU_Type; /* Floating-Point Context Control Register Definitions */ #define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ #define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ #define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ #define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ #define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ #define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ #define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ #define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ #define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ /* Floating-Point Context Address Register Definitions */ #define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ /* Floating-Point Default Status Control Register Definitions */ #define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ #define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ #define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ #define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ /* Media and FP Feature Register 0 Definitions */ #define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ #define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ #define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ #define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ #define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ #define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ #define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ #define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ /* Media and FP Feature Register 1 Definitions */ #define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ #define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ #define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ #define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ /* Media and FP Feature Register 2 Definitions */ /*@} end of group CMSIS_FPU */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \brief Type definitions for the Core Debug Registers @{ */ /** \brief Structure type to access the Core Debug Register (CoreDebug). */ typedef struct { __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ } CoreDebug_Type; /* Debug Halting Control and Status Register Definitions */ #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ /* Debug Core Register Selector Register Definitions */ #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ /* Debug Exception and Monitor Control Register Definitions */ #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ /*@} end of group CMSIS_CoreDebug */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_bitfield Core register bit field macros \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). @{ */ /** \brief Mask and shift a bit field value for use in a register bit range. \param[in] field Name of the register bit field. \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. \return Masked and shifted value. */ #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) /** \brief Mask and shift a register value to extract a bit filed value. \param[in] field Name of the register bit field. \param[in] value Value of register. This parameter is interpreted as an uint32_t type. \return Masked and shifted bit field value. */ #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) /*@} end of group CMSIS_core_bitfield */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_base Core Definitions \brief Definitions for base addresses, unions, and structures. @{ */ /* Memory mapping of Core Hardware */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ #endif #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ /*@} */ /******************************************************************************* * Hardware Abstraction Layer Core Function Interface contains: - Core NVIC Functions - Core SysTick Functions - Core Debug Functions - Core Register Access Functions ******************************************************************************/ /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference */ /* ########################## NVIC functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_NVICFunctions NVIC Functions \brief Functions that manage interrupts and exceptions via the NVIC. @{ */ #ifdef CMSIS_NVIC_VIRTUAL #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" #endif #include CMSIS_NVIC_VIRTUAL_HEADER_FILE #else #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping #define NVIC_EnableIRQ __NVIC_EnableIRQ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ #define NVIC_DisableIRQ __NVIC_DisableIRQ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ #define NVIC_GetActive __NVIC_GetActive #define NVIC_SetPriority __NVIC_SetPriority #define NVIC_GetPriority __NVIC_GetPriority #define NVIC_SystemReset __NVIC_SystemReset #endif /* CMSIS_NVIC_VIRTUAL */ #ifdef CMSIS_VECTAB_VIRTUAL #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" #endif #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE #else #define NVIC_SetVector __NVIC_SetVector #define NVIC_GetVector __NVIC_GetVector #endif /* (CMSIS_VECTAB_VIRTUAL) */ #define NVIC_USER_IRQ_OFFSET 16 /** \brief Set Priority Grouping \details Sets the priority grouping field using the required unlock sequence. The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ reg_value = SCB->AIRCR; /* read old register configuration */ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ SCB->AIRCR = reg_value; } /** \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); } /** \brief Enable Interrupt \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Interrupt Enable status \details Returns a device specific interrupt enable status from the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt is not enabled. \return 1 Interrupt is enabled. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Disable Interrupt \details Disables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __DSB(); __ISB(); } } /** \brief Get Pending Interrupt \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Pending Interrupt \details Sets the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Clear Pending Interrupt \details Clears the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Active Interrupt \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not active. \return 1 Interrupt status is active. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Interrupt Priority \details Sets the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) { NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } else { SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } /** \brief Get Interrupt Priority \details Reads the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); } else { return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); } } /** \brief Encode Priority \details Encodes the priority for an interrupt with the given priority group, preemptive priority value, and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Used priority group. \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) ); } /** \brief Decode Priority \details Decodes an interrupt priority value with a given priority group to preemptive priority value and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). \param [in] PriorityGroup Used priority group. \param [out] pPreemptPriority Preemptive priority value (starting from 0). \param [out] pSubPriority Subpriority value (starting from 0). */ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); } /** \brief Set Interrupt Vector \details Sets an interrupt vector in SRAM based interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. VTOR must been relocated to SRAM before. \param [in] IRQn Interrupt number \param [in] vector Address of interrupt handler function */ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { uint32_t *vectors = (uint32_t *)SCB->VTOR; vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; } /** \brief Get Interrupt Vector \details Reads an interrupt vector from interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Address of interrupt handler function */ __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) { uint32_t *vectors = (uint32_t *)SCB->VTOR; return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; } /** \brief System Reset \details Initiates a system reset request to reset the MCU. */ __STATIC_INLINE void __NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ __DSB(); /* Ensure completion of memory access */ for(;;) /* wait until reset */ { __NOP(); } } /*@} end of CMSIS_Core_NVICFunctions */ /* ########################## MPU functions #################################### */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #include "mpu_armv7.h" #endif /* ########################## FPU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_FpuFunctions FPU Functions \brief Function that provides FPU type. @{ */ /** \brief get FPU type \details returns the FPU type \returns - \b 0: No FPU - \b 1: Single precision FPU - \b 2: Double + Single precision FPU */ __STATIC_INLINE uint32_t SCB_GetFPUType(void) { uint32_t mvfr0; mvfr0 = SCB->MVFR0; if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) { return 2U; /* Double + Single precision FPU */ } else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) { return 1U; /* Single precision FPU */ } else { return 0U; /* No FPU */ } } /*@} end of CMSIS_Core_FpuFunctions */ /* ########################## Cache functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_CacheFunctions Cache Functions \brief Functions that configure Instruction and Data cache. @{ */ /* Cache Size ID Register Macros */ #define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) #define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) /** \brief Enable I-Cache \details Turns on I-Cache */ __STATIC_INLINE void SCB_EnableICache (void) { #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) __DSB(); __ISB(); SCB->ICIALLU = 0UL; /* invalidate I-Cache */ __DSB(); __ISB(); SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ __DSB(); __ISB(); #endif } /** \brief Disable I-Cache \details Turns off I-Cache */ __STATIC_INLINE void SCB_DisableICache (void) { #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) __DSB(); __ISB(); SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ SCB->ICIALLU = 0UL; /* invalidate I-Cache */ __DSB(); __ISB(); #endif } /** \brief Invalidate I-Cache \details Invalidates I-Cache */ __STATIC_INLINE void SCB_InvalidateICache (void) { #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) __DSB(); __ISB(); SCB->ICIALLU = 0UL; __DSB(); __ISB(); #endif } /** \brief Enable D-Cache \details Turns on D-Cache */ __STATIC_INLINE void SCB_EnableDCache (void) { #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) uint32_t ccsidr; uint32_t sets; uint32_t ways; SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ __DSB(); ccsidr = SCB->CCSIDR; /* invalidate D-Cache */ sets = (uint32_t)(CCSIDR_SETS(ccsidr)); do { ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); do { SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); #if defined ( __CC_ARM ) __schedule_barrier(); #endif } while (ways-- != 0U); } while(sets-- != 0U); __DSB(); SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ __DSB(); __ISB(); #endif } /** \brief Disable D-Cache \details Turns off D-Cache */ __STATIC_INLINE void SCB_DisableDCache (void) { #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) register uint32_t ccsidr; register uint32_t sets; register uint32_t ways; SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ __DSB(); SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ __DSB(); ccsidr = SCB->CCSIDR; /* clean & invalidate D-Cache */ sets = (uint32_t)(CCSIDR_SETS(ccsidr)); do { ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); do { SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); #if defined ( __CC_ARM ) __schedule_barrier(); #endif } while (ways-- != 0U); } while(sets-- != 0U); __DSB(); __ISB(); #endif } /** \brief Invalidate D-Cache \details Invalidates D-Cache */ __STATIC_INLINE void SCB_InvalidateDCache (void) { #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) uint32_t ccsidr; uint32_t sets; uint32_t ways; SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ __DSB(); ccsidr = SCB->CCSIDR; /* invalidate D-Cache */ sets = (uint32_t)(CCSIDR_SETS(ccsidr)); do { ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); do { SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); #if defined ( __CC_ARM ) __schedule_barrier(); #endif } while (ways-- != 0U); } while(sets-- != 0U); __DSB(); __ISB(); #endif } /** \brief Clean D-Cache \details Cleans D-Cache */ __STATIC_INLINE void SCB_CleanDCache (void) { #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) uint32_t ccsidr; uint32_t sets; uint32_t ways; SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ __DSB(); ccsidr = SCB->CCSIDR; /* clean D-Cache */ sets = (uint32_t)(CCSIDR_SETS(ccsidr)); do { ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); do { SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); #if defined ( __CC_ARM ) __schedule_barrier(); #endif } while (ways-- != 0U); } while(sets-- != 0U); __DSB(); __ISB(); #endif } /** \brief Clean & Invalidate D-Cache \details Cleans and Invalidates D-Cache */ __STATIC_INLINE void SCB_CleanInvalidateDCache (void) { #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) uint32_t ccsidr; uint32_t sets; uint32_t ways; SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ __DSB(); ccsidr = SCB->CCSIDR; /* clean & invalidate D-Cache */ sets = (uint32_t)(CCSIDR_SETS(ccsidr)); do { ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); do { SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); #if defined ( __CC_ARM ) __schedule_barrier(); #endif } while (ways-- != 0U); } while(sets-- != 0U); __DSB(); __ISB(); #endif } /** \brief D-Cache Invalidate by address \details Invalidates D-Cache for the given address \param[in] addr address (aligned to 32-byte boundary) \param[in] dsize size of memory block (in number of bytes) */ __STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) { #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) int32_t op_size = dsize; uint32_t op_addr = (uint32_t)addr; int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ __DSB(); while (op_size > 0) { SCB->DCIMVAC = op_addr; op_addr += (uint32_t)linesize; op_size -= linesize; } __DSB(); __ISB(); #endif } /** \brief D-Cache Clean by address \details Cleans D-Cache for the given address \param[in] addr address (aligned to 32-byte boundary) \param[in] dsize size of memory block (in number of bytes) */ __STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) { #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) int32_t op_size = dsize; uint32_t op_addr = (uint32_t) addr; int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ __DSB(); while (op_size > 0) { SCB->DCCMVAC = op_addr; op_addr += (uint32_t)linesize; op_size -= linesize; } __DSB(); __ISB(); #endif } /** \brief D-Cache Clean and Invalidate by address \details Cleans and invalidates D_Cache for the given address \param[in] addr address (aligned to 32-byte boundary) \param[in] dsize size of memory block (in number of bytes) */ __STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) { #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) int32_t op_size = dsize; uint32_t op_addr = (uint32_t) addr; int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ __DSB(); while (op_size > 0) { SCB->DCCIMVAC = op_addr; op_addr += (uint32_t)linesize; op_size -= linesize; } __DSB(); __ISB(); #endif } /*@} end of CMSIS_Core_CacheFunctions */ /* ################################## SysTick function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SysTickFunctions SysTick Functions \brief Functions that configure the System. @{ */ #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) /** \brief System Tick Configuration \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #endif /*@} end of CMSIS_Core_SysTickFunctions */ /* ##################################### Debug In/Output function ########################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_core_DebugFunctions ITM Functions \brief Functions that access the ITM debug interface. @{ */ extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ /** \brief ITM Send Character \details Transmits a character via the ITM channel 0, and \li Just returns when no debugger is connected that has booked the output. \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. \param [in] ch Character to transmit. \returns Character to transmit. */ __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) { if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ { while (ITM->PORT[0U].u32 == 0UL) { __NOP(); } ITM->PORT[0U].u8 = (uint8_t)ch; } return (ch); } /** \brief ITM Receive Character \details Inputs a character via the external variable \ref ITM_RxBuffer. \return Received character. \return -1 No character pending. */ __STATIC_INLINE int32_t ITM_ReceiveChar (void) { int32_t ch = -1; /* no character available */ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { ch = ITM_RxBuffer; ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ } return (ch); } /** \brief ITM Check Character \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. \return 0 No character available. \return 1 Character available. */ __STATIC_INLINE int32_t ITM_CheckChar (void) { if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { return (0); /* no character available */ } else { return (1); /* character available */ } } /*@} end of CMSIS_core_DebugFunctions */ #ifdef __cplusplus } #endif #endif /* __CORE_CM7_H_DEPENDANT */ #endif /* __CMSIS_GENERIC */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/CMSIS/Include/core_sc000.h.
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/**************************************************************************//** * @file core_sc000.h * @brief CMSIS SC000 Core Peripheral Access Layer Header File * @version V5.0.3 * @date 10. January 2018 ******************************************************************************/ /* * Copyright (c) 2009-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__clang__) #pragma clang system_header /* treat file as system include file */ #endif #ifndef __CORE_SC000_H_GENERIC #define __CORE_SC000_H_GENERIC #include <stdint.h> #ifdef __cplusplus extern "C" { #endif /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions CMSIS violates the following MISRA-C:2004 rules: \li Required Rule 8.5, object/function definition in header file.<br> Function definitions in header files are used to allow 'inlining'. \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br> Unions are used for effective representation of core registers. \li Advisory Rule 19.7, Function-like macro defined.<br> Function-like macros are used to allow more efficient code. */ /******************************************************************************* * CMSIS definitions ******************************************************************************/ /** \ingroup SC000 @{ */ #include "cmsis_version.h" /* CMSIS SC000 definitions */ #define __SC000_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ #define __SC000_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ #define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \ __SC000_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ #define __CORTEX_SC (000U) /*!< Cortex secure core */ /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all */ #define __FPU_USED 0U #if defined ( __CC_ARM ) #if defined __TARGET_FPU_VFP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #if defined __ARM_PCS_VFP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __GNUC__ ) #if defined (__VFP_FP__) && !defined(__SOFTFP__) #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __ICCARM__ ) #if defined __ARMVFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __TI_ARM__ ) #if defined __TI_VFP_SUPPORT__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __TASKING__ ) #if defined __FPU_VFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __CSMC__ ) #if ( __CSMC__ & 0x400U) #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #endif #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ #ifdef __cplusplus } #endif #endif /* __CORE_SC000_H_GENERIC */ #ifndef __CMSIS_GENERIC #ifndef __CORE_SC000_H_DEPENDANT #define __CORE_SC000_H_DEPENDANT #ifdef __cplusplus extern "C" { #endif /* check device defines and use defaults */ #if defined __CHECK_DEVICE_DEFINES #ifndef __SC000_REV #define __SC000_REV 0x0000U #warning "__SC000_REV not defined in device header file; using default!" #endif #ifndef __MPU_PRESENT #define __MPU_PRESENT 0U #warning "__MPU_PRESENT not defined in device header file; using default!" #endif #ifndef __NVIC_PRIO_BITS #define __NVIC_PRIO_BITS 2U #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" #endif #ifndef __Vendor_SysTickConfig #define __Vendor_SysTickConfig 0U #warning "__Vendor_SysTickConfig not defined in device header file; using default!" #endif #endif /* IO definitions (access restrictions to peripheral registers) */ /** \defgroup CMSIS_glob_defs CMSIS Global Defines <strong>IO Type Qualifiers</strong> are used \li to specify the access to peripheral variables. \li for automatic generation of peripheral register debug information. */ #ifdef __cplusplus #define __I volatile /*!< Defines 'read only' permissions */ #else #define __I volatile const /*!< Defines 'read only' permissions */ #endif #define __O volatile /*!< Defines 'write only' permissions */ #define __IO volatile /*!< Defines 'read / write' permissions */ /* following defines should be used for structure members */ #define __IM volatile const /*! Defines 'read only' structure member permissions */ #define __OM volatile /*! Defines 'write only' structure member permissions */ #define __IOM volatile /*! Defines 'read / write' structure member permissions */ /*@} end of group SC000 */ /******************************************************************************* * Register Abstraction Core Register contain: - Core Register - Core NVIC Register - Core SCB Register - Core SysTick Register - Core MPU Register ******************************************************************************/ /** \defgroup CMSIS_core_register Defines and Type Definitions \brief Type definitions and defines for Cortex-M processor based devices. */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CORE Status and Control Registers \brief Core Register type definitions. @{ */ /** \brief Union type to access the Application Program Status Register (APSR). */ typedef union { struct { uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } APSR_Type; /* APSR Register Definitions */ #define APSR_N_Pos 31U /*!< APSR: N Position */ #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ #define APSR_Z_Pos 30U /*!< APSR: Z Position */ #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ #define APSR_C_Pos 29U /*!< APSR: C Position */ #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ #define APSR_V_Pos 28U /*!< APSR: V Position */ #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } IPSR_Type; /* IPSR Register Definitions */ #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } xPSR_Type; /* xPSR Register Definitions */ #define xPSR_N_Pos 31U /*!< xPSR: N Position */ #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ #define xPSR_C_Pos 29U /*!< xPSR: C Position */ #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ #define xPSR_V_Pos 28U /*!< xPSR: V Position */ #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ #define xPSR_T_Pos 24U /*!< xPSR: T Position */ #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ /** \brief Union type to access the Control Registers (CONTROL). */ typedef union { struct { uint32_t _reserved0:1; /*!< bit: 0 Reserved */ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } CONTROL_Type; /* CONTROL Register Definitions */ #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ /*@} end of group CMSIS_CORE */ /** \ingroup CMSIS_core_register \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \brief Type definitions for the NVIC Registers @{ */ /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). */ typedef struct { __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ uint32_t RESERVED0[31U]; __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ uint32_t RSERVED1[31U]; __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ uint32_t RESERVED2[31U]; __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ uint32_t RESERVED3[31U]; uint32_t RESERVED4[64U]; __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ } NVIC_Type; /*@} end of group CMSIS_NVIC */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCB System Control Block (SCB) \brief Type definitions for the System Control Block Registers @{ */ /** \brief Structure type to access the System Control Block (SCB). */ typedef struct { __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ uint32_t RESERVED0[1U]; __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ uint32_t RESERVED1[154U]; __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ } SCB_Type; /* SCB CPUID Register Definitions */ #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ /* SCB Application Interrupt and Reset Control Register Definitions */ #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ /* SCB System Control Register Definitions */ #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ /* SCB Configuration Control Register Definitions */ #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ /* SCB System Handler Control and State Register Definitions */ #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ /*@} end of group CMSIS_SCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) \brief Type definitions for the System Control and ID Register not in the SCB @{ */ /** \brief Structure type to access the System Control and ID Register not in the SCB. */ typedef struct { uint32_t RESERVED0[2U]; __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ } SCnSCB_Type; /* Auxiliary Control Register Definitions */ #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ /*@} end of group CMSIS_SCnotSCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SysTick System Tick Timer (SysTick) \brief Type definitions for the System Timer Registers. @{ */ /** \brief Structure type to access the System Timer (SysTick). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ } SysTick_Type; /* SysTick Control / Status Register Definitions */ #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ /*@} end of group CMSIS_SysTick */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) /** \ingroup CMSIS_core_register \defgroup CMSIS_MPU Memory Protection Unit (MPU) \brief Type definitions for the Memory Protection Unit (MPU) @{ */ /** \brief Structure type to access the Memory Protection Unit (MPU). */ typedef struct { __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ } MPU_Type; /* MPU Type Register Definitions */ #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ /* MPU Control Register Definitions */ #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ /* MPU Region Number Register Definitions */ #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ /* MPU Region Base Address Register Definitions */ #define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ /* MPU Region Attribute and Size Register Definitions */ #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ /*@} end of group CMSIS_MPU */ #endif /** \ingroup CMSIS_core_register \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. Therefore they are not covered by the SC000 header file. @{ */ /*@} end of group CMSIS_CoreDebug */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_bitfield Core register bit field macros \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). @{ */ /** \brief Mask and shift a bit field value for use in a register bit range. \param[in] field Name of the register bit field. \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. \return Masked and shifted value. */ #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) /** \brief Mask and shift a register value to extract a bit filed value. \param[in] field Name of the register bit field. \param[in] value Value of register. This parameter is interpreted as an uint32_t type. \return Masked and shifted bit field value. */ #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) /*@} end of group CMSIS_core_bitfield */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_base Core Definitions \brief Definitions for base addresses, unions, and structures. @{ */ /* Memory mapping of Core Hardware */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ #endif /*@} */ /******************************************************************************* * Hardware Abstraction Layer Core Function Interface contains: - Core NVIC Functions - Core SysTick Functions - Core Register Access Functions ******************************************************************************/ /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference */ /* ########################## NVIC functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_NVICFunctions NVIC Functions \brief Functions that manage interrupts and exceptions via the NVIC. @{ */ #ifdef CMSIS_NVIC_VIRTUAL #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" #endif #include CMSIS_NVIC_VIRTUAL_HEADER_FILE #else /*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */ /*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */ #define NVIC_EnableIRQ __NVIC_EnableIRQ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ #define NVIC_DisableIRQ __NVIC_DisableIRQ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ /*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */ #define NVIC_SetPriority __NVIC_SetPriority #define NVIC_GetPriority __NVIC_GetPriority #define NVIC_SystemReset __NVIC_SystemReset #endif /* CMSIS_NVIC_VIRTUAL */ #ifdef CMSIS_VECTAB_VIRTUAL #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" #endif #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE #else #define NVIC_SetVector __NVIC_SetVector #define NVIC_GetVector __NVIC_GetVector #endif /* (CMSIS_VECTAB_VIRTUAL) */ #define NVIC_USER_IRQ_OFFSET 16 /* Interrupt Priorities are WORD accessible only under Armv6-M */ /* The following MACROS handle generation of the register offset and byte masks */ #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) /** \brief Enable Interrupt \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Interrupt Enable status \details Returns a device specific interrupt enable status from the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt is not enabled. \return 1 Interrupt is enabled. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Disable Interrupt \details Disables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __DSB(); __ISB(); } } /** \brief Get Pending Interrupt \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Pending Interrupt \details Sets the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Clear Pending Interrupt \details Clears the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Set Interrupt Priority \details Sets the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) { NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } else { SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } } /** \brief Get Interrupt Priority \details Reads the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); } else { return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); } } /** \brief Set Interrupt Vector \details Sets an interrupt vector in SRAM based interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. VTOR must been relocated to SRAM before. \param [in] IRQn Interrupt number \param [in] vector Address of interrupt handler function */ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { uint32_t *vectors = (uint32_t *)SCB->VTOR; vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; } /** \brief Get Interrupt Vector \details Reads an interrupt vector from interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Address of interrupt handler function */ __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) { uint32_t *vectors = (uint32_t *)SCB->VTOR; return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; } /** \brief System Reset \details Initiates a system reset request to reset the MCU. */ __STATIC_INLINE void __NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | SCB_AIRCR_SYSRESETREQ_Msk); __DSB(); /* Ensure completion of memory access */ for(;;) /* wait until reset */ { __NOP(); } } /*@} end of CMSIS_Core_NVICFunctions */ /* ########################## FPU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_FpuFunctions FPU Functions \brief Function that provides FPU type. @{ */ /** \brief get FPU type \details returns the FPU type \returns - \b 0: No FPU - \b 1: Single precision FPU - \b 2: Double + Single precision FPU */ __STATIC_INLINE uint32_t SCB_GetFPUType(void) { return 0U; /* No FPU */ } /*@} end of CMSIS_Core_FpuFunctions */ /* ################################## SysTick function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SysTickFunctions SysTick Functions \brief Functions that configure the System. @{ */ #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) /** \brief System Tick Configuration \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #endif /*@} end of CMSIS_Core_SysTickFunctions */ #ifdef __cplusplus } #endif #endif /* __CORE_SC000_H_DEPENDANT */ #endif /* __CMSIS_GENERIC */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/CMSIS/Include/core_sc300.h.
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/**************************************************************************//** * @file core_sc300.h * @brief CMSIS SC300 Core Peripheral Access Layer Header File * @version V5.0.3 * @date 10. January 2018 ******************************************************************************/ /* * Copyright (c) 2009-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__clang__) #pragma clang system_header /* treat file as system include file */ #endif #ifndef __CORE_SC300_H_GENERIC #define __CORE_SC300_H_GENERIC #include <stdint.h> #ifdef __cplusplus extern "C" { #endif /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions CMSIS violates the following MISRA-C:2004 rules: \li Required Rule 8.5, object/function definition in header file.<br> Function definitions in header files are used to allow 'inlining'. \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br> Unions are used for effective representation of core registers. \li Advisory Rule 19.7, Function-like macro defined.<br> Function-like macros are used to allow more efficient code. */ /******************************************************************************* * CMSIS definitions ******************************************************************************/ /** \ingroup SC3000 @{ */ #include "cmsis_version.h" /* CMSIS SC300 definitions */ #define __SC300_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ #define __SC300_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ #define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \ __SC300_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ #define __CORTEX_SC (300U) /*!< Cortex secure core */ /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all */ #define __FPU_USED 0U #if defined ( __CC_ARM ) #if defined __TARGET_FPU_VFP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #if defined __ARM_PCS_VFP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __GNUC__ ) #if defined (__VFP_FP__) && !defined(__SOFTFP__) #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __ICCARM__ ) #if defined __ARMVFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __TI_ARM__ ) #if defined __TI_VFP_SUPPORT__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __TASKING__ ) #if defined __FPU_VFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __CSMC__ ) #if ( __CSMC__ & 0x400U) #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #endif #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ #ifdef __cplusplus } #endif #endif /* __CORE_SC300_H_GENERIC */ #ifndef __CMSIS_GENERIC #ifndef __CORE_SC300_H_DEPENDANT #define __CORE_SC300_H_DEPENDANT #ifdef __cplusplus extern "C" { #endif /* check device defines and use defaults */ #if defined __CHECK_DEVICE_DEFINES #ifndef __SC300_REV #define __SC300_REV 0x0000U #warning "__SC300_REV not defined in device header file; using default!" #endif #ifndef __MPU_PRESENT #define __MPU_PRESENT 0U #warning "__MPU_PRESENT not defined in device header file; using default!" #endif #ifndef __NVIC_PRIO_BITS #define __NVIC_PRIO_BITS 3U #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" #endif #ifndef __Vendor_SysTickConfig #define __Vendor_SysTickConfig 0U #warning "__Vendor_SysTickConfig not defined in device header file; using default!" #endif #endif /* IO definitions (access restrictions to peripheral registers) */ /** \defgroup CMSIS_glob_defs CMSIS Global Defines <strong>IO Type Qualifiers</strong> are used \li to specify the access to peripheral variables. \li for automatic generation of peripheral register debug information. */ #ifdef __cplusplus #define __I volatile /*!< Defines 'read only' permissions */ #else #define __I volatile const /*!< Defines 'read only' permissions */ #endif #define __O volatile /*!< Defines 'write only' permissions */ #define __IO volatile /*!< Defines 'read / write' permissions */ /* following defines should be used for structure members */ #define __IM volatile const /*! Defines 'read only' structure member permissions */ #define __OM volatile /*! Defines 'write only' structure member permissions */ #define __IOM volatile /*! Defines 'read / write' structure member permissions */ /*@} end of group SC300 */ /******************************************************************************* * Register Abstraction Core Register contain: - Core Register - Core NVIC Register - Core SCB Register - Core SysTick Register - Core Debug Register - Core MPU Register ******************************************************************************/ /** \defgroup CMSIS_core_register Defines and Type Definitions \brief Type definitions and defines for Cortex-M processor based devices. */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CORE Status and Control Registers \brief Core Register type definitions. @{ */ /** \brief Union type to access the Application Program Status Register (APSR). */ typedef union { struct { uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } APSR_Type; /* APSR Register Definitions */ #define APSR_N_Pos 31U /*!< APSR: N Position */ #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ #define APSR_Z_Pos 30U /*!< APSR: Z Position */ #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ #define APSR_C_Pos 29U /*!< APSR: C Position */ #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ #define APSR_V_Pos 28U /*!< APSR: V Position */ #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ #define APSR_Q_Pos 27U /*!< APSR: Q Position */ #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } IPSR_Type; /* IPSR Register Definitions */ #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:1; /*!< bit: 9 Reserved */ uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ uint32_t T:1; /*!< bit: 24 Thumb bit */ uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } xPSR_Type; /* xPSR Register Definitions */ #define xPSR_N_Pos 31U /*!< xPSR: N Position */ #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ #define xPSR_C_Pos 29U /*!< xPSR: C Position */ #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ #define xPSR_V_Pos 28U /*!< xPSR: V Position */ #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ #define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ #define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ #define xPSR_T_Pos 24U /*!< xPSR: T Position */ #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ #define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ #define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ /** \brief Union type to access the Control Registers (CONTROL). */ typedef union { struct { uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } CONTROL_Type; /* CONTROL Register Definitions */ #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ /*@} end of group CMSIS_CORE */ /** \ingroup CMSIS_core_register \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \brief Type definitions for the NVIC Registers @{ */ /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). */ typedef struct { __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ uint32_t RESERVED0[24U]; __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ uint32_t RSERVED1[24U]; __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ uint32_t RESERVED2[24U]; __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ uint32_t RESERVED3[24U]; __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ uint32_t RESERVED4[56U]; __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ uint32_t RESERVED5[644U]; __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ } NVIC_Type; /* Software Triggered Interrupt Register Definitions */ #define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ /*@} end of group CMSIS_NVIC */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCB System Control Block (SCB) \brief Type definitions for the System Control Block Registers @{ */ /** \brief Structure type to access the System Control Block (SCB). */ typedef struct { __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ uint32_t RESERVED0[5U]; __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ uint32_t RESERVED1[129U]; __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ } SCB_Type; /* SCB CPUID Register Definitions */ #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ /* SCB Vector Table Offset Register Definitions */ #define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ #define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ #define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ /* SCB Application Interrupt and Reset Control Register Definitions */ #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ #define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ /* SCB System Control Register Definitions */ #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ /* SCB Configuration Control Register Definitions */ #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ #define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ /* SCB System Handler Control and State Register Definitions */ #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ /* SCB Configurable Fault Status Register Definitions */ #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ #define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ #define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ #define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ #define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ /* BusFault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ /* SCB Hard Fault Status Register Definitions */ #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ #define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ /* SCB Debug Fault Status Register Definitions */ #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ /*@} end of group CMSIS_SCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) \brief Type definitions for the System Control and ID Register not in the SCB @{ */ /** \brief Structure type to access the System Control and ID Register not in the SCB. */ typedef struct { uint32_t RESERVED0[1U]; __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ uint32_t RESERVED1[1U]; } SCnSCB_Type; /* Interrupt Controller Type Register Definitions */ #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ /*@} end of group CMSIS_SCnotSCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SysTick System Tick Timer (SysTick) \brief Type definitions for the System Timer Registers. @{ */ /** \brief Structure type to access the System Timer (SysTick). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ } SysTick_Type; /* SysTick Control / Status Register Definitions */ #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ /*@} end of group CMSIS_SysTick */ /** \ingroup CMSIS_core_register \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) \brief Type definitions for the Instrumentation Trace Macrocell (ITM) @{ */ /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). */ typedef struct { __OM union { __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ uint32_t RESERVED0[864U]; __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ uint32_t RESERVED1[15U]; __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ uint32_t RESERVED2[15U]; __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ uint32_t RESERVED3[29U]; __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ uint32_t RESERVED4[43U]; __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ uint32_t RESERVED5[6U]; __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ } ITM_Type; /* ITM Trace Privilege Register Definitions */ #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ /* ITM Trace Control Register Definitions */ #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ #define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ #define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ #define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ #define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ #define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ /* ITM Integration Write Register Definitions */ #define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ /* ITM Integration Read Register Definitions */ #define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ /* ITM Integration Mode Control Register Definitions */ #define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ /* ITM Lock Status Register Definitions */ #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ #define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ #define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ /*@}*/ /* end of group CMSIS_ITM */ /** \ingroup CMSIS_core_register \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) \brief Type definitions for the Data Watchpoint and Trace (DWT) @{ */ /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ uint32_t RESERVED0[1U]; __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ uint32_t RESERVED1[1U]; __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ uint32_t RESERVED2[1U]; __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ } DWT_Type; /* DWT Control Register Definitions */ #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ /* DWT CPI Count Register Definitions */ #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ /* DWT Exception Overhead Count Register Definitions */ #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ /* DWT Sleep Count Register Definitions */ #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ /* DWT LSU Count Register Definitions */ #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ /* DWT Folded-instruction Count Register Definitions */ #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ /* DWT Comparator Mask Register Definitions */ #define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ /* DWT Comparator Function Register Definitions */ #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ #define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ #define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ #define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ #define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ #define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ #define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ #define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ /*@}*/ /* end of group CMSIS_DWT */ /** \ingroup CMSIS_core_register \defgroup CMSIS_TPI Trace Port Interface (TPI) \brief Type definitions for the Trace Port Interface (TPI) @{ */ /** \brief Structure type to access the Trace Port Interface Register (TPI). */ typedef struct { __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ uint32_t RESERVED0[2U]; __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ uint32_t RESERVED1[55U]; __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ uint32_t RESERVED2[131U]; __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ uint32_t RESERVED3[759U]; __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ uint32_t RESERVED4[1U]; __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ uint32_t RESERVED5[39U]; __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ uint32_t RESERVED7[8U]; __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ } TPI_Type; /* TPI Asynchronous Clock Prescaler Register Definitions */ #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ /* TPI Selected Pin Protocol Register Definitions */ #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ /* TPI Formatter and Flush Status Register Definitions */ #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ /* TPI Formatter and Flush Control Register Definitions */ #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ /* TPI TRIGGER Register Definitions */ #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ /* TPI Integration ETM Data Register Definitions (FIFO0) */ #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ /* TPI ITATBCTR2 Register Definitions */ #define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ /* TPI Integration ITM Data Register Definitions (FIFO1) */ #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ /* TPI ITATBCTR0 Register Definitions */ #define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ /* TPI Integration Mode Control Register Definitions */ #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ /* TPI DEVID Register Definitions */ #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ /* TPI DEVTYPE Register Definitions */ #define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ #define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ /*@}*/ /* end of group CMSIS_TPI */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) /** \ingroup CMSIS_core_register \defgroup CMSIS_MPU Memory Protection Unit (MPU) \brief Type definitions for the Memory Protection Unit (MPU) @{ */ /** \brief Structure type to access the Memory Protection Unit (MPU). */ typedef struct { __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ } MPU_Type; /* MPU Type Register Definitions */ #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ /* MPU Control Register Definitions */ #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ /* MPU Region Number Register Definitions */ #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ /* MPU Region Base Address Register Definitions */ #define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ /* MPU Region Attribute and Size Register Definitions */ #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ /*@} end of group CMSIS_MPU */ #endif /** \ingroup CMSIS_core_register \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \brief Type definitions for the Core Debug Registers @{ */ /** \brief Structure type to access the Core Debug Register (CoreDebug). */ typedef struct { __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ } CoreDebug_Type; /* Debug Halting Control and Status Register Definitions */ #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ /* Debug Core Register Selector Register Definitions */ #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ /* Debug Exception and Monitor Control Register Definitions */ #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ /*@} end of group CMSIS_CoreDebug */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_bitfield Core register bit field macros \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). @{ */ /** \brief Mask and shift a bit field value for use in a register bit range. \param[in] field Name of the register bit field. \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. \return Masked and shifted value. */ #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) /** \brief Mask and shift a register value to extract a bit filed value. \param[in] field Name of the register bit field. \param[in] value Value of register. This parameter is interpreted as an uint32_t type. \return Masked and shifted bit field value. */ #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) /*@} end of group CMSIS_core_bitfield */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_base Core Definitions \brief Definitions for base addresses, unions, and structures. @{ */ /* Memory mapping of Core Hardware */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ #endif /*@} */ /******************************************************************************* * Hardware Abstraction Layer Core Function Interface contains: - Core NVIC Functions - Core SysTick Functions - Core Debug Functions - Core Register Access Functions ******************************************************************************/ /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference */ /* ########################## NVIC functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_NVICFunctions NVIC Functions \brief Functions that manage interrupts and exceptions via the NVIC. @{ */ #ifdef CMSIS_NVIC_VIRTUAL #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" #endif #include CMSIS_NVIC_VIRTUAL_HEADER_FILE #else #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping #define NVIC_EnableIRQ __NVIC_EnableIRQ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ #define NVIC_DisableIRQ __NVIC_DisableIRQ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ #define NVIC_GetActive __NVIC_GetActive #define NVIC_SetPriority __NVIC_SetPriority #define NVIC_GetPriority __NVIC_GetPriority #define NVIC_SystemReset __NVIC_SystemReset #endif /* CMSIS_NVIC_VIRTUAL */ #ifdef CMSIS_VECTAB_VIRTUAL #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" #endif #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE #else #define NVIC_SetVector __NVIC_SetVector #define NVIC_GetVector __NVIC_GetVector #endif /* (CMSIS_VECTAB_VIRTUAL) */ #define NVIC_USER_IRQ_OFFSET 16 /** \brief Set Priority Grouping \details Sets the priority grouping field using the required unlock sequence. The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ reg_value = SCB->AIRCR; /* read old register configuration */ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ SCB->AIRCR = reg_value; } /** \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); } /** \brief Enable Interrupt \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Interrupt Enable status \details Returns a device specific interrupt enable status from the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt is not enabled. \return 1 Interrupt is enabled. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Disable Interrupt \details Disables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __DSB(); __ISB(); } } /** \brief Get Pending Interrupt \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Pending Interrupt \details Sets the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Clear Pending Interrupt \details Clears the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Active Interrupt \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not active. \return 1 Interrupt status is active. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Interrupt Priority \details Sets the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) { NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } else { SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } /** \brief Get Interrupt Priority \details Reads the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); } else { return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); } } /** \brief Encode Priority \details Encodes the priority for an interrupt with the given priority group, preemptive priority value, and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Used priority group. \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) ); } /** \brief Decode Priority \details Decodes an interrupt priority value with a given priority group to preemptive priority value and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). \param [in] PriorityGroup Used priority group. \param [out] pPreemptPriority Preemptive priority value (starting from 0). \param [out] pSubPriority Subpriority value (starting from 0). */ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); } /** \brief Set Interrupt Vector \details Sets an interrupt vector in SRAM based interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. VTOR must been relocated to SRAM before. \param [in] IRQn Interrupt number \param [in] vector Address of interrupt handler function */ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { uint32_t *vectors = (uint32_t *)SCB->VTOR; vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; } /** \brief Get Interrupt Vector \details Reads an interrupt vector from interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Address of interrupt handler function */ __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) { uint32_t *vectors = (uint32_t *)SCB->VTOR; return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; } /** \brief System Reset \details Initiates a system reset request to reset the MCU. */ __STATIC_INLINE void __NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ __DSB(); /* Ensure completion of memory access */ for(;;) /* wait until reset */ { __NOP(); } } /*@} end of CMSIS_Core_NVICFunctions */ /* ########################## FPU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_FpuFunctions FPU Functions \brief Function that provides FPU type. @{ */ /** \brief get FPU type \details returns the FPU type \returns - \b 0: No FPU - \b 1: Single precision FPU - \b 2: Double + Single precision FPU */ __STATIC_INLINE uint32_t SCB_GetFPUType(void) { return 0U; /* No FPU */ } /*@} end of CMSIS_Core_FpuFunctions */ /* ################################## SysTick function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SysTickFunctions SysTick Functions \brief Functions that configure the System. @{ */ #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) /** \brief System Tick Configuration \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #endif /*@} end of CMSIS_Core_SysTickFunctions */ /* ##################################### Debug In/Output function ########################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_core_DebugFunctions ITM Functions \brief Functions that access the ITM debug interface. @{ */ extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ /** \brief ITM Send Character \details Transmits a character via the ITM channel 0, and \li Just returns when no debugger is connected that has booked the output. \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. \param [in] ch Character to transmit. \returns Character to transmit. */ __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) { if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ { while (ITM->PORT[0U].u32 == 0UL) { __NOP(); } ITM->PORT[0U].u8 = (uint8_t)ch; } return (ch); } /** \brief ITM Receive Character \details Inputs a character via the external variable \ref ITM_RxBuffer. \return Received character. \return -1 No character pending. */ __STATIC_INLINE int32_t ITM_ReceiveChar (void) { int32_t ch = -1; /* no character available */ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { ch = ITM_RxBuffer; ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ } return (ch); } /** \brief ITM Check Character \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. \return 0 No character available. \return 1 Character available. */ __STATIC_INLINE int32_t ITM_CheckChar (void) { if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { return (0); /* no character available */ } else { return (1); /* character available */ } } /*@} end of CMSIS_core_DebugFunctions */ #ifdef __cplusplus } #endif #endif /* __CORE_SC300_H_DEPENDANT */ #endif /* __CMSIS_GENERIC */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/CMSIS/Include/mpu_armv7.h.
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/****************************************************************************** * @file mpu_armv7.h * @brief CMSIS MPU API for Armv7-M MPU * @version V5.0.4 * @date 10. January 2018 ******************************************************************************/ /* * Copyright (c) 2017-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__clang__) #pragma clang system_header /* treat file as system include file */ #endif #ifndef ARM_MPU_ARMV7_H #define ARM_MPU_ARMV7_H #define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) #define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) #define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) #define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) #define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) #define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) #define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) #define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) #define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) #define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) #define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) #define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) #define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) #define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) #define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) #define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) #define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) #define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) #define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) #define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) #define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) #define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) #define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) #define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) #define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) #define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) #define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) #define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) #define ARM_MPU_AP_NONE 0U #define ARM_MPU_AP_PRIV 1U #define ARM_MPU_AP_URO 2U #define ARM_MPU_AP_FULL 3U #define ARM_MPU_AP_PRO 5U #define ARM_MPU_AP_RO 6U /** MPU Region Base Address Register Value * * \param Region The region to be configured, number 0 to 15. * \param BaseAddress The base address for the region. */ #define ARM_MPU_RBAR(Region, BaseAddress) \ (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ ((Region) & MPU_RBAR_REGION_Msk) | \ (MPU_RBAR_VALID_Msk)) /** * MPU Region Attribute and Size Register Value * * \param DisableExec Instruction access disable bit, 1= disable instruction fetches. * \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. * \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. * \param IsShareable Region is shareable between multiple bus masters. * \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. * \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. * \param SubRegionDisable Sub-region disable field. * \param Size Region size of the region to be configured, for example 4K, 8K. */ #define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ ((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ (((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ (((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ (((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ (((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk) | \ (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \ (((Size ) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \ (MPU_RASR_ENABLE_Msk)) /** * Struct for a single MPU Region */ typedef struct { uint32_t RBAR; //!< The region base address register value (RBAR) uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR } ARM_MPU_Region_t; /** Enable the MPU. * \param MPU_Control Default access permissions for unconfigured regions. */ __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) { __DSB(); __ISB(); MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; #ifdef SCB_SHCSR_MEMFAULTENA_Msk SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; #endif } /** Disable the MPU. */ __STATIC_INLINE void ARM_MPU_Disable(void) { __DSB(); __ISB(); #ifdef SCB_SHCSR_MEMFAULTENA_Msk SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; #endif MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; } /** Clear and disable the given MPU region. * \param rnr Region number to be cleared. */ __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) { MPU->RNR = rnr; MPU->RASR = 0U; } /** Configure an MPU region. * \param rbar Value for RBAR register. * \param rsar Value for RSAR register. */ __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) { MPU->RBAR = rbar; MPU->RASR = rasr; } /** Configure the given MPU region. * \param rnr Region number to be configured. * \param rbar Value for RBAR register. * \param rsar Value for RSAR register. */ __STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) { MPU->RNR = rnr; MPU->RBAR = rbar; MPU->RASR = rasr; } /** Memcopy with strictly ordered memory access, e.g. for register targets. * \param dst Destination data is copied to. * \param src Source data is copied from. * \param len Amount of data words to be copied. */ __STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) { uint32_t i; for (i = 0U; i < len; ++i) { dst[i] = src[i]; } } /** Load the given number of MPU regions from a table. * \param table Pointer to the MPU configuration table. * \param cnt Amount of regions to be configured. */ __STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) { const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; while (cnt > MPU_TYPE_RALIASES) { orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); table += MPU_TYPE_RALIASES; cnt -= MPU_TYPE_RALIASES; } orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); } #endif |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/CMSIS/Include/mpu_armv8.h.
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/****************************************************************************** * @file mpu_armv8.h * @brief CMSIS MPU API for Armv8-M MPU * @version V5.0.4 * @date 10. January 2018 ******************************************************************************/ /* * Copyright (c) 2017-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__clang__) #pragma clang system_header /* treat file as system include file */ #endif #ifndef ARM_MPU_ARMV8_H #define ARM_MPU_ARMV8_H /** \brief Attribute for device memory (outer only) */ #define ARM_MPU_ATTR_DEVICE ( 0U ) /** \brief Attribute for non-cacheable, normal memory */ #define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) /** \brief Attribute for normal memory (outer and inner) * \param NT Non-Transient: Set to 1 for non-transient data. * \param WB Write-Back: Set to 1 to use write-back update policy. * \param RA Read Allocation: Set to 1 to use cache allocation on read miss. * \param WA Write Allocation: Set to 1 to use cache allocation on write miss. */ #define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U)) /** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ #define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) /** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ #define ARM_MPU_ATTR_DEVICE_nGnRE (1U) /** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ #define ARM_MPU_ATTR_DEVICE_nGRE (2U) /** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ #define ARM_MPU_ATTR_DEVICE_GRE (3U) /** \brief Memory Attribute * \param O Outer memory attributes * \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes */ #define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U))) /** \brief Normal memory non-shareable */ #define ARM_MPU_SH_NON (0U) /** \brief Normal memory outer shareable */ #define ARM_MPU_SH_OUTER (2U) /** \brief Normal memory inner shareable */ #define ARM_MPU_SH_INNER (3U) /** \brief Memory access permissions * \param RO Read-Only: Set to 1 for read-only memory. * \param NP Non-Privileged: Set to 1 for non-privileged memory. */ #define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U)) /** \brief Region Base Address Register value * \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. * \param SH Defines the Shareability domain for this memory region. * \param RO Read-Only: Set to 1 for a read-only memory region. * \param NP Non-Privileged: Set to 1 for a non-privileged memory region. * \oaram XN eXecute Never: Set to 1 for a non-executable memory region. */ #define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ ((BASE & MPU_RBAR_BASE_Pos) | \ ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) /** \brief Region Limit Address Register value * \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. * \param IDX The attribute index to be associated with this memory region. */ #define ARM_MPU_RLAR(LIMIT, IDX) \ ((LIMIT & MPU_RLAR_LIMIT_Msk) | \ ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ (MPU_RLAR_EN_Msk)) /** * Struct for a single MPU Region */ typedef struct { uint32_t RBAR; /*!< Region Base Address Register value */ uint32_t RLAR; /*!< Region Limit Address Register value */ } ARM_MPU_Region_t; /** Enable the MPU. * \param MPU_Control Default access permissions for unconfigured regions. */ __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) { __DSB(); __ISB(); MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; #ifdef SCB_SHCSR_MEMFAULTENA_Msk SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; #endif } /** Disable the MPU. */ __STATIC_INLINE void ARM_MPU_Disable(void) { __DSB(); __ISB(); #ifdef SCB_SHCSR_MEMFAULTENA_Msk SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; #endif MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; } #ifdef MPU_NS /** Enable the Non-secure MPU. * \param MPU_Control Default access permissions for unconfigured regions. */ __STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) { __DSB(); __ISB(); MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; #ifdef SCB_SHCSR_MEMFAULTENA_Msk SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; #endif } /** Disable the Non-secure MPU. */ __STATIC_INLINE void ARM_MPU_Disable_NS(void) { __DSB(); __ISB(); #ifdef SCB_SHCSR_MEMFAULTENA_Msk SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; #endif MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; } #endif /** Set the memory attribute encoding to the given MPU. * \param mpu Pointer to the MPU to be configured. * \param idx The attribute index to be set [0-7] * \param attr The attribute value to be set. */ __STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) { const uint8_t reg = idx / 4U; const uint32_t pos = ((idx % 4U) * 8U); const uint32_t mask = 0xFFU << pos; if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { return; // invalid index } mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); } /** Set the memory attribute encoding. * \param idx The attribute index to be set [0-7] * \param attr The attribute value to be set. */ __STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) { ARM_MPU_SetMemAttrEx(MPU, idx, attr); } #ifdef MPU_NS /** Set the memory attribute encoding to the Non-secure MPU. * \param idx The attribute index to be set [0-7] * \param attr The attribute value to be set. */ __STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) { ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); } #endif /** Clear and disable the given MPU region of the given MPU. * \param mpu Pointer to MPU to be used. * \param rnr Region number to be cleared. */ __STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) { mpu->RNR = rnr; mpu->RLAR = 0U; } /** Clear and disable the given MPU region. * \param rnr Region number to be cleared. */ __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) { ARM_MPU_ClrRegionEx(MPU, rnr); } #ifdef MPU_NS /** Clear and disable the given Non-secure MPU region. * \param rnr Region number to be cleared. */ __STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) { ARM_MPU_ClrRegionEx(MPU_NS, rnr); } #endif /** Configure the given MPU region of the given MPU. * \param mpu Pointer to MPU to be used. * \param rnr Region number to be configured. * \param rbar Value for RBAR register. * \param rlar Value for RLAR register. */ __STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) { mpu->RNR = rnr; mpu->RBAR = rbar; mpu->RLAR = rlar; } /** Configure the given MPU region. * \param rnr Region number to be configured. * \param rbar Value for RBAR register. * \param rlar Value for RLAR register. */ __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) { ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); } #ifdef MPU_NS /** Configure the given Non-secure MPU region. * \param rnr Region number to be configured. * \param rbar Value for RBAR register. * \param rlar Value for RLAR register. */ __STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) { ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); } #endif /** Memcopy with strictly ordered memory access, e.g. for register targets. * \param dst Destination data is copied to. * \param src Source data is copied from. * \param len Amount of data words to be copied. */ __STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) { uint32_t i; for (i = 0U; i < len; ++i) { dst[i] = src[i]; } } /** Load the given number of MPU regions from a table to the given MPU. * \param mpu Pointer to the MPU registers to be used. * \param rnr First region number to be configured. * \param table Pointer to the MPU configuration table. * \param cnt Amount of regions to be configured. */ __STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) { const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; if (cnt == 1U) { mpu->RNR = rnr; orderedCpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); } else { uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; mpu->RNR = rnrBase; while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { uint32_t c = MPU_TYPE_RALIASES - rnrOffset; orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); table += c; cnt -= c; rnrOffset = 0U; rnrBase += MPU_TYPE_RALIASES; mpu->RNR = rnrBase; } orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); } } /** Load the given number of MPU regions from a table. * \param rnr First region number to be configured. * \param table Pointer to the MPU configuration table. * \param cnt Amount of regions to be configured. */ __STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) { ARM_MPU_LoadEx(MPU, rnr, table, cnt); } #ifdef MPU_NS /** Load the given number of MPU regions from a table to the Non-secure MPU. * \param rnr First region number to be configured. * \param table Pointer to the MPU configuration table. * \param cnt Amount of regions to be configured. */ __STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) { ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); } #endif #endif |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/CMSIS/Include/tz_context.h.
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/****************************************************************************** * @file tz_context.h * @brief Context Management for Armv8-M TrustZone * @version V1.0.1 * @date 10. January 2018 ******************************************************************************/ /* * Copyright (c) 2017-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__clang__) #pragma clang system_header /* treat file as system include file */ #endif #ifndef TZ_CONTEXT_H #define TZ_CONTEXT_H #include <stdint.h> #ifndef TZ_MODULEID_T #define TZ_MODULEID_T /// \details Data type that identifies secure software modules called by a process. typedef uint32_t TZ_ModuleId_t; #endif /// \details TZ Memory ID identifies an allocated memory slot. typedef uint32_t TZ_MemoryId_t; /// Initialize secure context memory system /// \return execution status (1: success, 0: error) uint32_t TZ_InitContextSystem_S (void); /// Allocate context memory for calling secure software modules in TrustZone /// \param[in] module identifies software modules called from non-secure mode /// \return value != 0 id TrustZone memory slot identifier /// \return value 0 no memory available or internal error TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); /// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S /// \param[in] id TrustZone memory slot identifier /// \return execution status (1: success, 0: error) uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); /// Load secure context (called on RTOS thread context switch) /// \param[in] id TrustZone memory slot identifier /// \return execution status (1: success, 0: error) uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); /// Store secure context (called on RTOS thread context switch) /// \param[in] id TrustZone memory slot identifier /// \return execution status (1: success, 0: error) uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); #endif // TZ_CONTEXT_H |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p332f1024gl125.h.
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/***************************************************************************//** * @file * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFR32MG12P332F1024GL125 * @version 5.7.0 ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * SPDX-License-Identifier: Zlib * * The licensor of this software is Silicon Laboratories Inc. * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be * appreciated but is not required. * 2. Altered source versions must be plainly marked as such, and must not be * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * ******************************************************************************/ #if defined(__ICCARM__) #pragma system_include /* Treat file as system include file. */ #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang system_header /* Treat file as system include file. */ #endif #ifndef EFR32MG12P332F1024GL125_H #define EFR32MG12P332F1024GL125_H #ifdef __cplusplus extern "C" { #endif /***************************************************************************//** * @addtogroup Parts * @{ ******************************************************************************/ /***************************************************************************//** * @defgroup EFR32MG12P332F1024GL125 EFR32MG12P332F1024GL125 * @{ ******************************************************************************/ /** Interrupt Number Definition */ typedef enum IRQn{ /****** Cortex-M4 Processor Exceptions Numbers ********************************************/ NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */ HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ /****** EFR32MG12P Peripheral Interrupt Numbers ********************************************/ EMU_IRQn = 0, /*!< 16+0 EFR32 EMU Interrupt */ FRC_PRI_IRQn = 1, /*!< 16+1 EFR32 FRC_PRI Interrupt */ WDOG0_IRQn = 2, /*!< 16+2 EFR32 WDOG0 Interrupt */ WDOG1_IRQn = 3, /*!< 16+3 EFR32 WDOG1 Interrupt */ FRC_IRQn = 4, /*!< 16+4 EFR32 FRC Interrupt */ MODEM_IRQn = 5, /*!< 16+5 EFR32 MODEM Interrupt */ RAC_SEQ_IRQn = 6, /*!< 16+6 EFR32 RAC_SEQ Interrupt */ RAC_RSM_IRQn = 7, /*!< 16+7 EFR32 RAC_RSM Interrupt */ BUFC_IRQn = 8, /*!< 16+8 EFR32 BUFC Interrupt */ LDMA_IRQn = 9, /*!< 16+9 EFR32 LDMA Interrupt */ GPIO_EVEN_IRQn = 10, /*!< 16+10 EFR32 GPIO_EVEN Interrupt */ TIMER0_IRQn = 11, /*!< 16+11 EFR32 TIMER0 Interrupt */ USART0_RX_IRQn = 12, /*!< 16+12 EFR32 USART0_RX Interrupt */ USART0_TX_IRQn = 13, /*!< 16+13 EFR32 USART0_TX Interrupt */ ACMP0_IRQn = 14, /*!< 16+14 EFR32 ACMP0 Interrupt */ ADC0_IRQn = 15, /*!< 16+15 EFR32 ADC0 Interrupt */ IDAC0_IRQn = 16, /*!< 16+16 EFR32 IDAC0 Interrupt */ I2C0_IRQn = 17, /*!< 16+17 EFR32 I2C0 Interrupt */ GPIO_ODD_IRQn = 18, /*!< 16+18 EFR32 GPIO_ODD Interrupt */ TIMER1_IRQn = 19, /*!< 16+19 EFR32 TIMER1 Interrupt */ USART1_RX_IRQn = 20, /*!< 16+20 EFR32 USART1_RX Interrupt */ USART1_TX_IRQn = 21, /*!< 16+21 EFR32 USART1_TX Interrupt */ LEUART0_IRQn = 22, /*!< 16+22 EFR32 LEUART0 Interrupt */ PCNT0_IRQn = 23, /*!< 16+23 EFR32 PCNT0 Interrupt */ CMU_IRQn = 24, /*!< 16+24 EFR32 CMU Interrupt */ MSC_IRQn = 25, /*!< 16+25 EFR32 MSC Interrupt */ CRYPTO0_IRQn = 26, /*!< 16+26 EFR32 CRYPTO0 Interrupt */ LETIMER0_IRQn = 27, /*!< 16+27 EFR32 LETIMER0 Interrupt */ AGC_IRQn = 28, /*!< 16+28 EFR32 AGC Interrupt */ PROTIMER_IRQn = 29, /*!< 16+29 EFR32 PROTIMER Interrupt */ RTCC_IRQn = 30, /*!< 16+30 EFR32 RTCC Interrupt */ SYNTH_IRQn = 31, /*!< 16+31 EFR32 SYNTH Interrupt */ CRYOTIMER_IRQn = 32, /*!< 16+32 EFR32 CRYOTIMER Interrupt */ RFSENSE_IRQn = 33, /*!< 16+33 EFR32 RFSENSE Interrupt */ FPUEH_IRQn = 34, /*!< 16+34 EFR32 FPUEH Interrupt */ SMU_IRQn = 35, /*!< 16+35 EFR32 SMU Interrupt */ WTIMER0_IRQn = 36, /*!< 16+36 EFR32 WTIMER0 Interrupt */ WTIMER1_IRQn = 37, /*!< 16+37 EFR32 WTIMER1 Interrupt */ PCNT1_IRQn = 38, /*!< 16+38 EFR32 PCNT1 Interrupt */ PCNT2_IRQn = 39, /*!< 16+39 EFR32 PCNT2 Interrupt */ USART2_RX_IRQn = 40, /*!< 16+40 EFR32 USART2_RX Interrupt */ USART2_TX_IRQn = 41, /*!< 16+41 EFR32 USART2_TX Interrupt */ I2C1_IRQn = 42, /*!< 16+42 EFR32 I2C1 Interrupt */ USART3_RX_IRQn = 43, /*!< 16+43 EFR32 USART3_RX Interrupt */ USART3_TX_IRQn = 44, /*!< 16+44 EFR32 USART3_TX Interrupt */ VDAC0_IRQn = 45, /*!< 16+45 EFR32 VDAC0 Interrupt */ CSEN_IRQn = 46, /*!< 16+46 EFR32 CSEN Interrupt */ LESENSE_IRQn = 47, /*!< 16+47 EFR32 LESENSE Interrupt */ CRYPTO1_IRQn = 48, /*!< 16+48 EFR32 CRYPTO1 Interrupt */ TRNG0_IRQn = 49, /*!< 16+49 EFR32 TRNG0 Interrupt */ } IRQn_Type; #define CRYPTO_IRQn CRYPTO0_IRQn /*!< Alias for CRYPTO0_IRQn */ /***************************************************************************//** * @defgroup EFR32MG12P332F1024GL125_Core Core * @{ * @brief Processor and Core Peripheral Section ******************************************************************************/ #define __MPU_PRESENT 1U /**< Presence of MPU */ #define __FPU_PRESENT 1U /**< Presence of FPU */ #define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ #define __NVIC_PRIO_BITS 3U /**< NVIC interrupt priority bits */ #define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ /** @} End of group EFR32MG12P332F1024GL125_Core */ /***************************************************************************//** * @defgroup EFR32MG12P332F1024GL125_Part Part * @{ ******************************************************************************/ /** Part family */ #define _EFR32_MIGHTY_FAMILY 1 /**< MIGHTY Gecko RF SoC Family */ #define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */ #define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ #define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ #define _SILICON_LABS_32B_SERIES_1_CONFIG_2 /**< Series 1, Configuration 2 */ #define _SILICON_LABS_32B_SERIES_1_CONFIG 2 /**< Series 1, Configuration 2 */ #define _SILICON_LABS_GECKO_INTERNAL_SDID 84 /**< Silicon Labs internal use only, may change any time */ #define _SILICON_LABS_GECKO_INTERNAL_SDID_84 /**< Silicon Labs internal use only, may change any time */ #define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /**< Radio supports Sub-GHz */ #define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /**< Radio supports 2.4 GHz */ #define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /**< Radio supports dual band */ #define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /**< Radio type */ #define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ #define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ #define _SILICON_LABS_32B_PLATFORM_2_GEN_2 /**< @deprecated Platform 2, generation 2 */ #define _SILICON_LABS_32B_PLATFORM_2_GEN 2 /**< @deprecated Platform 2, generation 2 */ /* If part number is not defined as compiler option, define it */ #if !defined(EFR32MG12P332F1024GL125) #define EFR32MG12P332F1024GL125 1 /**< MIGHTY Gecko Part */ #endif /** Configure part number */ #define PART_NUMBER "EFR32MG12P332F1024GL125" /**< Part Number */ /** Memory Base addresses and limits */ #define RAM0_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM0_CODE base address */ #define RAM0_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM0_CODE available address space */ #define RAM0_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM0_CODE end address */ #define RAM0_CODE_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM0_CODE used bits */ #define RAM2_MEM_BASE ((uint32_t) 0x20040000UL) /**< RAM2 base address */ #define RAM2_MEM_SIZE ((uint32_t) 0x800UL) /**< RAM2 available address space */ #define RAM2_MEM_END ((uint32_t) 0x200407FFUL) /**< RAM2 end address */ #define RAM2_MEM_BITS ((uint32_t) 0x0000000BUL) /**< RAM2 used bits */ #define RAM1_MEM_BASE ((uint32_t) 0x20020000UL) /**< RAM1 base address */ #define RAM1_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM1 available address space */ #define RAM1_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM1 end address */ #define RAM1_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM1 used bits */ #define CRYPTO1_BITCLR_MEM_BASE ((uint32_t) 0x440F0400UL) /**< CRYPTO1_BITCLR base address */ #define CRYPTO1_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1_BITCLR available address space */ #define CRYPTO1_BITCLR_MEM_END ((uint32_t) 0x440F07FFUL) /**< CRYPTO1_BITCLR end address */ #define CRYPTO1_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1_BITCLR used bits */ #define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */ #define PER_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER available address space */ #define PER_MEM_END ((uint32_t) 0x400EFFFFUL) /**< PER end address */ #define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */ #define RAM1_CODE_MEM_BASE ((uint32_t) 0x10020000UL) /**< RAM1_CODE base address */ #define RAM1_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM1_CODE available address space */ #define RAM1_CODE_MEM_END ((uint32_t) 0x1003FFFFUL) /**< RAM1_CODE end address */ #define RAM1_CODE_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM1_CODE used bits */ #define CRYPTO1_MEM_BASE ((uint32_t) 0x400F0400UL) /**< CRYPTO1 base address */ #define CRYPTO1_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1 available address space */ #define CRYPTO1_MEM_END ((uint32_t) 0x400F07FFUL) /**< CRYPTO1 end address */ #define CRYPTO1_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1 used bits */ #define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */ #define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */ #define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */ #define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */ #define CRYPTO0_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO0 base address */ #define CRYPTO0_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0 available address space */ #define CRYPTO0_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO0 end address */ #define CRYPTO0_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0 used bits */ #define CRYPTO_MEM_BASE CRYPTO0_MEM_BASE /**< Alias for CRYPTO0_MEM_BASE */ #define CRYPTO_MEM_SIZE CRYPTO0_MEM_SIZE /**< Alias for CRYPTO0_MEM_SIZE */ #define CRYPTO_MEM_END CRYPTO0_MEM_END /**< Alias for CRYPTO0_MEM_END */ #define CRYPTO_MEM_BITS CRYPTO0_MEM_BITS /**< Alias for CRYPTO0_MEM_BITS */ #define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */ #define PER_BITCLR_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER_BITCLR available address space */ #define PER_BITCLR_MEM_END ((uint32_t) 0x440EFFFFUL) /**< PER_BITCLR end address */ #define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */ #define CRYPTO0_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO0_BITSET base address */ #define CRYPTO0_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0_BITSET available address space */ #define CRYPTO0_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO0_BITSET end address */ #define CRYPTO0_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0_BITSET used bits */ #define CRYPTO_BITSET_MEM_BASE CRYPTO0_BITSET_MEM_BASE /**< Alias for CRYPTO0_BITSET_MEM_BASE */ #define CRYPTO_BITSET_MEM_SIZE CRYPTO0_BITSET_MEM_SIZE /**< Alias for CRYPTO0_BITSET_MEM_SIZE */ #define CRYPTO_BITSET_MEM_END CRYPTO0_BITSET_MEM_END /**< Alias for CRYPTO0_BITSET_MEM_END */ #define CRYPTO_BITSET_MEM_BITS CRYPTO0_BITSET_MEM_BITS /**< Alias for CRYPTO0_BITSET_MEM_BITS */ #define CRYPTO0_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO0_BITCLR base address */ #define CRYPTO0_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0_BITCLR available address space */ #define CRYPTO0_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO0_BITCLR end address */ #define CRYPTO0_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0_BITCLR used bits */ #define CRYPTO_BITCLR_MEM_BASE CRYPTO0_BITCLR_MEM_BASE /**< Alias for CRYPTO0_BITCLR_MEM_BASE */ #define CRYPTO_BITCLR_MEM_SIZE CRYPTO0_BITCLR_MEM_SIZE /**< Alias for CRYPTO0_BITCLR_MEM_SIZE */ #define CRYPTO_BITCLR_MEM_END CRYPTO0_BITCLR_MEM_END /**< Alias for CRYPTO0_BITCLR_MEM_END */ #define CRYPTO_BITCLR_MEM_BITS CRYPTO0_BITCLR_MEM_BITS /**< Alias for CRYPTO0_BITCLR_MEM_BITS */ #define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */ #define PER_BITSET_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER_BITSET available address space */ #define PER_BITSET_MEM_END ((uint32_t) 0x460EFFFFUL) /**< PER_BITSET end address */ #define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */ #define CRYPTO1_BITSET_MEM_BASE ((uint32_t) 0x460F0400UL) /**< CRYPTO1_BITSET base address */ #define CRYPTO1_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1_BITSET available address space */ #define CRYPTO1_BITSET_MEM_END ((uint32_t) 0x460F07FFUL) /**< CRYPTO1_BITSET end address */ #define CRYPTO1_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1_BITSET used bits */ #define RAM2_CODE_MEM_BASE ((uint32_t) 0x10040000UL) /**< RAM2_CODE base address */ #define RAM2_CODE_MEM_SIZE ((uint32_t) 0x800UL) /**< RAM2_CODE available address space */ #define RAM2_CODE_MEM_END ((uint32_t) 0x100407FFUL) /**< RAM2_CODE end address */ #define RAM2_CODE_MEM_BITS ((uint32_t) 0x0000000BUL) /**< RAM2_CODE used bits */ #define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */ #define RAM_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM available address space */ #define RAM_MEM_END ((uint32_t) 0x2001FFFFUL) /**< RAM end address */ #define RAM_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM used bits */ /** Bit banding area */ #define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */ #define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */ /** Flash and SRAM limits for EFR32MG12P332F1024GL125 */ #define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ #define FLASH_SIZE (0x00100000UL) /**< Available Flash Memory */ #define FLASH_PAGE_SIZE 2048U /**< Flash Memory page size (interleaving off) */ #define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ #define SRAM_SIZE (0x00040000UL) /**< Available SRAM Memory */ #define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */ #define PRS_CHAN_COUNT 12 /**< Number of PRS channels */ #define DMA_CHAN_COUNT 8 /**< Number of DMA channels */ #define EXT_IRQ_COUNT 51 /**< Number of External (NVIC) interrupts */ /** AF channels connect the different on-chip peripherals with the af-mux */ #define AFCHAN_MAX 136U /** AF channel maximum location number */ #define AFCHANLOC_MAX 32U /** Analog AF channels */ #define AFACHAN_MAX 125U /* Part number capabilities */ #define CRYPTO_PRESENT /**< CRYPTO is available in this part */ #define CRYPTO_COUNT 2 /**< 2 CRYPTOs available */ #define TIMER_PRESENT /**< TIMER is available in this part */ #define TIMER_COUNT 2 /**< 2 TIMERs available */ #define WTIMER_PRESENT /**< WTIMER is available in this part */ #define WTIMER_COUNT 2 /**< 2 WTIMERs available */ #define USART_PRESENT /**< USART is available in this part */ #define USART_COUNT 4 /**< 4 USARTs available */ #define LEUART_PRESENT /**< LEUART is available in this part */ #define LEUART_COUNT 1 /**< 1 LEUARTs available */ #define LETIMER_PRESENT /**< LETIMER is available in this part */ #define LETIMER_COUNT 1 /**< 1 LETIMERs available */ #define PCNT_PRESENT /**< PCNT is available in this part */ #define PCNT_COUNT 3 /**< 3 PCNTs available */ #define I2C_PRESENT /**< I2C is available in this part */ #define I2C_COUNT 2 /**< 2 I2Cs available */ #define ADC_PRESENT /**< ADC is available in this part */ #define ADC_COUNT 1 /**< 1 ADCs available */ #define ACMP_PRESENT /**< ACMP is available in this part */ #define ACMP_COUNT 2 /**< 2 ACMPs available */ #define IDAC_PRESENT /**< IDAC is available in this part */ #define IDAC_COUNT 1 /**< 1 IDACs available */ #define VDAC_PRESENT /**< VDAC is available in this part */ #define VDAC_COUNT 1 /**< 1 VDACs available */ #define WDOG_PRESENT /**< WDOG is available in this part */ #define WDOG_COUNT 2 /**< 2 WDOGs available */ #define TRNG_PRESENT /**< TRNG is available in this part */ #define TRNG_COUNT 1 /**< 1 TRNGs available */ #define MSC_PRESENT /**< MSC is available in this part */ #define MSC_COUNT 1 /**< 1 MSC available */ #define EMU_PRESENT /**< EMU is available in this part */ #define EMU_COUNT 1 /**< 1 EMU available */ #define RMU_PRESENT /**< RMU is available in this part */ #define RMU_COUNT 1 /**< 1 RMU available */ #define CMU_PRESENT /**< CMU is available in this part */ #define CMU_COUNT 1 /**< 1 CMU available */ #define GPIO_PRESENT /**< GPIO is available in this part */ #define GPIO_COUNT 1 /**< 1 GPIO available */ #define PRS_PRESENT /**< PRS is available in this part */ #define PRS_COUNT 1 /**< 1 PRS available */ #define LDMA_PRESENT /**< LDMA is available in this part */ #define LDMA_COUNT 1 /**< 1 LDMA available */ #define FPUEH_PRESENT /**< FPUEH is available in this part */ #define FPUEH_COUNT 1 /**< 1 FPUEH available */ #define GPCRC_PRESENT /**< GPCRC is available in this part */ #define GPCRC_COUNT 1 /**< 1 GPCRC available */ #define CRYOTIMER_PRESENT /**< CRYOTIMER is available in this part */ #define CRYOTIMER_COUNT 1 /**< 1 CRYOTIMER available */ #define CSEN_PRESENT /**< CSEN is available in this part */ #define CSEN_COUNT 1 /**< 1 CSEN available */ #define LESENSE_PRESENT /**< LESENSE is available in this part */ #define LESENSE_COUNT 1 /**< 1 LESENSE available */ #define RTCC_PRESENT /**< RTCC is available in this part */ #define RTCC_COUNT 1 /**< 1 RTCC available */ #define ETM_PRESENT /**< ETM is available in this part */ #define ETM_COUNT 1 /**< 1 ETM available */ #define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */ #define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */ #define SMU_PRESENT /**< SMU is available in this part */ #define SMU_COUNT 1 /**< 1 SMU available */ #define DCDC_PRESENT /**< DCDC is available in this part */ #define DCDC_COUNT 1 /**< 1 DCDC available */ #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ #include "system_efr32mg12p.h" /* System Header File */ /** @} End of group EFR32MG12P332F1024GL125_Part */ /***************************************************************************//** * @defgroup EFR32MG12P332F1024GL125_Peripheral_TypeDefs Peripheral TypeDefs * @{ * @brief Device Specific Peripheral Register Structures ******************************************************************************/ #include "efr32mg12p_msc.h" #include "efr32mg12p_emu.h" #include "efr32mg12p_rmu.h" #include "efr32mg12p_cmu.h" #include "efr32mg12p_crypto.h" #include "efr32mg12p_gpio_p.h" #include "efr32mg12p_gpio.h" #include "efr32mg12p_prs_ch.h" #include "efr32mg12p_prs.h" #include "efr32mg12p_ldma_ch.h" #include "efr32mg12p_ldma.h" #include "efr32mg12p_fpueh.h" #include "efr32mg12p_gpcrc.h" #include "efr32mg12p_timer_cc.h" #include "efr32mg12p_timer.h" #include "efr32mg12p_usart.h" #include "efr32mg12p_leuart.h" #include "efr32mg12p_letimer.h" #include "efr32mg12p_cryotimer.h" #include "efr32mg12p_pcnt.h" #include "efr32mg12p_i2c.h" #include "efr32mg12p_adc.h" #include "efr32mg12p_acmp.h" #include "efr32mg12p_idac.h" #include "efr32mg12p_vdac_opa.h" #include "efr32mg12p_vdac.h" #include "efr32mg12p_csen.h" #include "efr32mg12p_lesense_st.h" #include "efr32mg12p_lesense_buf.h" #include "efr32mg12p_lesense_ch.h" #include "efr32mg12p_lesense.h" #include "efr32mg12p_rtcc_cc.h" #include "efr32mg12p_rtcc_ret.h" #include "efr32mg12p_rtcc.h" #include "efr32mg12p_wdog_pch.h" #include "efr32mg12p_wdog.h" #include "efr32mg12p_etm.h" #include "efr32mg12p_smu.h" #include "efr32mg12p_trng.h" #include "efr32mg12p_dma_descriptor.h" #include "efr32mg12p_devinfo.h" #include "efr32mg12p_romtable.h" /** @} End of group EFR32MG12P332F1024GL125_Peripheral_TypeDefs */ /***************************************************************************//** * @defgroup EFR32MG12P332F1024GL125_Peripheral_Base Peripheral Memory Map * @{ ******************************************************************************/ #define MSC_BASE (0x400E0000UL) /**< MSC base address */ #define EMU_BASE (0x400E3000UL) /**< EMU base address */ #define RMU_BASE (0x400E5000UL) /**< RMU base address */ #define CMU_BASE (0x400E4000UL) /**< CMU base address */ #define CRYPTO0_BASE (0x400F0000UL) /**< CRYPTO0 base address */ #define CRYPTO_BASE CRYPTO0_BASE /**< Alias for CRYPTO0 base address */ #define CRYPTO1_BASE (0x400F0400UL) /**< CRYPTO1 base address */ #define GPIO_BASE (0x4000A000UL) /**< GPIO base address */ #define PRS_BASE (0x400E6000UL) /**< PRS base address */ #define LDMA_BASE (0x400E2000UL) /**< LDMA base address */ #define FPUEH_BASE (0x400E1000UL) /**< FPUEH base address */ #define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */ #define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */ #define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */ #define WTIMER0_BASE (0x4001A000UL) /**< WTIMER0 base address */ #define WTIMER1_BASE (0x4001A400UL) /**< WTIMER1 base address */ #define USART0_BASE (0x40010000UL) /**< USART0 base address */ #define USART1_BASE (0x40010400UL) /**< USART1 base address */ #define USART2_BASE (0x40010800UL) /**< USART2 base address */ #define USART3_BASE (0x40010C00UL) /**< USART3 base address */ #define LEUART0_BASE (0x4004A000UL) /**< LEUART0 base address */ #define LETIMER0_BASE (0x40046000UL) /**< LETIMER0 base address */ #define CRYOTIMER_BASE (0x4001E000UL) /**< CRYOTIMER base address */ #define PCNT0_BASE (0x4004E000UL) /**< PCNT0 base address */ #define PCNT1_BASE (0x4004E400UL) /**< PCNT1 base address */ #define PCNT2_BASE (0x4004E800UL) /**< PCNT2 base address */ #define I2C0_BASE (0x4000C000UL) /**< I2C0 base address */ #define I2C1_BASE (0x4000C400UL) /**< I2C1 base address */ #define ADC0_BASE (0x40002000UL) /**< ADC0 base address */ #define ACMP0_BASE (0x40000000UL) /**< ACMP0 base address */ #define ACMP1_BASE (0x40000400UL) /**< ACMP1 base address */ #define IDAC0_BASE (0x40006000UL) /**< IDAC0 base address */ #define VDAC0_BASE (0x40008000UL) /**< VDAC0 base address */ #define CSEN_BASE (0x4001F000UL) /**< CSEN base address */ #define LESENSE_BASE (0x40055000UL) /**< LESENSE base address */ #define RTCC_BASE (0x40042000UL) /**< RTCC base address */ #define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */ #define WDOG1_BASE (0x40052400UL) /**< WDOG1 base address */ #define ETM_BASE (0xE0041000UL) /**< ETM base address */ #define SMU_BASE (0x40022000UL) /**< SMU base address */ #define TRNG0_BASE (0x4001D000UL) /**< TRNG0 base address */ #define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */ #define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */ #define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */ #define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */ /** @} End of group EFR32MG12P332F1024GL125_Peripheral_Base */ /***************************************************************************//** * @defgroup EFR32MG12P332F1024GL125_Peripheral_Declaration Peripheral Declarations * @{ ******************************************************************************/ #define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ #define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ #define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */ #define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ #define CRYPTO0 ((CRYPTO_TypeDef *) CRYPTO0_BASE) /**< CRYPTO0 base pointer */ #define CRYPTO CRYPTO0 /**< Alias for CRYPTO0 base pointer */ #define CRYPTO1 ((CRYPTO_TypeDef *) CRYPTO1_BASE) /**< CRYPTO1 base pointer */ #define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ #define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ #define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ #define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */ #define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ #define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ #define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ #define WTIMER0 ((TIMER_TypeDef *) WTIMER0_BASE) /**< WTIMER0 base pointer */ #define WTIMER1 ((TIMER_TypeDef *) WTIMER1_BASE) /**< WTIMER1 base pointer */ #define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ #define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ #define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */ #define USART3 ((USART_TypeDef *) USART3_BASE) /**< USART3 base pointer */ #define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */ #define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ #define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */ #define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ #define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */ #define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */ #define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ #define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ #define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */ #define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ #define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ #define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */ #define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ #define CSEN ((CSEN_TypeDef *) CSEN_BASE) /**< CSEN base pointer */ #define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */ #define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */ #define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ #define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ #define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */ #define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ #define TRNG0 ((TRNG_TypeDef *) TRNG0_BASE) /**< TRNG0 base pointer */ #define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ #define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */ /** @} End of group EFR32MG12P332F1024GL125_Peripheral_Declaration */ /***************************************************************************//** * @defgroup EFR32MG12P332F1024GL125_Peripheral_Offsets Peripheral Offsets * @{ ******************************************************************************/ #define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */ #define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */ #define WTIMER_OFFSET 0x400 /**< Offset in bytes between WTIMER instances */ #define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */ #define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */ #define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */ #define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */ #define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */ #define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */ #define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */ #define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */ #define VDAC_OFFSET 0x400 /**< Offset in bytes between VDAC instances */ #define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */ #define TRNG_OFFSET 0x400 /**< Offset in bytes between TRNG instances */ /** @} End of group EFR32MG12P332F1024GL125_Peripheral_Offsets */ /***************************************************************************//** * @defgroup EFR32MG12P332F1024GL125_BitFields Bit Fields * @{ ******************************************************************************/ #include "efr32mg12p_prs_signals.h" #include "efr32mg12p_dmareq.h" /***************************************************************************//** * @addtogroup EFR32MG12P332F1024GL125_WTIMER * @{ * @defgroup EFR32MG12P332F1024GL125_WTIMER_BitFields WTIMER Bit Fields * @{ ******************************************************************************/ /* Bit fields for WTIMER CTRL */ #define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */ #define _WTIMER_CTRL_MASK 0x3F032FFBUL /**< Mask for WTIMER_CTRL */ #define _WTIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ #define _WTIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ #define _WTIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ #define _WTIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for WTIMER_CTRL */ #define _WTIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_CTRL */ #define _WTIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for WTIMER_CTRL */ #define _WTIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for WTIMER_CTRL */ #define WTIMER_CTRL_MODE_DEFAULT (_WTIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CTRL */ #define WTIMER_CTRL_MODE_UP (_WTIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for WTIMER_CTRL */ #define WTIMER_CTRL_MODE_DOWN (_WTIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for WTIMER_CTRL */ #define WTIMER_CTRL_MODE_UPDOWN (_WTIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for WTIMER_CTRL */ #define WTIMER_CTRL_MODE_QDEC (_WTIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for WTIMER_CTRL */ #define WTIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ #define _WTIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ #define _WTIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ #define _WTIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ #define WTIMER_CTRL_SYNC_DEFAULT (_WTIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_CTRL */ #define WTIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ #define _WTIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ #define _WTIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ #define _WTIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ #define WTIMER_CTRL_OSMEN_DEFAULT (_WTIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CTRL */ #define WTIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ #define _WTIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ #define _WTIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ #define _WTIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ #define _WTIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for WTIMER_CTRL */ #define _WTIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for WTIMER_CTRL */ #define WTIMER_CTRL_QDM_DEFAULT (_WTIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_CTRL */ #define WTIMER_CTRL_QDM_X2 (_WTIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for WTIMER_CTRL */ #define WTIMER_CTRL_QDM_X4 (_WTIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for WTIMER_CTRL */ #define WTIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ #define _WTIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ #define _WTIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ #define _WTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ #define WTIMER_CTRL_DEBUGRUN_DEFAULT (_WTIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_CTRL */ #define WTIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ #define _WTIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ #define _WTIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ #define _WTIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ #define WTIMER_CTRL_DMACLRACT_DEFAULT (_WTIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_CTRL */ #define _WTIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */ #define _WTIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */ #define _WTIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ #define _WTIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ #define _WTIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ #define _WTIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ #define _WTIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ #define WTIMER_CTRL_RISEA_DEFAULT (_WTIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CTRL */ #define WTIMER_CTRL_RISEA_NONE (_WTIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for WTIMER_CTRL */ #define WTIMER_CTRL_RISEA_START (_WTIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for WTIMER_CTRL */ #define WTIMER_CTRL_RISEA_STOP (_WTIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for WTIMER_CTRL */ #define WTIMER_CTRL_RISEA_RELOADSTART (_WTIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ #define _WTIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */ #define _WTIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */ #define _WTIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ #define _WTIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ #define _WTIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ #define _WTIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ #define _WTIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ #define WTIMER_CTRL_FALLA_DEFAULT (_WTIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CTRL */ #define WTIMER_CTRL_FALLA_NONE (_WTIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for WTIMER_CTRL */ #define WTIMER_CTRL_FALLA_START (_WTIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for WTIMER_CTRL */ #define WTIMER_CTRL_FALLA_STOP (_WTIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for WTIMER_CTRL */ #define WTIMER_CTRL_FALLA_RELOADSTART (_WTIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ #define WTIMER_CTRL_X2CNT (0x1UL << 13) /**< 2x Count Mode */ #define _WTIMER_CTRL_X2CNT_SHIFT 13 /**< Shift value for TIMER_X2CNT */ #define _WTIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */ #define _WTIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ #define WTIMER_CTRL_X2CNT_DEFAULT (_WTIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for WTIMER_CTRL */ #define _WTIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */ #define _WTIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */ #define _WTIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ #define _WTIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for WTIMER_CTRL */ #define _WTIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for WTIMER_CTRL */ #define _WTIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for WTIMER_CTRL */ #define WTIMER_CTRL_CLKSEL_DEFAULT (_WTIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CTRL */ #define WTIMER_CTRL_CLKSEL_PRESCHFPERCLK (_WTIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for WTIMER_CTRL */ #define WTIMER_CTRL_CLKSEL_CC1 (_WTIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for WTIMER_CTRL */ #define WTIMER_CTRL_CLKSEL_TIMEROUF (_WTIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for WTIMER_CTRL */ #define _WTIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */ #define _WTIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */ #define _WTIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ #define _WTIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_CTRL */ #define _WTIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_CTRL */ #define _WTIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_CTRL */ #define _WTIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_CTRL */ #define _WTIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_CTRL */ #define _WTIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_CTRL */ #define _WTIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_CTRL */ #define _WTIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_CTRL */ #define _WTIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_CTRL */ #define _WTIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_CTRL */ #define _WTIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_CTRL */ #define WTIMER_CTRL_PRESC_DEFAULT (_WTIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CTRL */ #define WTIMER_CTRL_PRESC_DIV1 (_WTIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for WTIMER_CTRL */ #define WTIMER_CTRL_PRESC_DIV2 (_WTIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for WTIMER_CTRL */ #define WTIMER_CTRL_PRESC_DIV4 (_WTIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for WTIMER_CTRL */ #define WTIMER_CTRL_PRESC_DIV8 (_WTIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for WTIMER_CTRL */ #define WTIMER_CTRL_PRESC_DIV16 (_WTIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for WTIMER_CTRL */ #define WTIMER_CTRL_PRESC_DIV32 (_WTIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for WTIMER_CTRL */ #define WTIMER_CTRL_PRESC_DIV64 (_WTIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for WTIMER_CTRL */ #define WTIMER_CTRL_PRESC_DIV128 (_WTIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for WTIMER_CTRL */ #define WTIMER_CTRL_PRESC_DIV256 (_WTIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for WTIMER_CTRL */ #define WTIMER_CTRL_PRESC_DIV512 (_WTIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for WTIMER_CTRL */ #define WTIMER_CTRL_PRESC_DIV1024 (_WTIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for WTIMER_CTRL */ #define WTIMER_CTRL_ATI (0x1UL << 28) /**< Always Track Inputs */ #define _WTIMER_CTRL_ATI_SHIFT 28 /**< Shift value for TIMER_ATI */ #define _WTIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */ #define _WTIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ #define WTIMER_CTRL_ATI_DEFAULT (_WTIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CTRL */ #define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output Initial State */ #define _WTIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */ #define _WTIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */ #define _WTIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ #define WTIMER_CTRL_RSSCOIST_DEFAULT (_WTIMER_CTRL_RSSCOIST_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CTRL */ /* Bit fields for WTIMER CMD */ #define _WTIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CMD */ #define _WTIMER_CMD_MASK 0x00000003UL /**< Mask for WTIMER_CMD */ #define WTIMER_CMD_START (0x1UL << 0) /**< Start Timer */ #define _WTIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ #define _WTIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ #define _WTIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ #define WTIMER_CMD_START_DEFAULT (_WTIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CMD */ #define WTIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ #define _WTIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ #define _WTIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ #define _WTIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ #define WTIMER_CMD_STOP_DEFAULT (_WTIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_CMD */ /* Bit fields for WTIMER STATUS */ #define _WTIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_STATUS */ #define _WTIMER_STATUS_MASK 0x0F0F0F07UL /**< Mask for WTIMER_STATUS */ #define WTIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ #define _WTIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ #define _WTIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ #define _WTIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ #define WTIMER_STATUS_RUNNING_DEFAULT (_WTIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_STATUS */ #define WTIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ #define _WTIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ #define _WTIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ #define _WTIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ #define _WTIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for WTIMER_STATUS */ #define _WTIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_STATUS */ #define WTIMER_STATUS_DIR_DEFAULT (_WTIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_STATUS */ #define WTIMER_STATUS_DIR_UP (_WTIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for WTIMER_STATUS */ #define WTIMER_STATUS_DIR_DOWN (_WTIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for WTIMER_STATUS */ #define WTIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */ #define _WTIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ #define _WTIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ #define _WTIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ #define WTIMER_STATUS_TOPBV_DEFAULT (_WTIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_STATUS */ #define WTIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */ #define _WTIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */ #define _WTIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */ #define _WTIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ #define WTIMER_STATUS_CCVBV0_DEFAULT (_WTIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_STATUS */ #define WTIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */ #define _WTIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */ #define _WTIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */ #define _WTIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ #define WTIMER_STATUS_CCVBV1_DEFAULT (_WTIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_STATUS */ #define WTIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */ #define _WTIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */ #define _WTIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */ #define _WTIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ #define WTIMER_STATUS_CCVBV2_DEFAULT (_WTIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_STATUS */ #define WTIMER_STATUS_CCVBV3 (0x1UL << 11) /**< CC3 CCVB Valid */ #define _WTIMER_STATUS_CCVBV3_SHIFT 11 /**< Shift value for TIMER_CCVBV3 */ #define _WTIMER_STATUS_CCVBV3_MASK 0x800UL /**< Bit mask for TIMER_CCVBV3 */ #define _WTIMER_STATUS_CCVBV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ #define WTIMER_STATUS_CCVBV3_DEFAULT (_WTIMER_STATUS_CCVBV3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_STATUS */ #define WTIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */ #define _WTIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */ #define _WTIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */ #define _WTIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ #define WTIMER_STATUS_ICV0_DEFAULT (_WTIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_STATUS */ #define WTIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */ #define _WTIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */ #define _WTIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */ #define _WTIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ #define WTIMER_STATUS_ICV1_DEFAULT (_WTIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for WTIMER_STATUS */ #define WTIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */ #define _WTIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */ #define _WTIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */ #define _WTIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ #define WTIMER_STATUS_ICV2_DEFAULT (_WTIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for WTIMER_STATUS */ #define WTIMER_STATUS_ICV3 (0x1UL << 19) /**< CC3 Input Capture Valid */ #define _WTIMER_STATUS_ICV3_SHIFT 19 /**< Shift value for TIMER_ICV3 */ #define _WTIMER_STATUS_ICV3_MASK 0x80000UL /**< Bit mask for TIMER_ICV3 */ #define _WTIMER_STATUS_ICV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ #define WTIMER_STATUS_ICV3_DEFAULT (_WTIMER_STATUS_ICV3_DEFAULT << 19) /**< Shifted mode DEFAULT for WTIMER_STATUS */ #define WTIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */ #define _WTIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ #define _WTIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ #define _WTIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ #define _WTIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ #define _WTIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ #define WTIMER_STATUS_CCPOL0_DEFAULT (_WTIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_STATUS */ #define WTIMER_STATUS_CCPOL0_LOWRISE (_WTIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for WTIMER_STATUS */ #define WTIMER_STATUS_CCPOL0_HIGHFALL (_WTIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ #define WTIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */ #define _WTIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ #define _WTIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ #define _WTIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ #define _WTIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ #define _WTIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ #define WTIMER_STATUS_CCPOL1_DEFAULT (_WTIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_STATUS */ #define WTIMER_STATUS_CCPOL1_LOWRISE (_WTIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for WTIMER_STATUS */ #define WTIMER_STATUS_CCPOL1_HIGHFALL (_WTIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ #define WTIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */ #define _WTIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ #define _WTIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ #define _WTIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ #define _WTIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ #define _WTIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ #define WTIMER_STATUS_CCPOL2_DEFAULT (_WTIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_STATUS */ #define WTIMER_STATUS_CCPOL2_LOWRISE (_WTIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for WTIMER_STATUS */ #define WTIMER_STATUS_CCPOL2_HIGHFALL (_WTIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ #define WTIMER_STATUS_CCPOL3 (0x1UL << 27) /**< CC3 Polarity */ #define _WTIMER_STATUS_CCPOL3_SHIFT 27 /**< Shift value for TIMER_CCPOL3 */ #define _WTIMER_STATUS_CCPOL3_MASK 0x8000000UL /**< Bit mask for TIMER_CCPOL3 */ #define _WTIMER_STATUS_CCPOL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ #define _WTIMER_STATUS_CCPOL3_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ #define _WTIMER_STATUS_CCPOL3_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ #define WTIMER_STATUS_CCPOL3_DEFAULT (_WTIMER_STATUS_CCPOL3_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_STATUS */ #define WTIMER_STATUS_CCPOL3_LOWRISE (_WTIMER_STATUS_CCPOL3_LOWRISE << 27) /**< Shifted mode LOWRISE for WTIMER_STATUS */ #define WTIMER_STATUS_CCPOL3_HIGHFALL (_WTIMER_STATUS_CCPOL3_HIGHFALL << 27) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ /* Bit fields for WTIMER IF */ #define _WTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IF */ #define _WTIMER_IF_MASK 0x00000FF7UL /**< Mask for WTIMER_IF */ #define WTIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ #define _WTIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ #define _WTIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ #define _WTIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ #define WTIMER_IF_OF_DEFAULT (_WTIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IF */ #define WTIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ #define _WTIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ #define _WTIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ #define _WTIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ #define WTIMER_IF_UF_DEFAULT (_WTIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IF */ #define WTIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ #define _WTIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ #define _WTIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ #define _WTIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ #define WTIMER_IF_DIRCHG_DEFAULT (_WTIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IF */ #define WTIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */ #define _WTIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ #define _WTIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ #define _WTIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ #define WTIMER_IF_CC0_DEFAULT (_WTIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IF */ #define WTIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */ #define _WTIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ #define _WTIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ #define _WTIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ #define WTIMER_IF_CC1_DEFAULT (_WTIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IF */ #define WTIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */ #define _WTIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ #define _WTIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ #define _WTIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ #define WTIMER_IF_CC2_DEFAULT (_WTIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IF */ #define WTIMER_IF_CC3 (0x1UL << 7) /**< CC Channel 3 Interrupt Flag */ #define _WTIMER_IF_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ #define _WTIMER_IF_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ #define _WTIMER_IF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ #define WTIMER_IF_CC3_DEFAULT (_WTIMER_IF_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IF */ #define WTIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */ #define _WTIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ #define _WTIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ #define _WTIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ #define WTIMER_IF_ICBOF0_DEFAULT (_WTIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IF */ #define WTIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */ #define _WTIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ #define _WTIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ #define _WTIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ #define WTIMER_IF_ICBOF1_DEFAULT (_WTIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IF */ #define WTIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */ #define _WTIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ #define _WTIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ #define _WTIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ #define WTIMER_IF_ICBOF2_DEFAULT (_WTIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IF */ #define WTIMER_IF_ICBOF3 (0x1UL << 11) /**< CC Channel 3 Input Capture Buffer Overflow Interrupt Flag */ #define _WTIMER_IF_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ #define _WTIMER_IF_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ #define _WTIMER_IF_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ #define WTIMER_IF_ICBOF3_DEFAULT (_WTIMER_IF_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IF */ /* Bit fields for WTIMER IFS */ #define _WTIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFS */ #define _WTIMER_IFS_MASK 0x00000FF7UL /**< Mask for WTIMER_IFS */ #define WTIMER_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */ #define _WTIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */ #define _WTIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ #define _WTIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ #define WTIMER_IFS_OF_DEFAULT (_WTIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFS */ #define WTIMER_IFS_UF (0x1UL << 1) /**< Set UF Interrupt Flag */ #define _WTIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */ #define _WTIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ #define _WTIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ #define WTIMER_IFS_UF_DEFAULT (_WTIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFS */ #define WTIMER_IFS_DIRCHG (0x1UL << 2) /**< Set DIRCHG Interrupt Flag */ #define _WTIMER_IFS_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ #define _WTIMER_IFS_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ #define _WTIMER_IFS_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ #define WTIMER_IFS_DIRCHG_DEFAULT (_WTIMER_IFS_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFS */ #define WTIMER_IFS_CC0 (0x1UL << 4) /**< Set CC0 Interrupt Flag */ #define _WTIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ #define _WTIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ #define _WTIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ #define WTIMER_IFS_CC0_DEFAULT (_WTIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFS */ #define WTIMER_IFS_CC1 (0x1UL << 5) /**< Set CC1 Interrupt Flag */ #define _WTIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ #define _WTIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ #define _WTIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ #define WTIMER_IFS_CC1_DEFAULT (_WTIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFS */ #define WTIMER_IFS_CC2 (0x1UL << 6) /**< Set CC2 Interrupt Flag */ #define _WTIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ #define _WTIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ #define _WTIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ #define WTIMER_IFS_CC2_DEFAULT (_WTIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFS */ #define WTIMER_IFS_CC3 (0x1UL << 7) /**< Set CC3 Interrupt Flag */ #define _WTIMER_IFS_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ #define _WTIMER_IFS_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ #define _WTIMER_IFS_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ #define WTIMER_IFS_CC3_DEFAULT (_WTIMER_IFS_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFS */ #define WTIMER_IFS_ICBOF0 (0x1UL << 8) /**< Set ICBOF0 Interrupt Flag */ #define _WTIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ #define _WTIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ #define _WTIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ #define WTIMER_IFS_ICBOF0_DEFAULT (_WTIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFS */ #define WTIMER_IFS_ICBOF1 (0x1UL << 9) /**< Set ICBOF1 Interrupt Flag */ #define _WTIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ #define _WTIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ #define _WTIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ #define WTIMER_IFS_ICBOF1_DEFAULT (_WTIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFS */ #define WTIMER_IFS_ICBOF2 (0x1UL << 10) /**< Set ICBOF2 Interrupt Flag */ #define _WTIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ #define _WTIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ #define _WTIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ #define WTIMER_IFS_ICBOF2_DEFAULT (_WTIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFS */ #define WTIMER_IFS_ICBOF3 (0x1UL << 11) /**< Set ICBOF3 Interrupt Flag */ #define _WTIMER_IFS_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ #define _WTIMER_IFS_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ #define _WTIMER_IFS_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ #define WTIMER_IFS_ICBOF3_DEFAULT (_WTIMER_IFS_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFS */ /* Bit fields for WTIMER IFC */ #define _WTIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFC */ #define _WTIMER_IFC_MASK 0x00000FF7UL /**< Mask for WTIMER_IFC */ #define WTIMER_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */ #define _WTIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */ #define _WTIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ #define _WTIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ #define WTIMER_IFC_OF_DEFAULT (_WTIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFC */ #define WTIMER_IFC_UF (0x1UL << 1) /**< Clear UF Interrupt Flag */ #define _WTIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */ #define _WTIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ #define _WTIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ #define WTIMER_IFC_UF_DEFAULT (_WTIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFC */ #define WTIMER_IFC_DIRCHG (0x1UL << 2) /**< Clear DIRCHG Interrupt Flag */ #define _WTIMER_IFC_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ #define _WTIMER_IFC_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ #define _WTIMER_IFC_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ #define WTIMER_IFC_DIRCHG_DEFAULT (_WTIMER_IFC_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFC */ #define WTIMER_IFC_CC0 (0x1UL << 4) /**< Clear CC0 Interrupt Flag */ #define _WTIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ #define _WTIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ #define _WTIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ #define WTIMER_IFC_CC0_DEFAULT (_WTIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFC */ #define WTIMER_IFC_CC1 (0x1UL << 5) /**< Clear CC1 Interrupt Flag */ #define _WTIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ #define _WTIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ #define _WTIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ #define WTIMER_IFC_CC1_DEFAULT (_WTIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFC */ #define WTIMER_IFC_CC2 (0x1UL << 6) /**< Clear CC2 Interrupt Flag */ #define _WTIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ #define _WTIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ #define _WTIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ #define WTIMER_IFC_CC2_DEFAULT (_WTIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFC */ #define WTIMER_IFC_CC3 (0x1UL << 7) /**< Clear CC3 Interrupt Flag */ #define _WTIMER_IFC_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ #define _WTIMER_IFC_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ #define _WTIMER_IFC_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ #define WTIMER_IFC_CC3_DEFAULT (_WTIMER_IFC_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFC */ #define WTIMER_IFC_ICBOF0 (0x1UL << 8) /**< Clear ICBOF0 Interrupt Flag */ #define _WTIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ #define _WTIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ #define _WTIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ #define WTIMER_IFC_ICBOF0_DEFAULT (_WTIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFC */ #define WTIMER_IFC_ICBOF1 (0x1UL << 9) /**< Clear ICBOF1 Interrupt Flag */ #define _WTIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ #define _WTIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ #define _WTIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ #define WTIMER_IFC_ICBOF1_DEFAULT (_WTIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFC */ #define WTIMER_IFC_ICBOF2 (0x1UL << 10) /**< Clear ICBOF2 Interrupt Flag */ #define _WTIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ #define _WTIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ #define _WTIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ #define WTIMER_IFC_ICBOF2_DEFAULT (_WTIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFC */ #define WTIMER_IFC_ICBOF3 (0x1UL << 11) /**< Clear ICBOF3 Interrupt Flag */ #define _WTIMER_IFC_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ #define _WTIMER_IFC_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ #define _WTIMER_IFC_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ #define WTIMER_IFC_ICBOF3_DEFAULT (_WTIMER_IFC_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFC */ /* Bit fields for WTIMER IEN */ #define _WTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IEN */ #define _WTIMER_IEN_MASK 0x00000FF7UL /**< Mask for WTIMER_IEN */ #define WTIMER_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ #define _WTIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ #define _WTIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ #define _WTIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ #define WTIMER_IEN_OF_DEFAULT (_WTIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IEN */ #define WTIMER_IEN_UF (0x1UL << 1) /**< UF Interrupt Enable */ #define _WTIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ #define _WTIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ #define _WTIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ #define WTIMER_IEN_UF_DEFAULT (_WTIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IEN */ #define WTIMER_IEN_DIRCHG (0x1UL << 2) /**< DIRCHG Interrupt Enable */ #define _WTIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ #define _WTIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ #define _WTIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ #define WTIMER_IEN_DIRCHG_DEFAULT (_WTIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IEN */ #define WTIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ #define _WTIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ #define _WTIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ #define _WTIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ #define WTIMER_IEN_CC0_DEFAULT (_WTIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IEN */ #define WTIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ #define _WTIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ #define _WTIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ #define _WTIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ #define WTIMER_IEN_CC1_DEFAULT (_WTIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IEN */ #define WTIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ #define _WTIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ #define _WTIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ #define _WTIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ #define WTIMER_IEN_CC2_DEFAULT (_WTIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IEN */ #define WTIMER_IEN_CC3 (0x1UL << 7) /**< CC3 Interrupt Enable */ #define _WTIMER_IEN_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ #define _WTIMER_IEN_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ #define _WTIMER_IEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ #define WTIMER_IEN_CC3_DEFAULT (_WTIMER_IEN_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IEN */ #define WTIMER_IEN_ICBOF0 (0x1UL << 8) /**< ICBOF0 Interrupt Enable */ #define _WTIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ #define _WTIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ #define _WTIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ #define WTIMER_IEN_ICBOF0_DEFAULT (_WTIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IEN */ #define WTIMER_IEN_ICBOF1 (0x1UL << 9) /**< ICBOF1 Interrupt Enable */ #define _WTIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ #define _WTIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ #define _WTIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ #define WTIMER_IEN_ICBOF1_DEFAULT (_WTIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IEN */ #define WTIMER_IEN_ICBOF2 (0x1UL << 10) /**< ICBOF2 Interrupt Enable */ #define _WTIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ #define _WTIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ #define _WTIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ #define WTIMER_IEN_ICBOF2_DEFAULT (_WTIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IEN */ #define WTIMER_IEN_ICBOF3 (0x1UL << 11) /**< ICBOF3 Interrupt Enable */ #define _WTIMER_IEN_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ #define _WTIMER_IEN_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ #define _WTIMER_IEN_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ #define WTIMER_IEN_ICBOF3_DEFAULT (_WTIMER_IEN_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IEN */ /* Bit fields for WTIMER TOP */ #define _WTIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for WTIMER_TOP */ #define _WTIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOP */ #define _WTIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ #define _WTIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */ #define _WTIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for WTIMER_TOP */ #define WTIMER_TOP_TOP_DEFAULT (_WTIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOP */ /* Bit fields for WTIMER TOPB */ #define _WTIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_TOPB */ #define _WTIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOPB */ #define _WTIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ #define _WTIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */ #define _WTIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_TOPB */ #define WTIMER_TOPB_TOPB_DEFAULT (_WTIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOPB */ /* Bit fields for WTIMER CNT */ #define _WTIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CNT */ #define _WTIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CNT */ #define _WTIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ #define _WTIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */ #define _WTIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CNT */ #define WTIMER_CNT_CNT_DEFAULT (_WTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CNT */ /* Bit fields for WTIMER LOCK */ #define _WTIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_LOCK */ #define _WTIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_LOCK */ #define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */ #define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */ #define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */ #define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */ #define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */ #define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */ #define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */ #define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */ #define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */ #define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */ #define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */ #define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */ /* Bit fields for WTIMER ROUTEPEN */ #define _WTIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTEPEN */ #define _WTIMER_ROUTEPEN_MASK 0x0000070FUL /**< Mask for WTIMER_ROUTEPEN */ #define WTIMER_ROUTEPEN_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */ #define _WTIMER_ROUTEPEN_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */ #define _WTIMER_ROUTEPEN_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */ #define _WTIMER_ROUTEPEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ #define WTIMER_ROUTEPEN_CC0PEN_DEFAULT (_WTIMER_ROUTEPEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ #define WTIMER_ROUTEPEN_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */ #define _WTIMER_ROUTEPEN_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */ #define _WTIMER_ROUTEPEN_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */ #define _WTIMER_ROUTEPEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ #define WTIMER_ROUTEPEN_CC1PEN_DEFAULT (_WTIMER_ROUTEPEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ #define WTIMER_ROUTEPEN_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */ #define _WTIMER_ROUTEPEN_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */ #define _WTIMER_ROUTEPEN_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */ #define _WTIMER_ROUTEPEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ #define WTIMER_ROUTEPEN_CC2PEN_DEFAULT (_WTIMER_ROUTEPEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ #define WTIMER_ROUTEPEN_CC3PEN (0x1UL << 3) /**< CC Channel 3 Pin Enable */ #define _WTIMER_ROUTEPEN_CC3PEN_SHIFT 3 /**< Shift value for TIMER_CC3PEN */ #define _WTIMER_ROUTEPEN_CC3PEN_MASK 0x8UL /**< Bit mask for TIMER_CC3PEN */ #define _WTIMER_ROUTEPEN_CC3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ #define WTIMER_ROUTEPEN_CC3PEN_DEFAULT (_WTIMER_ROUTEPEN_CC3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ #define WTIMER_ROUTEPEN_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */ #define _WTIMER_ROUTEPEN_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */ #define _WTIMER_ROUTEPEN_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */ #define _WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ #define WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ #define WTIMER_ROUTEPEN_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */ #define _WTIMER_ROUTEPEN_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */ #define _WTIMER_ROUTEPEN_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */ #define _WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ #define WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ #define WTIMER_ROUTEPEN_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */ #define _WTIMER_ROUTEPEN_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */ #define _WTIMER_ROUTEPEN_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */ #define _WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ #define WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ /* Bit fields for WTIMER ROUTELOC0 */ #define _WTIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_MASK 0x1F1F1F1FUL /**< Mask for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC0LOC_SHIFT 0 /**< Shift value for TIMER_CC0LOC */ #define _WTIMER_ROUTELOC0_CC0LOC_MASK 0x1FUL /**< Bit mask for TIMER_CC0LOC */ #define _WTIMER_ROUTELOC0_CC0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC0LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC0LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC0LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC0LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC0LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC0LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC0LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC0LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC0LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC0LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC0LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC0LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC0LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC0LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC0LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC0LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC0LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC0LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC0LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC0LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC0LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC0LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC0LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC0LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC0LOC_LOC0 (_WTIMER_ROUTELOC0_CC0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC0LOC_DEFAULT (_WTIMER_ROUTELOC0_CC0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC0LOC_LOC1 (_WTIMER_ROUTELOC0_CC0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC0LOC_LOC2 (_WTIMER_ROUTELOC0_CC0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC0LOC_LOC3 (_WTIMER_ROUTELOC0_CC0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC0LOC_LOC4 (_WTIMER_ROUTELOC0_CC0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC0LOC_LOC5 (_WTIMER_ROUTELOC0_CC0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC0LOC_LOC6 (_WTIMER_ROUTELOC0_CC0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC0LOC_LOC7 (_WTIMER_ROUTELOC0_CC0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC0LOC_LOC8 (_WTIMER_ROUTELOC0_CC0LOC_LOC8 << 0) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC0LOC_LOC9 (_WTIMER_ROUTELOC0_CC0LOC_LOC9 << 0) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC0LOC_LOC10 (_WTIMER_ROUTELOC0_CC0LOC_LOC10 << 0) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC0LOC_LOC11 (_WTIMER_ROUTELOC0_CC0LOC_LOC11 << 0) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC0LOC_LOC12 (_WTIMER_ROUTELOC0_CC0LOC_LOC12 << 0) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC0LOC_LOC13 (_WTIMER_ROUTELOC0_CC0LOC_LOC13 << 0) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC0LOC_LOC14 (_WTIMER_ROUTELOC0_CC0LOC_LOC14 << 0) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC0LOC_LOC15 (_WTIMER_ROUTELOC0_CC0LOC_LOC15 << 0) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC0LOC_LOC16 (_WTIMER_ROUTELOC0_CC0LOC_LOC16 << 0) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC0LOC_LOC17 (_WTIMER_ROUTELOC0_CC0LOC_LOC17 << 0) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC0LOC_LOC18 (_WTIMER_ROUTELOC0_CC0LOC_LOC18 << 0) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC0LOC_LOC19 (_WTIMER_ROUTELOC0_CC0LOC_LOC19 << 0) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC0LOC_LOC20 (_WTIMER_ROUTELOC0_CC0LOC_LOC20 << 0) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC0LOC_LOC21 (_WTIMER_ROUTELOC0_CC0LOC_LOC21 << 0) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC0LOC_LOC22 (_WTIMER_ROUTELOC0_CC0LOC_LOC22 << 0) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC0LOC_LOC23 (_WTIMER_ROUTELOC0_CC0LOC_LOC23 << 0) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC0LOC_LOC24 (_WTIMER_ROUTELOC0_CC0LOC_LOC24 << 0) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC0LOC_LOC25 (_WTIMER_ROUTELOC0_CC0LOC_LOC25 << 0) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC0LOC_LOC26 (_WTIMER_ROUTELOC0_CC0LOC_LOC26 << 0) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC0LOC_LOC27 (_WTIMER_ROUTELOC0_CC0LOC_LOC27 << 0) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC0LOC_LOC28 (_WTIMER_ROUTELOC0_CC0LOC_LOC28 << 0) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC0LOC_LOC29 (_WTIMER_ROUTELOC0_CC0LOC_LOC29 << 0) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC0LOC_LOC30 (_WTIMER_ROUTELOC0_CC0LOC_LOC30 << 0) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC0LOC_LOC31 (_WTIMER_ROUTELOC0_CC0LOC_LOC31 << 0) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC1LOC_SHIFT 8 /**< Shift value for TIMER_CC1LOC */ #define _WTIMER_ROUTELOC0_CC1LOC_MASK 0x1F00UL /**< Bit mask for TIMER_CC1LOC */ #define _WTIMER_ROUTELOC0_CC1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC1LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC1LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC1LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC1LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC1LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC1LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC1LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC1LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC1LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC1LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC1LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC1LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC1LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC1LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC1LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC1LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC1LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC1LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC1LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC1LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC1LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC1LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC1LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC1LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC1LOC_LOC0 (_WTIMER_ROUTELOC0_CC1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC1LOC_DEFAULT (_WTIMER_ROUTELOC0_CC1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC1LOC_LOC1 (_WTIMER_ROUTELOC0_CC1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC1LOC_LOC2 (_WTIMER_ROUTELOC0_CC1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC1LOC_LOC3 (_WTIMER_ROUTELOC0_CC1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC1LOC_LOC4 (_WTIMER_ROUTELOC0_CC1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC1LOC_LOC5 (_WTIMER_ROUTELOC0_CC1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC1LOC_LOC6 (_WTIMER_ROUTELOC0_CC1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC1LOC_LOC7 (_WTIMER_ROUTELOC0_CC1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC1LOC_LOC8 (_WTIMER_ROUTELOC0_CC1LOC_LOC8 << 8) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC1LOC_LOC9 (_WTIMER_ROUTELOC0_CC1LOC_LOC9 << 8) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC1LOC_LOC10 (_WTIMER_ROUTELOC0_CC1LOC_LOC10 << 8) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC1LOC_LOC11 (_WTIMER_ROUTELOC0_CC1LOC_LOC11 << 8) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC1LOC_LOC12 (_WTIMER_ROUTELOC0_CC1LOC_LOC12 << 8) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC1LOC_LOC13 (_WTIMER_ROUTELOC0_CC1LOC_LOC13 << 8) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC1LOC_LOC14 (_WTIMER_ROUTELOC0_CC1LOC_LOC14 << 8) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC1LOC_LOC15 (_WTIMER_ROUTELOC0_CC1LOC_LOC15 << 8) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC1LOC_LOC16 (_WTIMER_ROUTELOC0_CC1LOC_LOC16 << 8) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC1LOC_LOC17 (_WTIMER_ROUTELOC0_CC1LOC_LOC17 << 8) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC1LOC_LOC18 (_WTIMER_ROUTELOC0_CC1LOC_LOC18 << 8) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC1LOC_LOC19 (_WTIMER_ROUTELOC0_CC1LOC_LOC19 << 8) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC1LOC_LOC20 (_WTIMER_ROUTELOC0_CC1LOC_LOC20 << 8) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC1LOC_LOC21 (_WTIMER_ROUTELOC0_CC1LOC_LOC21 << 8) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC1LOC_LOC22 (_WTIMER_ROUTELOC0_CC1LOC_LOC22 << 8) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC1LOC_LOC23 (_WTIMER_ROUTELOC0_CC1LOC_LOC23 << 8) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC1LOC_LOC24 (_WTIMER_ROUTELOC0_CC1LOC_LOC24 << 8) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC1LOC_LOC25 (_WTIMER_ROUTELOC0_CC1LOC_LOC25 << 8) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC1LOC_LOC26 (_WTIMER_ROUTELOC0_CC1LOC_LOC26 << 8) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC1LOC_LOC27 (_WTIMER_ROUTELOC0_CC1LOC_LOC27 << 8) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC1LOC_LOC28 (_WTIMER_ROUTELOC0_CC1LOC_LOC28 << 8) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC1LOC_LOC29 (_WTIMER_ROUTELOC0_CC1LOC_LOC29 << 8) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC1LOC_LOC30 (_WTIMER_ROUTELOC0_CC1LOC_LOC30 << 8) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC1LOC_LOC31 (_WTIMER_ROUTELOC0_CC1LOC_LOC31 << 8) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC2LOC_SHIFT 16 /**< Shift value for TIMER_CC2LOC */ #define _WTIMER_ROUTELOC0_CC2LOC_MASK 0x1F0000UL /**< Bit mask for TIMER_CC2LOC */ #define _WTIMER_ROUTELOC0_CC2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC2LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC2LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC2LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC2LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC2LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC2LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC2LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC2LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC2LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC2LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC2LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC2LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC2LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC2LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC2LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC2LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC2LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC2LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC2LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC2LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC2LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC2LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC2LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC2LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC2LOC_LOC0 (_WTIMER_ROUTELOC0_CC2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC2LOC_DEFAULT (_WTIMER_ROUTELOC0_CC2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC2LOC_LOC1 (_WTIMER_ROUTELOC0_CC2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC2LOC_LOC2 (_WTIMER_ROUTELOC0_CC2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC2LOC_LOC3 (_WTIMER_ROUTELOC0_CC2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC2LOC_LOC4 (_WTIMER_ROUTELOC0_CC2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC2LOC_LOC5 (_WTIMER_ROUTELOC0_CC2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC2LOC_LOC6 (_WTIMER_ROUTELOC0_CC2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC2LOC_LOC7 (_WTIMER_ROUTELOC0_CC2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC2LOC_LOC8 (_WTIMER_ROUTELOC0_CC2LOC_LOC8 << 16) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC2LOC_LOC9 (_WTIMER_ROUTELOC0_CC2LOC_LOC9 << 16) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC2LOC_LOC10 (_WTIMER_ROUTELOC0_CC2LOC_LOC10 << 16) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC2LOC_LOC11 (_WTIMER_ROUTELOC0_CC2LOC_LOC11 << 16) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC2LOC_LOC12 (_WTIMER_ROUTELOC0_CC2LOC_LOC12 << 16) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC2LOC_LOC13 (_WTIMER_ROUTELOC0_CC2LOC_LOC13 << 16) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC2LOC_LOC14 (_WTIMER_ROUTELOC0_CC2LOC_LOC14 << 16) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC2LOC_LOC15 (_WTIMER_ROUTELOC0_CC2LOC_LOC15 << 16) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC2LOC_LOC16 (_WTIMER_ROUTELOC0_CC2LOC_LOC16 << 16) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC2LOC_LOC17 (_WTIMER_ROUTELOC0_CC2LOC_LOC17 << 16) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC2LOC_LOC18 (_WTIMER_ROUTELOC0_CC2LOC_LOC18 << 16) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC2LOC_LOC19 (_WTIMER_ROUTELOC0_CC2LOC_LOC19 << 16) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC2LOC_LOC20 (_WTIMER_ROUTELOC0_CC2LOC_LOC20 << 16) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC2LOC_LOC21 (_WTIMER_ROUTELOC0_CC2LOC_LOC21 << 16) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC2LOC_LOC22 (_WTIMER_ROUTELOC0_CC2LOC_LOC22 << 16) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC2LOC_LOC23 (_WTIMER_ROUTELOC0_CC2LOC_LOC23 << 16) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC2LOC_LOC24 (_WTIMER_ROUTELOC0_CC2LOC_LOC24 << 16) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC2LOC_LOC25 (_WTIMER_ROUTELOC0_CC2LOC_LOC25 << 16) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC2LOC_LOC26 (_WTIMER_ROUTELOC0_CC2LOC_LOC26 << 16) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC2LOC_LOC27 (_WTIMER_ROUTELOC0_CC2LOC_LOC27 << 16) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC2LOC_LOC28 (_WTIMER_ROUTELOC0_CC2LOC_LOC28 << 16) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC2LOC_LOC29 (_WTIMER_ROUTELOC0_CC2LOC_LOC29 << 16) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC2LOC_LOC30 (_WTIMER_ROUTELOC0_CC2LOC_LOC30 << 16) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC2LOC_LOC31 (_WTIMER_ROUTELOC0_CC2LOC_LOC31 << 16) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC3LOC_SHIFT 24 /**< Shift value for TIMER_CC3LOC */ #define _WTIMER_ROUTELOC0_CC3LOC_MASK 0x1F000000UL /**< Bit mask for TIMER_CC3LOC */ #define _WTIMER_ROUTELOC0_CC3LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC3LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC3LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC3LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC3LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC3LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC3LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC3LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC3LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC3LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC3LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC3LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC3LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC3LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC3LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC3LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC3LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC3LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC3LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC3LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC3LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC3LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC3LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC3LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC3LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC3LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC3LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC3LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC3LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC3LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC3LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ #define _WTIMER_ROUTELOC0_CC3LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC3LOC_LOC0 (_WTIMER_ROUTELOC0_CC3LOC_LOC0 << 24) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC3LOC_DEFAULT (_WTIMER_ROUTELOC0_CC3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC3LOC_LOC1 (_WTIMER_ROUTELOC0_CC3LOC_LOC1 << 24) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC3LOC_LOC2 (_WTIMER_ROUTELOC0_CC3LOC_LOC2 << 24) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC3LOC_LOC3 (_WTIMER_ROUTELOC0_CC3LOC_LOC3 << 24) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC3LOC_LOC4 (_WTIMER_ROUTELOC0_CC3LOC_LOC4 << 24) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC3LOC_LOC5 (_WTIMER_ROUTELOC0_CC3LOC_LOC5 << 24) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC3LOC_LOC6 (_WTIMER_ROUTELOC0_CC3LOC_LOC6 << 24) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC3LOC_LOC7 (_WTIMER_ROUTELOC0_CC3LOC_LOC7 << 24) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC3LOC_LOC8 (_WTIMER_ROUTELOC0_CC3LOC_LOC8 << 24) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC3LOC_LOC9 (_WTIMER_ROUTELOC0_CC3LOC_LOC9 << 24) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC3LOC_LOC10 (_WTIMER_ROUTELOC0_CC3LOC_LOC10 << 24) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC3LOC_LOC11 (_WTIMER_ROUTELOC0_CC3LOC_LOC11 << 24) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC3LOC_LOC12 (_WTIMER_ROUTELOC0_CC3LOC_LOC12 << 24) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC3LOC_LOC13 (_WTIMER_ROUTELOC0_CC3LOC_LOC13 << 24) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC3LOC_LOC14 (_WTIMER_ROUTELOC0_CC3LOC_LOC14 << 24) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC3LOC_LOC15 (_WTIMER_ROUTELOC0_CC3LOC_LOC15 << 24) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC3LOC_LOC16 (_WTIMER_ROUTELOC0_CC3LOC_LOC16 << 24) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC3LOC_LOC17 (_WTIMER_ROUTELOC0_CC3LOC_LOC17 << 24) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC3LOC_LOC18 (_WTIMER_ROUTELOC0_CC3LOC_LOC18 << 24) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC3LOC_LOC19 (_WTIMER_ROUTELOC0_CC3LOC_LOC19 << 24) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC3LOC_LOC20 (_WTIMER_ROUTELOC0_CC3LOC_LOC20 << 24) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC3LOC_LOC21 (_WTIMER_ROUTELOC0_CC3LOC_LOC21 << 24) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC3LOC_LOC22 (_WTIMER_ROUTELOC0_CC3LOC_LOC22 << 24) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC3LOC_LOC23 (_WTIMER_ROUTELOC0_CC3LOC_LOC23 << 24) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC3LOC_LOC24 (_WTIMER_ROUTELOC0_CC3LOC_LOC24 << 24) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC3LOC_LOC25 (_WTIMER_ROUTELOC0_CC3LOC_LOC25 << 24) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC3LOC_LOC26 (_WTIMER_ROUTELOC0_CC3LOC_LOC26 << 24) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC3LOC_LOC27 (_WTIMER_ROUTELOC0_CC3LOC_LOC27 << 24) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC3LOC_LOC28 (_WTIMER_ROUTELOC0_CC3LOC_LOC28 << 24) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC3LOC_LOC29 (_WTIMER_ROUTELOC0_CC3LOC_LOC29 << 24) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC3LOC_LOC30 (_WTIMER_ROUTELOC0_CC3LOC_LOC30 << 24) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ #define WTIMER_ROUTELOC0_CC3LOC_LOC31 (_WTIMER_ROUTELOC0_CC3LOC_LOC31 << 24) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ /* Bit fields for WTIMER ROUTELOC2 */ #define _WTIMER_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC2 */ #define _WTIMER_ROUTELOC2_MASK 0x001F1F1FUL /**< Mask for WTIMER_ROUTELOC2 */ #define _WTIMER_ROUTELOC2_CDTI0LOC_SHIFT 0 /**< Shift value for TIMER_CDTI0LOC */ #define _WTIMER_ROUTELOC2_CDTI0LOC_MASK 0x1FUL /**< Bit mask for TIMER_CDTI0LOC */ #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ #define _WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC2 */ #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC2 */ #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC2 */ #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC2 */ #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC2 */ #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC2 */ #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC2 */ #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC2 */ #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC2 */ #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC2 */ #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC2 */ #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC2 */ #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC2 */ #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC2 */ #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC2 */ #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC2 */ #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC2 */ #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC2 */ #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC2 */ #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC2 */ #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC2 */ #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC2 */ #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC2 */ #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC2 */ #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC2 */ #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC2 */ #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC2 */ #define WTIMER_ROUTELOC2_CDTI0LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ #define WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ #define WTIMER_ROUTELOC2_CDTI0LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ #define WTIMER_ROUTELOC2_CDTI0LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ #define WTIMER_ROUTELOC2_CDTI0LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ #define WTIMER_ROUTELOC2_CDTI0LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ #define WTIMER_ROUTELOC2_CDTI0LOC_LOC5 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC2 */ #define WTIMER_ROUTELOC2_CDTI0LOC_LOC6 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC2 */ #define WTIMER_ROUTELOC2_CDTI0LOC_LOC7 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC2 */ #define WTIMER_ROUTELOC2_CDTI0LOC_LOC8 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC8 << 0) /**< Shifted mode LOC8 for WTIMER_ROUTELOC2 */ #define WTIMER_ROUTELOC2_CDTI0LOC_LOC9 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC9 << 0) /**< Shifted mode LOC9 for WTIMER_ROUTELOC2 */ #define WTIMER_ROUTELOC2_CDTI0LOC_LOC10 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC10 << 0) /**< Shifted mode LOC10 for WTIMER_ROUTELOC2 */ #define WTIMER_ROUTELOC2_CDTI0LOC_LOC11 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC11 << 0) /**< Shifted mode LOC11 for WTIMER_ROUTELOC2 */ #define WTIMER_ROUTELOC2_CDTI0LOC_LOC12 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC12 << 0) /**< Shifted mode LOC12 for WTIMER_ROUTELOC2 */ #define WTIMER_ROUTELOC2_CDTI0LOC_LOC13 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC13 << 0) /**< Shifted mode LOC13 for WTIMER_ROUTELOC2 */ #define WTIMER_ROUTELOC2_CDTI0LOC_LOC14 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC14 << 0) /**< Shifted mode LOC14 for WTIMER_ROUTELOC2 */ #define WTIMER_ROUTELOC2_CDTI0LOC_LOC15 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC15 << 0) /**< Shifted mode LOC15 for WTIMER_ROUTELOC2 */ #define WTIMER_ROUTELOC2_CDTI0LOC_LOC16 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC16 << 0) /**< Shifted mode LOC16 for WTIMER_ROUTELOC2 */ #define WTIMER_ROUTELOC2_CDTI0LOC_LOC17 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC17 << 0) /**< Shifted mode LOC17 for WTIMER_ROUTELOC2 */ #define WTIMER_ROUTELOC2_CDTI0LOC_LOC18 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC18 << 0) /**< Shifted mode LOC18 for WTIMER_ROUTELOC2 */ #define WTIMER_ROUTELOC2_CDTI0LOC_LOC19 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC19 << 0) /**< Shifted mode LOC19 for WTIMER_ROUTELOC2 */ #define WTIMER_ROUTELOC2_CDTI0LOC_LOC20 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC20 << 0) /**< Shifted mode LOC20 for WTIMER_ROUTELOC2 */ #define WTIMER_ROUTELOC2_CDTI0LOC_LOC21 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC21 << 0) /**< Shifted mode LOC21 for WTIMER_ROUTELOC2 */ #define WTIMER_ROUTELOC2_CDTI0LOC_LOC22 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC22 << 0) /**< Shifted mode LOC22 for WTIMER_ROUTELOC2 */ #define WTIMER_ROUTELOC2_CDTI0LOC_LOC23 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC23 << 0) /**< Shifted mode LOC23 for WTIMER_ROUTELOC2 */ #define WTIMER_ROUTELOC2_CDTI0LOC_LOC24 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC24 << 0) /**< Shifted mode LOC24 for WTIMER_ROUTELOC2 */ #define WTIMER_ROUTELOC2_CDTI0LOC_LOC25 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC25 << 0) /**< Shifted mode LOC25 for WTIMER_ROUTELOC2 */ #define WTIMER_ROUTELOC2_CDTI0LOC_LOC26 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC26 << 0) /**< Shifted mode LOC26 for WTIMER_ROUTELOC2 */ #define WTIMER_ROUTELOC2_CDTI0LOC_LOC27 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC27 << 0) /**< Shifted mode LOC27 for WTIMER_ROUTELOC2 */ #define WTIMER_ROUTELOC2_CDTI0LOC_LOC28 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC28 << 0) /**< Shifted mode LOC28 for WTIMER_ROUTELOC2 */ #define WTIMER_ROUTELOC2_CDTI0LOC_LOC29 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC29 << 0) /**< Shifted mode LOC29 for WTIMER_ROUTELOC2 */ #define WTIMER_ROUTELOC2_CDTI0LOC_LOC30 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC30 << 0) /**< Shifted mode LOC30 for WTIMER_ROUTELOC2 */ #define WTIMER_ROUTELOC2_CDTI0LOC_LOC31 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC31 << 0) /**< Shifted mode LOC31 for WTIMER_ROUTELOC2 */ #define _WTIMER_ROUTELOC2_CDTI1LOC_SHIFT 8 /**< Shift value for TIMER_CDTI1LOC */ #define _WTIMER_ROUTELOC2_CDTI1LOC_MASK 0x1F00UL /**< Bit mask for TIMER_CDTI1LOC */ #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ #define _WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC2 */ #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC2 */ #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC2 */ #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC2 */ #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC2 */ #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC2 */ #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC2 */ #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC2 */ #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC2 */ #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC2 */ #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC2 */ #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC2 */ #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC2 */ #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC2 */ #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC2 */ #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC2 */ #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC2 */ #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC2 */ #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC2 */ #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC2 */ #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC2 */ #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC2 */ #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC2 */ #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC2 */ #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC2 */ #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC2 */ #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC2 */ #define WTIMER_ROUTELOC2_CDTI1LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ #define WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ #define WTIMER_ROUTELOC2_CDTI1LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ #define WTIMER_ROUTELOC2_CDTI1LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ #define WTIMER_ROUTELOC2_CDTI1LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ #define WTIMER_ROUTELOC2_CDTI1LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ #define WTIMER_ROUTELOC2_CDTI1LOC_LOC5 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC2 */ #define WTIMER_ROUTELOC2_CDTI1LOC_LOC6 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC2 */ #define WTIMER_ROUTELOC2_CDTI1LOC_LOC7 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC2 */ #define WTIMER_ROUTELOC2_CDTI1LOC_LOC8 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC8 << 8) /**< Shifted mode LOC8 for WTIMER_ROUTELOC2 */ #define WTIMER_ROUTELOC2_CDTI1LOC_LOC9 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC9 << 8) /**< Shifted mode LOC9 for WTIMER_ROUTELOC2 */ #define WTIMER_ROUTELOC2_CDTI1LOC_LOC10 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC10 << 8) /**< Shifted mode LOC10 for WTIMER_ROUTELOC2 */ #define WTIMER_ROUTELOC2_CDTI1LOC_LOC11 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC11 << 8) /**< Shifted mode LOC11 for WTIMER_ROUTELOC2 */ #define WTIMER_ROUTELOC2_CDTI1LOC_LOC12 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC12 << 8) /**< Shifted mode LOC12 for WTIMER_ROUTELOC2 */ #define WTIMER_ROUTELOC2_CDTI1LOC_LOC13 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC13 << 8) /**< Shifted mode LOC13 for WTIMER_ROUTELOC2 */ #define WTIMER_ROUTELOC2_CDTI1LOC_LOC14 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC14 << 8) /**< Shifted mode LOC14 for WTIMER_ROUTELOC2 */ #define WTIMER_ROUTELOC2_CDTI1LOC_LOC15 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC15 << 8) /**< Shifted mode LOC15 for WTIMER_ROUTELOC2 */ #define WTIMER_ROUTELOC2_CDTI1LOC_LOC16 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC16 << 8) /**< Shifted mode LOC16 for WTIMER_ROUTELOC2 */ #define WTIMER_ROUTELOC2_CDTI1LOC_LOC17 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC17 << 8) /**< Shifted mode LOC17 for WTIMER_ROUTELOC2 */ #define WTIMER_ROUTELOC2_CDTI1LOC_LOC18 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC18 << 8) /**< Shifted mode LOC18 for WTIMER_ROUTELOC2 */ #define WTIMER_ROUTELOC2_CDTI1LOC_LOC19 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC19 << 8) /**< Shifted mode LOC19 for WTIMER_ROUTELOC2 */ #define WTIMER_ROUTELOC2_CDTI1LOC_LOC20 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC20 << 8) /**< Shifted mode LOC20 for WTIMER_ROUTELOC2 */ #define WTIMER_ROUTELOC2_CDTI1LOC_LOC21 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC21 << 8) /**< Shifted mode LOC21 for WTIMER_ROUTELOC2 */ #define WTIMER_ROUTELOC2_CDTI1LOC_LOC22 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC22 << 8) /**< Shifted mode LOC22 for WTIMER_ROUTELOC2 */ #define WTIMER_ROUTELOC2_CDTI1LOC_LOC23 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC23 << 8) /**< Shifted mode LOC23 for WTIMER_ROUTELOC2 */ #define WTIMER_ROUTELOC2_CDTI1LOC_LOC24 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC24 << 8) /**< Shifted mode LOC24 for WTIMER_ROUTELOC2 */ #define WTIMER_ROUTELOC2_CDTI1LOC_LOC25 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC25 << 8) /**< Shifted mode LOC25 for WTIMER_ROUTELOC2 */ #define WTIMER_ROUTELOC2_CDTI1LOC_LOC26 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC26 << 8) /**< Shifted mode LOC26 for WTIMER_ROUTELOC2 */ #define WTIMER_ROUTELOC2_CDTI1LOC_LOC27 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC27 << 8) /**< Shifted mode LOC27 for WTIMER_ROUTELOC2 */ #define WTIMER_ROUTELOC2_CDTI1LOC_LOC28 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC28 << 8) /**< Shifted mode LOC28 for WTIMER_ROUTELOC2 */ #define WTIMER_ROUTELOC2_CDTI1LOC_LOC29 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC29 << 8) /**< Shifted mode LOC29 for WTIMER_ROUTELOC2 */ #define WTIMER_ROUTELOC2_CDTI1LOC_LOC30 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC30 << 8) /**< Shifted mode LOC30 for WTIMER_ROUTELOC2 */ #define WTIMER_ROUTELOC2_CDTI1LOC_LOC31 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC31 << 8) /**< Shifted mode LOC31 for WTIMER_ROUTELOC2 */ #define _WTIMER_ROUTELOC2_CDTI2LOC_SHIFT 16 /**< Shift value for TIMER_CDTI2LOC */ #define _WTIMER_ROUTELOC2_CDTI2LOC_MASK 0x1F0000UL /**< Bit mask for TIMER_CDTI2LOC */ #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ #define _WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC2 */ #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC2 */ #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC2 */ #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC2 */ #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC2 */ #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC2 */ #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC2 */ #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC2 */ #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC2 */ #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC2 */ #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC2 */ #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC2 */ #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC2 */ #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC2 */ #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC2 */ #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC2 */ #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC2 */ #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC2 */ #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC2 */ #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC2 */ #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC2 */ #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC2 */ #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC2 */ #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC2 */ #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC2 */ #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC2 */ #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC2 */ #define WTIMER_ROUTELOC2_CDTI2LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ #define WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ #define WTIMER_ROUTELOC2_CDTI2LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ #define WTIMER_ROUTELOC2_CDTI2LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ #define WTIMER_ROUTELOC2_CDTI2LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ #define WTIMER_ROUTELOC2_CDTI2LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ #define WTIMER_ROUTELOC2_CDTI2LOC_LOC5 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC2 */ #define WTIMER_ROUTELOC2_CDTI2LOC_LOC6 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC2 */ #define WTIMER_ROUTELOC2_CDTI2LOC_LOC7 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC2 */ #define WTIMER_ROUTELOC2_CDTI2LOC_LOC8 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC8 << 16) /**< Shifted mode LOC8 for WTIMER_ROUTELOC2 */ #define WTIMER_ROUTELOC2_CDTI2LOC_LOC9 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC9 << 16) /**< Shifted mode LOC9 for WTIMER_ROUTELOC2 */ #define WTIMER_ROUTELOC2_CDTI2LOC_LOC10 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC10 << 16) /**< Shifted mode LOC10 for WTIMER_ROUTELOC2 */ #define WTIMER_ROUTELOC2_CDTI2LOC_LOC11 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC11 << 16) /**< Shifted mode LOC11 for WTIMER_ROUTELOC2 */ #define WTIMER_ROUTELOC2_CDTI2LOC_LOC12 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC12 << 16) /**< Shifted mode LOC12 for WTIMER_ROUTELOC2 */ #define WTIMER_ROUTELOC2_CDTI2LOC_LOC13 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC13 << 16) /**< Shifted mode LOC13 for WTIMER_ROUTELOC2 */ #define WTIMER_ROUTELOC2_CDTI2LOC_LOC14 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC14 << 16) /**< Shifted mode LOC14 for WTIMER_ROUTELOC2 */ #define WTIMER_ROUTELOC2_CDTI2LOC_LOC15 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC15 << 16) /**< Shifted mode LOC15 for WTIMER_ROUTELOC2 */ #define WTIMER_ROUTELOC2_CDTI2LOC_LOC16 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC16 << 16) /**< Shifted mode LOC16 for WTIMER_ROUTELOC2 */ #define WTIMER_ROUTELOC2_CDTI2LOC_LOC17 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC17 << 16) /**< Shifted mode LOC17 for WTIMER_ROUTELOC2 */ #define WTIMER_ROUTELOC2_CDTI2LOC_LOC18 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC18 << 16) /**< Shifted mode LOC18 for WTIMER_ROUTELOC2 */ #define WTIMER_ROUTELOC2_CDTI2LOC_LOC19 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC19 << 16) /**< Shifted mode LOC19 for WTIMER_ROUTELOC2 */ #define WTIMER_ROUTELOC2_CDTI2LOC_LOC20 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC20 << 16) /**< Shifted mode LOC20 for WTIMER_ROUTELOC2 */ #define WTIMER_ROUTELOC2_CDTI2LOC_LOC21 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC21 << 16) /**< Shifted mode LOC21 for WTIMER_ROUTELOC2 */ #define WTIMER_ROUTELOC2_CDTI2LOC_LOC22 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC22 << 16) /**< Shifted mode LOC22 for WTIMER_ROUTELOC2 */ #define WTIMER_ROUTELOC2_CDTI2LOC_LOC23 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC23 << 16) /**< Shifted mode LOC23 for WTIMER_ROUTELOC2 */ #define WTIMER_ROUTELOC2_CDTI2LOC_LOC24 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC24 << 16) /**< Shifted mode LOC24 for WTIMER_ROUTELOC2 */ #define WTIMER_ROUTELOC2_CDTI2LOC_LOC25 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC25 << 16) /**< Shifted mode LOC25 for WTIMER_ROUTELOC2 */ #define WTIMER_ROUTELOC2_CDTI2LOC_LOC26 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC26 << 16) /**< Shifted mode LOC26 for WTIMER_ROUTELOC2 */ #define WTIMER_ROUTELOC2_CDTI2LOC_LOC27 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC27 << 16) /**< Shifted mode LOC27 for WTIMER_ROUTELOC2 */ #define WTIMER_ROUTELOC2_CDTI2LOC_LOC28 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC28 << 16) /**< Shifted mode LOC28 for WTIMER_ROUTELOC2 */ #define WTIMER_ROUTELOC2_CDTI2LOC_LOC29 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC29 << 16) /**< Shifted mode LOC29 for WTIMER_ROUTELOC2 */ #define WTIMER_ROUTELOC2_CDTI2LOC_LOC30 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC30 << 16) /**< Shifted mode LOC30 for WTIMER_ROUTELOC2 */ #define WTIMER_ROUTELOC2_CDTI2LOC_LOC31 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC31 << 16) /**< Shifted mode LOC31 for WTIMER_ROUTELOC2 */ /* Bit fields for WTIMER CC_CTRL */ #define _WTIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CTRL */ #define _WTIMER_CC_CTRL_MASK 0x7F0F3F17UL /**< Mask for WTIMER_CC_CTRL */ #define _WTIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ #define _WTIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ #define _WTIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ #define _WTIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for WTIMER_CC_CTRL */ #define _WTIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for WTIMER_CC_CTRL */ #define _WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ #define _WTIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for WTIMER_CC_CTRL */ #define WTIMER_CC_CTRL_MODE_DEFAULT (_WTIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ #define WTIMER_CC_CTRL_MODE_OFF (_WTIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for WTIMER_CC_CTRL */ #define WTIMER_CC_CTRL_MODE_INPUTCAPTURE (_WTIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for WTIMER_CC_CTRL */ #define WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ #define WTIMER_CC_CTRL_MODE_PWM (_WTIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for WTIMER_CC_CTRL */ #define WTIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ #define _WTIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ #define _WTIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ #define _WTIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ #define WTIMER_CC_CTRL_OUTINV_DEFAULT (_WTIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ #define WTIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */ #define _WTIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ #define _WTIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ #define _WTIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ #define WTIMER_CC_CTRL_COIST_DEFAULT (_WTIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ #define _WTIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ #define _WTIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ #define _WTIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ #define _WTIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ #define _WTIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ #define _WTIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ #define _WTIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ #define WTIMER_CC_CTRL_CMOA_DEFAULT (_WTIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ #define WTIMER_CC_CTRL_CMOA_NONE (_WTIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for WTIMER_CC_CTRL */ #define WTIMER_CC_CTRL_CMOA_TOGGLE (_WTIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ #define WTIMER_CC_CTRL_CMOA_CLEAR (_WTIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ #define WTIMER_CC_CTRL_CMOA_SET (_WTIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for WTIMER_CC_CTRL */ #define _WTIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ #define _WTIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ #define _WTIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ #define _WTIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ #define _WTIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ #define _WTIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ #define _WTIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ #define WTIMER_CC_CTRL_COFOA_DEFAULT (_WTIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ #define WTIMER_CC_CTRL_COFOA_NONE (_WTIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for WTIMER_CC_CTRL */ #define WTIMER_CC_CTRL_COFOA_TOGGLE (_WTIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ #define WTIMER_CC_CTRL_COFOA_CLEAR (_WTIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ #define WTIMER_CC_CTRL_COFOA_SET (_WTIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for WTIMER_CC_CTRL */ #define _WTIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ #define _WTIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ #define _WTIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ #define _WTIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ #define _WTIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ #define _WTIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ #define _WTIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ #define WTIMER_CC_CTRL_CUFOA_DEFAULT (_WTIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ #define WTIMER_CC_CTRL_CUFOA_NONE (_WTIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for WTIMER_CC_CTRL */ #define WTIMER_CC_CTRL_CUFOA_TOGGLE (_WTIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ #define WTIMER_CC_CTRL_CUFOA_CLEAR (_WTIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ #define WTIMER_CC_CTRL_CUFOA_SET (_WTIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for WTIMER_CC_CTRL */ #define _WTIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */ #define _WTIMER_CC_CTRL_PRSSEL_MASK 0xF0000UL /**< Bit mask for TIMER_PRSSEL */ #define _WTIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ #define _WTIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_CC_CTRL */ #define _WTIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_CC_CTRL */ #define _WTIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_CC_CTRL */ #define _WTIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_CC_CTRL */ #define _WTIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_CC_CTRL */ #define _WTIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_CC_CTRL */ #define _WTIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_CC_CTRL */ #define _WTIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_CC_CTRL */ #define _WTIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_CC_CTRL */ #define _WTIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_CC_CTRL */ #define _WTIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_CC_CTRL */ #define _WTIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_CC_CTRL */ #define WTIMER_CC_CTRL_PRSSEL_DEFAULT (_WTIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ #define WTIMER_CC_CTRL_PRSSEL_PRSCH0 (_WTIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for WTIMER_CC_CTRL */ #define WTIMER_CC_CTRL_PRSSEL_PRSCH1 (_WTIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for WTIMER_CC_CTRL */ #define WTIMER_CC_CTRL_PRSSEL_PRSCH2 (_WTIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for WTIMER_CC_CTRL */ #define WTIMER_CC_CTRL_PRSSEL_PRSCH3 (_WTIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for WTIMER_CC_CTRL */ #define WTIMER_CC_CTRL_PRSSEL_PRSCH4 (_WTIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for WTIMER_CC_CTRL */ #define WTIMER_CC_CTRL_PRSSEL_PRSCH5 (_WTIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for WTIMER_CC_CTRL */ #define WTIMER_CC_CTRL_PRSSEL_PRSCH6 (_WTIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for WTIMER_CC_CTRL */ #define WTIMER_CC_CTRL_PRSSEL_PRSCH7 (_WTIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for WTIMER_CC_CTRL */ #define WTIMER_CC_CTRL_PRSSEL_PRSCH8 (_WTIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for WTIMER_CC_CTRL */ #define WTIMER_CC_CTRL_PRSSEL_PRSCH9 (_WTIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for WTIMER_CC_CTRL */ #define WTIMER_CC_CTRL_PRSSEL_PRSCH10 (_WTIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for WTIMER_CC_CTRL */ #define WTIMER_CC_CTRL_PRSSEL_PRSCH11 (_WTIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for WTIMER_CC_CTRL */ #define _WTIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ #define _WTIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ #define _WTIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ #define _WTIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for WTIMER_CC_CTRL */ #define _WTIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for WTIMER_CC_CTRL */ #define _WTIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for WTIMER_CC_CTRL */ #define _WTIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for WTIMER_CC_CTRL */ #define WTIMER_CC_CTRL_ICEDGE_DEFAULT (_WTIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ #define WTIMER_CC_CTRL_ICEDGE_RISING (_WTIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for WTIMER_CC_CTRL */ #define WTIMER_CC_CTRL_ICEDGE_FALLING (_WTIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ #define WTIMER_CC_CTRL_ICEDGE_BOTH (_WTIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for WTIMER_CC_CTRL */ #define WTIMER_CC_CTRL_ICEDGE_NONE (_WTIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for WTIMER_CC_CTRL */ #define _WTIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ #define _WTIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ #define _WTIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ #define _WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for WTIMER_CC_CTRL */ #define _WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ #define _WTIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for WTIMER_CC_CTRL */ #define _WTIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for WTIMER_CC_CTRL */ #define WTIMER_CC_CTRL_ICEVCTRL_DEFAULT (_WTIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ #define WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for WTIMER_CC_CTRL */ #define WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ #define WTIMER_CC_CTRL_ICEVCTRL_RISING (_WTIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for WTIMER_CC_CTRL */ #define WTIMER_CC_CTRL_ICEVCTRL_FALLING (_WTIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ #define WTIMER_CC_CTRL_PRSCONF (0x1UL << 28) /**< PRS Configuration */ #define _WTIMER_CC_CTRL_PRSCONF_SHIFT 28 /**< Shift value for TIMER_PRSCONF */ #define _WTIMER_CC_CTRL_PRSCONF_MASK 0x10000000UL /**< Bit mask for TIMER_PRSCONF */ #define _WTIMER_CC_CTRL_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ #define _WTIMER_CC_CTRL_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for WTIMER_CC_CTRL */ #define _WTIMER_CC_CTRL_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for WTIMER_CC_CTRL */ #define WTIMER_CC_CTRL_PRSCONF_DEFAULT (_WTIMER_CC_CTRL_PRSCONF_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ #define WTIMER_CC_CTRL_PRSCONF_PULSE (_WTIMER_CC_CTRL_PRSCONF_PULSE << 28) /**< Shifted mode PULSE for WTIMER_CC_CTRL */ #define WTIMER_CC_CTRL_PRSCONF_LEVEL (_WTIMER_CC_CTRL_PRSCONF_LEVEL << 28) /**< Shifted mode LEVEL for WTIMER_CC_CTRL */ #define WTIMER_CC_CTRL_INSEL (0x1UL << 29) /**< Input Selection */ #define _WTIMER_CC_CTRL_INSEL_SHIFT 29 /**< Shift value for TIMER_INSEL */ #define _WTIMER_CC_CTRL_INSEL_MASK 0x20000000UL /**< Bit mask for TIMER_INSEL */ #define _WTIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ #define _WTIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for WTIMER_CC_CTRL */ #define _WTIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for WTIMER_CC_CTRL */ #define WTIMER_CC_CTRL_INSEL_DEFAULT (_WTIMER_CC_CTRL_INSEL_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ #define WTIMER_CC_CTRL_INSEL_PIN (_WTIMER_CC_CTRL_INSEL_PIN << 29) /**< Shifted mode PIN for WTIMER_CC_CTRL */ #define WTIMER_CC_CTRL_INSEL_PRS (_WTIMER_CC_CTRL_INSEL_PRS << 29) /**< Shifted mode PRS for WTIMER_CC_CTRL */ #define WTIMER_CC_CTRL_FILT (0x1UL << 30) /**< Digital Filter */ #define _WTIMER_CC_CTRL_FILT_SHIFT 30 /**< Shift value for TIMER_FILT */ #define _WTIMER_CC_CTRL_FILT_MASK 0x40000000UL /**< Bit mask for TIMER_FILT */ #define _WTIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ #define _WTIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for WTIMER_CC_CTRL */ #define _WTIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for WTIMER_CC_CTRL */ #define WTIMER_CC_CTRL_FILT_DEFAULT (_WTIMER_CC_CTRL_FILT_DEFAULT << 30) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ #define WTIMER_CC_CTRL_FILT_DISABLE (_WTIMER_CC_CTRL_FILT_DISABLE << 30) /**< Shifted mode DISABLE for WTIMER_CC_CTRL */ #define WTIMER_CC_CTRL_FILT_ENABLE (_WTIMER_CC_CTRL_FILT_ENABLE << 30) /**< Shifted mode ENABLE for WTIMER_CC_CTRL */ /* Bit fields for WTIMER CC_CCV */ #define _WTIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCV */ #define _WTIMER_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCV */ #define _WTIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */ #define _WTIMER_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCV */ #define _WTIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCV */ #define WTIMER_CC_CCV_CCV_DEFAULT (_WTIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCV */ /* Bit fields for WTIMER CC_CCVP */ #define _WTIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVP */ #define _WTIMER_CC_CCVP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVP */ #define _WTIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */ #define _WTIMER_CC_CCVP_CCVP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVP */ #define _WTIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVP */ #define WTIMER_CC_CCVP_CCVP_DEFAULT (_WTIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVP */ /* Bit fields for WTIMER CC_CCVB */ #define _WTIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVB */ #define _WTIMER_CC_CCVB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVB */ #define _WTIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */ #define _WTIMER_CC_CCVB_CCVB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVB */ #define _WTIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVB */ #define WTIMER_CC_CCVB_CCVB_DEFAULT (_WTIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVB */ /* Bit fields for WTIMER DTCTRL */ #define _WTIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTCTRL */ #define _WTIMER_DTCTRL_MASK 0x010006FFUL /**< Mask for WTIMER_DTCTRL */ #define WTIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */ #define _WTIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ #define _WTIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ #define _WTIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ #define WTIMER_DTCTRL_DTEN_DEFAULT (_WTIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ #define WTIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ #define _WTIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ #define _WTIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ #define _WTIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ #define _WTIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for WTIMER_DTCTRL */ #define _WTIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for WTIMER_DTCTRL */ #define WTIMER_DTCTRL_DTDAS_DEFAULT (_WTIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ #define WTIMER_DTCTRL_DTDAS_NORESTART (_WTIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for WTIMER_DTCTRL */ #define WTIMER_DTCTRL_DTDAS_RESTART (_WTIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for WTIMER_DTCTRL */ #define WTIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */ #define _WTIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */ #define _WTIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */ #define _WTIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ #define WTIMER_DTCTRL_DTIPOL_DEFAULT (_WTIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ #define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert */ #define _WTIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */ #define _WTIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */ #define _WTIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ #define WTIMER_DTCTRL_DTCINV_DEFAULT (_WTIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ #define _WTIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */ #define _WTIMER_DTCTRL_DTPRSSEL_MASK 0xF0UL /**< Bit mask for TIMER_DTPRSSEL */ #define _WTIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTCTRL */ #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTCTRL */ #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTCTRL */ #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTCTRL */ #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTCTRL */ #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTCTRL */ #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTCTRL */ #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTCTRL */ #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTCTRL */ #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTCTRL */ #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTCTRL */ #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTCTRL */ #define WTIMER_DTCTRL_DTPRSSEL_DEFAULT (_WTIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ #define WTIMER_DTCTRL_DTPRSSEL_PRSCH0 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for WTIMER_DTCTRL */ #define WTIMER_DTCTRL_DTPRSSEL_PRSCH1 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for WTIMER_DTCTRL */ #define WTIMER_DTCTRL_DTPRSSEL_PRSCH2 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for WTIMER_DTCTRL */ #define WTIMER_DTCTRL_DTPRSSEL_PRSCH3 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for WTIMER_DTCTRL */ #define WTIMER_DTCTRL_DTPRSSEL_PRSCH4 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for WTIMER_DTCTRL */ #define WTIMER_DTCTRL_DTPRSSEL_PRSCH5 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for WTIMER_DTCTRL */ #define WTIMER_DTCTRL_DTPRSSEL_PRSCH6 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for WTIMER_DTCTRL */ #define WTIMER_DTCTRL_DTPRSSEL_PRSCH7 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for WTIMER_DTCTRL */ #define WTIMER_DTCTRL_DTPRSSEL_PRSCH8 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for WTIMER_DTCTRL */ #define WTIMER_DTCTRL_DTPRSSEL_PRSCH9 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for WTIMER_DTCTRL */ #define WTIMER_DTCTRL_DTPRSSEL_PRSCH10 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for WTIMER_DTCTRL */ #define WTIMER_DTCTRL_DTPRSSEL_PRSCH11 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for WTIMER_DTCTRL */ #define WTIMER_DTCTRL_DTAR (0x1UL << 9) /**< DTI Always Run */ #define _WTIMER_DTCTRL_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ #define _WTIMER_DTCTRL_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ #define _WTIMER_DTCTRL_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ #define WTIMER_DTCTRL_DTAR_DEFAULT (_WTIMER_DTCTRL_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ #define WTIMER_DTCTRL_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ #define _WTIMER_DTCTRL_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ #define _WTIMER_DTCTRL_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ #define _WTIMER_DTCTRL_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ #define WTIMER_DTCTRL_DTFATS_DEFAULT (_WTIMER_DTCTRL_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ #define WTIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */ #define _WTIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */ #define _WTIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */ #define _WTIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ #define WTIMER_DTCTRL_DTPRSEN_DEFAULT (_WTIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ /* Bit fields for WTIMER DTTIME */ #define _WTIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTTIME */ #define _WTIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for WTIMER_DTTIME */ #define _WTIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ #define _WTIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */ #define _WTIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ #define _WTIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_DTTIME */ #define _WTIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_DTTIME */ #define _WTIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_DTTIME */ #define _WTIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_DTTIME */ #define _WTIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_DTTIME */ #define _WTIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_DTTIME */ #define _WTIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_DTTIME */ #define _WTIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_DTTIME */ #define _WTIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_DTTIME */ #define _WTIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_DTTIME */ #define _WTIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_DTTIME */ #define WTIMER_DTTIME_DTPRESC_DEFAULT (_WTIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ #define WTIMER_DTTIME_DTPRESC_DIV1 (_WTIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for WTIMER_DTTIME */ #define WTIMER_DTTIME_DTPRESC_DIV2 (_WTIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for WTIMER_DTTIME */ #define WTIMER_DTTIME_DTPRESC_DIV4 (_WTIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for WTIMER_DTTIME */ #define WTIMER_DTTIME_DTPRESC_DIV8 (_WTIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for WTIMER_DTTIME */ #define WTIMER_DTTIME_DTPRESC_DIV16 (_WTIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for WTIMER_DTTIME */ #define WTIMER_DTTIME_DTPRESC_DIV32 (_WTIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for WTIMER_DTTIME */ #define WTIMER_DTTIME_DTPRESC_DIV64 (_WTIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for WTIMER_DTTIME */ #define WTIMER_DTTIME_DTPRESC_DIV128 (_WTIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for WTIMER_DTTIME */ #define WTIMER_DTTIME_DTPRESC_DIV256 (_WTIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for WTIMER_DTTIME */ #define WTIMER_DTTIME_DTPRESC_DIV512 (_WTIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for WTIMER_DTTIME */ #define WTIMER_DTTIME_DTPRESC_DIV1024 (_WTIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for WTIMER_DTTIME */ #define _WTIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */ #define _WTIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */ #define _WTIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ #define WTIMER_DTTIME_DTRISET_DEFAULT (_WTIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ #define _WTIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ #define _WTIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ #define _WTIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ #define WTIMER_DTTIME_DTFALLT_DEFAULT (_WTIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ /* Bit fields for WTIMER DTFC */ #define _WTIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFC */ #define _WTIMER_DTFC_MASK 0x0F030F0FUL /**< Mask for WTIMER_DTFC */ #define _WTIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */ #define _WTIMER_DTFC_DTPRS0FSEL_MASK 0xFUL /**< Bit mask for TIMER_DTPRS0FSEL */ #define _WTIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ #define WTIMER_DTFC_DTPRS0FSEL_DEFAULT (_WTIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFC */ #define WTIMER_DTFC_DTPRS0FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ #define WTIMER_DTFC_DTPRS0FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ #define WTIMER_DTFC_DTPRS0FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ #define WTIMER_DTFC_DTPRS0FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ #define WTIMER_DTFC_DTPRS0FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ #define WTIMER_DTFC_DTPRS0FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ #define WTIMER_DTFC_DTPRS0FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ #define WTIMER_DTFC_DTPRS0FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ #define WTIMER_DTFC_DTPRS0FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ #define WTIMER_DTFC_DTPRS0FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ #define WTIMER_DTFC_DTPRS0FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ #define WTIMER_DTFC_DTPRS0FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ #define _WTIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */ #define _WTIMER_DTFC_DTPRS1FSEL_MASK 0xF00UL /**< Bit mask for TIMER_DTPRS1FSEL */ #define _WTIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ #define WTIMER_DTFC_DTPRS1FSEL_DEFAULT (_WTIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTFC */ #define WTIMER_DTFC_DTPRS1FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ #define WTIMER_DTFC_DTPRS1FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ #define WTIMER_DTFC_DTPRS1FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ #define WTIMER_DTFC_DTPRS1FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ #define WTIMER_DTFC_DTPRS1FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ #define WTIMER_DTFC_DTPRS1FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ #define WTIMER_DTFC_DTPRS1FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ #define WTIMER_DTFC_DTPRS1FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ #define WTIMER_DTFC_DTPRS1FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ #define WTIMER_DTFC_DTPRS1FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ #define WTIMER_DTFC_DTPRS1FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ #define WTIMER_DTFC_DTPRS1FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ #define _WTIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ #define _WTIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ #define _WTIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ #define _WTIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for WTIMER_DTFC */ #define _WTIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for WTIMER_DTFC */ #define _WTIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_DTFC */ #define _WTIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for WTIMER_DTFC */ #define WTIMER_DTFC_DTFA_DEFAULT (_WTIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTFC */ #define WTIMER_DTFC_DTFA_NONE (_WTIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for WTIMER_DTFC */ #define WTIMER_DTFC_DTFA_INACTIVE (_WTIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for WTIMER_DTFC */ #define WTIMER_DTFC_DTFA_CLEAR (_WTIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for WTIMER_DTFC */ #define WTIMER_DTFC_DTFA_TRISTATE (_WTIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for WTIMER_DTFC */ #define WTIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ #define _WTIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ #define _WTIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ #define _WTIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ #define WTIMER_DTFC_DTPRS0FEN_DEFAULT (_WTIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTFC */ #define WTIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ #define _WTIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ #define _WTIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ #define _WTIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ #define WTIMER_DTFC_DTPRS1FEN_DEFAULT (_WTIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_DTFC */ #define WTIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ #define _WTIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ #define _WTIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ #define _WTIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ #define WTIMER_DTFC_DTDBGFEN_DEFAULT (_WTIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_DTFC */ #define WTIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ #define _WTIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ #define _WTIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ #define _WTIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ #define WTIMER_DTFC_DTLOCKUPFEN_DEFAULT (_WTIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_DTFC */ /* Bit fields for WTIMER DTOGEN */ #define _WTIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTOGEN */ #define _WTIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for WTIMER_DTOGEN */ #define WTIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */ #define _WTIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ #define _WTIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ #define _WTIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ #define WTIMER_DTOGEN_DTOGCC0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ #define WTIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */ #define _WTIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ #define _WTIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ #define _WTIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ #define WTIMER_DTOGEN_DTOGCC1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ #define WTIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */ #define _WTIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ #define _WTIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ #define _WTIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ #define WTIMER_DTOGEN_DTOGCC2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ #define WTIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */ #define _WTIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ #define _WTIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ #define _WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ #define WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ #define WTIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */ #define _WTIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ #define _WTIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ #define _WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ #define WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ #define WTIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */ #define _WTIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ #define _WTIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ #define _WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ #define WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ /* Bit fields for WTIMER DTFAULT */ #define _WTIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULT */ #define _WTIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULT */ #define WTIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ #define _WTIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ #define _WTIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ #define _WTIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ #define WTIMER_DTFAULT_DTPRS0F_DEFAULT (_WTIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ #define WTIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ #define _WTIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ #define _WTIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ #define _WTIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ #define WTIMER_DTFAULT_DTPRS1F_DEFAULT (_WTIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ #define WTIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ #define _WTIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ #define _WTIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ #define _WTIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ #define WTIMER_DTFAULT_DTDBGF_DEFAULT (_WTIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ #define WTIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ #define _WTIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ #define _WTIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ #define _WTIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ #define WTIMER_DTFAULT_DTLOCKUPF_DEFAULT (_WTIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ /* Bit fields for WTIMER DTFAULTC */ #define _WTIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULTC */ #define _WTIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULTC */ #define WTIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ #define _WTIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ #define _WTIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ #define _WTIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ #define WTIMER_DTFAULTC_DTPRS0FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ #define WTIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ #define _WTIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ #define _WTIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ #define _WTIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ #define WTIMER_DTFAULTC_DTPRS1FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ #define WTIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ #define _WTIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ #define _WTIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ #define _WTIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ #define WTIMER_DTFAULTC_DTDBGFC_DEFAULT (_WTIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ #define WTIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ #define _WTIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */ #define _WTIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */ #define _WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ #define WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ /* Bit fields for WTIMER DTLOCK */ #define _WTIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTLOCK */ #define _WTIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_DTLOCK */ #define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ #define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ #define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */ #define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */ #define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */ #define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */ #define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */ #define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */ #define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */ #define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */ #define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */ #define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */ /** @} */ /** @} End of group EFR32MG12P332F1024GL125_WTIMER */ /***************************************************************************//** * @defgroup EFR32MG12P332F1024GL125_UNLOCK Unlock Codes * @{ ******************************************************************************/ #define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */ #define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */ #define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */ #define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */ #define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */ #define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */ #define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */ /** @} End of group EFR32MG12P332F1024GL125_UNLOCK */ /** @} End of group EFR32MG12P332F1024GL125_BitFields */ #include "efr32mg12p_af_ports.h" #include "efr32mg12p_af_pins.h" /** @} End of group EFR32MG12P332F1024GL125 */ /** @} End of group Parts */ #ifdef __cplusplus } #endif #endif /* EFR32MG12P332F1024GL125_H */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_acmp.h.
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/***************************************************************************//** * @file * @brief EFR32MG12P_ACMP register and bit field definitions * @version 5.7.0 ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * SPDX-License-Identifier: Zlib * * The licensor of this software is Silicon Laboratories Inc. * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be * appreciated but is not required. * 2. Altered source versions must be plainly marked as such, and must not be * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * ******************************************************************************/ #if defined(__ICCARM__) #pragma system_include /* Treat file as system include file. */ #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang system_header /* Treat file as system include file. */ #endif /***************************************************************************//** * @addtogroup Parts * @{ ******************************************************************************/ /***************************************************************************//** * @defgroup EFR32MG12P_ACMP ACMP * @{ * @brief EFR32MG12P_ACMP Register Declaration ******************************************************************************/ /** ACMP Register Declaration */ typedef struct { __IOM uint32_t CTRL; /**< Control Register */ __IOM uint32_t INPUTSEL; /**< Input Selection Register */ __IM uint32_t STATUS; /**< Status Register */ __IM uint32_t IF; /**< Interrupt Flag Register */ __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ __IOM uint32_t IEN; /**< Interrupt Enable Register */ uint32_t RESERVED0[1U]; /**< Reserved for future use **/ __IM uint32_t APORTREQ; /**< APORT Request Status Register */ __IM uint32_t APORTCONFLICT; /**< APORT Conflict Status Register */ __IOM uint32_t HYSTERESIS0; /**< Hysteresis 0 Register */ __IOM uint32_t HYSTERESIS1; /**< Hysteresis 1 Register */ uint32_t RESERVED1[4U]; /**< Reserved for future use **/ __IOM uint32_t ROUTEPEN; /**< I/O Routing Pine Enable Register */ __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ __IOM uint32_t EXTIFCTRL; /**< External Override Interface Control */ } ACMP_TypeDef; /** @} */ /***************************************************************************//** * @addtogroup EFR32MG12P_ACMP * @{ * @defgroup EFR32MG12P_ACMP_BitFields ACMP Bit Fields * @{ ******************************************************************************/ /* Bit fields for ACMP CTRL */ #define _ACMP_CTRL_RESETVALUE 0x07000000UL /**< Default value for ACMP_CTRL */ #define _ACMP_CTRL_MASK 0xBF3CF70DUL /**< Mask for ACMP_CTRL */ #define ACMP_CTRL_EN (0x1UL << 0) /**< Analog Comparator Enable */ #define _ACMP_CTRL_EN_SHIFT 0 /**< Shift value for ACMP_EN */ #define _ACMP_CTRL_EN_MASK 0x1UL /**< Bit mask for ACMP_EN */ #define _ACMP_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ #define ACMP_CTRL_EN_DEFAULT (_ACMP_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_CTRL */ #define ACMP_CTRL_INACTVAL (0x1UL << 2) /**< Inactive Value */ #define _ACMP_CTRL_INACTVAL_SHIFT 2 /**< Shift value for ACMP_INACTVAL */ #define _ACMP_CTRL_INACTVAL_MASK 0x4UL /**< Bit mask for ACMP_INACTVAL */ #define _ACMP_CTRL_INACTVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ #define _ACMP_CTRL_INACTVAL_LOW 0x00000000UL /**< Mode LOW for ACMP_CTRL */ #define _ACMP_CTRL_INACTVAL_HIGH 0x00000001UL /**< Mode HIGH for ACMP_CTRL */ #define ACMP_CTRL_INACTVAL_DEFAULT (_ACMP_CTRL_INACTVAL_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_CTRL */ #define ACMP_CTRL_INACTVAL_LOW (_ACMP_CTRL_INACTVAL_LOW << 2) /**< Shifted mode LOW for ACMP_CTRL */ #define ACMP_CTRL_INACTVAL_HIGH (_ACMP_CTRL_INACTVAL_HIGH << 2) /**< Shifted mode HIGH for ACMP_CTRL */ #define ACMP_CTRL_GPIOINV (0x1UL << 3) /**< Comparator GPIO Output Invert */ #define _ACMP_CTRL_GPIOINV_SHIFT 3 /**< Shift value for ACMP_GPIOINV */ #define _ACMP_CTRL_GPIOINV_MASK 0x8UL /**< Bit mask for ACMP_GPIOINV */ #define _ACMP_CTRL_GPIOINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ #define _ACMP_CTRL_GPIOINV_NOTINV 0x00000000UL /**< Mode NOTINV for ACMP_CTRL */ #define _ACMP_CTRL_GPIOINV_INV 0x00000001UL /**< Mode INV for ACMP_CTRL */ #define ACMP_CTRL_GPIOINV_DEFAULT (_ACMP_CTRL_GPIOINV_DEFAULT << 3) /**< Shifted mode DEFAULT for ACMP_CTRL */ #define ACMP_CTRL_GPIOINV_NOTINV (_ACMP_CTRL_GPIOINV_NOTINV << 3) /**< Shifted mode NOTINV for ACMP_CTRL */ #define ACMP_CTRL_GPIOINV_INV (_ACMP_CTRL_GPIOINV_INV << 3) /**< Shifted mode INV for ACMP_CTRL */ #define ACMP_CTRL_APORTXMASTERDIS (0x1UL << 8) /**< APORT Bus X Master Disable */ #define _ACMP_CTRL_APORTXMASTERDIS_SHIFT 8 /**< Shift value for ACMP_APORTXMASTERDIS */ #define _ACMP_CTRL_APORTXMASTERDIS_MASK 0x100UL /**< Bit mask for ACMP_APORTXMASTERDIS */ #define _ACMP_CTRL_APORTXMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ #define ACMP_CTRL_APORTXMASTERDIS_DEFAULT (_ACMP_CTRL_APORTXMASTERDIS_DEFAULT << 8) /**< Shifted mode DEFAULT for ACMP_CTRL */ #define ACMP_CTRL_APORTYMASTERDIS (0x1UL << 9) /**< APORT Bus Y Master Disable */ #define _ACMP_CTRL_APORTYMASTERDIS_SHIFT 9 /**< Shift value for ACMP_APORTYMASTERDIS */ #define _ACMP_CTRL_APORTYMASTERDIS_MASK 0x200UL /**< Bit mask for ACMP_APORTYMASTERDIS */ #define _ACMP_CTRL_APORTYMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ #define ACMP_CTRL_APORTYMASTERDIS_DEFAULT (_ACMP_CTRL_APORTYMASTERDIS_DEFAULT << 9) /**< Shifted mode DEFAULT for ACMP_CTRL */ #define ACMP_CTRL_APORTVMASTERDIS (0x1UL << 10) /**< APORT Bus Master Disable for Bus Selected By VASEL */ #define _ACMP_CTRL_APORTVMASTERDIS_SHIFT 10 /**< Shift value for ACMP_APORTVMASTERDIS */ #define _ACMP_CTRL_APORTVMASTERDIS_MASK 0x400UL /**< Bit mask for ACMP_APORTVMASTERDIS */ #define _ACMP_CTRL_APORTVMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ #define ACMP_CTRL_APORTVMASTERDIS_DEFAULT (_ACMP_CTRL_APORTVMASTERDIS_DEFAULT << 10) /**< Shifted mode DEFAULT for ACMP_CTRL */ #define _ACMP_CTRL_PWRSEL_SHIFT 12 /**< Shift value for ACMP_PWRSEL */ #define _ACMP_CTRL_PWRSEL_MASK 0x7000UL /**< Bit mask for ACMP_PWRSEL */ #define _ACMP_CTRL_PWRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ #define _ACMP_CTRL_PWRSEL_AVDD 0x00000000UL /**< Mode AVDD for ACMP_CTRL */ #define _ACMP_CTRL_PWRSEL_DVDD 0x00000001UL /**< Mode DVDD for ACMP_CTRL */ #define _ACMP_CTRL_PWRSEL_IOVDD0 0x00000002UL /**< Mode IOVDD0 for ACMP_CTRL */ #define _ACMP_CTRL_PWRSEL_IOVDD1 0x00000004UL /**< Mode IOVDD1 for ACMP_CTRL */ #define ACMP_CTRL_PWRSEL_DEFAULT (_ACMP_CTRL_PWRSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for ACMP_CTRL */ #define ACMP_CTRL_PWRSEL_AVDD (_ACMP_CTRL_PWRSEL_AVDD << 12) /**< Shifted mode AVDD for ACMP_CTRL */ #define ACMP_CTRL_PWRSEL_DVDD (_ACMP_CTRL_PWRSEL_DVDD << 12) /**< Shifted mode DVDD for ACMP_CTRL */ #define ACMP_CTRL_PWRSEL_IOVDD0 (_ACMP_CTRL_PWRSEL_IOVDD0 << 12) /**< Shifted mode IOVDD0 for ACMP_CTRL */ #define ACMP_CTRL_PWRSEL_IOVDD1 (_ACMP_CTRL_PWRSEL_IOVDD1 << 12) /**< Shifted mode IOVDD1 for ACMP_CTRL */ #define ACMP_CTRL_ACCURACY (0x1UL << 15) /**< ACMP Accuracy Mode */ #define _ACMP_CTRL_ACCURACY_SHIFT 15 /**< Shift value for ACMP_ACCURACY */ #define _ACMP_CTRL_ACCURACY_MASK 0x8000UL /**< Bit mask for ACMP_ACCURACY */ #define _ACMP_CTRL_ACCURACY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ #define _ACMP_CTRL_ACCURACY_LOW 0x00000000UL /**< Mode LOW for ACMP_CTRL */ #define _ACMP_CTRL_ACCURACY_HIGH 0x00000001UL /**< Mode HIGH for ACMP_CTRL */ #define ACMP_CTRL_ACCURACY_DEFAULT (_ACMP_CTRL_ACCURACY_DEFAULT << 15) /**< Shifted mode DEFAULT for ACMP_CTRL */ #define ACMP_CTRL_ACCURACY_LOW (_ACMP_CTRL_ACCURACY_LOW << 15) /**< Shifted mode LOW for ACMP_CTRL */ #define ACMP_CTRL_ACCURACY_HIGH (_ACMP_CTRL_ACCURACY_HIGH << 15) /**< Shifted mode HIGH for ACMP_CTRL */ #define _ACMP_CTRL_INPUTRANGE_SHIFT 18 /**< Shift value for ACMP_INPUTRANGE */ #define _ACMP_CTRL_INPUTRANGE_MASK 0xC0000UL /**< Bit mask for ACMP_INPUTRANGE */ #define _ACMP_CTRL_INPUTRANGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ #define _ACMP_CTRL_INPUTRANGE_FULL 0x00000000UL /**< Mode FULL for ACMP_CTRL */ #define _ACMP_CTRL_INPUTRANGE_GTVDDDIV2 0x00000001UL /**< Mode GTVDDDIV2 for ACMP_CTRL */ #define _ACMP_CTRL_INPUTRANGE_LTVDDDIV2 0x00000002UL /**< Mode LTVDDDIV2 for ACMP_CTRL */ #define ACMP_CTRL_INPUTRANGE_DEFAULT (_ACMP_CTRL_INPUTRANGE_DEFAULT << 18) /**< Shifted mode DEFAULT for ACMP_CTRL */ #define ACMP_CTRL_INPUTRANGE_FULL (_ACMP_CTRL_INPUTRANGE_FULL << 18) /**< Shifted mode FULL for ACMP_CTRL */ #define ACMP_CTRL_INPUTRANGE_GTVDDDIV2 (_ACMP_CTRL_INPUTRANGE_GTVDDDIV2 << 18) /**< Shifted mode GTVDDDIV2 for ACMP_CTRL */ #define ACMP_CTRL_INPUTRANGE_LTVDDDIV2 (_ACMP_CTRL_INPUTRANGE_LTVDDDIV2 << 18) /**< Shifted mode LTVDDDIV2 for ACMP_CTRL */ #define ACMP_CTRL_IRISE (0x1UL << 20) /**< Rising Edge Interrupt Sense */ #define _ACMP_CTRL_IRISE_SHIFT 20 /**< Shift value for ACMP_IRISE */ #define _ACMP_CTRL_IRISE_MASK 0x100000UL /**< Bit mask for ACMP_IRISE */ #define _ACMP_CTRL_IRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ #define _ACMP_CTRL_IRISE_DISABLED 0x00000000UL /**< Mode DISABLED for ACMP_CTRL */ #define _ACMP_CTRL_IRISE_ENABLED 0x00000001UL /**< Mode ENABLED for ACMP_CTRL */ #define ACMP_CTRL_IRISE_DEFAULT (_ACMP_CTRL_IRISE_DEFAULT << 20) /**< Shifted mode DEFAULT for ACMP_CTRL */ #define ACMP_CTRL_IRISE_DISABLED (_ACMP_CTRL_IRISE_DISABLED << 20) /**< Shifted mode DISABLED for ACMP_CTRL */ #define ACMP_CTRL_IRISE_ENABLED (_ACMP_CTRL_IRISE_ENABLED << 20) /**< Shifted mode ENABLED for ACMP_CTRL */ #define ACMP_CTRL_IFALL (0x1UL << 21) /**< Falling Edge Interrupt Sense */ #define _ACMP_CTRL_IFALL_SHIFT 21 /**< Shift value for ACMP_IFALL */ #define _ACMP_CTRL_IFALL_MASK 0x200000UL /**< Bit mask for ACMP_IFALL */ #define _ACMP_CTRL_IFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ #define _ACMP_CTRL_IFALL_DISABLED 0x00000000UL /**< Mode DISABLED for ACMP_CTRL */ #define _ACMP_CTRL_IFALL_ENABLED 0x00000001UL /**< Mode ENABLED for ACMP_CTRL */ #define ACMP_CTRL_IFALL_DEFAULT (_ACMP_CTRL_IFALL_DEFAULT << 21) /**< Shifted mode DEFAULT for ACMP_CTRL */ #define ACMP_CTRL_IFALL_DISABLED (_ACMP_CTRL_IFALL_DISABLED << 21) /**< Shifted mode DISABLED for ACMP_CTRL */ #define ACMP_CTRL_IFALL_ENABLED (_ACMP_CTRL_IFALL_ENABLED << 21) /**< Shifted mode ENABLED for ACMP_CTRL */ #define _ACMP_CTRL_BIASPROG_SHIFT 24 /**< Shift value for ACMP_BIASPROG */ #define _ACMP_CTRL_BIASPROG_MASK 0x3F000000UL /**< Bit mask for ACMP_BIASPROG */ #define _ACMP_CTRL_BIASPROG_DEFAULT 0x00000007UL /**< Mode DEFAULT for ACMP_CTRL */ #define ACMP_CTRL_BIASPROG_DEFAULT (_ACMP_CTRL_BIASPROG_DEFAULT << 24) /**< Shifted mode DEFAULT for ACMP_CTRL */ #define ACMP_CTRL_FULLBIAS (0x1UL << 31) /**< Full Bias Current */ #define _ACMP_CTRL_FULLBIAS_SHIFT 31 /**< Shift value for ACMP_FULLBIAS */ #define _ACMP_CTRL_FULLBIAS_MASK 0x80000000UL /**< Bit mask for ACMP_FULLBIAS */ #define _ACMP_CTRL_FULLBIAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ #define ACMP_CTRL_FULLBIAS_DEFAULT (_ACMP_CTRL_FULLBIAS_DEFAULT << 31) /**< Shifted mode DEFAULT for ACMP_CTRL */ /* Bit fields for ACMP INPUTSEL */ #define _ACMP_INPUTSEL_RESETVALUE 0x00000000UL /**< Default value for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_MASK 0x757FFFFFUL /**< Mask for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_SHIFT 0 /**< Shift value for ACMP_POSSEL */ #define _ACMP_INPUTSEL_POSSEL_MASK 0xFFUL /**< Bit mask for ACMP_POSSEL */ #define _ACMP_INPUTSEL_POSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT0XCH0 0x00000000UL /**< Mode APORT0XCH0 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT0XCH1 0x00000001UL /**< Mode APORT0XCH1 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT0XCH2 0x00000002UL /**< Mode APORT0XCH2 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT0XCH3 0x00000003UL /**< Mode APORT0XCH3 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT0XCH4 0x00000004UL /**< Mode APORT0XCH4 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT0XCH5 0x00000005UL /**< Mode APORT0XCH5 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT0XCH6 0x00000006UL /**< Mode APORT0XCH6 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT0XCH7 0x00000007UL /**< Mode APORT0XCH7 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT0XCH8 0x00000008UL /**< Mode APORT0XCH8 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT0XCH9 0x00000009UL /**< Mode APORT0XCH9 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT0XCH10 0x0000000AUL /**< Mode APORT0XCH10 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT0XCH11 0x0000000BUL /**< Mode APORT0XCH11 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT0XCH12 0x0000000CUL /**< Mode APORT0XCH12 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT0XCH13 0x0000000DUL /**< Mode APORT0XCH13 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT0XCH14 0x0000000EUL /**< Mode APORT0XCH14 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT0XCH15 0x0000000FUL /**< Mode APORT0XCH15 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT0YCH0 0x00000010UL /**< Mode APORT0YCH0 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT0YCH1 0x00000011UL /**< Mode APORT0YCH1 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT0YCH2 0x00000012UL /**< Mode APORT0YCH2 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT0YCH3 0x00000013UL /**< Mode APORT0YCH3 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT0YCH4 0x00000014UL /**< Mode APORT0YCH4 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT0YCH5 0x00000015UL /**< Mode APORT0YCH5 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT0YCH6 0x00000016UL /**< Mode APORT0YCH6 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT0YCH7 0x00000017UL /**< Mode APORT0YCH7 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT0YCH8 0x00000018UL /**< Mode APORT0YCH8 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT0YCH9 0x00000019UL /**< Mode APORT0YCH9 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT0YCH10 0x0000001AUL /**< Mode APORT0YCH10 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT0YCH11 0x0000001BUL /**< Mode APORT0YCH11 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT0YCH12 0x0000001CUL /**< Mode APORT0YCH12 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT0YCH13 0x0000001DUL /**< Mode APORT0YCH13 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT0YCH14 0x0000001EUL /**< Mode APORT0YCH14 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT0YCH15 0x0000001FUL /**< Mode APORT0YCH15 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT1XCH0 0x00000020UL /**< Mode APORT1XCH0 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT1YCH1 0x00000021UL /**< Mode APORT1YCH1 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT1XCH2 0x00000022UL /**< Mode APORT1XCH2 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT1YCH3 0x00000023UL /**< Mode APORT1YCH3 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT1XCH4 0x00000024UL /**< Mode APORT1XCH4 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT1YCH5 0x00000025UL /**< Mode APORT1YCH5 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT1XCH6 0x00000026UL /**< Mode APORT1XCH6 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT1YCH7 0x00000027UL /**< Mode APORT1YCH7 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT1XCH8 0x00000028UL /**< Mode APORT1XCH8 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT1YCH9 0x00000029UL /**< Mode APORT1YCH9 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT1XCH10 0x0000002AUL /**< Mode APORT1XCH10 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT1YCH11 0x0000002BUL /**< Mode APORT1YCH11 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT1XCH12 0x0000002CUL /**< Mode APORT1XCH12 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT1YCH13 0x0000002DUL /**< Mode APORT1YCH13 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT1XCH14 0x0000002EUL /**< Mode APORT1XCH14 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT1YCH15 0x0000002FUL /**< Mode APORT1YCH15 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT1XCH16 0x00000030UL /**< Mode APORT1XCH16 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT1YCH17 0x00000031UL /**< Mode APORT1YCH17 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT1XCH18 0x00000032UL /**< Mode APORT1XCH18 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT1YCH19 0x00000033UL /**< Mode APORT1YCH19 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT1XCH20 0x00000034UL /**< Mode APORT1XCH20 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT1YCH21 0x00000035UL /**< Mode APORT1YCH21 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT1XCH22 0x00000036UL /**< Mode APORT1XCH22 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT1YCH23 0x00000037UL /**< Mode APORT1YCH23 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT1XCH24 0x00000038UL /**< Mode APORT1XCH24 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT1YCH25 0x00000039UL /**< Mode APORT1YCH25 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT1XCH26 0x0000003AUL /**< Mode APORT1XCH26 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT1YCH27 0x0000003BUL /**< Mode APORT1YCH27 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT1XCH28 0x0000003CUL /**< Mode APORT1XCH28 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT1YCH29 0x0000003DUL /**< Mode APORT1YCH29 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT1XCH30 0x0000003EUL /**< Mode APORT1XCH30 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT1YCH31 0x0000003FUL /**< Mode APORT1YCH31 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT2YCH0 0x00000040UL /**< Mode APORT2YCH0 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT2XCH1 0x00000041UL /**< Mode APORT2XCH1 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT2YCH2 0x00000042UL /**< Mode APORT2YCH2 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT2XCH3 0x00000043UL /**< Mode APORT2XCH3 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT2YCH4 0x00000044UL /**< Mode APORT2YCH4 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT2XCH5 0x00000045UL /**< Mode APORT2XCH5 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT2YCH6 0x00000046UL /**< Mode APORT2YCH6 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT2XCH7 0x00000047UL /**< Mode APORT2XCH7 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT2YCH8 0x00000048UL /**< Mode APORT2YCH8 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT2XCH9 0x00000049UL /**< Mode APORT2XCH9 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT2YCH10 0x0000004AUL /**< Mode APORT2YCH10 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT2XCH11 0x0000004BUL /**< Mode APORT2XCH11 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT2YCH12 0x0000004CUL /**< Mode APORT2YCH12 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT2XCH13 0x0000004DUL /**< Mode APORT2XCH13 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT2YCH14 0x0000004EUL /**< Mode APORT2YCH14 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT2XCH15 0x0000004FUL /**< Mode APORT2XCH15 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT2YCH16 0x00000050UL /**< Mode APORT2YCH16 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT2XCH17 0x00000051UL /**< Mode APORT2XCH17 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT2YCH18 0x00000052UL /**< Mode APORT2YCH18 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT2XCH19 0x00000053UL /**< Mode APORT2XCH19 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT2YCH20 0x00000054UL /**< Mode APORT2YCH20 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT2XCH21 0x00000055UL /**< Mode APORT2XCH21 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT2YCH22 0x00000056UL /**< Mode APORT2YCH22 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT2XCH23 0x00000057UL /**< Mode APORT2XCH23 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT2YCH24 0x00000058UL /**< Mode APORT2YCH24 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT2XCH25 0x00000059UL /**< Mode APORT2XCH25 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT2YCH26 0x0000005AUL /**< Mode APORT2YCH26 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT2XCH27 0x0000005BUL /**< Mode APORT2XCH27 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT2YCH28 0x0000005CUL /**< Mode APORT2YCH28 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT2XCH29 0x0000005DUL /**< Mode APORT2XCH29 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT2YCH30 0x0000005EUL /**< Mode APORT2YCH30 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT2XCH31 0x0000005FUL /**< Mode APORT2XCH31 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT3XCH0 0x00000060UL /**< Mode APORT3XCH0 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT3YCH1 0x00000061UL /**< Mode APORT3YCH1 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT3XCH2 0x00000062UL /**< Mode APORT3XCH2 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT3YCH3 0x00000063UL /**< Mode APORT3YCH3 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT3XCH4 0x00000064UL /**< Mode APORT3XCH4 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT3YCH5 0x00000065UL /**< Mode APORT3YCH5 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT3XCH6 0x00000066UL /**< Mode APORT3XCH6 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT3YCH7 0x00000067UL /**< Mode APORT3YCH7 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT3XCH8 0x00000068UL /**< Mode APORT3XCH8 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT3YCH9 0x00000069UL /**< Mode APORT3YCH9 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT3XCH10 0x0000006AUL /**< Mode APORT3XCH10 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT3YCH11 0x0000006BUL /**< Mode APORT3YCH11 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT3XCH12 0x0000006CUL /**< Mode APORT3XCH12 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT3YCH13 0x0000006DUL /**< Mode APORT3YCH13 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT3XCH14 0x0000006EUL /**< Mode APORT3XCH14 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT3YCH15 0x0000006FUL /**< Mode APORT3YCH15 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT3XCH16 0x00000070UL /**< Mode APORT3XCH16 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT3YCH17 0x00000071UL /**< Mode APORT3YCH17 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT3XCH18 0x00000072UL /**< Mode APORT3XCH18 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT3YCH19 0x00000073UL /**< Mode APORT3YCH19 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT3XCH20 0x00000074UL /**< Mode APORT3XCH20 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT3YCH21 0x00000075UL /**< Mode APORT3YCH21 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT3XCH22 0x00000076UL /**< Mode APORT3XCH22 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT3YCH23 0x00000077UL /**< Mode APORT3YCH23 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT3XCH24 0x00000078UL /**< Mode APORT3XCH24 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT3YCH25 0x00000079UL /**< Mode APORT3YCH25 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT3XCH26 0x0000007AUL /**< Mode APORT3XCH26 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT3YCH27 0x0000007BUL /**< Mode APORT3YCH27 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT3XCH28 0x0000007CUL /**< Mode APORT3XCH28 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT3YCH29 0x0000007DUL /**< Mode APORT3YCH29 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT3XCH30 0x0000007EUL /**< Mode APORT3XCH30 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT3YCH31 0x0000007FUL /**< Mode APORT3YCH31 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT4YCH0 0x00000080UL /**< Mode APORT4YCH0 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT4XCH1 0x00000081UL /**< Mode APORT4XCH1 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT4YCH2 0x00000082UL /**< Mode APORT4YCH2 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT4XCH3 0x00000083UL /**< Mode APORT4XCH3 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT4YCH4 0x00000084UL /**< Mode APORT4YCH4 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT4XCH5 0x00000085UL /**< Mode APORT4XCH5 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT4YCH6 0x00000086UL /**< Mode APORT4YCH6 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT4XCH7 0x00000087UL /**< Mode APORT4XCH7 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT4YCH8 0x00000088UL /**< Mode APORT4YCH8 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT4XCH9 0x00000089UL /**< Mode APORT4XCH9 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT4YCH10 0x0000008AUL /**< Mode APORT4YCH10 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT4XCH11 0x0000008BUL /**< Mode APORT4XCH11 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT4YCH12 0x0000008CUL /**< Mode APORT4YCH12 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT4XCH13 0x0000008DUL /**< Mode APORT4XCH13 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT4YCH16 0x00000090UL /**< Mode APORT4YCH16 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT4XCH17 0x00000091UL /**< Mode APORT4XCH17 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT4YCH18 0x00000092UL /**< Mode APORT4YCH18 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT4XCH19 0x00000093UL /**< Mode APORT4XCH19 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT4YCH20 0x00000094UL /**< Mode APORT4YCH20 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT4XCH21 0x00000095UL /**< Mode APORT4XCH21 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT4YCH22 0x00000096UL /**< Mode APORT4YCH22 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT4XCH23 0x00000097UL /**< Mode APORT4XCH23 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT4YCH24 0x00000098UL /**< Mode APORT4YCH24 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT4XCH25 0x00000099UL /**< Mode APORT4XCH25 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT4YCH26 0x0000009AUL /**< Mode APORT4YCH26 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT4XCH27 0x0000009BUL /**< Mode APORT4XCH27 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT4YCH28 0x0000009CUL /**< Mode APORT4YCH28 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT4XCH29 0x0000009DUL /**< Mode APORT4XCH29 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT4YCH30 0x0000009EUL /**< Mode APORT4YCH30 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT4YCH14 0x0000009EUL /**< Mode APORT4YCH14 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT4XCH15 0x0000009FUL /**< Mode APORT4XCH15 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT4XCH31 0x0000009FUL /**< Mode APORT4XCH31 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_DACOUT0 0x000000F2UL /**< Mode DACOUT0 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_DACOUT1 0x000000F3UL /**< Mode DACOUT1 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_VLP 0x000000FBUL /**< Mode VLP for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_VBDIV 0x000000FCUL /**< Mode VBDIV for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_VADIV 0x000000FDUL /**< Mode VADIV for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_VDD 0x000000FEUL /**< Mode VDD for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_VSS 0x000000FFUL /**< Mode VSS for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_DEFAULT (_ACMP_INPUTSEL_POSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT0XCH0 (_ACMP_INPUTSEL_POSSEL_APORT0XCH0 << 0) /**< Shifted mode APORT0XCH0 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT0XCH1 (_ACMP_INPUTSEL_POSSEL_APORT0XCH1 << 0) /**< Shifted mode APORT0XCH1 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT0XCH2 (_ACMP_INPUTSEL_POSSEL_APORT0XCH2 << 0) /**< Shifted mode APORT0XCH2 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT0XCH3 (_ACMP_INPUTSEL_POSSEL_APORT0XCH3 << 0) /**< Shifted mode APORT0XCH3 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT0XCH4 (_ACMP_INPUTSEL_POSSEL_APORT0XCH4 << 0) /**< Shifted mode APORT0XCH4 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT0XCH5 (_ACMP_INPUTSEL_POSSEL_APORT0XCH5 << 0) /**< Shifted mode APORT0XCH5 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT0XCH6 (_ACMP_INPUTSEL_POSSEL_APORT0XCH6 << 0) /**< Shifted mode APORT0XCH6 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT0XCH7 (_ACMP_INPUTSEL_POSSEL_APORT0XCH7 << 0) /**< Shifted mode APORT0XCH7 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT0XCH8 (_ACMP_INPUTSEL_POSSEL_APORT0XCH8 << 0) /**< Shifted mode APORT0XCH8 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT0XCH9 (_ACMP_INPUTSEL_POSSEL_APORT0XCH9 << 0) /**< Shifted mode APORT0XCH9 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT0XCH10 (_ACMP_INPUTSEL_POSSEL_APORT0XCH10 << 0) /**< Shifted mode APORT0XCH10 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT0XCH11 (_ACMP_INPUTSEL_POSSEL_APORT0XCH11 << 0) /**< Shifted mode APORT0XCH11 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT0XCH12 (_ACMP_INPUTSEL_POSSEL_APORT0XCH12 << 0) /**< Shifted mode APORT0XCH12 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT0XCH13 (_ACMP_INPUTSEL_POSSEL_APORT0XCH13 << 0) /**< Shifted mode APORT0XCH13 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT0XCH14 (_ACMP_INPUTSEL_POSSEL_APORT0XCH14 << 0) /**< Shifted mode APORT0XCH14 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT0XCH15 (_ACMP_INPUTSEL_POSSEL_APORT0XCH15 << 0) /**< Shifted mode APORT0XCH15 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT0YCH0 (_ACMP_INPUTSEL_POSSEL_APORT0YCH0 << 0) /**< Shifted mode APORT0YCH0 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT0YCH1 (_ACMP_INPUTSEL_POSSEL_APORT0YCH1 << 0) /**< Shifted mode APORT0YCH1 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT0YCH2 (_ACMP_INPUTSEL_POSSEL_APORT0YCH2 << 0) /**< Shifted mode APORT0YCH2 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT0YCH3 (_ACMP_INPUTSEL_POSSEL_APORT0YCH3 << 0) /**< Shifted mode APORT0YCH3 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT0YCH4 (_ACMP_INPUTSEL_POSSEL_APORT0YCH4 << 0) /**< Shifted mode APORT0YCH4 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT0YCH5 (_ACMP_INPUTSEL_POSSEL_APORT0YCH5 << 0) /**< Shifted mode APORT0YCH5 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT0YCH6 (_ACMP_INPUTSEL_POSSEL_APORT0YCH6 << 0) /**< Shifted mode APORT0YCH6 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT0YCH7 (_ACMP_INPUTSEL_POSSEL_APORT0YCH7 << 0) /**< Shifted mode APORT0YCH7 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT0YCH8 (_ACMP_INPUTSEL_POSSEL_APORT0YCH8 << 0) /**< Shifted mode APORT0YCH8 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT0YCH9 (_ACMP_INPUTSEL_POSSEL_APORT0YCH9 << 0) /**< Shifted mode APORT0YCH9 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT0YCH10 (_ACMP_INPUTSEL_POSSEL_APORT0YCH10 << 0) /**< Shifted mode APORT0YCH10 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT0YCH11 (_ACMP_INPUTSEL_POSSEL_APORT0YCH11 << 0) /**< Shifted mode APORT0YCH11 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT0YCH12 (_ACMP_INPUTSEL_POSSEL_APORT0YCH12 << 0) /**< Shifted mode APORT0YCH12 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT0YCH13 (_ACMP_INPUTSEL_POSSEL_APORT0YCH13 << 0) /**< Shifted mode APORT0YCH13 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT0YCH14 (_ACMP_INPUTSEL_POSSEL_APORT0YCH14 << 0) /**< Shifted mode APORT0YCH14 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT0YCH15 (_ACMP_INPUTSEL_POSSEL_APORT0YCH15 << 0) /**< Shifted mode APORT0YCH15 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT1XCH0 (_ACMP_INPUTSEL_POSSEL_APORT1XCH0 << 0) /**< Shifted mode APORT1XCH0 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT1YCH1 (_ACMP_INPUTSEL_POSSEL_APORT1YCH1 << 0) /**< Shifted mode APORT1YCH1 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT1XCH2 (_ACMP_INPUTSEL_POSSEL_APORT1XCH2 << 0) /**< Shifted mode APORT1XCH2 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT1YCH3 (_ACMP_INPUTSEL_POSSEL_APORT1YCH3 << 0) /**< Shifted mode APORT1YCH3 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT1XCH4 (_ACMP_INPUTSEL_POSSEL_APORT1XCH4 << 0) /**< Shifted mode APORT1XCH4 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT1YCH5 (_ACMP_INPUTSEL_POSSEL_APORT1YCH5 << 0) /**< Shifted mode APORT1YCH5 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT1XCH6 (_ACMP_INPUTSEL_POSSEL_APORT1XCH6 << 0) /**< Shifted mode APORT1XCH6 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT1YCH7 (_ACMP_INPUTSEL_POSSEL_APORT1YCH7 << 0) /**< Shifted mode APORT1YCH7 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT1XCH8 (_ACMP_INPUTSEL_POSSEL_APORT1XCH8 << 0) /**< Shifted mode APORT1XCH8 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT1YCH9 (_ACMP_INPUTSEL_POSSEL_APORT1YCH9 << 0) /**< Shifted mode APORT1YCH9 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT1XCH10 (_ACMP_INPUTSEL_POSSEL_APORT1XCH10 << 0) /**< Shifted mode APORT1XCH10 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT1YCH11 (_ACMP_INPUTSEL_POSSEL_APORT1YCH11 << 0) /**< Shifted mode APORT1YCH11 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT1XCH12 (_ACMP_INPUTSEL_POSSEL_APORT1XCH12 << 0) /**< Shifted mode APORT1XCH12 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT1YCH13 (_ACMP_INPUTSEL_POSSEL_APORT1YCH13 << 0) /**< Shifted mode APORT1YCH13 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT1XCH14 (_ACMP_INPUTSEL_POSSEL_APORT1XCH14 << 0) /**< Shifted mode APORT1XCH14 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT1YCH15 (_ACMP_INPUTSEL_POSSEL_APORT1YCH15 << 0) /**< Shifted mode APORT1YCH15 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT1XCH16 (_ACMP_INPUTSEL_POSSEL_APORT1XCH16 << 0) /**< Shifted mode APORT1XCH16 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT1YCH17 (_ACMP_INPUTSEL_POSSEL_APORT1YCH17 << 0) /**< Shifted mode APORT1YCH17 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT1XCH18 (_ACMP_INPUTSEL_POSSEL_APORT1XCH18 << 0) /**< Shifted mode APORT1XCH18 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT1YCH19 (_ACMP_INPUTSEL_POSSEL_APORT1YCH19 << 0) /**< Shifted mode APORT1YCH19 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT1XCH20 (_ACMP_INPUTSEL_POSSEL_APORT1XCH20 << 0) /**< Shifted mode APORT1XCH20 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT1YCH21 (_ACMP_INPUTSEL_POSSEL_APORT1YCH21 << 0) /**< Shifted mode APORT1YCH21 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT1XCH22 (_ACMP_INPUTSEL_POSSEL_APORT1XCH22 << 0) /**< Shifted mode APORT1XCH22 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT1YCH23 (_ACMP_INPUTSEL_POSSEL_APORT1YCH23 << 0) /**< Shifted mode APORT1YCH23 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT1XCH24 (_ACMP_INPUTSEL_POSSEL_APORT1XCH24 << 0) /**< Shifted mode APORT1XCH24 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT1YCH25 (_ACMP_INPUTSEL_POSSEL_APORT1YCH25 << 0) /**< Shifted mode APORT1YCH25 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT1XCH26 (_ACMP_INPUTSEL_POSSEL_APORT1XCH26 << 0) /**< Shifted mode APORT1XCH26 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT1YCH27 (_ACMP_INPUTSEL_POSSEL_APORT1YCH27 << 0) /**< Shifted mode APORT1YCH27 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT1XCH28 (_ACMP_INPUTSEL_POSSEL_APORT1XCH28 << 0) /**< Shifted mode APORT1XCH28 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT1YCH29 (_ACMP_INPUTSEL_POSSEL_APORT1YCH29 << 0) /**< Shifted mode APORT1YCH29 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT1XCH30 (_ACMP_INPUTSEL_POSSEL_APORT1XCH30 << 0) /**< Shifted mode APORT1XCH30 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT1YCH31 (_ACMP_INPUTSEL_POSSEL_APORT1YCH31 << 0) /**< Shifted mode APORT1YCH31 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT2YCH0 (_ACMP_INPUTSEL_POSSEL_APORT2YCH0 << 0) /**< Shifted mode APORT2YCH0 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT2XCH1 (_ACMP_INPUTSEL_POSSEL_APORT2XCH1 << 0) /**< Shifted mode APORT2XCH1 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT2YCH2 (_ACMP_INPUTSEL_POSSEL_APORT2YCH2 << 0) /**< Shifted mode APORT2YCH2 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT2XCH3 (_ACMP_INPUTSEL_POSSEL_APORT2XCH3 << 0) /**< Shifted mode APORT2XCH3 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT2YCH4 (_ACMP_INPUTSEL_POSSEL_APORT2YCH4 << 0) /**< Shifted mode APORT2YCH4 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT2XCH5 (_ACMP_INPUTSEL_POSSEL_APORT2XCH5 << 0) /**< Shifted mode APORT2XCH5 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT2YCH6 (_ACMP_INPUTSEL_POSSEL_APORT2YCH6 << 0) /**< Shifted mode APORT2YCH6 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT2XCH7 (_ACMP_INPUTSEL_POSSEL_APORT2XCH7 << 0) /**< Shifted mode APORT2XCH7 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT2YCH8 (_ACMP_INPUTSEL_POSSEL_APORT2YCH8 << 0) /**< Shifted mode APORT2YCH8 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT2XCH9 (_ACMP_INPUTSEL_POSSEL_APORT2XCH9 << 0) /**< Shifted mode APORT2XCH9 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT2YCH10 (_ACMP_INPUTSEL_POSSEL_APORT2YCH10 << 0) /**< Shifted mode APORT2YCH10 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT2XCH11 (_ACMP_INPUTSEL_POSSEL_APORT2XCH11 << 0) /**< Shifted mode APORT2XCH11 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT2YCH12 (_ACMP_INPUTSEL_POSSEL_APORT2YCH12 << 0) /**< Shifted mode APORT2YCH12 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT2XCH13 (_ACMP_INPUTSEL_POSSEL_APORT2XCH13 << 0) /**< Shifted mode APORT2XCH13 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT2YCH14 (_ACMP_INPUTSEL_POSSEL_APORT2YCH14 << 0) /**< Shifted mode APORT2YCH14 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT2XCH15 (_ACMP_INPUTSEL_POSSEL_APORT2XCH15 << 0) /**< Shifted mode APORT2XCH15 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT2YCH16 (_ACMP_INPUTSEL_POSSEL_APORT2YCH16 << 0) /**< Shifted mode APORT2YCH16 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT2XCH17 (_ACMP_INPUTSEL_POSSEL_APORT2XCH17 << 0) /**< Shifted mode APORT2XCH17 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT2YCH18 (_ACMP_INPUTSEL_POSSEL_APORT2YCH18 << 0) /**< Shifted mode APORT2YCH18 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT2XCH19 (_ACMP_INPUTSEL_POSSEL_APORT2XCH19 << 0) /**< Shifted mode APORT2XCH19 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT2YCH20 (_ACMP_INPUTSEL_POSSEL_APORT2YCH20 << 0) /**< Shifted mode APORT2YCH20 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT2XCH21 (_ACMP_INPUTSEL_POSSEL_APORT2XCH21 << 0) /**< Shifted mode APORT2XCH21 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT2YCH22 (_ACMP_INPUTSEL_POSSEL_APORT2YCH22 << 0) /**< Shifted mode APORT2YCH22 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT2XCH23 (_ACMP_INPUTSEL_POSSEL_APORT2XCH23 << 0) /**< Shifted mode APORT2XCH23 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT2YCH24 (_ACMP_INPUTSEL_POSSEL_APORT2YCH24 << 0) /**< Shifted mode APORT2YCH24 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT2XCH25 (_ACMP_INPUTSEL_POSSEL_APORT2XCH25 << 0) /**< Shifted mode APORT2XCH25 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT2YCH26 (_ACMP_INPUTSEL_POSSEL_APORT2YCH26 << 0) /**< Shifted mode APORT2YCH26 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT2XCH27 (_ACMP_INPUTSEL_POSSEL_APORT2XCH27 << 0) /**< Shifted mode APORT2XCH27 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT2YCH28 (_ACMP_INPUTSEL_POSSEL_APORT2YCH28 << 0) /**< Shifted mode APORT2YCH28 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT2XCH29 (_ACMP_INPUTSEL_POSSEL_APORT2XCH29 << 0) /**< Shifted mode APORT2XCH29 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT2YCH30 (_ACMP_INPUTSEL_POSSEL_APORT2YCH30 << 0) /**< Shifted mode APORT2YCH30 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT2XCH31 (_ACMP_INPUTSEL_POSSEL_APORT2XCH31 << 0) /**< Shifted mode APORT2XCH31 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT3XCH0 (_ACMP_INPUTSEL_POSSEL_APORT3XCH0 << 0) /**< Shifted mode APORT3XCH0 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT3YCH1 (_ACMP_INPUTSEL_POSSEL_APORT3YCH1 << 0) /**< Shifted mode APORT3YCH1 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT3XCH2 (_ACMP_INPUTSEL_POSSEL_APORT3XCH2 << 0) /**< Shifted mode APORT3XCH2 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT3YCH3 (_ACMP_INPUTSEL_POSSEL_APORT3YCH3 << 0) /**< Shifted mode APORT3YCH3 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT3XCH4 (_ACMP_INPUTSEL_POSSEL_APORT3XCH4 << 0) /**< Shifted mode APORT3XCH4 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT3YCH5 (_ACMP_INPUTSEL_POSSEL_APORT3YCH5 << 0) /**< Shifted mode APORT3YCH5 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT3XCH6 (_ACMP_INPUTSEL_POSSEL_APORT3XCH6 << 0) /**< Shifted mode APORT3XCH6 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT3YCH7 (_ACMP_INPUTSEL_POSSEL_APORT3YCH7 << 0) /**< Shifted mode APORT3YCH7 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT3XCH8 (_ACMP_INPUTSEL_POSSEL_APORT3XCH8 << 0) /**< Shifted mode APORT3XCH8 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT3YCH9 (_ACMP_INPUTSEL_POSSEL_APORT3YCH9 << 0) /**< Shifted mode APORT3YCH9 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT3XCH10 (_ACMP_INPUTSEL_POSSEL_APORT3XCH10 << 0) /**< Shifted mode APORT3XCH10 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT3YCH11 (_ACMP_INPUTSEL_POSSEL_APORT3YCH11 << 0) /**< Shifted mode APORT3YCH11 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT3XCH12 (_ACMP_INPUTSEL_POSSEL_APORT3XCH12 << 0) /**< Shifted mode APORT3XCH12 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT3YCH13 (_ACMP_INPUTSEL_POSSEL_APORT3YCH13 << 0) /**< Shifted mode APORT3YCH13 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT3XCH14 (_ACMP_INPUTSEL_POSSEL_APORT3XCH14 << 0) /**< Shifted mode APORT3XCH14 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT3YCH15 (_ACMP_INPUTSEL_POSSEL_APORT3YCH15 << 0) /**< Shifted mode APORT3YCH15 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT3XCH16 (_ACMP_INPUTSEL_POSSEL_APORT3XCH16 << 0) /**< Shifted mode APORT3XCH16 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT3YCH17 (_ACMP_INPUTSEL_POSSEL_APORT3YCH17 << 0) /**< Shifted mode APORT3YCH17 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT3XCH18 (_ACMP_INPUTSEL_POSSEL_APORT3XCH18 << 0) /**< Shifted mode APORT3XCH18 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT3YCH19 (_ACMP_INPUTSEL_POSSEL_APORT3YCH19 << 0) /**< Shifted mode APORT3YCH19 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT3XCH20 (_ACMP_INPUTSEL_POSSEL_APORT3XCH20 << 0) /**< Shifted mode APORT3XCH20 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT3YCH21 (_ACMP_INPUTSEL_POSSEL_APORT3YCH21 << 0) /**< Shifted mode APORT3YCH21 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT3XCH22 (_ACMP_INPUTSEL_POSSEL_APORT3XCH22 << 0) /**< Shifted mode APORT3XCH22 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT3YCH23 (_ACMP_INPUTSEL_POSSEL_APORT3YCH23 << 0) /**< Shifted mode APORT3YCH23 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT3XCH24 (_ACMP_INPUTSEL_POSSEL_APORT3XCH24 << 0) /**< Shifted mode APORT3XCH24 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT3YCH25 (_ACMP_INPUTSEL_POSSEL_APORT3YCH25 << 0) /**< Shifted mode APORT3YCH25 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT3XCH26 (_ACMP_INPUTSEL_POSSEL_APORT3XCH26 << 0) /**< Shifted mode APORT3XCH26 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT3YCH27 (_ACMP_INPUTSEL_POSSEL_APORT3YCH27 << 0) /**< Shifted mode APORT3YCH27 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT3XCH28 (_ACMP_INPUTSEL_POSSEL_APORT3XCH28 << 0) /**< Shifted mode APORT3XCH28 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT3YCH29 (_ACMP_INPUTSEL_POSSEL_APORT3YCH29 << 0) /**< Shifted mode APORT3YCH29 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT3XCH30 (_ACMP_INPUTSEL_POSSEL_APORT3XCH30 << 0) /**< Shifted mode APORT3XCH30 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT3YCH31 (_ACMP_INPUTSEL_POSSEL_APORT3YCH31 << 0) /**< Shifted mode APORT3YCH31 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT4YCH0 (_ACMP_INPUTSEL_POSSEL_APORT4YCH0 << 0) /**< Shifted mode APORT4YCH0 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT4XCH1 (_ACMP_INPUTSEL_POSSEL_APORT4XCH1 << 0) /**< Shifted mode APORT4XCH1 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT4YCH2 (_ACMP_INPUTSEL_POSSEL_APORT4YCH2 << 0) /**< Shifted mode APORT4YCH2 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT4XCH3 (_ACMP_INPUTSEL_POSSEL_APORT4XCH3 << 0) /**< Shifted mode APORT4XCH3 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT4YCH4 (_ACMP_INPUTSEL_POSSEL_APORT4YCH4 << 0) /**< Shifted mode APORT4YCH4 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT4XCH5 (_ACMP_INPUTSEL_POSSEL_APORT4XCH5 << 0) /**< Shifted mode APORT4XCH5 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT4YCH6 (_ACMP_INPUTSEL_POSSEL_APORT4YCH6 << 0) /**< Shifted mode APORT4YCH6 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT4XCH7 (_ACMP_INPUTSEL_POSSEL_APORT4XCH7 << 0) /**< Shifted mode APORT4XCH7 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT4YCH8 (_ACMP_INPUTSEL_POSSEL_APORT4YCH8 << 0) /**< Shifted mode APORT4YCH8 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT4XCH9 (_ACMP_INPUTSEL_POSSEL_APORT4XCH9 << 0) /**< Shifted mode APORT4XCH9 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT4YCH10 (_ACMP_INPUTSEL_POSSEL_APORT4YCH10 << 0) /**< Shifted mode APORT4YCH10 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT4XCH11 (_ACMP_INPUTSEL_POSSEL_APORT4XCH11 << 0) /**< Shifted mode APORT4XCH11 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT4YCH12 (_ACMP_INPUTSEL_POSSEL_APORT4YCH12 << 0) /**< Shifted mode APORT4YCH12 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT4XCH13 (_ACMP_INPUTSEL_POSSEL_APORT4XCH13 << 0) /**< Shifted mode APORT4XCH13 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT4YCH16 (_ACMP_INPUTSEL_POSSEL_APORT4YCH16 << 0) /**< Shifted mode APORT4YCH16 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT4XCH17 (_ACMP_INPUTSEL_POSSEL_APORT4XCH17 << 0) /**< Shifted mode APORT4XCH17 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT4YCH18 (_ACMP_INPUTSEL_POSSEL_APORT4YCH18 << 0) /**< Shifted mode APORT4YCH18 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT4XCH19 (_ACMP_INPUTSEL_POSSEL_APORT4XCH19 << 0) /**< Shifted mode APORT4XCH19 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT4YCH20 (_ACMP_INPUTSEL_POSSEL_APORT4YCH20 << 0) /**< Shifted mode APORT4YCH20 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT4XCH21 (_ACMP_INPUTSEL_POSSEL_APORT4XCH21 << 0) /**< Shifted mode APORT4XCH21 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT4YCH22 (_ACMP_INPUTSEL_POSSEL_APORT4YCH22 << 0) /**< Shifted mode APORT4YCH22 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT4XCH23 (_ACMP_INPUTSEL_POSSEL_APORT4XCH23 << 0) /**< Shifted mode APORT4XCH23 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT4YCH24 (_ACMP_INPUTSEL_POSSEL_APORT4YCH24 << 0) /**< Shifted mode APORT4YCH24 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT4XCH25 (_ACMP_INPUTSEL_POSSEL_APORT4XCH25 << 0) /**< Shifted mode APORT4XCH25 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT4YCH26 (_ACMP_INPUTSEL_POSSEL_APORT4YCH26 << 0) /**< Shifted mode APORT4YCH26 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT4XCH27 (_ACMP_INPUTSEL_POSSEL_APORT4XCH27 << 0) /**< Shifted mode APORT4XCH27 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT4YCH28 (_ACMP_INPUTSEL_POSSEL_APORT4YCH28 << 0) /**< Shifted mode APORT4YCH28 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT4XCH29 (_ACMP_INPUTSEL_POSSEL_APORT4XCH29 << 0) /**< Shifted mode APORT4XCH29 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT4YCH30 (_ACMP_INPUTSEL_POSSEL_APORT4YCH30 << 0) /**< Shifted mode APORT4YCH30 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT4YCH14 (_ACMP_INPUTSEL_POSSEL_APORT4YCH14 << 0) /**< Shifted mode APORT4YCH14 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT4XCH15 (_ACMP_INPUTSEL_POSSEL_APORT4XCH15 << 0) /**< Shifted mode APORT4XCH15 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT4XCH31 (_ACMP_INPUTSEL_POSSEL_APORT4XCH31 << 0) /**< Shifted mode APORT4XCH31 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_DACOUT0 (_ACMP_INPUTSEL_POSSEL_DACOUT0 << 0) /**< Shifted mode DACOUT0 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_DACOUT1 (_ACMP_INPUTSEL_POSSEL_DACOUT1 << 0) /**< Shifted mode DACOUT1 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_VLP (_ACMP_INPUTSEL_POSSEL_VLP << 0) /**< Shifted mode VLP for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_VBDIV (_ACMP_INPUTSEL_POSSEL_VBDIV << 0) /**< Shifted mode VBDIV for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_VADIV (_ACMP_INPUTSEL_POSSEL_VADIV << 0) /**< Shifted mode VADIV for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_VDD (_ACMP_INPUTSEL_POSSEL_VDD << 0) /**< Shifted mode VDD for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_VSS (_ACMP_INPUTSEL_POSSEL_VSS << 0) /**< Shifted mode VSS for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_SHIFT 8 /**< Shift value for ACMP_NEGSEL */ #define _ACMP_INPUTSEL_NEGSEL_MASK 0xFF00UL /**< Bit mask for ACMP_NEGSEL */ #define _ACMP_INPUTSEL_NEGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT0XCH0 0x00000000UL /**< Mode APORT0XCH0 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT0XCH1 0x00000001UL /**< Mode APORT0XCH1 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT0XCH2 0x00000002UL /**< Mode APORT0XCH2 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT0XCH3 0x00000003UL /**< Mode APORT0XCH3 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT0XCH4 0x00000004UL /**< Mode APORT0XCH4 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT0XCH5 0x00000005UL /**< Mode APORT0XCH5 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT0XCH6 0x00000006UL /**< Mode APORT0XCH6 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT0XCH7 0x00000007UL /**< Mode APORT0XCH7 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT0XCH8 0x00000008UL /**< Mode APORT0XCH8 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT0XCH9 0x00000009UL /**< Mode APORT0XCH9 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT0XCH10 0x0000000AUL /**< Mode APORT0XCH10 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT0XCH11 0x0000000BUL /**< Mode APORT0XCH11 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT0XCH12 0x0000000CUL /**< Mode APORT0XCH12 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT0XCH13 0x0000000DUL /**< Mode APORT0XCH13 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT0XCH14 0x0000000EUL /**< Mode APORT0XCH14 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT0XCH15 0x0000000FUL /**< Mode APORT0XCH15 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT0YCH0 0x00000010UL /**< Mode APORT0YCH0 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT0YCH1 0x00000011UL /**< Mode APORT0YCH1 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT0YCH2 0x00000012UL /**< Mode APORT0YCH2 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT0YCH3 0x00000013UL /**< Mode APORT0YCH3 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT0YCH4 0x00000014UL /**< Mode APORT0YCH4 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT0YCH5 0x00000015UL /**< Mode APORT0YCH5 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT0YCH6 0x00000016UL /**< Mode APORT0YCH6 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT0YCH7 0x00000017UL /**< Mode APORT0YCH7 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT0YCH8 0x00000018UL /**< Mode APORT0YCH8 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT0YCH9 0x00000019UL /**< Mode APORT0YCH9 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT0YCH10 0x0000001AUL /**< Mode APORT0YCH10 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT0YCH11 0x0000001BUL /**< Mode APORT0YCH11 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT0YCH12 0x0000001CUL /**< Mode APORT0YCH12 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT0YCH13 0x0000001DUL /**< Mode APORT0YCH13 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT0YCH14 0x0000001EUL /**< Mode APORT0YCH14 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT0YCH15 0x0000001FUL /**< Mode APORT0YCH15 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT1XCH0 0x00000020UL /**< Mode APORT1XCH0 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT1YCH1 0x00000021UL /**< Mode APORT1YCH1 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT1XCH2 0x00000022UL /**< Mode APORT1XCH2 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT1YCH3 0x00000023UL /**< Mode APORT1YCH3 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT1XCH4 0x00000024UL /**< Mode APORT1XCH4 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT1YCH5 0x00000025UL /**< Mode APORT1YCH5 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT1XCH6 0x00000026UL /**< Mode APORT1XCH6 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT1YCH7 0x00000027UL /**< Mode APORT1YCH7 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT1XCH8 0x00000028UL /**< Mode APORT1XCH8 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT1YCH9 0x00000029UL /**< Mode APORT1YCH9 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT1XCH10 0x0000002AUL /**< Mode APORT1XCH10 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT1YCH11 0x0000002BUL /**< Mode APORT1YCH11 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT1XCH12 0x0000002CUL /**< Mode APORT1XCH12 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT1YCH13 0x0000002DUL /**< Mode APORT1YCH13 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT1XCH14 0x0000002EUL /**< Mode APORT1XCH14 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT1YCH15 0x0000002FUL /**< Mode APORT1YCH15 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT1XCH16 0x00000030UL /**< Mode APORT1XCH16 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT1YCH17 0x00000031UL /**< Mode APORT1YCH17 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT1XCH18 0x00000032UL /**< Mode APORT1XCH18 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT1YCH19 0x00000033UL /**< Mode APORT1YCH19 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT1XCH20 0x00000034UL /**< Mode APORT1XCH20 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT1YCH21 0x00000035UL /**< Mode APORT1YCH21 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT1XCH22 0x00000036UL /**< Mode APORT1XCH22 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT1YCH23 0x00000037UL /**< Mode APORT1YCH23 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT1XCH24 0x00000038UL /**< Mode APORT1XCH24 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT1YCH25 0x00000039UL /**< Mode APORT1YCH25 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT1XCH26 0x0000003AUL /**< Mode APORT1XCH26 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT1YCH27 0x0000003BUL /**< Mode APORT1YCH27 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT1XCH28 0x0000003CUL /**< Mode APORT1XCH28 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT1YCH29 0x0000003DUL /**< Mode APORT1YCH29 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT1XCH30 0x0000003EUL /**< Mode APORT1XCH30 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT1YCH31 0x0000003FUL /**< Mode APORT1YCH31 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT2YCH0 0x00000040UL /**< Mode APORT2YCH0 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT2XCH1 0x00000041UL /**< Mode APORT2XCH1 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT2YCH2 0x00000042UL /**< Mode APORT2YCH2 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT2XCH3 0x00000043UL /**< Mode APORT2XCH3 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT2YCH4 0x00000044UL /**< Mode APORT2YCH4 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT2XCH5 0x00000045UL /**< Mode APORT2XCH5 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT2YCH6 0x00000046UL /**< Mode APORT2YCH6 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT2XCH7 0x00000047UL /**< Mode APORT2XCH7 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT2YCH8 0x00000048UL /**< Mode APORT2YCH8 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT2XCH9 0x00000049UL /**< Mode APORT2XCH9 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT2YCH10 0x0000004AUL /**< Mode APORT2YCH10 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT2XCH11 0x0000004BUL /**< Mode APORT2XCH11 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT2YCH12 0x0000004CUL /**< Mode APORT2YCH12 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT2XCH13 0x0000004DUL /**< Mode APORT2XCH13 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT2YCH14 0x0000004EUL /**< Mode APORT2YCH14 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT2XCH15 0x0000004FUL /**< Mode APORT2XCH15 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT2YCH16 0x00000050UL /**< Mode APORT2YCH16 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT2XCH17 0x00000051UL /**< Mode APORT2XCH17 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT2YCH18 0x00000052UL /**< Mode APORT2YCH18 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT2XCH19 0x00000053UL /**< Mode APORT2XCH19 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT2YCH20 0x00000054UL /**< Mode APORT2YCH20 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT2XCH21 0x00000055UL /**< Mode APORT2XCH21 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT2YCH22 0x00000056UL /**< Mode APORT2YCH22 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT2XCH23 0x00000057UL /**< Mode APORT2XCH23 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT2YCH24 0x00000058UL /**< Mode APORT2YCH24 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT2XCH25 0x00000059UL /**< Mode APORT2XCH25 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT2YCH26 0x0000005AUL /**< Mode APORT2YCH26 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT2XCH27 0x0000005BUL /**< Mode APORT2XCH27 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT2YCH28 0x0000005CUL /**< Mode APORT2YCH28 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT2XCH29 0x0000005DUL /**< Mode APORT2XCH29 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT2YCH30 0x0000005EUL /**< Mode APORT2YCH30 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT2XCH31 0x0000005FUL /**< Mode APORT2XCH31 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT3XCH0 0x00000060UL /**< Mode APORT3XCH0 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT3YCH1 0x00000061UL /**< Mode APORT3YCH1 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT3XCH2 0x00000062UL /**< Mode APORT3XCH2 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT3YCH3 0x00000063UL /**< Mode APORT3YCH3 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT3XCH4 0x00000064UL /**< Mode APORT3XCH4 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT3YCH5 0x00000065UL /**< Mode APORT3YCH5 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT3XCH6 0x00000066UL /**< Mode APORT3XCH6 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT3YCH7 0x00000067UL /**< Mode APORT3YCH7 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT3XCH8 0x00000068UL /**< Mode APORT3XCH8 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT3YCH9 0x00000069UL /**< Mode APORT3YCH9 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT3XCH10 0x0000006AUL /**< Mode APORT3XCH10 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT3YCH11 0x0000006BUL /**< Mode APORT3YCH11 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT3XCH12 0x0000006CUL /**< Mode APORT3XCH12 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT3YCH13 0x0000006DUL /**< Mode APORT3YCH13 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT3XCH14 0x0000006EUL /**< Mode APORT3XCH14 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT3YCH15 0x0000006FUL /**< Mode APORT3YCH15 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT3XCH16 0x00000070UL /**< Mode APORT3XCH16 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT3YCH17 0x00000071UL /**< Mode APORT3YCH17 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT3XCH18 0x00000072UL /**< Mode APORT3XCH18 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT3YCH19 0x00000073UL /**< Mode APORT3YCH19 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT3XCH20 0x00000074UL /**< Mode APORT3XCH20 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT3YCH21 0x00000075UL /**< Mode APORT3YCH21 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT3XCH22 0x00000076UL /**< Mode APORT3XCH22 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT3YCH23 0x00000077UL /**< Mode APORT3YCH23 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT3XCH24 0x00000078UL /**< Mode APORT3XCH24 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT3YCH25 0x00000079UL /**< Mode APORT3YCH25 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT3XCH26 0x0000007AUL /**< Mode APORT3XCH26 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT3YCH27 0x0000007BUL /**< Mode APORT3YCH27 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT3XCH28 0x0000007CUL /**< Mode APORT3XCH28 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT3YCH29 0x0000007DUL /**< Mode APORT3YCH29 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT3XCH30 0x0000007EUL /**< Mode APORT3XCH30 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT3YCH31 0x0000007FUL /**< Mode APORT3YCH31 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT4YCH0 0x00000080UL /**< Mode APORT4YCH0 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT4XCH1 0x00000081UL /**< Mode APORT4XCH1 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT4YCH2 0x00000082UL /**< Mode APORT4YCH2 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT4XCH3 0x00000083UL /**< Mode APORT4XCH3 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT4YCH4 0x00000084UL /**< Mode APORT4YCH4 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT4XCH5 0x00000085UL /**< Mode APORT4XCH5 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT4YCH6 0x00000086UL /**< Mode APORT4YCH6 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT4XCH7 0x00000087UL /**< Mode APORT4XCH7 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT4YCH8 0x00000088UL /**< Mode APORT4YCH8 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT4XCH9 0x00000089UL /**< Mode APORT4XCH9 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT4YCH10 0x0000008AUL /**< Mode APORT4YCH10 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT4XCH11 0x0000008BUL /**< Mode APORT4XCH11 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT4YCH12 0x0000008CUL /**< Mode APORT4YCH12 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT4XCH13 0x0000008DUL /**< Mode APORT4XCH13 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT4YCH16 0x00000090UL /**< Mode APORT4YCH16 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT4XCH17 0x00000091UL /**< Mode APORT4XCH17 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT4YCH18 0x00000092UL /**< Mode APORT4YCH18 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT4XCH19 0x00000093UL /**< Mode APORT4XCH19 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT4YCH20 0x00000094UL /**< Mode APORT4YCH20 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT4XCH21 0x00000095UL /**< Mode APORT4XCH21 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT4YCH22 0x00000096UL /**< Mode APORT4YCH22 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT4XCH23 0x00000097UL /**< Mode APORT4XCH23 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT4YCH24 0x00000098UL /**< Mode APORT4YCH24 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT4XCH25 0x00000099UL /**< Mode APORT4XCH25 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT4YCH26 0x0000009AUL /**< Mode APORT4YCH26 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT4XCH27 0x0000009BUL /**< Mode APORT4XCH27 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT4YCH28 0x0000009CUL /**< Mode APORT4YCH28 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT4XCH29 0x0000009DUL /**< Mode APORT4XCH29 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT4YCH30 0x0000009EUL /**< Mode APORT4YCH30 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT4YCH14 0x0000009EUL /**< Mode APORT4YCH14 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT4XCH15 0x0000009FUL /**< Mode APORT4XCH15 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT4XCH31 0x0000009FUL /**< Mode APORT4XCH31 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_DACOUT0 0x000000F2UL /**< Mode DACOUT0 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_DACOUT1 0x000000F3UL /**< Mode DACOUT1 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_VLP 0x000000FBUL /**< Mode VLP for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_VBDIV 0x000000FCUL /**< Mode VBDIV for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_VADIV 0x000000FDUL /**< Mode VADIV for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_VDD 0x000000FEUL /**< Mode VDD for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_VSS 0x000000FFUL /**< Mode VSS for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_DEFAULT (_ACMP_INPUTSEL_NEGSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT0XCH0 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH0 << 8) /**< Shifted mode APORT0XCH0 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT0XCH1 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH1 << 8) /**< Shifted mode APORT0XCH1 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT0XCH2 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH2 << 8) /**< Shifted mode APORT0XCH2 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT0XCH3 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH3 << 8) /**< Shifted mode APORT0XCH3 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT0XCH4 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH4 << 8) /**< Shifted mode APORT0XCH4 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT0XCH5 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH5 << 8) /**< Shifted mode APORT0XCH5 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT0XCH6 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH6 << 8) /**< Shifted mode APORT0XCH6 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT0XCH7 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH7 << 8) /**< Shifted mode APORT0XCH7 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT0XCH8 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH8 << 8) /**< Shifted mode APORT0XCH8 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT0XCH9 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH9 << 8) /**< Shifted mode APORT0XCH9 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT0XCH10 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH10 << 8) /**< Shifted mode APORT0XCH10 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT0XCH11 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH11 << 8) /**< Shifted mode APORT0XCH11 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT0XCH12 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH12 << 8) /**< Shifted mode APORT0XCH12 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT0XCH13 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH13 << 8) /**< Shifted mode APORT0XCH13 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT0XCH14 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH14 << 8) /**< Shifted mode APORT0XCH14 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT0XCH15 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH15 << 8) /**< Shifted mode APORT0XCH15 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT0YCH0 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH0 << 8) /**< Shifted mode APORT0YCH0 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT0YCH1 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH1 << 8) /**< Shifted mode APORT0YCH1 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT0YCH2 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH2 << 8) /**< Shifted mode APORT0YCH2 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT0YCH3 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH3 << 8) /**< Shifted mode APORT0YCH3 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT0YCH4 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH4 << 8) /**< Shifted mode APORT0YCH4 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT0YCH5 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH5 << 8) /**< Shifted mode APORT0YCH5 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT0YCH6 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH6 << 8) /**< Shifted mode APORT0YCH6 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT0YCH7 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH7 << 8) /**< Shifted mode APORT0YCH7 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT0YCH8 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH8 << 8) /**< Shifted mode APORT0YCH8 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT0YCH9 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH9 << 8) /**< Shifted mode APORT0YCH9 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT0YCH10 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH10 << 8) /**< Shifted mode APORT0YCH10 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT0YCH11 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH11 << 8) /**< Shifted mode APORT0YCH11 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT0YCH12 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH12 << 8) /**< Shifted mode APORT0YCH12 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT0YCH13 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH13 << 8) /**< Shifted mode APORT0YCH13 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT0YCH14 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH14 << 8) /**< Shifted mode APORT0YCH14 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT0YCH15 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH15 << 8) /**< Shifted mode APORT0YCH15 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT1XCH0 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH0 << 8) /**< Shifted mode APORT1XCH0 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT1YCH1 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH1 << 8) /**< Shifted mode APORT1YCH1 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT1XCH2 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH2 << 8) /**< Shifted mode APORT1XCH2 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT1YCH3 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH3 << 8) /**< Shifted mode APORT1YCH3 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT1XCH4 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH4 << 8) /**< Shifted mode APORT1XCH4 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT1YCH5 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH5 << 8) /**< Shifted mode APORT1YCH5 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT1XCH6 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH6 << 8) /**< Shifted mode APORT1XCH6 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT1YCH7 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH7 << 8) /**< Shifted mode APORT1YCH7 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT1XCH8 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH8 << 8) /**< Shifted mode APORT1XCH8 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT1YCH9 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH9 << 8) /**< Shifted mode APORT1YCH9 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT1XCH10 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH10 << 8) /**< Shifted mode APORT1XCH10 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT1YCH11 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH11 << 8) /**< Shifted mode APORT1YCH11 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT1XCH12 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH12 << 8) /**< Shifted mode APORT1XCH12 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT1YCH13 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH13 << 8) /**< Shifted mode APORT1YCH13 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT1XCH14 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH14 << 8) /**< Shifted mode APORT1XCH14 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT1YCH15 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH15 << 8) /**< Shifted mode APORT1YCH15 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT1XCH16 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH16 << 8) /**< Shifted mode APORT1XCH16 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT1YCH17 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH17 << 8) /**< Shifted mode APORT1YCH17 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT1XCH18 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH18 << 8) /**< Shifted mode APORT1XCH18 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT1YCH19 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH19 << 8) /**< Shifted mode APORT1YCH19 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT1XCH20 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH20 << 8) /**< Shifted mode APORT1XCH20 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT1YCH21 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH21 << 8) /**< Shifted mode APORT1YCH21 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT1XCH22 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH22 << 8) /**< Shifted mode APORT1XCH22 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT1YCH23 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH23 << 8) /**< Shifted mode APORT1YCH23 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT1XCH24 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH24 << 8) /**< Shifted mode APORT1XCH24 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT1YCH25 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH25 << 8) /**< Shifted mode APORT1YCH25 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT1XCH26 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH26 << 8) /**< Shifted mode APORT1XCH26 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT1YCH27 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH27 << 8) /**< Shifted mode APORT1YCH27 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT1XCH28 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH28 << 8) /**< Shifted mode APORT1XCH28 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT1YCH29 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH29 << 8) /**< Shifted mode APORT1YCH29 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT1XCH30 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH30 << 8) /**< Shifted mode APORT1XCH30 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT1YCH31 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH31 << 8) /**< Shifted mode APORT1YCH31 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT2YCH0 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH0 << 8) /**< Shifted mode APORT2YCH0 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT2XCH1 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH1 << 8) /**< Shifted mode APORT2XCH1 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT2YCH2 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH2 << 8) /**< Shifted mode APORT2YCH2 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT2XCH3 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH3 << 8) /**< Shifted mode APORT2XCH3 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT2YCH4 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH4 << 8) /**< Shifted mode APORT2YCH4 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT2XCH5 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH5 << 8) /**< Shifted mode APORT2XCH5 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT2YCH6 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH6 << 8) /**< Shifted mode APORT2YCH6 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT2XCH7 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH7 << 8) /**< Shifted mode APORT2XCH7 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT2YCH8 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH8 << 8) /**< Shifted mode APORT2YCH8 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT2XCH9 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH9 << 8) /**< Shifted mode APORT2XCH9 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT2YCH10 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH10 << 8) /**< Shifted mode APORT2YCH10 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT2XCH11 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH11 << 8) /**< Shifted mode APORT2XCH11 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT2YCH12 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH12 << 8) /**< Shifted mode APORT2YCH12 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT2XCH13 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH13 << 8) /**< Shifted mode APORT2XCH13 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT2YCH14 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH14 << 8) /**< Shifted mode APORT2YCH14 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT2XCH15 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH15 << 8) /**< Shifted mode APORT2XCH15 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT2YCH16 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH16 << 8) /**< Shifted mode APORT2YCH16 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT2XCH17 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH17 << 8) /**< Shifted mode APORT2XCH17 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT2YCH18 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH18 << 8) /**< Shifted mode APORT2YCH18 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT2XCH19 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH19 << 8) /**< Shifted mode APORT2XCH19 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT2YCH20 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH20 << 8) /**< Shifted mode APORT2YCH20 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT2XCH21 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH21 << 8) /**< Shifted mode APORT2XCH21 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT2YCH22 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH22 << 8) /**< Shifted mode APORT2YCH22 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT2XCH23 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH23 << 8) /**< Shifted mode APORT2XCH23 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT2YCH24 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH24 << 8) /**< Shifted mode APORT2YCH24 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT2XCH25 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH25 << 8) /**< Shifted mode APORT2XCH25 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT2YCH26 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH26 << 8) /**< Shifted mode APORT2YCH26 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT2XCH27 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH27 << 8) /**< Shifted mode APORT2XCH27 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT2YCH28 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH28 << 8) /**< Shifted mode APORT2YCH28 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT2XCH29 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH29 << 8) /**< Shifted mode APORT2XCH29 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT2YCH30 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH30 << 8) /**< Shifted mode APORT2YCH30 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT2XCH31 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH31 << 8) /**< Shifted mode APORT2XCH31 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT3XCH0 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH0 << 8) /**< Shifted mode APORT3XCH0 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT3YCH1 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH1 << 8) /**< Shifted mode APORT3YCH1 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT3XCH2 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH2 << 8) /**< Shifted mode APORT3XCH2 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT3YCH3 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH3 << 8) /**< Shifted mode APORT3YCH3 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT3XCH4 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH4 << 8) /**< Shifted mode APORT3XCH4 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT3YCH5 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH5 << 8) /**< Shifted mode APORT3YCH5 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT3XCH6 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH6 << 8) /**< Shifted mode APORT3XCH6 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT3YCH7 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH7 << 8) /**< Shifted mode APORT3YCH7 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT3XCH8 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH8 << 8) /**< Shifted mode APORT3XCH8 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT3YCH9 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH9 << 8) /**< Shifted mode APORT3YCH9 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT3XCH10 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH10 << 8) /**< Shifted mode APORT3XCH10 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT3YCH11 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH11 << 8) /**< Shifted mode APORT3YCH11 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT3XCH12 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH12 << 8) /**< Shifted mode APORT3XCH12 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT3YCH13 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH13 << 8) /**< Shifted mode APORT3YCH13 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT3XCH14 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH14 << 8) /**< Shifted mode APORT3XCH14 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT3YCH15 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH15 << 8) /**< Shifted mode APORT3YCH15 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT3XCH16 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH16 << 8) /**< Shifted mode APORT3XCH16 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT3YCH17 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH17 << 8) /**< Shifted mode APORT3YCH17 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT3XCH18 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH18 << 8) /**< Shifted mode APORT3XCH18 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT3YCH19 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH19 << 8) /**< Shifted mode APORT3YCH19 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT3XCH20 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH20 << 8) /**< Shifted mode APORT3XCH20 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT3YCH21 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH21 << 8) /**< Shifted mode APORT3YCH21 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT3XCH22 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH22 << 8) /**< Shifted mode APORT3XCH22 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT3YCH23 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH23 << 8) /**< Shifted mode APORT3YCH23 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT3XCH24 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH24 << 8) /**< Shifted mode APORT3XCH24 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT3YCH25 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH25 << 8) /**< Shifted mode APORT3YCH25 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT3XCH26 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH26 << 8) /**< Shifted mode APORT3XCH26 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT3YCH27 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH27 << 8) /**< Shifted mode APORT3YCH27 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT3XCH28 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH28 << 8) /**< Shifted mode APORT3XCH28 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT3YCH29 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH29 << 8) /**< Shifted mode APORT3YCH29 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT3XCH30 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH30 << 8) /**< Shifted mode APORT3XCH30 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT3YCH31 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH31 << 8) /**< Shifted mode APORT3YCH31 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT4YCH0 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH0 << 8) /**< Shifted mode APORT4YCH0 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT4XCH1 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH1 << 8) /**< Shifted mode APORT4XCH1 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT4YCH2 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH2 << 8) /**< Shifted mode APORT4YCH2 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT4XCH3 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH3 << 8) /**< Shifted mode APORT4XCH3 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT4YCH4 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH4 << 8) /**< Shifted mode APORT4YCH4 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT4XCH5 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH5 << 8) /**< Shifted mode APORT4XCH5 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT4YCH6 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH6 << 8) /**< Shifted mode APORT4YCH6 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT4XCH7 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH7 << 8) /**< Shifted mode APORT4XCH7 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT4YCH8 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH8 << 8) /**< Shifted mode APORT4YCH8 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT4XCH9 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH9 << 8) /**< Shifted mode APORT4XCH9 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT4YCH10 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH10 << 8) /**< Shifted mode APORT4YCH10 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT4XCH11 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH11 << 8) /**< Shifted mode APORT4XCH11 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT4YCH12 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH12 << 8) /**< Shifted mode APORT4YCH12 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT4XCH13 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH13 << 8) /**< Shifted mode APORT4XCH13 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT4YCH16 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH16 << 8) /**< Shifted mode APORT4YCH16 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT4XCH17 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH17 << 8) /**< Shifted mode APORT4XCH17 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT4YCH18 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH18 << 8) /**< Shifted mode APORT4YCH18 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT4XCH19 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH19 << 8) /**< Shifted mode APORT4XCH19 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT4YCH20 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH20 << 8) /**< Shifted mode APORT4YCH20 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT4XCH21 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH21 << 8) /**< Shifted mode APORT4XCH21 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT4YCH22 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH22 << 8) /**< Shifted mode APORT4YCH22 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT4XCH23 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH23 << 8) /**< Shifted mode APORT4XCH23 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT4YCH24 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH24 << 8) /**< Shifted mode APORT4YCH24 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT4XCH25 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH25 << 8) /**< Shifted mode APORT4XCH25 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT4YCH26 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH26 << 8) /**< Shifted mode APORT4YCH26 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT4XCH27 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH27 << 8) /**< Shifted mode APORT4XCH27 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT4YCH28 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH28 << 8) /**< Shifted mode APORT4YCH28 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT4XCH29 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH29 << 8) /**< Shifted mode APORT4XCH29 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT4YCH30 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH30 << 8) /**< Shifted mode APORT4YCH30 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT4YCH14 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH14 << 8) /**< Shifted mode APORT4YCH14 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT4XCH15 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH15 << 8) /**< Shifted mode APORT4XCH15 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT4XCH31 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH31 << 8) /**< Shifted mode APORT4XCH31 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_DACOUT0 (_ACMP_INPUTSEL_NEGSEL_DACOUT0 << 8) /**< Shifted mode DACOUT0 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_DACOUT1 (_ACMP_INPUTSEL_NEGSEL_DACOUT1 << 8) /**< Shifted mode DACOUT1 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_VLP (_ACMP_INPUTSEL_NEGSEL_VLP << 8) /**< Shifted mode VLP for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_VBDIV (_ACMP_INPUTSEL_NEGSEL_VBDIV << 8) /**< Shifted mode VBDIV for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_VADIV (_ACMP_INPUTSEL_NEGSEL_VADIV << 8) /**< Shifted mode VADIV for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_VDD (_ACMP_INPUTSEL_NEGSEL_VDD << 8) /**< Shifted mode VDD for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_VSS (_ACMP_INPUTSEL_NEGSEL_VSS << 8) /**< Shifted mode VSS for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_VASEL_SHIFT 16 /**< Shift value for ACMP_VASEL */ #define _ACMP_INPUTSEL_VASEL_MASK 0x3F0000UL /**< Bit mask for ACMP_VASEL */ #define _ACMP_INPUTSEL_VASEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_VASEL_VDD 0x00000000UL /**< Mode VDD for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_VASEL_APORT2YCH0 0x00000001UL /**< Mode APORT2YCH0 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_VASEL_APORT2YCH2 0x00000003UL /**< Mode APORT2YCH2 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_VASEL_APORT2YCH4 0x00000005UL /**< Mode APORT2YCH4 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_VASEL_APORT2YCH6 0x00000007UL /**< Mode APORT2YCH6 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_VASEL_APORT2YCH8 0x00000009UL /**< Mode APORT2YCH8 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_VASEL_APORT2YCH10 0x0000000BUL /**< Mode APORT2YCH10 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_VASEL_APORT2YCH12 0x0000000DUL /**< Mode APORT2YCH12 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_VASEL_APORT2YCH14 0x0000000FUL /**< Mode APORT2YCH14 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_VASEL_APORT2YCH16 0x00000011UL /**< Mode APORT2YCH16 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_VASEL_APORT2YCH18 0x00000013UL /**< Mode APORT2YCH18 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_VASEL_APORT2YCH20 0x00000015UL /**< Mode APORT2YCH20 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_VASEL_APORT2YCH22 0x00000017UL /**< Mode APORT2YCH22 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_VASEL_APORT2YCH24 0x00000019UL /**< Mode APORT2YCH24 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_VASEL_APORT2YCH26 0x0000001BUL /**< Mode APORT2YCH26 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_VASEL_APORT2YCH28 0x0000001DUL /**< Mode APORT2YCH28 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_VASEL_APORT2YCH30 0x0000001FUL /**< Mode APORT2YCH30 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_VASEL_APORT1XCH0 0x00000020UL /**< Mode APORT1XCH0 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_VASEL_APORT1YCH1 0x00000021UL /**< Mode APORT1YCH1 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_VASEL_APORT1XCH2 0x00000022UL /**< Mode APORT1XCH2 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_VASEL_APORT1YCH3 0x00000023UL /**< Mode APORT1YCH3 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_VASEL_APORT1XCH4 0x00000024UL /**< Mode APORT1XCH4 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_VASEL_APORT1YCH5 0x00000025UL /**< Mode APORT1YCH5 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_VASEL_APORT1XCH6 0x00000026UL /**< Mode APORT1XCH6 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_VASEL_APORT1YCH7 0x00000027UL /**< Mode APORT1YCH7 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_VASEL_APORT1XCH8 0x00000028UL /**< Mode APORT1XCH8 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_VASEL_APORT1YCH9 0x00000029UL /**< Mode APORT1YCH9 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_VASEL_APORT1XCH10 0x0000002AUL /**< Mode APORT1XCH10 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_VASEL_APORT1YCH11 0x0000002BUL /**< Mode APORT1YCH11 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_VASEL_APORT1XCH12 0x0000002CUL /**< Mode APORT1XCH12 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_VASEL_APORT1YCH13 0x0000002DUL /**< Mode APORT1YCH13 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_VASEL_APORT1XCH14 0x0000002EUL /**< Mode APORT1XCH14 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_VASEL_APORT1YCH15 0x0000002FUL /**< Mode APORT1YCH15 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_VASEL_APORT1XCH16 0x00000030UL /**< Mode APORT1XCH16 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_VASEL_APORT1YCH17 0x00000031UL /**< Mode APORT1YCH17 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_VASEL_APORT1XCH18 0x00000032UL /**< Mode APORT1XCH18 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_VASEL_APORT1YCH19 0x00000033UL /**< Mode APORT1YCH19 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_VASEL_APORT1XCH20 0x00000034UL /**< Mode APORT1XCH20 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_VASEL_APORT1YCH21 0x00000035UL /**< Mode APORT1YCH21 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_VASEL_APORT1XCH22 0x00000036UL /**< Mode APORT1XCH22 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_VASEL_APORT1YCH23 0x00000037UL /**< Mode APORT1YCH23 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_VASEL_APORT1XCH24 0x00000038UL /**< Mode APORT1XCH24 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_VASEL_APORT1YCH25 0x00000039UL /**< Mode APORT1YCH25 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_VASEL_APORT1XCH26 0x0000003AUL /**< Mode APORT1XCH26 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_VASEL_APORT1YCH27 0x0000003BUL /**< Mode APORT1YCH27 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_VASEL_APORT1XCH28 0x0000003CUL /**< Mode APORT1XCH28 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_VASEL_APORT1YCH29 0x0000003DUL /**< Mode APORT1YCH29 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_VASEL_APORT1XCH30 0x0000003EUL /**< Mode APORT1XCH30 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_VASEL_APORT1YCH31 0x0000003FUL /**< Mode APORT1YCH31 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_VASEL_DEFAULT (_ACMP_INPUTSEL_VASEL_DEFAULT << 16) /**< Shifted mode DEFAULT for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_VASEL_VDD (_ACMP_INPUTSEL_VASEL_VDD << 16) /**< Shifted mode VDD for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_VASEL_APORT2YCH0 (_ACMP_INPUTSEL_VASEL_APORT2YCH0 << 16) /**< Shifted mode APORT2YCH0 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_VASEL_APORT2YCH2 (_ACMP_INPUTSEL_VASEL_APORT2YCH2 << 16) /**< Shifted mode APORT2YCH2 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_VASEL_APORT2YCH4 (_ACMP_INPUTSEL_VASEL_APORT2YCH4 << 16) /**< Shifted mode APORT2YCH4 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_VASEL_APORT2YCH6 (_ACMP_INPUTSEL_VASEL_APORT2YCH6 << 16) /**< Shifted mode APORT2YCH6 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_VASEL_APORT2YCH8 (_ACMP_INPUTSEL_VASEL_APORT2YCH8 << 16) /**< Shifted mode APORT2YCH8 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_VASEL_APORT2YCH10 (_ACMP_INPUTSEL_VASEL_APORT2YCH10 << 16) /**< Shifted mode APORT2YCH10 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_VASEL_APORT2YCH12 (_ACMP_INPUTSEL_VASEL_APORT2YCH12 << 16) /**< Shifted mode APORT2YCH12 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_VASEL_APORT2YCH14 (_ACMP_INPUTSEL_VASEL_APORT2YCH14 << 16) /**< Shifted mode APORT2YCH14 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_VASEL_APORT2YCH16 (_ACMP_INPUTSEL_VASEL_APORT2YCH16 << 16) /**< Shifted mode APORT2YCH16 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_VASEL_APORT2YCH18 (_ACMP_INPUTSEL_VASEL_APORT2YCH18 << 16) /**< Shifted mode APORT2YCH18 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_VASEL_APORT2YCH20 (_ACMP_INPUTSEL_VASEL_APORT2YCH20 << 16) /**< Shifted mode APORT2YCH20 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_VASEL_APORT2YCH22 (_ACMP_INPUTSEL_VASEL_APORT2YCH22 << 16) /**< Shifted mode APORT2YCH22 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_VASEL_APORT2YCH24 (_ACMP_INPUTSEL_VASEL_APORT2YCH24 << 16) /**< Shifted mode APORT2YCH24 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_VASEL_APORT2YCH26 (_ACMP_INPUTSEL_VASEL_APORT2YCH26 << 16) /**< Shifted mode APORT2YCH26 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_VASEL_APORT2YCH28 (_ACMP_INPUTSEL_VASEL_APORT2YCH28 << 16) /**< Shifted mode APORT2YCH28 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_VASEL_APORT2YCH30 (_ACMP_INPUTSEL_VASEL_APORT2YCH30 << 16) /**< Shifted mode APORT2YCH30 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_VASEL_APORT1XCH0 (_ACMP_INPUTSEL_VASEL_APORT1XCH0 << 16) /**< Shifted mode APORT1XCH0 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_VASEL_APORT1YCH1 (_ACMP_INPUTSEL_VASEL_APORT1YCH1 << 16) /**< Shifted mode APORT1YCH1 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_VASEL_APORT1XCH2 (_ACMP_INPUTSEL_VASEL_APORT1XCH2 << 16) /**< Shifted mode APORT1XCH2 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_VASEL_APORT1YCH3 (_ACMP_INPUTSEL_VASEL_APORT1YCH3 << 16) /**< Shifted mode APORT1YCH3 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_VASEL_APORT1XCH4 (_ACMP_INPUTSEL_VASEL_APORT1XCH4 << 16) /**< Shifted mode APORT1XCH4 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_VASEL_APORT1YCH5 (_ACMP_INPUTSEL_VASEL_APORT1YCH5 << 16) /**< Shifted mode APORT1YCH5 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_VASEL_APORT1XCH6 (_ACMP_INPUTSEL_VASEL_APORT1XCH6 << 16) /**< Shifted mode APORT1XCH6 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_VASEL_APORT1YCH7 (_ACMP_INPUTSEL_VASEL_APORT1YCH7 << 16) /**< Shifted mode APORT1YCH7 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_VASEL_APORT1XCH8 (_ACMP_INPUTSEL_VASEL_APORT1XCH8 << 16) /**< Shifted mode APORT1XCH8 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_VASEL_APORT1YCH9 (_ACMP_INPUTSEL_VASEL_APORT1YCH9 << 16) /**< Shifted mode APORT1YCH9 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_VASEL_APORT1XCH10 (_ACMP_INPUTSEL_VASEL_APORT1XCH10 << 16) /**< Shifted mode APORT1XCH10 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_VASEL_APORT1YCH11 (_ACMP_INPUTSEL_VASEL_APORT1YCH11 << 16) /**< Shifted mode APORT1YCH11 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_VASEL_APORT1XCH12 (_ACMP_INPUTSEL_VASEL_APORT1XCH12 << 16) /**< Shifted mode APORT1XCH12 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_VASEL_APORT1YCH13 (_ACMP_INPUTSEL_VASEL_APORT1YCH13 << 16) /**< Shifted mode APORT1YCH13 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_VASEL_APORT1XCH14 (_ACMP_INPUTSEL_VASEL_APORT1XCH14 << 16) /**< Shifted mode APORT1XCH14 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_VASEL_APORT1YCH15 (_ACMP_INPUTSEL_VASEL_APORT1YCH15 << 16) /**< Shifted mode APORT1YCH15 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_VASEL_APORT1XCH16 (_ACMP_INPUTSEL_VASEL_APORT1XCH16 << 16) /**< Shifted mode APORT1XCH16 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_VASEL_APORT1YCH17 (_ACMP_INPUTSEL_VASEL_APORT1YCH17 << 16) /**< Shifted mode APORT1YCH17 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_VASEL_APORT1XCH18 (_ACMP_INPUTSEL_VASEL_APORT1XCH18 << 16) /**< Shifted mode APORT1XCH18 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_VASEL_APORT1YCH19 (_ACMP_INPUTSEL_VASEL_APORT1YCH19 << 16) /**< Shifted mode APORT1YCH19 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_VASEL_APORT1XCH20 (_ACMP_INPUTSEL_VASEL_APORT1XCH20 << 16) /**< Shifted mode APORT1XCH20 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_VASEL_APORT1YCH21 (_ACMP_INPUTSEL_VASEL_APORT1YCH21 << 16) /**< Shifted mode APORT1YCH21 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_VASEL_APORT1XCH22 (_ACMP_INPUTSEL_VASEL_APORT1XCH22 << 16) /**< Shifted mode APORT1XCH22 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_VASEL_APORT1YCH23 (_ACMP_INPUTSEL_VASEL_APORT1YCH23 << 16) /**< Shifted mode APORT1YCH23 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_VASEL_APORT1XCH24 (_ACMP_INPUTSEL_VASEL_APORT1XCH24 << 16) /**< Shifted mode APORT1XCH24 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_VASEL_APORT1YCH25 (_ACMP_INPUTSEL_VASEL_APORT1YCH25 << 16) /**< Shifted mode APORT1YCH25 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_VASEL_APORT1XCH26 (_ACMP_INPUTSEL_VASEL_APORT1XCH26 << 16) /**< Shifted mode APORT1XCH26 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_VASEL_APORT1YCH27 (_ACMP_INPUTSEL_VASEL_APORT1YCH27 << 16) /**< Shifted mode APORT1YCH27 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_VASEL_APORT1XCH28 (_ACMP_INPUTSEL_VASEL_APORT1XCH28 << 16) /**< Shifted mode APORT1XCH28 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_VASEL_APORT1YCH29 (_ACMP_INPUTSEL_VASEL_APORT1YCH29 << 16) /**< Shifted mode APORT1YCH29 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_VASEL_APORT1XCH30 (_ACMP_INPUTSEL_VASEL_APORT1XCH30 << 16) /**< Shifted mode APORT1XCH30 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_VASEL_APORT1YCH31 (_ACMP_INPUTSEL_VASEL_APORT1YCH31 << 16) /**< Shifted mode APORT1YCH31 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_VBSEL (0x1UL << 22) /**< VB Selection */ #define _ACMP_INPUTSEL_VBSEL_SHIFT 22 /**< Shift value for ACMP_VBSEL */ #define _ACMP_INPUTSEL_VBSEL_MASK 0x400000UL /**< Bit mask for ACMP_VBSEL */ #define _ACMP_INPUTSEL_VBSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_VBSEL_1V25 0x00000000UL /**< Mode 1V25 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_VBSEL_2V5 0x00000001UL /**< Mode 2V5 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_VBSEL_DEFAULT (_ACMP_INPUTSEL_VBSEL_DEFAULT << 22) /**< Shifted mode DEFAULT for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_VBSEL_1V25 (_ACMP_INPUTSEL_VBSEL_1V25 << 22) /**< Shifted mode 1V25 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_VBSEL_2V5 (_ACMP_INPUTSEL_VBSEL_2V5 << 22) /**< Shifted mode 2V5 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_VLPSEL (0x1UL << 24) /**< Low-Power Sampled Voltage Selection */ #define _ACMP_INPUTSEL_VLPSEL_SHIFT 24 /**< Shift value for ACMP_VLPSEL */ #define _ACMP_INPUTSEL_VLPSEL_MASK 0x1000000UL /**< Bit mask for ACMP_VLPSEL */ #define _ACMP_INPUTSEL_VLPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_VLPSEL_VADIV 0x00000000UL /**< Mode VADIV for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_VLPSEL_VBDIV 0x00000001UL /**< Mode VBDIV for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_VLPSEL_DEFAULT (_ACMP_INPUTSEL_VLPSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_VLPSEL_VADIV (_ACMP_INPUTSEL_VLPSEL_VADIV << 24) /**< Shifted mode VADIV for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_VLPSEL_VBDIV (_ACMP_INPUTSEL_VLPSEL_VBDIV << 24) /**< Shifted mode VBDIV for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_CSRESEN (0x1UL << 26) /**< Capacitive Sense Mode Internal Resistor Enable */ #define _ACMP_INPUTSEL_CSRESEN_SHIFT 26 /**< Shift value for ACMP_CSRESEN */ #define _ACMP_INPUTSEL_CSRESEN_MASK 0x4000000UL /**< Bit mask for ACMP_CSRESEN */ #define _ACMP_INPUTSEL_CSRESEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_CSRESEN_DEFAULT (_ACMP_INPUTSEL_CSRESEN_DEFAULT << 26) /**< Shifted mode DEFAULT for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_CSRESSEL_SHIFT 28 /**< Shift value for ACMP_CSRESSEL */ #define _ACMP_INPUTSEL_CSRESSEL_MASK 0x70000000UL /**< Bit mask for ACMP_CSRESSEL */ #define _ACMP_INPUTSEL_CSRESSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_CSRESSEL_RES0 0x00000000UL /**< Mode RES0 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_CSRESSEL_RES1 0x00000001UL /**< Mode RES1 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_CSRESSEL_RES2 0x00000002UL /**< Mode RES2 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_CSRESSEL_RES3 0x00000003UL /**< Mode RES3 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_CSRESSEL_RES4 0x00000004UL /**< Mode RES4 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_CSRESSEL_RES5 0x00000005UL /**< Mode RES5 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_CSRESSEL_RES6 0x00000006UL /**< Mode RES6 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_CSRESSEL_RES7 0x00000007UL /**< Mode RES7 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_CSRESSEL_DEFAULT (_ACMP_INPUTSEL_CSRESSEL_DEFAULT << 28) /**< Shifted mode DEFAULT for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_CSRESSEL_RES0 (_ACMP_INPUTSEL_CSRESSEL_RES0 << 28) /**< Shifted mode RES0 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_CSRESSEL_RES1 (_ACMP_INPUTSEL_CSRESSEL_RES1 << 28) /**< Shifted mode RES1 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_CSRESSEL_RES2 (_ACMP_INPUTSEL_CSRESSEL_RES2 << 28) /**< Shifted mode RES2 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_CSRESSEL_RES3 (_ACMP_INPUTSEL_CSRESSEL_RES3 << 28) /**< Shifted mode RES3 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_CSRESSEL_RES4 (_ACMP_INPUTSEL_CSRESSEL_RES4 << 28) /**< Shifted mode RES4 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_CSRESSEL_RES5 (_ACMP_INPUTSEL_CSRESSEL_RES5 << 28) /**< Shifted mode RES5 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_CSRESSEL_RES6 (_ACMP_INPUTSEL_CSRESSEL_RES6 << 28) /**< Shifted mode RES6 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_CSRESSEL_RES7 (_ACMP_INPUTSEL_CSRESSEL_RES7 << 28) /**< Shifted mode RES7 for ACMP_INPUTSEL */ /* Bit fields for ACMP STATUS */ #define _ACMP_STATUS_RESETVALUE 0x00000000UL /**< Default value for ACMP_STATUS */ #define _ACMP_STATUS_MASK 0x0000000FUL /**< Mask for ACMP_STATUS */ #define ACMP_STATUS_ACMPACT (0x1UL << 0) /**< Analog Comparator Active */ #define _ACMP_STATUS_ACMPACT_SHIFT 0 /**< Shift value for ACMP_ACMPACT */ #define _ACMP_STATUS_ACMPACT_MASK 0x1UL /**< Bit mask for ACMP_ACMPACT */ #define _ACMP_STATUS_ACMPACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_STATUS */ #define ACMP_STATUS_ACMPACT_DEFAULT (_ACMP_STATUS_ACMPACT_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_STATUS */ #define ACMP_STATUS_ACMPOUT (0x1UL << 1) /**< Analog Comparator Output */ #define _ACMP_STATUS_ACMPOUT_SHIFT 1 /**< Shift value for ACMP_ACMPOUT */ #define _ACMP_STATUS_ACMPOUT_MASK 0x2UL /**< Bit mask for ACMP_ACMPOUT */ #define _ACMP_STATUS_ACMPOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_STATUS */ #define ACMP_STATUS_ACMPOUT_DEFAULT (_ACMP_STATUS_ACMPOUT_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_STATUS */ #define ACMP_STATUS_APORTCONFLICT (0x1UL << 2) /**< APORT Conflict Output */ #define _ACMP_STATUS_APORTCONFLICT_SHIFT 2 /**< Shift value for ACMP_APORTCONFLICT */ #define _ACMP_STATUS_APORTCONFLICT_MASK 0x4UL /**< Bit mask for ACMP_APORTCONFLICT */ #define _ACMP_STATUS_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_STATUS */ #define ACMP_STATUS_APORTCONFLICT_DEFAULT (_ACMP_STATUS_APORTCONFLICT_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_STATUS */ #define ACMP_STATUS_EXTIFACT (0x1UL << 3) /**< External Override Interface Active */ #define _ACMP_STATUS_EXTIFACT_SHIFT 3 /**< Shift value for ACMP_EXTIFACT */ #define _ACMP_STATUS_EXTIFACT_MASK 0x8UL /**< Bit mask for ACMP_EXTIFACT */ #define _ACMP_STATUS_EXTIFACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_STATUS */ #define ACMP_STATUS_EXTIFACT_DEFAULT (_ACMP_STATUS_EXTIFACT_DEFAULT << 3) /**< Shifted mode DEFAULT for ACMP_STATUS */ /* Bit fields for ACMP IF */ #define _ACMP_IF_RESETVALUE 0x00000000UL /**< Default value for ACMP_IF */ #define _ACMP_IF_MASK 0x00000007UL /**< Mask for ACMP_IF */ #define ACMP_IF_EDGE (0x1UL << 0) /**< Edge Triggered Interrupt Flag */ #define _ACMP_IF_EDGE_SHIFT 0 /**< Shift value for ACMP_EDGE */ #define _ACMP_IF_EDGE_MASK 0x1UL /**< Bit mask for ACMP_EDGE */ #define _ACMP_IF_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IF */ #define ACMP_IF_EDGE_DEFAULT (_ACMP_IF_EDGE_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_IF */ #define ACMP_IF_WARMUP (0x1UL << 1) /**< Warm-up Interrupt Flag */ #define _ACMP_IF_WARMUP_SHIFT 1 /**< Shift value for ACMP_WARMUP */ #define _ACMP_IF_WARMUP_MASK 0x2UL /**< Bit mask for ACMP_WARMUP */ #define _ACMP_IF_WARMUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IF */ #define ACMP_IF_WARMUP_DEFAULT (_ACMP_IF_WARMUP_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_IF */ #define ACMP_IF_APORTCONFLICT (0x1UL << 2) /**< APORT Conflict Interrupt Flag */ #define _ACMP_IF_APORTCONFLICT_SHIFT 2 /**< Shift value for ACMP_APORTCONFLICT */ #define _ACMP_IF_APORTCONFLICT_MASK 0x4UL /**< Bit mask for ACMP_APORTCONFLICT */ #define _ACMP_IF_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IF */ #define ACMP_IF_APORTCONFLICT_DEFAULT (_ACMP_IF_APORTCONFLICT_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_IF */ /* Bit fields for ACMP IFS */ #define _ACMP_IFS_RESETVALUE 0x00000000UL /**< Default value for ACMP_IFS */ #define _ACMP_IFS_MASK 0x00000007UL /**< Mask for ACMP_IFS */ #define ACMP_IFS_EDGE (0x1UL << 0) /**< Set EDGE Interrupt Flag */ #define _ACMP_IFS_EDGE_SHIFT 0 /**< Shift value for ACMP_EDGE */ #define _ACMP_IFS_EDGE_MASK 0x1UL /**< Bit mask for ACMP_EDGE */ #define _ACMP_IFS_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IFS */ #define ACMP_IFS_EDGE_DEFAULT (_ACMP_IFS_EDGE_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_IFS */ #define ACMP_IFS_WARMUP (0x1UL << 1) /**< Set WARMUP Interrupt Flag */ #define _ACMP_IFS_WARMUP_SHIFT 1 /**< Shift value for ACMP_WARMUP */ #define _ACMP_IFS_WARMUP_MASK 0x2UL /**< Bit mask for ACMP_WARMUP */ #define _ACMP_IFS_WARMUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IFS */ #define ACMP_IFS_WARMUP_DEFAULT (_ACMP_IFS_WARMUP_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_IFS */ #define ACMP_IFS_APORTCONFLICT (0x1UL << 2) /**< Set APORTCONFLICT Interrupt Flag */ #define _ACMP_IFS_APORTCONFLICT_SHIFT 2 /**< Shift value for ACMP_APORTCONFLICT */ #define _ACMP_IFS_APORTCONFLICT_MASK 0x4UL /**< Bit mask for ACMP_APORTCONFLICT */ #define _ACMP_IFS_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IFS */ #define ACMP_IFS_APORTCONFLICT_DEFAULT (_ACMP_IFS_APORTCONFLICT_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_IFS */ /* Bit fields for ACMP IFC */ #define _ACMP_IFC_RESETVALUE 0x00000000UL /**< Default value for ACMP_IFC */ #define _ACMP_IFC_MASK 0x00000007UL /**< Mask for ACMP_IFC */ #define ACMP_IFC_EDGE (0x1UL << 0) /**< Clear EDGE Interrupt Flag */ #define _ACMP_IFC_EDGE_SHIFT 0 /**< Shift value for ACMP_EDGE */ #define _ACMP_IFC_EDGE_MASK 0x1UL /**< Bit mask for ACMP_EDGE */ #define _ACMP_IFC_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IFC */ #define ACMP_IFC_EDGE_DEFAULT (_ACMP_IFC_EDGE_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_IFC */ #define ACMP_IFC_WARMUP (0x1UL << 1) /**< Clear WARMUP Interrupt Flag */ #define _ACMP_IFC_WARMUP_SHIFT 1 /**< Shift value for ACMP_WARMUP */ #define _ACMP_IFC_WARMUP_MASK 0x2UL /**< Bit mask for ACMP_WARMUP */ #define _ACMP_IFC_WARMUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IFC */ #define ACMP_IFC_WARMUP_DEFAULT (_ACMP_IFC_WARMUP_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_IFC */ #define ACMP_IFC_APORTCONFLICT (0x1UL << 2) /**< Clear APORTCONFLICT Interrupt Flag */ #define _ACMP_IFC_APORTCONFLICT_SHIFT 2 /**< Shift value for ACMP_APORTCONFLICT */ #define _ACMP_IFC_APORTCONFLICT_MASK 0x4UL /**< Bit mask for ACMP_APORTCONFLICT */ #define _ACMP_IFC_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IFC */ #define ACMP_IFC_APORTCONFLICT_DEFAULT (_ACMP_IFC_APORTCONFLICT_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_IFC */ /* Bit fields for ACMP IEN */ #define _ACMP_IEN_RESETVALUE 0x00000000UL /**< Default value for ACMP_IEN */ #define _ACMP_IEN_MASK 0x00000007UL /**< Mask for ACMP_IEN */ #define ACMP_IEN_EDGE (0x1UL << 0) /**< EDGE Interrupt Enable */ #define _ACMP_IEN_EDGE_SHIFT 0 /**< Shift value for ACMP_EDGE */ #define _ACMP_IEN_EDGE_MASK 0x1UL /**< Bit mask for ACMP_EDGE */ #define _ACMP_IEN_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IEN */ #define ACMP_IEN_EDGE_DEFAULT (_ACMP_IEN_EDGE_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_IEN */ #define ACMP_IEN_WARMUP (0x1UL << 1) /**< WARMUP Interrupt Enable */ #define _ACMP_IEN_WARMUP_SHIFT 1 /**< Shift value for ACMP_WARMUP */ #define _ACMP_IEN_WARMUP_MASK 0x2UL /**< Bit mask for ACMP_WARMUP */ #define _ACMP_IEN_WARMUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IEN */ #define ACMP_IEN_WARMUP_DEFAULT (_ACMP_IEN_WARMUP_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_IEN */ #define ACMP_IEN_APORTCONFLICT (0x1UL << 2) /**< APORTCONFLICT Interrupt Enable */ #define _ACMP_IEN_APORTCONFLICT_SHIFT 2 /**< Shift value for ACMP_APORTCONFLICT */ #define _ACMP_IEN_APORTCONFLICT_MASK 0x4UL /**< Bit mask for ACMP_APORTCONFLICT */ #define _ACMP_IEN_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IEN */ #define ACMP_IEN_APORTCONFLICT_DEFAULT (_ACMP_IEN_APORTCONFLICT_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_IEN */ /* Bit fields for ACMP APORTREQ */ #define _ACMP_APORTREQ_RESETVALUE 0x00000000UL /**< Default value for ACMP_APORTREQ */ #define _ACMP_APORTREQ_MASK 0x000003FFUL /**< Mask for ACMP_APORTREQ */ #define ACMP_APORTREQ_APORT0XREQ (0x1UL << 0) /**< 1 If the Bus Connected to APORT0X is Requested */ #define _ACMP_APORTREQ_APORT0XREQ_SHIFT 0 /**< Shift value for ACMP_APORT0XREQ */ #define _ACMP_APORTREQ_APORT0XREQ_MASK 0x1UL /**< Bit mask for ACMP_APORT0XREQ */ #define _ACMP_APORTREQ_APORT0XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTREQ */ #define ACMP_APORTREQ_APORT0XREQ_DEFAULT (_ACMP_APORTREQ_APORT0XREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_APORTREQ */ #define ACMP_APORTREQ_APORT0YREQ (0x1UL << 1) /**< 1 If the Bus Connected to APORT0Y is Requested */ #define _ACMP_APORTREQ_APORT0YREQ_SHIFT 1 /**< Shift value for ACMP_APORT0YREQ */ #define _ACMP_APORTREQ_APORT0YREQ_MASK 0x2UL /**< Bit mask for ACMP_APORT0YREQ */ #define _ACMP_APORTREQ_APORT0YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTREQ */ #define ACMP_APORTREQ_APORT0YREQ_DEFAULT (_ACMP_APORTREQ_APORT0YREQ_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_APORTREQ */ #define ACMP_APORTREQ_APORT1XREQ (0x1UL << 2) /**< 1 If the Bus Connected to APORT2X is Requested */ #define _ACMP_APORTREQ_APORT1XREQ_SHIFT 2 /**< Shift value for ACMP_APORT1XREQ */ #define _ACMP_APORTREQ_APORT1XREQ_MASK 0x4UL /**< Bit mask for ACMP_APORT1XREQ */ #define _ACMP_APORTREQ_APORT1XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTREQ */ #define ACMP_APORTREQ_APORT1XREQ_DEFAULT (_ACMP_APORTREQ_APORT1XREQ_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_APORTREQ */ #define ACMP_APORTREQ_APORT1YREQ (0x1UL << 3) /**< 1 If the Bus Connected to APORT1X is Requested */ #define _ACMP_APORTREQ_APORT1YREQ_SHIFT 3 /**< Shift value for ACMP_APORT1YREQ */ #define _ACMP_APORTREQ_APORT1YREQ_MASK 0x8UL /**< Bit mask for ACMP_APORT1YREQ */ #define _ACMP_APORTREQ_APORT1YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTREQ */ #define ACMP_APORTREQ_APORT1YREQ_DEFAULT (_ACMP_APORTREQ_APORT1YREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for ACMP_APORTREQ */ #define ACMP_APORTREQ_APORT2XREQ (0x1UL << 4) /**< 1 If the Bus Connected to APORT2X is Requested */ #define _ACMP_APORTREQ_APORT2XREQ_SHIFT 4 /**< Shift value for ACMP_APORT2XREQ */ #define _ACMP_APORTREQ_APORT2XREQ_MASK 0x10UL /**< Bit mask for ACMP_APORT2XREQ */ #define _ACMP_APORTREQ_APORT2XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTREQ */ #define ACMP_APORTREQ_APORT2XREQ_DEFAULT (_ACMP_APORTREQ_APORT2XREQ_DEFAULT << 4) /**< Shifted mode DEFAULT for ACMP_APORTREQ */ #define ACMP_APORTREQ_APORT2YREQ (0x1UL << 5) /**< 1 If the Bus Connected to APORT2Y is Requested */ #define _ACMP_APORTREQ_APORT2YREQ_SHIFT 5 /**< Shift value for ACMP_APORT2YREQ */ #define _ACMP_APORTREQ_APORT2YREQ_MASK 0x20UL /**< Bit mask for ACMP_APORT2YREQ */ #define _ACMP_APORTREQ_APORT2YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTREQ */ #define ACMP_APORTREQ_APORT2YREQ_DEFAULT (_ACMP_APORTREQ_APORT2YREQ_DEFAULT << 5) /**< Shifted mode DEFAULT for ACMP_APORTREQ */ #define ACMP_APORTREQ_APORT3XREQ (0x1UL << 6) /**< 1 If the Bus Connected to APORT3X is Requested */ #define _ACMP_APORTREQ_APORT3XREQ_SHIFT 6 /**< Shift value for ACMP_APORT3XREQ */ #define _ACMP_APORTREQ_APORT3XREQ_MASK 0x40UL /**< Bit mask for ACMP_APORT3XREQ */ #define _ACMP_APORTREQ_APORT3XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTREQ */ #define ACMP_APORTREQ_APORT3XREQ_DEFAULT (_ACMP_APORTREQ_APORT3XREQ_DEFAULT << 6) /**< Shifted mode DEFAULT for ACMP_APORTREQ */ #define ACMP_APORTREQ_APORT3YREQ (0x1UL << 7) /**< 1 If the Bus Connected to APORT3Y is Requested */ #define _ACMP_APORTREQ_APORT3YREQ_SHIFT 7 /**< Shift value for ACMP_APORT3YREQ */ #define _ACMP_APORTREQ_APORT3YREQ_MASK 0x80UL /**< Bit mask for ACMP_APORT3YREQ */ #define _ACMP_APORTREQ_APORT3YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTREQ */ #define ACMP_APORTREQ_APORT3YREQ_DEFAULT (_ACMP_APORTREQ_APORT3YREQ_DEFAULT << 7) /**< Shifted mode DEFAULT for ACMP_APORTREQ */ #define ACMP_APORTREQ_APORT4XREQ (0x1UL << 8) /**< 1 If the Bus Connected to APORT4X is Requested */ #define _ACMP_APORTREQ_APORT4XREQ_SHIFT 8 /**< Shift value for ACMP_APORT4XREQ */ #define _ACMP_APORTREQ_APORT4XREQ_MASK 0x100UL /**< Bit mask for ACMP_APORT4XREQ */ #define _ACMP_APORTREQ_APORT4XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTREQ */ #define ACMP_APORTREQ_APORT4XREQ_DEFAULT (_ACMP_APORTREQ_APORT4XREQ_DEFAULT << 8) /**< Shifted mode DEFAULT for ACMP_APORTREQ */ #define ACMP_APORTREQ_APORT4YREQ (0x1UL << 9) /**< 1 If the Bus Connected to APORT4Y is Requested */ #define _ACMP_APORTREQ_APORT4YREQ_SHIFT 9 /**< Shift value for ACMP_APORT4YREQ */ #define _ACMP_APORTREQ_APORT4YREQ_MASK 0x200UL /**< Bit mask for ACMP_APORT4YREQ */ #define _ACMP_APORTREQ_APORT4YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTREQ */ #define ACMP_APORTREQ_APORT4YREQ_DEFAULT (_ACMP_APORTREQ_APORT4YREQ_DEFAULT << 9) /**< Shifted mode DEFAULT for ACMP_APORTREQ */ /* Bit fields for ACMP APORTCONFLICT */ #define _ACMP_APORTCONFLICT_RESETVALUE 0x00000000UL /**< Default value for ACMP_APORTCONFLICT */ #define _ACMP_APORTCONFLICT_MASK 0x000003FFUL /**< Mask for ACMP_APORTCONFLICT */ #define ACMP_APORTCONFLICT_APORT0XCONFLICT (0x1UL << 0) /**< 1 If the Bus Connected to APORT0X is in Conflict With Another Peripheral */ #define _ACMP_APORTCONFLICT_APORT0XCONFLICT_SHIFT 0 /**< Shift value for ACMP_APORT0XCONFLICT */ #define _ACMP_APORTCONFLICT_APORT0XCONFLICT_MASK 0x1UL /**< Bit mask for ACMP_APORT0XCONFLICT */ #define _ACMP_APORTCONFLICT_APORT0XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTCONFLICT */ #define ACMP_APORTCONFLICT_APORT0XCONFLICT_DEFAULT (_ACMP_APORTCONFLICT_APORT0XCONFLICT_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */ #define ACMP_APORTCONFLICT_APORT0YCONFLICT (0x1UL << 1) /**< 1 If the Bus Connected to APORT0Y is in Conflict With Another Peripheral */ #define _ACMP_APORTCONFLICT_APORT0YCONFLICT_SHIFT 1 /**< Shift value for ACMP_APORT0YCONFLICT */ #define _ACMP_APORTCONFLICT_APORT0YCONFLICT_MASK 0x2UL /**< Bit mask for ACMP_APORT0YCONFLICT */ #define _ACMP_APORTCONFLICT_APORT0YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTCONFLICT */ #define ACMP_APORTCONFLICT_APORT0YCONFLICT_DEFAULT (_ACMP_APORTCONFLICT_APORT0YCONFLICT_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */ #define ACMP_APORTCONFLICT_APORT1XCONFLICT (0x1UL << 2) /**< 1 If the Bus Connected to APORT1X is in Conflict With Another Peripheral */ #define _ACMP_APORTCONFLICT_APORT1XCONFLICT_SHIFT 2 /**< Shift value for ACMP_APORT1XCONFLICT */ #define _ACMP_APORTCONFLICT_APORT1XCONFLICT_MASK 0x4UL /**< Bit mask for ACMP_APORT1XCONFLICT */ #define _ACMP_APORTCONFLICT_APORT1XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTCONFLICT */ #define ACMP_APORTCONFLICT_APORT1XCONFLICT_DEFAULT (_ACMP_APORTCONFLICT_APORT1XCONFLICT_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */ #define ACMP_APORTCONFLICT_APORT1YCONFLICT (0x1UL << 3) /**< 1 If the Bus Connected to APORT1X is in Conflict With Another Peripheral */ #define _ACMP_APORTCONFLICT_APORT1YCONFLICT_SHIFT 3 /**< Shift value for ACMP_APORT1YCONFLICT */ #define _ACMP_APORTCONFLICT_APORT1YCONFLICT_MASK 0x8UL /**< Bit mask for ACMP_APORT1YCONFLICT */ #define _ACMP_APORTCONFLICT_APORT1YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTCONFLICT */ #define ACMP_APORTCONFLICT_APORT1YCONFLICT_DEFAULT (_ACMP_APORTCONFLICT_APORT1YCONFLICT_DEFAULT << 3) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */ #define ACMP_APORTCONFLICT_APORT2XCONFLICT (0x1UL << 4) /**< 1 If the Bus Connected to APORT2X is in Conflict With Another Peripheral */ #define _ACMP_APORTCONFLICT_APORT2XCONFLICT_SHIFT 4 /**< Shift value for ACMP_APORT2XCONFLICT */ #define _ACMP_APORTCONFLICT_APORT2XCONFLICT_MASK 0x10UL /**< Bit mask for ACMP_APORT2XCONFLICT */ #define _ACMP_APORTCONFLICT_APORT2XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTCONFLICT */ #define ACMP_APORTCONFLICT_APORT2XCONFLICT_DEFAULT (_ACMP_APORTCONFLICT_APORT2XCONFLICT_DEFAULT << 4) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */ #define ACMP_APORTCONFLICT_APORT2YCONFLICT (0x1UL << 5) /**< 1 If the Bus Connected to APORT2Y is in Conflict With Another Peripheral */ #define _ACMP_APORTCONFLICT_APORT2YCONFLICT_SHIFT 5 /**< Shift value for ACMP_APORT2YCONFLICT */ #define _ACMP_APORTCONFLICT_APORT2YCONFLICT_MASK 0x20UL /**< Bit mask for ACMP_APORT2YCONFLICT */ #define _ACMP_APORTCONFLICT_APORT2YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTCONFLICT */ #define ACMP_APORTCONFLICT_APORT2YCONFLICT_DEFAULT (_ACMP_APORTCONFLICT_APORT2YCONFLICT_DEFAULT << 5) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */ #define ACMP_APORTCONFLICT_APORT3XCONFLICT (0x1UL << 6) /**< 1 If the Bus Connected to APORT3X is in Conflict With Another Peripheral */ #define _ACMP_APORTCONFLICT_APORT3XCONFLICT_SHIFT 6 /**< Shift value for ACMP_APORT3XCONFLICT */ #define _ACMP_APORTCONFLICT_APORT3XCONFLICT_MASK 0x40UL /**< Bit mask for ACMP_APORT3XCONFLICT */ #define _ACMP_APORTCONFLICT_APORT3XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTCONFLICT */ #define ACMP_APORTCONFLICT_APORT3XCONFLICT_DEFAULT (_ACMP_APORTCONFLICT_APORT3XCONFLICT_DEFAULT << 6) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */ #define ACMP_APORTCONFLICT_APORT3YCONFLICT (0x1UL << 7) /**< 1 If the Bus Connected to APORT3Y is in Conflict With Another Peripheral */ #define _ACMP_APORTCONFLICT_APORT3YCONFLICT_SHIFT 7 /**< Shift value for ACMP_APORT3YCONFLICT */ #define _ACMP_APORTCONFLICT_APORT3YCONFLICT_MASK 0x80UL /**< Bit mask for ACMP_APORT3YCONFLICT */ #define _ACMP_APORTCONFLICT_APORT3YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTCONFLICT */ #define ACMP_APORTCONFLICT_APORT3YCONFLICT_DEFAULT (_ACMP_APORTCONFLICT_APORT3YCONFLICT_DEFAULT << 7) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */ #define ACMP_APORTCONFLICT_APORT4XCONFLICT (0x1UL << 8) /**< 1 If the Bus Connected to APORT4X is in Conflict With Another Peripheral */ #define _ACMP_APORTCONFLICT_APORT4XCONFLICT_SHIFT 8 /**< Shift value for ACMP_APORT4XCONFLICT */ #define _ACMP_APORTCONFLICT_APORT4XCONFLICT_MASK 0x100UL /**< Bit mask for ACMP_APORT4XCONFLICT */ #define _ACMP_APORTCONFLICT_APORT4XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTCONFLICT */ #define ACMP_APORTCONFLICT_APORT4XCONFLICT_DEFAULT (_ACMP_APORTCONFLICT_APORT4XCONFLICT_DEFAULT << 8) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */ #define ACMP_APORTCONFLICT_APORT4YCONFLICT (0x1UL << 9) /**< 1 If the Bus Connected to APORT4Y is in Conflict With Another Peripheral */ #define _ACMP_APORTCONFLICT_APORT4YCONFLICT_SHIFT 9 /**< Shift value for ACMP_APORT4YCONFLICT */ #define _ACMP_APORTCONFLICT_APORT4YCONFLICT_MASK 0x200UL /**< Bit mask for ACMP_APORT4YCONFLICT */ #define _ACMP_APORTCONFLICT_APORT4YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTCONFLICT */ #define ACMP_APORTCONFLICT_APORT4YCONFLICT_DEFAULT (_ACMP_APORTCONFLICT_APORT4YCONFLICT_DEFAULT << 9) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */ /* Bit fields for ACMP HYSTERESIS0 */ #define _ACMP_HYSTERESIS0_RESETVALUE 0x00000000UL /**< Default value for ACMP_HYSTERESIS0 */ #define _ACMP_HYSTERESIS0_MASK 0x3F3F000FUL /**< Mask for ACMP_HYSTERESIS0 */ #define _ACMP_HYSTERESIS0_HYST_SHIFT 0 /**< Shift value for ACMP_HYST */ #define _ACMP_HYSTERESIS0_HYST_MASK 0xFUL /**< Bit mask for ACMP_HYST */ #define _ACMP_HYSTERESIS0_HYST_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_HYSTERESIS0 */ #define _ACMP_HYSTERESIS0_HYST_HYST0 0x00000000UL /**< Mode HYST0 for ACMP_HYSTERESIS0 */ #define _ACMP_HYSTERESIS0_HYST_HYST1 0x00000001UL /**< Mode HYST1 for ACMP_HYSTERESIS0 */ #define _ACMP_HYSTERESIS0_HYST_HYST2 0x00000002UL /**< Mode HYST2 for ACMP_HYSTERESIS0 */ #define _ACMP_HYSTERESIS0_HYST_HYST3 0x00000003UL /**< Mode HYST3 for ACMP_HYSTERESIS0 */ #define _ACMP_HYSTERESIS0_HYST_HYST4 0x00000004UL /**< Mode HYST4 for ACMP_HYSTERESIS0 */ #define _ACMP_HYSTERESIS0_HYST_HYST5 0x00000005UL /**< Mode HYST5 for ACMP_HYSTERESIS0 */ #define _ACMP_HYSTERESIS0_HYST_HYST6 0x00000006UL /**< Mode HYST6 for ACMP_HYSTERESIS0 */ #define _ACMP_HYSTERESIS0_HYST_HYST7 0x00000007UL /**< Mode HYST7 for ACMP_HYSTERESIS0 */ #define _ACMP_HYSTERESIS0_HYST_HYST8 0x00000008UL /**< Mode HYST8 for ACMP_HYSTERESIS0 */ #define _ACMP_HYSTERESIS0_HYST_HYST9 0x00000009UL /**< Mode HYST9 for ACMP_HYSTERESIS0 */ #define _ACMP_HYSTERESIS0_HYST_HYST10 0x0000000AUL /**< Mode HYST10 for ACMP_HYSTERESIS0 */ #define _ACMP_HYSTERESIS0_HYST_HYST11 0x0000000BUL /**< Mode HYST11 for ACMP_HYSTERESIS0 */ #define _ACMP_HYSTERESIS0_HYST_HYST12 0x0000000CUL /**< Mode HYST12 for ACMP_HYSTERESIS0 */ #define _ACMP_HYSTERESIS0_HYST_HYST13 0x0000000DUL /**< Mode HYST13 for ACMP_HYSTERESIS0 */ #define _ACMP_HYSTERESIS0_HYST_HYST14 0x0000000EUL /**< Mode HYST14 for ACMP_HYSTERESIS0 */ #define _ACMP_HYSTERESIS0_HYST_HYST15 0x0000000FUL /**< Mode HYST15 for ACMP_HYSTERESIS0 */ #define ACMP_HYSTERESIS0_HYST_DEFAULT (_ACMP_HYSTERESIS0_HYST_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_HYSTERESIS0 */ #define ACMP_HYSTERESIS0_HYST_HYST0 (_ACMP_HYSTERESIS0_HYST_HYST0 << 0) /**< Shifted mode HYST0 for ACMP_HYSTERESIS0 */ #define ACMP_HYSTERESIS0_HYST_HYST1 (_ACMP_HYSTERESIS0_HYST_HYST1 << 0) /**< Shifted mode HYST1 for ACMP_HYSTERESIS0 */ #define ACMP_HYSTERESIS0_HYST_HYST2 (_ACMP_HYSTERESIS0_HYST_HYST2 << 0) /**< Shifted mode HYST2 for ACMP_HYSTERESIS0 */ #define ACMP_HYSTERESIS0_HYST_HYST3 (_ACMP_HYSTERESIS0_HYST_HYST3 << 0) /**< Shifted mode HYST3 for ACMP_HYSTERESIS0 */ #define ACMP_HYSTERESIS0_HYST_HYST4 (_ACMP_HYSTERESIS0_HYST_HYST4 << 0) /**< Shifted mode HYST4 for ACMP_HYSTERESIS0 */ #define ACMP_HYSTERESIS0_HYST_HYST5 (_ACMP_HYSTERESIS0_HYST_HYST5 << 0) /**< Shifted mode HYST5 for ACMP_HYSTERESIS0 */ #define ACMP_HYSTERESIS0_HYST_HYST6 (_ACMP_HYSTERESIS0_HYST_HYST6 << 0) /**< Shifted mode HYST6 for ACMP_HYSTERESIS0 */ #define ACMP_HYSTERESIS0_HYST_HYST7 (_ACMP_HYSTERESIS0_HYST_HYST7 << 0) /**< Shifted mode HYST7 for ACMP_HYSTERESIS0 */ #define ACMP_HYSTERESIS0_HYST_HYST8 (_ACMP_HYSTERESIS0_HYST_HYST8 << 0) /**< Shifted mode HYST8 for ACMP_HYSTERESIS0 */ #define ACMP_HYSTERESIS0_HYST_HYST9 (_ACMP_HYSTERESIS0_HYST_HYST9 << 0) /**< Shifted mode HYST9 for ACMP_HYSTERESIS0 */ #define ACMP_HYSTERESIS0_HYST_HYST10 (_ACMP_HYSTERESIS0_HYST_HYST10 << 0) /**< Shifted mode HYST10 for ACMP_HYSTERESIS0 */ #define ACMP_HYSTERESIS0_HYST_HYST11 (_ACMP_HYSTERESIS0_HYST_HYST11 << 0) /**< Shifted mode HYST11 for ACMP_HYSTERESIS0 */ #define ACMP_HYSTERESIS0_HYST_HYST12 (_ACMP_HYSTERESIS0_HYST_HYST12 << 0) /**< Shifted mode HYST12 for ACMP_HYSTERESIS0 */ #define ACMP_HYSTERESIS0_HYST_HYST13 (_ACMP_HYSTERESIS0_HYST_HYST13 << 0) /**< Shifted mode HYST13 for ACMP_HYSTERESIS0 */ #define ACMP_HYSTERESIS0_HYST_HYST14 (_ACMP_HYSTERESIS0_HYST_HYST14 << 0) /**< Shifted mode HYST14 for ACMP_HYSTERESIS0 */ #define ACMP_HYSTERESIS0_HYST_HYST15 (_ACMP_HYSTERESIS0_HYST_HYST15 << 0) /**< Shifted mode HYST15 for ACMP_HYSTERESIS0 */ #define _ACMP_HYSTERESIS0_DIVVA_SHIFT 16 /**< Shift value for ACMP_DIVVA */ #define _ACMP_HYSTERESIS0_DIVVA_MASK 0x3F0000UL /**< Bit mask for ACMP_DIVVA */ #define _ACMP_HYSTERESIS0_DIVVA_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_HYSTERESIS0 */ #define ACMP_HYSTERESIS0_DIVVA_DEFAULT (_ACMP_HYSTERESIS0_DIVVA_DEFAULT << 16) /**< Shifted mode DEFAULT for ACMP_HYSTERESIS0 */ #define _ACMP_HYSTERESIS0_DIVVB_SHIFT 24 /**< Shift value for ACMP_DIVVB */ #define _ACMP_HYSTERESIS0_DIVVB_MASK 0x3F000000UL /**< Bit mask for ACMP_DIVVB */ #define _ACMP_HYSTERESIS0_DIVVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_HYSTERESIS0 */ #define ACMP_HYSTERESIS0_DIVVB_DEFAULT (_ACMP_HYSTERESIS0_DIVVB_DEFAULT << 24) /**< Shifted mode DEFAULT for ACMP_HYSTERESIS0 */ /* Bit fields for ACMP HYSTERESIS1 */ #define _ACMP_HYSTERESIS1_RESETVALUE 0x00000000UL /**< Default value for ACMP_HYSTERESIS1 */ #define _ACMP_HYSTERESIS1_MASK 0x3F3F000FUL /**< Mask for ACMP_HYSTERESIS1 */ #define _ACMP_HYSTERESIS1_HYST_SHIFT 0 /**< Shift value for ACMP_HYST */ #define _ACMP_HYSTERESIS1_HYST_MASK 0xFUL /**< Bit mask for ACMP_HYST */ #define _ACMP_HYSTERESIS1_HYST_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_HYSTERESIS1 */ #define _ACMP_HYSTERESIS1_HYST_HYST0 0x00000000UL /**< Mode HYST0 for ACMP_HYSTERESIS1 */ #define _ACMP_HYSTERESIS1_HYST_HYST1 0x00000001UL /**< Mode HYST1 for ACMP_HYSTERESIS1 */ #define _ACMP_HYSTERESIS1_HYST_HYST2 0x00000002UL /**< Mode HYST2 for ACMP_HYSTERESIS1 */ #define _ACMP_HYSTERESIS1_HYST_HYST3 0x00000003UL /**< Mode HYST3 for ACMP_HYSTERESIS1 */ #define _ACMP_HYSTERESIS1_HYST_HYST4 0x00000004UL /**< Mode HYST4 for ACMP_HYSTERESIS1 */ #define _ACMP_HYSTERESIS1_HYST_HYST5 0x00000005UL /**< Mode HYST5 for ACMP_HYSTERESIS1 */ #define _ACMP_HYSTERESIS1_HYST_HYST6 0x00000006UL /**< Mode HYST6 for ACMP_HYSTERESIS1 */ #define _ACMP_HYSTERESIS1_HYST_HYST7 0x00000007UL /**< Mode HYST7 for ACMP_HYSTERESIS1 */ #define _ACMP_HYSTERESIS1_HYST_HYST8 0x00000008UL /**< Mode HYST8 for ACMP_HYSTERESIS1 */ #define _ACMP_HYSTERESIS1_HYST_HYST9 0x00000009UL /**< Mode HYST9 for ACMP_HYSTERESIS1 */ #define _ACMP_HYSTERESIS1_HYST_HYST10 0x0000000AUL /**< Mode HYST10 for ACMP_HYSTERESIS1 */ #define _ACMP_HYSTERESIS1_HYST_HYST11 0x0000000BUL /**< Mode HYST11 for ACMP_HYSTERESIS1 */ #define _ACMP_HYSTERESIS1_HYST_HYST12 0x0000000CUL /**< Mode HYST12 for ACMP_HYSTERESIS1 */ #define _ACMP_HYSTERESIS1_HYST_HYST13 0x0000000DUL /**< Mode HYST13 for ACMP_HYSTERESIS1 */ #define _ACMP_HYSTERESIS1_HYST_HYST14 0x0000000EUL /**< Mode HYST14 for ACMP_HYSTERESIS1 */ #define _ACMP_HYSTERESIS1_HYST_HYST15 0x0000000FUL /**< Mode HYST15 for ACMP_HYSTERESIS1 */ #define ACMP_HYSTERESIS1_HYST_DEFAULT (_ACMP_HYSTERESIS1_HYST_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_HYSTERESIS1 */ #define ACMP_HYSTERESIS1_HYST_HYST0 (_ACMP_HYSTERESIS1_HYST_HYST0 << 0) /**< Shifted mode HYST0 for ACMP_HYSTERESIS1 */ #define ACMP_HYSTERESIS1_HYST_HYST1 (_ACMP_HYSTERESIS1_HYST_HYST1 << 0) /**< Shifted mode HYST1 for ACMP_HYSTERESIS1 */ #define ACMP_HYSTERESIS1_HYST_HYST2 (_ACMP_HYSTERESIS1_HYST_HYST2 << 0) /**< Shifted mode HYST2 for ACMP_HYSTERESIS1 */ #define ACMP_HYSTERESIS1_HYST_HYST3 (_ACMP_HYSTERESIS1_HYST_HYST3 << 0) /**< Shifted mode HYST3 for ACMP_HYSTERESIS1 */ #define ACMP_HYSTERESIS1_HYST_HYST4 (_ACMP_HYSTERESIS1_HYST_HYST4 << 0) /**< Shifted mode HYST4 for ACMP_HYSTERESIS1 */ #define ACMP_HYSTERESIS1_HYST_HYST5 (_ACMP_HYSTERESIS1_HYST_HYST5 << 0) /**< Shifted mode HYST5 for ACMP_HYSTERESIS1 */ #define ACMP_HYSTERESIS1_HYST_HYST6 (_ACMP_HYSTERESIS1_HYST_HYST6 << 0) /**< Shifted mode HYST6 for ACMP_HYSTERESIS1 */ #define ACMP_HYSTERESIS1_HYST_HYST7 (_ACMP_HYSTERESIS1_HYST_HYST7 << 0) /**< Shifted mode HYST7 for ACMP_HYSTERESIS1 */ #define ACMP_HYSTERESIS1_HYST_HYST8 (_ACMP_HYSTERESIS1_HYST_HYST8 << 0) /**< Shifted mode HYST8 for ACMP_HYSTERESIS1 */ #define ACMP_HYSTERESIS1_HYST_HYST9 (_ACMP_HYSTERESIS1_HYST_HYST9 << 0) /**< Shifted mode HYST9 for ACMP_HYSTERESIS1 */ #define ACMP_HYSTERESIS1_HYST_HYST10 (_ACMP_HYSTERESIS1_HYST_HYST10 << 0) /**< Shifted mode HYST10 for ACMP_HYSTERESIS1 */ #define ACMP_HYSTERESIS1_HYST_HYST11 (_ACMP_HYSTERESIS1_HYST_HYST11 << 0) /**< Shifted mode HYST11 for ACMP_HYSTERESIS1 */ #define ACMP_HYSTERESIS1_HYST_HYST12 (_ACMP_HYSTERESIS1_HYST_HYST12 << 0) /**< Shifted mode HYST12 for ACMP_HYSTERESIS1 */ #define ACMP_HYSTERESIS1_HYST_HYST13 (_ACMP_HYSTERESIS1_HYST_HYST13 << 0) /**< Shifted mode HYST13 for ACMP_HYSTERESIS1 */ #define ACMP_HYSTERESIS1_HYST_HYST14 (_ACMP_HYSTERESIS1_HYST_HYST14 << 0) /**< Shifted mode HYST14 for ACMP_HYSTERESIS1 */ #define ACMP_HYSTERESIS1_HYST_HYST15 (_ACMP_HYSTERESIS1_HYST_HYST15 << 0) /**< Shifted mode HYST15 for ACMP_HYSTERESIS1 */ #define _ACMP_HYSTERESIS1_DIVVA_SHIFT 16 /**< Shift value for ACMP_DIVVA */ #define _ACMP_HYSTERESIS1_DIVVA_MASK 0x3F0000UL /**< Bit mask for ACMP_DIVVA */ #define _ACMP_HYSTERESIS1_DIVVA_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_HYSTERESIS1 */ #define ACMP_HYSTERESIS1_DIVVA_DEFAULT (_ACMP_HYSTERESIS1_DIVVA_DEFAULT << 16) /**< Shifted mode DEFAULT for ACMP_HYSTERESIS1 */ #define _ACMP_HYSTERESIS1_DIVVB_SHIFT 24 /**< Shift value for ACMP_DIVVB */ #define _ACMP_HYSTERESIS1_DIVVB_MASK 0x3F000000UL /**< Bit mask for ACMP_DIVVB */ #define _ACMP_HYSTERESIS1_DIVVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_HYSTERESIS1 */ #define ACMP_HYSTERESIS1_DIVVB_DEFAULT (_ACMP_HYSTERESIS1_DIVVB_DEFAULT << 24) /**< Shifted mode DEFAULT for ACMP_HYSTERESIS1 */ /* Bit fields for ACMP ROUTEPEN */ #define _ACMP_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for ACMP_ROUTEPEN */ #define _ACMP_ROUTEPEN_MASK 0x00000001UL /**< Mask for ACMP_ROUTEPEN */ #define ACMP_ROUTEPEN_OUTPEN (0x1UL << 0) /**< ACMP Output Pin Enable */ #define _ACMP_ROUTEPEN_OUTPEN_SHIFT 0 /**< Shift value for ACMP_OUTPEN */ #define _ACMP_ROUTEPEN_OUTPEN_MASK 0x1UL /**< Bit mask for ACMP_OUTPEN */ #define _ACMP_ROUTEPEN_OUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_ROUTEPEN */ #define ACMP_ROUTEPEN_OUTPEN_DEFAULT (_ACMP_ROUTEPEN_OUTPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_ROUTEPEN */ /* Bit fields for ACMP ROUTELOC0 */ #define _ACMP_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for ACMP_ROUTELOC0 */ #define _ACMP_ROUTELOC0_MASK 0x0000001FUL /**< Mask for ACMP_ROUTELOC0 */ #define _ACMP_ROUTELOC0_OUTLOC_SHIFT 0 /**< Shift value for ACMP_OUTLOC */ #define _ACMP_ROUTELOC0_OUTLOC_MASK 0x1FUL /**< Bit mask for ACMP_OUTLOC */ #define _ACMP_ROUTELOC0_OUTLOC_LOC0 0x00000000UL /**< Mode LOC0 for ACMP_ROUTELOC0 */ #define _ACMP_ROUTELOC0_OUTLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_ROUTELOC0 */ #define _ACMP_ROUTELOC0_OUTLOC_LOC1 0x00000001UL /**< Mode LOC1 for ACMP_ROUTELOC0 */ #define _ACMP_ROUTELOC0_OUTLOC_LOC2 0x00000002UL /**< Mode LOC2 for ACMP_ROUTELOC0 */ #define _ACMP_ROUTELOC0_OUTLOC_LOC3 0x00000003UL /**< Mode LOC3 for ACMP_ROUTELOC0 */ #define _ACMP_ROUTELOC0_OUTLOC_LOC4 0x00000004UL /**< Mode LOC4 for ACMP_ROUTELOC0 */ #define _ACMP_ROUTELOC0_OUTLOC_LOC5 0x00000005UL /**< Mode LOC5 for ACMP_ROUTELOC0 */ #define _ACMP_ROUTELOC0_OUTLOC_LOC6 0x00000006UL /**< Mode LOC6 for ACMP_ROUTELOC0 */ #define _ACMP_ROUTELOC0_OUTLOC_LOC7 0x00000007UL /**< Mode LOC7 for ACMP_ROUTELOC0 */ #define _ACMP_ROUTELOC0_OUTLOC_LOC8 0x00000008UL /**< Mode LOC8 for ACMP_ROUTELOC0 */ #define _ACMP_ROUTELOC0_OUTLOC_LOC9 0x00000009UL /**< Mode LOC9 for ACMP_ROUTELOC0 */ #define _ACMP_ROUTELOC0_OUTLOC_LOC10 0x0000000AUL /**< Mode LOC10 for ACMP_ROUTELOC0 */ #define _ACMP_ROUTELOC0_OUTLOC_LOC11 0x0000000BUL /**< Mode LOC11 for ACMP_ROUTELOC0 */ #define _ACMP_ROUTELOC0_OUTLOC_LOC12 0x0000000CUL /**< Mode LOC12 for ACMP_ROUTELOC0 */ #define _ACMP_ROUTELOC0_OUTLOC_LOC13 0x0000000DUL /**< Mode LOC13 for ACMP_ROUTELOC0 */ #define _ACMP_ROUTELOC0_OUTLOC_LOC14 0x0000000EUL /**< Mode LOC14 for ACMP_ROUTELOC0 */ #define _ACMP_ROUTELOC0_OUTLOC_LOC15 0x0000000FUL /**< Mode LOC15 for ACMP_ROUTELOC0 */ #define _ACMP_ROUTELOC0_OUTLOC_LOC16 0x00000010UL /**< Mode LOC16 for ACMP_ROUTELOC0 */ #define _ACMP_ROUTELOC0_OUTLOC_LOC17 0x00000011UL /**< Mode LOC17 for ACMP_ROUTELOC0 */ #define _ACMP_ROUTELOC0_OUTLOC_LOC18 0x00000012UL /**< Mode LOC18 for ACMP_ROUTELOC0 */ #define _ACMP_ROUTELOC0_OUTLOC_LOC19 0x00000013UL /**< Mode LOC19 for ACMP_ROUTELOC0 */ #define _ACMP_ROUTELOC0_OUTLOC_LOC20 0x00000014UL /**< Mode LOC20 for ACMP_ROUTELOC0 */ #define _ACMP_ROUTELOC0_OUTLOC_LOC21 0x00000015UL /**< Mode LOC21 for ACMP_ROUTELOC0 */ #define _ACMP_ROUTELOC0_OUTLOC_LOC22 0x00000016UL /**< Mode LOC22 for ACMP_ROUTELOC0 */ #define _ACMP_ROUTELOC0_OUTLOC_LOC23 0x00000017UL /**< Mode LOC23 for ACMP_ROUTELOC0 */ #define _ACMP_ROUTELOC0_OUTLOC_LOC24 0x00000018UL /**< Mode LOC24 for ACMP_ROUTELOC0 */ #define _ACMP_ROUTELOC0_OUTLOC_LOC25 0x00000019UL /**< Mode LOC25 for ACMP_ROUTELOC0 */ #define _ACMP_ROUTELOC0_OUTLOC_LOC26 0x0000001AUL /**< Mode LOC26 for ACMP_ROUTELOC0 */ #define _ACMP_ROUTELOC0_OUTLOC_LOC27 0x0000001BUL /**< Mode LOC27 for ACMP_ROUTELOC0 */ #define _ACMP_ROUTELOC0_OUTLOC_LOC28 0x0000001CUL /**< Mode LOC28 for ACMP_ROUTELOC0 */ #define _ACMP_ROUTELOC0_OUTLOC_LOC29 0x0000001DUL /**< Mode LOC29 for ACMP_ROUTELOC0 */ #define _ACMP_ROUTELOC0_OUTLOC_LOC30 0x0000001EUL /**< Mode LOC30 for ACMP_ROUTELOC0 */ #define _ACMP_ROUTELOC0_OUTLOC_LOC31 0x0000001FUL /**< Mode LOC31 for ACMP_ROUTELOC0 */ #define ACMP_ROUTELOC0_OUTLOC_LOC0 (_ACMP_ROUTELOC0_OUTLOC_LOC0 << 0) /**< Shifted mode LOC0 for ACMP_ROUTELOC0 */ #define ACMP_ROUTELOC0_OUTLOC_DEFAULT (_ACMP_ROUTELOC0_OUTLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_ROUTELOC0 */ #define ACMP_ROUTELOC0_OUTLOC_LOC1 (_ACMP_ROUTELOC0_OUTLOC_LOC1 << 0) /**< Shifted mode LOC1 for ACMP_ROUTELOC0 */ #define ACMP_ROUTELOC0_OUTLOC_LOC2 (_ACMP_ROUTELOC0_OUTLOC_LOC2 << 0) /**< Shifted mode LOC2 for ACMP_ROUTELOC0 */ #define ACMP_ROUTELOC0_OUTLOC_LOC3 (_ACMP_ROUTELOC0_OUTLOC_LOC3 << 0) /**< Shifted mode LOC3 for ACMP_ROUTELOC0 */ #define ACMP_ROUTELOC0_OUTLOC_LOC4 (_ACMP_ROUTELOC0_OUTLOC_LOC4 << 0) /**< Shifted mode LOC4 for ACMP_ROUTELOC0 */ #define ACMP_ROUTELOC0_OUTLOC_LOC5 (_ACMP_ROUTELOC0_OUTLOC_LOC5 << 0) /**< Shifted mode LOC5 for ACMP_ROUTELOC0 */ #define ACMP_ROUTELOC0_OUTLOC_LOC6 (_ACMP_ROUTELOC0_OUTLOC_LOC6 << 0) /**< Shifted mode LOC6 for ACMP_ROUTELOC0 */ #define ACMP_ROUTELOC0_OUTLOC_LOC7 (_ACMP_ROUTELOC0_OUTLOC_LOC7 << 0) /**< Shifted mode LOC7 for ACMP_ROUTELOC0 */ #define ACMP_ROUTELOC0_OUTLOC_LOC8 (_ACMP_ROUTELOC0_OUTLOC_LOC8 << 0) /**< Shifted mode LOC8 for ACMP_ROUTELOC0 */ #define ACMP_ROUTELOC0_OUTLOC_LOC9 (_ACMP_ROUTELOC0_OUTLOC_LOC9 << 0) /**< Shifted mode LOC9 for ACMP_ROUTELOC0 */ #define ACMP_ROUTELOC0_OUTLOC_LOC10 (_ACMP_ROUTELOC0_OUTLOC_LOC10 << 0) /**< Shifted mode LOC10 for ACMP_ROUTELOC0 */ #define ACMP_ROUTELOC0_OUTLOC_LOC11 (_ACMP_ROUTELOC0_OUTLOC_LOC11 << 0) /**< Shifted mode LOC11 for ACMP_ROUTELOC0 */ #define ACMP_ROUTELOC0_OUTLOC_LOC12 (_ACMP_ROUTELOC0_OUTLOC_LOC12 << 0) /**< Shifted mode LOC12 for ACMP_ROUTELOC0 */ #define ACMP_ROUTELOC0_OUTLOC_LOC13 (_ACMP_ROUTELOC0_OUTLOC_LOC13 << 0) /**< Shifted mode LOC13 for ACMP_ROUTELOC0 */ #define ACMP_ROUTELOC0_OUTLOC_LOC14 (_ACMP_ROUTELOC0_OUTLOC_LOC14 << 0) /**< Shifted mode LOC14 for ACMP_ROUTELOC0 */ #define ACMP_ROUTELOC0_OUTLOC_LOC15 (_ACMP_ROUTELOC0_OUTLOC_LOC15 << 0) /**< Shifted mode LOC15 for ACMP_ROUTELOC0 */ #define ACMP_ROUTELOC0_OUTLOC_LOC16 (_ACMP_ROUTELOC0_OUTLOC_LOC16 << 0) /**< Shifted mode LOC16 for ACMP_ROUTELOC0 */ #define ACMP_ROUTELOC0_OUTLOC_LOC17 (_ACMP_ROUTELOC0_OUTLOC_LOC17 << 0) /**< Shifted mode LOC17 for ACMP_ROUTELOC0 */ #define ACMP_ROUTELOC0_OUTLOC_LOC18 (_ACMP_ROUTELOC0_OUTLOC_LOC18 << 0) /**< Shifted mode LOC18 for ACMP_ROUTELOC0 */ #define ACMP_ROUTELOC0_OUTLOC_LOC19 (_ACMP_ROUTELOC0_OUTLOC_LOC19 << 0) /**< Shifted mode LOC19 for ACMP_ROUTELOC0 */ #define ACMP_ROUTELOC0_OUTLOC_LOC20 (_ACMP_ROUTELOC0_OUTLOC_LOC20 << 0) /**< Shifted mode LOC20 for ACMP_ROUTELOC0 */ #define ACMP_ROUTELOC0_OUTLOC_LOC21 (_ACMP_ROUTELOC0_OUTLOC_LOC21 << 0) /**< Shifted mode LOC21 for ACMP_ROUTELOC0 */ #define ACMP_ROUTELOC0_OUTLOC_LOC22 (_ACMP_ROUTELOC0_OUTLOC_LOC22 << 0) /**< Shifted mode LOC22 for ACMP_ROUTELOC0 */ #define ACMP_ROUTELOC0_OUTLOC_LOC23 (_ACMP_ROUTELOC0_OUTLOC_LOC23 << 0) /**< Shifted mode LOC23 for ACMP_ROUTELOC0 */ #define ACMP_ROUTELOC0_OUTLOC_LOC24 (_ACMP_ROUTELOC0_OUTLOC_LOC24 << 0) /**< Shifted mode LOC24 for ACMP_ROUTELOC0 */ #define ACMP_ROUTELOC0_OUTLOC_LOC25 (_ACMP_ROUTELOC0_OUTLOC_LOC25 << 0) /**< Shifted mode LOC25 for ACMP_ROUTELOC0 */ #define ACMP_ROUTELOC0_OUTLOC_LOC26 (_ACMP_ROUTELOC0_OUTLOC_LOC26 << 0) /**< Shifted mode LOC26 for ACMP_ROUTELOC0 */ #define ACMP_ROUTELOC0_OUTLOC_LOC27 (_ACMP_ROUTELOC0_OUTLOC_LOC27 << 0) /**< Shifted mode LOC27 for ACMP_ROUTELOC0 */ #define ACMP_ROUTELOC0_OUTLOC_LOC28 (_ACMP_ROUTELOC0_OUTLOC_LOC28 << 0) /**< Shifted mode LOC28 for ACMP_ROUTELOC0 */ #define ACMP_ROUTELOC0_OUTLOC_LOC29 (_ACMP_ROUTELOC0_OUTLOC_LOC29 << 0) /**< Shifted mode LOC29 for ACMP_ROUTELOC0 */ #define ACMP_ROUTELOC0_OUTLOC_LOC30 (_ACMP_ROUTELOC0_OUTLOC_LOC30 << 0) /**< Shifted mode LOC30 for ACMP_ROUTELOC0 */ #define ACMP_ROUTELOC0_OUTLOC_LOC31 (_ACMP_ROUTELOC0_OUTLOC_LOC31 << 0) /**< Shifted mode LOC31 for ACMP_ROUTELOC0 */ /* Bit fields for ACMP EXTIFCTRL */ #define _ACMP_EXTIFCTRL_RESETVALUE 0x00000000UL /**< Default value for ACMP_EXTIFCTRL */ #define _ACMP_EXTIFCTRL_MASK 0x000000F1UL /**< Mask for ACMP_EXTIFCTRL */ #define ACMP_EXTIFCTRL_EN (0x1UL << 0) /**< Enable External Interface */ #define _ACMP_EXTIFCTRL_EN_SHIFT 0 /**< Shift value for ACMP_EN */ #define _ACMP_EXTIFCTRL_EN_MASK 0x1UL /**< Bit mask for ACMP_EN */ #define _ACMP_EXTIFCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_EXTIFCTRL */ #define ACMP_EXTIFCTRL_EN_DEFAULT (_ACMP_EXTIFCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_EXTIFCTRL */ #define _ACMP_EXTIFCTRL_APORTSEL_SHIFT 4 /**< Shift value for ACMP_APORTSEL */ #define _ACMP_EXTIFCTRL_APORTSEL_MASK 0xF0UL /**< Bit mask for ACMP_APORTSEL */ #define _ACMP_EXTIFCTRL_APORTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_EXTIFCTRL */ #define _ACMP_EXTIFCTRL_APORTSEL_APORT0X 0x00000000UL /**< Mode APORT0X for ACMP_EXTIFCTRL */ #define _ACMP_EXTIFCTRL_APORTSEL_APORT0Y 0x00000001UL /**< Mode APORT0Y for ACMP_EXTIFCTRL */ #define _ACMP_EXTIFCTRL_APORTSEL_APORT1X 0x00000002UL /**< Mode APORT1X for ACMP_EXTIFCTRL */ #define _ACMP_EXTIFCTRL_APORTSEL_APORT1Y 0x00000003UL /**< Mode APORT1Y for ACMP_EXTIFCTRL */ #define _ACMP_EXTIFCTRL_APORTSEL_APORT1XY 0x00000004UL /**< Mode APORT1XY for ACMP_EXTIFCTRL */ #define _ACMP_EXTIFCTRL_APORTSEL_APORT2X 0x00000005UL /**< Mode APORT2X for ACMP_EXTIFCTRL */ #define _ACMP_EXTIFCTRL_APORTSEL_APORT2Y 0x00000006UL /**< Mode APORT2Y for ACMP_EXTIFCTRL */ #define _ACMP_EXTIFCTRL_APORTSEL_APORT2YX 0x00000007UL /**< Mode APORT2YX for ACMP_EXTIFCTRL */ #define _ACMP_EXTIFCTRL_APORTSEL_APORT3X 0x00000008UL /**< Mode APORT3X for ACMP_EXTIFCTRL */ #define _ACMP_EXTIFCTRL_APORTSEL_APORT3Y 0x00000009UL /**< Mode APORT3Y for ACMP_EXTIFCTRL */ #define _ACMP_EXTIFCTRL_APORTSEL_APORT3XY 0x0000000AUL /**< Mode APORT3XY for ACMP_EXTIFCTRL */ #define _ACMP_EXTIFCTRL_APORTSEL_APORT4X 0x0000000BUL /**< Mode APORT4X for ACMP_EXTIFCTRL */ #define _ACMP_EXTIFCTRL_APORTSEL_APORT4Y 0x0000000CUL /**< Mode APORT4Y for ACMP_EXTIFCTRL */ #define _ACMP_EXTIFCTRL_APORTSEL_APORT4YX 0x0000000DUL /**< Mode APORT4YX for ACMP_EXTIFCTRL */ #define ACMP_EXTIFCTRL_APORTSEL_DEFAULT (_ACMP_EXTIFCTRL_APORTSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for ACMP_EXTIFCTRL */ #define ACMP_EXTIFCTRL_APORTSEL_APORT0X (_ACMP_EXTIFCTRL_APORTSEL_APORT0X << 4) /**< Shifted mode APORT0X for ACMP_EXTIFCTRL */ #define ACMP_EXTIFCTRL_APORTSEL_APORT0Y (_ACMP_EXTIFCTRL_APORTSEL_APORT0Y << 4) /**< Shifted mode APORT0Y for ACMP_EXTIFCTRL */ #define ACMP_EXTIFCTRL_APORTSEL_APORT1X (_ACMP_EXTIFCTRL_APORTSEL_APORT1X << 4) /**< Shifted mode APORT1X for ACMP_EXTIFCTRL */ #define ACMP_EXTIFCTRL_APORTSEL_APORT1Y (_ACMP_EXTIFCTRL_APORTSEL_APORT1Y << 4) /**< Shifted mode APORT1Y for ACMP_EXTIFCTRL */ #define ACMP_EXTIFCTRL_APORTSEL_APORT1XY (_ACMP_EXTIFCTRL_APORTSEL_APORT1XY << 4) /**< Shifted mode APORT1XY for ACMP_EXTIFCTRL */ #define ACMP_EXTIFCTRL_APORTSEL_APORT2X (_ACMP_EXTIFCTRL_APORTSEL_APORT2X << 4) /**< Shifted mode APORT2X for ACMP_EXTIFCTRL */ #define ACMP_EXTIFCTRL_APORTSEL_APORT2Y (_ACMP_EXTIFCTRL_APORTSEL_APORT2Y << 4) /**< Shifted mode APORT2Y for ACMP_EXTIFCTRL */ #define ACMP_EXTIFCTRL_APORTSEL_APORT2YX (_ACMP_EXTIFCTRL_APORTSEL_APORT2YX << 4) /**< Shifted mode APORT2YX for ACMP_EXTIFCTRL */ #define ACMP_EXTIFCTRL_APORTSEL_APORT3X (_ACMP_EXTIFCTRL_APORTSEL_APORT3X << 4) /**< Shifted mode APORT3X for ACMP_EXTIFCTRL */ #define ACMP_EXTIFCTRL_APORTSEL_APORT3Y (_ACMP_EXTIFCTRL_APORTSEL_APORT3Y << 4) /**< Shifted mode APORT3Y for ACMP_EXTIFCTRL */ #define ACMP_EXTIFCTRL_APORTSEL_APORT3XY (_ACMP_EXTIFCTRL_APORTSEL_APORT3XY << 4) /**< Shifted mode APORT3XY for ACMP_EXTIFCTRL */ #define ACMP_EXTIFCTRL_APORTSEL_APORT4X (_ACMP_EXTIFCTRL_APORTSEL_APORT4X << 4) /**< Shifted mode APORT4X for ACMP_EXTIFCTRL */ #define ACMP_EXTIFCTRL_APORTSEL_APORT4Y (_ACMP_EXTIFCTRL_APORTSEL_APORT4Y << 4) /**< Shifted mode APORT4Y for ACMP_EXTIFCTRL */ #define ACMP_EXTIFCTRL_APORTSEL_APORT4YX (_ACMP_EXTIFCTRL_APORTSEL_APORT4YX << 4) /**< Shifted mode APORT4YX for ACMP_EXTIFCTRL */ /** @} */ /** @} End of group EFR32MG12P_ACMP */ /** @} End of group Parts */ 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Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_adc.h.
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/***************************************************************************//** * @file * @brief EFR32MG12P_ADC register and bit field definitions * @version 5.7.0 ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * SPDX-License-Identifier: Zlib * * The licensor of this software is Silicon Laboratories Inc. * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be * appreciated but is not required. * 2. Altered source versions must be plainly marked as such, and must not be * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * ******************************************************************************/ #if defined(__ICCARM__) #pragma system_include /* Treat file as system include file. */ #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang system_header /* Treat file as system include file. */ #endif /***************************************************************************//** * @addtogroup Parts * @{ ******************************************************************************/ /***************************************************************************//** * @defgroup EFR32MG12P_ADC ADC * @{ * @brief EFR32MG12P_ADC Register Declaration ******************************************************************************/ /** ADC Register Declaration */ typedef struct { __IOM uint32_t CTRL; /**< Control Register */ uint32_t RESERVED0[1U]; /**< Reserved for future use **/ __IOM uint32_t CMD; /**< Command Register */ __IM uint32_t STATUS; /**< Status Register */ __IOM uint32_t SINGLECTRL; /**< Single Channel Control Register */ __IOM uint32_t SINGLECTRLX; /**< Single Channel Control Register Continued */ __IOM uint32_t SCANCTRL; /**< Scan Control Register */ __IOM uint32_t SCANCTRLX; /**< Scan Control Register Continued */ __IOM uint32_t SCANMASK; /**< Scan Sequence Input Mask Register */ __IOM uint32_t SCANINPUTSEL; /**< Input Selection Register for Scan Mode */ __IOM uint32_t SCANNEGSEL; /**< Negative Input Select Register for Scan */ __IOM uint32_t CMPTHR; /**< Compare Threshold Register */ __IOM uint32_t BIASPROG; /**< Bias Programming Register for Various Analog Blocks Used in ADC Operation */ __IOM uint32_t CAL; /**< Calibration Register */ __IM uint32_t IF; /**< Interrupt Flag Register */ __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ __IOM uint32_t IEN; /**< Interrupt Enable Register */ __IM uint32_t SINGLEDATA; /**< Single Conversion Result Data */ __IM uint32_t SCANDATA; /**< Scan Conversion Result Data */ __IM uint32_t SINGLEDATAP; /**< Single Conversion Result Data Peek Register */ __IM uint32_t SCANDATAP; /**< Scan Sequence Result Data Peek Register */ uint32_t RESERVED1[4U]; /**< Reserved for future use **/ __IM uint32_t SCANDATAX; /**< Scan Sequence Result Data + Data Source Register */ __IM uint32_t SCANDATAXP; /**< Scan Sequence Result Data + Data Source Peek Register */ uint32_t RESERVED2[3U]; /**< Reserved for future use **/ __IM uint32_t APORTREQ; /**< APORT Request Status Register */ __IM uint32_t APORTCONFLICT; /**< APORT Conflict Status Register */ __IM uint32_t SINGLEFIFOCOUNT; /**< Single FIFO Count Register */ __IM uint32_t SCANFIFOCOUNT; /**< Scan FIFO Count Register */ __IOM uint32_t SINGLEFIFOCLEAR; /**< Single FIFO Clear Register */ __IOM uint32_t SCANFIFOCLEAR; /**< Scan FIFO Clear Register */ __IOM uint32_t APORTMASTERDIS; /**< APORT Bus Master Disable Register */ } ADC_TypeDef; /** @} */ /***************************************************************************//** * @addtogroup EFR32MG12P_ADC * @{ * @defgroup EFR32MG12P_ADC_BitFields ADC Bit Fields * @{ ******************************************************************************/ /* Bit fields for ADC CTRL */ #define _ADC_CTRL_RESETVALUE 0x001F0000UL /**< Default value for ADC_CTRL */ #define _ADC_CTRL_MASK 0xFF7F7FDFUL /**< Mask for ADC_CTRL */ #define _ADC_CTRL_WARMUPMODE_SHIFT 0 /**< Shift value for ADC_WARMUPMODE */ #define _ADC_CTRL_WARMUPMODE_MASK 0x3UL /**< Bit mask for ADC_WARMUPMODE */ #define _ADC_CTRL_WARMUPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */ #define _ADC_CTRL_WARMUPMODE_NORMAL 0x00000000UL /**< Mode NORMAL for ADC_CTRL */ #define _ADC_CTRL_WARMUPMODE_KEEPINSTANDBY 0x00000001UL /**< Mode KEEPINSTANDBY for ADC_CTRL */ #define _ADC_CTRL_WARMUPMODE_KEEPINSLOWACC 0x00000002UL /**< Mode KEEPINSLOWACC for ADC_CTRL */ #define _ADC_CTRL_WARMUPMODE_KEEPADCWARM 0x00000003UL /**< Mode KEEPADCWARM for ADC_CTRL */ #define ADC_CTRL_WARMUPMODE_DEFAULT (_ADC_CTRL_WARMUPMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_CTRL */ #define ADC_CTRL_WARMUPMODE_NORMAL (_ADC_CTRL_WARMUPMODE_NORMAL << 0) /**< Shifted mode NORMAL for ADC_CTRL */ #define ADC_CTRL_WARMUPMODE_KEEPINSTANDBY (_ADC_CTRL_WARMUPMODE_KEEPINSTANDBY << 0) /**< Shifted mode KEEPINSTANDBY for ADC_CTRL */ #define ADC_CTRL_WARMUPMODE_KEEPINSLOWACC (_ADC_CTRL_WARMUPMODE_KEEPINSLOWACC << 0) /**< Shifted mode KEEPINSLOWACC for ADC_CTRL */ #define ADC_CTRL_WARMUPMODE_KEEPADCWARM (_ADC_CTRL_WARMUPMODE_KEEPADCWARM << 0) /**< Shifted mode KEEPADCWARM for ADC_CTRL */ #define ADC_CTRL_SINGLEDMAWU (0x1UL << 2) /**< SINGLEFIFO DMA Wakeup */ #define _ADC_CTRL_SINGLEDMAWU_SHIFT 2 /**< Shift value for ADC_SINGLEDMAWU */ #define _ADC_CTRL_SINGLEDMAWU_MASK 0x4UL /**< Bit mask for ADC_SINGLEDMAWU */ #define _ADC_CTRL_SINGLEDMAWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */ #define ADC_CTRL_SINGLEDMAWU_DEFAULT (_ADC_CTRL_SINGLEDMAWU_DEFAULT << 2) /**< Shifted mode DEFAULT for ADC_CTRL */ #define ADC_CTRL_SCANDMAWU (0x1UL << 3) /**< SCANFIFO DMA Wakeup */ #define _ADC_CTRL_SCANDMAWU_SHIFT 3 /**< Shift value for ADC_SCANDMAWU */ #define _ADC_CTRL_SCANDMAWU_MASK 0x8UL /**< Bit mask for ADC_SCANDMAWU */ #define _ADC_CTRL_SCANDMAWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */ #define ADC_CTRL_SCANDMAWU_DEFAULT (_ADC_CTRL_SCANDMAWU_DEFAULT << 3) /**< Shifted mode DEFAULT for ADC_CTRL */ #define ADC_CTRL_TAILGATE (0x1UL << 4) /**< Conversion Tailgating */ #define _ADC_CTRL_TAILGATE_SHIFT 4 /**< Shift value for ADC_TAILGATE */ #define _ADC_CTRL_TAILGATE_MASK 0x10UL /**< Bit mask for ADC_TAILGATE */ #define _ADC_CTRL_TAILGATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */ #define ADC_CTRL_TAILGATE_DEFAULT (_ADC_CTRL_TAILGATE_DEFAULT << 4) /**< Shifted mode DEFAULT for ADC_CTRL */ #define ADC_CTRL_ASYNCCLKEN (0x1UL << 6) /**< Selects ASYNC CLK Enable Mode When ADCCLKMODE=1 */ #define _ADC_CTRL_ASYNCCLKEN_SHIFT 6 /**< Shift value for ADC_ASYNCCLKEN */ #define _ADC_CTRL_ASYNCCLKEN_MASK 0x40UL /**< Bit mask for ADC_ASYNCCLKEN */ #define _ADC_CTRL_ASYNCCLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */ #define _ADC_CTRL_ASYNCCLKEN_ASNEEDED 0x00000000UL /**< Mode ASNEEDED for ADC_CTRL */ #define _ADC_CTRL_ASYNCCLKEN_ALWAYSON 0x00000001UL /**< Mode ALWAYSON for ADC_CTRL */ #define ADC_CTRL_ASYNCCLKEN_DEFAULT (_ADC_CTRL_ASYNCCLKEN_DEFAULT << 6) /**< Shifted mode DEFAULT for ADC_CTRL */ #define ADC_CTRL_ASYNCCLKEN_ASNEEDED (_ADC_CTRL_ASYNCCLKEN_ASNEEDED << 6) /**< Shifted mode ASNEEDED for ADC_CTRL */ #define ADC_CTRL_ASYNCCLKEN_ALWAYSON (_ADC_CTRL_ASYNCCLKEN_ALWAYSON << 6) /**< Shifted mode ALWAYSON for ADC_CTRL */ #define ADC_CTRL_ADCCLKMODE (0x1UL << 7) /**< ADC Clock Mode */ #define _ADC_CTRL_ADCCLKMODE_SHIFT 7 /**< Shift value for ADC_ADCCLKMODE */ #define _ADC_CTRL_ADCCLKMODE_MASK 0x80UL /**< Bit mask for ADC_ADCCLKMODE */ #define _ADC_CTRL_ADCCLKMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */ #define _ADC_CTRL_ADCCLKMODE_SYNC 0x00000000UL /**< Mode SYNC for ADC_CTRL */ #define _ADC_CTRL_ADCCLKMODE_ASYNC 0x00000001UL /**< Mode ASYNC for ADC_CTRL */ #define ADC_CTRL_ADCCLKMODE_DEFAULT (_ADC_CTRL_ADCCLKMODE_DEFAULT << 7) /**< Shifted mode DEFAULT for ADC_CTRL */ #define ADC_CTRL_ADCCLKMODE_SYNC (_ADC_CTRL_ADCCLKMODE_SYNC << 7) /**< Shifted mode SYNC for ADC_CTRL */ #define ADC_CTRL_ADCCLKMODE_ASYNC (_ADC_CTRL_ADCCLKMODE_ASYNC << 7) /**< Shifted mode ASYNC for ADC_CTRL */ #define _ADC_CTRL_PRESC_SHIFT 8 /**< Shift value for ADC_PRESC */ #define _ADC_CTRL_PRESC_MASK 0x7F00UL /**< Bit mask for ADC_PRESC */ #define _ADC_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */ #define _ADC_CTRL_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for ADC_CTRL */ #define ADC_CTRL_PRESC_DEFAULT (_ADC_CTRL_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_CTRL */ #define ADC_CTRL_PRESC_NODIVISION (_ADC_CTRL_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for ADC_CTRL */ #define _ADC_CTRL_TIMEBASE_SHIFT 16 /**< Shift value for ADC_TIMEBASE */ #define _ADC_CTRL_TIMEBASE_MASK 0x7F0000UL /**< Bit mask for ADC_TIMEBASE */ #define _ADC_CTRL_TIMEBASE_DEFAULT 0x0000001FUL /**< Mode DEFAULT for ADC_CTRL */ #define ADC_CTRL_TIMEBASE_DEFAULT (_ADC_CTRL_TIMEBASE_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_CTRL */ #define _ADC_CTRL_OVSRSEL_SHIFT 24 /**< Shift value for ADC_OVSRSEL */ #define _ADC_CTRL_OVSRSEL_MASK 0xF000000UL /**< Bit mask for ADC_OVSRSEL */ #define _ADC_CTRL_OVSRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */ #define _ADC_CTRL_OVSRSEL_X2 0x00000000UL /**< Mode X2 for ADC_CTRL */ #define _ADC_CTRL_OVSRSEL_X4 0x00000001UL /**< Mode X4 for ADC_CTRL */ #define _ADC_CTRL_OVSRSEL_X8 0x00000002UL /**< Mode X8 for ADC_CTRL */ #define _ADC_CTRL_OVSRSEL_X16 0x00000003UL /**< Mode X16 for ADC_CTRL */ #define _ADC_CTRL_OVSRSEL_X32 0x00000004UL /**< Mode X32 for ADC_CTRL */ #define _ADC_CTRL_OVSRSEL_X64 0x00000005UL /**< Mode X64 for ADC_CTRL */ #define _ADC_CTRL_OVSRSEL_X128 0x00000006UL /**< Mode X128 for ADC_CTRL */ #define _ADC_CTRL_OVSRSEL_X256 0x00000007UL /**< Mode X256 for ADC_CTRL */ #define _ADC_CTRL_OVSRSEL_X512 0x00000008UL /**< Mode X512 for ADC_CTRL */ #define _ADC_CTRL_OVSRSEL_X1024 0x00000009UL /**< Mode X1024 for ADC_CTRL */ #define _ADC_CTRL_OVSRSEL_X2048 0x0000000AUL /**< Mode X2048 for ADC_CTRL */ #define _ADC_CTRL_OVSRSEL_X4096 0x0000000BUL /**< Mode X4096 for ADC_CTRL */ #define ADC_CTRL_OVSRSEL_DEFAULT (_ADC_CTRL_OVSRSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_CTRL */ #define ADC_CTRL_OVSRSEL_X2 (_ADC_CTRL_OVSRSEL_X2 << 24) /**< Shifted mode X2 for ADC_CTRL */ #define ADC_CTRL_OVSRSEL_X4 (_ADC_CTRL_OVSRSEL_X4 << 24) /**< Shifted mode X4 for ADC_CTRL */ #define ADC_CTRL_OVSRSEL_X8 (_ADC_CTRL_OVSRSEL_X8 << 24) /**< Shifted mode X8 for ADC_CTRL */ #define ADC_CTRL_OVSRSEL_X16 (_ADC_CTRL_OVSRSEL_X16 << 24) /**< Shifted mode X16 for ADC_CTRL */ #define ADC_CTRL_OVSRSEL_X32 (_ADC_CTRL_OVSRSEL_X32 << 24) /**< Shifted mode X32 for ADC_CTRL */ #define ADC_CTRL_OVSRSEL_X64 (_ADC_CTRL_OVSRSEL_X64 << 24) /**< Shifted mode X64 for ADC_CTRL */ #define ADC_CTRL_OVSRSEL_X128 (_ADC_CTRL_OVSRSEL_X128 << 24) /**< Shifted mode X128 for ADC_CTRL */ #define ADC_CTRL_OVSRSEL_X256 (_ADC_CTRL_OVSRSEL_X256 << 24) /**< Shifted mode X256 for ADC_CTRL */ #define ADC_CTRL_OVSRSEL_X512 (_ADC_CTRL_OVSRSEL_X512 << 24) /**< Shifted mode X512 for ADC_CTRL */ #define ADC_CTRL_OVSRSEL_X1024 (_ADC_CTRL_OVSRSEL_X1024 << 24) /**< Shifted mode X1024 for ADC_CTRL */ #define ADC_CTRL_OVSRSEL_X2048 (_ADC_CTRL_OVSRSEL_X2048 << 24) /**< Shifted mode X2048 for ADC_CTRL */ #define ADC_CTRL_OVSRSEL_X4096 (_ADC_CTRL_OVSRSEL_X4096 << 24) /**< Shifted mode X4096 for ADC_CTRL */ #define ADC_CTRL_DBGHALT (0x1UL << 28) /**< Debug Mode Halt Enable */ #define _ADC_CTRL_DBGHALT_SHIFT 28 /**< Shift value for ADC_DBGHALT */ #define _ADC_CTRL_DBGHALT_MASK 0x10000000UL /**< Bit mask for ADC_DBGHALT */ #define _ADC_CTRL_DBGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */ #define ADC_CTRL_DBGHALT_DEFAULT (_ADC_CTRL_DBGHALT_DEFAULT << 28) /**< Shifted mode DEFAULT for ADC_CTRL */ #define ADC_CTRL_CHCONMODE (0x1UL << 29) /**< Channel Connect */ #define _ADC_CTRL_CHCONMODE_SHIFT 29 /**< Shift value for ADC_CHCONMODE */ #define _ADC_CTRL_CHCONMODE_MASK 0x20000000UL /**< Bit mask for ADC_CHCONMODE */ #define _ADC_CTRL_CHCONMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */ #define _ADC_CTRL_CHCONMODE_MAXSETTLE 0x00000000UL /**< Mode MAXSETTLE for ADC_CTRL */ #define _ADC_CTRL_CHCONMODE_MAXRESP 0x00000001UL /**< Mode MAXRESP for ADC_CTRL */ #define ADC_CTRL_CHCONMODE_DEFAULT (_ADC_CTRL_CHCONMODE_DEFAULT << 29) /**< Shifted mode DEFAULT for ADC_CTRL */ #define ADC_CTRL_CHCONMODE_MAXSETTLE (_ADC_CTRL_CHCONMODE_MAXSETTLE << 29) /**< Shifted mode MAXSETTLE for ADC_CTRL */ #define ADC_CTRL_CHCONMODE_MAXRESP (_ADC_CTRL_CHCONMODE_MAXRESP << 29) /**< Shifted mode MAXRESP for ADC_CTRL */ #define _ADC_CTRL_CHCONREFWARMIDLE_SHIFT 30 /**< Shift value for ADC_CHCONREFWARMIDLE */ #define _ADC_CTRL_CHCONREFWARMIDLE_MASK 0xC0000000UL /**< Bit mask for ADC_CHCONREFWARMIDLE */ #define _ADC_CTRL_CHCONREFWARMIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */ #define _ADC_CTRL_CHCONREFWARMIDLE_PREFSCAN 0x00000000UL /**< Mode PREFSCAN for ADC_CTRL */ #define _ADC_CTRL_CHCONREFWARMIDLE_PREFSINGLE 0x00000001UL /**< Mode PREFSINGLE for ADC_CTRL */ #define _ADC_CTRL_CHCONREFWARMIDLE_KEEPPREV 0x00000002UL /**< Mode KEEPPREV for ADC_CTRL */ #define ADC_CTRL_CHCONREFWARMIDLE_DEFAULT (_ADC_CTRL_CHCONREFWARMIDLE_DEFAULT << 30) /**< Shifted mode DEFAULT for ADC_CTRL */ #define ADC_CTRL_CHCONREFWARMIDLE_PREFSCAN (_ADC_CTRL_CHCONREFWARMIDLE_PREFSCAN << 30) /**< Shifted mode PREFSCAN for ADC_CTRL */ #define ADC_CTRL_CHCONREFWARMIDLE_PREFSINGLE (_ADC_CTRL_CHCONREFWARMIDLE_PREFSINGLE << 30) /**< Shifted mode PREFSINGLE for ADC_CTRL */ #define ADC_CTRL_CHCONREFWARMIDLE_KEEPPREV (_ADC_CTRL_CHCONREFWARMIDLE_KEEPPREV << 30) /**< Shifted mode KEEPPREV for ADC_CTRL */ /* Bit fields for ADC CMD */ #define _ADC_CMD_RESETVALUE 0x00000000UL /**< Default value for ADC_CMD */ #define _ADC_CMD_MASK 0x0000000FUL /**< Mask for ADC_CMD */ #define ADC_CMD_SINGLESTART (0x1UL << 0) /**< Single Channel Conversion Start */ #define _ADC_CMD_SINGLESTART_SHIFT 0 /**< Shift value for ADC_SINGLESTART */ #define _ADC_CMD_SINGLESTART_MASK 0x1UL /**< Bit mask for ADC_SINGLESTART */ #define _ADC_CMD_SINGLESTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CMD */ #define ADC_CMD_SINGLESTART_DEFAULT (_ADC_CMD_SINGLESTART_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_CMD */ #define ADC_CMD_SINGLESTOP (0x1UL << 1) /**< Single Channel Conversion Stop */ #define _ADC_CMD_SINGLESTOP_SHIFT 1 /**< Shift value for ADC_SINGLESTOP */ #define _ADC_CMD_SINGLESTOP_MASK 0x2UL /**< Bit mask for ADC_SINGLESTOP */ #define _ADC_CMD_SINGLESTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CMD */ #define ADC_CMD_SINGLESTOP_DEFAULT (_ADC_CMD_SINGLESTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_CMD */ #define ADC_CMD_SCANSTART (0x1UL << 2) /**< Scan Sequence Start */ #define _ADC_CMD_SCANSTART_SHIFT 2 /**< Shift value for ADC_SCANSTART */ #define _ADC_CMD_SCANSTART_MASK 0x4UL /**< Bit mask for ADC_SCANSTART */ #define _ADC_CMD_SCANSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CMD */ #define ADC_CMD_SCANSTART_DEFAULT (_ADC_CMD_SCANSTART_DEFAULT << 2) /**< Shifted mode DEFAULT for ADC_CMD */ #define ADC_CMD_SCANSTOP (0x1UL << 3) /**< Scan Sequence Stop */ #define _ADC_CMD_SCANSTOP_SHIFT 3 /**< Shift value for ADC_SCANSTOP */ #define _ADC_CMD_SCANSTOP_MASK 0x8UL /**< Bit mask for ADC_SCANSTOP */ #define _ADC_CMD_SCANSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CMD */ #define ADC_CMD_SCANSTOP_DEFAULT (_ADC_CMD_SCANSTOP_DEFAULT << 3) /**< Shifted mode DEFAULT for ADC_CMD */ /* Bit fields for ADC STATUS */ #define _ADC_STATUS_RESETVALUE 0x00000000UL /**< Default value for ADC_STATUS */ #define _ADC_STATUS_MASK 0x00031F07UL /**< Mask for ADC_STATUS */ #define ADC_STATUS_SINGLEACT (0x1UL << 0) /**< Single Channel Conversion Active */ #define _ADC_STATUS_SINGLEACT_SHIFT 0 /**< Shift value for ADC_SINGLEACT */ #define _ADC_STATUS_SINGLEACT_MASK 0x1UL /**< Bit mask for ADC_SINGLEACT */ #define _ADC_STATUS_SINGLEACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */ #define ADC_STATUS_SINGLEACT_DEFAULT (_ADC_STATUS_SINGLEACT_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_STATUS */ #define ADC_STATUS_SCANACT (0x1UL << 1) /**< Scan Conversion Active */ #define _ADC_STATUS_SCANACT_SHIFT 1 /**< Shift value for ADC_SCANACT */ #define _ADC_STATUS_SCANACT_MASK 0x2UL /**< Bit mask for ADC_SCANACT */ #define _ADC_STATUS_SCANACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */ #define ADC_STATUS_SCANACT_DEFAULT (_ADC_STATUS_SCANACT_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_STATUS */ #define ADC_STATUS_SCANPENDING (0x1UL << 2) /**< Scan Conversion Pending */ #define _ADC_STATUS_SCANPENDING_SHIFT 2 /**< Shift value for ADC_SCANPENDING */ #define _ADC_STATUS_SCANPENDING_MASK 0x4UL /**< Bit mask for ADC_SCANPENDING */ #define _ADC_STATUS_SCANPENDING_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */ #define ADC_STATUS_SCANPENDING_DEFAULT (_ADC_STATUS_SCANPENDING_DEFAULT << 2) /**< Shifted mode DEFAULT for ADC_STATUS */ #define ADC_STATUS_SINGLEREFWARM (0x1UL << 8) /**< Single Channel Reference Warmed Up */ #define _ADC_STATUS_SINGLEREFWARM_SHIFT 8 /**< Shift value for ADC_SINGLEREFWARM */ #define _ADC_STATUS_SINGLEREFWARM_MASK 0x100UL /**< Bit mask for ADC_SINGLEREFWARM */ #define _ADC_STATUS_SINGLEREFWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */ #define ADC_STATUS_SINGLEREFWARM_DEFAULT (_ADC_STATUS_SINGLEREFWARM_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_STATUS */ #define ADC_STATUS_SCANREFWARM (0x1UL << 9) /**< Scan Reference Warmed Up */ #define _ADC_STATUS_SCANREFWARM_SHIFT 9 /**< Shift value for ADC_SCANREFWARM */ #define _ADC_STATUS_SCANREFWARM_MASK 0x200UL /**< Bit mask for ADC_SCANREFWARM */ #define _ADC_STATUS_SCANREFWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */ #define ADC_STATUS_SCANREFWARM_DEFAULT (_ADC_STATUS_SCANREFWARM_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_STATUS */ #define _ADC_STATUS_PROGERR_SHIFT 10 /**< Shift value for ADC_PROGERR */ #define _ADC_STATUS_PROGERR_MASK 0xC00UL /**< Bit mask for ADC_PROGERR */ #define _ADC_STATUS_PROGERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */ #define _ADC_STATUS_PROGERR_BUSCONF 0x00000001UL /**< Mode BUSCONF for ADC_STATUS */ #define _ADC_STATUS_PROGERR_NEGSELCONF 0x00000002UL /**< Mode NEGSELCONF for ADC_STATUS */ #define ADC_STATUS_PROGERR_DEFAULT (_ADC_STATUS_PROGERR_DEFAULT << 10) /**< Shifted mode DEFAULT for ADC_STATUS */ #define ADC_STATUS_PROGERR_BUSCONF (_ADC_STATUS_PROGERR_BUSCONF << 10) /**< Shifted mode BUSCONF for ADC_STATUS */ #define ADC_STATUS_PROGERR_NEGSELCONF (_ADC_STATUS_PROGERR_NEGSELCONF << 10) /**< Shifted mode NEGSELCONF for ADC_STATUS */ #define ADC_STATUS_WARM (0x1UL << 12) /**< ADC Warmed Up */ #define _ADC_STATUS_WARM_SHIFT 12 /**< Shift value for ADC_WARM */ #define _ADC_STATUS_WARM_MASK 0x1000UL /**< Bit mask for ADC_WARM */ #define _ADC_STATUS_WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */ #define ADC_STATUS_WARM_DEFAULT (_ADC_STATUS_WARM_DEFAULT << 12) /**< Shifted mode DEFAULT for ADC_STATUS */ #define ADC_STATUS_SINGLEDV (0x1UL << 16) /**< Single Channel Data Valid */ #define _ADC_STATUS_SINGLEDV_SHIFT 16 /**< Shift value for ADC_SINGLEDV */ #define _ADC_STATUS_SINGLEDV_MASK 0x10000UL /**< Bit mask for ADC_SINGLEDV */ #define _ADC_STATUS_SINGLEDV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */ #define ADC_STATUS_SINGLEDV_DEFAULT (_ADC_STATUS_SINGLEDV_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_STATUS */ #define ADC_STATUS_SCANDV (0x1UL << 17) /**< Scan Data Valid */ #define _ADC_STATUS_SCANDV_SHIFT 17 /**< Shift value for ADC_SCANDV */ #define _ADC_STATUS_SCANDV_MASK 0x20000UL /**< Bit mask for ADC_SCANDV */ #define _ADC_STATUS_SCANDV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */ #define ADC_STATUS_SCANDV_DEFAULT (_ADC_STATUS_SCANDV_DEFAULT << 17) /**< Shifted mode DEFAULT for ADC_STATUS */ /* Bit fields for ADC SINGLECTRL */ #define _ADC_SINGLECTRL_RESETVALUE 0x00FFFF00UL /**< Default value for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_MASK 0xAFFFFFFFUL /**< Mask for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_REP (0x1UL << 0) /**< Single Channel Repetitive Mode */ #define _ADC_SINGLECTRL_REP_SHIFT 0 /**< Shift value for ADC_REP */ #define _ADC_SINGLECTRL_REP_MASK 0x1UL /**< Bit mask for ADC_REP */ #define _ADC_SINGLECTRL_REP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_REP_DEFAULT (_ADC_SINGLECTRL_REP_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_DIFF (0x1UL << 1) /**< Single Channel Differential Mode */ #define _ADC_SINGLECTRL_DIFF_SHIFT 1 /**< Shift value for ADC_DIFF */ #define _ADC_SINGLECTRL_DIFF_MASK 0x2UL /**< Bit mask for ADC_DIFF */ #define _ADC_SINGLECTRL_DIFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_DIFF_DEFAULT (_ADC_SINGLECTRL_DIFF_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_ADJ (0x1UL << 2) /**< Single Channel Result Adjustment */ #define _ADC_SINGLECTRL_ADJ_SHIFT 2 /**< Shift value for ADC_ADJ */ #define _ADC_SINGLECTRL_ADJ_MASK 0x4UL /**< Bit mask for ADC_ADJ */ #define _ADC_SINGLECTRL_ADJ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_ADJ_RIGHT 0x00000000UL /**< Mode RIGHT for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_ADJ_LEFT 0x00000001UL /**< Mode LEFT for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_ADJ_DEFAULT (_ADC_SINGLECTRL_ADJ_DEFAULT << 2) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_ADJ_RIGHT (_ADC_SINGLECTRL_ADJ_RIGHT << 2) /**< Shifted mode RIGHT for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_ADJ_LEFT (_ADC_SINGLECTRL_ADJ_LEFT << 2) /**< Shifted mode LEFT for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_RES_SHIFT 3 /**< Shift value for ADC_RES */ #define _ADC_SINGLECTRL_RES_MASK 0x18UL /**< Bit mask for ADC_RES */ #define _ADC_SINGLECTRL_RES_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_RES_12BIT 0x00000000UL /**< Mode 12BIT for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_RES_8BIT 0x00000001UL /**< Mode 8BIT for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_RES_6BIT 0x00000002UL /**< Mode 6BIT for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_RES_OVS 0x00000003UL /**< Mode OVS for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_RES_DEFAULT (_ADC_SINGLECTRL_RES_DEFAULT << 3) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_RES_12BIT (_ADC_SINGLECTRL_RES_12BIT << 3) /**< Shifted mode 12BIT for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_RES_8BIT (_ADC_SINGLECTRL_RES_8BIT << 3) /**< Shifted mode 8BIT for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_RES_6BIT (_ADC_SINGLECTRL_RES_6BIT << 3) /**< Shifted mode 6BIT for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_RES_OVS (_ADC_SINGLECTRL_RES_OVS << 3) /**< Shifted mode OVS for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_REF_SHIFT 5 /**< Shift value for ADC_REF */ #define _ADC_SINGLECTRL_REF_MASK 0xE0UL /**< Bit mask for ADC_REF */ #define _ADC_SINGLECTRL_REF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_REF_1V25 0x00000000UL /**< Mode 1V25 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_REF_2V5 0x00000001UL /**< Mode 2V5 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_REF_VDD 0x00000002UL /**< Mode VDD for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_REF_5V 0x00000003UL /**< Mode 5V for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_REF_EXTSINGLE 0x00000004UL /**< Mode EXTSINGLE for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_REF_2XEXTDIFF 0x00000005UL /**< Mode 2XEXTDIFF for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_REF_2XVDD 0x00000006UL /**< Mode 2XVDD for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_REF_CONF 0x00000007UL /**< Mode CONF for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_REF_DEFAULT (_ADC_SINGLECTRL_REF_DEFAULT << 5) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_REF_1V25 (_ADC_SINGLECTRL_REF_1V25 << 5) /**< Shifted mode 1V25 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_REF_2V5 (_ADC_SINGLECTRL_REF_2V5 << 5) /**< Shifted mode 2V5 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_REF_VDD (_ADC_SINGLECTRL_REF_VDD << 5) /**< Shifted mode VDD for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_REF_5V (_ADC_SINGLECTRL_REF_5V << 5) /**< Shifted mode 5V for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_REF_EXTSINGLE (_ADC_SINGLECTRL_REF_EXTSINGLE << 5) /**< Shifted mode EXTSINGLE for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_REF_2XEXTDIFF (_ADC_SINGLECTRL_REF_2XEXTDIFF << 5) /**< Shifted mode 2XEXTDIFF for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_REF_2XVDD (_ADC_SINGLECTRL_REF_2XVDD << 5) /**< Shifted mode 2XVDD for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_REF_CONF (_ADC_SINGLECTRL_REF_CONF << 5) /**< Shifted mode CONF for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_SHIFT 8 /**< Shift value for ADC_POSSEL */ #define _ADC_SINGLECTRL_POSSEL_MASK 0xFF00UL /**< Bit mask for ADC_POSSEL */ #define _ADC_SINGLECTRL_POSSEL_APORT0XCH0 0x00000000UL /**< Mode APORT0XCH0 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT0XCH1 0x00000001UL /**< Mode APORT0XCH1 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT0XCH2 0x00000002UL /**< Mode APORT0XCH2 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT0XCH3 0x00000003UL /**< Mode APORT0XCH3 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT0XCH4 0x00000004UL /**< Mode APORT0XCH4 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT0XCH5 0x00000005UL /**< Mode APORT0XCH5 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT0XCH6 0x00000006UL /**< Mode APORT0XCH6 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT0XCH7 0x00000007UL /**< Mode APORT0XCH7 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT0XCH8 0x00000008UL /**< Mode APORT0XCH8 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT0XCH9 0x00000009UL /**< Mode APORT0XCH9 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT0XCH10 0x0000000AUL /**< Mode APORT0XCH10 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT0XCH11 0x0000000BUL /**< Mode APORT0XCH11 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT0XCH12 0x0000000CUL /**< Mode APORT0XCH12 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT0XCH13 0x0000000DUL /**< Mode APORT0XCH13 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT0XCH14 0x0000000EUL /**< Mode APORT0XCH14 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT0XCH15 0x0000000FUL /**< Mode APORT0XCH15 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT0YCH0 0x00000010UL /**< Mode APORT0YCH0 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT0YCH1 0x00000011UL /**< Mode APORT0YCH1 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT0YCH2 0x00000012UL /**< Mode APORT0YCH2 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT0YCH3 0x00000013UL /**< Mode APORT0YCH3 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT0YCH4 0x00000014UL /**< Mode APORT0YCH4 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT0YCH5 0x00000015UL /**< Mode APORT0YCH5 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT0YCH6 0x00000016UL /**< Mode APORT0YCH6 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT0YCH7 0x00000017UL /**< Mode APORT0YCH7 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT0YCH8 0x00000018UL /**< Mode APORT0YCH8 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT0YCH9 0x00000019UL /**< Mode APORT0YCH9 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT0YCH10 0x0000001AUL /**< Mode APORT0YCH10 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT0YCH11 0x0000001BUL /**< Mode APORT0YCH11 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT0YCH12 0x0000001CUL /**< Mode APORT0YCH12 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT0YCH13 0x0000001DUL /**< Mode APORT0YCH13 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT0YCH14 0x0000001EUL /**< Mode APORT0YCH14 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT0YCH15 0x0000001FUL /**< Mode APORT0YCH15 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT1XCH0 0x00000020UL /**< Mode APORT1XCH0 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT1YCH1 0x00000021UL /**< Mode APORT1YCH1 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT1XCH2 0x00000022UL /**< Mode APORT1XCH2 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT1YCH3 0x00000023UL /**< Mode APORT1YCH3 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT1XCH4 0x00000024UL /**< Mode APORT1XCH4 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT1YCH5 0x00000025UL /**< Mode APORT1YCH5 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT1XCH6 0x00000026UL /**< Mode APORT1XCH6 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT1YCH7 0x00000027UL /**< Mode APORT1YCH7 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT1XCH8 0x00000028UL /**< Mode APORT1XCH8 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT1YCH9 0x00000029UL /**< Mode APORT1YCH9 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT1XCH10 0x0000002AUL /**< Mode APORT1XCH10 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT1YCH11 0x0000002BUL /**< Mode APORT1YCH11 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT1XCH12 0x0000002CUL /**< Mode APORT1XCH12 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT1YCH13 0x0000002DUL /**< Mode APORT1YCH13 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT1XCH14 0x0000002EUL /**< Mode APORT1XCH14 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT1YCH15 0x0000002FUL /**< Mode APORT1YCH15 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT1XCH16 0x00000030UL /**< Mode APORT1XCH16 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT1YCH17 0x00000031UL /**< Mode APORT1YCH17 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT1XCH18 0x00000032UL /**< Mode APORT1XCH18 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT1YCH19 0x00000033UL /**< Mode APORT1YCH19 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT1XCH20 0x00000034UL /**< Mode APORT1XCH20 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT1YCH21 0x00000035UL /**< Mode APORT1YCH21 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT1XCH22 0x00000036UL /**< Mode APORT1XCH22 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT1YCH23 0x00000037UL /**< Mode APORT1YCH23 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT1XCH24 0x00000038UL /**< Mode APORT1XCH24 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT1YCH25 0x00000039UL /**< Mode APORT1YCH25 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT1XCH26 0x0000003AUL /**< Mode APORT1XCH26 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT1YCH27 0x0000003BUL /**< Mode APORT1YCH27 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT1XCH28 0x0000003CUL /**< Mode APORT1XCH28 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT1YCH29 0x0000003DUL /**< Mode APORT1YCH29 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT1XCH30 0x0000003EUL /**< Mode APORT1XCH30 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT1YCH31 0x0000003FUL /**< Mode APORT1YCH31 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT2YCH0 0x00000040UL /**< Mode APORT2YCH0 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT2XCH1 0x00000041UL /**< Mode APORT2XCH1 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT2YCH2 0x00000042UL /**< Mode APORT2YCH2 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT2XCH3 0x00000043UL /**< Mode APORT2XCH3 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT2YCH4 0x00000044UL /**< Mode APORT2YCH4 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT2XCH5 0x00000045UL /**< Mode APORT2XCH5 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT2YCH6 0x00000046UL /**< Mode APORT2YCH6 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT2XCH7 0x00000047UL /**< Mode APORT2XCH7 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT2YCH8 0x00000048UL /**< Mode APORT2YCH8 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT2XCH9 0x00000049UL /**< Mode APORT2XCH9 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT2YCH10 0x0000004AUL /**< Mode APORT2YCH10 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT2XCH11 0x0000004BUL /**< Mode APORT2XCH11 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT2YCH12 0x0000004CUL /**< Mode APORT2YCH12 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT2XCH13 0x0000004DUL /**< Mode APORT2XCH13 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT2YCH14 0x0000004EUL /**< Mode APORT2YCH14 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT2XCH15 0x0000004FUL /**< Mode APORT2XCH15 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT2YCH16 0x00000050UL /**< Mode APORT2YCH16 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT2XCH17 0x00000051UL /**< Mode APORT2XCH17 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT2YCH18 0x00000052UL /**< Mode APORT2YCH18 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT2XCH19 0x00000053UL /**< Mode APORT2XCH19 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT2YCH20 0x00000054UL /**< Mode APORT2YCH20 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT2XCH21 0x00000055UL /**< Mode APORT2XCH21 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT2YCH22 0x00000056UL /**< Mode APORT2YCH22 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT2XCH23 0x00000057UL /**< Mode APORT2XCH23 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT2YCH24 0x00000058UL /**< Mode APORT2YCH24 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT2XCH25 0x00000059UL /**< Mode APORT2XCH25 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT2YCH26 0x0000005AUL /**< Mode APORT2YCH26 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT2XCH27 0x0000005BUL /**< Mode APORT2XCH27 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT2YCH28 0x0000005CUL /**< Mode APORT2YCH28 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT2XCH29 0x0000005DUL /**< Mode APORT2XCH29 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT2YCH30 0x0000005EUL /**< Mode APORT2YCH30 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT2XCH31 0x0000005FUL /**< Mode APORT2XCH31 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT3XCH0 0x00000060UL /**< Mode APORT3XCH0 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT3YCH1 0x00000061UL /**< Mode APORT3YCH1 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT3XCH2 0x00000062UL /**< Mode APORT3XCH2 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT3YCH3 0x00000063UL /**< Mode APORT3YCH3 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT3XCH4 0x00000064UL /**< Mode APORT3XCH4 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT3YCH5 0x00000065UL /**< Mode APORT3YCH5 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT3XCH6 0x00000066UL /**< Mode APORT3XCH6 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT3YCH7 0x00000067UL /**< Mode APORT3YCH7 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT3XCH8 0x00000068UL /**< Mode APORT3XCH8 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT3YCH9 0x00000069UL /**< Mode APORT3YCH9 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT3XCH10 0x0000006AUL /**< Mode APORT3XCH10 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT3YCH11 0x0000006BUL /**< Mode APORT3YCH11 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT3XCH12 0x0000006CUL /**< Mode APORT3XCH12 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT3YCH13 0x0000006DUL /**< Mode APORT3YCH13 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT3XCH14 0x0000006EUL /**< Mode APORT3XCH14 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT3YCH15 0x0000006FUL /**< Mode APORT3YCH15 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT3XCH16 0x00000070UL /**< Mode APORT3XCH16 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT3YCH17 0x00000071UL /**< Mode APORT3YCH17 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT3XCH18 0x00000072UL /**< Mode APORT3XCH18 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT3YCH19 0x00000073UL /**< Mode APORT3YCH19 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT3XCH20 0x00000074UL /**< Mode APORT3XCH20 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT3YCH21 0x00000075UL /**< Mode APORT3YCH21 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT3XCH22 0x00000076UL /**< Mode APORT3XCH22 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT3YCH23 0x00000077UL /**< Mode APORT3YCH23 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT3XCH24 0x00000078UL /**< Mode APORT3XCH24 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT3YCH25 0x00000079UL /**< Mode APORT3YCH25 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT3XCH26 0x0000007AUL /**< Mode APORT3XCH26 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT3YCH27 0x0000007BUL /**< Mode APORT3YCH27 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT3XCH28 0x0000007CUL /**< Mode APORT3XCH28 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT3YCH29 0x0000007DUL /**< Mode APORT3YCH29 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT3XCH30 0x0000007EUL /**< Mode APORT3XCH30 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT3YCH31 0x0000007FUL /**< Mode APORT3YCH31 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT4YCH0 0x00000080UL /**< Mode APORT4YCH0 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT4XCH1 0x00000081UL /**< Mode APORT4XCH1 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT4YCH2 0x00000082UL /**< Mode APORT4YCH2 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT4XCH3 0x00000083UL /**< Mode APORT4XCH3 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT4YCH4 0x00000084UL /**< Mode APORT4YCH4 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT4XCH5 0x00000085UL /**< Mode APORT4XCH5 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT4YCH6 0x00000086UL /**< Mode APORT4YCH6 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT4XCH7 0x00000087UL /**< Mode APORT4XCH7 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT4YCH8 0x00000088UL /**< Mode APORT4YCH8 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT4XCH9 0x00000089UL /**< Mode APORT4XCH9 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT4YCH10 0x0000008AUL /**< Mode APORT4YCH10 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT4XCH11 0x0000008BUL /**< Mode APORT4XCH11 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT4YCH12 0x0000008CUL /**< Mode APORT4YCH12 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT4XCH13 0x0000008DUL /**< Mode APORT4XCH13 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT4YCH14 0x0000008EUL /**< Mode APORT4YCH14 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT4XCH15 0x0000008FUL /**< Mode APORT4XCH15 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT4YCH16 0x00000090UL /**< Mode APORT4YCH16 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT4XCH17 0x00000091UL /**< Mode APORT4XCH17 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT4YCH18 0x00000092UL /**< Mode APORT4YCH18 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT4XCH19 0x00000093UL /**< Mode APORT4XCH19 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT4YCH20 0x00000094UL /**< Mode APORT4YCH20 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT4XCH21 0x00000095UL /**< Mode APORT4XCH21 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT4YCH22 0x00000096UL /**< Mode APORT4YCH22 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT4XCH23 0x00000097UL /**< Mode APORT4XCH23 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT4YCH24 0x00000098UL /**< Mode APORT4YCH24 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT4XCH25 0x00000099UL /**< Mode APORT4XCH25 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT4YCH26 0x0000009AUL /**< Mode APORT4YCH26 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT4XCH27 0x0000009BUL /**< Mode APORT4XCH27 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT4YCH28 0x0000009CUL /**< Mode APORT4YCH28 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT4XCH29 0x0000009DUL /**< Mode APORT4XCH29 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT4YCH30 0x0000009EUL /**< Mode APORT4YCH30 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_APORT4XCH31 0x0000009FUL /**< Mode APORT4XCH31 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_AVDD 0x000000E0UL /**< Mode AVDD for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_BUVDD 0x000000E1UL /**< Mode BUVDD for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_DVDD 0x000000E2UL /**< Mode DVDD for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_PAVDD 0x000000E3UL /**< Mode PAVDD for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_DECOUPLE 0x000000E4UL /**< Mode DECOUPLE for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_IOVDD 0x000000E5UL /**< Mode IOVDD for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_IOVDD1 0x000000E6UL /**< Mode IOVDD1 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_VSP 0x000000E7UL /**< Mode VSP for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_OPA2 0x000000F2UL /**< Mode OPA2 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_TEMP 0x000000F3UL /**< Mode TEMP for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_DAC0OUT0 0x000000F4UL /**< Mode DAC0OUT0 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_R5VOUT 0x000000F5UL /**< Mode R5VOUT for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_SP1 0x000000F6UL /**< Mode SP1 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_SP2 0x000000F7UL /**< Mode SP2 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_DAC0OUT1 0x000000F8UL /**< Mode DAC0OUT1 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_SUBLSB 0x000000F9UL /**< Mode SUBLSB for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_OPA3 0x000000FAUL /**< Mode OPA3 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_DEFAULT 0x000000FFUL /**< Mode DEFAULT for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_POSSEL_VSS 0x000000FFUL /**< Mode VSS for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT0XCH0 (_ADC_SINGLECTRL_POSSEL_APORT0XCH0 << 8) /**< Shifted mode APORT0XCH0 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT0XCH1 (_ADC_SINGLECTRL_POSSEL_APORT0XCH1 << 8) /**< Shifted mode APORT0XCH1 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT0XCH2 (_ADC_SINGLECTRL_POSSEL_APORT0XCH2 << 8) /**< Shifted mode APORT0XCH2 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT0XCH3 (_ADC_SINGLECTRL_POSSEL_APORT0XCH3 << 8) /**< Shifted mode APORT0XCH3 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT0XCH4 (_ADC_SINGLECTRL_POSSEL_APORT0XCH4 << 8) /**< Shifted mode APORT0XCH4 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT0XCH5 (_ADC_SINGLECTRL_POSSEL_APORT0XCH5 << 8) /**< Shifted mode APORT0XCH5 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT0XCH6 (_ADC_SINGLECTRL_POSSEL_APORT0XCH6 << 8) /**< Shifted mode APORT0XCH6 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT0XCH7 (_ADC_SINGLECTRL_POSSEL_APORT0XCH7 << 8) /**< Shifted mode APORT0XCH7 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT0XCH8 (_ADC_SINGLECTRL_POSSEL_APORT0XCH8 << 8) /**< Shifted mode APORT0XCH8 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT0XCH9 (_ADC_SINGLECTRL_POSSEL_APORT0XCH9 << 8) /**< Shifted mode APORT0XCH9 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT0XCH10 (_ADC_SINGLECTRL_POSSEL_APORT0XCH10 << 8) /**< Shifted mode APORT0XCH10 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT0XCH11 (_ADC_SINGLECTRL_POSSEL_APORT0XCH11 << 8) /**< Shifted mode APORT0XCH11 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT0XCH12 (_ADC_SINGLECTRL_POSSEL_APORT0XCH12 << 8) /**< Shifted mode APORT0XCH12 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT0XCH13 (_ADC_SINGLECTRL_POSSEL_APORT0XCH13 << 8) /**< Shifted mode APORT0XCH13 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT0XCH14 (_ADC_SINGLECTRL_POSSEL_APORT0XCH14 << 8) /**< Shifted mode APORT0XCH14 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT0XCH15 (_ADC_SINGLECTRL_POSSEL_APORT0XCH15 << 8) /**< Shifted mode APORT0XCH15 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT0YCH0 (_ADC_SINGLECTRL_POSSEL_APORT0YCH0 << 8) /**< Shifted mode APORT0YCH0 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT0YCH1 (_ADC_SINGLECTRL_POSSEL_APORT0YCH1 << 8) /**< Shifted mode APORT0YCH1 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT0YCH2 (_ADC_SINGLECTRL_POSSEL_APORT0YCH2 << 8) /**< Shifted mode APORT0YCH2 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT0YCH3 (_ADC_SINGLECTRL_POSSEL_APORT0YCH3 << 8) /**< Shifted mode APORT0YCH3 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT0YCH4 (_ADC_SINGLECTRL_POSSEL_APORT0YCH4 << 8) /**< Shifted mode APORT0YCH4 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT0YCH5 (_ADC_SINGLECTRL_POSSEL_APORT0YCH5 << 8) /**< Shifted mode APORT0YCH5 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT0YCH6 (_ADC_SINGLECTRL_POSSEL_APORT0YCH6 << 8) /**< Shifted mode APORT0YCH6 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT0YCH7 (_ADC_SINGLECTRL_POSSEL_APORT0YCH7 << 8) /**< Shifted mode APORT0YCH7 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT0YCH8 (_ADC_SINGLECTRL_POSSEL_APORT0YCH8 << 8) /**< Shifted mode APORT0YCH8 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT0YCH9 (_ADC_SINGLECTRL_POSSEL_APORT0YCH9 << 8) /**< Shifted mode APORT0YCH9 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT0YCH10 (_ADC_SINGLECTRL_POSSEL_APORT0YCH10 << 8) /**< Shifted mode APORT0YCH10 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT0YCH11 (_ADC_SINGLECTRL_POSSEL_APORT0YCH11 << 8) /**< Shifted mode APORT0YCH11 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT0YCH12 (_ADC_SINGLECTRL_POSSEL_APORT0YCH12 << 8) /**< Shifted mode APORT0YCH12 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT0YCH13 (_ADC_SINGLECTRL_POSSEL_APORT0YCH13 << 8) /**< Shifted mode APORT0YCH13 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT0YCH14 (_ADC_SINGLECTRL_POSSEL_APORT0YCH14 << 8) /**< Shifted mode APORT0YCH14 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT0YCH15 (_ADC_SINGLECTRL_POSSEL_APORT0YCH15 << 8) /**< Shifted mode APORT0YCH15 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT1XCH0 (_ADC_SINGLECTRL_POSSEL_APORT1XCH0 << 8) /**< Shifted mode APORT1XCH0 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT1YCH1 (_ADC_SINGLECTRL_POSSEL_APORT1YCH1 << 8) /**< Shifted mode APORT1YCH1 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT1XCH2 (_ADC_SINGLECTRL_POSSEL_APORT1XCH2 << 8) /**< Shifted mode APORT1XCH2 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT1YCH3 (_ADC_SINGLECTRL_POSSEL_APORT1YCH3 << 8) /**< Shifted mode APORT1YCH3 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT1XCH4 (_ADC_SINGLECTRL_POSSEL_APORT1XCH4 << 8) /**< Shifted mode APORT1XCH4 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT1YCH5 (_ADC_SINGLECTRL_POSSEL_APORT1YCH5 << 8) /**< Shifted mode APORT1YCH5 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT1XCH6 (_ADC_SINGLECTRL_POSSEL_APORT1XCH6 << 8) /**< Shifted mode APORT1XCH6 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT1YCH7 (_ADC_SINGLECTRL_POSSEL_APORT1YCH7 << 8) /**< Shifted mode APORT1YCH7 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT1XCH8 (_ADC_SINGLECTRL_POSSEL_APORT1XCH8 << 8) /**< Shifted mode APORT1XCH8 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT1YCH9 (_ADC_SINGLECTRL_POSSEL_APORT1YCH9 << 8) /**< Shifted mode APORT1YCH9 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT1XCH10 (_ADC_SINGLECTRL_POSSEL_APORT1XCH10 << 8) /**< Shifted mode APORT1XCH10 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT1YCH11 (_ADC_SINGLECTRL_POSSEL_APORT1YCH11 << 8) /**< Shifted mode APORT1YCH11 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT1XCH12 (_ADC_SINGLECTRL_POSSEL_APORT1XCH12 << 8) /**< Shifted mode APORT1XCH12 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT1YCH13 (_ADC_SINGLECTRL_POSSEL_APORT1YCH13 << 8) /**< Shifted mode APORT1YCH13 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT1XCH14 (_ADC_SINGLECTRL_POSSEL_APORT1XCH14 << 8) /**< Shifted mode APORT1XCH14 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT1YCH15 (_ADC_SINGLECTRL_POSSEL_APORT1YCH15 << 8) /**< Shifted mode APORT1YCH15 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT1XCH16 (_ADC_SINGLECTRL_POSSEL_APORT1XCH16 << 8) /**< Shifted mode APORT1XCH16 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT1YCH17 (_ADC_SINGLECTRL_POSSEL_APORT1YCH17 << 8) /**< Shifted mode APORT1YCH17 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT1XCH18 (_ADC_SINGLECTRL_POSSEL_APORT1XCH18 << 8) /**< Shifted mode APORT1XCH18 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT1YCH19 (_ADC_SINGLECTRL_POSSEL_APORT1YCH19 << 8) /**< Shifted mode APORT1YCH19 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT1XCH20 (_ADC_SINGLECTRL_POSSEL_APORT1XCH20 << 8) /**< Shifted mode APORT1XCH20 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT1YCH21 (_ADC_SINGLECTRL_POSSEL_APORT1YCH21 << 8) /**< Shifted mode APORT1YCH21 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT1XCH22 (_ADC_SINGLECTRL_POSSEL_APORT1XCH22 << 8) /**< Shifted mode APORT1XCH22 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT1YCH23 (_ADC_SINGLECTRL_POSSEL_APORT1YCH23 << 8) /**< Shifted mode APORT1YCH23 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT1XCH24 (_ADC_SINGLECTRL_POSSEL_APORT1XCH24 << 8) /**< Shifted mode APORT1XCH24 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT1YCH25 (_ADC_SINGLECTRL_POSSEL_APORT1YCH25 << 8) /**< Shifted mode APORT1YCH25 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT1XCH26 (_ADC_SINGLECTRL_POSSEL_APORT1XCH26 << 8) /**< Shifted mode APORT1XCH26 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT1YCH27 (_ADC_SINGLECTRL_POSSEL_APORT1YCH27 << 8) /**< Shifted mode APORT1YCH27 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT1XCH28 (_ADC_SINGLECTRL_POSSEL_APORT1XCH28 << 8) /**< Shifted mode APORT1XCH28 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT1YCH29 (_ADC_SINGLECTRL_POSSEL_APORT1YCH29 << 8) /**< Shifted mode APORT1YCH29 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT1XCH30 (_ADC_SINGLECTRL_POSSEL_APORT1XCH30 << 8) /**< Shifted mode APORT1XCH30 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT1YCH31 (_ADC_SINGLECTRL_POSSEL_APORT1YCH31 << 8) /**< Shifted mode APORT1YCH31 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT2YCH0 (_ADC_SINGLECTRL_POSSEL_APORT2YCH0 << 8) /**< Shifted mode APORT2YCH0 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT2XCH1 (_ADC_SINGLECTRL_POSSEL_APORT2XCH1 << 8) /**< Shifted mode APORT2XCH1 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT2YCH2 (_ADC_SINGLECTRL_POSSEL_APORT2YCH2 << 8) /**< Shifted mode APORT2YCH2 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT2XCH3 (_ADC_SINGLECTRL_POSSEL_APORT2XCH3 << 8) /**< Shifted mode APORT2XCH3 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT2YCH4 (_ADC_SINGLECTRL_POSSEL_APORT2YCH4 << 8) /**< Shifted mode APORT2YCH4 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT2XCH5 (_ADC_SINGLECTRL_POSSEL_APORT2XCH5 << 8) /**< Shifted mode APORT2XCH5 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT2YCH6 (_ADC_SINGLECTRL_POSSEL_APORT2YCH6 << 8) /**< Shifted mode APORT2YCH6 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT2XCH7 (_ADC_SINGLECTRL_POSSEL_APORT2XCH7 << 8) /**< Shifted mode APORT2XCH7 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT2YCH8 (_ADC_SINGLECTRL_POSSEL_APORT2YCH8 << 8) /**< Shifted mode APORT2YCH8 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT2XCH9 (_ADC_SINGLECTRL_POSSEL_APORT2XCH9 << 8) /**< Shifted mode APORT2XCH9 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT2YCH10 (_ADC_SINGLECTRL_POSSEL_APORT2YCH10 << 8) /**< Shifted mode APORT2YCH10 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT2XCH11 (_ADC_SINGLECTRL_POSSEL_APORT2XCH11 << 8) /**< Shifted mode APORT2XCH11 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT2YCH12 (_ADC_SINGLECTRL_POSSEL_APORT2YCH12 << 8) /**< Shifted mode APORT2YCH12 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT2XCH13 (_ADC_SINGLECTRL_POSSEL_APORT2XCH13 << 8) /**< Shifted mode APORT2XCH13 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT2YCH14 (_ADC_SINGLECTRL_POSSEL_APORT2YCH14 << 8) /**< Shifted mode APORT2YCH14 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT2XCH15 (_ADC_SINGLECTRL_POSSEL_APORT2XCH15 << 8) /**< Shifted mode APORT2XCH15 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT2YCH16 (_ADC_SINGLECTRL_POSSEL_APORT2YCH16 << 8) /**< Shifted mode APORT2YCH16 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT2XCH17 (_ADC_SINGLECTRL_POSSEL_APORT2XCH17 << 8) /**< Shifted mode APORT2XCH17 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT2YCH18 (_ADC_SINGLECTRL_POSSEL_APORT2YCH18 << 8) /**< Shifted mode APORT2YCH18 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT2XCH19 (_ADC_SINGLECTRL_POSSEL_APORT2XCH19 << 8) /**< Shifted mode APORT2XCH19 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT2YCH20 (_ADC_SINGLECTRL_POSSEL_APORT2YCH20 << 8) /**< Shifted mode APORT2YCH20 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT2XCH21 (_ADC_SINGLECTRL_POSSEL_APORT2XCH21 << 8) /**< Shifted mode APORT2XCH21 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT2YCH22 (_ADC_SINGLECTRL_POSSEL_APORT2YCH22 << 8) /**< Shifted mode APORT2YCH22 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT2XCH23 (_ADC_SINGLECTRL_POSSEL_APORT2XCH23 << 8) /**< Shifted mode APORT2XCH23 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT2YCH24 (_ADC_SINGLECTRL_POSSEL_APORT2YCH24 << 8) /**< Shifted mode APORT2YCH24 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT2XCH25 (_ADC_SINGLECTRL_POSSEL_APORT2XCH25 << 8) /**< Shifted mode APORT2XCH25 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT2YCH26 (_ADC_SINGLECTRL_POSSEL_APORT2YCH26 << 8) /**< Shifted mode APORT2YCH26 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT2XCH27 (_ADC_SINGLECTRL_POSSEL_APORT2XCH27 << 8) /**< Shifted mode APORT2XCH27 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT2YCH28 (_ADC_SINGLECTRL_POSSEL_APORT2YCH28 << 8) /**< Shifted mode APORT2YCH28 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT2XCH29 (_ADC_SINGLECTRL_POSSEL_APORT2XCH29 << 8) /**< Shifted mode APORT2XCH29 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT2YCH30 (_ADC_SINGLECTRL_POSSEL_APORT2YCH30 << 8) /**< Shifted mode APORT2YCH30 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT2XCH31 (_ADC_SINGLECTRL_POSSEL_APORT2XCH31 << 8) /**< Shifted mode APORT2XCH31 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT3XCH0 (_ADC_SINGLECTRL_POSSEL_APORT3XCH0 << 8) /**< Shifted mode APORT3XCH0 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT3YCH1 (_ADC_SINGLECTRL_POSSEL_APORT3YCH1 << 8) /**< Shifted mode APORT3YCH1 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT3XCH2 (_ADC_SINGLECTRL_POSSEL_APORT3XCH2 << 8) /**< Shifted mode APORT3XCH2 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT3YCH3 (_ADC_SINGLECTRL_POSSEL_APORT3YCH3 << 8) /**< Shifted mode APORT3YCH3 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT3XCH4 (_ADC_SINGLECTRL_POSSEL_APORT3XCH4 << 8) /**< Shifted mode APORT3XCH4 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT3YCH5 (_ADC_SINGLECTRL_POSSEL_APORT3YCH5 << 8) /**< Shifted mode APORT3YCH5 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT3XCH6 (_ADC_SINGLECTRL_POSSEL_APORT3XCH6 << 8) /**< Shifted mode APORT3XCH6 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT3YCH7 (_ADC_SINGLECTRL_POSSEL_APORT3YCH7 << 8) /**< Shifted mode APORT3YCH7 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT3XCH8 (_ADC_SINGLECTRL_POSSEL_APORT3XCH8 << 8) /**< Shifted mode APORT3XCH8 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT3YCH9 (_ADC_SINGLECTRL_POSSEL_APORT3YCH9 << 8) /**< Shifted mode APORT3YCH9 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT3XCH10 (_ADC_SINGLECTRL_POSSEL_APORT3XCH10 << 8) /**< Shifted mode APORT3XCH10 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT3YCH11 (_ADC_SINGLECTRL_POSSEL_APORT3YCH11 << 8) /**< Shifted mode APORT3YCH11 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT3XCH12 (_ADC_SINGLECTRL_POSSEL_APORT3XCH12 << 8) /**< Shifted mode APORT3XCH12 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT3YCH13 (_ADC_SINGLECTRL_POSSEL_APORT3YCH13 << 8) /**< Shifted mode APORT3YCH13 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT3XCH14 (_ADC_SINGLECTRL_POSSEL_APORT3XCH14 << 8) /**< Shifted mode APORT3XCH14 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT3YCH15 (_ADC_SINGLECTRL_POSSEL_APORT3YCH15 << 8) /**< Shifted mode APORT3YCH15 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT3XCH16 (_ADC_SINGLECTRL_POSSEL_APORT3XCH16 << 8) /**< Shifted mode APORT3XCH16 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT3YCH17 (_ADC_SINGLECTRL_POSSEL_APORT3YCH17 << 8) /**< Shifted mode APORT3YCH17 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT3XCH18 (_ADC_SINGLECTRL_POSSEL_APORT3XCH18 << 8) /**< Shifted mode APORT3XCH18 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT3YCH19 (_ADC_SINGLECTRL_POSSEL_APORT3YCH19 << 8) /**< Shifted mode APORT3YCH19 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT3XCH20 (_ADC_SINGLECTRL_POSSEL_APORT3XCH20 << 8) /**< Shifted mode APORT3XCH20 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT3YCH21 (_ADC_SINGLECTRL_POSSEL_APORT3YCH21 << 8) /**< Shifted mode APORT3YCH21 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT3XCH22 (_ADC_SINGLECTRL_POSSEL_APORT3XCH22 << 8) /**< Shifted mode APORT3XCH22 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT3YCH23 (_ADC_SINGLECTRL_POSSEL_APORT3YCH23 << 8) /**< Shifted mode APORT3YCH23 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT3XCH24 (_ADC_SINGLECTRL_POSSEL_APORT3XCH24 << 8) /**< Shifted mode APORT3XCH24 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT3YCH25 (_ADC_SINGLECTRL_POSSEL_APORT3YCH25 << 8) /**< Shifted mode APORT3YCH25 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT3XCH26 (_ADC_SINGLECTRL_POSSEL_APORT3XCH26 << 8) /**< Shifted mode APORT3XCH26 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT3YCH27 (_ADC_SINGLECTRL_POSSEL_APORT3YCH27 << 8) /**< Shifted mode APORT3YCH27 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT3XCH28 (_ADC_SINGLECTRL_POSSEL_APORT3XCH28 << 8) /**< Shifted mode APORT3XCH28 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT3YCH29 (_ADC_SINGLECTRL_POSSEL_APORT3YCH29 << 8) /**< Shifted mode APORT3YCH29 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT3XCH30 (_ADC_SINGLECTRL_POSSEL_APORT3XCH30 << 8) /**< Shifted mode APORT3XCH30 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT3YCH31 (_ADC_SINGLECTRL_POSSEL_APORT3YCH31 << 8) /**< Shifted mode APORT3YCH31 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT4YCH0 (_ADC_SINGLECTRL_POSSEL_APORT4YCH0 << 8) /**< Shifted mode APORT4YCH0 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT4XCH1 (_ADC_SINGLECTRL_POSSEL_APORT4XCH1 << 8) /**< Shifted mode APORT4XCH1 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT4YCH2 (_ADC_SINGLECTRL_POSSEL_APORT4YCH2 << 8) /**< Shifted mode APORT4YCH2 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT4XCH3 (_ADC_SINGLECTRL_POSSEL_APORT4XCH3 << 8) /**< Shifted mode APORT4XCH3 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT4YCH4 (_ADC_SINGLECTRL_POSSEL_APORT4YCH4 << 8) /**< Shifted mode APORT4YCH4 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT4XCH5 (_ADC_SINGLECTRL_POSSEL_APORT4XCH5 << 8) /**< Shifted mode APORT4XCH5 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT4YCH6 (_ADC_SINGLECTRL_POSSEL_APORT4YCH6 << 8) /**< Shifted mode APORT4YCH6 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT4XCH7 (_ADC_SINGLECTRL_POSSEL_APORT4XCH7 << 8) /**< Shifted mode APORT4XCH7 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT4YCH8 (_ADC_SINGLECTRL_POSSEL_APORT4YCH8 << 8) /**< Shifted mode APORT4YCH8 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT4XCH9 (_ADC_SINGLECTRL_POSSEL_APORT4XCH9 << 8) /**< Shifted mode APORT4XCH9 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT4YCH10 (_ADC_SINGLECTRL_POSSEL_APORT4YCH10 << 8) /**< Shifted mode APORT4YCH10 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT4XCH11 (_ADC_SINGLECTRL_POSSEL_APORT4XCH11 << 8) /**< Shifted mode APORT4XCH11 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT4YCH12 (_ADC_SINGLECTRL_POSSEL_APORT4YCH12 << 8) /**< Shifted mode APORT4YCH12 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT4XCH13 (_ADC_SINGLECTRL_POSSEL_APORT4XCH13 << 8) /**< Shifted mode APORT4XCH13 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT4YCH14 (_ADC_SINGLECTRL_POSSEL_APORT4YCH14 << 8) /**< Shifted mode APORT4YCH14 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT4XCH15 (_ADC_SINGLECTRL_POSSEL_APORT4XCH15 << 8) /**< Shifted mode APORT4XCH15 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT4YCH16 (_ADC_SINGLECTRL_POSSEL_APORT4YCH16 << 8) /**< Shifted mode APORT4YCH16 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT4XCH17 (_ADC_SINGLECTRL_POSSEL_APORT4XCH17 << 8) /**< Shifted mode APORT4XCH17 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT4YCH18 (_ADC_SINGLECTRL_POSSEL_APORT4YCH18 << 8) /**< Shifted mode APORT4YCH18 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT4XCH19 (_ADC_SINGLECTRL_POSSEL_APORT4XCH19 << 8) /**< Shifted mode APORT4XCH19 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT4YCH20 (_ADC_SINGLECTRL_POSSEL_APORT4YCH20 << 8) /**< Shifted mode APORT4YCH20 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT4XCH21 (_ADC_SINGLECTRL_POSSEL_APORT4XCH21 << 8) /**< Shifted mode APORT4XCH21 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT4YCH22 (_ADC_SINGLECTRL_POSSEL_APORT4YCH22 << 8) /**< Shifted mode APORT4YCH22 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT4XCH23 (_ADC_SINGLECTRL_POSSEL_APORT4XCH23 << 8) /**< Shifted mode APORT4XCH23 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT4YCH24 (_ADC_SINGLECTRL_POSSEL_APORT4YCH24 << 8) /**< Shifted mode APORT4YCH24 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT4XCH25 (_ADC_SINGLECTRL_POSSEL_APORT4XCH25 << 8) /**< Shifted mode APORT4XCH25 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT4YCH26 (_ADC_SINGLECTRL_POSSEL_APORT4YCH26 << 8) /**< Shifted mode APORT4YCH26 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT4XCH27 (_ADC_SINGLECTRL_POSSEL_APORT4XCH27 << 8) /**< Shifted mode APORT4XCH27 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT4YCH28 (_ADC_SINGLECTRL_POSSEL_APORT4YCH28 << 8) /**< Shifted mode APORT4YCH28 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT4XCH29 (_ADC_SINGLECTRL_POSSEL_APORT4XCH29 << 8) /**< Shifted mode APORT4XCH29 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT4YCH30 (_ADC_SINGLECTRL_POSSEL_APORT4YCH30 << 8) /**< Shifted mode APORT4YCH30 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_APORT4XCH31 (_ADC_SINGLECTRL_POSSEL_APORT4XCH31 << 8) /**< Shifted mode APORT4XCH31 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_AVDD (_ADC_SINGLECTRL_POSSEL_AVDD << 8) /**< Shifted mode AVDD for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_BUVDD (_ADC_SINGLECTRL_POSSEL_BUVDD << 8) /**< Shifted mode BUVDD for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_DVDD (_ADC_SINGLECTRL_POSSEL_DVDD << 8) /**< Shifted mode DVDD for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_PAVDD (_ADC_SINGLECTRL_POSSEL_PAVDD << 8) /**< Shifted mode PAVDD for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_DECOUPLE (_ADC_SINGLECTRL_POSSEL_DECOUPLE << 8) /**< Shifted mode DECOUPLE for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_IOVDD (_ADC_SINGLECTRL_POSSEL_IOVDD << 8) /**< Shifted mode IOVDD for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_IOVDD1 (_ADC_SINGLECTRL_POSSEL_IOVDD1 << 8) /**< Shifted mode IOVDD1 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_VSP (_ADC_SINGLECTRL_POSSEL_VSP << 8) /**< Shifted mode VSP for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_OPA2 (_ADC_SINGLECTRL_POSSEL_OPA2 << 8) /**< Shifted mode OPA2 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_TEMP (_ADC_SINGLECTRL_POSSEL_TEMP << 8) /**< Shifted mode TEMP for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_DAC0OUT0 (_ADC_SINGLECTRL_POSSEL_DAC0OUT0 << 8) /**< Shifted mode DAC0OUT0 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_R5VOUT (_ADC_SINGLECTRL_POSSEL_R5VOUT << 8) /**< Shifted mode R5VOUT for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_SP1 (_ADC_SINGLECTRL_POSSEL_SP1 << 8) /**< Shifted mode SP1 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_SP2 (_ADC_SINGLECTRL_POSSEL_SP2 << 8) /**< Shifted mode SP2 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_DAC0OUT1 (_ADC_SINGLECTRL_POSSEL_DAC0OUT1 << 8) /**< Shifted mode DAC0OUT1 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_SUBLSB (_ADC_SINGLECTRL_POSSEL_SUBLSB << 8) /**< Shifted mode SUBLSB for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_OPA3 (_ADC_SINGLECTRL_POSSEL_OPA3 << 8) /**< Shifted mode OPA3 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_DEFAULT (_ADC_SINGLECTRL_POSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_POSSEL_VSS (_ADC_SINGLECTRL_POSSEL_VSS << 8) /**< Shifted mode VSS for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_SHIFT 16 /**< Shift value for ADC_NEGSEL */ #define _ADC_SINGLECTRL_NEGSEL_MASK 0xFF0000UL /**< Bit mask for ADC_NEGSEL */ #define _ADC_SINGLECTRL_NEGSEL_APORT0XCH0 0x00000000UL /**< Mode APORT0XCH0 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT0XCH1 0x00000001UL /**< Mode APORT0XCH1 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT0XCH2 0x00000002UL /**< Mode APORT0XCH2 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT0XCH3 0x00000003UL /**< Mode APORT0XCH3 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT0XCH4 0x00000004UL /**< Mode APORT0XCH4 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT0XCH5 0x00000005UL /**< Mode APORT0XCH5 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT0XCH6 0x00000006UL /**< Mode APORT0XCH6 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT0XCH7 0x00000007UL /**< Mode APORT0XCH7 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT0XCH8 0x00000008UL /**< Mode APORT0XCH8 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT0XCH9 0x00000009UL /**< Mode APORT0XCH9 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT0XCH10 0x0000000AUL /**< Mode APORT0XCH10 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT0XCH11 0x0000000BUL /**< Mode APORT0XCH11 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT0XCH12 0x0000000CUL /**< Mode APORT0XCH12 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT0XCH13 0x0000000DUL /**< Mode APORT0XCH13 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT0XCH14 0x0000000EUL /**< Mode APORT0XCH14 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT0XCH15 0x0000000FUL /**< Mode APORT0XCH15 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT0YCH0 0x00000010UL /**< Mode APORT0YCH0 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT0YCH1 0x00000011UL /**< Mode APORT0YCH1 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT0YCH2 0x00000012UL /**< Mode APORT0YCH2 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT0YCH3 0x00000013UL /**< Mode APORT0YCH3 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT0YCH4 0x00000014UL /**< Mode APORT0YCH4 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT0YCH5 0x00000015UL /**< Mode APORT0YCH5 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT0YCH6 0x00000016UL /**< Mode APORT0YCH6 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT0YCH7 0x00000017UL /**< Mode APORT0YCH7 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT0YCH8 0x00000018UL /**< Mode APORT0YCH8 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT0YCH9 0x00000019UL /**< Mode APORT0YCH9 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT0YCH10 0x0000001AUL /**< Mode APORT0YCH10 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT0YCH11 0x0000001BUL /**< Mode APORT0YCH11 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT0YCH12 0x0000001CUL /**< Mode APORT0YCH12 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT0YCH13 0x0000001DUL /**< Mode APORT0YCH13 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT0YCH14 0x0000001EUL /**< Mode APORT0YCH14 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT0YCH15 0x0000001FUL /**< Mode APORT0YCH15 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT1XCH0 0x00000020UL /**< Mode APORT1XCH0 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT1YCH1 0x00000021UL /**< Mode APORT1YCH1 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT1XCH2 0x00000022UL /**< Mode APORT1XCH2 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT1YCH3 0x00000023UL /**< Mode APORT1YCH3 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT1XCH4 0x00000024UL /**< Mode APORT1XCH4 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT1YCH5 0x00000025UL /**< Mode APORT1YCH5 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT1XCH6 0x00000026UL /**< Mode APORT1XCH6 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT1YCH7 0x00000027UL /**< Mode APORT1YCH7 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT1XCH8 0x00000028UL /**< Mode APORT1XCH8 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT1YCH9 0x00000029UL /**< Mode APORT1YCH9 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT1XCH10 0x0000002AUL /**< Mode APORT1XCH10 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT1YCH11 0x0000002BUL /**< Mode APORT1YCH11 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT1XCH12 0x0000002CUL /**< Mode APORT1XCH12 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT1YCH13 0x0000002DUL /**< Mode APORT1YCH13 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT1XCH14 0x0000002EUL /**< Mode APORT1XCH14 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT1YCH15 0x0000002FUL /**< Mode APORT1YCH15 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT1XCH16 0x00000030UL /**< Mode APORT1XCH16 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT1YCH17 0x00000031UL /**< Mode APORT1YCH17 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT1XCH18 0x00000032UL /**< Mode APORT1XCH18 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT1YCH19 0x00000033UL /**< Mode APORT1YCH19 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT1XCH20 0x00000034UL /**< Mode APORT1XCH20 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT1YCH21 0x00000035UL /**< Mode APORT1YCH21 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT1XCH22 0x00000036UL /**< Mode APORT1XCH22 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT1YCH23 0x00000037UL /**< Mode APORT1YCH23 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT1XCH24 0x00000038UL /**< Mode APORT1XCH24 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT1YCH25 0x00000039UL /**< Mode APORT1YCH25 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT1XCH26 0x0000003AUL /**< Mode APORT1XCH26 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT1YCH27 0x0000003BUL /**< Mode APORT1YCH27 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT1XCH28 0x0000003CUL /**< Mode APORT1XCH28 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT1YCH29 0x0000003DUL /**< Mode APORT1YCH29 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT1XCH30 0x0000003EUL /**< Mode APORT1XCH30 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT1YCH31 0x0000003FUL /**< Mode APORT1YCH31 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT2YCH0 0x00000040UL /**< Mode APORT2YCH0 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT2XCH1 0x00000041UL /**< Mode APORT2XCH1 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT2YCH2 0x00000042UL /**< Mode APORT2YCH2 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT2XCH3 0x00000043UL /**< Mode APORT2XCH3 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT2YCH4 0x00000044UL /**< Mode APORT2YCH4 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT2XCH5 0x00000045UL /**< Mode APORT2XCH5 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT2YCH6 0x00000046UL /**< Mode APORT2YCH6 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT2XCH7 0x00000047UL /**< Mode APORT2XCH7 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT2YCH8 0x00000048UL /**< Mode APORT2YCH8 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT2XCH9 0x00000049UL /**< Mode APORT2XCH9 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT2YCH10 0x0000004AUL /**< Mode APORT2YCH10 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT2XCH11 0x0000004BUL /**< Mode APORT2XCH11 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT2YCH12 0x0000004CUL /**< Mode APORT2YCH12 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT2XCH13 0x0000004DUL /**< Mode APORT2XCH13 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT2YCH14 0x0000004EUL /**< Mode APORT2YCH14 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT2XCH15 0x0000004FUL /**< Mode APORT2XCH15 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT2YCH16 0x00000050UL /**< Mode APORT2YCH16 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT2XCH17 0x00000051UL /**< Mode APORT2XCH17 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT2YCH18 0x00000052UL /**< Mode APORT2YCH18 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT2XCH19 0x00000053UL /**< Mode APORT2XCH19 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT2YCH20 0x00000054UL /**< Mode APORT2YCH20 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT2XCH21 0x00000055UL /**< Mode APORT2XCH21 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT2YCH22 0x00000056UL /**< Mode APORT2YCH22 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT2XCH23 0x00000057UL /**< Mode APORT2XCH23 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT2YCH24 0x00000058UL /**< Mode APORT2YCH24 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT2XCH25 0x00000059UL /**< Mode APORT2XCH25 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT2YCH26 0x0000005AUL /**< Mode APORT2YCH26 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT2XCH27 0x0000005BUL /**< Mode APORT2XCH27 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT2YCH28 0x0000005CUL /**< Mode APORT2YCH28 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT2XCH29 0x0000005DUL /**< Mode APORT2XCH29 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT2YCH30 0x0000005EUL /**< Mode APORT2YCH30 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT2XCH31 0x0000005FUL /**< Mode APORT2XCH31 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT3XCH0 0x00000060UL /**< Mode APORT3XCH0 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT3YCH1 0x00000061UL /**< Mode APORT3YCH1 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT3XCH2 0x00000062UL /**< Mode APORT3XCH2 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT3YCH3 0x00000063UL /**< Mode APORT3YCH3 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT3XCH4 0x00000064UL /**< Mode APORT3XCH4 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT3YCH5 0x00000065UL /**< Mode APORT3YCH5 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT3XCH6 0x00000066UL /**< Mode APORT3XCH6 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT3YCH7 0x00000067UL /**< Mode APORT3YCH7 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT3XCH8 0x00000068UL /**< Mode APORT3XCH8 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT3YCH9 0x00000069UL /**< Mode APORT3YCH9 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT3XCH10 0x0000006AUL /**< Mode APORT3XCH10 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT3YCH11 0x0000006BUL /**< Mode APORT3YCH11 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT3XCH12 0x0000006CUL /**< Mode APORT3XCH12 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT3YCH13 0x0000006DUL /**< Mode APORT3YCH13 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT3XCH14 0x0000006EUL /**< Mode APORT3XCH14 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT3YCH15 0x0000006FUL /**< Mode APORT3YCH15 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT3XCH16 0x00000070UL /**< Mode APORT3XCH16 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT3YCH17 0x00000071UL /**< Mode APORT3YCH17 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT3XCH18 0x00000072UL /**< Mode APORT3XCH18 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT3YCH19 0x00000073UL /**< Mode APORT3YCH19 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT3XCH20 0x00000074UL /**< Mode APORT3XCH20 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT3YCH21 0x00000075UL /**< Mode APORT3YCH21 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT3XCH22 0x00000076UL /**< Mode APORT3XCH22 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT3YCH23 0x00000077UL /**< Mode APORT3YCH23 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT3XCH24 0x00000078UL /**< Mode APORT3XCH24 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT3YCH25 0x00000079UL /**< Mode APORT3YCH25 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT3XCH26 0x0000007AUL /**< Mode APORT3XCH26 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT3YCH27 0x0000007BUL /**< Mode APORT3YCH27 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT3XCH28 0x0000007CUL /**< Mode APORT3XCH28 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT3YCH29 0x0000007DUL /**< Mode APORT3YCH29 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT3XCH30 0x0000007EUL /**< Mode APORT3XCH30 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT3YCH31 0x0000007FUL /**< Mode APORT3YCH31 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT4YCH0 0x00000080UL /**< Mode APORT4YCH0 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT4XCH1 0x00000081UL /**< Mode APORT4XCH1 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT4YCH2 0x00000082UL /**< Mode APORT4YCH2 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT4XCH3 0x00000083UL /**< Mode APORT4XCH3 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT4YCH4 0x00000084UL /**< Mode APORT4YCH4 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT4XCH5 0x00000085UL /**< Mode APORT4XCH5 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT4YCH6 0x00000086UL /**< Mode APORT4YCH6 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT4XCH7 0x00000087UL /**< Mode APORT4XCH7 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT4YCH8 0x00000088UL /**< Mode APORT4YCH8 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT4XCH9 0x00000089UL /**< Mode APORT4XCH9 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT4YCH10 0x0000008AUL /**< Mode APORT4YCH10 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT4XCH11 0x0000008BUL /**< Mode APORT4XCH11 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT4YCH12 0x0000008CUL /**< Mode APORT4YCH12 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT4XCH13 0x0000008DUL /**< Mode APORT4XCH13 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT4YCH14 0x0000008EUL /**< Mode APORT4YCH14 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT4XCH15 0x0000008FUL /**< Mode APORT4XCH15 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT4YCH16 0x00000090UL /**< Mode APORT4YCH16 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT4XCH17 0x00000091UL /**< Mode APORT4XCH17 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT4YCH18 0x00000092UL /**< Mode APORT4YCH18 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT4XCH19 0x00000093UL /**< Mode APORT4XCH19 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT4YCH20 0x00000094UL /**< Mode APORT4YCH20 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT4XCH21 0x00000095UL /**< Mode APORT4XCH21 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT4YCH22 0x00000096UL /**< Mode APORT4YCH22 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT4XCH23 0x00000097UL /**< Mode APORT4XCH23 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT4YCH24 0x00000098UL /**< Mode APORT4YCH24 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT4XCH25 0x00000099UL /**< Mode APORT4XCH25 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT4YCH26 0x0000009AUL /**< Mode APORT4YCH26 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT4XCH27 0x0000009BUL /**< Mode APORT4XCH27 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT4YCH28 0x0000009CUL /**< Mode APORT4YCH28 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT4XCH29 0x0000009DUL /**< Mode APORT4XCH29 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT4YCH30 0x0000009EUL /**< Mode APORT4YCH30 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_APORT4XCH31 0x0000009FUL /**< Mode APORT4XCH31 for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_TESTN 0x000000F5UL /**< Mode TESTN for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_DEFAULT 0x000000FFUL /**< Mode DEFAULT for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_NEGSEL_VSS 0x000000FFUL /**< Mode VSS for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT0XCH0 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH0 << 16) /**< Shifted mode APORT0XCH0 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT0XCH1 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH1 << 16) /**< Shifted mode APORT0XCH1 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT0XCH2 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH2 << 16) /**< Shifted mode APORT0XCH2 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT0XCH3 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH3 << 16) /**< Shifted mode APORT0XCH3 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT0XCH4 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH4 << 16) /**< Shifted mode APORT0XCH4 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT0XCH5 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH5 << 16) /**< Shifted mode APORT0XCH5 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT0XCH6 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH6 << 16) /**< Shifted mode APORT0XCH6 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT0XCH7 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH7 << 16) /**< Shifted mode APORT0XCH7 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT0XCH8 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH8 << 16) /**< Shifted mode APORT0XCH8 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT0XCH9 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH9 << 16) /**< Shifted mode APORT0XCH9 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT0XCH10 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH10 << 16) /**< Shifted mode APORT0XCH10 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT0XCH11 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH11 << 16) /**< Shifted mode APORT0XCH11 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT0XCH12 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH12 << 16) /**< Shifted mode APORT0XCH12 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT0XCH13 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH13 << 16) /**< Shifted mode APORT0XCH13 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT0XCH14 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH14 << 16) /**< Shifted mode APORT0XCH14 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT0XCH15 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH15 << 16) /**< Shifted mode APORT0XCH15 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT0YCH0 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH0 << 16) /**< Shifted mode APORT0YCH0 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT0YCH1 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH1 << 16) /**< Shifted mode APORT0YCH1 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT0YCH2 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH2 << 16) /**< Shifted mode APORT0YCH2 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT0YCH3 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH3 << 16) /**< Shifted mode APORT0YCH3 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT0YCH4 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH4 << 16) /**< Shifted mode APORT0YCH4 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT0YCH5 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH5 << 16) /**< Shifted mode APORT0YCH5 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT0YCH6 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH6 << 16) /**< Shifted mode APORT0YCH6 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT0YCH7 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH7 << 16) /**< Shifted mode APORT0YCH7 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT0YCH8 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH8 << 16) /**< Shifted mode APORT0YCH8 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT0YCH9 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH9 << 16) /**< Shifted mode APORT0YCH9 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT0YCH10 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH10 << 16) /**< Shifted mode APORT0YCH10 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT0YCH11 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH11 << 16) /**< Shifted mode APORT0YCH11 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT0YCH12 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH12 << 16) /**< Shifted mode APORT0YCH12 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT0YCH13 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH13 << 16) /**< Shifted mode APORT0YCH13 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT0YCH14 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH14 << 16) /**< Shifted mode APORT0YCH14 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT0YCH15 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH15 << 16) /**< Shifted mode APORT0YCH15 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT1XCH0 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH0 << 16) /**< Shifted mode APORT1XCH0 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT1YCH1 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH1 << 16) /**< Shifted mode APORT1YCH1 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT1XCH2 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH2 << 16) /**< Shifted mode APORT1XCH2 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT1YCH3 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH3 << 16) /**< Shifted mode APORT1YCH3 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT1XCH4 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH4 << 16) /**< Shifted mode APORT1XCH4 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT1YCH5 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH5 << 16) /**< Shifted mode APORT1YCH5 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT1XCH6 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH6 << 16) /**< Shifted mode APORT1XCH6 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT1YCH7 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH7 << 16) /**< Shifted mode APORT1YCH7 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT1XCH8 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH8 << 16) /**< Shifted mode APORT1XCH8 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT1YCH9 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH9 << 16) /**< Shifted mode APORT1YCH9 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT1XCH10 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH10 << 16) /**< Shifted mode APORT1XCH10 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT1YCH11 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH11 << 16) /**< Shifted mode APORT1YCH11 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT1XCH12 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH12 << 16) /**< Shifted mode APORT1XCH12 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT1YCH13 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH13 << 16) /**< Shifted mode APORT1YCH13 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT1XCH14 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH14 << 16) /**< Shifted mode APORT1XCH14 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT1YCH15 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH15 << 16) /**< Shifted mode APORT1YCH15 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT1XCH16 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH16 << 16) /**< Shifted mode APORT1XCH16 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT1YCH17 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH17 << 16) /**< Shifted mode APORT1YCH17 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT1XCH18 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH18 << 16) /**< Shifted mode APORT1XCH18 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT1YCH19 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH19 << 16) /**< Shifted mode APORT1YCH19 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT1XCH20 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH20 << 16) /**< Shifted mode APORT1XCH20 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT1YCH21 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH21 << 16) /**< Shifted mode APORT1YCH21 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT1XCH22 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH22 << 16) /**< Shifted mode APORT1XCH22 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT1YCH23 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH23 << 16) /**< Shifted mode APORT1YCH23 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT1XCH24 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH24 << 16) /**< Shifted mode APORT1XCH24 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT1YCH25 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH25 << 16) /**< Shifted mode APORT1YCH25 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT1XCH26 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH26 << 16) /**< Shifted mode APORT1XCH26 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT1YCH27 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH27 << 16) /**< Shifted mode APORT1YCH27 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT1XCH28 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH28 << 16) /**< Shifted mode APORT1XCH28 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT1YCH29 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH29 << 16) /**< Shifted mode APORT1YCH29 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT1XCH30 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH30 << 16) /**< Shifted mode APORT1XCH30 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT1YCH31 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH31 << 16) /**< Shifted mode APORT1YCH31 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT2YCH0 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH0 << 16) /**< Shifted mode APORT2YCH0 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT2XCH1 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH1 << 16) /**< Shifted mode APORT2XCH1 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT2YCH2 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH2 << 16) /**< Shifted mode APORT2YCH2 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT2XCH3 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH3 << 16) /**< Shifted mode APORT2XCH3 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT2YCH4 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH4 << 16) /**< Shifted mode APORT2YCH4 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT2XCH5 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH5 << 16) /**< Shifted mode APORT2XCH5 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT2YCH6 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH6 << 16) /**< Shifted mode APORT2YCH6 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT2XCH7 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH7 << 16) /**< Shifted mode APORT2XCH7 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT2YCH8 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH8 << 16) /**< Shifted mode APORT2YCH8 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT2XCH9 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH9 << 16) /**< Shifted mode APORT2XCH9 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT2YCH10 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH10 << 16) /**< Shifted mode APORT2YCH10 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT2XCH11 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH11 << 16) /**< Shifted mode APORT2XCH11 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT2YCH12 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH12 << 16) /**< Shifted mode APORT2YCH12 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT2XCH13 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH13 << 16) /**< Shifted mode APORT2XCH13 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT2YCH14 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH14 << 16) /**< Shifted mode APORT2YCH14 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT2XCH15 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH15 << 16) /**< Shifted mode APORT2XCH15 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT2YCH16 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH16 << 16) /**< Shifted mode APORT2YCH16 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT2XCH17 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH17 << 16) /**< Shifted mode APORT2XCH17 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT2YCH18 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH18 << 16) /**< Shifted mode APORT2YCH18 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT2XCH19 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH19 << 16) /**< Shifted mode APORT2XCH19 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT2YCH20 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH20 << 16) /**< Shifted mode APORT2YCH20 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT2XCH21 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH21 << 16) /**< Shifted mode APORT2XCH21 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT2YCH22 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH22 << 16) /**< Shifted mode APORT2YCH22 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT2XCH23 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH23 << 16) /**< Shifted mode APORT2XCH23 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT2YCH24 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH24 << 16) /**< Shifted mode APORT2YCH24 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT2XCH25 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH25 << 16) /**< Shifted mode APORT2XCH25 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT2YCH26 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH26 << 16) /**< Shifted mode APORT2YCH26 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT2XCH27 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH27 << 16) /**< Shifted mode APORT2XCH27 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT2YCH28 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH28 << 16) /**< Shifted mode APORT2YCH28 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT2XCH29 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH29 << 16) /**< Shifted mode APORT2XCH29 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT2YCH30 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH30 << 16) /**< Shifted mode APORT2YCH30 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT2XCH31 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH31 << 16) /**< Shifted mode APORT2XCH31 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT3XCH0 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH0 << 16) /**< Shifted mode APORT3XCH0 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT3YCH1 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH1 << 16) /**< Shifted mode APORT3YCH1 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT3XCH2 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH2 << 16) /**< Shifted mode APORT3XCH2 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT3YCH3 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH3 << 16) /**< Shifted mode APORT3YCH3 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT3XCH4 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH4 << 16) /**< Shifted mode APORT3XCH4 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT3YCH5 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH5 << 16) /**< Shifted mode APORT3YCH5 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT3XCH6 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH6 << 16) /**< Shifted mode APORT3XCH6 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT3YCH7 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH7 << 16) /**< Shifted mode APORT3YCH7 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT3XCH8 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH8 << 16) /**< Shifted mode APORT3XCH8 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT3YCH9 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH9 << 16) /**< Shifted mode APORT3YCH9 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT3XCH10 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH10 << 16) /**< Shifted mode APORT3XCH10 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT3YCH11 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH11 << 16) /**< Shifted mode APORT3YCH11 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT3XCH12 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH12 << 16) /**< Shifted mode APORT3XCH12 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT3YCH13 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH13 << 16) /**< Shifted mode APORT3YCH13 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT3XCH14 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH14 << 16) /**< Shifted mode APORT3XCH14 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT3YCH15 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH15 << 16) /**< Shifted mode APORT3YCH15 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT3XCH16 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH16 << 16) /**< Shifted mode APORT3XCH16 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT3YCH17 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH17 << 16) /**< Shifted mode APORT3YCH17 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT3XCH18 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH18 << 16) /**< Shifted mode APORT3XCH18 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT3YCH19 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH19 << 16) /**< Shifted mode APORT3YCH19 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT3XCH20 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH20 << 16) /**< Shifted mode APORT3XCH20 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT3YCH21 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH21 << 16) /**< Shifted mode APORT3YCH21 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT3XCH22 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH22 << 16) /**< Shifted mode APORT3XCH22 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT3YCH23 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH23 << 16) /**< Shifted mode APORT3YCH23 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT3XCH24 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH24 << 16) /**< Shifted mode APORT3XCH24 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT3YCH25 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH25 << 16) /**< Shifted mode APORT3YCH25 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT3XCH26 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH26 << 16) /**< Shifted mode APORT3XCH26 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT3YCH27 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH27 << 16) /**< Shifted mode APORT3YCH27 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT3XCH28 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH28 << 16) /**< Shifted mode APORT3XCH28 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT3YCH29 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH29 << 16) /**< Shifted mode APORT3YCH29 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT3XCH30 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH30 << 16) /**< Shifted mode APORT3XCH30 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT3YCH31 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH31 << 16) /**< Shifted mode APORT3YCH31 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT4YCH0 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH0 << 16) /**< Shifted mode APORT4YCH0 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT4XCH1 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH1 << 16) /**< Shifted mode APORT4XCH1 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT4YCH2 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH2 << 16) /**< Shifted mode APORT4YCH2 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT4XCH3 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH3 << 16) /**< Shifted mode APORT4XCH3 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT4YCH4 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH4 << 16) /**< Shifted mode APORT4YCH4 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT4XCH5 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH5 << 16) /**< Shifted mode APORT4XCH5 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT4YCH6 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH6 << 16) /**< Shifted mode APORT4YCH6 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT4XCH7 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH7 << 16) /**< Shifted mode APORT4XCH7 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT4YCH8 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH8 << 16) /**< Shifted mode APORT4YCH8 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT4XCH9 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH9 << 16) /**< Shifted mode APORT4XCH9 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT4YCH10 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH10 << 16) /**< Shifted mode APORT4YCH10 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT4XCH11 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH11 << 16) /**< Shifted mode APORT4XCH11 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT4YCH12 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH12 << 16) /**< Shifted mode APORT4YCH12 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT4XCH13 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH13 << 16) /**< Shifted mode APORT4XCH13 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT4YCH14 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH14 << 16) /**< Shifted mode APORT4YCH14 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT4XCH15 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH15 << 16) /**< Shifted mode APORT4XCH15 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT4YCH16 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH16 << 16) /**< Shifted mode APORT4YCH16 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT4XCH17 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH17 << 16) /**< Shifted mode APORT4XCH17 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT4YCH18 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH18 << 16) /**< Shifted mode APORT4YCH18 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT4XCH19 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH19 << 16) /**< Shifted mode APORT4XCH19 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT4YCH20 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH20 << 16) /**< Shifted mode APORT4YCH20 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT4XCH21 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH21 << 16) /**< Shifted mode APORT4XCH21 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT4YCH22 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH22 << 16) /**< Shifted mode APORT4YCH22 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT4XCH23 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH23 << 16) /**< Shifted mode APORT4XCH23 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT4YCH24 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH24 << 16) /**< Shifted mode APORT4YCH24 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT4XCH25 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH25 << 16) /**< Shifted mode APORT4XCH25 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT4YCH26 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH26 << 16) /**< Shifted mode APORT4YCH26 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT4XCH27 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH27 << 16) /**< Shifted mode APORT4XCH27 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT4YCH28 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH28 << 16) /**< Shifted mode APORT4YCH28 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT4XCH29 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH29 << 16) /**< Shifted mode APORT4XCH29 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT4YCH30 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH30 << 16) /**< Shifted mode APORT4YCH30 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_APORT4XCH31 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH31 << 16) /**< Shifted mode APORT4XCH31 for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_TESTN (_ADC_SINGLECTRL_NEGSEL_TESTN << 16) /**< Shifted mode TESTN for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_DEFAULT (_ADC_SINGLECTRL_NEGSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_NEGSEL_VSS (_ADC_SINGLECTRL_NEGSEL_VSS << 16) /**< Shifted mode VSS for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_AT_SHIFT 24 /**< Shift value for ADC_AT */ #define _ADC_SINGLECTRL_AT_MASK 0xF000000UL /**< Bit mask for ADC_AT */ #define _ADC_SINGLECTRL_AT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_AT_1CYCLE 0x00000000UL /**< Mode 1CYCLE for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_AT_2CYCLES 0x00000001UL /**< Mode 2CYCLES for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_AT_3CYCLES 0x00000002UL /**< Mode 3CYCLES for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_AT_4CYCLES 0x00000003UL /**< Mode 4CYCLES for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_AT_8CYCLES 0x00000004UL /**< Mode 8CYCLES for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_AT_16CYCLES 0x00000005UL /**< Mode 16CYCLES for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_AT_32CYCLES 0x00000006UL /**< Mode 32CYCLES for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_AT_64CYCLES 0x00000007UL /**< Mode 64CYCLES for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_AT_128CYCLES 0x00000008UL /**< Mode 128CYCLES for ADC_SINGLECTRL */ #define _ADC_SINGLECTRL_AT_256CYCLES 0x00000009UL /**< Mode 256CYCLES for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_AT_DEFAULT (_ADC_SINGLECTRL_AT_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_AT_1CYCLE (_ADC_SINGLECTRL_AT_1CYCLE << 24) /**< Shifted mode 1CYCLE for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_AT_2CYCLES (_ADC_SINGLECTRL_AT_2CYCLES << 24) /**< Shifted mode 2CYCLES for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_AT_3CYCLES (_ADC_SINGLECTRL_AT_3CYCLES << 24) /**< Shifted mode 3CYCLES for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_AT_4CYCLES (_ADC_SINGLECTRL_AT_4CYCLES << 24) /**< Shifted mode 4CYCLES for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_AT_8CYCLES (_ADC_SINGLECTRL_AT_8CYCLES << 24) /**< Shifted mode 8CYCLES for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_AT_16CYCLES (_ADC_SINGLECTRL_AT_16CYCLES << 24) /**< Shifted mode 16CYCLES for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_AT_32CYCLES (_ADC_SINGLECTRL_AT_32CYCLES << 24) /**< Shifted mode 32CYCLES for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_AT_64CYCLES (_ADC_SINGLECTRL_AT_64CYCLES << 24) /**< Shifted mode 64CYCLES for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_AT_128CYCLES (_ADC_SINGLECTRL_AT_128CYCLES << 24) /**< Shifted mode 128CYCLES for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_AT_256CYCLES (_ADC_SINGLECTRL_AT_256CYCLES << 24) /**< Shifted mode 256CYCLES for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_PRSEN (0x1UL << 29) /**< Single Channel PRS Trigger Enable */ #define _ADC_SINGLECTRL_PRSEN_SHIFT 29 /**< Shift value for ADC_PRSEN */ #define _ADC_SINGLECTRL_PRSEN_MASK 0x20000000UL /**< Bit mask for ADC_PRSEN */ #define _ADC_SINGLECTRL_PRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_PRSEN_DEFAULT (_ADC_SINGLECTRL_PRSEN_DEFAULT << 29) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_CMPEN (0x1UL << 31) /**< Compare Logic Enable for Single Channel */ #define _ADC_SINGLECTRL_CMPEN_SHIFT 31 /**< Shift value for ADC_CMPEN */ #define _ADC_SINGLECTRL_CMPEN_MASK 0x80000000UL /**< Bit mask for ADC_CMPEN */ #define _ADC_SINGLECTRL_CMPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */ #define ADC_SINGLECTRL_CMPEN_DEFAULT (_ADC_SINGLECTRL_CMPEN_DEFAULT << 31) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */ /* Bit fields for ADC SINGLECTRLX */ #define _ADC_SINGLECTRLX_RESETVALUE 0x00000000UL /**< Default value for ADC_SINGLECTRLX */ #define _ADC_SINGLECTRLX_MASK 0xEFDF7FFFUL /**< Mask for ADC_SINGLECTRLX */ #define _ADC_SINGLECTRLX_VREFSEL_SHIFT 0 /**< Shift value for ADC_VREFSEL */ #define _ADC_SINGLECTRLX_VREFSEL_MASK 0x7UL /**< Bit mask for ADC_VREFSEL */ #define _ADC_SINGLECTRLX_VREFSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRLX */ #define _ADC_SINGLECTRLX_VREFSEL_VBGR 0x00000000UL /**< Mode VBGR for ADC_SINGLECTRLX */ #define _ADC_SINGLECTRLX_VREFSEL_VDDXWATT 0x00000001UL /**< Mode VDDXWATT for ADC_SINGLECTRLX */ #define _ADC_SINGLECTRLX_VREFSEL_VREFPWATT 0x00000002UL /**< Mode VREFPWATT for ADC_SINGLECTRLX */ #define _ADC_SINGLECTRLX_VREFSEL_VREFP 0x00000003UL /**< Mode VREFP for ADC_SINGLECTRLX */ #define _ADC_SINGLECTRLX_VREFSEL_VENTROPY 0x00000004UL /**< Mode VENTROPY for ADC_SINGLECTRLX */ #define _ADC_SINGLECTRLX_VREFSEL_VREFPNWATT 0x00000005UL /**< Mode VREFPNWATT for ADC_SINGLECTRLX */ #define _ADC_SINGLECTRLX_VREFSEL_VREFPN 0x00000006UL /**< Mode VREFPN for ADC_SINGLECTRLX */ #define _ADC_SINGLECTRLX_VREFSEL_VBGRLOW 0x00000007UL /**< Mode VBGRLOW for ADC_SINGLECTRLX */ #define ADC_SINGLECTRLX_VREFSEL_DEFAULT (_ADC_SINGLECTRLX_VREFSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */ #define ADC_SINGLECTRLX_VREFSEL_VBGR (_ADC_SINGLECTRLX_VREFSEL_VBGR << 0) /**< Shifted mode VBGR for ADC_SINGLECTRLX */ #define ADC_SINGLECTRLX_VREFSEL_VDDXWATT (_ADC_SINGLECTRLX_VREFSEL_VDDXWATT << 0) /**< Shifted mode VDDXWATT for ADC_SINGLECTRLX */ #define ADC_SINGLECTRLX_VREFSEL_VREFPWATT (_ADC_SINGLECTRLX_VREFSEL_VREFPWATT << 0) /**< Shifted mode VREFPWATT for ADC_SINGLECTRLX */ #define ADC_SINGLECTRLX_VREFSEL_VREFP (_ADC_SINGLECTRLX_VREFSEL_VREFP << 0) /**< Shifted mode VREFP for ADC_SINGLECTRLX */ #define ADC_SINGLECTRLX_VREFSEL_VENTROPY (_ADC_SINGLECTRLX_VREFSEL_VENTROPY << 0) /**< Shifted mode VENTROPY for ADC_SINGLECTRLX */ #define ADC_SINGLECTRLX_VREFSEL_VREFPNWATT (_ADC_SINGLECTRLX_VREFSEL_VREFPNWATT << 0) /**< Shifted mode VREFPNWATT for ADC_SINGLECTRLX */ #define ADC_SINGLECTRLX_VREFSEL_VREFPN (_ADC_SINGLECTRLX_VREFSEL_VREFPN << 0) /**< Shifted mode VREFPN for ADC_SINGLECTRLX */ #define ADC_SINGLECTRLX_VREFSEL_VBGRLOW (_ADC_SINGLECTRLX_VREFSEL_VBGRLOW << 0) /**< Shifted mode VBGRLOW for ADC_SINGLECTRLX */ #define ADC_SINGLECTRLX_VREFATTFIX (0x1UL << 3) /**< Enable Fixed Scaling on VREF */ #define _ADC_SINGLECTRLX_VREFATTFIX_SHIFT 3 /**< Shift value for ADC_VREFATTFIX */ #define _ADC_SINGLECTRLX_VREFATTFIX_MASK 0x8UL /**< Bit mask for ADC_VREFATTFIX */ #define _ADC_SINGLECTRLX_VREFATTFIX_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRLX */ #define ADC_SINGLECTRLX_VREFATTFIX_DEFAULT (_ADC_SINGLECTRLX_VREFATTFIX_DEFAULT << 3) /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */ #define _ADC_SINGLECTRLX_VREFATT_SHIFT 4 /**< Shift value for ADC_VREFATT */ #define _ADC_SINGLECTRLX_VREFATT_MASK 0xF0UL /**< Bit mask for ADC_VREFATT */ #define _ADC_SINGLECTRLX_VREFATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRLX */ #define ADC_SINGLECTRLX_VREFATT_DEFAULT (_ADC_SINGLECTRLX_VREFATT_DEFAULT << 4) /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */ #define _ADC_SINGLECTRLX_VINATT_SHIFT 8 /**< Shift value for ADC_VINATT */ #define _ADC_SINGLECTRLX_VINATT_MASK 0xF00UL /**< Bit mask for ADC_VINATT */ #define _ADC_SINGLECTRLX_VINATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRLX */ #define ADC_SINGLECTRLX_VINATT_DEFAULT (_ADC_SINGLECTRLX_VINATT_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */ #define _ADC_SINGLECTRLX_DVL_SHIFT 12 /**< Shift value for ADC_DVL */ #define _ADC_SINGLECTRLX_DVL_MASK 0x3000UL /**< Bit mask for ADC_DVL */ #define _ADC_SINGLECTRLX_DVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRLX */ #define ADC_SINGLECTRLX_DVL_DEFAULT (_ADC_SINGLECTRLX_DVL_DEFAULT << 12) /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */ #define ADC_SINGLECTRLX_FIFOOFACT (0x1UL << 14) /**< Single Channel FIFO Overflow Action */ #define _ADC_SINGLECTRLX_FIFOOFACT_SHIFT 14 /**< Shift value for ADC_FIFOOFACT */ #define _ADC_SINGLECTRLX_FIFOOFACT_MASK 0x4000UL /**< Bit mask for ADC_FIFOOFACT */ #define _ADC_SINGLECTRLX_FIFOOFACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRLX */ #define _ADC_SINGLECTRLX_FIFOOFACT_DISCARD 0x00000000UL /**< Mode DISCARD for ADC_SINGLECTRLX */ #define _ADC_SINGLECTRLX_FIFOOFACT_OVERWRITE 0x00000001UL /**< Mode OVERWRITE for ADC_SINGLECTRLX */ #define ADC_SINGLECTRLX_FIFOOFACT_DEFAULT (_ADC_SINGLECTRLX_FIFOOFACT_DEFAULT << 14) /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */ #define ADC_SINGLECTRLX_FIFOOFACT_DISCARD (_ADC_SINGLECTRLX_FIFOOFACT_DISCARD << 14) /**< Shifted mode DISCARD for ADC_SINGLECTRLX */ #define ADC_SINGLECTRLX_FIFOOFACT_OVERWRITE (_ADC_SINGLECTRLX_FIFOOFACT_OVERWRITE << 14) /**< Shifted mode OVERWRITE for ADC_SINGLECTRLX */ #define ADC_SINGLECTRLX_PRSMODE (0x1UL << 16) /**< Single Channel PRS Trigger Mode */ #define _ADC_SINGLECTRLX_PRSMODE_SHIFT 16 /**< Shift value for ADC_PRSMODE */ #define _ADC_SINGLECTRLX_PRSMODE_MASK 0x10000UL /**< Bit mask for ADC_PRSMODE */ #define _ADC_SINGLECTRLX_PRSMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRLX */ #define _ADC_SINGLECTRLX_PRSMODE_PULSED 0x00000000UL /**< Mode PULSED for ADC_SINGLECTRLX */ #define _ADC_SINGLECTRLX_PRSMODE_TIMED 0x00000001UL /**< Mode TIMED for ADC_SINGLECTRLX */ #define ADC_SINGLECTRLX_PRSMODE_DEFAULT (_ADC_SINGLECTRLX_PRSMODE_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */ #define ADC_SINGLECTRLX_PRSMODE_PULSED (_ADC_SINGLECTRLX_PRSMODE_PULSED << 16) /**< Shifted mode PULSED for ADC_SINGLECTRLX */ #define ADC_SINGLECTRLX_PRSMODE_TIMED (_ADC_SINGLECTRLX_PRSMODE_TIMED << 16) /**< Shifted mode TIMED for ADC_SINGLECTRLX */ #define _ADC_SINGLECTRLX_PRSSEL_SHIFT 17 /**< Shift value for ADC_PRSSEL */ #define _ADC_SINGLECTRLX_PRSSEL_MASK 0x1E0000UL /**< Bit mask for ADC_PRSSEL */ #define _ADC_SINGLECTRLX_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRLX */ #define _ADC_SINGLECTRLX_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for ADC_SINGLECTRLX */ #define _ADC_SINGLECTRLX_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for ADC_SINGLECTRLX */ #define _ADC_SINGLECTRLX_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for ADC_SINGLECTRLX */ #define _ADC_SINGLECTRLX_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for ADC_SINGLECTRLX */ #define _ADC_SINGLECTRLX_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for ADC_SINGLECTRLX */ #define _ADC_SINGLECTRLX_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for ADC_SINGLECTRLX */ #define _ADC_SINGLECTRLX_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for ADC_SINGLECTRLX */ #define _ADC_SINGLECTRLX_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for ADC_SINGLECTRLX */ #define _ADC_SINGLECTRLX_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for ADC_SINGLECTRLX */ #define _ADC_SINGLECTRLX_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for ADC_SINGLECTRLX */ #define _ADC_SINGLECTRLX_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for ADC_SINGLECTRLX */ #define _ADC_SINGLECTRLX_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for ADC_SINGLECTRLX */ #define ADC_SINGLECTRLX_PRSSEL_DEFAULT (_ADC_SINGLECTRLX_PRSSEL_DEFAULT << 17) /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */ #define ADC_SINGLECTRLX_PRSSEL_PRSCH0 (_ADC_SINGLECTRLX_PRSSEL_PRSCH0 << 17) /**< Shifted mode PRSCH0 for ADC_SINGLECTRLX */ #define ADC_SINGLECTRLX_PRSSEL_PRSCH1 (_ADC_SINGLECTRLX_PRSSEL_PRSCH1 << 17) /**< Shifted mode PRSCH1 for ADC_SINGLECTRLX */ #define ADC_SINGLECTRLX_PRSSEL_PRSCH2 (_ADC_SINGLECTRLX_PRSSEL_PRSCH2 << 17) /**< Shifted mode PRSCH2 for ADC_SINGLECTRLX */ #define ADC_SINGLECTRLX_PRSSEL_PRSCH3 (_ADC_SINGLECTRLX_PRSSEL_PRSCH3 << 17) /**< Shifted mode PRSCH3 for ADC_SINGLECTRLX */ #define ADC_SINGLECTRLX_PRSSEL_PRSCH4 (_ADC_SINGLECTRLX_PRSSEL_PRSCH4 << 17) /**< Shifted mode PRSCH4 for ADC_SINGLECTRLX */ #define ADC_SINGLECTRLX_PRSSEL_PRSCH5 (_ADC_SINGLECTRLX_PRSSEL_PRSCH5 << 17) /**< Shifted mode PRSCH5 for ADC_SINGLECTRLX */ #define ADC_SINGLECTRLX_PRSSEL_PRSCH6 (_ADC_SINGLECTRLX_PRSSEL_PRSCH6 << 17) /**< Shifted mode PRSCH6 for ADC_SINGLECTRLX */ #define ADC_SINGLECTRLX_PRSSEL_PRSCH7 (_ADC_SINGLECTRLX_PRSSEL_PRSCH7 << 17) /**< Shifted mode PRSCH7 for ADC_SINGLECTRLX */ #define ADC_SINGLECTRLX_PRSSEL_PRSCH8 (_ADC_SINGLECTRLX_PRSSEL_PRSCH8 << 17) /**< Shifted mode PRSCH8 for ADC_SINGLECTRLX */ #define ADC_SINGLECTRLX_PRSSEL_PRSCH9 (_ADC_SINGLECTRLX_PRSSEL_PRSCH9 << 17) /**< Shifted mode PRSCH9 for ADC_SINGLECTRLX */ #define ADC_SINGLECTRLX_PRSSEL_PRSCH10 (_ADC_SINGLECTRLX_PRSSEL_PRSCH10 << 17) /**< Shifted mode PRSCH10 for ADC_SINGLECTRLX */ #define ADC_SINGLECTRLX_PRSSEL_PRSCH11 (_ADC_SINGLECTRLX_PRSSEL_PRSCH11 << 17) /**< Shifted mode PRSCH11 for ADC_SINGLECTRLX */ #define _ADC_SINGLECTRLX_CONVSTARTDELAY_SHIFT 22 /**< Shift value for ADC_CONVSTARTDELAY */ #define _ADC_SINGLECTRLX_CONVSTARTDELAY_MASK 0x7C00000UL /**< Bit mask for ADC_CONVSTARTDELAY */ #define _ADC_SINGLECTRLX_CONVSTARTDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRLX */ #define ADC_SINGLECTRLX_CONVSTARTDELAY_DEFAULT (_ADC_SINGLECTRLX_CONVSTARTDELAY_DEFAULT << 22) /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */ #define ADC_SINGLECTRLX_CONVSTARTDELAYEN (0x1UL << 27) /**< Enable Delaying Next Conversion Start */ #define _ADC_SINGLECTRLX_CONVSTARTDELAYEN_SHIFT 27 /**< Shift value for ADC_CONVSTARTDELAYEN */ #define _ADC_SINGLECTRLX_CONVSTARTDELAYEN_MASK 0x8000000UL /**< Bit mask for ADC_CONVSTARTDELAYEN */ #define _ADC_SINGLECTRLX_CONVSTARTDELAYEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRLX */ #define ADC_SINGLECTRLX_CONVSTARTDELAYEN_DEFAULT (_ADC_SINGLECTRLX_CONVSTARTDELAYEN_DEFAULT << 27) /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */ #define _ADC_SINGLECTRLX_REPDELAY_SHIFT 29 /**< Shift value for ADC_REPDELAY */ #define _ADC_SINGLECTRLX_REPDELAY_MASK 0xE0000000UL /**< Bit mask for ADC_REPDELAY */ #define _ADC_SINGLECTRLX_REPDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRLX */ #define _ADC_SINGLECTRLX_REPDELAY_NODELAY 0x00000000UL /**< Mode NODELAY for ADC_SINGLECTRLX */ #define _ADC_SINGLECTRLX_REPDELAY_4CYCLES 0x00000001UL /**< Mode 4CYCLES for ADC_SINGLECTRLX */ #define _ADC_SINGLECTRLX_REPDELAY_8CYCLES 0x00000002UL /**< Mode 8CYCLES for ADC_SINGLECTRLX */ #define _ADC_SINGLECTRLX_REPDELAY_16CYCLES 0x00000003UL /**< Mode 16CYCLES for ADC_SINGLECTRLX */ #define _ADC_SINGLECTRLX_REPDELAY_32CYCLES 0x00000004UL /**< Mode 32CYCLES for ADC_SINGLECTRLX */ #define _ADC_SINGLECTRLX_REPDELAY_64CYCLES 0x00000005UL /**< Mode 64CYCLES for ADC_SINGLECTRLX */ #define _ADC_SINGLECTRLX_REPDELAY_128CYCLES 0x00000006UL /**< Mode 128CYCLES for ADC_SINGLECTRLX */ #define _ADC_SINGLECTRLX_REPDELAY_256CYCLES 0x00000007UL /**< Mode 256CYCLES for ADC_SINGLECTRLX */ #define ADC_SINGLECTRLX_REPDELAY_DEFAULT (_ADC_SINGLECTRLX_REPDELAY_DEFAULT << 29) /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */ #define ADC_SINGLECTRLX_REPDELAY_NODELAY (_ADC_SINGLECTRLX_REPDELAY_NODELAY << 29) /**< Shifted mode NODELAY for ADC_SINGLECTRLX */ #define ADC_SINGLECTRLX_REPDELAY_4CYCLES (_ADC_SINGLECTRLX_REPDELAY_4CYCLES << 29) /**< Shifted mode 4CYCLES for ADC_SINGLECTRLX */ #define ADC_SINGLECTRLX_REPDELAY_8CYCLES (_ADC_SINGLECTRLX_REPDELAY_8CYCLES << 29) /**< Shifted mode 8CYCLES for ADC_SINGLECTRLX */ #define ADC_SINGLECTRLX_REPDELAY_16CYCLES (_ADC_SINGLECTRLX_REPDELAY_16CYCLES << 29) /**< Shifted mode 16CYCLES for ADC_SINGLECTRLX */ #define ADC_SINGLECTRLX_REPDELAY_32CYCLES (_ADC_SINGLECTRLX_REPDELAY_32CYCLES << 29) /**< Shifted mode 32CYCLES for ADC_SINGLECTRLX */ #define ADC_SINGLECTRLX_REPDELAY_64CYCLES (_ADC_SINGLECTRLX_REPDELAY_64CYCLES << 29) /**< Shifted mode 64CYCLES for ADC_SINGLECTRLX */ #define ADC_SINGLECTRLX_REPDELAY_128CYCLES (_ADC_SINGLECTRLX_REPDELAY_128CYCLES << 29) /**< Shifted mode 128CYCLES for ADC_SINGLECTRLX */ #define ADC_SINGLECTRLX_REPDELAY_256CYCLES (_ADC_SINGLECTRLX_REPDELAY_256CYCLES << 29) /**< Shifted mode 256CYCLES for ADC_SINGLECTRLX */ /* Bit fields for ADC SCANCTRL */ #define _ADC_SCANCTRL_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANCTRL */ #define _ADC_SCANCTRL_MASK 0xAF0000FFUL /**< Mask for ADC_SCANCTRL */ #define ADC_SCANCTRL_REP (0x1UL << 0) /**< Scan Sequence Repetitive Mode */ #define _ADC_SCANCTRL_REP_SHIFT 0 /**< Shift value for ADC_REP */ #define _ADC_SCANCTRL_REP_MASK 0x1UL /**< Bit mask for ADC_REP */ #define _ADC_SCANCTRL_REP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */ #define ADC_SCANCTRL_REP_DEFAULT (_ADC_SCANCTRL_REP_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANCTRL */ #define ADC_SCANCTRL_DIFF (0x1UL << 1) /**< Scan Sequence Differential Mode */ #define _ADC_SCANCTRL_DIFF_SHIFT 1 /**< Shift value for ADC_DIFF */ #define _ADC_SCANCTRL_DIFF_MASK 0x2UL /**< Bit mask for ADC_DIFF */ #define _ADC_SCANCTRL_DIFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */ #define ADC_SCANCTRL_DIFF_DEFAULT (_ADC_SCANCTRL_DIFF_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_SCANCTRL */ #define ADC_SCANCTRL_ADJ (0x1UL << 2) /**< Scan Sequence Result Adjustment */ #define _ADC_SCANCTRL_ADJ_SHIFT 2 /**< Shift value for ADC_ADJ */ #define _ADC_SCANCTRL_ADJ_MASK 0x4UL /**< Bit mask for ADC_ADJ */ #define _ADC_SCANCTRL_ADJ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */ #define _ADC_SCANCTRL_ADJ_RIGHT 0x00000000UL /**< Mode RIGHT for ADC_SCANCTRL */ #define _ADC_SCANCTRL_ADJ_LEFT 0x00000001UL /**< Mode LEFT for ADC_SCANCTRL */ #define ADC_SCANCTRL_ADJ_DEFAULT (_ADC_SCANCTRL_ADJ_DEFAULT << 2) /**< Shifted mode DEFAULT for ADC_SCANCTRL */ #define ADC_SCANCTRL_ADJ_RIGHT (_ADC_SCANCTRL_ADJ_RIGHT << 2) /**< Shifted mode RIGHT for ADC_SCANCTRL */ #define ADC_SCANCTRL_ADJ_LEFT (_ADC_SCANCTRL_ADJ_LEFT << 2) /**< Shifted mode LEFT for ADC_SCANCTRL */ #define _ADC_SCANCTRL_RES_SHIFT 3 /**< Shift value for ADC_RES */ #define _ADC_SCANCTRL_RES_MASK 0x18UL /**< Bit mask for ADC_RES */ #define _ADC_SCANCTRL_RES_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */ #define _ADC_SCANCTRL_RES_12BIT 0x00000000UL /**< Mode 12BIT for ADC_SCANCTRL */ #define _ADC_SCANCTRL_RES_8BIT 0x00000001UL /**< Mode 8BIT for ADC_SCANCTRL */ #define _ADC_SCANCTRL_RES_6BIT 0x00000002UL /**< Mode 6BIT for ADC_SCANCTRL */ #define _ADC_SCANCTRL_RES_OVS 0x00000003UL /**< Mode OVS for ADC_SCANCTRL */ #define ADC_SCANCTRL_RES_DEFAULT (_ADC_SCANCTRL_RES_DEFAULT << 3) /**< Shifted mode DEFAULT for ADC_SCANCTRL */ #define ADC_SCANCTRL_RES_12BIT (_ADC_SCANCTRL_RES_12BIT << 3) /**< Shifted mode 12BIT for ADC_SCANCTRL */ #define ADC_SCANCTRL_RES_8BIT (_ADC_SCANCTRL_RES_8BIT << 3) /**< Shifted mode 8BIT for ADC_SCANCTRL */ #define ADC_SCANCTRL_RES_6BIT (_ADC_SCANCTRL_RES_6BIT << 3) /**< Shifted mode 6BIT for ADC_SCANCTRL */ #define ADC_SCANCTRL_RES_OVS (_ADC_SCANCTRL_RES_OVS << 3) /**< Shifted mode OVS for ADC_SCANCTRL */ #define _ADC_SCANCTRL_REF_SHIFT 5 /**< Shift value for ADC_REF */ #define _ADC_SCANCTRL_REF_MASK 0xE0UL /**< Bit mask for ADC_REF */ #define _ADC_SCANCTRL_REF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */ #define _ADC_SCANCTRL_REF_1V25 0x00000000UL /**< Mode 1V25 for ADC_SCANCTRL */ #define _ADC_SCANCTRL_REF_2V5 0x00000001UL /**< Mode 2V5 for ADC_SCANCTRL */ #define _ADC_SCANCTRL_REF_VDD 0x00000002UL /**< Mode VDD for ADC_SCANCTRL */ #define _ADC_SCANCTRL_REF_5V 0x00000003UL /**< Mode 5V for ADC_SCANCTRL */ #define _ADC_SCANCTRL_REF_EXTSINGLE 0x00000004UL /**< Mode EXTSINGLE for ADC_SCANCTRL */ #define _ADC_SCANCTRL_REF_2XEXTDIFF 0x00000005UL /**< Mode 2XEXTDIFF for ADC_SCANCTRL */ #define _ADC_SCANCTRL_REF_2XVDD 0x00000006UL /**< Mode 2XVDD for ADC_SCANCTRL */ #define _ADC_SCANCTRL_REF_CONF 0x00000007UL /**< Mode CONF for ADC_SCANCTRL */ #define ADC_SCANCTRL_REF_DEFAULT (_ADC_SCANCTRL_REF_DEFAULT << 5) /**< Shifted mode DEFAULT for ADC_SCANCTRL */ #define ADC_SCANCTRL_REF_1V25 (_ADC_SCANCTRL_REF_1V25 << 5) /**< Shifted mode 1V25 for ADC_SCANCTRL */ #define ADC_SCANCTRL_REF_2V5 (_ADC_SCANCTRL_REF_2V5 << 5) /**< Shifted mode 2V5 for ADC_SCANCTRL */ #define ADC_SCANCTRL_REF_VDD (_ADC_SCANCTRL_REF_VDD << 5) /**< Shifted mode VDD for ADC_SCANCTRL */ #define ADC_SCANCTRL_REF_5V (_ADC_SCANCTRL_REF_5V << 5) /**< Shifted mode 5V for ADC_SCANCTRL */ #define ADC_SCANCTRL_REF_EXTSINGLE (_ADC_SCANCTRL_REF_EXTSINGLE << 5) /**< Shifted mode EXTSINGLE for ADC_SCANCTRL */ #define ADC_SCANCTRL_REF_2XEXTDIFF (_ADC_SCANCTRL_REF_2XEXTDIFF << 5) /**< Shifted mode 2XEXTDIFF for ADC_SCANCTRL */ #define ADC_SCANCTRL_REF_2XVDD (_ADC_SCANCTRL_REF_2XVDD << 5) /**< Shifted mode 2XVDD for ADC_SCANCTRL */ #define ADC_SCANCTRL_REF_CONF (_ADC_SCANCTRL_REF_CONF << 5) /**< Shifted mode CONF for ADC_SCANCTRL */ #define _ADC_SCANCTRL_AT_SHIFT 24 /**< Shift value for ADC_AT */ #define _ADC_SCANCTRL_AT_MASK 0xF000000UL /**< Bit mask for ADC_AT */ #define _ADC_SCANCTRL_AT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */ #define _ADC_SCANCTRL_AT_1CYCLE 0x00000000UL /**< Mode 1CYCLE for ADC_SCANCTRL */ #define _ADC_SCANCTRL_AT_2CYCLES 0x00000001UL /**< Mode 2CYCLES for ADC_SCANCTRL */ #define _ADC_SCANCTRL_AT_3CYCLES 0x00000002UL /**< Mode 3CYCLES for ADC_SCANCTRL */ #define _ADC_SCANCTRL_AT_4CYCLES 0x00000003UL /**< Mode 4CYCLES for ADC_SCANCTRL */ #define _ADC_SCANCTRL_AT_8CYCLES 0x00000004UL /**< Mode 8CYCLES for ADC_SCANCTRL */ #define _ADC_SCANCTRL_AT_16CYCLES 0x00000005UL /**< Mode 16CYCLES for ADC_SCANCTRL */ #define _ADC_SCANCTRL_AT_32CYCLES 0x00000006UL /**< Mode 32CYCLES for ADC_SCANCTRL */ #define _ADC_SCANCTRL_AT_64CYCLES 0x00000007UL /**< Mode 64CYCLES for ADC_SCANCTRL */ #define _ADC_SCANCTRL_AT_128CYCLES 0x00000008UL /**< Mode 128CYCLES for ADC_SCANCTRL */ #define _ADC_SCANCTRL_AT_256CYCLES 0x00000009UL /**< Mode 256CYCLES for ADC_SCANCTRL */ #define ADC_SCANCTRL_AT_DEFAULT (_ADC_SCANCTRL_AT_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_SCANCTRL */ #define ADC_SCANCTRL_AT_1CYCLE (_ADC_SCANCTRL_AT_1CYCLE << 24) /**< Shifted mode 1CYCLE for ADC_SCANCTRL */ #define ADC_SCANCTRL_AT_2CYCLES (_ADC_SCANCTRL_AT_2CYCLES << 24) /**< Shifted mode 2CYCLES for ADC_SCANCTRL */ #define ADC_SCANCTRL_AT_3CYCLES (_ADC_SCANCTRL_AT_3CYCLES << 24) /**< Shifted mode 3CYCLES for ADC_SCANCTRL */ #define ADC_SCANCTRL_AT_4CYCLES (_ADC_SCANCTRL_AT_4CYCLES << 24) /**< Shifted mode 4CYCLES for ADC_SCANCTRL */ #define ADC_SCANCTRL_AT_8CYCLES (_ADC_SCANCTRL_AT_8CYCLES << 24) /**< Shifted mode 8CYCLES for ADC_SCANCTRL */ #define ADC_SCANCTRL_AT_16CYCLES (_ADC_SCANCTRL_AT_16CYCLES << 24) /**< Shifted mode 16CYCLES for ADC_SCANCTRL */ #define ADC_SCANCTRL_AT_32CYCLES (_ADC_SCANCTRL_AT_32CYCLES << 24) /**< Shifted mode 32CYCLES for ADC_SCANCTRL */ #define ADC_SCANCTRL_AT_64CYCLES (_ADC_SCANCTRL_AT_64CYCLES << 24) /**< Shifted mode 64CYCLES for ADC_SCANCTRL */ #define ADC_SCANCTRL_AT_128CYCLES (_ADC_SCANCTRL_AT_128CYCLES << 24) /**< Shifted mode 128CYCLES for ADC_SCANCTRL */ #define ADC_SCANCTRL_AT_256CYCLES (_ADC_SCANCTRL_AT_256CYCLES << 24) /**< Shifted mode 256CYCLES for ADC_SCANCTRL */ #define ADC_SCANCTRL_PRSEN (0x1UL << 29) /**< Scan Sequence PRS Trigger Enable */ #define _ADC_SCANCTRL_PRSEN_SHIFT 29 /**< Shift value for ADC_PRSEN */ #define _ADC_SCANCTRL_PRSEN_MASK 0x20000000UL /**< Bit mask for ADC_PRSEN */ #define _ADC_SCANCTRL_PRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */ #define ADC_SCANCTRL_PRSEN_DEFAULT (_ADC_SCANCTRL_PRSEN_DEFAULT << 29) /**< Shifted mode DEFAULT for ADC_SCANCTRL */ #define ADC_SCANCTRL_CMPEN (0x1UL << 31) /**< Compare Logic Enable for Scan */ #define _ADC_SCANCTRL_CMPEN_SHIFT 31 /**< Shift value for ADC_CMPEN */ #define _ADC_SCANCTRL_CMPEN_MASK 0x80000000UL /**< Bit mask for ADC_CMPEN */ #define _ADC_SCANCTRL_CMPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */ #define ADC_SCANCTRL_CMPEN_DEFAULT (_ADC_SCANCTRL_CMPEN_DEFAULT << 31) /**< Shifted mode DEFAULT for ADC_SCANCTRL */ /* Bit fields for ADC SCANCTRLX */ #define _ADC_SCANCTRLX_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANCTRLX */ #define _ADC_SCANCTRLX_MASK 0xEFDF7FFFUL /**< Mask for ADC_SCANCTRLX */ #define _ADC_SCANCTRLX_VREFSEL_SHIFT 0 /**< Shift value for ADC_VREFSEL */ #define _ADC_SCANCTRLX_VREFSEL_MASK 0x7UL /**< Bit mask for ADC_VREFSEL */ #define _ADC_SCANCTRLX_VREFSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRLX */ #define _ADC_SCANCTRLX_VREFSEL_VBGR 0x00000000UL /**< Mode VBGR for ADC_SCANCTRLX */ #define _ADC_SCANCTRLX_VREFSEL_VDDXWATT 0x00000001UL /**< Mode VDDXWATT for ADC_SCANCTRLX */ #define _ADC_SCANCTRLX_VREFSEL_VREFPWATT 0x00000002UL /**< Mode VREFPWATT for ADC_SCANCTRLX */ #define _ADC_SCANCTRLX_VREFSEL_VREFP 0x00000003UL /**< Mode VREFP for ADC_SCANCTRLX */ #define _ADC_SCANCTRLX_VREFSEL_VREFPNWATT 0x00000005UL /**< Mode VREFPNWATT for ADC_SCANCTRLX */ #define _ADC_SCANCTRLX_VREFSEL_VREFPN 0x00000006UL /**< Mode VREFPN for ADC_SCANCTRLX */ #define _ADC_SCANCTRLX_VREFSEL_VBGRLOW 0x00000007UL /**< Mode VBGRLOW for ADC_SCANCTRLX */ #define ADC_SCANCTRLX_VREFSEL_DEFAULT (_ADC_SCANCTRLX_VREFSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANCTRLX */ #define ADC_SCANCTRLX_VREFSEL_VBGR (_ADC_SCANCTRLX_VREFSEL_VBGR << 0) /**< Shifted mode VBGR for ADC_SCANCTRLX */ #define ADC_SCANCTRLX_VREFSEL_VDDXWATT (_ADC_SCANCTRLX_VREFSEL_VDDXWATT << 0) /**< Shifted mode VDDXWATT for ADC_SCANCTRLX */ #define ADC_SCANCTRLX_VREFSEL_VREFPWATT (_ADC_SCANCTRLX_VREFSEL_VREFPWATT << 0) /**< Shifted mode VREFPWATT for ADC_SCANCTRLX */ #define ADC_SCANCTRLX_VREFSEL_VREFP (_ADC_SCANCTRLX_VREFSEL_VREFP << 0) /**< Shifted mode VREFP for ADC_SCANCTRLX */ #define ADC_SCANCTRLX_VREFSEL_VREFPNWATT (_ADC_SCANCTRLX_VREFSEL_VREFPNWATT << 0) /**< Shifted mode VREFPNWATT for ADC_SCANCTRLX */ #define ADC_SCANCTRLX_VREFSEL_VREFPN (_ADC_SCANCTRLX_VREFSEL_VREFPN << 0) /**< Shifted mode VREFPN for ADC_SCANCTRLX */ #define ADC_SCANCTRLX_VREFSEL_VBGRLOW (_ADC_SCANCTRLX_VREFSEL_VBGRLOW << 0) /**< Shifted mode VBGRLOW for ADC_SCANCTRLX */ #define ADC_SCANCTRLX_VREFATTFIX (0x1UL << 3) /**< Enable Fixed Scaling on VREF */ #define _ADC_SCANCTRLX_VREFATTFIX_SHIFT 3 /**< Shift value for ADC_VREFATTFIX */ #define _ADC_SCANCTRLX_VREFATTFIX_MASK 0x8UL /**< Bit mask for ADC_VREFATTFIX */ #define _ADC_SCANCTRLX_VREFATTFIX_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRLX */ #define ADC_SCANCTRLX_VREFATTFIX_DEFAULT (_ADC_SCANCTRLX_VREFATTFIX_DEFAULT << 3) /**< Shifted mode DEFAULT for ADC_SCANCTRLX */ #define _ADC_SCANCTRLX_VREFATT_SHIFT 4 /**< Shift value for ADC_VREFATT */ #define _ADC_SCANCTRLX_VREFATT_MASK 0xF0UL /**< Bit mask for ADC_VREFATT */ #define _ADC_SCANCTRLX_VREFATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRLX */ #define ADC_SCANCTRLX_VREFATT_DEFAULT (_ADC_SCANCTRLX_VREFATT_DEFAULT << 4) /**< Shifted mode DEFAULT for ADC_SCANCTRLX */ #define _ADC_SCANCTRLX_VINATT_SHIFT 8 /**< Shift value for ADC_VINATT */ #define _ADC_SCANCTRLX_VINATT_MASK 0xF00UL /**< Bit mask for ADC_VINATT */ #define _ADC_SCANCTRLX_VINATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRLX */ #define ADC_SCANCTRLX_VINATT_DEFAULT (_ADC_SCANCTRLX_VINATT_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_SCANCTRLX */ #define _ADC_SCANCTRLX_DVL_SHIFT 12 /**< Shift value for ADC_DVL */ #define _ADC_SCANCTRLX_DVL_MASK 0x3000UL /**< Bit mask for ADC_DVL */ #define _ADC_SCANCTRLX_DVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRLX */ #define ADC_SCANCTRLX_DVL_DEFAULT (_ADC_SCANCTRLX_DVL_DEFAULT << 12) /**< Shifted mode DEFAULT for ADC_SCANCTRLX */ #define ADC_SCANCTRLX_FIFOOFACT (0x1UL << 14) /**< Scan FIFO Overflow Action */ #define _ADC_SCANCTRLX_FIFOOFACT_SHIFT 14 /**< Shift value for ADC_FIFOOFACT */ #define _ADC_SCANCTRLX_FIFOOFACT_MASK 0x4000UL /**< Bit mask for ADC_FIFOOFACT */ #define _ADC_SCANCTRLX_FIFOOFACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRLX */ #define _ADC_SCANCTRLX_FIFOOFACT_DISCARD 0x00000000UL /**< Mode DISCARD for ADC_SCANCTRLX */ #define _ADC_SCANCTRLX_FIFOOFACT_OVERWRITE 0x00000001UL /**< Mode OVERWRITE for ADC_SCANCTRLX */ #define ADC_SCANCTRLX_FIFOOFACT_DEFAULT (_ADC_SCANCTRLX_FIFOOFACT_DEFAULT << 14) /**< Shifted mode DEFAULT for ADC_SCANCTRLX */ #define ADC_SCANCTRLX_FIFOOFACT_DISCARD (_ADC_SCANCTRLX_FIFOOFACT_DISCARD << 14) /**< Shifted mode DISCARD for ADC_SCANCTRLX */ #define ADC_SCANCTRLX_FIFOOFACT_OVERWRITE (_ADC_SCANCTRLX_FIFOOFACT_OVERWRITE << 14) /**< Shifted mode OVERWRITE for ADC_SCANCTRLX */ #define ADC_SCANCTRLX_PRSMODE (0x1UL << 16) /**< Scan PRS Trigger Mode */ #define _ADC_SCANCTRLX_PRSMODE_SHIFT 16 /**< Shift value for ADC_PRSMODE */ #define _ADC_SCANCTRLX_PRSMODE_MASK 0x10000UL /**< Bit mask for ADC_PRSMODE */ #define _ADC_SCANCTRLX_PRSMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRLX */ #define _ADC_SCANCTRLX_PRSMODE_PULSED 0x00000000UL /**< Mode PULSED for ADC_SCANCTRLX */ #define _ADC_SCANCTRLX_PRSMODE_TIMED 0x00000001UL /**< Mode TIMED for ADC_SCANCTRLX */ #define ADC_SCANCTRLX_PRSMODE_DEFAULT (_ADC_SCANCTRLX_PRSMODE_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_SCANCTRLX */ #define ADC_SCANCTRLX_PRSMODE_PULSED (_ADC_SCANCTRLX_PRSMODE_PULSED << 16) /**< Shifted mode PULSED for ADC_SCANCTRLX */ #define ADC_SCANCTRLX_PRSMODE_TIMED (_ADC_SCANCTRLX_PRSMODE_TIMED << 16) /**< Shifted mode TIMED for ADC_SCANCTRLX */ #define _ADC_SCANCTRLX_PRSSEL_SHIFT 17 /**< Shift value for ADC_PRSSEL */ #define _ADC_SCANCTRLX_PRSSEL_MASK 0x1E0000UL /**< Bit mask for ADC_PRSSEL */ #define _ADC_SCANCTRLX_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRLX */ #define _ADC_SCANCTRLX_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for ADC_SCANCTRLX */ #define _ADC_SCANCTRLX_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for ADC_SCANCTRLX */ #define _ADC_SCANCTRLX_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for ADC_SCANCTRLX */ #define _ADC_SCANCTRLX_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for ADC_SCANCTRLX */ #define _ADC_SCANCTRLX_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for ADC_SCANCTRLX */ #define _ADC_SCANCTRLX_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for ADC_SCANCTRLX */ #define _ADC_SCANCTRLX_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for ADC_SCANCTRLX */ #define _ADC_SCANCTRLX_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for ADC_SCANCTRLX */ #define _ADC_SCANCTRLX_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for ADC_SCANCTRLX */ #define _ADC_SCANCTRLX_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for ADC_SCANCTRLX */ #define _ADC_SCANCTRLX_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for ADC_SCANCTRLX */ #define _ADC_SCANCTRLX_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for ADC_SCANCTRLX */ #define ADC_SCANCTRLX_PRSSEL_DEFAULT (_ADC_SCANCTRLX_PRSSEL_DEFAULT << 17) /**< Shifted mode DEFAULT for ADC_SCANCTRLX */ #define ADC_SCANCTRLX_PRSSEL_PRSCH0 (_ADC_SCANCTRLX_PRSSEL_PRSCH0 << 17) /**< Shifted mode PRSCH0 for ADC_SCANCTRLX */ #define ADC_SCANCTRLX_PRSSEL_PRSCH1 (_ADC_SCANCTRLX_PRSSEL_PRSCH1 << 17) /**< Shifted mode PRSCH1 for ADC_SCANCTRLX */ #define ADC_SCANCTRLX_PRSSEL_PRSCH2 (_ADC_SCANCTRLX_PRSSEL_PRSCH2 << 17) /**< Shifted mode PRSCH2 for ADC_SCANCTRLX */ #define ADC_SCANCTRLX_PRSSEL_PRSCH3 (_ADC_SCANCTRLX_PRSSEL_PRSCH3 << 17) /**< Shifted mode PRSCH3 for ADC_SCANCTRLX */ #define ADC_SCANCTRLX_PRSSEL_PRSCH4 (_ADC_SCANCTRLX_PRSSEL_PRSCH4 << 17) /**< Shifted mode PRSCH4 for ADC_SCANCTRLX */ #define ADC_SCANCTRLX_PRSSEL_PRSCH5 (_ADC_SCANCTRLX_PRSSEL_PRSCH5 << 17) /**< Shifted mode PRSCH5 for ADC_SCANCTRLX */ #define ADC_SCANCTRLX_PRSSEL_PRSCH6 (_ADC_SCANCTRLX_PRSSEL_PRSCH6 << 17) /**< Shifted mode PRSCH6 for ADC_SCANCTRLX */ #define ADC_SCANCTRLX_PRSSEL_PRSCH7 (_ADC_SCANCTRLX_PRSSEL_PRSCH7 << 17) /**< Shifted mode PRSCH7 for ADC_SCANCTRLX */ #define ADC_SCANCTRLX_PRSSEL_PRSCH8 (_ADC_SCANCTRLX_PRSSEL_PRSCH8 << 17) /**< Shifted mode PRSCH8 for ADC_SCANCTRLX */ #define ADC_SCANCTRLX_PRSSEL_PRSCH9 (_ADC_SCANCTRLX_PRSSEL_PRSCH9 << 17) /**< Shifted mode PRSCH9 for ADC_SCANCTRLX */ #define ADC_SCANCTRLX_PRSSEL_PRSCH10 (_ADC_SCANCTRLX_PRSSEL_PRSCH10 << 17) /**< Shifted mode PRSCH10 for ADC_SCANCTRLX */ #define ADC_SCANCTRLX_PRSSEL_PRSCH11 (_ADC_SCANCTRLX_PRSSEL_PRSCH11 << 17) /**< Shifted mode PRSCH11 for ADC_SCANCTRLX */ #define _ADC_SCANCTRLX_CONVSTARTDELAY_SHIFT 22 /**< Shift value for ADC_CONVSTARTDELAY */ #define _ADC_SCANCTRLX_CONVSTARTDELAY_MASK 0x7C00000UL /**< Bit mask for ADC_CONVSTARTDELAY */ #define _ADC_SCANCTRLX_CONVSTARTDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRLX */ #define ADC_SCANCTRLX_CONVSTARTDELAY_DEFAULT (_ADC_SCANCTRLX_CONVSTARTDELAY_DEFAULT << 22) /**< Shifted mode DEFAULT for ADC_SCANCTRLX */ #define ADC_SCANCTRLX_CONVSTARTDELAYEN (0x1UL << 27) /**< Enable Delaying Next Conversion Start */ #define _ADC_SCANCTRLX_CONVSTARTDELAYEN_SHIFT 27 /**< Shift value for ADC_CONVSTARTDELAYEN */ #define _ADC_SCANCTRLX_CONVSTARTDELAYEN_MASK 0x8000000UL /**< Bit mask for ADC_CONVSTARTDELAYEN */ #define _ADC_SCANCTRLX_CONVSTARTDELAYEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRLX */ #define ADC_SCANCTRLX_CONVSTARTDELAYEN_DEFAULT (_ADC_SCANCTRLX_CONVSTARTDELAYEN_DEFAULT << 27) /**< Shifted mode DEFAULT for ADC_SCANCTRLX */ #define _ADC_SCANCTRLX_REPDELAY_SHIFT 29 /**< Shift value for ADC_REPDELAY */ #define _ADC_SCANCTRLX_REPDELAY_MASK 0xE0000000UL /**< Bit mask for ADC_REPDELAY */ #define _ADC_SCANCTRLX_REPDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRLX */ #define _ADC_SCANCTRLX_REPDELAY_NODELAY 0x00000000UL /**< Mode NODELAY for ADC_SCANCTRLX */ #define _ADC_SCANCTRLX_REPDELAY_4CYCLES 0x00000001UL /**< Mode 4CYCLES for ADC_SCANCTRLX */ #define _ADC_SCANCTRLX_REPDELAY_8CYCLES 0x00000002UL /**< Mode 8CYCLES for ADC_SCANCTRLX */ #define _ADC_SCANCTRLX_REPDELAY_16CYCLES 0x00000003UL /**< Mode 16CYCLES for ADC_SCANCTRLX */ #define _ADC_SCANCTRLX_REPDELAY_32CYCLES 0x00000004UL /**< Mode 32CYCLES for ADC_SCANCTRLX */ #define _ADC_SCANCTRLX_REPDELAY_64CYCLES 0x00000005UL /**< Mode 64CYCLES for ADC_SCANCTRLX */ #define _ADC_SCANCTRLX_REPDELAY_128CYCLES 0x00000006UL /**< Mode 128CYCLES for ADC_SCANCTRLX */ #define _ADC_SCANCTRLX_REPDELAY_256CYCLES 0x00000007UL /**< Mode 256CYCLES for ADC_SCANCTRLX */ #define ADC_SCANCTRLX_REPDELAY_DEFAULT (_ADC_SCANCTRLX_REPDELAY_DEFAULT << 29) /**< Shifted mode DEFAULT for ADC_SCANCTRLX */ #define ADC_SCANCTRLX_REPDELAY_NODELAY (_ADC_SCANCTRLX_REPDELAY_NODELAY << 29) /**< Shifted mode NODELAY for ADC_SCANCTRLX */ #define ADC_SCANCTRLX_REPDELAY_4CYCLES (_ADC_SCANCTRLX_REPDELAY_4CYCLES << 29) /**< Shifted mode 4CYCLES for ADC_SCANCTRLX */ #define ADC_SCANCTRLX_REPDELAY_8CYCLES (_ADC_SCANCTRLX_REPDELAY_8CYCLES << 29) /**< Shifted mode 8CYCLES for ADC_SCANCTRLX */ #define ADC_SCANCTRLX_REPDELAY_16CYCLES (_ADC_SCANCTRLX_REPDELAY_16CYCLES << 29) /**< Shifted mode 16CYCLES for ADC_SCANCTRLX */ #define ADC_SCANCTRLX_REPDELAY_32CYCLES (_ADC_SCANCTRLX_REPDELAY_32CYCLES << 29) /**< Shifted mode 32CYCLES for ADC_SCANCTRLX */ #define ADC_SCANCTRLX_REPDELAY_64CYCLES (_ADC_SCANCTRLX_REPDELAY_64CYCLES << 29) /**< Shifted mode 64CYCLES for ADC_SCANCTRLX */ #define ADC_SCANCTRLX_REPDELAY_128CYCLES (_ADC_SCANCTRLX_REPDELAY_128CYCLES << 29) /**< Shifted mode 128CYCLES for ADC_SCANCTRLX */ #define ADC_SCANCTRLX_REPDELAY_256CYCLES (_ADC_SCANCTRLX_REPDELAY_256CYCLES << 29) /**< Shifted mode 256CYCLES for ADC_SCANCTRLX */ /* Bit fields for ADC SCANMASK */ #define _ADC_SCANMASK_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANMASK */ #define _ADC_SCANMASK_MASK 0xFFFFFFFFUL /**< Mask for ADC_SCANMASK */ #define _ADC_SCANMASK_SCANINPUTEN_SHIFT 0 /**< Shift value for ADC_SCANINPUTEN */ #define _ADC_SCANMASK_SCANINPUTEN_MASK 0xFFFFFFFFUL /**< Bit mask for ADC_SCANINPUTEN */ #define _ADC_SCANMASK_SCANINPUTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANMASK */ #define _ADC_SCANMASK_SCANINPUTEN_INPUT0INPUT0NEGSEL 0x00000001UL /**< Mode INPUT0INPUT0NEGSEL for ADC_SCANMASK */ #define _ADC_SCANMASK_SCANINPUTEN_INPUT0 0x00000001UL /**< Mode INPUT0 for ADC_SCANMASK */ #define _ADC_SCANMASK_SCANINPUTEN_INPUT1 0x00000002UL /**< Mode INPUT1 for ADC_SCANMASK */ #define _ADC_SCANMASK_SCANINPUTEN_INPUT1INPUT2 0x00000002UL /**< Mode INPUT1INPUT2 for ADC_SCANMASK */ #define _ADC_SCANMASK_SCANINPUTEN_INPUT2 0x00000004UL /**< Mode INPUT2 for ADC_SCANMASK */ #define _ADC_SCANMASK_SCANINPUTEN_INPUT2INPUT2NEGSEL 0x00000004UL /**< Mode INPUT2INPUT2NEGSEL for ADC_SCANMASK */ #define _ADC_SCANMASK_SCANINPUTEN_INPUT3 0x00000008UL /**< Mode INPUT3 for ADC_SCANMASK */ #define _ADC_SCANMASK_SCANINPUTEN_INPUT3INPUT4 0x00000008UL /**< Mode INPUT3INPUT4 for ADC_SCANMASK */ #define _ADC_SCANMASK_SCANINPUTEN_INPUT4 0x00000010UL /**< Mode INPUT4 for ADC_SCANMASK */ #define _ADC_SCANMASK_SCANINPUTEN_INPUT4INPUT4NEGSEL 0x00000010UL /**< Mode INPUT4INPUT4NEGSEL for ADC_SCANMASK */ #define _ADC_SCANMASK_SCANINPUTEN_INPUT5INPUT6 0x00000020UL /**< Mode INPUT5INPUT6 for ADC_SCANMASK */ #define _ADC_SCANMASK_SCANINPUTEN_INPUT5 0x00000020UL /**< Mode INPUT5 for ADC_SCANMASK */ #define _ADC_SCANMASK_SCANINPUTEN_INPUT6INPUT6NEGSEL 0x00000040UL /**< Mode INPUT6INPUT6NEGSEL for ADC_SCANMASK */ #define _ADC_SCANMASK_SCANINPUTEN_INPUT6 0x00000040UL /**< Mode INPUT6 for ADC_SCANMASK */ #define _ADC_SCANMASK_SCANINPUTEN_INPUT7 0x00000080UL /**< Mode INPUT7 for ADC_SCANMASK */ #define _ADC_SCANMASK_SCANINPUTEN_INPUT7INPUT0 0x00000080UL /**< Mode INPUT7INPUT0 for ADC_SCANMASK */ #define _ADC_SCANMASK_SCANINPUTEN_INPUT8INPUT9 0x00000100UL /**< Mode INPUT8INPUT9 for ADC_SCANMASK */ #define _ADC_SCANMASK_SCANINPUTEN_INPUT8 0x00000100UL /**< Mode INPUT8 for ADC_SCANMASK */ #define _ADC_SCANMASK_SCANINPUTEN_INPUT9 0x00000200UL /**< Mode INPUT9 for ADC_SCANMASK */ #define _ADC_SCANMASK_SCANINPUTEN_INPUT9INPUT9NEGSEL 0x00000200UL /**< Mode INPUT9INPUT9NEGSEL for ADC_SCANMASK */ #define _ADC_SCANMASK_SCANINPUTEN_INPUT10INPUT11 0x00000400UL /**< Mode INPUT10INPUT11 for ADC_SCANMASK */ #define _ADC_SCANMASK_SCANINPUTEN_INPUT10 0x00000400UL /**< Mode INPUT10 for ADC_SCANMASK */ #define _ADC_SCANMASK_SCANINPUTEN_INPUT11INPUT11NEGSEL 0x00000800UL /**< Mode INPUT11INPUT11NEGSEL for ADC_SCANMASK */ #define _ADC_SCANMASK_SCANINPUTEN_INPUT11 0x00000800UL /**< Mode INPUT11 for ADC_SCANMASK */ #define _ADC_SCANMASK_SCANINPUTEN_INPUT12INPUT13 0x00001000UL /**< Mode INPUT12INPUT13 for ADC_SCANMASK */ #define _ADC_SCANMASK_SCANINPUTEN_INPUT12 0x00001000UL /**< Mode INPUT12 for ADC_SCANMASK */ #define _ADC_SCANMASK_SCANINPUTEN_INPUT13INPUT13NEGSEL 0x00002000UL /**< Mode INPUT13INPUT13NEGSEL for ADC_SCANMASK */ #define _ADC_SCANMASK_SCANINPUTEN_INPUT13 0x00002000UL /**< Mode INPUT13 for ADC_SCANMASK */ #define _ADC_SCANMASK_SCANINPUTEN_INPUT14INPUT15 0x00004000UL /**< Mode INPUT14INPUT15 for ADC_SCANMASK */ #define _ADC_SCANMASK_SCANINPUTEN_INPUT14 0x00004000UL /**< Mode INPUT14 for ADC_SCANMASK */ #define _ADC_SCANMASK_SCANINPUTEN_INPUT15INPUT15NEGSEL 0x00008000UL /**< Mode INPUT15INPUT15NEGSEL for ADC_SCANMASK */ #define _ADC_SCANMASK_SCANINPUTEN_INPUT15 0x00008000UL /**< Mode INPUT15 for ADC_SCANMASK */ #define _ADC_SCANMASK_SCANINPUTEN_INPUT16INPUT17 0x00010000UL /**< Mode INPUT16INPUT17 for ADC_SCANMASK */ #define _ADC_SCANMASK_SCANINPUTEN_INPUT16 0x00010000UL /**< Mode INPUT16 for ADC_SCANMASK */ #define _ADC_SCANMASK_SCANINPUTEN_INPUT17INPUT18 0x00020000UL /**< Mode INPUT17INPUT18 for ADC_SCANMASK */ #define _ADC_SCANMASK_SCANINPUTEN_INPUT17 0x00020000UL /**< Mode INPUT17 for ADC_SCANMASK */ #define _ADC_SCANMASK_SCANINPUTEN_INPUT18INPUT19 0x00040000UL /**< Mode INPUT18INPUT19 for ADC_SCANMASK */ #define _ADC_SCANMASK_SCANINPUTEN_INPUT18 0x00040000UL /**< Mode INPUT18 for ADC_SCANMASK */ #define _ADC_SCANMASK_SCANINPUTEN_INPUT19 0x00080000UL /**< Mode INPUT19 for ADC_SCANMASK */ #define _ADC_SCANMASK_SCANINPUTEN_INPUT19INPUT20 0x00080000UL /**< Mode INPUT19INPUT20 for ADC_SCANMASK */ #define _ADC_SCANMASK_SCANINPUTEN_INPUT20INPUT21 0x00100000UL /**< Mode INPUT20INPUT21 for ADC_SCANMASK */ #define _ADC_SCANMASK_SCANINPUTEN_INPUT20 0x00100000UL /**< Mode INPUT20 for ADC_SCANMASK */ #define _ADC_SCANMASK_SCANINPUTEN_INPUT21 0x00200000UL /**< Mode INPUT21 for ADC_SCANMASK */ #define _ADC_SCANMASK_SCANINPUTEN_INPUT21INPUT22 0x00200000UL /**< Mode INPUT21INPUT22 for ADC_SCANMASK */ #define _ADC_SCANMASK_SCANINPUTEN_INPUT22INPUT23 0x00400000UL /**< Mode INPUT22INPUT23 for ADC_SCANMASK */ #define _ADC_SCANMASK_SCANINPUTEN_INPUT22 0x00400000UL /**< Mode INPUT22 for ADC_SCANMASK */ #define _ADC_SCANMASK_SCANINPUTEN_INPUT23INPUT16 0x00800000UL /**< Mode INPUT23INPUT16 for ADC_SCANMASK */ #define _ADC_SCANMASK_SCANINPUTEN_INPUT23 0x00800000UL /**< Mode INPUT23 for ADC_SCANMASK */ #define _ADC_SCANMASK_SCANINPUTEN_INPUT24 0x01000000UL /**< Mode INPUT24 for ADC_SCANMASK */ #define _ADC_SCANMASK_SCANINPUTEN_INPUT24INPUT25 0x01000000UL /**< Mode INPUT24INPUT25 for ADC_SCANMASK */ #define _ADC_SCANMASK_SCANINPUTEN_INPUT25INPUT26 0x02000000UL /**< Mode INPUT25INPUT26 for ADC_SCANMASK */ #define _ADC_SCANMASK_SCANINPUTEN_INPUT25 0x02000000UL /**< Mode INPUT25 for ADC_SCANMASK */ #define _ADC_SCANMASK_SCANINPUTEN_INPUT26 0x04000000UL /**< Mode INPUT26 for ADC_SCANMASK */ #define _ADC_SCANMASK_SCANINPUTEN_INPUT26INPUT27 0x04000000UL /**< Mode INPUT26INPUT27 for ADC_SCANMASK */ #define _ADC_SCANMASK_SCANINPUTEN_INPUT27INPUT28 0x08000000UL /**< Mode INPUT27INPUT28 for ADC_SCANMASK */ #define _ADC_SCANMASK_SCANINPUTEN_INPUT27 0x08000000UL /**< Mode INPUT27 for ADC_SCANMASK */ #define _ADC_SCANMASK_SCANINPUTEN_INPUT28INPUT29 0x10000000UL /**< Mode INPUT28INPUT29 for ADC_SCANMASK */ #define _ADC_SCANMASK_SCANINPUTEN_INPUT28 0x10000000UL /**< Mode INPUT28 for ADC_SCANMASK */ #define _ADC_SCANMASK_SCANINPUTEN_INPUT29 0x20000000UL /**< Mode INPUT29 for ADC_SCANMASK */ #define _ADC_SCANMASK_SCANINPUTEN_INPUT29INPUT30 0x20000000UL /**< Mode INPUT29INPUT30 for ADC_SCANMASK */ #define _ADC_SCANMASK_SCANINPUTEN_INPUT30 0x40000000UL /**< Mode INPUT30 for ADC_SCANMASK */ #define _ADC_SCANMASK_SCANINPUTEN_INPUT30INPUT31 0x40000000UL /**< Mode INPUT30INPUT31 for ADC_SCANMASK */ #define _ADC_SCANMASK_SCANINPUTEN_INPUT31INPUT24 0x80000000UL /**< Mode INPUT31INPUT24 for ADC_SCANMASK */ #define _ADC_SCANMASK_SCANINPUTEN_INPUT31 0x80000000UL /**< Mode INPUT31 for ADC_SCANMASK */ #define ADC_SCANMASK_SCANINPUTEN_DEFAULT (_ADC_SCANMASK_SCANINPUTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANMASK */ #define ADC_SCANMASK_SCANINPUTEN_INPUT0INPUT0NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT0INPUT0NEGSEL << 0) /**< Shifted mode INPUT0INPUT0NEGSEL for ADC_SCANMASK */ #define ADC_SCANMASK_SCANINPUTEN_INPUT0 (_ADC_SCANMASK_SCANINPUTEN_INPUT0 << 0) /**< Shifted mode INPUT0 for ADC_SCANMASK */ #define ADC_SCANMASK_SCANINPUTEN_INPUT1 (_ADC_SCANMASK_SCANINPUTEN_INPUT1 << 0) /**< Shifted mode INPUT1 for ADC_SCANMASK */ #define ADC_SCANMASK_SCANINPUTEN_INPUT1INPUT2 (_ADC_SCANMASK_SCANINPUTEN_INPUT1INPUT2 << 0) /**< Shifted mode INPUT1INPUT2 for ADC_SCANMASK */ #define ADC_SCANMASK_SCANINPUTEN_INPUT2 (_ADC_SCANMASK_SCANINPUTEN_INPUT2 << 0) /**< Shifted mode INPUT2 for ADC_SCANMASK */ #define ADC_SCANMASK_SCANINPUTEN_INPUT2INPUT2NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT2INPUT2NEGSEL << 0) /**< Shifted mode INPUT2INPUT2NEGSEL for ADC_SCANMASK */ #define ADC_SCANMASK_SCANINPUTEN_INPUT3 (_ADC_SCANMASK_SCANINPUTEN_INPUT3 << 0) /**< Shifted mode INPUT3 for ADC_SCANMASK */ #define ADC_SCANMASK_SCANINPUTEN_INPUT3INPUT4 (_ADC_SCANMASK_SCANINPUTEN_INPUT3INPUT4 << 0) /**< Shifted mode INPUT3INPUT4 for ADC_SCANMASK */ #define ADC_SCANMASK_SCANINPUTEN_INPUT4 (_ADC_SCANMASK_SCANINPUTEN_INPUT4 << 0) /**< Shifted mode INPUT4 for ADC_SCANMASK */ #define ADC_SCANMASK_SCANINPUTEN_INPUT4INPUT4NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT4INPUT4NEGSEL << 0) /**< Shifted mode INPUT4INPUT4NEGSEL for ADC_SCANMASK */ #define ADC_SCANMASK_SCANINPUTEN_INPUT5INPUT6 (_ADC_SCANMASK_SCANINPUTEN_INPUT5INPUT6 << 0) /**< Shifted mode INPUT5INPUT6 for ADC_SCANMASK */ #define ADC_SCANMASK_SCANINPUTEN_INPUT5 (_ADC_SCANMASK_SCANINPUTEN_INPUT5 << 0) /**< Shifted mode INPUT5 for ADC_SCANMASK */ #define ADC_SCANMASK_SCANINPUTEN_INPUT6INPUT6NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT6INPUT6NEGSEL << 0) /**< Shifted mode INPUT6INPUT6NEGSEL for ADC_SCANMASK */ #define ADC_SCANMASK_SCANINPUTEN_INPUT6 (_ADC_SCANMASK_SCANINPUTEN_INPUT6 << 0) /**< Shifted mode INPUT6 for ADC_SCANMASK */ #define ADC_SCANMASK_SCANINPUTEN_INPUT7 (_ADC_SCANMASK_SCANINPUTEN_INPUT7 << 0) /**< Shifted mode INPUT7 for ADC_SCANMASK */ #define ADC_SCANMASK_SCANINPUTEN_INPUT7INPUT0 (_ADC_SCANMASK_SCANINPUTEN_INPUT7INPUT0 << 0) /**< Shifted mode INPUT7INPUT0 for ADC_SCANMASK */ #define ADC_SCANMASK_SCANINPUTEN_INPUT8INPUT9 (_ADC_SCANMASK_SCANINPUTEN_INPUT8INPUT9 << 0) /**< Shifted mode INPUT8INPUT9 for ADC_SCANMASK */ #define ADC_SCANMASK_SCANINPUTEN_INPUT8 (_ADC_SCANMASK_SCANINPUTEN_INPUT8 << 0) /**< Shifted mode INPUT8 for ADC_SCANMASK */ #define ADC_SCANMASK_SCANINPUTEN_INPUT9 (_ADC_SCANMASK_SCANINPUTEN_INPUT9 << 0) /**< Shifted mode INPUT9 for ADC_SCANMASK */ #define ADC_SCANMASK_SCANINPUTEN_INPUT9INPUT9NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT9INPUT9NEGSEL << 0) /**< Shifted mode INPUT9INPUT9NEGSEL for ADC_SCANMASK */ #define ADC_SCANMASK_SCANINPUTEN_INPUT10INPUT11 (_ADC_SCANMASK_SCANINPUTEN_INPUT10INPUT11 << 0) /**< Shifted mode INPUT10INPUT11 for ADC_SCANMASK */ #define ADC_SCANMASK_SCANINPUTEN_INPUT10 (_ADC_SCANMASK_SCANINPUTEN_INPUT10 << 0) /**< Shifted mode INPUT10 for ADC_SCANMASK */ #define ADC_SCANMASK_SCANINPUTEN_INPUT11INPUT11NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT11INPUT11NEGSEL << 0) /**< Shifted mode INPUT11INPUT11NEGSEL for ADC_SCANMASK */ #define ADC_SCANMASK_SCANINPUTEN_INPUT11 (_ADC_SCANMASK_SCANINPUTEN_INPUT11 << 0) /**< Shifted mode INPUT11 for ADC_SCANMASK */ #define ADC_SCANMASK_SCANINPUTEN_INPUT12INPUT13 (_ADC_SCANMASK_SCANINPUTEN_INPUT12INPUT13 << 0) /**< Shifted mode INPUT12INPUT13 for ADC_SCANMASK */ #define ADC_SCANMASK_SCANINPUTEN_INPUT12 (_ADC_SCANMASK_SCANINPUTEN_INPUT12 << 0) /**< Shifted mode INPUT12 for ADC_SCANMASK */ #define ADC_SCANMASK_SCANINPUTEN_INPUT13INPUT13NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT13INPUT13NEGSEL << 0) /**< Shifted mode INPUT13INPUT13NEGSEL for ADC_SCANMASK */ #define ADC_SCANMASK_SCANINPUTEN_INPUT13 (_ADC_SCANMASK_SCANINPUTEN_INPUT13 << 0) /**< Shifted mode INPUT13 for ADC_SCANMASK */ #define ADC_SCANMASK_SCANINPUTEN_INPUT14INPUT15 (_ADC_SCANMASK_SCANINPUTEN_INPUT14INPUT15 << 0) /**< Shifted mode INPUT14INPUT15 for ADC_SCANMASK */ #define ADC_SCANMASK_SCANINPUTEN_INPUT14 (_ADC_SCANMASK_SCANINPUTEN_INPUT14 << 0) /**< Shifted mode INPUT14 for ADC_SCANMASK */ #define ADC_SCANMASK_SCANINPUTEN_INPUT15INPUT15NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT15INPUT15NEGSEL << 0) /**< Shifted mode INPUT15INPUT15NEGSEL for ADC_SCANMASK */ #define ADC_SCANMASK_SCANINPUTEN_INPUT15 (_ADC_SCANMASK_SCANINPUTEN_INPUT15 << 0) /**< Shifted mode INPUT15 for ADC_SCANMASK */ #define ADC_SCANMASK_SCANINPUTEN_INPUT16INPUT17 (_ADC_SCANMASK_SCANINPUTEN_INPUT16INPUT17 << 0) /**< Shifted mode INPUT16INPUT17 for ADC_SCANMASK */ #define ADC_SCANMASK_SCANINPUTEN_INPUT16 (_ADC_SCANMASK_SCANINPUTEN_INPUT16 << 0) /**< Shifted mode INPUT16 for ADC_SCANMASK */ #define ADC_SCANMASK_SCANINPUTEN_INPUT17INPUT18 (_ADC_SCANMASK_SCANINPUTEN_INPUT17INPUT18 << 0) /**< Shifted mode INPUT17INPUT18 for ADC_SCANMASK */ #define ADC_SCANMASK_SCANINPUTEN_INPUT17 (_ADC_SCANMASK_SCANINPUTEN_INPUT17 << 0) /**< Shifted mode INPUT17 for ADC_SCANMASK */ #define ADC_SCANMASK_SCANINPUTEN_INPUT18INPUT19 (_ADC_SCANMASK_SCANINPUTEN_INPUT18INPUT19 << 0) /**< Shifted mode INPUT18INPUT19 for ADC_SCANMASK */ #define ADC_SCANMASK_SCANINPUTEN_INPUT18 (_ADC_SCANMASK_SCANINPUTEN_INPUT18 << 0) /**< Shifted mode INPUT18 for ADC_SCANMASK */ #define ADC_SCANMASK_SCANINPUTEN_INPUT19 (_ADC_SCANMASK_SCANINPUTEN_INPUT19 << 0) /**< Shifted mode INPUT19 for ADC_SCANMASK */ #define ADC_SCANMASK_SCANINPUTEN_INPUT19INPUT20 (_ADC_SCANMASK_SCANINPUTEN_INPUT19INPUT20 << 0) /**< Shifted mode INPUT19INPUT20 for ADC_SCANMASK */ #define ADC_SCANMASK_SCANINPUTEN_INPUT20INPUT21 (_ADC_SCANMASK_SCANINPUTEN_INPUT20INPUT21 << 0) /**< Shifted mode INPUT20INPUT21 for ADC_SCANMASK */ #define ADC_SCANMASK_SCANINPUTEN_INPUT20 (_ADC_SCANMASK_SCANINPUTEN_INPUT20 << 0) /**< Shifted mode INPUT20 for ADC_SCANMASK */ #define ADC_SCANMASK_SCANINPUTEN_INPUT21 (_ADC_SCANMASK_SCANINPUTEN_INPUT21 << 0) /**< Shifted mode INPUT21 for ADC_SCANMASK */ #define ADC_SCANMASK_SCANINPUTEN_INPUT21INPUT22 (_ADC_SCANMASK_SCANINPUTEN_INPUT21INPUT22 << 0) /**< Shifted mode INPUT21INPUT22 for ADC_SCANMASK */ #define ADC_SCANMASK_SCANINPUTEN_INPUT22INPUT23 (_ADC_SCANMASK_SCANINPUTEN_INPUT22INPUT23 << 0) /**< Shifted mode INPUT22INPUT23 for ADC_SCANMASK */ #define ADC_SCANMASK_SCANINPUTEN_INPUT22 (_ADC_SCANMASK_SCANINPUTEN_INPUT22 << 0) /**< Shifted mode INPUT22 for ADC_SCANMASK */ #define ADC_SCANMASK_SCANINPUTEN_INPUT23INPUT16 (_ADC_SCANMASK_SCANINPUTEN_INPUT23INPUT16 << 0) /**< Shifted mode INPUT23INPUT16 for ADC_SCANMASK */ #define ADC_SCANMASK_SCANINPUTEN_INPUT23 (_ADC_SCANMASK_SCANINPUTEN_INPUT23 << 0) /**< Shifted mode INPUT23 for ADC_SCANMASK */ #define ADC_SCANMASK_SCANINPUTEN_INPUT24 (_ADC_SCANMASK_SCANINPUTEN_INPUT24 << 0) /**< Shifted mode INPUT24 for ADC_SCANMASK */ #define ADC_SCANMASK_SCANINPUTEN_INPUT24INPUT25 (_ADC_SCANMASK_SCANINPUTEN_INPUT24INPUT25 << 0) /**< Shifted mode INPUT24INPUT25 for ADC_SCANMASK */ #define ADC_SCANMASK_SCANINPUTEN_INPUT25INPUT26 (_ADC_SCANMASK_SCANINPUTEN_INPUT25INPUT26 << 0) /**< Shifted mode INPUT25INPUT26 for ADC_SCANMASK */ #define ADC_SCANMASK_SCANINPUTEN_INPUT25 (_ADC_SCANMASK_SCANINPUTEN_INPUT25 << 0) /**< Shifted mode INPUT25 for ADC_SCANMASK */ #define ADC_SCANMASK_SCANINPUTEN_INPUT26 (_ADC_SCANMASK_SCANINPUTEN_INPUT26 << 0) /**< Shifted mode INPUT26 for ADC_SCANMASK */ #define ADC_SCANMASK_SCANINPUTEN_INPUT26INPUT27 (_ADC_SCANMASK_SCANINPUTEN_INPUT26INPUT27 << 0) /**< Shifted mode INPUT26INPUT27 for ADC_SCANMASK */ #define ADC_SCANMASK_SCANINPUTEN_INPUT27INPUT28 (_ADC_SCANMASK_SCANINPUTEN_INPUT27INPUT28 << 0) /**< Shifted mode INPUT27INPUT28 for ADC_SCANMASK */ #define ADC_SCANMASK_SCANINPUTEN_INPUT27 (_ADC_SCANMASK_SCANINPUTEN_INPUT27 << 0) /**< Shifted mode INPUT27 for ADC_SCANMASK */ #define ADC_SCANMASK_SCANINPUTEN_INPUT28INPUT29 (_ADC_SCANMASK_SCANINPUTEN_INPUT28INPUT29 << 0) /**< Shifted mode INPUT28INPUT29 for ADC_SCANMASK */ #define ADC_SCANMASK_SCANINPUTEN_INPUT28 (_ADC_SCANMASK_SCANINPUTEN_INPUT28 << 0) /**< Shifted mode INPUT28 for ADC_SCANMASK */ #define ADC_SCANMASK_SCANINPUTEN_INPUT29 (_ADC_SCANMASK_SCANINPUTEN_INPUT29 << 0) /**< Shifted mode INPUT29 for ADC_SCANMASK */ #define ADC_SCANMASK_SCANINPUTEN_INPUT29INPUT30 (_ADC_SCANMASK_SCANINPUTEN_INPUT29INPUT30 << 0) /**< Shifted mode INPUT29INPUT30 for ADC_SCANMASK */ #define ADC_SCANMASK_SCANINPUTEN_INPUT30 (_ADC_SCANMASK_SCANINPUTEN_INPUT30 << 0) /**< Shifted mode INPUT30 for ADC_SCANMASK */ #define ADC_SCANMASK_SCANINPUTEN_INPUT30INPUT31 (_ADC_SCANMASK_SCANINPUTEN_INPUT30INPUT31 << 0) /**< Shifted mode INPUT30INPUT31 for ADC_SCANMASK */ #define ADC_SCANMASK_SCANINPUTEN_INPUT31INPUT24 (_ADC_SCANMASK_SCANINPUTEN_INPUT31INPUT24 << 0) /**< Shifted mode INPUT31INPUT24 for ADC_SCANMASK */ #define ADC_SCANMASK_SCANINPUTEN_INPUT31 (_ADC_SCANMASK_SCANINPUTEN_INPUT31 << 0) /**< Shifted mode INPUT31 for ADC_SCANMASK */ /* Bit fields for ADC SCANINPUTSEL */ #define _ADC_SCANINPUTSEL_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANINPUTSEL */ #define _ADC_SCANINPUTSEL_MASK 0x1F1F1F1FUL /**< Mask for ADC_SCANINPUTSEL */ #define _ADC_SCANINPUTSEL_INPUT0TO7SEL_SHIFT 0 /**< Shift value for ADC_INPUT0TO7SEL */ #define _ADC_SCANINPUTSEL_INPUT0TO7SEL_MASK 0x1FUL /**< Bit mask for ADC_INPUT0TO7SEL */ #define _ADC_SCANINPUTSEL_INPUT0TO7SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANINPUTSEL */ #define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT0CH0TO7 0x00000000UL /**< Mode APORT0CH0TO7 for ADC_SCANINPUTSEL */ #define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT0CH8TO15 0x00000001UL /**< Mode APORT0CH8TO15 for ADC_SCANINPUTSEL */ #define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH0TO7 0x00000004UL /**< Mode APORT1CH0TO7 for ADC_SCANINPUTSEL */ #define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH8TO15 0x00000005UL /**< Mode APORT1CH8TO15 for ADC_SCANINPUTSEL */ #define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH16TO23 0x00000006UL /**< Mode APORT1CH16TO23 for ADC_SCANINPUTSEL */ #define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH24TO31 0x00000007UL /**< Mode APORT1CH24TO31 for ADC_SCANINPUTSEL */ #define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH0TO7 0x00000008UL /**< Mode APORT2CH0TO7 for ADC_SCANINPUTSEL */ #define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH8TO15 0x00000009UL /**< Mode APORT2CH8TO15 for ADC_SCANINPUTSEL */ #define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH16TO23 0x0000000AUL /**< Mode APORT2CH16TO23 for ADC_SCANINPUTSEL */ #define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH24TO31 0x0000000BUL /**< Mode APORT2CH24TO31 for ADC_SCANINPUTSEL */ #define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH0TO7 0x0000000CUL /**< Mode APORT3CH0TO7 for ADC_SCANINPUTSEL */ #define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH8TO15 0x0000000DUL /**< Mode APORT3CH8TO15 for ADC_SCANINPUTSEL */ #define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH16TO23 0x0000000EUL /**< Mode APORT3CH16TO23 for ADC_SCANINPUTSEL */ #define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH24TO31 0x0000000FUL /**< Mode APORT3CH24TO31 for ADC_SCANINPUTSEL */ #define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH0TO7 0x00000010UL /**< Mode APORT4CH0TO7 for ADC_SCANINPUTSEL */ #define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH8TO15 0x00000011UL /**< Mode APORT4CH8TO15 for ADC_SCANINPUTSEL */ #define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH16TO23 0x00000012UL /**< Mode APORT4CH16TO23 for ADC_SCANINPUTSEL */ #define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH24TO31 0x00000013UL /**< Mode APORT4CH24TO31 for ADC_SCANINPUTSEL */ #define ADC_SCANINPUTSEL_INPUT0TO7SEL_DEFAULT (_ADC_SCANINPUTSEL_INPUT0TO7SEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANINPUTSEL */ #define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT0CH0TO7 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT0CH0TO7 << 0) /**< Shifted mode APORT0CH0TO7 for ADC_SCANINPUTSEL */ #define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT0CH8TO15 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT0CH8TO15 << 0) /**< Shifted mode APORT0CH8TO15 for ADC_SCANINPUTSEL */ #define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH0TO7 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH0TO7 << 0) /**< Shifted mode APORT1CH0TO7 for ADC_SCANINPUTSEL */ #define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH8TO15 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH8TO15 << 0) /**< Shifted mode APORT1CH8TO15 for ADC_SCANINPUTSEL */ #define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH16TO23 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH16TO23 << 0) /**< Shifted mode APORT1CH16TO23 for ADC_SCANINPUTSEL */ #define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH24TO31 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH24TO31 << 0) /**< Shifted mode APORT1CH24TO31 for ADC_SCANINPUTSEL */ #define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH0TO7 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH0TO7 << 0) /**< Shifted mode APORT2CH0TO7 for ADC_SCANINPUTSEL */ #define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH8TO15 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH8TO15 << 0) /**< Shifted mode APORT2CH8TO15 for ADC_SCANINPUTSEL */ #define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH16TO23 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH16TO23 << 0) /**< Shifted mode APORT2CH16TO23 for ADC_SCANINPUTSEL */ #define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH24TO31 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH24TO31 << 0) /**< Shifted mode APORT2CH24TO31 for ADC_SCANINPUTSEL */ #define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH0TO7 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH0TO7 << 0) /**< Shifted mode APORT3CH0TO7 for ADC_SCANINPUTSEL */ #define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH8TO15 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH8TO15 << 0) /**< Shifted mode APORT3CH8TO15 for ADC_SCANINPUTSEL */ #define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH16TO23 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH16TO23 << 0) /**< Shifted mode APORT3CH16TO23 for ADC_SCANINPUTSEL */ #define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH24TO31 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH24TO31 << 0) /**< Shifted mode APORT3CH24TO31 for ADC_SCANINPUTSEL */ #define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH0TO7 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH0TO7 << 0) /**< Shifted mode APORT4CH0TO7 for ADC_SCANINPUTSEL */ #define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH8TO15 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH8TO15 << 0) /**< Shifted mode APORT4CH8TO15 for ADC_SCANINPUTSEL */ #define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH16TO23 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH16TO23 << 0) /**< Shifted mode APORT4CH16TO23 for ADC_SCANINPUTSEL */ #define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH24TO31 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH24TO31 << 0) /**< Shifted mode APORT4CH24TO31 for ADC_SCANINPUTSEL */ #define _ADC_SCANINPUTSEL_INPUT8TO15SEL_SHIFT 8 /**< Shift value for ADC_INPUT8TO15SEL */ #define _ADC_SCANINPUTSEL_INPUT8TO15SEL_MASK 0x1F00UL /**< Bit mask for ADC_INPUT8TO15SEL */ #define _ADC_SCANINPUTSEL_INPUT8TO15SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANINPUTSEL */ #define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT0CH0TO7 0x00000000UL /**< Mode APORT0CH0TO7 for ADC_SCANINPUTSEL */ #define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT0CH8TO15 0x00000001UL /**< Mode APORT0CH8TO15 for ADC_SCANINPUTSEL */ #define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH0TO7 0x00000004UL /**< Mode APORT1CH0TO7 for ADC_SCANINPUTSEL */ #define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH8TO15 0x00000005UL /**< Mode APORT1CH8TO15 for ADC_SCANINPUTSEL */ #define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH16TO23 0x00000006UL /**< Mode APORT1CH16TO23 for ADC_SCANINPUTSEL */ #define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH24TO31 0x00000007UL /**< Mode APORT1CH24TO31 for ADC_SCANINPUTSEL */ #define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH0TO7 0x00000008UL /**< Mode APORT2CH0TO7 for ADC_SCANINPUTSEL */ #define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH8TO15 0x00000009UL /**< Mode APORT2CH8TO15 for ADC_SCANINPUTSEL */ #define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH16TO23 0x0000000AUL /**< Mode APORT2CH16TO23 for ADC_SCANINPUTSEL */ #define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH24TO31 0x0000000BUL /**< Mode APORT2CH24TO31 for ADC_SCANINPUTSEL */ #define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH0TO7 0x0000000CUL /**< Mode APORT3CH0TO7 for ADC_SCANINPUTSEL */ #define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH8TO15 0x0000000DUL /**< Mode APORT3CH8TO15 for ADC_SCANINPUTSEL */ #define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH16TO23 0x0000000EUL /**< Mode APORT3CH16TO23 for ADC_SCANINPUTSEL */ #define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH24TO31 0x0000000FUL /**< Mode APORT3CH24TO31 for ADC_SCANINPUTSEL */ #define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH0TO7 0x00000010UL /**< Mode APORT4CH0TO7 for ADC_SCANINPUTSEL */ #define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH8TO15 0x00000011UL /**< Mode APORT4CH8TO15 for ADC_SCANINPUTSEL */ #define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH16TO23 0x00000012UL /**< Mode APORT4CH16TO23 for ADC_SCANINPUTSEL */ #define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH24TO31 0x00000013UL /**< Mode APORT4CH24TO31 for ADC_SCANINPUTSEL */ #define ADC_SCANINPUTSEL_INPUT8TO15SEL_DEFAULT (_ADC_SCANINPUTSEL_INPUT8TO15SEL_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_SCANINPUTSEL */ #define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT0CH0TO7 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT0CH0TO7 << 8) /**< Shifted mode APORT0CH0TO7 for ADC_SCANINPUTSEL */ #define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT0CH8TO15 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT0CH8TO15 << 8) /**< Shifted mode APORT0CH8TO15 for ADC_SCANINPUTSEL */ #define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH0TO7 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH0TO7 << 8) /**< Shifted mode APORT1CH0TO7 for ADC_SCANINPUTSEL */ #define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH8TO15 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH8TO15 << 8) /**< Shifted mode APORT1CH8TO15 for ADC_SCANINPUTSEL */ #define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH16TO23 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH16TO23 << 8) /**< Shifted mode APORT1CH16TO23 for ADC_SCANINPUTSEL */ #define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH24TO31 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH24TO31 << 8) /**< Shifted mode APORT1CH24TO31 for ADC_SCANINPUTSEL */ #define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH0TO7 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH0TO7 << 8) /**< Shifted mode APORT2CH0TO7 for ADC_SCANINPUTSEL */ #define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH8TO15 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH8TO15 << 8) /**< Shifted mode APORT2CH8TO15 for ADC_SCANINPUTSEL */ #define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH16TO23 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH16TO23 << 8) /**< Shifted mode APORT2CH16TO23 for ADC_SCANINPUTSEL */ #define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH24TO31 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH24TO31 << 8) /**< Shifted mode APORT2CH24TO31 for ADC_SCANINPUTSEL */ #define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH0TO7 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH0TO7 << 8) /**< Shifted mode APORT3CH0TO7 for ADC_SCANINPUTSEL */ #define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH8TO15 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH8TO15 << 8) /**< Shifted mode APORT3CH8TO15 for ADC_SCANINPUTSEL */ #define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH16TO23 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH16TO23 << 8) /**< Shifted mode APORT3CH16TO23 for ADC_SCANINPUTSEL */ #define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH24TO31 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH24TO31 << 8) /**< Shifted mode APORT3CH24TO31 for ADC_SCANINPUTSEL */ #define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH0TO7 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH0TO7 << 8) /**< Shifted mode APORT4CH0TO7 for ADC_SCANINPUTSEL */ #define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH8TO15 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH8TO15 << 8) /**< Shifted mode APORT4CH8TO15 for ADC_SCANINPUTSEL */ #define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH16TO23 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH16TO23 << 8) /**< Shifted mode APORT4CH16TO23 for ADC_SCANINPUTSEL */ #define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH24TO31 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH24TO31 << 8) /**< Shifted mode APORT4CH24TO31 for ADC_SCANINPUTSEL */ #define _ADC_SCANINPUTSEL_INPUT16TO23SEL_SHIFT 16 /**< Shift value for ADC_INPUT16TO23SEL */ #define _ADC_SCANINPUTSEL_INPUT16TO23SEL_MASK 0x1F0000UL /**< Bit mask for ADC_INPUT16TO23SEL */ #define _ADC_SCANINPUTSEL_INPUT16TO23SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANINPUTSEL */ #define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT0CH0TO7 0x00000000UL /**< Mode APORT0CH0TO7 for ADC_SCANINPUTSEL */ #define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT0CH8TO15 0x00000001UL /**< Mode APORT0CH8TO15 for ADC_SCANINPUTSEL */ #define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH0TO7 0x00000004UL /**< Mode APORT1CH0TO7 for ADC_SCANINPUTSEL */ #define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH8TO15 0x00000005UL /**< Mode APORT1CH8TO15 for ADC_SCANINPUTSEL */ #define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH16TO23 0x00000006UL /**< Mode APORT1CH16TO23 for ADC_SCANINPUTSEL */ #define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH24TO31 0x00000007UL /**< Mode APORT1CH24TO31 for ADC_SCANINPUTSEL */ #define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH0TO7 0x00000008UL /**< Mode APORT2CH0TO7 for ADC_SCANINPUTSEL */ #define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH8TO15 0x00000009UL /**< Mode APORT2CH8TO15 for ADC_SCANINPUTSEL */ #define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH16TO23 0x0000000AUL /**< Mode APORT2CH16TO23 for ADC_SCANINPUTSEL */ #define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH24TO31 0x0000000BUL /**< Mode APORT2CH24TO31 for ADC_SCANINPUTSEL */ #define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH0TO7 0x0000000CUL /**< Mode APORT3CH0TO7 for ADC_SCANINPUTSEL */ #define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH8TO15 0x0000000DUL /**< Mode APORT3CH8TO15 for ADC_SCANINPUTSEL */ #define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH16TO23 0x0000000EUL /**< Mode APORT3CH16TO23 for ADC_SCANINPUTSEL */ #define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH24TO31 0x0000000FUL /**< Mode APORT3CH24TO31 for ADC_SCANINPUTSEL */ #define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH0TO7 0x00000010UL /**< Mode APORT4CH0TO7 for ADC_SCANINPUTSEL */ #define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH8TO15 0x00000011UL /**< Mode APORT4CH8TO15 for ADC_SCANINPUTSEL */ #define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH16TO23 0x00000012UL /**< Mode APORT4CH16TO23 for ADC_SCANINPUTSEL */ #define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH24TO31 0x00000013UL /**< Mode APORT4CH24TO31 for ADC_SCANINPUTSEL */ #define ADC_SCANINPUTSEL_INPUT16TO23SEL_DEFAULT (_ADC_SCANINPUTSEL_INPUT16TO23SEL_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_SCANINPUTSEL */ #define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT0CH0TO7 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT0CH0TO7 << 16) /**< Shifted mode APORT0CH0TO7 for ADC_SCANINPUTSEL */ #define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT0CH8TO15 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT0CH8TO15 << 16) /**< Shifted mode APORT0CH8TO15 for ADC_SCANINPUTSEL */ #define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH0TO7 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH0TO7 << 16) /**< Shifted mode APORT1CH0TO7 for ADC_SCANINPUTSEL */ #define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH8TO15 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH8TO15 << 16) /**< Shifted mode APORT1CH8TO15 for ADC_SCANINPUTSEL */ #define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH16TO23 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH16TO23 << 16) /**< Shifted mode APORT1CH16TO23 for ADC_SCANINPUTSEL */ #define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH24TO31 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH24TO31 << 16) /**< Shifted mode APORT1CH24TO31 for ADC_SCANINPUTSEL */ #define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH0TO7 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH0TO7 << 16) /**< Shifted mode APORT2CH0TO7 for ADC_SCANINPUTSEL */ #define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH8TO15 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH8TO15 << 16) /**< Shifted mode APORT2CH8TO15 for ADC_SCANINPUTSEL */ #define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH16TO23 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH16TO23 << 16) /**< Shifted mode APORT2CH16TO23 for ADC_SCANINPUTSEL */ #define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH24TO31 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH24TO31 << 16) /**< Shifted mode APORT2CH24TO31 for ADC_SCANINPUTSEL */ #define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH0TO7 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH0TO7 << 16) /**< Shifted mode APORT3CH0TO7 for ADC_SCANINPUTSEL */ #define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH8TO15 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH8TO15 << 16) /**< Shifted mode APORT3CH8TO15 for ADC_SCANINPUTSEL */ #define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH16TO23 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH16TO23 << 16) /**< Shifted mode APORT3CH16TO23 for ADC_SCANINPUTSEL */ #define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH24TO31 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH24TO31 << 16) /**< Shifted mode APORT3CH24TO31 for ADC_SCANINPUTSEL */ #define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH0TO7 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH0TO7 << 16) /**< Shifted mode APORT4CH0TO7 for ADC_SCANINPUTSEL */ #define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH8TO15 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH8TO15 << 16) /**< Shifted mode APORT4CH8TO15 for ADC_SCANINPUTSEL */ #define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH16TO23 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH16TO23 << 16) /**< Shifted mode APORT4CH16TO23 for ADC_SCANINPUTSEL */ #define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH24TO31 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH24TO31 << 16) /**< Shifted mode APORT4CH24TO31 for ADC_SCANINPUTSEL */ #define _ADC_SCANINPUTSEL_INPUT24TO31SEL_SHIFT 24 /**< Shift value for ADC_INPUT24TO31SEL */ #define _ADC_SCANINPUTSEL_INPUT24TO31SEL_MASK 0x1F000000UL /**< Bit mask for ADC_INPUT24TO31SEL */ #define _ADC_SCANINPUTSEL_INPUT24TO31SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANINPUTSEL */ #define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT0CH0TO7 0x00000000UL /**< Mode APORT0CH0TO7 for ADC_SCANINPUTSEL */ #define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT0CH8TO15 0x00000001UL /**< Mode APORT0CH8TO15 for ADC_SCANINPUTSEL */ #define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH0TO7 0x00000004UL /**< Mode APORT1CH0TO7 for ADC_SCANINPUTSEL */ #define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH8TO15 0x00000005UL /**< Mode APORT1CH8TO15 for ADC_SCANINPUTSEL */ #define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH16TO23 0x00000006UL /**< Mode APORT1CH16TO23 for ADC_SCANINPUTSEL */ #define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH24TO31 0x00000007UL /**< Mode APORT1CH24TO31 for ADC_SCANINPUTSEL */ #define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH0TO7 0x00000008UL /**< Mode APORT2CH0TO7 for ADC_SCANINPUTSEL */ #define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH8TO15 0x00000009UL /**< Mode APORT2CH8TO15 for ADC_SCANINPUTSEL */ #define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH16TO23 0x0000000AUL /**< Mode APORT2CH16TO23 for ADC_SCANINPUTSEL */ #define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH24TO31 0x0000000BUL /**< Mode APORT2CH24TO31 for ADC_SCANINPUTSEL */ #define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH0TO7 0x0000000CUL /**< Mode APORT3CH0TO7 for ADC_SCANINPUTSEL */ #define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH8TO15 0x0000000DUL /**< Mode APORT3CH8TO15 for ADC_SCANINPUTSEL */ #define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH16TO23 0x0000000EUL /**< Mode APORT3CH16TO23 for ADC_SCANINPUTSEL */ #define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH24TO31 0x0000000FUL /**< Mode APORT3CH24TO31 for ADC_SCANINPUTSEL */ #define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH0TO7 0x00000010UL /**< Mode APORT4CH0TO7 for ADC_SCANINPUTSEL */ #define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH8TO15 0x00000011UL /**< Mode APORT4CH8TO15 for ADC_SCANINPUTSEL */ #define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH16TO23 0x00000012UL /**< Mode APORT4CH16TO23 for ADC_SCANINPUTSEL */ #define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH24TO31 0x00000013UL /**< Mode APORT4CH24TO31 for ADC_SCANINPUTSEL */ #define ADC_SCANINPUTSEL_INPUT24TO31SEL_DEFAULT (_ADC_SCANINPUTSEL_INPUT24TO31SEL_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_SCANINPUTSEL */ #define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT0CH0TO7 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT0CH0TO7 << 24) /**< Shifted mode APORT0CH0TO7 for ADC_SCANINPUTSEL */ #define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT0CH8TO15 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT0CH8TO15 << 24) /**< Shifted mode APORT0CH8TO15 for ADC_SCANINPUTSEL */ #define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH0TO7 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH0TO7 << 24) /**< Shifted mode APORT1CH0TO7 for ADC_SCANINPUTSEL */ #define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH8TO15 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH8TO15 << 24) /**< Shifted mode APORT1CH8TO15 for ADC_SCANINPUTSEL */ #define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH16TO23 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH16TO23 << 24) /**< Shifted mode APORT1CH16TO23 for ADC_SCANINPUTSEL */ #define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH24TO31 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH24TO31 << 24) /**< Shifted mode APORT1CH24TO31 for ADC_SCANINPUTSEL */ #define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH0TO7 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH0TO7 << 24) /**< Shifted mode APORT2CH0TO7 for ADC_SCANINPUTSEL */ #define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH8TO15 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH8TO15 << 24) /**< Shifted mode APORT2CH8TO15 for ADC_SCANINPUTSEL */ #define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH16TO23 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH16TO23 << 24) /**< Shifted mode APORT2CH16TO23 for ADC_SCANINPUTSEL */ #define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH24TO31 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH24TO31 << 24) /**< Shifted mode APORT2CH24TO31 for ADC_SCANINPUTSEL */ #define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH0TO7 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH0TO7 << 24) /**< Shifted mode APORT3CH0TO7 for ADC_SCANINPUTSEL */ #define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH8TO15 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH8TO15 << 24) /**< Shifted mode APORT3CH8TO15 for ADC_SCANINPUTSEL */ #define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH16TO23 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH16TO23 << 24) /**< Shifted mode APORT3CH16TO23 for ADC_SCANINPUTSEL */ #define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH24TO31 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH24TO31 << 24) /**< Shifted mode APORT3CH24TO31 for ADC_SCANINPUTSEL */ #define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH0TO7 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH0TO7 << 24) /**< Shifted mode APORT4CH0TO7 for ADC_SCANINPUTSEL */ #define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH8TO15 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH8TO15 << 24) /**< Shifted mode APORT4CH8TO15 for ADC_SCANINPUTSEL */ #define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH16TO23 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH16TO23 << 24) /**< Shifted mode APORT4CH16TO23 for ADC_SCANINPUTSEL */ #define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH24TO31 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH24TO31 << 24) /**< Shifted mode APORT4CH24TO31 for ADC_SCANINPUTSEL */ /* Bit fields for ADC SCANNEGSEL */ #define _ADC_SCANNEGSEL_RESETVALUE 0x000039E4UL /**< Default value for ADC_SCANNEGSEL */ #define _ADC_SCANNEGSEL_MASK 0x0000FFFFUL /**< Mask for ADC_SCANNEGSEL */ #define _ADC_SCANNEGSEL_INPUT0NEGSEL_SHIFT 0 /**< Shift value for ADC_INPUT0NEGSEL */ #define _ADC_SCANNEGSEL_INPUT0NEGSEL_MASK 0x3UL /**< Bit mask for ADC_INPUT0NEGSEL */ #define _ADC_SCANNEGSEL_INPUT0NEGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANNEGSEL */ #define _ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT1 0x00000000UL /**< Mode INPUT1 for ADC_SCANNEGSEL */ #define _ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT3 0x00000001UL /**< Mode INPUT3 for ADC_SCANNEGSEL */ #define _ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT5 0x00000002UL /**< Mode INPUT5 for ADC_SCANNEGSEL */ #define _ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT7 0x00000003UL /**< Mode INPUT7 for ADC_SCANNEGSEL */ #define ADC_SCANNEGSEL_INPUT0NEGSEL_DEFAULT (_ADC_SCANNEGSEL_INPUT0NEGSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANNEGSEL */ #define ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT1 (_ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT1 << 0) /**< Shifted mode INPUT1 for ADC_SCANNEGSEL */ #define ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT3 (_ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT3 << 0) /**< Shifted mode INPUT3 for ADC_SCANNEGSEL */ #define ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT5 (_ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT5 << 0) /**< Shifted mode INPUT5 for ADC_SCANNEGSEL */ #define ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT7 (_ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT7 << 0) /**< Shifted mode INPUT7 for ADC_SCANNEGSEL */ #define _ADC_SCANNEGSEL_INPUT2NEGSEL_SHIFT 2 /**< Shift value for ADC_INPUT2NEGSEL */ #define _ADC_SCANNEGSEL_INPUT2NEGSEL_MASK 0xCUL /**< Bit mask for ADC_INPUT2NEGSEL */ #define _ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT1 0x00000000UL /**< Mode INPUT1 for ADC_SCANNEGSEL */ #define _ADC_SCANNEGSEL_INPUT2NEGSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for ADC_SCANNEGSEL */ #define _ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT3 0x00000001UL /**< Mode INPUT3 for ADC_SCANNEGSEL */ #define _ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT5 0x00000002UL /**< Mode INPUT5 for ADC_SCANNEGSEL */ #define _ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT7 0x00000003UL /**< Mode INPUT7 for ADC_SCANNEGSEL */ #define ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT1 (_ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT1 << 2) /**< Shifted mode INPUT1 for ADC_SCANNEGSEL */ #define ADC_SCANNEGSEL_INPUT2NEGSEL_DEFAULT (_ADC_SCANNEGSEL_INPUT2NEGSEL_DEFAULT << 2) /**< Shifted mode DEFAULT for ADC_SCANNEGSEL */ #define ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT3 (_ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT3 << 2) /**< Shifted mode INPUT3 for ADC_SCANNEGSEL */ #define ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT5 (_ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT5 << 2) /**< Shifted mode INPUT5 for ADC_SCANNEGSEL */ #define ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT7 (_ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT7 << 2) /**< Shifted mode INPUT7 for ADC_SCANNEGSEL */ #define _ADC_SCANNEGSEL_INPUT4NEGSEL_SHIFT 4 /**< Shift value for ADC_INPUT4NEGSEL */ #define _ADC_SCANNEGSEL_INPUT4NEGSEL_MASK 0x30UL /**< Bit mask for ADC_INPUT4NEGSEL */ #define _ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT1 0x00000000UL /**< Mode INPUT1 for ADC_SCANNEGSEL */ #define _ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT3 0x00000001UL /**< Mode INPUT3 for ADC_SCANNEGSEL */ #define _ADC_SCANNEGSEL_INPUT4NEGSEL_DEFAULT 0x00000002UL /**< Mode DEFAULT for ADC_SCANNEGSEL */ #define _ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT5 0x00000002UL /**< Mode INPUT5 for ADC_SCANNEGSEL */ #define _ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT7 0x00000003UL /**< Mode INPUT7 for ADC_SCANNEGSEL */ #define ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT1 (_ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT1 << 4) /**< Shifted mode INPUT1 for ADC_SCANNEGSEL */ #define ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT3 (_ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT3 << 4) /**< Shifted mode INPUT3 for ADC_SCANNEGSEL */ #define ADC_SCANNEGSEL_INPUT4NEGSEL_DEFAULT (_ADC_SCANNEGSEL_INPUT4NEGSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for ADC_SCANNEGSEL */ #define ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT5 (_ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT5 << 4) /**< Shifted mode INPUT5 for ADC_SCANNEGSEL */ #define ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT7 (_ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT7 << 4) /**< Shifted mode INPUT7 for ADC_SCANNEGSEL */ #define _ADC_SCANNEGSEL_INPUT6NEGSEL_SHIFT 6 /**< Shift value for ADC_INPUT6NEGSEL */ #define _ADC_SCANNEGSEL_INPUT6NEGSEL_MASK 0xC0UL /**< Bit mask for ADC_INPUT6NEGSEL */ #define _ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT1 0x00000000UL /**< Mode INPUT1 for ADC_SCANNEGSEL */ #define _ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT3 0x00000001UL /**< Mode INPUT3 for ADC_SCANNEGSEL */ #define _ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT5 0x00000002UL /**< Mode INPUT5 for ADC_SCANNEGSEL */ #define _ADC_SCANNEGSEL_INPUT6NEGSEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for ADC_SCANNEGSEL */ #define _ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT7 0x00000003UL /**< Mode INPUT7 for ADC_SCANNEGSEL */ #define ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT1 (_ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT1 << 6) /**< Shifted mode INPUT1 for ADC_SCANNEGSEL */ #define ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT3 (_ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT3 << 6) /**< Shifted mode INPUT3 for ADC_SCANNEGSEL */ #define ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT5 (_ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT5 << 6) /**< Shifted mode INPUT5 for ADC_SCANNEGSEL */ #define ADC_SCANNEGSEL_INPUT6NEGSEL_DEFAULT (_ADC_SCANNEGSEL_INPUT6NEGSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for ADC_SCANNEGSEL */ #define ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT7 (_ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT7 << 6) /**< Shifted mode INPUT7 for ADC_SCANNEGSEL */ #define _ADC_SCANNEGSEL_INPUT9NEGSEL_SHIFT 8 /**< Shift value for ADC_INPUT9NEGSEL */ #define _ADC_SCANNEGSEL_INPUT9NEGSEL_MASK 0x300UL /**< Bit mask for ADC_INPUT9NEGSEL */ #define _ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT8 0x00000000UL /**< Mode INPUT8 for ADC_SCANNEGSEL */ #define _ADC_SCANNEGSEL_INPUT9NEGSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for ADC_SCANNEGSEL */ #define _ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT10 0x00000001UL /**< Mode INPUT10 for ADC_SCANNEGSEL */ #define _ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT12 0x00000002UL /**< Mode INPUT12 for ADC_SCANNEGSEL */ #define _ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT14 0x00000003UL /**< Mode INPUT14 for ADC_SCANNEGSEL */ #define ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT8 (_ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT8 << 8) /**< Shifted mode INPUT8 for ADC_SCANNEGSEL */ #define ADC_SCANNEGSEL_INPUT9NEGSEL_DEFAULT (_ADC_SCANNEGSEL_INPUT9NEGSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_SCANNEGSEL */ #define ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT10 (_ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT10 << 8) /**< Shifted mode INPUT10 for ADC_SCANNEGSEL */ #define ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT12 (_ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT12 << 8) /**< Shifted mode INPUT12 for ADC_SCANNEGSEL */ #define ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT14 (_ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT14 << 8) /**< Shifted mode INPUT14 for ADC_SCANNEGSEL */ #define _ADC_SCANNEGSEL_INPUT11NEGSEL_SHIFT 10 /**< Shift value for ADC_INPUT11NEGSEL */ #define _ADC_SCANNEGSEL_INPUT11NEGSEL_MASK 0xC00UL /**< Bit mask for ADC_INPUT11NEGSEL */ #define _ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT8 0x00000000UL /**< Mode INPUT8 for ADC_SCANNEGSEL */ #define _ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT10 0x00000001UL /**< Mode INPUT10 for ADC_SCANNEGSEL */ #define _ADC_SCANNEGSEL_INPUT11NEGSEL_DEFAULT 0x00000002UL /**< Mode DEFAULT for ADC_SCANNEGSEL */ #define _ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT12 0x00000002UL /**< Mode INPUT12 for ADC_SCANNEGSEL */ #define _ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT14 0x00000003UL /**< Mode INPUT14 for ADC_SCANNEGSEL */ #define ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT8 (_ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT8 << 10) /**< Shifted mode INPUT8 for ADC_SCANNEGSEL */ #define ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT10 (_ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT10 << 10) /**< Shifted mode INPUT10 for ADC_SCANNEGSEL */ #define ADC_SCANNEGSEL_INPUT11NEGSEL_DEFAULT (_ADC_SCANNEGSEL_INPUT11NEGSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for ADC_SCANNEGSEL */ #define ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT12 (_ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT12 << 10) /**< Shifted mode INPUT12 for ADC_SCANNEGSEL */ #define ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT14 (_ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT14 << 10) /**< Shifted mode INPUT14 for ADC_SCANNEGSEL */ #define _ADC_SCANNEGSEL_INPUT13NEGSEL_SHIFT 12 /**< Shift value for ADC_INPUT13NEGSEL */ #define _ADC_SCANNEGSEL_INPUT13NEGSEL_MASK 0x3000UL /**< Bit mask for ADC_INPUT13NEGSEL */ #define _ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT8 0x00000000UL /**< Mode INPUT8 for ADC_SCANNEGSEL */ #define _ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT10 0x00000001UL /**< Mode INPUT10 for ADC_SCANNEGSEL */ #define _ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT12 0x00000002UL /**< Mode INPUT12 for ADC_SCANNEGSEL */ #define _ADC_SCANNEGSEL_INPUT13NEGSEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for ADC_SCANNEGSEL */ #define _ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT14 0x00000003UL /**< Mode INPUT14 for ADC_SCANNEGSEL */ #define ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT8 (_ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT8 << 12) /**< Shifted mode INPUT8 for ADC_SCANNEGSEL */ #define ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT10 (_ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT10 << 12) /**< Shifted mode INPUT10 for ADC_SCANNEGSEL */ #define ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT12 (_ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT12 << 12) /**< Shifted mode INPUT12 for ADC_SCANNEGSEL */ #define ADC_SCANNEGSEL_INPUT13NEGSEL_DEFAULT (_ADC_SCANNEGSEL_INPUT13NEGSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for ADC_SCANNEGSEL */ #define ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT14 (_ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT14 << 12) /**< Shifted mode INPUT14 for ADC_SCANNEGSEL */ #define _ADC_SCANNEGSEL_INPUT15NEGSEL_SHIFT 14 /**< Shift value for ADC_INPUT15NEGSEL */ #define _ADC_SCANNEGSEL_INPUT15NEGSEL_MASK 0xC000UL /**< Bit mask for ADC_INPUT15NEGSEL */ #define _ADC_SCANNEGSEL_INPUT15NEGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANNEGSEL */ #define _ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT8 0x00000000UL /**< Mode INPUT8 for ADC_SCANNEGSEL */ #define _ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT10 0x00000001UL /**< Mode INPUT10 for ADC_SCANNEGSEL */ #define _ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT12 0x00000002UL /**< Mode INPUT12 for ADC_SCANNEGSEL */ #define _ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT14 0x00000003UL /**< Mode INPUT14 for ADC_SCANNEGSEL */ #define ADC_SCANNEGSEL_INPUT15NEGSEL_DEFAULT (_ADC_SCANNEGSEL_INPUT15NEGSEL_DEFAULT << 14) /**< Shifted mode DEFAULT for ADC_SCANNEGSEL */ #define ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT8 (_ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT8 << 14) /**< Shifted mode INPUT8 for ADC_SCANNEGSEL */ #define ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT10 (_ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT10 << 14) /**< Shifted mode INPUT10 for ADC_SCANNEGSEL */ #define ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT12 (_ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT12 << 14) /**< Shifted mode INPUT12 for ADC_SCANNEGSEL */ #define ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT14 (_ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT14 << 14) /**< Shifted mode INPUT14 for ADC_SCANNEGSEL */ /* Bit fields for ADC CMPTHR */ #define _ADC_CMPTHR_RESETVALUE 0x00000000UL /**< Default value for ADC_CMPTHR */ #define _ADC_CMPTHR_MASK 0xFFFFFFFFUL /**< Mask for ADC_CMPTHR */ #define _ADC_CMPTHR_ADLT_SHIFT 0 /**< Shift value for ADC_ADLT */ #define _ADC_CMPTHR_ADLT_MASK 0xFFFFUL /**< Bit mask for ADC_ADLT */ #define _ADC_CMPTHR_ADLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CMPTHR */ #define ADC_CMPTHR_ADLT_DEFAULT (_ADC_CMPTHR_ADLT_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_CMPTHR */ #define _ADC_CMPTHR_ADGT_SHIFT 16 /**< Shift value for ADC_ADGT */ #define _ADC_CMPTHR_ADGT_MASK 0xFFFF0000UL /**< Bit mask for ADC_ADGT */ #define _ADC_CMPTHR_ADGT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CMPTHR */ #define ADC_CMPTHR_ADGT_DEFAULT (_ADC_CMPTHR_ADGT_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_CMPTHR */ /* Bit fields for ADC BIASPROG */ #define _ADC_BIASPROG_RESETVALUE 0x00000000UL /**< Default value for ADC_BIASPROG */ #define _ADC_BIASPROG_MASK 0x0001100FUL /**< Mask for ADC_BIASPROG */ #define _ADC_BIASPROG_ADCBIASPROG_SHIFT 0 /**< Shift value for ADC_ADCBIASPROG */ #define _ADC_BIASPROG_ADCBIASPROG_MASK 0xFUL /**< Bit mask for ADC_ADCBIASPROG */ #define _ADC_BIASPROG_ADCBIASPROG_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_BIASPROG */ #define _ADC_BIASPROG_ADCBIASPROG_NORMAL 0x00000000UL /**< Mode NORMAL for ADC_BIASPROG */ #define _ADC_BIASPROG_ADCBIASPROG_SCALE2 0x00000004UL /**< Mode SCALE2 for ADC_BIASPROG */ #define _ADC_BIASPROG_ADCBIASPROG_SCALE4 0x00000008UL /**< Mode SCALE4 for ADC_BIASPROG */ #define _ADC_BIASPROG_ADCBIASPROG_SCALE8 0x0000000CUL /**< Mode SCALE8 for ADC_BIASPROG */ #define _ADC_BIASPROG_ADCBIASPROG_SCALE16 0x0000000EUL /**< Mode SCALE16 for ADC_BIASPROG */ #define _ADC_BIASPROG_ADCBIASPROG_SCALE32 0x0000000FUL /**< Mode SCALE32 for ADC_BIASPROG */ #define ADC_BIASPROG_ADCBIASPROG_DEFAULT (_ADC_BIASPROG_ADCBIASPROG_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_BIASPROG */ #define ADC_BIASPROG_ADCBIASPROG_NORMAL (_ADC_BIASPROG_ADCBIASPROG_NORMAL << 0) /**< Shifted mode NORMAL for ADC_BIASPROG */ #define ADC_BIASPROG_ADCBIASPROG_SCALE2 (_ADC_BIASPROG_ADCBIASPROG_SCALE2 << 0) /**< Shifted mode SCALE2 for ADC_BIASPROG */ #define ADC_BIASPROG_ADCBIASPROG_SCALE4 (_ADC_BIASPROG_ADCBIASPROG_SCALE4 << 0) /**< Shifted mode SCALE4 for ADC_BIASPROG */ #define ADC_BIASPROG_ADCBIASPROG_SCALE8 (_ADC_BIASPROG_ADCBIASPROG_SCALE8 << 0) /**< Shifted mode SCALE8 for ADC_BIASPROG */ #define ADC_BIASPROG_ADCBIASPROG_SCALE16 (_ADC_BIASPROG_ADCBIASPROG_SCALE16 << 0) /**< Shifted mode SCALE16 for ADC_BIASPROG */ #define ADC_BIASPROG_ADCBIASPROG_SCALE32 (_ADC_BIASPROG_ADCBIASPROG_SCALE32 << 0) /**< Shifted mode SCALE32 for ADC_BIASPROG */ #define ADC_BIASPROG_VFAULTCLR (0x1UL << 12) /**< Clear VREFOF Flag */ #define _ADC_BIASPROG_VFAULTCLR_SHIFT 12 /**< Shift value for ADC_VFAULTCLR */ #define _ADC_BIASPROG_VFAULTCLR_MASK 0x1000UL /**< Bit mask for ADC_VFAULTCLR */ #define _ADC_BIASPROG_VFAULTCLR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_BIASPROG */ #define ADC_BIASPROG_VFAULTCLR_DEFAULT (_ADC_BIASPROG_VFAULTCLR_DEFAULT << 12) /**< Shifted mode DEFAULT for ADC_BIASPROG */ #define ADC_BIASPROG_GPBIASACC (0x1UL << 16) /**< Accuracy Setting for the System Bias During ADC Operation */ #define _ADC_BIASPROG_GPBIASACC_SHIFT 16 /**< Shift value for ADC_GPBIASACC */ #define _ADC_BIASPROG_GPBIASACC_MASK 0x10000UL /**< Bit mask for ADC_GPBIASACC */ #define _ADC_BIASPROG_GPBIASACC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_BIASPROG */ #define _ADC_BIASPROG_GPBIASACC_HIGHACC 0x00000000UL /**< Mode HIGHACC for ADC_BIASPROG */ #define _ADC_BIASPROG_GPBIASACC_LOWACC 0x00000001UL /**< Mode LOWACC for ADC_BIASPROG */ #define ADC_BIASPROG_GPBIASACC_DEFAULT (_ADC_BIASPROG_GPBIASACC_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_BIASPROG */ #define ADC_BIASPROG_GPBIASACC_HIGHACC (_ADC_BIASPROG_GPBIASACC_HIGHACC << 16) /**< Shifted mode HIGHACC for ADC_BIASPROG */ #define ADC_BIASPROG_GPBIASACC_LOWACC (_ADC_BIASPROG_GPBIASACC_LOWACC << 16) /**< Shifted mode LOWACC for ADC_BIASPROG */ /* Bit fields for ADC CAL */ #define _ADC_CAL_RESETVALUE 0x40784078UL /**< Default value for ADC_CAL */ #define _ADC_CAL_MASK 0xFFFFFFFFUL /**< Mask for ADC_CAL */ #define _ADC_CAL_SINGLEOFFSET_SHIFT 0 /**< Shift value for ADC_SINGLEOFFSET */ #define _ADC_CAL_SINGLEOFFSET_MASK 0xFUL /**< Bit mask for ADC_SINGLEOFFSET */ #define _ADC_CAL_SINGLEOFFSET_DEFAULT 0x00000008UL /**< Mode DEFAULT for ADC_CAL */ #define ADC_CAL_SINGLEOFFSET_DEFAULT (_ADC_CAL_SINGLEOFFSET_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_CAL */ #define _ADC_CAL_SINGLEOFFSETINV_SHIFT 4 /**< Shift value for ADC_SINGLEOFFSETINV */ #define _ADC_CAL_SINGLEOFFSETINV_MASK 0xF0UL /**< Bit mask for ADC_SINGLEOFFSETINV */ #define _ADC_CAL_SINGLEOFFSETINV_DEFAULT 0x00000007UL /**< Mode DEFAULT for ADC_CAL */ #define ADC_CAL_SINGLEOFFSETINV_DEFAULT (_ADC_CAL_SINGLEOFFSETINV_DEFAULT << 4) /**< Shifted mode DEFAULT for ADC_CAL */ #define _ADC_CAL_SINGLEGAIN_SHIFT 8 /**< Shift value for ADC_SINGLEGAIN */ #define _ADC_CAL_SINGLEGAIN_MASK 0x7F00UL /**< Bit mask for ADC_SINGLEGAIN */ #define _ADC_CAL_SINGLEGAIN_DEFAULT 0x00000040UL /**< Mode DEFAULT for ADC_CAL */ #define ADC_CAL_SINGLEGAIN_DEFAULT (_ADC_CAL_SINGLEGAIN_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_CAL */ #define ADC_CAL_OFFSETINVMODE (0x1UL << 15) /**< Negative Single-ended Offset Calibration is Enabled */ #define _ADC_CAL_OFFSETINVMODE_SHIFT 15 /**< Shift value for ADC_OFFSETINVMODE */ #define _ADC_CAL_OFFSETINVMODE_MASK 0x8000UL /**< Bit mask for ADC_OFFSETINVMODE */ #define _ADC_CAL_OFFSETINVMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CAL */ #define ADC_CAL_OFFSETINVMODE_DEFAULT (_ADC_CAL_OFFSETINVMODE_DEFAULT << 15) /**< Shifted mode DEFAULT for ADC_CAL */ #define _ADC_CAL_SCANOFFSET_SHIFT 16 /**< Shift value for ADC_SCANOFFSET */ #define _ADC_CAL_SCANOFFSET_MASK 0xF0000UL /**< Bit mask for ADC_SCANOFFSET */ #define _ADC_CAL_SCANOFFSET_DEFAULT 0x00000008UL /**< Mode DEFAULT for ADC_CAL */ #define ADC_CAL_SCANOFFSET_DEFAULT (_ADC_CAL_SCANOFFSET_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_CAL */ #define _ADC_CAL_SCANOFFSETINV_SHIFT 20 /**< Shift value for ADC_SCANOFFSETINV */ #define _ADC_CAL_SCANOFFSETINV_MASK 0xF00000UL /**< Bit mask for ADC_SCANOFFSETINV */ #define _ADC_CAL_SCANOFFSETINV_DEFAULT 0x00000007UL /**< Mode DEFAULT for ADC_CAL */ #define ADC_CAL_SCANOFFSETINV_DEFAULT (_ADC_CAL_SCANOFFSETINV_DEFAULT << 20) /**< Shifted mode DEFAULT for ADC_CAL */ #define _ADC_CAL_SCANGAIN_SHIFT 24 /**< Shift value for ADC_SCANGAIN */ #define _ADC_CAL_SCANGAIN_MASK 0x7F000000UL /**< Bit mask for ADC_SCANGAIN */ #define _ADC_CAL_SCANGAIN_DEFAULT 0x00000040UL /**< Mode DEFAULT for ADC_CAL */ #define ADC_CAL_SCANGAIN_DEFAULT (_ADC_CAL_SCANGAIN_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_CAL */ #define ADC_CAL_CALEN (0x1UL << 31) /**< Calibration Mode is Enabled */ #define _ADC_CAL_CALEN_SHIFT 31 /**< Shift value for ADC_CALEN */ #define _ADC_CAL_CALEN_MASK 0x80000000UL /**< Bit mask for ADC_CALEN */ #define _ADC_CAL_CALEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CAL */ #define ADC_CAL_CALEN_DEFAULT (_ADC_CAL_CALEN_DEFAULT << 31) /**< Shifted mode DEFAULT for ADC_CAL */ /* Bit fields for ADC IF */ #define _ADC_IF_RESETVALUE 0x00000000UL /**< Default value for ADC_IF */ #define _ADC_IF_MASK 0x3F030F03UL /**< Mask for ADC_IF */ #define ADC_IF_SINGLE (0x1UL << 0) /**< Single Conversion Complete Interrupt Flag */ #define _ADC_IF_SINGLE_SHIFT 0 /**< Shift value for ADC_SINGLE */ #define _ADC_IF_SINGLE_MASK 0x1UL /**< Bit mask for ADC_SINGLE */ #define _ADC_IF_SINGLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */ #define ADC_IF_SINGLE_DEFAULT (_ADC_IF_SINGLE_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_IF */ #define ADC_IF_SCAN (0x1UL << 1) /**< Scan Conversion Complete Interrupt Flag */ #define _ADC_IF_SCAN_SHIFT 1 /**< Shift value for ADC_SCAN */ #define _ADC_IF_SCAN_MASK 0x2UL /**< Bit mask for ADC_SCAN */ #define _ADC_IF_SCAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */ #define ADC_IF_SCAN_DEFAULT (_ADC_IF_SCAN_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_IF */ #define ADC_IF_SINGLEOF (0x1UL << 8) /**< Single FIFO Overflow Interrupt Flag */ #define _ADC_IF_SINGLEOF_SHIFT 8 /**< Shift value for ADC_SINGLEOF */ #define _ADC_IF_SINGLEOF_MASK 0x100UL /**< Bit mask for ADC_SINGLEOF */ #define _ADC_IF_SINGLEOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */ #define ADC_IF_SINGLEOF_DEFAULT (_ADC_IF_SINGLEOF_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_IF */ #define ADC_IF_SCANOF (0x1UL << 9) /**< Scan FIFO Overflow Interrupt Flag */ #define _ADC_IF_SCANOF_SHIFT 9 /**< Shift value for ADC_SCANOF */ #define _ADC_IF_SCANOF_MASK 0x200UL /**< Bit mask for ADC_SCANOF */ #define _ADC_IF_SCANOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */ #define ADC_IF_SCANOF_DEFAULT (_ADC_IF_SCANOF_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_IF */ #define ADC_IF_SINGLEUF (0x1UL << 10) /**< Single FIFO Underflow Interrupt Flag */ #define _ADC_IF_SINGLEUF_SHIFT 10 /**< Shift value for ADC_SINGLEUF */ #define _ADC_IF_SINGLEUF_MASK 0x400UL /**< Bit mask for ADC_SINGLEUF */ #define _ADC_IF_SINGLEUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */ #define ADC_IF_SINGLEUF_DEFAULT (_ADC_IF_SINGLEUF_DEFAULT << 10) /**< Shifted mode DEFAULT for ADC_IF */ #define ADC_IF_SCANUF (0x1UL << 11) /**< Scan FIFO Underflow Interrupt Flag */ #define _ADC_IF_SCANUF_SHIFT 11 /**< Shift value for ADC_SCANUF */ #define _ADC_IF_SCANUF_MASK 0x800UL /**< Bit mask for ADC_SCANUF */ #define _ADC_IF_SCANUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */ #define ADC_IF_SCANUF_DEFAULT (_ADC_IF_SCANUF_DEFAULT << 11) /**< Shifted mode DEFAULT for ADC_IF */ #define ADC_IF_SINGLECMP (0x1UL << 16) /**< Single Result Compare Match Interrupt Flag */ #define _ADC_IF_SINGLECMP_SHIFT 16 /**< Shift value for ADC_SINGLECMP */ #define _ADC_IF_SINGLECMP_MASK 0x10000UL /**< Bit mask for ADC_SINGLECMP */ #define _ADC_IF_SINGLECMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */ #define ADC_IF_SINGLECMP_DEFAULT (_ADC_IF_SINGLECMP_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_IF */ #define ADC_IF_SCANCMP (0x1UL << 17) /**< Scan Result Compare Match Interrupt Flag */ #define _ADC_IF_SCANCMP_SHIFT 17 /**< Shift value for ADC_SCANCMP */ #define _ADC_IF_SCANCMP_MASK 0x20000UL /**< Bit mask for ADC_SCANCMP */ #define _ADC_IF_SCANCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */ #define ADC_IF_SCANCMP_DEFAULT (_ADC_IF_SCANCMP_DEFAULT << 17) /**< Shifted mode DEFAULT for ADC_IF */ #define ADC_IF_VREFOV (0x1UL << 24) /**< VREF Over Voltage Interrupt Flag */ #define _ADC_IF_VREFOV_SHIFT 24 /**< Shift value for ADC_VREFOV */ #define _ADC_IF_VREFOV_MASK 0x1000000UL /**< Bit mask for ADC_VREFOV */ #define _ADC_IF_VREFOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */ #define ADC_IF_VREFOV_DEFAULT (_ADC_IF_VREFOV_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_IF */ #define ADC_IF_PROGERR (0x1UL << 25) /**< Programming Error Interrupt Flag */ #define _ADC_IF_PROGERR_SHIFT 25 /**< Shift value for ADC_PROGERR */ #define _ADC_IF_PROGERR_MASK 0x2000000UL /**< Bit mask for ADC_PROGERR */ #define _ADC_IF_PROGERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */ #define ADC_IF_PROGERR_DEFAULT (_ADC_IF_PROGERR_DEFAULT << 25) /**< Shifted mode DEFAULT for ADC_IF */ #define ADC_IF_SCANEXTPEND (0x1UL << 26) /**< External Scan Trigger Pending Flag */ #define _ADC_IF_SCANEXTPEND_SHIFT 26 /**< Shift value for ADC_SCANEXTPEND */ #define _ADC_IF_SCANEXTPEND_MASK 0x4000000UL /**< Bit mask for ADC_SCANEXTPEND */ #define _ADC_IF_SCANEXTPEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */ #define ADC_IF_SCANEXTPEND_DEFAULT (_ADC_IF_SCANEXTPEND_DEFAULT << 26) /**< Shifted mode DEFAULT for ADC_IF */ #define ADC_IF_SCANPEND (0x1UL << 27) /**< Scan Trigger Pending Flag */ #define _ADC_IF_SCANPEND_SHIFT 27 /**< Shift value for ADC_SCANPEND */ #define _ADC_IF_SCANPEND_MASK 0x8000000UL /**< Bit mask for ADC_SCANPEND */ #define _ADC_IF_SCANPEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */ #define ADC_IF_SCANPEND_DEFAULT (_ADC_IF_SCANPEND_DEFAULT << 27) /**< Shifted mode DEFAULT for ADC_IF */ #define ADC_IF_PRSTIMEDERR (0x1UL << 28) /**< PRS Timed Mode Error Flag */ #define _ADC_IF_PRSTIMEDERR_SHIFT 28 /**< Shift value for ADC_PRSTIMEDERR */ #define _ADC_IF_PRSTIMEDERR_MASK 0x10000000UL /**< Bit mask for ADC_PRSTIMEDERR */ #define _ADC_IF_PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */ #define ADC_IF_PRSTIMEDERR_DEFAULT (_ADC_IF_PRSTIMEDERR_DEFAULT << 28) /**< Shifted mode DEFAULT for ADC_IF */ #define ADC_IF_EM23ERR (0x1UL << 29) /**< EM23 Entry Error Flag */ #define _ADC_IF_EM23ERR_SHIFT 29 /**< Shift value for ADC_EM23ERR */ #define _ADC_IF_EM23ERR_MASK 0x20000000UL /**< Bit mask for ADC_EM23ERR */ #define _ADC_IF_EM23ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */ #define ADC_IF_EM23ERR_DEFAULT (_ADC_IF_EM23ERR_DEFAULT << 29) /**< Shifted mode DEFAULT for ADC_IF */ /* Bit fields for ADC IFS */ #define _ADC_IFS_RESETVALUE 0x00000000UL /**< Default value for ADC_IFS */ #define _ADC_IFS_MASK 0x3F030F00UL /**< Mask for ADC_IFS */ #define ADC_IFS_SINGLEOF (0x1UL << 8) /**< Set SINGLEOF Interrupt Flag */ #define _ADC_IFS_SINGLEOF_SHIFT 8 /**< Shift value for ADC_SINGLEOF */ #define _ADC_IFS_SINGLEOF_MASK 0x100UL /**< Bit mask for ADC_SINGLEOF */ #define _ADC_IFS_SINGLEOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */ #define ADC_IFS_SINGLEOF_DEFAULT (_ADC_IFS_SINGLEOF_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_IFS */ #define ADC_IFS_SCANOF (0x1UL << 9) /**< Set SCANOF Interrupt Flag */ #define _ADC_IFS_SCANOF_SHIFT 9 /**< Shift value for ADC_SCANOF */ #define _ADC_IFS_SCANOF_MASK 0x200UL /**< Bit mask for ADC_SCANOF */ #define _ADC_IFS_SCANOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */ #define ADC_IFS_SCANOF_DEFAULT (_ADC_IFS_SCANOF_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_IFS */ #define ADC_IFS_SINGLEUF (0x1UL << 10) /**< Set SINGLEUF Interrupt Flag */ #define _ADC_IFS_SINGLEUF_SHIFT 10 /**< Shift value for ADC_SINGLEUF */ #define _ADC_IFS_SINGLEUF_MASK 0x400UL /**< Bit mask for ADC_SINGLEUF */ #define _ADC_IFS_SINGLEUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */ #define ADC_IFS_SINGLEUF_DEFAULT (_ADC_IFS_SINGLEUF_DEFAULT << 10) /**< Shifted mode DEFAULT for ADC_IFS */ #define ADC_IFS_SCANUF (0x1UL << 11) /**< Set SCANUF Interrupt Flag */ #define _ADC_IFS_SCANUF_SHIFT 11 /**< Shift value for ADC_SCANUF */ #define _ADC_IFS_SCANUF_MASK 0x800UL /**< Bit mask for ADC_SCANUF */ #define _ADC_IFS_SCANUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */ #define ADC_IFS_SCANUF_DEFAULT (_ADC_IFS_SCANUF_DEFAULT << 11) /**< Shifted mode DEFAULT for ADC_IFS */ #define ADC_IFS_SINGLECMP (0x1UL << 16) /**< Set SINGLECMP Interrupt Flag */ #define _ADC_IFS_SINGLECMP_SHIFT 16 /**< Shift value for ADC_SINGLECMP */ #define _ADC_IFS_SINGLECMP_MASK 0x10000UL /**< Bit mask for ADC_SINGLECMP */ #define _ADC_IFS_SINGLECMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */ #define ADC_IFS_SINGLECMP_DEFAULT (_ADC_IFS_SINGLECMP_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_IFS */ #define ADC_IFS_SCANCMP (0x1UL << 17) /**< Set SCANCMP Interrupt Flag */ #define _ADC_IFS_SCANCMP_SHIFT 17 /**< Shift value for ADC_SCANCMP */ #define _ADC_IFS_SCANCMP_MASK 0x20000UL /**< Bit mask for ADC_SCANCMP */ #define _ADC_IFS_SCANCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */ #define ADC_IFS_SCANCMP_DEFAULT (_ADC_IFS_SCANCMP_DEFAULT << 17) /**< Shifted mode DEFAULT for ADC_IFS */ #define ADC_IFS_VREFOV (0x1UL << 24) /**< Set VREFOV Interrupt Flag */ #define _ADC_IFS_VREFOV_SHIFT 24 /**< Shift value for ADC_VREFOV */ #define _ADC_IFS_VREFOV_MASK 0x1000000UL /**< Bit mask for ADC_VREFOV */ #define _ADC_IFS_VREFOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */ #define ADC_IFS_VREFOV_DEFAULT (_ADC_IFS_VREFOV_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_IFS */ #define ADC_IFS_PROGERR (0x1UL << 25) /**< Set PROGERR Interrupt Flag */ #define _ADC_IFS_PROGERR_SHIFT 25 /**< Shift value for ADC_PROGERR */ #define _ADC_IFS_PROGERR_MASK 0x2000000UL /**< Bit mask for ADC_PROGERR */ #define _ADC_IFS_PROGERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */ #define ADC_IFS_PROGERR_DEFAULT (_ADC_IFS_PROGERR_DEFAULT << 25) /**< Shifted mode DEFAULT for ADC_IFS */ #define ADC_IFS_SCANEXTPEND (0x1UL << 26) /**< Set SCANEXTPEND Interrupt Flag */ #define _ADC_IFS_SCANEXTPEND_SHIFT 26 /**< Shift value for ADC_SCANEXTPEND */ #define _ADC_IFS_SCANEXTPEND_MASK 0x4000000UL /**< Bit mask for ADC_SCANEXTPEND */ #define _ADC_IFS_SCANEXTPEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */ #define ADC_IFS_SCANEXTPEND_DEFAULT (_ADC_IFS_SCANEXTPEND_DEFAULT << 26) /**< Shifted mode DEFAULT for ADC_IFS */ #define ADC_IFS_SCANPEND (0x1UL << 27) /**< Set SCANPEND Interrupt Flag */ #define _ADC_IFS_SCANPEND_SHIFT 27 /**< Shift value for ADC_SCANPEND */ #define _ADC_IFS_SCANPEND_MASK 0x8000000UL /**< Bit mask for ADC_SCANPEND */ #define _ADC_IFS_SCANPEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */ #define ADC_IFS_SCANPEND_DEFAULT (_ADC_IFS_SCANPEND_DEFAULT << 27) /**< Shifted mode DEFAULT for ADC_IFS */ #define ADC_IFS_PRSTIMEDERR (0x1UL << 28) /**< Set PRSTIMEDERR Interrupt Flag */ #define _ADC_IFS_PRSTIMEDERR_SHIFT 28 /**< Shift value for ADC_PRSTIMEDERR */ #define _ADC_IFS_PRSTIMEDERR_MASK 0x10000000UL /**< Bit mask for ADC_PRSTIMEDERR */ #define _ADC_IFS_PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */ #define ADC_IFS_PRSTIMEDERR_DEFAULT (_ADC_IFS_PRSTIMEDERR_DEFAULT << 28) /**< Shifted mode DEFAULT for ADC_IFS */ #define ADC_IFS_EM23ERR (0x1UL << 29) /**< Set EM23ERR Interrupt Flag */ #define _ADC_IFS_EM23ERR_SHIFT 29 /**< Shift value for ADC_EM23ERR */ #define _ADC_IFS_EM23ERR_MASK 0x20000000UL /**< Bit mask for ADC_EM23ERR */ #define _ADC_IFS_EM23ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */ #define ADC_IFS_EM23ERR_DEFAULT (_ADC_IFS_EM23ERR_DEFAULT << 29) /**< Shifted mode DEFAULT for ADC_IFS */ /* Bit fields for ADC IFC */ #define _ADC_IFC_RESETVALUE 0x00000000UL /**< Default value for ADC_IFC */ #define _ADC_IFC_MASK 0x3F030F00UL /**< Mask for ADC_IFC */ #define ADC_IFC_SINGLEOF (0x1UL << 8) /**< Clear SINGLEOF Interrupt Flag */ #define _ADC_IFC_SINGLEOF_SHIFT 8 /**< Shift value for ADC_SINGLEOF */ #define _ADC_IFC_SINGLEOF_MASK 0x100UL /**< Bit mask for ADC_SINGLEOF */ #define _ADC_IFC_SINGLEOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */ #define ADC_IFC_SINGLEOF_DEFAULT (_ADC_IFC_SINGLEOF_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_IFC */ #define ADC_IFC_SCANOF (0x1UL << 9) /**< Clear SCANOF Interrupt Flag */ #define _ADC_IFC_SCANOF_SHIFT 9 /**< Shift value for ADC_SCANOF */ #define _ADC_IFC_SCANOF_MASK 0x200UL /**< Bit mask for ADC_SCANOF */ #define _ADC_IFC_SCANOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */ #define ADC_IFC_SCANOF_DEFAULT (_ADC_IFC_SCANOF_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_IFC */ #define ADC_IFC_SINGLEUF (0x1UL << 10) /**< Clear SINGLEUF Interrupt Flag */ #define _ADC_IFC_SINGLEUF_SHIFT 10 /**< Shift value for ADC_SINGLEUF */ #define _ADC_IFC_SINGLEUF_MASK 0x400UL /**< Bit mask for ADC_SINGLEUF */ #define _ADC_IFC_SINGLEUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */ #define ADC_IFC_SINGLEUF_DEFAULT (_ADC_IFC_SINGLEUF_DEFAULT << 10) /**< Shifted mode DEFAULT for ADC_IFC */ #define ADC_IFC_SCANUF (0x1UL << 11) /**< Clear SCANUF Interrupt Flag */ #define _ADC_IFC_SCANUF_SHIFT 11 /**< Shift value for ADC_SCANUF */ #define _ADC_IFC_SCANUF_MASK 0x800UL /**< Bit mask for ADC_SCANUF */ #define _ADC_IFC_SCANUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */ #define ADC_IFC_SCANUF_DEFAULT (_ADC_IFC_SCANUF_DEFAULT << 11) /**< Shifted mode DEFAULT for ADC_IFC */ #define ADC_IFC_SINGLECMP (0x1UL << 16) /**< Clear SINGLECMP Interrupt Flag */ #define _ADC_IFC_SINGLECMP_SHIFT 16 /**< Shift value for ADC_SINGLECMP */ #define _ADC_IFC_SINGLECMP_MASK 0x10000UL /**< Bit mask for ADC_SINGLECMP */ #define _ADC_IFC_SINGLECMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */ #define ADC_IFC_SINGLECMP_DEFAULT (_ADC_IFC_SINGLECMP_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_IFC */ #define ADC_IFC_SCANCMP (0x1UL << 17) /**< Clear SCANCMP Interrupt Flag */ #define _ADC_IFC_SCANCMP_SHIFT 17 /**< Shift value for ADC_SCANCMP */ #define _ADC_IFC_SCANCMP_MASK 0x20000UL /**< Bit mask for ADC_SCANCMP */ #define _ADC_IFC_SCANCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */ #define ADC_IFC_SCANCMP_DEFAULT (_ADC_IFC_SCANCMP_DEFAULT << 17) /**< Shifted mode DEFAULT for ADC_IFC */ #define ADC_IFC_VREFOV (0x1UL << 24) /**< Clear VREFOV Interrupt Flag */ #define _ADC_IFC_VREFOV_SHIFT 24 /**< Shift value for ADC_VREFOV */ #define _ADC_IFC_VREFOV_MASK 0x1000000UL /**< Bit mask for ADC_VREFOV */ #define _ADC_IFC_VREFOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */ #define ADC_IFC_VREFOV_DEFAULT (_ADC_IFC_VREFOV_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_IFC */ #define ADC_IFC_PROGERR (0x1UL << 25) /**< Clear PROGERR Interrupt Flag */ #define _ADC_IFC_PROGERR_SHIFT 25 /**< Shift value for ADC_PROGERR */ #define _ADC_IFC_PROGERR_MASK 0x2000000UL /**< Bit mask for ADC_PROGERR */ #define _ADC_IFC_PROGERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */ #define ADC_IFC_PROGERR_DEFAULT (_ADC_IFC_PROGERR_DEFAULT << 25) /**< Shifted mode DEFAULT for ADC_IFC */ #define ADC_IFC_SCANEXTPEND (0x1UL << 26) /**< Clear SCANEXTPEND Interrupt Flag */ #define _ADC_IFC_SCANEXTPEND_SHIFT 26 /**< Shift value for ADC_SCANEXTPEND */ #define _ADC_IFC_SCANEXTPEND_MASK 0x4000000UL /**< Bit mask for ADC_SCANEXTPEND */ #define _ADC_IFC_SCANEXTPEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */ #define ADC_IFC_SCANEXTPEND_DEFAULT (_ADC_IFC_SCANEXTPEND_DEFAULT << 26) /**< Shifted mode DEFAULT for ADC_IFC */ #define ADC_IFC_SCANPEND (0x1UL << 27) /**< Clear SCANPEND Interrupt Flag */ #define _ADC_IFC_SCANPEND_SHIFT 27 /**< Shift value for ADC_SCANPEND */ #define _ADC_IFC_SCANPEND_MASK 0x8000000UL /**< Bit mask for ADC_SCANPEND */ #define _ADC_IFC_SCANPEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */ #define ADC_IFC_SCANPEND_DEFAULT (_ADC_IFC_SCANPEND_DEFAULT << 27) /**< Shifted mode DEFAULT for ADC_IFC */ #define ADC_IFC_PRSTIMEDERR (0x1UL << 28) /**< Clear PRSTIMEDERR Interrupt Flag */ #define _ADC_IFC_PRSTIMEDERR_SHIFT 28 /**< Shift value for ADC_PRSTIMEDERR */ #define _ADC_IFC_PRSTIMEDERR_MASK 0x10000000UL /**< Bit mask for ADC_PRSTIMEDERR */ #define _ADC_IFC_PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */ #define ADC_IFC_PRSTIMEDERR_DEFAULT (_ADC_IFC_PRSTIMEDERR_DEFAULT << 28) /**< Shifted mode DEFAULT for ADC_IFC */ #define ADC_IFC_EM23ERR (0x1UL << 29) /**< Clear EM23ERR Interrupt Flag */ #define _ADC_IFC_EM23ERR_SHIFT 29 /**< Shift value for ADC_EM23ERR */ #define _ADC_IFC_EM23ERR_MASK 0x20000000UL /**< Bit mask for ADC_EM23ERR */ #define _ADC_IFC_EM23ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */ #define ADC_IFC_EM23ERR_DEFAULT (_ADC_IFC_EM23ERR_DEFAULT << 29) /**< Shifted mode DEFAULT for ADC_IFC */ /* Bit fields for ADC IEN */ #define _ADC_IEN_RESETVALUE 0x00000000UL /**< Default value for ADC_IEN */ #define _ADC_IEN_MASK 0x3F030F03UL /**< Mask for ADC_IEN */ #define ADC_IEN_SINGLE (0x1UL << 0) /**< SINGLE Interrupt Enable */ #define _ADC_IEN_SINGLE_SHIFT 0 /**< Shift value for ADC_SINGLE */ #define _ADC_IEN_SINGLE_MASK 0x1UL /**< Bit mask for ADC_SINGLE */ #define _ADC_IEN_SINGLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */ #define ADC_IEN_SINGLE_DEFAULT (_ADC_IEN_SINGLE_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_IEN */ #define ADC_IEN_SCAN (0x1UL << 1) /**< SCAN Interrupt Enable */ #define _ADC_IEN_SCAN_SHIFT 1 /**< Shift value for ADC_SCAN */ #define _ADC_IEN_SCAN_MASK 0x2UL /**< Bit mask for ADC_SCAN */ #define _ADC_IEN_SCAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */ #define ADC_IEN_SCAN_DEFAULT (_ADC_IEN_SCAN_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_IEN */ #define ADC_IEN_SINGLEOF (0x1UL << 8) /**< SINGLEOF Interrupt Enable */ #define _ADC_IEN_SINGLEOF_SHIFT 8 /**< Shift value for ADC_SINGLEOF */ #define _ADC_IEN_SINGLEOF_MASK 0x100UL /**< Bit mask for ADC_SINGLEOF */ #define _ADC_IEN_SINGLEOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */ #define ADC_IEN_SINGLEOF_DEFAULT (_ADC_IEN_SINGLEOF_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_IEN */ #define ADC_IEN_SCANOF (0x1UL << 9) /**< SCANOF Interrupt Enable */ #define _ADC_IEN_SCANOF_SHIFT 9 /**< Shift value for ADC_SCANOF */ #define _ADC_IEN_SCANOF_MASK 0x200UL /**< Bit mask for ADC_SCANOF */ #define _ADC_IEN_SCANOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */ #define ADC_IEN_SCANOF_DEFAULT (_ADC_IEN_SCANOF_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_IEN */ #define ADC_IEN_SINGLEUF (0x1UL << 10) /**< SINGLEUF Interrupt Enable */ #define _ADC_IEN_SINGLEUF_SHIFT 10 /**< Shift value for ADC_SINGLEUF */ #define _ADC_IEN_SINGLEUF_MASK 0x400UL /**< Bit mask for ADC_SINGLEUF */ #define _ADC_IEN_SINGLEUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */ #define ADC_IEN_SINGLEUF_DEFAULT (_ADC_IEN_SINGLEUF_DEFAULT << 10) /**< Shifted mode DEFAULT for ADC_IEN */ #define ADC_IEN_SCANUF (0x1UL << 11) /**< SCANUF Interrupt Enable */ #define _ADC_IEN_SCANUF_SHIFT 11 /**< Shift value for ADC_SCANUF */ #define _ADC_IEN_SCANUF_MASK 0x800UL /**< Bit mask for ADC_SCANUF */ #define _ADC_IEN_SCANUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */ #define ADC_IEN_SCANUF_DEFAULT (_ADC_IEN_SCANUF_DEFAULT << 11) /**< Shifted mode DEFAULT for ADC_IEN */ #define ADC_IEN_SINGLECMP (0x1UL << 16) /**< SINGLECMP Interrupt Enable */ #define _ADC_IEN_SINGLECMP_SHIFT 16 /**< Shift value for ADC_SINGLECMP */ #define _ADC_IEN_SINGLECMP_MASK 0x10000UL /**< Bit mask for ADC_SINGLECMP */ #define _ADC_IEN_SINGLECMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */ #define ADC_IEN_SINGLECMP_DEFAULT (_ADC_IEN_SINGLECMP_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_IEN */ #define ADC_IEN_SCANCMP (0x1UL << 17) /**< SCANCMP Interrupt Enable */ #define _ADC_IEN_SCANCMP_SHIFT 17 /**< Shift value for ADC_SCANCMP */ #define _ADC_IEN_SCANCMP_MASK 0x20000UL /**< Bit mask for ADC_SCANCMP */ #define _ADC_IEN_SCANCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */ #define ADC_IEN_SCANCMP_DEFAULT (_ADC_IEN_SCANCMP_DEFAULT << 17) /**< Shifted mode DEFAULT for ADC_IEN */ #define ADC_IEN_VREFOV (0x1UL << 24) /**< VREFOV Interrupt Enable */ #define _ADC_IEN_VREFOV_SHIFT 24 /**< Shift value for ADC_VREFOV */ #define _ADC_IEN_VREFOV_MASK 0x1000000UL /**< Bit mask for ADC_VREFOV */ #define _ADC_IEN_VREFOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */ #define ADC_IEN_VREFOV_DEFAULT (_ADC_IEN_VREFOV_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_IEN */ #define ADC_IEN_PROGERR (0x1UL << 25) /**< PROGERR Interrupt Enable */ #define _ADC_IEN_PROGERR_SHIFT 25 /**< Shift value for ADC_PROGERR */ #define _ADC_IEN_PROGERR_MASK 0x2000000UL /**< Bit mask for ADC_PROGERR */ #define _ADC_IEN_PROGERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */ #define ADC_IEN_PROGERR_DEFAULT (_ADC_IEN_PROGERR_DEFAULT << 25) /**< Shifted mode DEFAULT for ADC_IEN */ #define ADC_IEN_SCANEXTPEND (0x1UL << 26) /**< SCANEXTPEND Interrupt Enable */ #define _ADC_IEN_SCANEXTPEND_SHIFT 26 /**< Shift value for ADC_SCANEXTPEND */ #define _ADC_IEN_SCANEXTPEND_MASK 0x4000000UL /**< Bit mask for ADC_SCANEXTPEND */ #define _ADC_IEN_SCANEXTPEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */ #define ADC_IEN_SCANEXTPEND_DEFAULT (_ADC_IEN_SCANEXTPEND_DEFAULT << 26) /**< Shifted mode DEFAULT for ADC_IEN */ #define ADC_IEN_SCANPEND (0x1UL << 27) /**< SCANPEND Interrupt Enable */ #define _ADC_IEN_SCANPEND_SHIFT 27 /**< Shift value for ADC_SCANPEND */ #define _ADC_IEN_SCANPEND_MASK 0x8000000UL /**< Bit mask for ADC_SCANPEND */ #define _ADC_IEN_SCANPEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */ #define ADC_IEN_SCANPEND_DEFAULT (_ADC_IEN_SCANPEND_DEFAULT << 27) /**< Shifted mode DEFAULT for ADC_IEN */ #define ADC_IEN_PRSTIMEDERR (0x1UL << 28) /**< PRSTIMEDERR Interrupt Enable */ #define _ADC_IEN_PRSTIMEDERR_SHIFT 28 /**< Shift value for ADC_PRSTIMEDERR */ #define _ADC_IEN_PRSTIMEDERR_MASK 0x10000000UL /**< Bit mask for ADC_PRSTIMEDERR */ #define _ADC_IEN_PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */ #define ADC_IEN_PRSTIMEDERR_DEFAULT (_ADC_IEN_PRSTIMEDERR_DEFAULT << 28) /**< Shifted mode DEFAULT for ADC_IEN */ #define ADC_IEN_EM23ERR (0x1UL << 29) /**< EM23ERR Interrupt Enable */ #define _ADC_IEN_EM23ERR_SHIFT 29 /**< Shift value for ADC_EM23ERR */ #define _ADC_IEN_EM23ERR_MASK 0x20000000UL /**< Bit mask for ADC_EM23ERR */ #define _ADC_IEN_EM23ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */ #define ADC_IEN_EM23ERR_DEFAULT (_ADC_IEN_EM23ERR_DEFAULT << 29) /**< Shifted mode DEFAULT for ADC_IEN */ /* Bit fields for ADC SINGLEDATA */ #define _ADC_SINGLEDATA_RESETVALUE 0x00000000UL /**< Default value for ADC_SINGLEDATA */ #define _ADC_SINGLEDATA_MASK 0xFFFFFFFFUL /**< Mask for ADC_SINGLEDATA */ #define _ADC_SINGLEDATA_DATA_SHIFT 0 /**< Shift value for ADC_DATA */ #define _ADC_SINGLEDATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for ADC_DATA */ #define _ADC_SINGLEDATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLEDATA */ #define ADC_SINGLEDATA_DATA_DEFAULT (_ADC_SINGLEDATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SINGLEDATA */ /* Bit fields for ADC SCANDATA */ #define _ADC_SCANDATA_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANDATA */ #define _ADC_SCANDATA_MASK 0xFFFFFFFFUL /**< Mask for ADC_SCANDATA */ #define _ADC_SCANDATA_DATA_SHIFT 0 /**< Shift value for ADC_DATA */ #define _ADC_SCANDATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for ADC_DATA */ #define _ADC_SCANDATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANDATA */ #define ADC_SCANDATA_DATA_DEFAULT (_ADC_SCANDATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANDATA */ /* Bit fields for ADC SINGLEDATAP */ #define _ADC_SINGLEDATAP_RESETVALUE 0x00000000UL /**< Default value for ADC_SINGLEDATAP */ #define _ADC_SINGLEDATAP_MASK 0xFFFFFFFFUL /**< Mask for ADC_SINGLEDATAP */ #define _ADC_SINGLEDATAP_DATAP_SHIFT 0 /**< Shift value for ADC_DATAP */ #define _ADC_SINGLEDATAP_DATAP_MASK 0xFFFFFFFFUL /**< Bit mask for ADC_DATAP */ #define _ADC_SINGLEDATAP_DATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLEDATAP */ #define ADC_SINGLEDATAP_DATAP_DEFAULT (_ADC_SINGLEDATAP_DATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SINGLEDATAP */ /* Bit fields for ADC SCANDATAP */ #define _ADC_SCANDATAP_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANDATAP */ #define _ADC_SCANDATAP_MASK 0xFFFFFFFFUL /**< Mask for ADC_SCANDATAP */ #define _ADC_SCANDATAP_DATAP_SHIFT 0 /**< Shift value for ADC_DATAP */ #define _ADC_SCANDATAP_DATAP_MASK 0xFFFFFFFFUL /**< Bit mask for ADC_DATAP */ #define _ADC_SCANDATAP_DATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANDATAP */ #define ADC_SCANDATAP_DATAP_DEFAULT (_ADC_SCANDATAP_DATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANDATAP */ /* Bit fields for ADC SCANDATAX */ #define _ADC_SCANDATAX_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANDATAX */ #define _ADC_SCANDATAX_MASK 0x001FFFFFUL /**< Mask for ADC_SCANDATAX */ #define _ADC_SCANDATAX_DATA_SHIFT 0 /**< Shift value for ADC_DATA */ #define _ADC_SCANDATAX_DATA_MASK 0xFFFFUL /**< Bit mask for ADC_DATA */ #define _ADC_SCANDATAX_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANDATAX */ #define ADC_SCANDATAX_DATA_DEFAULT (_ADC_SCANDATAX_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANDATAX */ #define _ADC_SCANDATAX_SCANINPUTID_SHIFT 16 /**< Shift value for ADC_SCANINPUTID */ #define _ADC_SCANDATAX_SCANINPUTID_MASK 0x1F0000UL /**< Bit mask for ADC_SCANINPUTID */ #define _ADC_SCANDATAX_SCANINPUTID_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANDATAX */ #define ADC_SCANDATAX_SCANINPUTID_DEFAULT (_ADC_SCANDATAX_SCANINPUTID_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_SCANDATAX */ /* Bit fields for ADC SCANDATAXP */ #define _ADC_SCANDATAXP_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANDATAXP */ #define _ADC_SCANDATAXP_MASK 0x001FFFFFUL /**< Mask for ADC_SCANDATAXP */ #define _ADC_SCANDATAXP_DATAP_SHIFT 0 /**< Shift value for ADC_DATAP */ #define _ADC_SCANDATAXP_DATAP_MASK 0xFFFFUL /**< Bit mask for ADC_DATAP */ #define _ADC_SCANDATAXP_DATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANDATAXP */ #define ADC_SCANDATAXP_DATAP_DEFAULT (_ADC_SCANDATAXP_DATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANDATAXP */ #define _ADC_SCANDATAXP_SCANINPUTIDPEEK_SHIFT 16 /**< Shift value for ADC_SCANINPUTIDPEEK */ #define _ADC_SCANDATAXP_SCANINPUTIDPEEK_MASK 0x1F0000UL /**< Bit mask for ADC_SCANINPUTIDPEEK */ #define _ADC_SCANDATAXP_SCANINPUTIDPEEK_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANDATAXP */ #define ADC_SCANDATAXP_SCANINPUTIDPEEK_DEFAULT (_ADC_SCANDATAXP_SCANINPUTIDPEEK_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_SCANDATAXP */ /* Bit fields for ADC APORTREQ */ #define _ADC_APORTREQ_RESETVALUE 0x00000000UL /**< Default value for ADC_APORTREQ */ #define _ADC_APORTREQ_MASK 0x000003FFUL /**< Mask for ADC_APORTREQ */ #define ADC_APORTREQ_APORT0XREQ (0x1UL << 0) /**< 1 If the Bus Connected to APORT0X is Requested */ #define _ADC_APORTREQ_APORT0XREQ_SHIFT 0 /**< Shift value for ADC_APORT0XREQ */ #define _ADC_APORTREQ_APORT0XREQ_MASK 0x1UL /**< Bit mask for ADC_APORT0XREQ */ #define _ADC_APORTREQ_APORT0XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */ #define ADC_APORTREQ_APORT0XREQ_DEFAULT (_ADC_APORTREQ_APORT0XREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_APORTREQ */ #define ADC_APORTREQ_APORT0YREQ (0x1UL << 1) /**< 1 If the Bus Connected to APORT0Y is Requested */ #define _ADC_APORTREQ_APORT0YREQ_SHIFT 1 /**< Shift value for ADC_APORT0YREQ */ #define _ADC_APORTREQ_APORT0YREQ_MASK 0x2UL /**< Bit mask for ADC_APORT0YREQ */ #define _ADC_APORTREQ_APORT0YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */ #define ADC_APORTREQ_APORT0YREQ_DEFAULT (_ADC_APORTREQ_APORT0YREQ_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_APORTREQ */ #define ADC_APORTREQ_APORT1XREQ (0x1UL << 2) /**< 1 If the Bus Connected to APORT1X is Requested */ #define _ADC_APORTREQ_APORT1XREQ_SHIFT 2 /**< Shift value for ADC_APORT1XREQ */ #define _ADC_APORTREQ_APORT1XREQ_MASK 0x4UL /**< Bit mask for ADC_APORT1XREQ */ #define _ADC_APORTREQ_APORT1XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */ #define ADC_APORTREQ_APORT1XREQ_DEFAULT (_ADC_APORTREQ_APORT1XREQ_DEFAULT << 2) /**< Shifted mode DEFAULT for ADC_APORTREQ */ #define ADC_APORTREQ_APORT1YREQ (0x1UL << 3) /**< 1 If the Bus Connected to APORT1Y is Requested */ #define _ADC_APORTREQ_APORT1YREQ_SHIFT 3 /**< Shift value for ADC_APORT1YREQ */ #define _ADC_APORTREQ_APORT1YREQ_MASK 0x8UL /**< Bit mask for ADC_APORT1YREQ */ #define _ADC_APORTREQ_APORT1YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */ #define ADC_APORTREQ_APORT1YREQ_DEFAULT (_ADC_APORTREQ_APORT1YREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for ADC_APORTREQ */ #define ADC_APORTREQ_APORT2XREQ (0x1UL << 4) /**< 1 If the Bus Connected to APORT2X is Requested */ #define _ADC_APORTREQ_APORT2XREQ_SHIFT 4 /**< Shift value for ADC_APORT2XREQ */ #define _ADC_APORTREQ_APORT2XREQ_MASK 0x10UL /**< Bit mask for ADC_APORT2XREQ */ #define _ADC_APORTREQ_APORT2XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */ #define ADC_APORTREQ_APORT2XREQ_DEFAULT (_ADC_APORTREQ_APORT2XREQ_DEFAULT << 4) /**< Shifted mode DEFAULT for ADC_APORTREQ */ #define ADC_APORTREQ_APORT2YREQ (0x1UL << 5) /**< 1 If the Bus Connected to APORT2Y is Requested */ #define _ADC_APORTREQ_APORT2YREQ_SHIFT 5 /**< Shift value for ADC_APORT2YREQ */ #define _ADC_APORTREQ_APORT2YREQ_MASK 0x20UL /**< Bit mask for ADC_APORT2YREQ */ #define _ADC_APORTREQ_APORT2YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */ #define ADC_APORTREQ_APORT2YREQ_DEFAULT (_ADC_APORTREQ_APORT2YREQ_DEFAULT << 5) /**< Shifted mode DEFAULT for ADC_APORTREQ */ #define ADC_APORTREQ_APORT3XREQ (0x1UL << 6) /**< 1 If the Bus Connected to APORT3X is Requested */ #define _ADC_APORTREQ_APORT3XREQ_SHIFT 6 /**< Shift value for ADC_APORT3XREQ */ #define _ADC_APORTREQ_APORT3XREQ_MASK 0x40UL /**< Bit mask for ADC_APORT3XREQ */ #define _ADC_APORTREQ_APORT3XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */ #define ADC_APORTREQ_APORT3XREQ_DEFAULT (_ADC_APORTREQ_APORT3XREQ_DEFAULT << 6) /**< Shifted mode DEFAULT for ADC_APORTREQ */ #define ADC_APORTREQ_APORT3YREQ (0x1UL << 7) /**< 1 If the Bus Connected to APORT3Y is Requested */ #define _ADC_APORTREQ_APORT3YREQ_SHIFT 7 /**< Shift value for ADC_APORT3YREQ */ #define _ADC_APORTREQ_APORT3YREQ_MASK 0x80UL /**< Bit mask for ADC_APORT3YREQ */ #define _ADC_APORTREQ_APORT3YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */ #define ADC_APORTREQ_APORT3YREQ_DEFAULT (_ADC_APORTREQ_APORT3YREQ_DEFAULT << 7) /**< Shifted mode DEFAULT for ADC_APORTREQ */ #define ADC_APORTREQ_APORT4XREQ (0x1UL << 8) /**< 1 If the Bus Connected to APORT4X is Requested */ #define _ADC_APORTREQ_APORT4XREQ_SHIFT 8 /**< Shift value for ADC_APORT4XREQ */ #define _ADC_APORTREQ_APORT4XREQ_MASK 0x100UL /**< Bit mask for ADC_APORT4XREQ */ #define _ADC_APORTREQ_APORT4XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */ #define ADC_APORTREQ_APORT4XREQ_DEFAULT (_ADC_APORTREQ_APORT4XREQ_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_APORTREQ */ #define ADC_APORTREQ_APORT4YREQ (0x1UL << 9) /**< 1 If the Bus Connected to APORT4Y is Requested */ #define _ADC_APORTREQ_APORT4YREQ_SHIFT 9 /**< Shift value for ADC_APORT4YREQ */ #define _ADC_APORTREQ_APORT4YREQ_MASK 0x200UL /**< Bit mask for ADC_APORT4YREQ */ #define _ADC_APORTREQ_APORT4YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */ #define ADC_APORTREQ_APORT4YREQ_DEFAULT (_ADC_APORTREQ_APORT4YREQ_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_APORTREQ */ /* Bit fields for ADC APORTCONFLICT */ #define _ADC_APORTCONFLICT_RESETVALUE 0x00000000UL /**< Default value for ADC_APORTCONFLICT */ #define _ADC_APORTCONFLICT_MASK 0x000003FFUL /**< Mask for ADC_APORTCONFLICT */ #define ADC_APORTCONFLICT_APORT0XCONFLICT (0x1UL << 0) /**< 1 If the Bus Connected to APORT0X is in Conflict With Another Peripheral */ #define _ADC_APORTCONFLICT_APORT0XCONFLICT_SHIFT 0 /**< Shift value for ADC_APORT0XCONFLICT */ #define _ADC_APORTCONFLICT_APORT0XCONFLICT_MASK 0x1UL /**< Bit mask for ADC_APORT0XCONFLICT */ #define _ADC_APORTCONFLICT_APORT0XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */ #define ADC_APORTCONFLICT_APORT0XCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT0XCONFLICT_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */ #define ADC_APORTCONFLICT_APORT0YCONFLICT (0x1UL << 1) /**< 1 If the Bus Connected to APORT0Y is in Conflict With Another Peripheral */ #define _ADC_APORTCONFLICT_APORT0YCONFLICT_SHIFT 1 /**< Shift value for ADC_APORT0YCONFLICT */ #define _ADC_APORTCONFLICT_APORT0YCONFLICT_MASK 0x2UL /**< Bit mask for ADC_APORT0YCONFLICT */ #define _ADC_APORTCONFLICT_APORT0YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */ #define ADC_APORTCONFLICT_APORT0YCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT0YCONFLICT_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */ #define ADC_APORTCONFLICT_APORT1XCONFLICT (0x1UL << 2) /**< 1 If the Bus Connected to APORT1X is in Conflict With Another Peripheral */ #define _ADC_APORTCONFLICT_APORT1XCONFLICT_SHIFT 2 /**< Shift value for ADC_APORT1XCONFLICT */ #define _ADC_APORTCONFLICT_APORT1XCONFLICT_MASK 0x4UL /**< Bit mask for ADC_APORT1XCONFLICT */ #define _ADC_APORTCONFLICT_APORT1XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */ #define ADC_APORTCONFLICT_APORT1XCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT1XCONFLICT_DEFAULT << 2) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */ #define ADC_APORTCONFLICT_APORT1YCONFLICT (0x1UL << 3) /**< 1 If the Bus Connected to APORT1Y is in Conflict With Another Peripheral */ #define _ADC_APORTCONFLICT_APORT1YCONFLICT_SHIFT 3 /**< Shift value for ADC_APORT1YCONFLICT */ #define _ADC_APORTCONFLICT_APORT1YCONFLICT_MASK 0x8UL /**< Bit mask for ADC_APORT1YCONFLICT */ #define _ADC_APORTCONFLICT_APORT1YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */ #define ADC_APORTCONFLICT_APORT1YCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT1YCONFLICT_DEFAULT << 3) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */ #define ADC_APORTCONFLICT_APORT2XCONFLICT (0x1UL << 4) /**< 1 If the Bus Connected to APORT2X is in Conflict With Another Peripheral */ #define _ADC_APORTCONFLICT_APORT2XCONFLICT_SHIFT 4 /**< Shift value for ADC_APORT2XCONFLICT */ #define _ADC_APORTCONFLICT_APORT2XCONFLICT_MASK 0x10UL /**< Bit mask for ADC_APORT2XCONFLICT */ #define _ADC_APORTCONFLICT_APORT2XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */ #define ADC_APORTCONFLICT_APORT2XCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT2XCONFLICT_DEFAULT << 4) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */ #define ADC_APORTCONFLICT_APORT2YCONFLICT (0x1UL << 5) /**< 1 If the Bus Connected to APORT2Y is in Conflict With Another Peripheral */ #define _ADC_APORTCONFLICT_APORT2YCONFLICT_SHIFT 5 /**< Shift value for ADC_APORT2YCONFLICT */ #define _ADC_APORTCONFLICT_APORT2YCONFLICT_MASK 0x20UL /**< Bit mask for ADC_APORT2YCONFLICT */ #define _ADC_APORTCONFLICT_APORT2YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */ #define ADC_APORTCONFLICT_APORT2YCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT2YCONFLICT_DEFAULT << 5) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */ #define ADC_APORTCONFLICT_APORT3XCONFLICT (0x1UL << 6) /**< 1 If the Bus Connected to APORT3X is in Conflict With Another Peripheral */ #define _ADC_APORTCONFLICT_APORT3XCONFLICT_SHIFT 6 /**< Shift value for ADC_APORT3XCONFLICT */ #define _ADC_APORTCONFLICT_APORT3XCONFLICT_MASK 0x40UL /**< Bit mask for ADC_APORT3XCONFLICT */ #define _ADC_APORTCONFLICT_APORT3XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */ #define ADC_APORTCONFLICT_APORT3XCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT3XCONFLICT_DEFAULT << 6) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */ #define ADC_APORTCONFLICT_APORT3YCONFLICT (0x1UL << 7) /**< 1 If the Bus Connected to APORT3Y is in Conflict With Another Peripheral */ #define _ADC_APORTCONFLICT_APORT3YCONFLICT_SHIFT 7 /**< Shift value for ADC_APORT3YCONFLICT */ #define _ADC_APORTCONFLICT_APORT3YCONFLICT_MASK 0x80UL /**< Bit mask for ADC_APORT3YCONFLICT */ #define _ADC_APORTCONFLICT_APORT3YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */ #define ADC_APORTCONFLICT_APORT3YCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT3YCONFLICT_DEFAULT << 7) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */ #define ADC_APORTCONFLICT_APORT4XCONFLICT (0x1UL << 8) /**< 1 If the Bus Connected to APORT4X is in Conflict With Another Peripheral */ #define _ADC_APORTCONFLICT_APORT4XCONFLICT_SHIFT 8 /**< Shift value for ADC_APORT4XCONFLICT */ #define _ADC_APORTCONFLICT_APORT4XCONFLICT_MASK 0x100UL /**< Bit mask for ADC_APORT4XCONFLICT */ #define _ADC_APORTCONFLICT_APORT4XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */ #define ADC_APORTCONFLICT_APORT4XCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT4XCONFLICT_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */ #define ADC_APORTCONFLICT_APORT4YCONFLICT (0x1UL << 9) /**< 1 If the Bus Connected to APORT4Y is in Conflict With Another Peripheral */ #define _ADC_APORTCONFLICT_APORT4YCONFLICT_SHIFT 9 /**< Shift value for ADC_APORT4YCONFLICT */ #define _ADC_APORTCONFLICT_APORT4YCONFLICT_MASK 0x200UL /**< Bit mask for ADC_APORT4YCONFLICT */ #define _ADC_APORTCONFLICT_APORT4YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */ #define ADC_APORTCONFLICT_APORT4YCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT4YCONFLICT_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */ /* Bit fields for ADC SINGLEFIFOCOUNT */ #define _ADC_SINGLEFIFOCOUNT_RESETVALUE 0x00000000UL /**< Default value for ADC_SINGLEFIFOCOUNT */ #define _ADC_SINGLEFIFOCOUNT_MASK 0x00000007UL /**< Mask for ADC_SINGLEFIFOCOUNT */ #define _ADC_SINGLEFIFOCOUNT_SINGLEDC_SHIFT 0 /**< Shift value for ADC_SINGLEDC */ #define _ADC_SINGLEFIFOCOUNT_SINGLEDC_MASK 0x7UL /**< Bit mask for ADC_SINGLEDC */ #define _ADC_SINGLEFIFOCOUNT_SINGLEDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLEFIFOCOUNT */ #define ADC_SINGLEFIFOCOUNT_SINGLEDC_DEFAULT (_ADC_SINGLEFIFOCOUNT_SINGLEDC_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SINGLEFIFOCOUNT */ /* Bit fields for ADC SCANFIFOCOUNT */ #define _ADC_SCANFIFOCOUNT_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANFIFOCOUNT */ #define _ADC_SCANFIFOCOUNT_MASK 0x00000007UL /**< Mask for ADC_SCANFIFOCOUNT */ #define _ADC_SCANFIFOCOUNT_SCANDC_SHIFT 0 /**< Shift value for ADC_SCANDC */ #define _ADC_SCANFIFOCOUNT_SCANDC_MASK 0x7UL /**< Bit mask for ADC_SCANDC */ #define _ADC_SCANFIFOCOUNT_SCANDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANFIFOCOUNT */ #define ADC_SCANFIFOCOUNT_SCANDC_DEFAULT (_ADC_SCANFIFOCOUNT_SCANDC_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANFIFOCOUNT */ /* Bit fields for ADC SINGLEFIFOCLEAR */ #define _ADC_SINGLEFIFOCLEAR_RESETVALUE 0x00000000UL /**< Default value for ADC_SINGLEFIFOCLEAR */ #define _ADC_SINGLEFIFOCLEAR_MASK 0x00000001UL /**< Mask for ADC_SINGLEFIFOCLEAR */ #define ADC_SINGLEFIFOCLEAR_SINGLEFIFOCLEAR (0x1UL << 0) /**< Clear Single FIFO Content */ #define _ADC_SINGLEFIFOCLEAR_SINGLEFIFOCLEAR_SHIFT 0 /**< Shift value for ADC_SINGLEFIFOCLEAR */ #define _ADC_SINGLEFIFOCLEAR_SINGLEFIFOCLEAR_MASK 0x1UL /**< Bit mask for ADC_SINGLEFIFOCLEAR */ #define _ADC_SINGLEFIFOCLEAR_SINGLEFIFOCLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLEFIFOCLEAR */ #define ADC_SINGLEFIFOCLEAR_SINGLEFIFOCLEAR_DEFAULT (_ADC_SINGLEFIFOCLEAR_SINGLEFIFOCLEAR_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SINGLEFIFOCLEAR */ /* Bit fields for ADC SCANFIFOCLEAR */ #define _ADC_SCANFIFOCLEAR_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANFIFOCLEAR */ #define _ADC_SCANFIFOCLEAR_MASK 0x00000001UL /**< Mask for ADC_SCANFIFOCLEAR */ #define ADC_SCANFIFOCLEAR_SCANFIFOCLEAR (0x1UL << 0) /**< Clear Scan FIFO Content */ #define _ADC_SCANFIFOCLEAR_SCANFIFOCLEAR_SHIFT 0 /**< Shift value for ADC_SCANFIFOCLEAR */ #define _ADC_SCANFIFOCLEAR_SCANFIFOCLEAR_MASK 0x1UL /**< Bit mask for ADC_SCANFIFOCLEAR */ #define _ADC_SCANFIFOCLEAR_SCANFIFOCLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANFIFOCLEAR */ #define ADC_SCANFIFOCLEAR_SCANFIFOCLEAR_DEFAULT (_ADC_SCANFIFOCLEAR_SCANFIFOCLEAR_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANFIFOCLEAR */ /* Bit fields for ADC APORTMASTERDIS */ #define _ADC_APORTMASTERDIS_RESETVALUE 0x00000000UL /**< Default value for ADC_APORTMASTERDIS */ #define _ADC_APORTMASTERDIS_MASK 0x000003FCUL /**< Mask for ADC_APORTMASTERDIS */ #define ADC_APORTMASTERDIS_APORT1XMASTERDIS (0x1UL << 2) /**< APORT1X Master Disable */ #define _ADC_APORTMASTERDIS_APORT1XMASTERDIS_SHIFT 2 /**< Shift value for ADC_APORT1XMASTERDIS */ #define _ADC_APORTMASTERDIS_APORT1XMASTERDIS_MASK 0x4UL /**< Bit mask for ADC_APORT1XMASTERDIS */ #define _ADC_APORTMASTERDIS_APORT1XMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTMASTERDIS */ #define ADC_APORTMASTERDIS_APORT1XMASTERDIS_DEFAULT (_ADC_APORTMASTERDIS_APORT1XMASTERDIS_DEFAULT << 2) /**< Shifted mode DEFAULT for ADC_APORTMASTERDIS */ #define ADC_APORTMASTERDIS_APORT1YMASTERDIS (0x1UL << 3) /**< APORT1Y Master Disable */ #define _ADC_APORTMASTERDIS_APORT1YMASTERDIS_SHIFT 3 /**< Shift value for ADC_APORT1YMASTERDIS */ #define _ADC_APORTMASTERDIS_APORT1YMASTERDIS_MASK 0x8UL /**< Bit mask for ADC_APORT1YMASTERDIS */ #define _ADC_APORTMASTERDIS_APORT1YMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTMASTERDIS */ #define ADC_APORTMASTERDIS_APORT1YMASTERDIS_DEFAULT (_ADC_APORTMASTERDIS_APORT1YMASTERDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for ADC_APORTMASTERDIS */ #define ADC_APORTMASTERDIS_APORT2XMASTERDIS (0x1UL << 4) /**< APORT2X Master Disable */ #define _ADC_APORTMASTERDIS_APORT2XMASTERDIS_SHIFT 4 /**< Shift value for ADC_APORT2XMASTERDIS */ #define _ADC_APORTMASTERDIS_APORT2XMASTERDIS_MASK 0x10UL /**< Bit mask for ADC_APORT2XMASTERDIS */ #define _ADC_APORTMASTERDIS_APORT2XMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTMASTERDIS */ #define ADC_APORTMASTERDIS_APORT2XMASTERDIS_DEFAULT (_ADC_APORTMASTERDIS_APORT2XMASTERDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for ADC_APORTMASTERDIS */ #define ADC_APORTMASTERDIS_APORT2YMASTERDIS (0x1UL << 5) /**< APORT2Y Master Disable */ #define _ADC_APORTMASTERDIS_APORT2YMASTERDIS_SHIFT 5 /**< Shift value for ADC_APORT2YMASTERDIS */ #define _ADC_APORTMASTERDIS_APORT2YMASTERDIS_MASK 0x20UL /**< Bit mask for ADC_APORT2YMASTERDIS */ #define _ADC_APORTMASTERDIS_APORT2YMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTMASTERDIS */ #define ADC_APORTMASTERDIS_APORT2YMASTERDIS_DEFAULT (_ADC_APORTMASTERDIS_APORT2YMASTERDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for ADC_APORTMASTERDIS */ #define ADC_APORTMASTERDIS_APORT3XMASTERDIS (0x1UL << 6) /**< APORT3X Master Disable */ #define _ADC_APORTMASTERDIS_APORT3XMASTERDIS_SHIFT 6 /**< Shift value for ADC_APORT3XMASTERDIS */ #define _ADC_APORTMASTERDIS_APORT3XMASTERDIS_MASK 0x40UL /**< Bit mask for ADC_APORT3XMASTERDIS */ #define _ADC_APORTMASTERDIS_APORT3XMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTMASTERDIS */ #define ADC_APORTMASTERDIS_APORT3XMASTERDIS_DEFAULT (_ADC_APORTMASTERDIS_APORT3XMASTERDIS_DEFAULT << 6) /**< Shifted mode DEFAULT for ADC_APORTMASTERDIS */ #define ADC_APORTMASTERDIS_APORT3YMASTERDIS (0x1UL << 7) /**< APORT3Y Master Disable */ #define _ADC_APORTMASTERDIS_APORT3YMASTERDIS_SHIFT 7 /**< Shift value for ADC_APORT3YMASTERDIS */ #define _ADC_APORTMASTERDIS_APORT3YMASTERDIS_MASK 0x80UL /**< Bit mask for ADC_APORT3YMASTERDIS */ #define _ADC_APORTMASTERDIS_APORT3YMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTMASTERDIS */ #define ADC_APORTMASTERDIS_APORT3YMASTERDIS_DEFAULT (_ADC_APORTMASTERDIS_APORT3YMASTERDIS_DEFAULT << 7) /**< Shifted mode DEFAULT for ADC_APORTMASTERDIS */ #define ADC_APORTMASTERDIS_APORT4XMASTERDIS (0x1UL << 8) /**< APORT4X Master Disable */ #define _ADC_APORTMASTERDIS_APORT4XMASTERDIS_SHIFT 8 /**< Shift value for ADC_APORT4XMASTERDIS */ #define _ADC_APORTMASTERDIS_APORT4XMASTERDIS_MASK 0x100UL /**< Bit mask for ADC_APORT4XMASTERDIS */ #define _ADC_APORTMASTERDIS_APORT4XMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTMASTERDIS */ #define ADC_APORTMASTERDIS_APORT4XMASTERDIS_DEFAULT (_ADC_APORTMASTERDIS_APORT4XMASTERDIS_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_APORTMASTERDIS */ #define ADC_APORTMASTERDIS_APORT4YMASTERDIS (0x1UL << 9) /**< APORT4Y Master Disable */ #define _ADC_APORTMASTERDIS_APORT4YMASTERDIS_SHIFT 9 /**< Shift value for ADC_APORT4YMASTERDIS */ #define _ADC_APORTMASTERDIS_APORT4YMASTERDIS_MASK 0x200UL /**< Bit mask for ADC_APORT4YMASTERDIS */ #define _ADC_APORTMASTERDIS_APORT4YMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTMASTERDIS */ #define ADC_APORTMASTERDIS_APORT4YMASTERDIS_DEFAULT (_ADC_APORTMASTERDIS_APORT4YMASTERDIS_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_APORTMASTERDIS */ /** @} */ /** @} End of group EFR32MG12P_ADC */ /** @} End of group Parts */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_af_pins.h.
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/***************************************************************************//** * @file * @brief EFR32MG12P_AF_PINS register and bit field definitions * @version 5.7.0 ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * SPDX-License-Identifier: Zlib * * The licensor of this software is Silicon Laboratories Inc. * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be * appreciated but is not required. * 2. Altered source versions must be plainly marked as such, and must not be * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * ******************************************************************************/ #if defined(__ICCARM__) #pragma system_include /* Treat file as system include file. */ #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang system_header /* Treat file as system include file. */ #endif /***************************************************************************//** * @addtogroup Parts * @{ ******************************************************************************/ /***************************************************************************//** * @addtogroup EFR32MG12P_Alternate_Function Alternate Function * @{ * @defgroup EFR32MG12P_AF_Pins Alternate Function Pins * @{ ******************************************************************************/ #define AF_CMU_CLK0_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 15 : (i) == 2 ? 6 : (i) == 3 ? 11 : (i) == 4 ? 9 : (i) == 5 ? 14 : (i) == 6 ? 2 : (i) == 7 ? 7 : -1) /**< Pin number for AF_CMU_CLK0 location number i */ #define AF_CMU_CLK1_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 14 : (i) == 2 ? 7 : (i) == 3 ? 10 : (i) == 4 ? 10 : (i) == 5 ? 15 : (i) == 6 ? 3 : (i) == 7 ? 6 : -1) /**< Pin number for AF_CMU_CLK1 location number i */ #define AF_CMU_CLKI0_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 7 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 5 : -1) /**< Pin number for AF_CMU_CLKI0 location number i */ #define AF_PRS_CH0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 6 : (i) == 9 ? 7 : (i) == 10 ? 8 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 11 : -1) /**< Pin number for AF_PRS_CH0 location number i */ #define AF_PRS_CH1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 6 : (i) == 6 ? 7 : (i) == 7 ? 0 : -1) /**< Pin number for AF_PRS_CH1 location number i */ #define AF_PRS_CH2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 6 : (i) == 5 ? 7 : (i) == 6 ? 0 : (i) == 7 ? 1 : -1) /**< Pin number for AF_PRS_CH2 location number i */ #define AF_PRS_CH3_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 5 : (i) == 3 ? 6 : (i) == 4 ? 7 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 2 : (i) == 8 ? 9 : (i) == 9 ? 10 : (i) == 10 ? 11 : (i) == 11 ? 12 : (i) == 12 ? 13 : (i) == 13 ? 14 : (i) == 14 ? 15 : -1) /**< Pin number for AF_PRS_CH3 location number i */ #define AF_PRS_CH4_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 10 : (i) == 2 ? 11 : (i) == 3 ? 12 : (i) == 4 ? 13 : (i) == 5 ? 14 : (i) == 6 ? 15 : -1) /**< Pin number for AF_PRS_CH4 location number i */ #define AF_PRS_CH5_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 11 : (i) == 2 ? 12 : (i) == 3 ? 13 : (i) == 4 ? 14 : (i) == 5 ? 15 : (i) == 6 ? 9 : -1) /**< Pin number for AF_PRS_CH5 location number i */ #define AF_PRS_CH6_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 11 : (i) == 14 ? 12 : (i) == 15 ? 13 : (i) == 16 ? 14 : (i) == 17 ? 15 : -1) /**< Pin number for AF_PRS_CH6 location number i */ #define AF_PRS_CH7_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 0 : -1) /**< Pin number for AF_PRS_CH7 location number i */ #define AF_PRS_CH8_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 11 : (i) == 5 ? 12 : (i) == 6 ? 13 : (i) == 7 ? 14 : (i) == 8 ? 15 : (i) == 9 ? 0 : (i) == 10 ? 1 : -1) /**< Pin number for AF_PRS_CH8 location number i */ #define AF_PRS_CH9_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 5 : (i) == 3 ? 11 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 14 : (i) == 7 ? 15 : (i) == 8 ? 0 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : -1) /**< Pin number for AF_PRS_CH9 location number i */ #define AF_PRS_CH10_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 7 : (i) == 2 ? 8 : (i) == 3 ? 9 : (i) == 4 ? 10 : (i) == 5 ? 11 : -1) /**< Pin number for AF_PRS_CH10 location number i */ #define AF_PRS_CH11_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 8 : (i) == 2 ? 9 : (i) == 3 ? 10 : (i) == 4 ? 11 : (i) == 5 ? 6 : -1) /**< Pin number for AF_PRS_CH11 location number i */ #define AF_TIMER0_CC0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1) /**< Pin number for AF_TIMER0_CC0 location number i */ #define AF_TIMER0_CC1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 9 : (i) == 17 ? 10 : (i) == 18 ? 11 : (i) == 19 ? 12 : (i) == 20 ? 13 : (i) == 21 ? 14 : (i) == 22 ? 15 : (i) == 23 ? 0 : (i) == 24 ? 1 : (i) == 25 ? 2 : (i) == 26 ? 3 : (i) == 27 ? 4 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 0 : -1) /**< Pin number for AF_TIMER0_CC1 location number i */ #define AF_TIMER0_CC2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 11 : (i) == 5 ? 12 : (i) == 6 ? 13 : (i) == 7 ? 14 : (i) == 8 ? 15 : (i) == 9 ? 6 : (i) == 10 ? 7 : (i) == 11 ? 8 : (i) == 12 ? 9 : (i) == 13 ? 10 : (i) == 14 ? 11 : (i) == 15 ? 9 : (i) == 16 ? 10 : (i) == 17 ? 11 : (i) == 18 ? 12 : (i) == 19 ? 13 : (i) == 20 ? 14 : (i) == 21 ? 15 : (i) == 22 ? 0 : (i) == 23 ? 1 : (i) == 24 ? 2 : (i) == 25 ? 3 : (i) == 26 ? 4 : (i) == 27 ? 5 : (i) == 28 ? 6 : (i) == 29 ? 7 : (i) == 30 ? 0 : (i) == 31 ? 1 : -1) /**< Pin number for AF_TIMER0_CC2 location number i */ #define AF_TIMER0_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER0_CC3 location number i */ #define AF_TIMER0_CDTI0_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 5 : (i) == 3 ? 11 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 14 : (i) == 7 ? 15 : (i) == 8 ? 6 : (i) == 9 ? 7 : (i) == 10 ? 8 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 11 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 12 : (i) == 18 ? 13 : (i) == 19 ? 14 : (i) == 20 ? 15 : (i) == 21 ? 0 : (i) == 22 ? 1 : (i) == 23 ? 2 : (i) == 24 ? 3 : (i) == 25 ? 4 : (i) == 26 ? 5 : (i) == 27 ? 6 : (i) == 28 ? 7 : (i) == 29 ? 0 : (i) == 30 ? 1 : (i) == 31 ? 2 : -1) /**< Pin number for AF_TIMER0_CDTI0 location number i */ #define AF_TIMER0_CDTI1_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 11 : (i) == 3 ? 12 : (i) == 4 ? 13 : (i) == 5 ? 14 : (i) == 6 ? 15 : (i) == 7 ? 6 : (i) == 8 ? 7 : (i) == 9 ? 8 : (i) == 10 ? 9 : (i) == 11 ? 10 : (i) == 12 ? 11 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 12 : (i) == 17 ? 13 : (i) == 18 ? 14 : (i) == 19 ? 15 : (i) == 20 ? 0 : (i) == 21 ? 1 : (i) == 22 ? 2 : (i) == 23 ? 3 : (i) == 24 ? 4 : (i) == 25 ? 5 : (i) == 26 ? 6 : (i) == 27 ? 7 : (i) == 28 ? 0 : (i) == 29 ? 1 : (i) == 30 ? 2 : (i) == 31 ? 3 : -1) /**< Pin number for AF_TIMER0_CDTI1 location number i */ #define AF_TIMER0_CDTI2_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 11 : (i) == 2 ? 12 : (i) == 3 ? 13 : (i) == 4 ? 14 : (i) == 5 ? 15 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 8 : (i) == 9 ? 9 : (i) == 10 ? 10 : (i) == 11 ? 11 : (i) == 12 ? 9 : (i) == 13 ? 10 : (i) == 14 ? 11 : (i) == 15 ? 12 : (i) == 16 ? 13 : (i) == 17 ? 14 : (i) == 18 ? 15 : (i) == 19 ? 0 : (i) == 20 ? 1 : (i) == 21 ? 2 : (i) == 22 ? 3 : (i) == 23 ? 4 : (i) == 24 ? 5 : (i) == 25 ? 6 : (i) == 26 ? 7 : (i) == 27 ? 0 : (i) == 28 ? 1 : (i) == 29 ? 2 : (i) == 30 ? 3 : (i) == 31 ? 4 : -1) /**< Pin number for AF_TIMER0_CDTI2 location number i */ #define AF_TIMER0_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER0_CDTI3 location number i */ #define AF_TIMER1_CC0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1) /**< Pin number for AF_TIMER1_CC0 location number i */ #define AF_TIMER1_CC1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 9 : (i) == 17 ? 10 : (i) == 18 ? 11 : (i) == 19 ? 12 : (i) == 20 ? 13 : (i) == 21 ? 14 : (i) == 22 ? 15 : (i) == 23 ? 0 : (i) == 24 ? 1 : (i) == 25 ? 2 : (i) == 26 ? 3 : (i) == 27 ? 4 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 0 : -1) /**< Pin number for AF_TIMER1_CC1 location number i */ #define AF_TIMER1_CC2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 11 : (i) == 5 ? 12 : (i) == 6 ? 13 : (i) == 7 ? 14 : (i) == 8 ? 15 : (i) == 9 ? 6 : (i) == 10 ? 7 : (i) == 11 ? 8 : (i) == 12 ? 9 : (i) == 13 ? 10 : (i) == 14 ? 11 : (i) == 15 ? 9 : (i) == 16 ? 10 : (i) == 17 ? 11 : (i) == 18 ? 12 : (i) == 19 ? 13 : (i) == 20 ? 14 : (i) == 21 ? 15 : (i) == 22 ? 0 : (i) == 23 ? 1 : (i) == 24 ? 2 : (i) == 25 ? 3 : (i) == 26 ? 4 : (i) == 27 ? 5 : (i) == 28 ? 6 : (i) == 29 ? 7 : (i) == 30 ? 0 : (i) == 31 ? 1 : -1) /**< Pin number for AF_TIMER1_CC2 location number i */ #define AF_TIMER1_CC3_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 5 : (i) == 3 ? 11 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 14 : (i) == 7 ? 15 : (i) == 8 ? 6 : (i) == 9 ? 7 : (i) == 10 ? 8 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 11 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 12 : (i) == 18 ? 13 : (i) == 19 ? 14 : (i) == 20 ? 15 : (i) == 21 ? 0 : (i) == 22 ? 1 : (i) == 23 ? 2 : (i) == 24 ? 3 : (i) == 25 ? 4 : (i) == 26 ? 5 : (i) == 27 ? 6 : (i) == 28 ? 7 : (i) == 29 ? 0 : (i) == 30 ? 1 : (i) == 31 ? 2 : -1) /**< Pin number for AF_TIMER1_CC3 location number i */ #define AF_TIMER1_CDTI0_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI0 location number i */ #define AF_TIMER1_CDTI1_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI1 location number i */ #define AF_TIMER1_CDTI2_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI2 location number i */ #define AF_TIMER1_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI3 location number i */ #define AF_WTIMER0_CC0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 8 : (i) == 9 ? 9 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 12 : (i) == 17 ? 13 : (i) == 18 ? 14 : (i) == 19 ? 15 : (i) == 20 ? 0 : (i) == 21 ? 1 : (i) == 22 ? 2 : (i) == 23 ? 3 : (i) == 24 ? 4 : (i) == 25 ? 5 : (i) == 26 ? 6 : (i) == 27 ? 7 : (i) == 28 ? 8 : (i) == 29 ? 9 : (i) == 30 ? 10 : (i) == 31 ? 11 : -1) /**< Pin number for AF_WTIMER0_CC0 location number i */ #define AF_WTIMER0_CC1_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 6 : (i) == 5 ? 7 : (i) == 6 ? 8 : (i) == 7 ? 9 : (i) == 8 ? 6 : (i) == 9 ? 7 : (i) == 10 ? 8 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 11 : (i) == 14 ? 12 : (i) == 15 ? 13 : (i) == 16 ? 14 : (i) == 17 ? 15 : (i) == 18 ? 0 : (i) == 19 ? 1 : (i) == 20 ? 2 : (i) == 21 ? 3 : (i) == 22 ? 4 : (i) == 23 ? 5 : (i) == 24 ? 6 : (i) == 25 ? 7 : (i) == 26 ? 8 : (i) == 27 ? 9 : (i) == 28 ? 10 : (i) == 29 ? 11 : (i) == 30 ? 8 : (i) == 31 ? 9 : -1) /**< Pin number for AF_WTIMER0_CC1 location number i */ #define AF_WTIMER0_CC2_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 8 : (i) == 5 ? 9 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 8 : (i) == 9 ? 9 : (i) == 10 ? 10 : (i) == 11 ? 11 : (i) == 12 ? 12 : (i) == 13 ? 13 : (i) == 14 ? 14 : (i) == 15 ? 15 : (i) == 16 ? 0 : (i) == 17 ? 1 : (i) == 18 ? 2 : (i) == 19 ? 3 : (i) == 20 ? 4 : (i) == 21 ? 5 : (i) == 22 ? 6 : (i) == 23 ? 7 : (i) == 24 ? 8 : (i) == 25 ? 9 : (i) == 26 ? 10 : (i) == 27 ? 11 : (i) == 28 ? 8 : (i) == 29 ? 9 : (i) == 30 ? 10 : (i) == 31 ? 11 : -1) /**< Pin number for AF_WTIMER0_CC2 location number i */ #define AF_WTIMER0_CC3_PIN(i) (-1) /**< Pin number for AF_WTIMER0_CC3 location number i */ #define AF_WTIMER0_CDTI0_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 9 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 8 : (i) == 5 ? 9 : (i) == 6 ? 10 : (i) == 7 ? 11 : (i) == 8 ? 12 : (i) == 9 ? 13 : (i) == 10 ? 14 : (i) == 11 ? 15 : (i) == 12 ? 0 : (i) == 13 ? 1 : (i) == 14 ? 2 : (i) == 15 ? 3 : (i) == 16 ? 4 : (i) == 17 ? 5 : (i) == 18 ? 6 : (i) == 19 ? 7 : (i) == 20 ? 8 : (i) == 21 ? 9 : (i) == 22 ? 10 : (i) == 23 ? 11 : (i) == 24 ? 8 : (i) == 25 ? 9 : (i) == 26 ? 10 : (i) == 27 ? 11 : (i) == 28 ? 12 : (i) == 29 ? 13 : (i) == 30 ? 14 : (i) == 31 ? 15 : -1) /**< Pin number for AF_WTIMER0_CDTI0 location number i */ #define AF_WTIMER0_CDTI1_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 7 : (i) == 2 ? 8 : (i) == 3 ? 9 : (i) == 4 ? 10 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 0 : (i) == 11 ? 1 : (i) == 12 ? 2 : (i) == 13 ? 3 : (i) == 14 ? 4 : (i) == 15 ? 5 : (i) == 16 ? 6 : (i) == 17 ? 7 : (i) == 18 ? 8 : (i) == 19 ? 9 : (i) == 20 ? 10 : (i) == 21 ? 11 : (i) == 22 ? 8 : (i) == 23 ? 9 : (i) == 24 ? 10 : (i) == 25 ? 11 : (i) == 26 ? 12 : (i) == 27 ? 13 : (i) == 28 ? 14 : (i) == 29 ? 15 : (i) == 30 ? 0 : (i) == 31 ? 1 : -1) /**< Pin number for AF_WTIMER0_CDTI1 location number i */ #define AF_WTIMER0_CDTI2_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 9 : (i) == 2 ? 10 : (i) == 3 ? 11 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 14 : (i) == 7 ? 15 : (i) == 8 ? 0 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 3 : (i) == 12 ? 4 : (i) == 13 ? 5 : (i) == 14 ? 6 : (i) == 15 ? 7 : (i) == 16 ? 8 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 8 : (i) == 21 ? 9 : (i) == 22 ? 10 : (i) == 23 ? 11 : (i) == 24 ? 12 : (i) == 25 ? 13 : (i) == 26 ? 14 : (i) == 27 ? 15 : (i) == 28 ? 0 : (i) == 29 ? 1 : (i) == 30 ? 2 : (i) == 31 ? 3 : -1) /**< Pin number for AF_WTIMER0_CDTI2 location number i */ #define AF_WTIMER0_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER0_CDTI3 location number i */ #define AF_WTIMER1_CC0_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 13 : (i) == 2 ? 14 : (i) == 3 ? 15 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 2 : (i) == 7 ? 3 : (i) == 8 ? 4 : (i) == 9 ? 5 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 8 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1) /**< Pin number for AF_WTIMER1_CC0 location number i */ #define AF_WTIMER1_CC1_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 15 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 5 : (i) == 8 ? 6 : (i) == 9 ? 7 : (i) == 10 ? 8 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 11 : (i) == 14 ? 8 : (i) == 15 ? 9 : (i) == 16 ? 10 : (i) == 17 ? 11 : (i) == 18 ? 12 : (i) == 19 ? 13 : (i) == 20 ? 14 : (i) == 21 ? 15 : (i) == 22 ? 0 : (i) == 23 ? 1 : (i) == 24 ? 2 : (i) == 25 ? 3 : (i) == 26 ? 4 : (i) == 27 ? 5 : (i) == 28 ? 6 : (i) == 29 ? 7 : (i) == 30 ? 8 : (i) == 31 ? 9 : -1) /**< Pin number for AF_WTIMER1_CC1 location number i */ #define AF_WTIMER1_CC2_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 8 : (i) == 9 ? 9 : (i) == 10 ? 10 : (i) == 11 ? 11 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 12 : (i) == 17 ? 13 : (i) == 18 ? 14 : (i) == 19 ? 15 : (i) == 20 ? 0 : (i) == 21 ? 1 : (i) == 22 ? 2 : (i) == 23 ? 3 : (i) == 24 ? 4 : (i) == 25 ? 5 : (i) == 26 ? 6 : (i) == 27 ? 7 : (i) == 28 ? 8 : (i) == 29 ? 9 : (i) == 30 ? 10 : (i) == 31 ? 11 : -1) /**< Pin number for AF_WTIMER1_CC2 location number i */ #define AF_WTIMER1_CC3_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 6 : (i) == 5 ? 7 : (i) == 6 ? 8 : (i) == 7 ? 9 : (i) == 8 ? 10 : (i) == 9 ? 11 : (i) == 10 ? 8 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 11 : (i) == 14 ? 12 : (i) == 15 ? 13 : (i) == 16 ? 14 : (i) == 17 ? 15 : (i) == 18 ? 0 : (i) == 19 ? 1 : (i) == 20 ? 2 : (i) == 21 ? 3 : (i) == 22 ? 4 : (i) == 23 ? 5 : (i) == 24 ? 6 : (i) == 25 ? 7 : (i) == 26 ? 8 : (i) == 27 ? 9 : (i) == 28 ? 10 : (i) == 29 ? 11 : (i) == 30 ? 12 : (i) == 31 ? 13 : -1) /**< Pin number for AF_WTIMER1_CC3 location number i */ #define AF_WTIMER1_CDTI0_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI0 location number i */ #define AF_WTIMER1_CDTI1_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI1 location number i */ #define AF_WTIMER1_CDTI2_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI2 location number i */ #define AF_WTIMER1_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI3 location number i */ #define AF_USART0_TX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1) /**< Pin number for AF_USART0_TX location number i */ #define AF_USART0_RX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 9 : (i) == 17 ? 10 : (i) == 18 ? 11 : (i) == 19 ? 12 : (i) == 20 ? 13 : (i) == 21 ? 14 : (i) == 22 ? 15 : (i) == 23 ? 0 : (i) == 24 ? 1 : (i) == 25 ? 2 : (i) == 26 ? 3 : (i) == 27 ? 4 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 0 : -1) /**< Pin number for AF_USART0_RX location number i */ #define AF_USART0_CLK_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 11 : (i) == 5 ? 12 : (i) == 6 ? 13 : (i) == 7 ? 14 : (i) == 8 ? 15 : (i) == 9 ? 6 : (i) == 10 ? 7 : (i) == 11 ? 8 : (i) == 12 ? 9 : (i) == 13 ? 10 : (i) == 14 ? 11 : (i) == 15 ? 9 : (i) == 16 ? 10 : (i) == 17 ? 11 : (i) == 18 ? 12 : (i) == 19 ? 13 : (i) == 20 ? 14 : (i) == 21 ? 15 : (i) == 22 ? 0 : (i) == 23 ? 1 : (i) == 24 ? 2 : (i) == 25 ? 3 : (i) == 26 ? 4 : (i) == 27 ? 5 : (i) == 28 ? 6 : (i) == 29 ? 7 : (i) == 30 ? 0 : (i) == 31 ? 1 : -1) /**< Pin number for AF_USART0_CLK location number i */ #define AF_USART0_CS_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 5 : (i) == 3 ? 11 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 14 : (i) == 7 ? 15 : (i) == 8 ? 6 : (i) == 9 ? 7 : (i) == 10 ? 8 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 11 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 12 : (i) == 18 ? 13 : (i) == 19 ? 14 : (i) == 20 ? 15 : (i) == 21 ? 0 : (i) == 22 ? 1 : (i) == 23 ? 2 : (i) == 24 ? 3 : (i) == 25 ? 4 : (i) == 26 ? 5 : (i) == 27 ? 6 : (i) == 28 ? 7 : (i) == 29 ? 0 : (i) == 30 ? 1 : (i) == 31 ? 2 : -1) /**< Pin number for AF_USART0_CS location number i */ #define AF_USART0_CTS_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 11 : (i) == 3 ? 12 : (i) == 4 ? 13 : (i) == 5 ? 14 : (i) == 6 ? 15 : (i) == 7 ? 6 : (i) == 8 ? 7 : (i) == 9 ? 8 : (i) == 10 ? 9 : (i) == 11 ? 10 : (i) == 12 ? 11 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 12 : (i) == 17 ? 13 : (i) == 18 ? 14 : (i) == 19 ? 15 : (i) == 20 ? 0 : (i) == 21 ? 1 : (i) == 22 ? 2 : (i) == 23 ? 3 : (i) == 24 ? 4 : (i) == 25 ? 5 : (i) == 26 ? 6 : (i) == 27 ? 7 : (i) == 28 ? 0 : (i) == 29 ? 1 : (i) == 30 ? 2 : (i) == 31 ? 3 : -1) /**< Pin number for AF_USART0_CTS location number i */ #define AF_USART0_RTS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 11 : (i) == 2 ? 12 : (i) == 3 ? 13 : (i) == 4 ? 14 : (i) == 5 ? 15 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 8 : (i) == 9 ? 9 : (i) == 10 ? 10 : (i) == 11 ? 11 : (i) == 12 ? 9 : (i) == 13 ? 10 : (i) == 14 ? 11 : (i) == 15 ? 12 : (i) == 16 ? 13 : (i) == 17 ? 14 : (i) == 18 ? 15 : (i) == 19 ? 0 : (i) == 20 ? 1 : (i) == 21 ? 2 : (i) == 22 ? 3 : (i) == 23 ? 4 : (i) == 24 ? 5 : (i) == 25 ? 6 : (i) == 26 ? 7 : (i) == 27 ? 0 : (i) == 28 ? 1 : (i) == 29 ? 2 : (i) == 30 ? 3 : (i) == 31 ? 4 : -1) /**< Pin number for AF_USART0_RTS location number i */ #define AF_USART1_TX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1) /**< Pin number for AF_USART1_TX location number i */ #define AF_USART1_RX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 9 : (i) == 17 ? 10 : (i) == 18 ? 11 : (i) == 19 ? 12 : (i) == 20 ? 13 : (i) == 21 ? 14 : (i) == 22 ? 15 : (i) == 23 ? 0 : (i) == 24 ? 1 : (i) == 25 ? 2 : (i) == 26 ? 3 : (i) == 27 ? 4 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 0 : -1) /**< Pin number for AF_USART1_RX location number i */ #define AF_USART1_CLK_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 11 : (i) == 5 ? 12 : (i) == 6 ? 13 : (i) == 7 ? 14 : (i) == 8 ? 15 : (i) == 9 ? 6 : (i) == 10 ? 7 : (i) == 11 ? 8 : (i) == 12 ? 9 : (i) == 13 ? 10 : (i) == 14 ? 11 : (i) == 15 ? 9 : (i) == 16 ? 10 : (i) == 17 ? 11 : (i) == 18 ? 12 : (i) == 19 ? 13 : (i) == 20 ? 14 : (i) == 21 ? 15 : (i) == 22 ? 0 : (i) == 23 ? 1 : (i) == 24 ? 2 : (i) == 25 ? 3 : (i) == 26 ? 4 : (i) == 27 ? 5 : (i) == 28 ? 6 : (i) == 29 ? 7 : (i) == 30 ? 0 : (i) == 31 ? 1 : -1) /**< Pin number for AF_USART1_CLK location number i */ #define AF_USART1_CS_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 5 : (i) == 3 ? 11 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 14 : (i) == 7 ? 15 : (i) == 8 ? 6 : (i) == 9 ? 7 : (i) == 10 ? 8 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 11 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 12 : (i) == 18 ? 13 : (i) == 19 ? 14 : (i) == 20 ? 15 : (i) == 21 ? 0 : (i) == 22 ? 1 : (i) == 23 ? 2 : (i) == 24 ? 3 : (i) == 25 ? 4 : (i) == 26 ? 5 : (i) == 27 ? 6 : (i) == 28 ? 7 : (i) == 29 ? 0 : (i) == 30 ? 1 : (i) == 31 ? 2 : -1) /**< Pin number for AF_USART1_CS location number i */ #define AF_USART1_CTS_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 11 : (i) == 3 ? 12 : (i) == 4 ? 13 : (i) == 5 ? 14 : (i) == 6 ? 15 : (i) == 7 ? 6 : (i) == 8 ? 7 : (i) == 9 ? 8 : (i) == 10 ? 9 : (i) == 11 ? 10 : (i) == 12 ? 11 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 12 : (i) == 17 ? 13 : (i) == 18 ? 14 : (i) == 19 ? 15 : (i) == 20 ? 0 : (i) == 21 ? 1 : (i) == 22 ? 2 : (i) == 23 ? 3 : (i) == 24 ? 4 : (i) == 25 ? 5 : (i) == 26 ? 6 : (i) == 27 ? 7 : (i) == 28 ? 0 : (i) == 29 ? 1 : (i) == 30 ? 2 : (i) == 31 ? 3 : -1) /**< Pin number for AF_USART1_CTS location number i */ #define AF_USART1_RTS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 11 : (i) == 2 ? 12 : (i) == 3 ? 13 : (i) == 4 ? 14 : (i) == 5 ? 15 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 8 : (i) == 9 ? 9 : (i) == 10 ? 10 : (i) == 11 ? 11 : (i) == 12 ? 9 : (i) == 13 ? 10 : (i) == 14 ? 11 : (i) == 15 ? 12 : (i) == 16 ? 13 : (i) == 17 ? 14 : (i) == 18 ? 15 : (i) == 19 ? 0 : (i) == 20 ? 1 : (i) == 21 ? 2 : (i) == 22 ? 3 : (i) == 23 ? 4 : (i) == 24 ? 5 : (i) == 25 ? 6 : (i) == 26 ? 7 : (i) == 27 ? 0 : (i) == 28 ? 1 : (i) == 29 ? 2 : (i) == 30 ? 3 : (i) == 31 ? 4 : -1) /**< Pin number for AF_USART1_RTS location number i */ #define AF_USART2_TX_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 6 : (i) == 2 ? 7 : (i) == 3 ? 8 : (i) == 4 ? 9 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 2 : (i) == 8 ? 3 : (i) == 9 ? 6 : (i) == 10 ? 7 : (i) == 11 ? 8 : (i) == 12 ? 9 : (i) == 13 ? 10 : (i) == 14 ? 0 : (i) == 15 ? 1 : (i) == 16 ? 3 : (i) == 17 ? 4 : (i) == 18 ? 5 : (i) == 19 ? 6 : (i) == 20 ? 7 : (i) == 21 ? 8 : (i) == 22 ? 9 : (i) == 23 ? 10 : (i) == 24 ? 11 : (i) == 25 ? 12 : (i) == 26 ? 13 : (i) == 27 ? 14 : (i) == 28 ? 15 : (i) == 29 ? 0 : (i) == 30 ? 1 : (i) == 31 ? 2 : -1) /**< Pin number for AF_USART2_TX location number i */ #define AF_USART2_RX_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 7 : (i) == 2 ? 8 : (i) == 3 ? 9 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 2 : (i) == 7 ? 3 : (i) == 8 ? 6 : (i) == 9 ? 7 : (i) == 10 ? 8 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 0 : (i) == 14 ? 1 : (i) == 15 ? 3 : (i) == 16 ? 4 : (i) == 17 ? 5 : (i) == 18 ? 6 : (i) == 19 ? 7 : (i) == 20 ? 8 : (i) == 21 ? 9 : (i) == 22 ? 10 : (i) == 23 ? 11 : (i) == 24 ? 12 : (i) == 25 ? 13 : (i) == 26 ? 14 : (i) == 27 ? 15 : (i) == 28 ? 0 : (i) == 29 ? 1 : (i) == 30 ? 2 : (i) == 31 ? 5 : -1) /**< Pin number for AF_USART2_RX location number i */ #define AF_USART2_CLK_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 8 : (i) == 2 ? 9 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 3 : (i) == 7 ? 6 : (i) == 8 ? 7 : (i) == 9 ? 8 : (i) == 10 ? 9 : (i) == 11 ? 10 : (i) == 12 ? 0 : (i) == 13 ? 1 : (i) == 14 ? 3 : (i) == 15 ? 4 : (i) == 16 ? 5 : (i) == 17 ? 6 : (i) == 18 ? 7 : (i) == 19 ? 8 : (i) == 20 ? 9 : (i) == 21 ? 10 : (i) == 22 ? 11 : (i) == 23 ? 12 : (i) == 24 ? 13 : (i) == 25 ? 14 : (i) == 26 ? 15 : (i) == 27 ? 0 : (i) == 28 ? 1 : (i) == 29 ? 2 : (i) == 30 ? 5 : (i) == 31 ? 6 : -1) /**< Pin number for AF_USART2_CLK location number i */ #define AF_USART2_CS_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 9 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 3 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 8 : (i) == 9 ? 9 : (i) == 10 ? 10 : (i) == 11 ? 0 : (i) == 12 ? 1 : (i) == 13 ? 3 : (i) == 14 ? 4 : (i) == 15 ? 5 : (i) == 16 ? 6 : (i) == 17 ? 7 : (i) == 18 ? 8 : (i) == 19 ? 9 : (i) == 20 ? 10 : (i) == 21 ? 11 : (i) == 22 ? 12 : (i) == 23 ? 13 : (i) == 24 ? 14 : (i) == 25 ? 15 : (i) == 26 ? 0 : (i) == 27 ? 1 : (i) == 28 ? 2 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1) /**< Pin number for AF_USART2_CS location number i */ #define AF_USART2_CTS_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 3 : (i) == 5 ? 6 : (i) == 6 ? 7 : (i) == 7 ? 8 : (i) == 8 ? 9 : (i) == 9 ? 10 : (i) == 10 ? 0 : (i) == 11 ? 1 : (i) == 12 ? 3 : (i) == 13 ? 4 : (i) == 14 ? 5 : (i) == 15 ? 6 : (i) == 16 ? 7 : (i) == 17 ? 8 : (i) == 18 ? 9 : (i) == 19 ? 10 : (i) == 20 ? 11 : (i) == 21 ? 12 : (i) == 22 ? 13 : (i) == 23 ? 14 : (i) == 24 ? 15 : (i) == 25 ? 0 : (i) == 26 ? 1 : (i) == 27 ? 2 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 8 : -1) /**< Pin number for AF_USART2_CTS location number i */ #define AF_USART2_RTS_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 6 : (i) == 5 ? 7 : (i) == 6 ? 8 : (i) == 7 ? 9 : (i) == 8 ? 10 : (i) == 9 ? 0 : (i) == 10 ? 1 : (i) == 11 ? 3 : (i) == 12 ? 4 : (i) == 13 ? 5 : (i) == 14 ? 6 : (i) == 15 ? 7 : (i) == 16 ? 8 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 5 : (i) == 28 ? 6 : (i) == 29 ? 7 : (i) == 30 ? 8 : (i) == 31 ? 9 : -1) /**< Pin number for AF_USART2_RTS location number i */ #define AF_USART3_TX_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 9 : (i) == 2 ? 10 : (i) == 3 ? 11 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 14 : (i) == 7 ? 15 : (i) == 8 ? 2 : (i) == 9 ? 3 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 14 : (i) == 17 ? 15 : (i) == 18 ? 0 : (i) == 19 ? 1 : (i) == 20 ? 2 : (i) == 21 ? 3 : (i) == 22 ? 4 : (i) == 23 ? 5 : (i) == 24 ? 11 : (i) == 25 ? 12 : (i) == 26 ? 13 : (i) == 27 ? 14 : (i) == 28 ? 15 : (i) == 29 ? 0 : (i) == 30 ? 1 : (i) == 31 ? 2 : -1) /**< Pin number for AF_USART3_TX location number i */ #define AF_USART3_RX_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 10 : (i) == 2 ? 11 : (i) == 3 ? 12 : (i) == 4 ? 13 : (i) == 5 ? 14 : (i) == 6 ? 15 : (i) == 7 ? 2 : (i) == 8 ? 3 : (i) == 9 ? 6 : (i) == 10 ? 7 : (i) == 11 ? 8 : (i) == 12 ? 9 : (i) == 13 ? 10 : (i) == 14 ? 11 : (i) == 15 ? 14 : (i) == 16 ? 15 : (i) == 17 ? 0 : (i) == 18 ? 1 : (i) == 19 ? 2 : (i) == 20 ? 3 : (i) == 21 ? 4 : (i) == 22 ? 5 : (i) == 23 ? 11 : (i) == 24 ? 12 : (i) == 25 ? 13 : (i) == 26 ? 14 : (i) == 27 ? 15 : (i) == 28 ? 0 : (i) == 29 ? 1 : (i) == 30 ? 2 : (i) == 31 ? 8 : -1) /**< Pin number for AF_USART3_RX location number i */ #define AF_USART3_CLK_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 11 : (i) == 2 ? 12 : (i) == 3 ? 13 : (i) == 4 ? 14 : (i) == 5 ? 15 : (i) == 6 ? 2 : (i) == 7 ? 3 : (i) == 8 ? 6 : (i) == 9 ? 7 : (i) == 10 ? 8 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 11 : (i) == 14 ? 14 : (i) == 15 ? 15 : (i) == 16 ? 0 : (i) == 17 ? 1 : (i) == 18 ? 2 : (i) == 19 ? 3 : (i) == 20 ? 4 : (i) == 21 ? 5 : (i) == 22 ? 11 : (i) == 23 ? 12 : (i) == 24 ? 13 : (i) == 25 ? 14 : (i) == 26 ? 15 : (i) == 27 ? 0 : (i) == 28 ? 1 : (i) == 29 ? 2 : (i) == 30 ? 8 : (i) == 31 ? 9 : -1) /**< Pin number for AF_USART3_CLK location number i */ #define AF_USART3_CS_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 12 : (i) == 2 ? 13 : (i) == 3 ? 14 : (i) == 4 ? 15 : (i) == 5 ? 2 : (i) == 6 ? 3 : (i) == 7 ? 6 : (i) == 8 ? 7 : (i) == 9 ? 8 : (i) == 10 ? 9 : (i) == 11 ? 10 : (i) == 12 ? 11 : (i) == 13 ? 14 : (i) == 14 ? 15 : (i) == 15 ? 0 : (i) == 16 ? 1 : (i) == 17 ? 2 : (i) == 18 ? 3 : (i) == 19 ? 4 : (i) == 20 ? 5 : (i) == 21 ? 11 : (i) == 22 ? 12 : (i) == 23 ? 13 : (i) == 24 ? 14 : (i) == 25 ? 15 : (i) == 26 ? 0 : (i) == 27 ? 1 : (i) == 28 ? 2 : (i) == 29 ? 8 : (i) == 30 ? 9 : (i) == 31 ? 10 : -1) /**< Pin number for AF_USART3_CS location number i */ #define AF_USART3_CTS_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 13 : (i) == 2 ? 14 : (i) == 3 ? 15 : (i) == 4 ? 2 : (i) == 5 ? 3 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 8 : (i) == 9 ? 9 : (i) == 10 ? 10 : (i) == 11 ? 11 : (i) == 12 ? 14 : (i) == 13 ? 15 : (i) == 14 ? 0 : (i) == 15 ? 1 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 4 : (i) == 19 ? 5 : (i) == 20 ? 11 : (i) == 21 ? 12 : (i) == 22 ? 13 : (i) == 23 ? 14 : (i) == 24 ? 15 : (i) == 25 ? 0 : (i) == 26 ? 1 : (i) == 27 ? 2 : (i) == 28 ? 8 : (i) == 29 ? 9 : (i) == 30 ? 10 : (i) == 31 ? 11 : -1) /**< Pin number for AF_USART3_CTS location number i */ #define AF_USART3_RTS_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 14 : (i) == 2 ? 15 : (i) == 3 ? 2 : (i) == 4 ? 3 : (i) == 5 ? 6 : (i) == 6 ? 7 : (i) == 7 ? 8 : (i) == 8 ? 9 : (i) == 9 ? 10 : (i) == 10 ? 11 : (i) == 11 ? 14 : (i) == 12 ? 15 : (i) == 13 ? 0 : (i) == 14 ? 1 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 4 : (i) == 18 ? 5 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 8 : (i) == 28 ? 9 : (i) == 29 ? 10 : (i) == 30 ? 11 : (i) == 31 ? 12 : -1) /**< Pin number for AF_USART3_RTS location number i */ #define AF_LEUART0_TX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1) /**< Pin number for AF_LEUART0_TX location number i */ #define AF_LEUART0_RX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 9 : (i) == 17 ? 10 : (i) == 18 ? 11 : (i) == 19 ? 12 : (i) == 20 ? 13 : (i) == 21 ? 14 : (i) == 22 ? 15 : (i) == 23 ? 0 : (i) == 24 ? 1 : (i) == 25 ? 2 : (i) == 26 ? 3 : (i) == 27 ? 4 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 0 : -1) /**< Pin number for AF_LEUART0_RX location number i */ #define AF_LETIMER0_OUT0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1) /**< Pin number for AF_LETIMER0_OUT0 location number i */ #define AF_LETIMER0_OUT1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 9 : (i) == 17 ? 10 : (i) == 18 ? 11 : (i) == 19 ? 12 : (i) == 20 ? 13 : (i) == 21 ? 14 : (i) == 22 ? 15 : (i) == 23 ? 0 : (i) == 24 ? 1 : (i) == 25 ? 2 : (i) == 26 ? 3 : (i) == 27 ? 4 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 0 : -1) /**< Pin number for AF_LETIMER0_OUT1 location number i */ #define AF_PCNT0_S0IN_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1) /**< Pin number for AF_PCNT0_S0IN location number i */ #define AF_PCNT0_S1IN_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 9 : (i) == 17 ? 10 : (i) == 18 ? 11 : (i) == 19 ? 12 : (i) == 20 ? 13 : (i) == 21 ? 14 : (i) == 22 ? 15 : (i) == 23 ? 0 : (i) == 24 ? 1 : (i) == 25 ? 2 : (i) == 26 ? 3 : (i) == 27 ? 4 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 0 : -1) /**< Pin number for AF_PCNT0_S1IN location number i */ #define AF_PCNT1_S0IN_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 7 : (i) == 2 ? 8 : (i) == 3 ? 9 : (i) == 4 ? 2 : (i) == 5 ? 3 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 8 : (i) == 9 ? 9 : (i) == 10 ? 10 : (i) == 11 ? 14 : (i) == 12 ? 15 : (i) == 13 ? 0 : (i) == 14 ? 1 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 4 : (i) == 18 ? 5 : (i) == 19 ? 6 : (i) == 20 ? 7 : (i) == 21 ? 8 : (i) == 22 ? 9 : (i) == 23 ? 10 : (i) == 24 ? 11 : (i) == 25 ? 12 : (i) == 26 ? 13 : (i) == 27 ? 14 : (i) == 28 ? 15 : (i) == 29 ? 0 : (i) == 30 ? 1 : (i) == 31 ? 2 : -1) /**< Pin number for AF_PCNT1_S0IN location number i */ #define AF_PCNT1_S1IN_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 8 : (i) == 2 ? 9 : (i) == 3 ? 2 : (i) == 4 ? 3 : (i) == 5 ? 6 : (i) == 6 ? 7 : (i) == 7 ? 8 : (i) == 8 ? 9 : (i) == 9 ? 10 : (i) == 10 ? 14 : (i) == 11 ? 15 : (i) == 12 ? 0 : (i) == 13 ? 1 : (i) == 14 ? 2 : (i) == 15 ? 3 : (i) == 16 ? 4 : (i) == 17 ? 5 : (i) == 18 ? 6 : (i) == 19 ? 7 : (i) == 20 ? 8 : (i) == 21 ? 9 : (i) == 22 ? 10 : (i) == 23 ? 11 : (i) == 24 ? 12 : (i) == 25 ? 13 : (i) == 26 ? 14 : (i) == 27 ? 15 : (i) == 28 ? 0 : (i) == 29 ? 1 : (i) == 30 ? 2 : (i) == 31 ? 6 : -1) /**< Pin number for AF_PCNT1_S1IN location number i */ #define AF_PCNT2_S0IN_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 7 : (i) == 2 ? 8 : (i) == 3 ? 9 : (i) == 4 ? 2 : (i) == 5 ? 3 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 8 : (i) == 9 ? 9 : (i) == 10 ? 10 : (i) == 11 ? 14 : (i) == 12 ? 15 : (i) == 13 ? 0 : (i) == 14 ? 1 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 4 : (i) == 18 ? 5 : (i) == 19 ? 10 : (i) == 20 ? 11 : (i) == 21 ? 8 : (i) == 22 ? 9 : (i) == 23 ? 10 : (i) == 24 ? 11 : (i) == 25 ? 12 : (i) == 26 ? 13 : (i) == 27 ? 14 : (i) == 28 ? 15 : (i) == 29 ? 0 : (i) == 30 ? 1 : (i) == 31 ? 2 : -1) /**< Pin number for AF_PCNT2_S0IN location number i */ #define AF_PCNT2_S1IN_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 8 : (i) == 2 ? 9 : (i) == 3 ? 2 : (i) == 4 ? 3 : (i) == 5 ? 6 : (i) == 6 ? 7 : (i) == 7 ? 8 : (i) == 8 ? 9 : (i) == 9 ? 10 : (i) == 10 ? 14 : (i) == 11 ? 15 : (i) == 12 ? 0 : (i) == 13 ? 1 : (i) == 14 ? 2 : (i) == 15 ? 3 : (i) == 16 ? 4 : (i) == 17 ? 5 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 8 : (i) == 21 ? 9 : (i) == 22 ? 10 : (i) == 23 ? 11 : (i) == 24 ? 12 : (i) == 25 ? 13 : (i) == 26 ? 14 : (i) == 27 ? 15 : (i) == 28 ? 0 : (i) == 29 ? 1 : (i) == 30 ? 2 : (i) == 31 ? 6 : -1) /**< Pin number for AF_PCNT2_S1IN location number i */ #define AF_I2C0_SDA_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1) /**< Pin number for AF_I2C0_SDA location number i */ #define AF_I2C0_SCL_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 9 : (i) == 17 ? 10 : (i) == 18 ? 11 : (i) == 19 ? 12 : (i) == 20 ? 13 : (i) == 21 ? 14 : (i) == 22 ? 15 : (i) == 23 ? 0 : (i) == 24 ? 1 : (i) == 25 ? 2 : (i) == 26 ? 3 : (i) == 27 ? 4 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 0 : -1) /**< Pin number for AF_I2C0_SCL location number i */ #define AF_I2C1_SDA_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 7 : (i) == 2 ? 8 : (i) == 3 ? 9 : (i) == 4 ? 2 : (i) == 5 ? 3 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 8 : (i) == 9 ? 9 : (i) == 10 ? 10 : (i) == 11 ? 14 : (i) == 12 ? 15 : (i) == 13 ? 0 : (i) == 14 ? 1 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 4 : (i) == 18 ? 5 : (i) == 19 ? 10 : (i) == 20 ? 11 : (i) == 21 ? 8 : (i) == 22 ? 9 : (i) == 23 ? 10 : (i) == 24 ? 11 : (i) == 25 ? 12 : (i) == 26 ? 13 : (i) == 27 ? 14 : (i) == 28 ? 15 : (i) == 29 ? 0 : (i) == 30 ? 1 : (i) == 31 ? 2 : -1) /**< Pin number for AF_I2C1_SDA location number i */ #define AF_I2C1_SCL_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 8 : (i) == 2 ? 9 : (i) == 3 ? 2 : (i) == 4 ? 3 : (i) == 5 ? 6 : (i) == 6 ? 7 : (i) == 7 ? 8 : (i) == 8 ? 9 : (i) == 9 ? 10 : (i) == 10 ? 14 : (i) == 11 ? 15 : (i) == 12 ? 0 : (i) == 13 ? 1 : (i) == 14 ? 2 : (i) == 15 ? 3 : (i) == 16 ? 4 : (i) == 17 ? 5 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 8 : (i) == 21 ? 9 : (i) == 22 ? 10 : (i) == 23 ? 11 : (i) == 24 ? 12 : (i) == 25 ? 13 : (i) == 26 ? 14 : (i) == 27 ? 15 : (i) == 28 ? 0 : (i) == 29 ? 1 : (i) == 30 ? 2 : (i) == 31 ? 6 : -1) /**< Pin number for AF_I2C1_SCL location number i */ #define AF_ACMP0_OUT_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1) /**< Pin number for AF_ACMP0_OUT location number i */ #define AF_ACMP1_OUT_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1) /**< Pin number for AF_ACMP1_OUT location number i */ #define AF_LESENSE_CH0_PIN(i) ((i) == 0 ? 8 : -1) /**< Pin number for AF_LESENSE_CH0 location number i */ #define AF_LESENSE_CH1_PIN(i) ((i) == 0 ? 9 : -1) /**< Pin number for AF_LESENSE_CH1 location number i */ #define AF_LESENSE_CH2_PIN(i) ((i) == 0 ? 10 : -1) /**< Pin number for AF_LESENSE_CH2 location number i */ #define AF_LESENSE_CH3_PIN(i) ((i) == 0 ? 11 : -1) /**< Pin number for AF_LESENSE_CH3 location number i */ #define AF_LESENSE_CH4_PIN(i) ((i) == 0 ? 12 : -1) /**< Pin number for AF_LESENSE_CH4 location number i */ #define AF_LESENSE_CH5_PIN(i) ((i) == 0 ? 13 : -1) /**< Pin number for AF_LESENSE_CH5 location number i */ #define AF_LESENSE_CH6_PIN(i) ((i) == 0 ? 14 : -1) /**< Pin number for AF_LESENSE_CH6 location number i */ #define AF_LESENSE_CH7_PIN(i) ((i) == 0 ? 15 : -1) /**< Pin number for AF_LESENSE_CH7 location number i */ #define AF_LESENSE_CH8_PIN(i) ((i) == 0 ? 0 : -1) /**< Pin number for AF_LESENSE_CH8 location number i */ #define AF_LESENSE_CH9_PIN(i) ((i) == 0 ? 1 : -1) /**< Pin number for AF_LESENSE_CH9 location number i */ #define AF_LESENSE_CH10_PIN(i) ((i) == 0 ? 2 : -1) /**< Pin number for AF_LESENSE_CH10 location number i */ #define AF_LESENSE_CH11_PIN(i) ((i) == 0 ? 3 : -1) /**< Pin number for AF_LESENSE_CH11 location number i */ #define AF_LESENSE_CH12_PIN(i) ((i) == 0 ? 4 : -1) /**< Pin number for AF_LESENSE_CH12 location number i */ #define AF_LESENSE_CH13_PIN(i) ((i) == 0 ? 5 : -1) /**< Pin number for AF_LESENSE_CH13 location number i */ #define AF_LESENSE_CH14_PIN(i) ((i) == 0 ? 6 : -1) /**< Pin number for AF_LESENSE_CH14 location number i */ #define AF_LESENSE_CH15_PIN(i) ((i) == 0 ? 7 : -1) /**< Pin number for AF_LESENSE_CH15 location number i */ #define AF_LESENSE_ALTEX0_PIN(i) ((i) == 0 ? 8 : -1) /**< Pin number for AF_LESENSE_ALTEX0 location number i */ #define AF_LESENSE_ALTEX1_PIN(i) ((i) == 0 ? 9 : -1) /**< Pin number for AF_LESENSE_ALTEX1 location number i */ #define AF_LESENSE_ALTEX2_PIN(i) ((i) == 0 ? 14 : -1) /**< Pin number for AF_LESENSE_ALTEX2 location number i */ #define AF_LESENSE_ALTEX3_PIN(i) ((i) == 0 ? 15 : -1) /**< Pin number for AF_LESENSE_ALTEX3 location number i */ #define AF_LESENSE_ALTEX4_PIN(i) ((i) == 0 ? 0 : -1) /**< Pin number for AF_LESENSE_ALTEX4 location number i */ #define AF_LESENSE_ALTEX5_PIN(i) ((i) == 0 ? 1 : -1) /**< Pin number for AF_LESENSE_ALTEX5 location number i */ #define AF_LESENSE_ALTEX6_PIN(i) ((i) == 0 ? 2 : -1) /**< Pin number for AF_LESENSE_ALTEX6 location number i */ #define AF_LESENSE_ALTEX7_PIN(i) ((i) == 0 ? 3 : -1) /**< Pin number for AF_LESENSE_ALTEX7 location number i */ #define AF_DBG_TDI_PIN(i) ((i) == 0 ? 3 : -1) /**< Pin number for AF_DBG_TDI location number i */ #define AF_DBG_TDO_PIN(i) ((i) == 0 ? 2 : -1) /**< Pin number for AF_DBG_TDO location number i */ #define AF_DBG_SWV_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 13 : (i) == 2 ? 15 : (i) == 3 ? 11 : -1) /**< Pin number for AF_DBG_SWV location number i */ #define AF_DBG_SWDIOTMS_PIN(i) ((i) == 0 ? 1 : -1) /**< Pin number for AF_DBG_SWDIOTMS location number i */ #define AF_DBG_SWCLKTCK_PIN(i) ((i) == 0 ? 0 : -1) /**< Pin number for AF_DBG_SWCLKTCK location number i */ #define AF_ETM_TCLK_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 6 : -1) /**< Pin number for AF_ETM_TCLK location number i */ #define AF_ETM_TD0_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 6 : (i) == 2 ? 3 : (i) == 3 ? 7 : -1) /**< Pin number for AF_ETM_TD0 location number i */ #define AF_ETM_TD1_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 7 : (i) == 2 ? 6 : (i) == 3 ? 8 : -1) /**< Pin number for AF_ETM_TD1 location number i */ #define AF_ETM_TD2_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 8 : (i) == 2 ? 7 : (i) == 3 ? 9 : -1) /**< Pin number for AF_ETM_TD2 location number i */ #define AF_ETM_TD3_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 9 : (i) == 2 ? 8 : (i) == 3 ? 10 : -1) /**< Pin number for AF_ETM_TD3 location number i */ /** @} */ /** @} End of group EFR32MG12P_AF_Pins */ /** @} End of group Parts */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_af_ports.h.
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/***************************************************************************//** * @file * @brief EFR32MG12P_AF_PORTS register and bit field definitions * @version 5.7.0 ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * SPDX-License-Identifier: Zlib * * The licensor of this software is Silicon Laboratories Inc. * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be * appreciated but is not required. * 2. Altered source versions must be plainly marked as such, and must not be * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * ******************************************************************************/ #if defined(__ICCARM__) #pragma system_include /* Treat file as system include file. */ #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang system_header /* Treat file as system include file. */ #endif /***************************************************************************//** * @addtogroup Parts * @{ ******************************************************************************/ /***************************************************************************//** * @addtogroup EFR32MG12P_Alternate_Function Alternate Function * @{ * @defgroup EFR32MG12P_AF_Ports Alternate Function Ports * @{ ******************************************************************************/ #define AF_CMU_CLK0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 3 : (i) == 5 ? 3 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_CMU_CLK0 location number i */ #define AF_CMU_CLK1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 3 : (i) == 5 ? 3 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_CMU_CLK1 location number i */ #define AF_CMU_CLKI0_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 0 : -1) /**< Port number for AF_CMU_CLKI0 location number i */ #define AF_PRS_CH0_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 5 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : -1) /**< Port number for AF_PRS_CH0 location number i */ #define AF_PRS_CH1_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_PRS_CH1 location number i */ #define AF_PRS_CH2_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_PRS_CH2 location number i */ #define AF_PRS_CH3_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 5 : (i) == 8 ? 3 : (i) == 9 ? 3 : (i) == 10 ? 3 : (i) == 11 ? 3 : (i) == 12 ? 3 : (i) == 13 ? 3 : (i) == 14 ? 3 : -1) /**< Port number for AF_PRS_CH3 location number i */ #define AF_PRS_CH4_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 3 : (i) == 5 ? 3 : (i) == 6 ? 3 : -1) /**< Port number for AF_PRS_CH4 location number i */ #define AF_PRS_CH5_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 3 : (i) == 5 ? 3 : (i) == 6 ? 3 : -1) /**< Port number for AF_PRS_CH5 location number i */ #define AF_PRS_CH6_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 3 : (i) == 12 ? 3 : (i) == 13 ? 3 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : -1) /**< Port number for AF_PRS_CH6 location number i */ #define AF_PRS_CH7_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 0 : -1) /**< Port number for AF_PRS_CH7 location number i */ #define AF_PRS_CH8_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 0 : (i) == 10 ? 0 : -1) /**< Port number for AF_PRS_CH8 location number i */ #define AF_PRS_CH9_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 0 : (i) == 9 ? 0 : (i) == 10 ? 0 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : -1) /**< Port number for AF_PRS_CH9 location number i */ #define AF_PRS_CH10_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 2 : -1) /**< Port number for AF_PRS_CH10 location number i */ #define AF_PRS_CH11_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 2 : -1) /**< Port number for AF_PRS_CH11 location number i */ #define AF_TIMER0_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) /**< Port number for AF_TIMER0_CC0 location number i */ #define AF_TIMER0_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 0 : -1) /**< Port number for AF_TIMER0_CC1 location number i */ #define AF_TIMER0_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) /**< Port number for AF_TIMER0_CC2 location number i */ #define AF_TIMER0_CC3_PORT(i) (-1) /**< Port number for AF_TIMER0_CC3 location number i */ #define AF_TIMER0_CDTI0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) /**< Port number for AF_TIMER0_CDTI0 location number i */ #define AF_TIMER0_CDTI1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 3 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 0 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) /**< Port number for AF_TIMER0_CDTI1 location number i */ #define AF_TIMER0_CDTI2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 2 : (i) == 7 ? 2 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 3 : (i) == 13 ? 3 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 0 : (i) == 28 ? 0 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) /**< Port number for AF_TIMER0_CDTI2 location number i */ #define AF_TIMER0_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER0_CDTI3 location number i */ #define AF_TIMER1_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) /**< Port number for AF_TIMER1_CC0 location number i */ #define AF_TIMER1_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 0 : -1) /**< Port number for AF_TIMER1_CC1 location number i */ #define AF_TIMER1_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) /**< Port number for AF_TIMER1_CC2 location number i */ #define AF_TIMER1_CC3_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) /**< Port number for AF_TIMER1_CC3 location number i */ #define AF_TIMER1_CDTI0_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI0 location number i */ #define AF_TIMER1_CDTI1_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI1 location number i */ #define AF_TIMER1_CDTI2_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI2 location number i */ #define AF_TIMER1_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI3 location number i */ #define AF_WTIMER0_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 0 : (i) == 7 ? 0 : (i) == 8 ? 0 : (i) == 9 ? 0 : (i) == 10 ? 1 : (i) == 11 ? 1 : (i) == 12 ? 1 : (i) == 13 ? 1 : (i) == 14 ? 1 : (i) == 15 ? 1 : (i) == 16 ? 1 : (i) == 17 ? 1 : (i) == 18 ? 1 : (i) == 19 ? 1 : (i) == 20 ? 2 : (i) == 21 ? 2 : (i) == 22 ? 2 : (i) == 23 ? 2 : (i) == 24 ? 2 : (i) == 25 ? 2 : (i) == 26 ? 2 : (i) == 27 ? 2 : (i) == 28 ? 2 : (i) == 29 ? 2 : (i) == 30 ? 2 : (i) == 31 ? 2 : -1) /**< Port number for AF_WTIMER0_CC0 location number i */ #define AF_WTIMER0_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 0 : (i) == 7 ? 0 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 1 : (i) == 12 ? 1 : (i) == 13 ? 1 : (i) == 14 ? 1 : (i) == 15 ? 1 : (i) == 16 ? 1 : (i) == 17 ? 1 : (i) == 18 ? 2 : (i) == 19 ? 2 : (i) == 20 ? 2 : (i) == 21 ? 2 : (i) == 22 ? 2 : (i) == 23 ? 2 : (i) == 24 ? 2 : (i) == 25 ? 2 : (i) == 26 ? 2 : (i) == 27 ? 2 : (i) == 28 ? 2 : (i) == 29 ? 2 : (i) == 30 ? 3 : (i) == 31 ? 3 : -1) /**< Port number for AF_WTIMER0_CC1 location number i */ #define AF_WTIMER0_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 1 : (i) == 12 ? 1 : (i) == 13 ? 1 : (i) == 14 ? 1 : (i) == 15 ? 1 : (i) == 16 ? 2 : (i) == 17 ? 2 : (i) == 18 ? 2 : (i) == 19 ? 2 : (i) == 20 ? 2 : (i) == 21 ? 2 : (i) == 22 ? 2 : (i) == 23 ? 2 : (i) == 24 ? 2 : (i) == 25 ? 2 : (i) == 26 ? 2 : (i) == 27 ? 2 : (i) == 28 ? 3 : (i) == 29 ? 3 : (i) == 30 ? 3 : (i) == 31 ? 3 : -1) /**< Port number for AF_WTIMER0_CC2 location number i */ #define AF_WTIMER0_CC3_PORT(i) (-1) /**< Port number for AF_WTIMER0_CC3 location number i */ #define AF_WTIMER0_CDTI0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 1 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 2 : (i) == 18 ? 2 : (i) == 19 ? 2 : (i) == 20 ? 2 : (i) == 21 ? 2 : (i) == 22 ? 2 : (i) == 23 ? 2 : (i) == 24 ? 3 : (i) == 25 ? 3 : (i) == 26 ? 3 : (i) == 27 ? 3 : (i) == 28 ? 3 : (i) == 29 ? 3 : (i) == 30 ? 3 : (i) == 31 ? 3 : -1) /**< Port number for AF_WTIMER0_CDTI0 location number i */ #define AF_WTIMER0_CDTI1_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 2 : (i) == 18 ? 2 : (i) == 19 ? 2 : (i) == 20 ? 2 : (i) == 21 ? 2 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 3 : (i) == 25 ? 3 : (i) == 26 ? 3 : (i) == 27 ? 3 : (i) == 28 ? 3 : (i) == 29 ? 3 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) /**< Port number for AF_WTIMER0_CDTI1 location number i */ #define AF_WTIMER0_CDTI2_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 2 : (i) == 18 ? 2 : (i) == 19 ? 2 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 3 : (i) == 25 ? 3 : (i) == 26 ? 3 : (i) == 27 ? 3 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) /**< Port number for AF_WTIMER0_CDTI2 location number i */ #define AF_WTIMER0_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER0_CDTI3 location number i */ #define AF_WTIMER1_CC0_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 2 : (i) == 7 ? 2 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) /**< Port number for AF_WTIMER1_CC0 location number i */ #define AF_WTIMER1_CC1_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 2 : (i) == 7 ? 2 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) /**< Port number for AF_WTIMER1_CC1 location number i */ #define AF_WTIMER1_CC2_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 2 : (i) == 7 ? 2 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 3 : (i) == 13 ? 3 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) /**< Port number for AF_WTIMER1_CC2 location number i */ #define AF_WTIMER1_CC3_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 2 : (i) == 7 ? 2 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 3 : (i) == 11 ? 3 : (i) == 12 ? 3 : (i) == 13 ? 3 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 5 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) /**< Port number for AF_WTIMER1_CC3 location number i */ #define AF_WTIMER1_CDTI0_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI0 location number i */ #define AF_WTIMER1_CDTI1_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI1 location number i */ #define AF_WTIMER1_CDTI2_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI2 location number i */ #define AF_WTIMER1_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI3 location number i */ #define AF_USART0_TX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) /**< Port number for AF_USART0_TX location number i */ #define AF_USART0_RX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 0 : -1) /**< Port number for AF_USART0_RX location number i */ #define AF_USART0_CLK_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) /**< Port number for AF_USART0_CLK location number i */ #define AF_USART0_CS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) /**< Port number for AF_USART0_CS location number i */ #define AF_USART0_CTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 3 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 0 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) /**< Port number for AF_USART0_CTS location number i */ #define AF_USART0_RTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 2 : (i) == 7 ? 2 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 3 : (i) == 13 ? 3 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 0 : (i) == 28 ? 0 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) /**< Port number for AF_USART0_RTS location number i */ #define AF_USART1_TX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) /**< Port number for AF_USART1_TX location number i */ #define AF_USART1_RX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 0 : -1) /**< Port number for AF_USART1_RX location number i */ #define AF_USART1_CLK_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) /**< Port number for AF_USART1_CLK location number i */ #define AF_USART1_CS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) /**< Port number for AF_USART1_CS location number i */ #define AF_USART1_CTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 3 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 0 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) /**< Port number for AF_USART1_CTS location number i */ #define AF_USART1_RTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 2 : (i) == 7 ? 2 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 3 : (i) == 13 ? 3 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 0 : (i) == 28 ? 0 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) /**< Port number for AF_USART1_RTS location number i */ #define AF_USART2_TX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 8 : (i) == 6 ? 8 : (i) == 7 ? 8 : (i) == 8 ? 8 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 1 : (i) == 12 ? 1 : (i) == 13 ? 1 : (i) == 14 ? 5 : (i) == 15 ? 5 : (i) == 16 ? 5 : (i) == 17 ? 5 : (i) == 18 ? 5 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 10 : (i) == 30 ? 10 : (i) == 31 ? 10 : -1) /**< Port number for AF_USART2_TX location number i */ #define AF_USART2_RX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 8 : (i) == 7 ? 8 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 1 : (i) == 12 ? 1 : (i) == 13 ? 5 : (i) == 14 ? 5 : (i) == 15 ? 5 : (i) == 16 ? 5 : (i) == 17 ? 5 : (i) == 18 ? 5 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 10 : (i) == 29 ? 10 : (i) == 30 ? 10 : (i) == 31 ? 0 : -1) /**< Port number for AF_USART2_RX location number i */ #define AF_USART2_CLK_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 8 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 8 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 1 : (i) == 12 ? 5 : (i) == 13 ? 5 : (i) == 14 ? 5 : (i) == 15 ? 5 : (i) == 16 ? 5 : (i) == 17 ? 5 : (i) == 18 ? 5 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 10 : (i) == 28 ? 10 : (i) == 29 ? 10 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) /**< Port number for AF_USART2_CLK location number i */ #define AF_USART2_CS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 5 : (i) == 12 ? 5 : (i) == 13 ? 5 : (i) == 14 ? 5 : (i) == 15 ? 5 : (i) == 16 ? 5 : (i) == 17 ? 5 : (i) == 18 ? 5 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 10 : (i) == 27 ? 10 : (i) == 28 ? 10 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) /**< Port number for AF_USART2_CS location number i */ #define AF_USART2_CTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 8 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 8 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 5 : (i) == 11 ? 5 : (i) == 12 ? 5 : (i) == 13 ? 5 : (i) == 14 ? 5 : (i) == 15 ? 5 : (i) == 16 ? 5 : (i) == 17 ? 5 : (i) == 18 ? 5 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 10 : (i) == 26 ? 10 : (i) == 27 ? 10 : (i) == 28 ? 0 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) /**< Port number for AF_USART2_CTS location number i */ #define AF_USART2_RTS_PORT(i) ((i) == 0 ? 8 : (i) == 1 ? 8 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 5 : (i) == 10 ? 5 : (i) == 11 ? 5 : (i) == 12 ? 5 : (i) == 13 ? 5 : (i) == 14 ? 5 : (i) == 15 ? 5 : (i) == 16 ? 5 : (i) == 17 ? 5 : (i) == 18 ? 5 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 10 : (i) == 25 ? 10 : (i) == 26 ? 10 : (i) == 27 ? 0 : (i) == 28 ? 0 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) /**< Port number for AF_USART2_RTS location number i */ #define AF_USART3_TX_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 3 : (i) == 5 ? 3 : (i) == 6 ? 3 : (i) == 7 ? 3 : (i) == 8 ? 8 : (i) == 9 ? 8 : (i) == 10 ? 1 : (i) == 11 ? 1 : (i) == 12 ? 1 : (i) == 13 ? 1 : (i) == 14 ? 1 : (i) == 15 ? 1 : (i) == 16 ? 9 : (i) == 17 ? 9 : (i) == 18 ? 2 : (i) == 19 ? 2 : (i) == 20 ? 2 : (i) == 21 ? 2 : (i) == 22 ? 2 : (i) == 23 ? 2 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 10 : (i) == 30 ? 10 : (i) == 31 ? 10 : -1) /**< Port number for AF_USART3_TX location number i */ #define AF_USART3_RX_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 3 : (i) == 5 ? 3 : (i) == 6 ? 3 : (i) == 7 ? 8 : (i) == 8 ? 8 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 1 : (i) == 12 ? 1 : (i) == 13 ? 1 : (i) == 14 ? 1 : (i) == 15 ? 9 : (i) == 16 ? 9 : (i) == 17 ? 2 : (i) == 18 ? 2 : (i) == 19 ? 2 : (i) == 20 ? 2 : (i) == 21 ? 2 : (i) == 22 ? 2 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 10 : (i) == 29 ? 10 : (i) == 30 ? 10 : (i) == 31 ? 3 : -1) /**< Port number for AF_USART3_RX location number i */ #define AF_USART3_CLK_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 3 : (i) == 5 ? 3 : (i) == 6 ? 8 : (i) == 7 ? 8 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 1 : (i) == 12 ? 1 : (i) == 13 ? 1 : (i) == 14 ? 9 : (i) == 15 ? 9 : (i) == 16 ? 2 : (i) == 17 ? 2 : (i) == 18 ? 2 : (i) == 19 ? 2 : (i) == 20 ? 2 : (i) == 21 ? 2 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 10 : (i) == 28 ? 10 : (i) == 29 ? 10 : (i) == 30 ? 3 : (i) == 31 ? 3 : -1) /**< Port number for AF_USART3_CLK location number i */ #define AF_USART3_CS_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 3 : (i) == 5 ? 8 : (i) == 6 ? 8 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 1 : (i) == 12 ? 1 : (i) == 13 ? 9 : (i) == 14 ? 9 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 2 : (i) == 18 ? 2 : (i) == 19 ? 2 : (i) == 20 ? 2 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 10 : (i) == 27 ? 10 : (i) == 28 ? 10 : (i) == 29 ? 3 : (i) == 30 ? 3 : (i) == 31 ? 3 : -1) /**< Port number for AF_USART3_CS location number i */ #define AF_USART3_CTS_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 1 : (i) == 12 ? 9 : (i) == 13 ? 9 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 2 : (i) == 18 ? 2 : (i) == 19 ? 2 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 10 : (i) == 26 ? 10 : (i) == 27 ? 10 : (i) == 28 ? 3 : (i) == 29 ? 3 : (i) == 30 ? 3 : (i) == 31 ? 3 : -1) /**< Port number for AF_USART3_CTS location number i */ #define AF_USART3_RTS_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 8 : (i) == 4 ? 8 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 9 : (i) == 12 ? 9 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 2 : (i) == 18 ? 2 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 10 : (i) == 25 ? 10 : (i) == 26 ? 10 : (i) == 27 ? 3 : (i) == 28 ? 3 : (i) == 29 ? 3 : (i) == 30 ? 3 : (i) == 31 ? 3 : -1) /**< Port number for AF_USART3_RTS location number i */ #define AF_LEUART0_TX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) /**< Port number for AF_LEUART0_TX location number i */ #define AF_LEUART0_RX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 0 : -1) /**< Port number for AF_LEUART0_RX location number i */ #define AF_LETIMER0_OUT0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) /**< Port number for AF_LETIMER0_OUT0 location number i */ #define AF_LETIMER0_OUT1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 0 : -1) /**< Port number for AF_LETIMER0_OUT1 location number i */ #define AF_PCNT0_S0IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) /**< Port number for AF_PCNT0_S0IN location number i */ #define AF_PCNT0_S1IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 0 : -1) /**< Port number for AF_PCNT0_S1IN location number i */ #define AF_PCNT1_S0IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 9 : (i) == 12 ? 9 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 2 : (i) == 18 ? 2 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 10 : (i) == 30 ? 10 : (i) == 31 ? 10 : -1) /**< Port number for AF_PCNT1_S0IN location number i */ #define AF_PCNT1_S1IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 8 : (i) == 4 ? 8 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 9 : (i) == 11 ? 9 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 2 : (i) == 18 ? 5 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 10 : (i) == 29 ? 10 : (i) == 30 ? 10 : (i) == 31 ? 0 : -1) /**< Port number for AF_PCNT1_S1IN location number i */ #define AF_PCNT2_S0IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 9 : (i) == 12 ? 9 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 2 : (i) == 18 ? 2 : (i) == 19 ? 2 : (i) == 20 ? 2 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 10 : (i) == 30 ? 10 : (i) == 31 ? 10 : -1) /**< Port number for AF_PCNT2_S0IN location number i */ #define AF_PCNT2_S1IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 8 : (i) == 4 ? 8 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 9 : (i) == 11 ? 9 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 2 : (i) == 18 ? 2 : (i) == 19 ? 2 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 10 : (i) == 29 ? 10 : (i) == 30 ? 10 : (i) == 31 ? 0 : -1) /**< Port number for AF_PCNT2_S1IN location number i */ #define AF_I2C0_SDA_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) /**< Port number for AF_I2C0_SDA location number i */ #define AF_I2C0_SCL_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 0 : -1) /**< Port number for AF_I2C0_SCL location number i */ #define AF_I2C1_SDA_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 9 : (i) == 12 ? 9 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 2 : (i) == 18 ? 2 : (i) == 19 ? 2 : (i) == 20 ? 2 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 10 : (i) == 30 ? 10 : (i) == 31 ? 10 : -1) /**< Port number for AF_I2C1_SDA location number i */ #define AF_I2C1_SCL_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 8 : (i) == 4 ? 8 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 9 : (i) == 11 ? 9 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 2 : (i) == 18 ? 2 : (i) == 19 ? 2 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 10 : (i) == 29 ? 10 : (i) == 30 ? 10 : (i) == 31 ? 0 : -1) /**< Port number for AF_I2C1_SCL location number i */ #define AF_ACMP0_OUT_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) /**< Port number for AF_ACMP0_OUT location number i */ #define AF_ACMP1_OUT_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) /**< Port number for AF_ACMP1_OUT location number i */ #define AF_LESENSE_CH0_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_LESENSE_CH0 location number i */ #define AF_LESENSE_CH1_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_LESENSE_CH1 location number i */ #define AF_LESENSE_CH2_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_LESENSE_CH2 location number i */ #define AF_LESENSE_CH3_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_LESENSE_CH3 location number i */ #define AF_LESENSE_CH4_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_LESENSE_CH4 location number i */ #define AF_LESENSE_CH5_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_LESENSE_CH5 location number i */ #define AF_LESENSE_CH6_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_LESENSE_CH6 location number i */ #define AF_LESENSE_CH7_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_LESENSE_CH7 location number i */ #define AF_LESENSE_CH8_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_CH8 location number i */ #define AF_LESENSE_CH9_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_CH9 location number i */ #define AF_LESENSE_CH10_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_CH10 location number i */ #define AF_LESENSE_CH11_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_CH11 location number i */ #define AF_LESENSE_CH12_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_CH12 location number i */ #define AF_LESENSE_CH13_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_CH13 location number i */ #define AF_LESENSE_CH14_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_CH14 location number i */ #define AF_LESENSE_CH15_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_CH15 location number i */ #define AF_LESENSE_ALTEX0_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_ALTEX0 location number i */ #define AF_LESENSE_ALTEX1_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_ALTEX1 location number i */ #define AF_LESENSE_ALTEX2_PORT(i) ((i) == 0 ? 9 : -1) /**< Port number for AF_LESENSE_ALTEX2 location number i */ #define AF_LESENSE_ALTEX3_PORT(i) ((i) == 0 ? 9 : -1) /**< Port number for AF_LESENSE_ALTEX3 location number i */ #define AF_LESENSE_ALTEX4_PORT(i) ((i) == 0 ? 8 : -1) /**< Port number for AF_LESENSE_ALTEX4 location number i */ #define AF_LESENSE_ALTEX5_PORT(i) ((i) == 0 ? 8 : -1) /**< Port number for AF_LESENSE_ALTEX5 location number i */ #define AF_LESENSE_ALTEX6_PORT(i) ((i) == 0 ? 8 : -1) /**< Port number for AF_LESENSE_ALTEX6 location number i */ #define AF_LESENSE_ALTEX7_PORT(i) ((i) == 0 ? 8 : -1) /**< Port number for AF_LESENSE_ALTEX7 location number i */ #define AF_DBG_TDI_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_TDI location number i */ #define AF_DBG_TDO_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_TDO location number i */ #define AF_DBG_SWV_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 2 : -1) /**< Port number for AF_DBG_SWV location number i */ #define AF_DBG_SWDIOTMS_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_SWDIOTMS location number i */ #define AF_DBG_SWCLKTCK_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_SWCLKTCK location number i */ #define AF_ETM_TCLK_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 8 : (i) == 3 ? 2 : -1) /**< Port number for AF_ETM_TCLK location number i */ #define AF_ETM_TD0_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 8 : (i) == 3 ? 2 : -1) /**< Port number for AF_ETM_TD0 location number i */ #define AF_ETM_TD1_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 2 : -1) /**< Port number for AF_ETM_TD1 location number i */ #define AF_ETM_TD2_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 2 : -1) /**< Port number for AF_ETM_TD2 location number i */ #define AF_ETM_TD3_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 2 : -1) /**< Port number for AF_ETM_TD3 location number i */ /** @} */ /** @} End of group EFR32MG12P_AF_Ports */ /** @} End of group Parts */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_cmu.h.
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/***************************************************************************//** * @file * @brief EFR32MG12P_CMU register and bit field definitions * @version 5.7.0 ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * SPDX-License-Identifier: Zlib * * The licensor of this software is Silicon Laboratories Inc. * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be * appreciated but is not required. * 2. Altered source versions must be plainly marked as such, and must not be * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * ******************************************************************************/ #if defined(__ICCARM__) #pragma system_include /* Treat file as system include file. */ #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang system_header /* Treat file as system include file. */ #endif /***************************************************************************//** * @addtogroup Parts * @{ ******************************************************************************/ /***************************************************************************//** * @defgroup EFR32MG12P_CMU CMU * @{ * @brief EFR32MG12P_CMU Register Declaration ******************************************************************************/ /** CMU Register Declaration */ typedef struct { __IOM uint32_t CTRL; /**< CMU Control Register */ uint32_t RESERVED0[3U]; /**< Reserved for future use **/ __IOM uint32_t HFRCOCTRL; /**< HFRCO Control Register */ uint32_t RESERVED1[1U]; /**< Reserved for future use **/ __IOM uint32_t AUXHFRCOCTRL; /**< AUXHFRCO Control Register */ uint32_t RESERVED2[1U]; /**< Reserved for future use **/ __IOM uint32_t LFRCOCTRL; /**< LFRCO Control Register */ __IOM uint32_t HFXOCTRL; /**< HFXO Control Register */ uint32_t RESERVED3[1U]; /**< Reserved for future use **/ __IOM uint32_t HFXOSTARTUPCTRL; /**< HFXO Startup Control */ __IOM uint32_t HFXOSTEADYSTATECTRL; /**< HFXO Steady State Control */ __IOM uint32_t HFXOTIMEOUTCTRL; /**< HFXO Timeout Control */ __IOM uint32_t LFXOCTRL; /**< LFXO Control Register */ uint32_t RESERVED4[1U]; /**< Reserved for future use **/ __IOM uint32_t DPLLCTRL; /**< DPLL Control Register */ __IOM uint32_t DPLLCTRL1; /**< DPLL Control Register */ uint32_t RESERVED5[2U]; /**< Reserved for future use **/ __IOM uint32_t CALCTRL; /**< Calibration Control Register */ __IOM uint32_t CALCNT; /**< Calibration Counter Register */ uint32_t RESERVED6[2U]; /**< Reserved for future use **/ __IOM uint32_t OSCENCMD; /**< Oscillator Enable/Disable Command Register */ __IOM uint32_t CMD; /**< Command Register */ uint32_t RESERVED7[2U]; /**< Reserved for future use **/ __IOM uint32_t DBGCLKSEL; /**< Debug Trace Clock Select */ __IOM uint32_t HFCLKSEL; /**< High Frequency Clock Select Command Register */ uint32_t RESERVED8[2U]; /**< Reserved for future use **/ __IOM uint32_t LFACLKSEL; /**< Low Frequency A Clock Select Register */ __IOM uint32_t LFBCLKSEL; /**< Low Frequency B Clock Select Register */ __IOM uint32_t LFECLKSEL; /**< Low Frequency E Clock Select Register */ uint32_t RESERVED9[1U]; /**< Reserved for future use **/ __IM uint32_t STATUS; /**< Status Register */ __IM uint32_t HFCLKSTATUS; /**< HFCLK Status Register */ uint32_t RESERVED10[1U]; /**< Reserved for future use **/ __IM uint32_t HFXOTRIMSTATUS; /**< HFXO Trim Status */ __IM uint32_t IF; /**< Interrupt Flag Register */ __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ __IOM uint32_t IEN; /**< Interrupt Enable Register */ __IOM uint32_t HFBUSCLKEN0; /**< High Frequency Bus Clock Enable Register 0 */ uint32_t RESERVED11[3U]; /**< Reserved for future use **/ __IOM uint32_t HFPERCLKEN0; /**< High Frequency Peripheral Clock Enable Register 0 */ uint32_t RESERVED12[7U]; /**< Reserved for future use **/ __IOM uint32_t LFACLKEN0; /**< Low Frequency a Clock Enable Register 0 (Async Reg) */ uint32_t RESERVED13[1U]; /**< Reserved for future use **/ __IOM uint32_t LFBCLKEN0; /**< Low Frequency B Clock Enable Register 0 (Async Reg) */ uint32_t RESERVED14[1U]; /**< Reserved for future use **/ __IOM uint32_t LFECLKEN0; /**< Low Frequency E Clock Enable Register 0 (Async Reg) */ uint32_t RESERVED15[3U]; /**< Reserved for future use **/ __IOM uint32_t HFPRESC; /**< High Frequency Clock Prescaler Register */ uint32_t RESERVED16[1U]; /**< Reserved for future use **/ __IOM uint32_t HFCOREPRESC; /**< High Frequency Core Clock Prescaler Register */ __IOM uint32_t HFPERPRESC; /**< High Frequency Peripheral Clock Prescaler Register */ uint32_t RESERVED17[1U]; /**< Reserved for future use **/ __IOM uint32_t HFEXPPRESC; /**< High Frequency Export Clock Prescaler Register */ uint32_t RESERVED18[2U]; /**< Reserved for future use **/ __IOM uint32_t LFAPRESC0; /**< Low Frequency a Prescaler Register 0 (Async Reg) */ uint32_t RESERVED19[1U]; /**< Reserved for future use **/ __IOM uint32_t LFBPRESC0; /**< Low Frequency B Prescaler Register 0 (Async Reg) */ uint32_t RESERVED20[1U]; /**< Reserved for future use **/ __IOM uint32_t LFEPRESC0; /**< Low Frequency E Prescaler Register 0 (Async Reg) */ uint32_t RESERVED21[3U]; /**< Reserved for future use **/ __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ __IOM uint32_t FREEZE; /**< Freeze Register */ uint32_t RESERVED22[2U]; /**< Reserved for future use **/ __IOM uint32_t PCNTCTRL; /**< PCNT Control Register */ uint32_t RESERVED23[2U]; /**< Reserved for future use **/ __IOM uint32_t ADCCTRL; /**< ADC Control Register */ uint32_t RESERVED24[4U]; /**< Reserved for future use **/ __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ __IOM uint32_t ROUTELOC1; /**< I/O Routing Location Register */ uint32_t RESERVED25[1U]; /**< Reserved for future use **/ __IOM uint32_t LOCK; /**< Configuration Lock Register */ __IOM uint32_t HFRCOSS; /**< HFRCO Spread Spectrum Register */ } CMU_TypeDef; /** @} */ /***************************************************************************//** * @addtogroup EFR32MG12P_CMU * @{ * @defgroup EFR32MG12P_CMU_BitFields CMU Bit Fields * @{ ******************************************************************************/ /* Bit fields for CMU CTRL */ #define _CMU_CTRL_RESETVALUE 0x00300000UL /**< Default value for CMU_CTRL */ #define _CMU_CTRL_MASK 0x001101EFUL /**< Mask for CMU_CTRL */ #define _CMU_CTRL_CLKOUTSEL0_SHIFT 0 /**< Shift value for CMU_CLKOUTSEL0 */ #define _CMU_CTRL_CLKOUTSEL0_MASK 0xFUL /**< Bit mask for CMU_CLKOUTSEL0 */ #define _CMU_CTRL_CLKOUTSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ #define _CMU_CTRL_CLKOUTSEL0_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */ #define _CMU_CTRL_CLKOUTSEL0_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */ #define _CMU_CTRL_CLKOUTSEL0_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */ #define _CMU_CTRL_CLKOUTSEL0_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */ #define _CMU_CTRL_CLKOUTSEL0_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */ #define _CMU_CTRL_CLKOUTSEL0_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */ #define _CMU_CTRL_CLKOUTSEL0_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */ #define _CMU_CTRL_CLKOUTSEL0_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */ #define _CMU_CTRL_CLKOUTSEL0_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */ #define _CMU_CTRL_CLKOUTSEL0_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */ #define _CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */ #define _CMU_CTRL_CLKOUTSEL0_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */ #define _CMU_CTRL_CLKOUTSEL0_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */ #define CMU_CTRL_CLKOUTSEL0_DEFAULT (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CTRL */ #define CMU_CTRL_CLKOUTSEL0_DISABLED (_CMU_CTRL_CLKOUTSEL0_DISABLED << 0) /**< Shifted mode DISABLED for CMU_CTRL */ #define CMU_CTRL_CLKOUTSEL0_ULFRCO (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_CTRL */ #define CMU_CTRL_CLKOUTSEL0_LFRCO (_CMU_CTRL_CLKOUTSEL0_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CTRL */ #define CMU_CTRL_CLKOUTSEL0_LFXO (_CMU_CTRL_CLKOUTSEL0_LFXO << 0) /**< Shifted mode LFXO for CMU_CTRL */ #define CMU_CTRL_CLKOUTSEL0_HFXO (_CMU_CTRL_CLKOUTSEL0_HFXO << 0) /**< Shifted mode HFXO for CMU_CTRL */ #define CMU_CTRL_CLKOUTSEL0_HFEXPCLK (_CMU_CTRL_CLKOUTSEL0_HFEXPCLK << 0) /**< Shifted mode HFEXPCLK for CMU_CTRL */ #define CMU_CTRL_CLKOUTSEL0_ULFRCOQ (_CMU_CTRL_CLKOUTSEL0_ULFRCOQ << 0) /**< Shifted mode ULFRCOQ for CMU_CTRL */ #define CMU_CTRL_CLKOUTSEL0_LFRCOQ (_CMU_CTRL_CLKOUTSEL0_LFRCOQ << 0) /**< Shifted mode LFRCOQ for CMU_CTRL */ #define CMU_CTRL_CLKOUTSEL0_LFXOQ (_CMU_CTRL_CLKOUTSEL0_LFXOQ << 0) /**< Shifted mode LFXOQ for CMU_CTRL */ #define CMU_CTRL_CLKOUTSEL0_HFRCOQ (_CMU_CTRL_CLKOUTSEL0_HFRCOQ << 0) /**< Shifted mode HFRCOQ for CMU_CTRL */ #define CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ << 0) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */ #define CMU_CTRL_CLKOUTSEL0_HFXOQ (_CMU_CTRL_CLKOUTSEL0_HFXOQ << 0) /**< Shifted mode HFXOQ for CMU_CTRL */ #define CMU_CTRL_CLKOUTSEL0_HFSRCCLK (_CMU_CTRL_CLKOUTSEL0_HFSRCCLK << 0) /**< Shifted mode HFSRCCLK for CMU_CTRL */ #define _CMU_CTRL_CLKOUTSEL1_SHIFT 5 /**< Shift value for CMU_CLKOUTSEL1 */ #define _CMU_CTRL_CLKOUTSEL1_MASK 0x1E0UL /**< Bit mask for CMU_CLKOUTSEL1 */ #define _CMU_CTRL_CLKOUTSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ #define _CMU_CTRL_CLKOUTSEL1_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */ #define _CMU_CTRL_CLKOUTSEL1_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */ #define _CMU_CTRL_CLKOUTSEL1_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */ #define _CMU_CTRL_CLKOUTSEL1_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */ #define _CMU_CTRL_CLKOUTSEL1_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */ #define _CMU_CTRL_CLKOUTSEL1_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */ #define _CMU_CTRL_CLKOUTSEL1_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */ #define _CMU_CTRL_CLKOUTSEL1_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */ #define _CMU_CTRL_CLKOUTSEL1_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */ #define _CMU_CTRL_CLKOUTSEL1_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */ #define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */ #define _CMU_CTRL_CLKOUTSEL1_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */ #define _CMU_CTRL_CLKOUTSEL1_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */ #define CMU_CTRL_CLKOUTSEL1_DEFAULT (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CTRL */ #define CMU_CTRL_CLKOUTSEL1_DISABLED (_CMU_CTRL_CLKOUTSEL1_DISABLED << 5) /**< Shifted mode DISABLED for CMU_CTRL */ #define CMU_CTRL_CLKOUTSEL1_ULFRCO (_CMU_CTRL_CLKOUTSEL1_ULFRCO << 5) /**< Shifted mode ULFRCO for CMU_CTRL */ #define CMU_CTRL_CLKOUTSEL1_LFRCO (_CMU_CTRL_CLKOUTSEL1_LFRCO << 5) /**< Shifted mode LFRCO for CMU_CTRL */ #define CMU_CTRL_CLKOUTSEL1_LFXO (_CMU_CTRL_CLKOUTSEL1_LFXO << 5) /**< Shifted mode LFXO for CMU_CTRL */ #define CMU_CTRL_CLKOUTSEL1_HFXO (_CMU_CTRL_CLKOUTSEL1_HFXO << 5) /**< Shifted mode HFXO for CMU_CTRL */ #define CMU_CTRL_CLKOUTSEL1_HFEXPCLK (_CMU_CTRL_CLKOUTSEL1_HFEXPCLK << 5) /**< Shifted mode HFEXPCLK for CMU_CTRL */ #define CMU_CTRL_CLKOUTSEL1_ULFRCOQ (_CMU_CTRL_CLKOUTSEL1_ULFRCOQ << 5) /**< Shifted mode ULFRCOQ for CMU_CTRL */ #define CMU_CTRL_CLKOUTSEL1_LFRCOQ (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 5) /**< Shifted mode LFRCOQ for CMU_CTRL */ #define CMU_CTRL_CLKOUTSEL1_LFXOQ (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 5) /**< Shifted mode LFXOQ for CMU_CTRL */ #define CMU_CTRL_CLKOUTSEL1_HFRCOQ (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 5) /**< Shifted mode HFRCOQ for CMU_CTRL */ #define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 5) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */ #define CMU_CTRL_CLKOUTSEL1_HFXOQ (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 5) /**< Shifted mode HFXOQ for CMU_CTRL */ #define CMU_CTRL_CLKOUTSEL1_HFSRCCLK (_CMU_CTRL_CLKOUTSEL1_HFSRCCLK << 5) /**< Shifted mode HFSRCCLK for CMU_CTRL */ #define CMU_CTRL_WSHFLE (0x1UL << 16) /**< Wait State for High-Frequency LE Interface */ #define _CMU_CTRL_WSHFLE_SHIFT 16 /**< Shift value for CMU_WSHFLE */ #define _CMU_CTRL_WSHFLE_MASK 0x10000UL /**< Bit mask for CMU_WSHFLE */ #define _CMU_CTRL_WSHFLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ #define CMU_CTRL_WSHFLE_DEFAULT (_CMU_CTRL_WSHFLE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CTRL */ #define CMU_CTRL_HFPERCLKEN (0x1UL << 20) /**< HFPERCLK Enable */ #define _CMU_CTRL_HFPERCLKEN_SHIFT 20 /**< Shift value for CMU_HFPERCLKEN */ #define _CMU_CTRL_HFPERCLKEN_MASK 0x100000UL /**< Bit mask for CMU_HFPERCLKEN */ #define _CMU_CTRL_HFPERCLKEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */ #define CMU_CTRL_HFPERCLKEN_DEFAULT (_CMU_CTRL_HFPERCLKEN_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CTRL */ /* Bit fields for CMU HFRCOCTRL */ #define _CMU_HFRCOCTRL_RESETVALUE 0xB1481F7FUL /**< Default value for CMU_HFRCOCTRL */ #define _CMU_HFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_HFRCOCTRL */ #define _CMU_HFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ #define _CMU_HFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ #define _CMU_HFRCOCTRL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ #define CMU_HFRCOCTRL_TUNING_DEFAULT (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ #define _CMU_HFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */ #define _CMU_HFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */ #define _CMU_HFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ #define CMU_HFRCOCTRL_FINETUNING_DEFAULT (_CMU_HFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ #define _CMU_HFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */ #define _CMU_HFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */ #define _CMU_HFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ #define CMU_HFRCOCTRL_FREQRANGE_DEFAULT (_CMU_HFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ #define _CMU_HFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */ #define _CMU_HFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */ #define _CMU_HFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ #define CMU_HFRCOCTRL_CMPBIAS_DEFAULT (_CMU_HFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ #define CMU_HFRCOCTRL_LDOHP (0x1UL << 24) /**< HFRCO LDO High Power Mode */ #define _CMU_HFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */ #define _CMU_HFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */ #define _CMU_HFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ #define CMU_HFRCOCTRL_LDOHP_DEFAULT (_CMU_HFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ #define _CMU_HFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */ #define _CMU_HFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */ #define _CMU_HFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ #define _CMU_HFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_HFRCOCTRL */ #define _CMU_HFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_HFRCOCTRL */ #define _CMU_HFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_HFRCOCTRL */ #define CMU_HFRCOCTRL_CLKDIV_DEFAULT (_CMU_HFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ #define CMU_HFRCOCTRL_CLKDIV_DIV1 (_CMU_HFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_HFRCOCTRL */ #define CMU_HFRCOCTRL_CLKDIV_DIV2 (_CMU_HFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_HFRCOCTRL */ #define CMU_HFRCOCTRL_CLKDIV_DIV4 (_CMU_HFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_HFRCOCTRL */ #define CMU_HFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable Reference for Fine Tuning */ #define _CMU_HFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */ #define _CMU_HFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */ #define _CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ #define CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ #define _CMU_HFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */ #define _CMU_HFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */ #define _CMU_HFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ #define CMU_HFRCOCTRL_VREFTC_DEFAULT (_CMU_HFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ /* Bit fields for CMU AUXHFRCOCTRL */ #define _CMU_AUXHFRCOCTRL_RESETVALUE 0xB1481F7FUL /**< Default value for CMU_AUXHFRCOCTRL */ #define _CMU_AUXHFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_AUXHFRCOCTRL */ #define _CMU_AUXHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ #define _CMU_AUXHFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ #define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ #define CMU_AUXHFRCOCTRL_TUNING_DEFAULT (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ #define _CMU_AUXHFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */ #define _CMU_AUXHFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */ #define _CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ #define CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT (_CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ #define _CMU_AUXHFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */ #define _CMU_AUXHFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */ #define _CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ #define CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT (_CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ #define _CMU_AUXHFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */ #define _CMU_AUXHFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */ #define _CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ #define CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT (_CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ #define CMU_AUXHFRCOCTRL_LDOHP (0x1UL << 24) /**< AUXHFRCO LDO High Power Mode */ #define _CMU_AUXHFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */ #define _CMU_AUXHFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */ #define _CMU_AUXHFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ #define CMU_AUXHFRCOCTRL_LDOHP_DEFAULT (_CMU_AUXHFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ #define _CMU_AUXHFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */ #define _CMU_AUXHFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */ #define _CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ #define _CMU_AUXHFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_AUXHFRCOCTRL */ #define _CMU_AUXHFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_AUXHFRCOCTRL */ #define _CMU_AUXHFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_AUXHFRCOCTRL */ #define CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT (_CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ #define CMU_AUXHFRCOCTRL_CLKDIV_DIV1 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_AUXHFRCOCTRL */ #define CMU_AUXHFRCOCTRL_CLKDIV_DIV2 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_AUXHFRCOCTRL */ #define CMU_AUXHFRCOCTRL_CLKDIV_DIV4 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_AUXHFRCOCTRL */ #define CMU_AUXHFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable Reference for Fine Tuning */ #define _CMU_AUXHFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */ #define _CMU_AUXHFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */ #define _CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ #define CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ #define _CMU_AUXHFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */ #define _CMU_AUXHFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */ #define _CMU_AUXHFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ #define CMU_AUXHFRCOCTRL_VREFTC_DEFAULT (_CMU_AUXHFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ /* Bit fields for CMU LFRCOCTRL */ #define _CMU_LFRCOCTRL_RESETVALUE 0x81060100UL /**< Default value for CMU_LFRCOCTRL */ #define _CMU_LFRCOCTRL_MASK 0xF33701FFUL /**< Mask for CMU_LFRCOCTRL */ #define _CMU_LFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ #define _CMU_LFRCOCTRL_TUNING_MASK 0x1FFUL /**< Bit mask for CMU_TUNING */ #define _CMU_LFRCOCTRL_TUNING_DEFAULT 0x00000100UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ #define CMU_LFRCOCTRL_TUNING_DEFAULT (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ #define CMU_LFRCOCTRL_ENVREF (0x1UL << 16) /**< Enable Duty Cycling of Vref */ #define _CMU_LFRCOCTRL_ENVREF_SHIFT 16 /**< Shift value for CMU_ENVREF */ #define _CMU_LFRCOCTRL_ENVREF_MASK 0x10000UL /**< Bit mask for CMU_ENVREF */ #define _CMU_LFRCOCTRL_ENVREF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ #define CMU_LFRCOCTRL_ENVREF_DEFAULT (_CMU_LFRCOCTRL_ENVREF_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ #define CMU_LFRCOCTRL_ENCHOP (0x1UL << 17) /**< Enable Comparator Chopping */ #define _CMU_LFRCOCTRL_ENCHOP_SHIFT 17 /**< Shift value for CMU_ENCHOP */ #define _CMU_LFRCOCTRL_ENCHOP_MASK 0x20000UL /**< Bit mask for CMU_ENCHOP */ #define _CMU_LFRCOCTRL_ENCHOP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ #define CMU_LFRCOCTRL_ENCHOP_DEFAULT (_CMU_LFRCOCTRL_ENCHOP_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ #define CMU_LFRCOCTRL_ENDEM (0x1UL << 18) /**< Enable Dynamic Element Matching */ #define _CMU_LFRCOCTRL_ENDEM_SHIFT 18 /**< Shift value for CMU_ENDEM */ #define _CMU_LFRCOCTRL_ENDEM_MASK 0x40000UL /**< Bit mask for CMU_ENDEM */ #define _CMU_LFRCOCTRL_ENDEM_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ #define CMU_LFRCOCTRL_ENDEM_DEFAULT (_CMU_LFRCOCTRL_ENDEM_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ #define _CMU_LFRCOCTRL_VREFUPDATE_SHIFT 20 /**< Shift value for CMU_VREFUPDATE */ #define _CMU_LFRCOCTRL_VREFUPDATE_MASK 0x300000UL /**< Bit mask for CMU_VREFUPDATE */ #define _CMU_LFRCOCTRL_VREFUPDATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ #define _CMU_LFRCOCTRL_VREFUPDATE_32CYCLES 0x00000000UL /**< Mode 32CYCLES for CMU_LFRCOCTRL */ #define _CMU_LFRCOCTRL_VREFUPDATE_64CYCLES 0x00000001UL /**< Mode 64CYCLES for CMU_LFRCOCTRL */ #define _CMU_LFRCOCTRL_VREFUPDATE_128CYCLES 0x00000002UL /**< Mode 128CYCLES for CMU_LFRCOCTRL */ #define _CMU_LFRCOCTRL_VREFUPDATE_256CYCLES 0x00000003UL /**< Mode 256CYCLES for CMU_LFRCOCTRL */ #define CMU_LFRCOCTRL_VREFUPDATE_DEFAULT (_CMU_LFRCOCTRL_VREFUPDATE_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ #define CMU_LFRCOCTRL_VREFUPDATE_32CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_32CYCLES << 20) /**< Shifted mode 32CYCLES for CMU_LFRCOCTRL */ #define CMU_LFRCOCTRL_VREFUPDATE_64CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_64CYCLES << 20) /**< Shifted mode 64CYCLES for CMU_LFRCOCTRL */ #define CMU_LFRCOCTRL_VREFUPDATE_128CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_128CYCLES << 20) /**< Shifted mode 128CYCLES for CMU_LFRCOCTRL */ #define CMU_LFRCOCTRL_VREFUPDATE_256CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_256CYCLES << 20) /**< Shifted mode 256CYCLES for CMU_LFRCOCTRL */ #define _CMU_LFRCOCTRL_TIMEOUT_SHIFT 24 /**< Shift value for CMU_TIMEOUT */ #define _CMU_LFRCOCTRL_TIMEOUT_MASK 0x3000000UL /**< Bit mask for CMU_TIMEOUT */ #define _CMU_LFRCOCTRL_TIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_LFRCOCTRL */ #define _CMU_LFRCOCTRL_TIMEOUT_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ #define _CMU_LFRCOCTRL_TIMEOUT_16CYCLES 0x00000001UL /**< Mode 16CYCLES for CMU_LFRCOCTRL */ #define _CMU_LFRCOCTRL_TIMEOUT_32CYCLES 0x00000002UL /**< Mode 32CYCLES for CMU_LFRCOCTRL */ #define CMU_LFRCOCTRL_TIMEOUT_2CYCLES (_CMU_LFRCOCTRL_TIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_LFRCOCTRL */ #define CMU_LFRCOCTRL_TIMEOUT_DEFAULT (_CMU_LFRCOCTRL_TIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ #define CMU_LFRCOCTRL_TIMEOUT_16CYCLES (_CMU_LFRCOCTRL_TIMEOUT_16CYCLES << 24) /**< Shifted mode 16CYCLES for CMU_LFRCOCTRL */ #define CMU_LFRCOCTRL_TIMEOUT_32CYCLES (_CMU_LFRCOCTRL_TIMEOUT_32CYCLES << 24) /**< Shifted mode 32CYCLES for CMU_LFRCOCTRL */ #define _CMU_LFRCOCTRL_GMCCURTUNE_SHIFT 28 /**< Shift value for CMU_GMCCURTUNE */ #define _CMU_LFRCOCTRL_GMCCURTUNE_MASK 0xF0000000UL /**< Bit mask for CMU_GMCCURTUNE */ #define _CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ #define CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT (_CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ /* Bit fields for CMU HFXOCTRL */ #define _CMU_HFXOCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_HFXOCTRL */ #define _CMU_HFXOCTRL_MASK 0x37000731UL /**< Mask for CMU_HFXOCTRL */ #define CMU_HFXOCTRL_MODE (0x1UL << 0) /**< HFXO Mode */ #define _CMU_HFXOCTRL_MODE_SHIFT 0 /**< Shift value for CMU_MODE */ #define _CMU_HFXOCTRL_MODE_MASK 0x1UL /**< Bit mask for CMU_MODE */ #define _CMU_HFXOCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ #define _CMU_HFXOCTRL_MODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_HFXOCTRL */ #define _CMU_HFXOCTRL_MODE_EXTCLK 0x00000001UL /**< Mode EXTCLK for CMU_HFXOCTRL */ #define CMU_HFXOCTRL_MODE_DEFAULT (_CMU_HFXOCTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ #define CMU_HFXOCTRL_MODE_XTAL (_CMU_HFXOCTRL_MODE_XTAL << 0) /**< Shifted mode XTAL for CMU_HFXOCTRL */ #define CMU_HFXOCTRL_MODE_EXTCLK (_CMU_HFXOCTRL_MODE_EXTCLK << 0) /**< Shifted mode EXTCLK for CMU_HFXOCTRL */ #define _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_SHIFT 4 /**< Shift value for CMU_PEAKDETSHUNTOPTMODE */ #define _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK 0x30UL /**< Bit mask for CMU_PEAKDETSHUNTOPTMODE */ #define _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ #define _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_AUTOCMD 0x00000000UL /**< Mode AUTOCMD for CMU_HFXOCTRL */ #define _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_CMD 0x00000001UL /**< Mode CMD for CMU_HFXOCTRL */ #define _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MANUAL 0x00000002UL /**< Mode MANUAL for CMU_HFXOCTRL */ #define CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_DEFAULT (_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ #define CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_AUTOCMD (_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_AUTOCMD << 4) /**< Shifted mode AUTOCMD for CMU_HFXOCTRL */ #define CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_CMD (_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_CMD << 4) /**< Shifted mode CMD for CMU_HFXOCTRL */ #define CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MANUAL (_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MANUAL << 4) /**< Shifted mode MANUAL for CMU_HFXOCTRL */ #define CMU_HFXOCTRL_LOWPOWER (0x1UL << 8) /**< Low Power Mode Control */ #define _CMU_HFXOCTRL_LOWPOWER_SHIFT 8 /**< Shift value for CMU_LOWPOWER */ #define _CMU_HFXOCTRL_LOWPOWER_MASK 0x100UL /**< Bit mask for CMU_LOWPOWER */ #define _CMU_HFXOCTRL_LOWPOWER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ #define CMU_HFXOCTRL_LOWPOWER_DEFAULT (_CMU_HFXOCTRL_LOWPOWER_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ #define CMU_HFXOCTRL_XTI2GND (0x1UL << 9) /**< Clamp HFXTAL_N Pin to Ground When HFXO Oscillator is Off */ #define _CMU_HFXOCTRL_XTI2GND_SHIFT 9 /**< Shift value for CMU_XTI2GND */ #define _CMU_HFXOCTRL_XTI2GND_MASK 0x200UL /**< Bit mask for CMU_XTI2GND */ #define _CMU_HFXOCTRL_XTI2GND_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ #define CMU_HFXOCTRL_XTI2GND_DEFAULT (_CMU_HFXOCTRL_XTI2GND_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ #define CMU_HFXOCTRL_XTO2GND (0x1UL << 10) /**< Clamp HFXTAL_P Pin to Ground When HFXO Oscillator is Off */ #define _CMU_HFXOCTRL_XTO2GND_SHIFT 10 /**< Shift value for CMU_XTO2GND */ #define _CMU_HFXOCTRL_XTO2GND_MASK 0x400UL /**< Bit mask for CMU_XTO2GND */ #define _CMU_HFXOCTRL_XTO2GND_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ #define CMU_HFXOCTRL_XTO2GND_DEFAULT (_CMU_HFXOCTRL_XTO2GND_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ #define _CMU_HFXOCTRL_LFTIMEOUT_SHIFT 24 /**< Shift value for CMU_LFTIMEOUT */ #define _CMU_HFXOCTRL_LFTIMEOUT_MASK 0x7000000UL /**< Bit mask for CMU_LFTIMEOUT */ #define _CMU_HFXOCTRL_LFTIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ #define _CMU_HFXOCTRL_LFTIMEOUT_0CYCLES 0x00000000UL /**< Mode 0CYCLES for CMU_HFXOCTRL */ #define _CMU_HFXOCTRL_LFTIMEOUT_2CYCLES 0x00000001UL /**< Mode 2CYCLES for CMU_HFXOCTRL */ #define _CMU_HFXOCTRL_LFTIMEOUT_4CYCLES 0x00000002UL /**< Mode 4CYCLES for CMU_HFXOCTRL */ #define _CMU_HFXOCTRL_LFTIMEOUT_16CYCLES 0x00000003UL /**< Mode 16CYCLES for CMU_HFXOCTRL */ #define _CMU_HFXOCTRL_LFTIMEOUT_32CYCLES 0x00000004UL /**< Mode 32CYCLES for CMU_HFXOCTRL */ #define _CMU_HFXOCTRL_LFTIMEOUT_64CYCLES 0x00000005UL /**< Mode 64CYCLES for CMU_HFXOCTRL */ #define _CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES 0x00000006UL /**< Mode 1KCYCLES for CMU_HFXOCTRL */ #define _CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES 0x00000007UL /**< Mode 4KCYCLES for CMU_HFXOCTRL */ #define CMU_HFXOCTRL_LFTIMEOUT_DEFAULT (_CMU_HFXOCTRL_LFTIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ #define CMU_HFXOCTRL_LFTIMEOUT_0CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_0CYCLES << 24) /**< Shifted mode 0CYCLES for CMU_HFXOCTRL */ #define CMU_HFXOCTRL_LFTIMEOUT_2CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_HFXOCTRL */ #define CMU_HFXOCTRL_LFTIMEOUT_4CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_4CYCLES << 24) /**< Shifted mode 4CYCLES for CMU_HFXOCTRL */ #define CMU_HFXOCTRL_LFTIMEOUT_16CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_16CYCLES << 24) /**< Shifted mode 16CYCLES for CMU_HFXOCTRL */ #define CMU_HFXOCTRL_LFTIMEOUT_32CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_32CYCLES << 24) /**< Shifted mode 32CYCLES for CMU_HFXOCTRL */ #define CMU_HFXOCTRL_LFTIMEOUT_64CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_64CYCLES << 24) /**< Shifted mode 64CYCLES for CMU_HFXOCTRL */ #define CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES (_CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES << 24) /**< Shifted mode 1KCYCLES for CMU_HFXOCTRL */ #define CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES (_CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES << 24) /**< Shifted mode 4KCYCLES for CMU_HFXOCTRL */ #define CMU_HFXOCTRL_AUTOSTARTEM0EM1 (0x1UL << 28) /**< Automatically Start of HFXO Upon EM0/EM1 Entry From EM2/EM3 */ #define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_SHIFT 28 /**< Shift value for CMU_AUTOSTARTEM0EM1 */ #define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_MASK 0x10000000UL /**< Bit mask for CMU_AUTOSTARTEM0EM1 */ #define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ #define CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT (_CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ #define CMU_HFXOCTRL_AUTOSTARTSELEM0EM1 (0x1UL << 29) /**< Automatically Start and Select of HFXO Upon EM0/EM1 Entry From EM2/EM3 */ #define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_SHIFT 29 /**< Shift value for CMU_AUTOSTARTSELEM0EM1 */ #define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_MASK 0x20000000UL /**< Bit mask for CMU_AUTOSTARTSELEM0EM1 */ #define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ #define CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT (_CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ /* Bit fields for CMU HFXOSTARTUPCTRL */ #define _CMU_HFXOSTARTUPCTRL_RESETVALUE 0x00050020UL /**< Default value for CMU_HFXOSTARTUPCTRL */ #define _CMU_HFXOSTARTUPCTRL_MASK 0x000FF87FUL /**< Mask for CMU_HFXOSTARTUPCTRL */ #define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ #define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_MASK 0x7FUL /**< Bit mask for CMU_IBTRIMXOCORE */ #define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT 0x00000020UL /**< Mode DEFAULT for CMU_HFXOSTARTUPCTRL */ #define CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT (_CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOSTARTUPCTRL */ #define _CMU_HFXOSTARTUPCTRL_CTUNE_SHIFT 11 /**< Shift value for CMU_CTUNE */ #define _CMU_HFXOSTARTUPCTRL_CTUNE_MASK 0xFF800UL /**< Bit mask for CMU_CTUNE */ #define _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT 0x000000A0UL /**< Mode DEFAULT for CMU_HFXOSTARTUPCTRL */ #define CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT (_CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFXOSTARTUPCTRL */ /* Bit fields for CMU HFXOSTEADYSTATECTRL */ #define _CMU_HFXOSTEADYSTATECTRL_RESETVALUE 0xA30B4507UL /**< Default value for CMU_HFXOSTEADYSTATECTRL */ #define _CMU_HFXOSTEADYSTATECTRL_MASK 0xF70FFFFFUL /**< Mask for CMU_HFXOSTEADYSTATECTRL */ #define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ #define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_MASK 0x7FUL /**< Bit mask for CMU_IBTRIMXOCORE */ #define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT 0x00000007UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ #define CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ #define _CMU_HFXOSTEADYSTATECTRL_REGISH_SHIFT 7 /**< Shift value for CMU_REGISH */ #define _CMU_HFXOSTEADYSTATECTRL_REGISH_MASK 0x780UL /**< Bit mask for CMU_REGISH */ #define _CMU_HFXOSTEADYSTATECTRL_REGISH_DEFAULT 0x0000000AUL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ #define CMU_HFXOSTEADYSTATECTRL_REGISH_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_REGISH_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ #define _CMU_HFXOSTEADYSTATECTRL_CTUNE_SHIFT 11 /**< Shift value for CMU_CTUNE */ #define _CMU_HFXOSTEADYSTATECTRL_CTUNE_MASK 0xFF800UL /**< Bit mask for CMU_CTUNE */ #define _CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT 0x00000168UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ #define CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ #define _CMU_HFXOSTEADYSTATECTRL_REGSELILOW_SHIFT 24 /**< Shift value for CMU_REGSELILOW */ #define _CMU_HFXOSTEADYSTATECTRL_REGSELILOW_MASK 0x3000000UL /**< Bit mask for CMU_REGSELILOW */ #define _CMU_HFXOSTEADYSTATECTRL_REGSELILOW_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ #define CMU_HFXOSTEADYSTATECTRL_REGSELILOW_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_REGSELILOW_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ #define CMU_HFXOSTEADYSTATECTRL_PEAKDETEN (0x1UL << 26) /**< Enables Oscillator Peak Detectors */ #define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_SHIFT 26 /**< Shift value for CMU_PEAKDETEN */ #define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_MASK 0x4000000UL /**< Bit mask for CMU_PEAKDETEN */ #define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ #define CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ #define _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_SHIFT 28 /**< Shift value for CMU_REGISHUPPER */ #define _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_MASK 0xF0000000UL /**< Bit mask for CMU_REGISHUPPER */ #define _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_DEFAULT 0x0000000AUL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ #define CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ /* Bit fields for CMU HFXOTIMEOUTCTRL */ #define _CMU_HFXOTIMEOUTCTRL_RESETVALUE 0x0002A067UL /**< Default value for CMU_HFXOTIMEOUTCTRL */ #define _CMU_HFXOTIMEOUTCTRL_MASK 0x000FF0FFUL /**< Mask for CMU_HFXOTIMEOUTCTRL */ #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_SHIFT 0 /**< Shift value for CMU_STARTUPTIMEOUT */ #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_MASK 0xFUL /**< Bit mask for CMU_STARTUPTIMEOUT */ #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES 0x00000004UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES 0x00000005UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES 0x00000006UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT 0x00000007UL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES 0x00000007UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES 0x00000008UL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES 0x00000009UL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES 0x0000000AUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES << 0) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES << 0) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES << 0) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES << 0) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES << 0) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES << 0) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES << 0) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES << 0) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES << 0) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES << 0) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES << 0) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_SHIFT 4 /**< Shift value for CMU_STEADYTIMEOUT */ #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_MASK 0xF0UL /**< Bit mask for CMU_STEADYTIMEOUT */ #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES 0x00000004UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES 0x00000005UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT 0x00000006UL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES 0x00000006UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES 0x00000007UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES 0x00000008UL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES 0x00000009UL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES 0x0000000AUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES << 4) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES << 4) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES << 4) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES << 4) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES << 4) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES << 4) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES << 4) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES << 4) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES << 4) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES << 4) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES << 4) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_SHIFT 12 /**< Shift value for CMU_PEAKDETTIMEOUT */ #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_MASK 0xF000UL /**< Bit mask for CMU_PEAKDETTIMEOUT */ #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES 0x00000004UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES 0x00000005UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES 0x00000006UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES 0x00000007UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES 0x00000008UL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES 0x00000009UL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT 0x0000000AUL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES 0x0000000AUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES << 12) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES << 12) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES << 12) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES << 12) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES << 12) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES << 12) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES << 12) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES << 12) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES << 12) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES << 12) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES << 12) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ #define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_SHIFT 16 /**< Shift value for CMU_SHUNTOPTTIMEOUT */ #define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_MASK 0xF0000UL /**< Bit mask for CMU_SHUNTOPTTIMEOUT */ #define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ #define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ #define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ #define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ #define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ #define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_256CYCLES 0x00000004UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ #define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_1KCYCLES 0x00000005UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ #define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_2KCYCLES 0x00000006UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ #define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_4KCYCLES 0x00000007UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ #define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_8KCYCLES 0x00000008UL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ #define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_16KCYCLES 0x00000009UL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ #define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_32KCYCLES 0x0000000AUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ #define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_2CYCLES << 16) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ #define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_4CYCLES << 16) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ #define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ #define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_16CYCLES << 16) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ #define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_32CYCLES << 16) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ #define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_256CYCLES << 16) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ #define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_1KCYCLES << 16) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ #define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_2KCYCLES << 16) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ #define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_4KCYCLES << 16) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ #define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_8KCYCLES << 16) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ #define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_16KCYCLES << 16) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ #define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_32KCYCLES << 16) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ /* Bit fields for CMU LFXOCTRL */ #define _CMU_LFXOCTRL_RESETVALUE 0x07009000UL /**< Default value for CMU_LFXOCTRL */ #define _CMU_LFXOCTRL_MASK 0x0713DB7FUL /**< Mask for CMU_LFXOCTRL */ #define _CMU_LFXOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ #define _CMU_LFXOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ #define _CMU_LFXOCTRL_TUNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ #define CMU_LFXOCTRL_TUNING_DEFAULT (_CMU_LFXOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ #define _CMU_LFXOCTRL_MODE_SHIFT 8 /**< Shift value for CMU_MODE */ #define _CMU_LFXOCTRL_MODE_MASK 0x300UL /**< Bit mask for CMU_MODE */ #define _CMU_LFXOCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ #define _CMU_LFXOCTRL_MODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_LFXOCTRL */ #define _CMU_LFXOCTRL_MODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_LFXOCTRL */ #define _CMU_LFXOCTRL_MODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_LFXOCTRL */ #define CMU_LFXOCTRL_MODE_DEFAULT (_CMU_LFXOCTRL_MODE_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ #define CMU_LFXOCTRL_MODE_XTAL (_CMU_LFXOCTRL_MODE_XTAL << 8) /**< Shifted mode XTAL for CMU_LFXOCTRL */ #define CMU_LFXOCTRL_MODE_BUFEXTCLK (_CMU_LFXOCTRL_MODE_BUFEXTCLK << 8) /**< Shifted mode BUFEXTCLK for CMU_LFXOCTRL */ #define CMU_LFXOCTRL_MODE_DIGEXTCLK (_CMU_LFXOCTRL_MODE_DIGEXTCLK << 8) /**< Shifted mode DIGEXTCLK for CMU_LFXOCTRL */ #define _CMU_LFXOCTRL_GAIN_SHIFT 11 /**< Shift value for CMU_GAIN */ #define _CMU_LFXOCTRL_GAIN_MASK 0x1800UL /**< Bit mask for CMU_GAIN */ #define _CMU_LFXOCTRL_GAIN_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_LFXOCTRL */ #define CMU_LFXOCTRL_GAIN_DEFAULT (_CMU_LFXOCTRL_GAIN_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ #define CMU_LFXOCTRL_HIGHAMPL (0x1UL << 14) /**< LFXO High XTAL Oscillation Amplitude Enable */ #define _CMU_LFXOCTRL_HIGHAMPL_SHIFT 14 /**< Shift value for CMU_HIGHAMPL */ #define _CMU_LFXOCTRL_HIGHAMPL_MASK 0x4000UL /**< Bit mask for CMU_HIGHAMPL */ #define _CMU_LFXOCTRL_HIGHAMPL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ #define CMU_LFXOCTRL_HIGHAMPL_DEFAULT (_CMU_LFXOCTRL_HIGHAMPL_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ #define CMU_LFXOCTRL_AGC (0x1UL << 15) /**< LFXO AGC Enable */ #define _CMU_LFXOCTRL_AGC_SHIFT 15 /**< Shift value for CMU_AGC */ #define _CMU_LFXOCTRL_AGC_MASK 0x8000UL /**< Bit mask for CMU_AGC */ #define _CMU_LFXOCTRL_AGC_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFXOCTRL */ #define CMU_LFXOCTRL_AGC_DEFAULT (_CMU_LFXOCTRL_AGC_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ #define _CMU_LFXOCTRL_CUR_SHIFT 16 /**< Shift value for CMU_CUR */ #define _CMU_LFXOCTRL_CUR_MASK 0x30000UL /**< Bit mask for CMU_CUR */ #define _CMU_LFXOCTRL_CUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ #define CMU_LFXOCTRL_CUR_DEFAULT (_CMU_LFXOCTRL_CUR_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ #define CMU_LFXOCTRL_BUFCUR (0x1UL << 20) /**< LFXO Buffer Bias Current */ #define _CMU_LFXOCTRL_BUFCUR_SHIFT 20 /**< Shift value for CMU_BUFCUR */ #define _CMU_LFXOCTRL_BUFCUR_MASK 0x100000UL /**< Bit mask for CMU_BUFCUR */ #define _CMU_LFXOCTRL_BUFCUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ #define CMU_LFXOCTRL_BUFCUR_DEFAULT (_CMU_LFXOCTRL_BUFCUR_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ #define _CMU_LFXOCTRL_TIMEOUT_SHIFT 24 /**< Shift value for CMU_TIMEOUT */ #define _CMU_LFXOCTRL_TIMEOUT_MASK 0x7000000UL /**< Bit mask for CMU_TIMEOUT */ #define _CMU_LFXOCTRL_TIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_LFXOCTRL */ #define _CMU_LFXOCTRL_TIMEOUT_256CYCLES 0x00000001UL /**< Mode 256CYCLES for CMU_LFXOCTRL */ #define _CMU_LFXOCTRL_TIMEOUT_1KCYCLES 0x00000002UL /**< Mode 1KCYCLES for CMU_LFXOCTRL */ #define _CMU_LFXOCTRL_TIMEOUT_2KCYCLES 0x00000003UL /**< Mode 2KCYCLES for CMU_LFXOCTRL */ #define _CMU_LFXOCTRL_TIMEOUT_4KCYCLES 0x00000004UL /**< Mode 4KCYCLES for CMU_LFXOCTRL */ #define _CMU_LFXOCTRL_TIMEOUT_8KCYCLES 0x00000005UL /**< Mode 8KCYCLES for CMU_LFXOCTRL */ #define _CMU_LFXOCTRL_TIMEOUT_16KCYCLES 0x00000006UL /**< Mode 16KCYCLES for CMU_LFXOCTRL */ #define _CMU_LFXOCTRL_TIMEOUT_DEFAULT 0x00000007UL /**< Mode DEFAULT for CMU_LFXOCTRL */ #define _CMU_LFXOCTRL_TIMEOUT_32KCYCLES 0x00000007UL /**< Mode 32KCYCLES for CMU_LFXOCTRL */ #define CMU_LFXOCTRL_TIMEOUT_2CYCLES (_CMU_LFXOCTRL_TIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_LFXOCTRL */ #define CMU_LFXOCTRL_TIMEOUT_256CYCLES (_CMU_LFXOCTRL_TIMEOUT_256CYCLES << 24) /**< Shifted mode 256CYCLES for CMU_LFXOCTRL */ #define CMU_LFXOCTRL_TIMEOUT_1KCYCLES (_CMU_LFXOCTRL_TIMEOUT_1KCYCLES << 24) /**< Shifted mode 1KCYCLES for CMU_LFXOCTRL */ #define CMU_LFXOCTRL_TIMEOUT_2KCYCLES (_CMU_LFXOCTRL_TIMEOUT_2KCYCLES << 24) /**< Shifted mode 2KCYCLES for CMU_LFXOCTRL */ #define CMU_LFXOCTRL_TIMEOUT_4KCYCLES (_CMU_LFXOCTRL_TIMEOUT_4KCYCLES << 24) /**< Shifted mode 4KCYCLES for CMU_LFXOCTRL */ #define CMU_LFXOCTRL_TIMEOUT_8KCYCLES (_CMU_LFXOCTRL_TIMEOUT_8KCYCLES << 24) /**< Shifted mode 8KCYCLES for CMU_LFXOCTRL */ #define CMU_LFXOCTRL_TIMEOUT_16KCYCLES (_CMU_LFXOCTRL_TIMEOUT_16KCYCLES << 24) /**< Shifted mode 16KCYCLES for CMU_LFXOCTRL */ #define CMU_LFXOCTRL_TIMEOUT_DEFAULT (_CMU_LFXOCTRL_TIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ #define CMU_LFXOCTRL_TIMEOUT_32KCYCLES (_CMU_LFXOCTRL_TIMEOUT_32KCYCLES << 24) /**< Shifted mode 32KCYCLES for CMU_LFXOCTRL */ /* Bit fields for CMU DPLLCTRL */ #define _CMU_DPLLCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_DPLLCTRL */ #define _CMU_DPLLCTRL_MASK 0x0000001FUL /**< Mask for CMU_DPLLCTRL */ #define CMU_DPLLCTRL_MODE (0x1UL << 0) /**< Operating Mode Control */ #define _CMU_DPLLCTRL_MODE_SHIFT 0 /**< Shift value for CMU_MODE */ #define _CMU_DPLLCTRL_MODE_MASK 0x1UL /**< Bit mask for CMU_MODE */ #define _CMU_DPLLCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ #define _CMU_DPLLCTRL_MODE_FREQLL 0x00000000UL /**< Mode FREQLL for CMU_DPLLCTRL */ #define _CMU_DPLLCTRL_MODE_PHASELL 0x00000001UL /**< Mode PHASELL for CMU_DPLLCTRL */ #define CMU_DPLLCTRL_MODE_DEFAULT (_CMU_DPLLCTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ #define CMU_DPLLCTRL_MODE_FREQLL (_CMU_DPLLCTRL_MODE_FREQLL << 0) /**< Shifted mode FREQLL for CMU_DPLLCTRL */ #define CMU_DPLLCTRL_MODE_PHASELL (_CMU_DPLLCTRL_MODE_PHASELL << 0) /**< Shifted mode PHASELL for CMU_DPLLCTRL */ #define CMU_DPLLCTRL_EDGESEL (0x1UL << 1) /**< Reference Edge Select */ #define _CMU_DPLLCTRL_EDGESEL_SHIFT 1 /**< Shift value for CMU_EDGESEL */ #define _CMU_DPLLCTRL_EDGESEL_MASK 0x2UL /**< Bit mask for CMU_EDGESEL */ #define _CMU_DPLLCTRL_EDGESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ #define _CMU_DPLLCTRL_EDGESEL_FALL 0x00000000UL /**< Mode FALL for CMU_DPLLCTRL */ #define _CMU_DPLLCTRL_EDGESEL_RISE 0x00000001UL /**< Mode RISE for CMU_DPLLCTRL */ #define CMU_DPLLCTRL_EDGESEL_DEFAULT (_CMU_DPLLCTRL_EDGESEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ #define CMU_DPLLCTRL_EDGESEL_FALL (_CMU_DPLLCTRL_EDGESEL_FALL << 1) /**< Shifted mode FALL for CMU_DPLLCTRL */ #define CMU_DPLLCTRL_EDGESEL_RISE (_CMU_DPLLCTRL_EDGESEL_RISE << 1) /**< Shifted mode RISE for CMU_DPLLCTRL */ #define CMU_DPLLCTRL_AUTORECOVER (0x1UL << 2) /**< Automatic Recovery Ctrl */ #define _CMU_DPLLCTRL_AUTORECOVER_SHIFT 2 /**< Shift value for CMU_AUTORECOVER */ #define _CMU_DPLLCTRL_AUTORECOVER_MASK 0x4UL /**< Bit mask for CMU_AUTORECOVER */ #define _CMU_DPLLCTRL_AUTORECOVER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ #define CMU_DPLLCTRL_AUTORECOVER_DEFAULT (_CMU_DPLLCTRL_AUTORECOVER_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ #define _CMU_DPLLCTRL_REFSEL_SHIFT 3 /**< Shift value for CMU_REFSEL */ #define _CMU_DPLLCTRL_REFSEL_MASK 0x18UL /**< Bit mask for CMU_REFSEL */ #define _CMU_DPLLCTRL_REFSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ #define _CMU_DPLLCTRL_REFSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_DPLLCTRL */ #define _CMU_DPLLCTRL_REFSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_DPLLCTRL */ #define _CMU_DPLLCTRL_REFSEL_CLKIN0 0x00000003UL /**< Mode CLKIN0 for CMU_DPLLCTRL */ #define CMU_DPLLCTRL_REFSEL_DEFAULT (_CMU_DPLLCTRL_REFSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ #define CMU_DPLLCTRL_REFSEL_HFXO (_CMU_DPLLCTRL_REFSEL_HFXO << 3) /**< Shifted mode HFXO for CMU_DPLLCTRL */ #define CMU_DPLLCTRL_REFSEL_LFXO (_CMU_DPLLCTRL_REFSEL_LFXO << 3) /**< Shifted mode LFXO for CMU_DPLLCTRL */ #define CMU_DPLLCTRL_REFSEL_CLKIN0 (_CMU_DPLLCTRL_REFSEL_CLKIN0 << 3) /**< Shifted mode CLKIN0 for CMU_DPLLCTRL */ /* Bit fields for CMU DPLLCTRL1 */ #define _CMU_DPLLCTRL1_RESETVALUE 0x00000000UL /**< Default value for CMU_DPLLCTRL1 */ #define _CMU_DPLLCTRL1_MASK 0x0FFF0FFFUL /**< Mask for CMU_DPLLCTRL1 */ #define _CMU_DPLLCTRL1_M_SHIFT 0 /**< Shift value for CMU_M */ #define _CMU_DPLLCTRL1_M_MASK 0xFFFUL /**< Bit mask for CMU_M */ #define _CMU_DPLLCTRL1_M_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL1 */ #define CMU_DPLLCTRL1_M_DEFAULT (_CMU_DPLLCTRL1_M_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DPLLCTRL1 */ #define _CMU_DPLLCTRL1_N_SHIFT 16 /**< Shift value for CMU_N */ #define _CMU_DPLLCTRL1_N_MASK 0xFFF0000UL /**< Bit mask for CMU_N */ #define _CMU_DPLLCTRL1_N_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL1 */ #define CMU_DPLLCTRL1_N_DEFAULT (_CMU_DPLLCTRL1_N_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_DPLLCTRL1 */ /* Bit fields for CMU CALCTRL */ #define _CMU_CALCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCTRL */ #define _CMU_CALCTRL_MASK 0x0F0F0177UL /**< Mask for CMU_CALCTRL */ #define _CMU_CALCTRL_UPSEL_SHIFT 0 /**< Shift value for CMU_UPSEL */ #define _CMU_CALCTRL_UPSEL_MASK 0x7UL /**< Bit mask for CMU_UPSEL */ #define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ #define _CMU_CALCTRL_UPSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_CALCTRL */ #define _CMU_CALCTRL_UPSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_CALCTRL */ #define _CMU_CALCTRL_UPSEL_HFRCO 0x00000002UL /**< Mode HFRCO for CMU_CALCTRL */ #define _CMU_CALCTRL_UPSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CALCTRL */ #define _CMU_CALCTRL_UPSEL_AUXHFRCO 0x00000004UL /**< Mode AUXHFRCO for CMU_CALCTRL */ #define _CMU_CALCTRL_UPSEL_PRS 0x00000005UL /**< Mode PRS for CMU_CALCTRL */ #define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCTRL */ #define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CALCTRL */ #define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CALCTRL */ #define CMU_CALCTRL_UPSEL_HFRCO (_CMU_CALCTRL_UPSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CALCTRL */ #define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CALCTRL */ #define CMU_CALCTRL_UPSEL_AUXHFRCO (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */ #define CMU_CALCTRL_UPSEL_PRS (_CMU_CALCTRL_UPSEL_PRS << 0) /**< Shifted mode PRS for CMU_CALCTRL */ #define _CMU_CALCTRL_DOWNSEL_SHIFT 4 /**< Shift value for CMU_DOWNSEL */ #define _CMU_CALCTRL_DOWNSEL_MASK 0x70UL /**< Bit mask for CMU_DOWNSEL */ #define _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ #define _CMU_CALCTRL_DOWNSEL_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_CALCTRL */ #define _CMU_CALCTRL_DOWNSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_CALCTRL */ #define _CMU_CALCTRL_DOWNSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_CALCTRL */ #define _CMU_CALCTRL_DOWNSEL_HFRCO 0x00000003UL /**< Mode HFRCO for CMU_CALCTRL */ #define _CMU_CALCTRL_DOWNSEL_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_CALCTRL */ #define _CMU_CALCTRL_DOWNSEL_AUXHFRCO 0x00000005UL /**< Mode AUXHFRCO for CMU_CALCTRL */ #define _CMU_CALCTRL_DOWNSEL_PRS 0x00000006UL /**< Mode PRS for CMU_CALCTRL */ #define CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CALCTRL */ #define CMU_CALCTRL_DOWNSEL_HFCLK (_CMU_CALCTRL_DOWNSEL_HFCLK << 4) /**< Shifted mode HFCLK for CMU_CALCTRL */ #define CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 4) /**< Shifted mode HFXO for CMU_CALCTRL */ #define CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 4) /**< Shifted mode LFXO for CMU_CALCTRL */ #define CMU_CALCTRL_DOWNSEL_HFRCO (_CMU_CALCTRL_DOWNSEL_HFRCO << 4) /**< Shifted mode HFRCO for CMU_CALCTRL */ #define CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 4) /**< Shifted mode LFRCO for CMU_CALCTRL */ #define CMU_CALCTRL_DOWNSEL_AUXHFRCO (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 4) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */ #define CMU_CALCTRL_DOWNSEL_PRS (_CMU_CALCTRL_DOWNSEL_PRS << 4) /**< Shifted mode PRS for CMU_CALCTRL */ #define CMU_CALCTRL_CONT (0x1UL << 8) /**< Continuous Calibration */ #define _CMU_CALCTRL_CONT_SHIFT 8 /**< Shift value for CMU_CONT */ #define _CMU_CALCTRL_CONT_MASK 0x100UL /**< Bit mask for CMU_CONT */ #define _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ #define CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_CALCTRL */ #define _CMU_CALCTRL_PRSUPSEL_SHIFT 16 /**< Shift value for CMU_PRSUPSEL */ #define _CMU_CALCTRL_PRSUPSEL_MASK 0xF0000UL /**< Bit mask for CMU_PRSUPSEL */ #define _CMU_CALCTRL_PRSUPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ #define _CMU_CALCTRL_PRSUPSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for CMU_CALCTRL */ #define _CMU_CALCTRL_PRSUPSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for CMU_CALCTRL */ #define _CMU_CALCTRL_PRSUPSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for CMU_CALCTRL */ #define _CMU_CALCTRL_PRSUPSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for CMU_CALCTRL */ #define _CMU_CALCTRL_PRSUPSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for CMU_CALCTRL */ #define _CMU_CALCTRL_PRSUPSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for CMU_CALCTRL */ #define _CMU_CALCTRL_PRSUPSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for CMU_CALCTRL */ #define _CMU_CALCTRL_PRSUPSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for CMU_CALCTRL */ #define _CMU_CALCTRL_PRSUPSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for CMU_CALCTRL */ #define _CMU_CALCTRL_PRSUPSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for CMU_CALCTRL */ #define _CMU_CALCTRL_PRSUPSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for CMU_CALCTRL */ #define _CMU_CALCTRL_PRSUPSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for CMU_CALCTRL */ #define CMU_CALCTRL_PRSUPSEL_DEFAULT (_CMU_CALCTRL_PRSUPSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CALCTRL */ #define CMU_CALCTRL_PRSUPSEL_PRSCH0 (_CMU_CALCTRL_PRSUPSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for CMU_CALCTRL */ #define CMU_CALCTRL_PRSUPSEL_PRSCH1 (_CMU_CALCTRL_PRSUPSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for CMU_CALCTRL */ #define CMU_CALCTRL_PRSUPSEL_PRSCH2 (_CMU_CALCTRL_PRSUPSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for CMU_CALCTRL */ #define CMU_CALCTRL_PRSUPSEL_PRSCH3 (_CMU_CALCTRL_PRSUPSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for CMU_CALCTRL */ #define CMU_CALCTRL_PRSUPSEL_PRSCH4 (_CMU_CALCTRL_PRSUPSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for CMU_CALCTRL */ #define CMU_CALCTRL_PRSUPSEL_PRSCH5 (_CMU_CALCTRL_PRSUPSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for CMU_CALCTRL */ #define CMU_CALCTRL_PRSUPSEL_PRSCH6 (_CMU_CALCTRL_PRSUPSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for CMU_CALCTRL */ #define CMU_CALCTRL_PRSUPSEL_PRSCH7 (_CMU_CALCTRL_PRSUPSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for CMU_CALCTRL */ #define CMU_CALCTRL_PRSUPSEL_PRSCH8 (_CMU_CALCTRL_PRSUPSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for CMU_CALCTRL */ #define CMU_CALCTRL_PRSUPSEL_PRSCH9 (_CMU_CALCTRL_PRSUPSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for CMU_CALCTRL */ #define CMU_CALCTRL_PRSUPSEL_PRSCH10 (_CMU_CALCTRL_PRSUPSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for CMU_CALCTRL */ #define CMU_CALCTRL_PRSUPSEL_PRSCH11 (_CMU_CALCTRL_PRSUPSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for CMU_CALCTRL */ #define _CMU_CALCTRL_PRSDOWNSEL_SHIFT 24 /**< Shift value for CMU_PRSDOWNSEL */ #define _CMU_CALCTRL_PRSDOWNSEL_MASK 0xF000000UL /**< Bit mask for CMU_PRSDOWNSEL */ #define _CMU_CALCTRL_PRSDOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for CMU_CALCTRL */ #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for CMU_CALCTRL */ #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for CMU_CALCTRL */ #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for CMU_CALCTRL */ #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for CMU_CALCTRL */ #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for CMU_CALCTRL */ #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for CMU_CALCTRL */ #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for CMU_CALCTRL */ #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for CMU_CALCTRL */ #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for CMU_CALCTRL */ #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for CMU_CALCTRL */ #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for CMU_CALCTRL */ #define CMU_CALCTRL_PRSDOWNSEL_DEFAULT (_CMU_CALCTRL_PRSDOWNSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_CALCTRL */ #define CMU_CALCTRL_PRSDOWNSEL_PRSCH0 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH0 << 24) /**< Shifted mode PRSCH0 for CMU_CALCTRL */ #define CMU_CALCTRL_PRSDOWNSEL_PRSCH1 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH1 << 24) /**< Shifted mode PRSCH1 for CMU_CALCTRL */ #define CMU_CALCTRL_PRSDOWNSEL_PRSCH2 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH2 << 24) /**< Shifted mode PRSCH2 for CMU_CALCTRL */ #define CMU_CALCTRL_PRSDOWNSEL_PRSCH3 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH3 << 24) /**< Shifted mode PRSCH3 for CMU_CALCTRL */ #define CMU_CALCTRL_PRSDOWNSEL_PRSCH4 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH4 << 24) /**< Shifted mode PRSCH4 for CMU_CALCTRL */ #define CMU_CALCTRL_PRSDOWNSEL_PRSCH5 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH5 << 24) /**< Shifted mode PRSCH5 for CMU_CALCTRL */ #define CMU_CALCTRL_PRSDOWNSEL_PRSCH6 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH6 << 24) /**< Shifted mode PRSCH6 for CMU_CALCTRL */ #define CMU_CALCTRL_PRSDOWNSEL_PRSCH7 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH7 << 24) /**< Shifted mode PRSCH7 for CMU_CALCTRL */ #define CMU_CALCTRL_PRSDOWNSEL_PRSCH8 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH8 << 24) /**< Shifted mode PRSCH8 for CMU_CALCTRL */ #define CMU_CALCTRL_PRSDOWNSEL_PRSCH9 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH9 << 24) /**< Shifted mode PRSCH9 for CMU_CALCTRL */ #define CMU_CALCTRL_PRSDOWNSEL_PRSCH10 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH10 << 24) /**< Shifted mode PRSCH10 for CMU_CALCTRL */ #define CMU_CALCTRL_PRSDOWNSEL_PRSCH11 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH11 << 24) /**< Shifted mode PRSCH11 for CMU_CALCTRL */ /* Bit fields for CMU CALCNT */ #define _CMU_CALCNT_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCNT */ #define _CMU_CALCNT_MASK 0x000FFFFFUL /**< Mask for CMU_CALCNT */ #define _CMU_CALCNT_CALCNT_SHIFT 0 /**< Shift value for CMU_CALCNT */ #define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL /**< Bit mask for CMU_CALCNT */ #define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCNT */ #define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCNT */ /* Bit fields for CMU OSCENCMD */ #define _CMU_OSCENCMD_RESETVALUE 0x00000000UL /**< Default value for CMU_OSCENCMD */ #define _CMU_OSCENCMD_MASK 0x000033FFUL /**< Mask for CMU_OSCENCMD */ #define CMU_OSCENCMD_HFRCOEN (0x1UL << 0) /**< HFRCO Enable */ #define _CMU_OSCENCMD_HFRCOEN_SHIFT 0 /**< Shift value for CMU_HFRCOEN */ #define _CMU_OSCENCMD_HFRCOEN_MASK 0x1UL /**< Bit mask for CMU_HFRCOEN */ #define _CMU_OSCENCMD_HFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ #define CMU_OSCENCMD_HFRCOEN_DEFAULT (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ #define CMU_OSCENCMD_HFRCODIS (0x1UL << 1) /**< HFRCO Disable */ #define _CMU_OSCENCMD_HFRCODIS_SHIFT 1 /**< Shift value for CMU_HFRCODIS */ #define _CMU_OSCENCMD_HFRCODIS_MASK 0x2UL /**< Bit mask for CMU_HFRCODIS */ #define _CMU_OSCENCMD_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ #define CMU_OSCENCMD_HFRCODIS_DEFAULT (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ #define CMU_OSCENCMD_HFXOEN (0x1UL << 2) /**< HFXO Enable */ #define _CMU_OSCENCMD_HFXOEN_SHIFT 2 /**< Shift value for CMU_HFXOEN */ #define _CMU_OSCENCMD_HFXOEN_MASK 0x4UL /**< Bit mask for CMU_HFXOEN */ #define _CMU_OSCENCMD_HFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ #define CMU_OSCENCMD_HFXOEN_DEFAULT (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ #define CMU_OSCENCMD_HFXODIS (0x1UL << 3) /**< HFXO Disable */ #define _CMU_OSCENCMD_HFXODIS_SHIFT 3 /**< Shift value for CMU_HFXODIS */ #define _CMU_OSCENCMD_HFXODIS_MASK 0x8UL /**< Bit mask for CMU_HFXODIS */ #define _CMU_OSCENCMD_HFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ #define CMU_OSCENCMD_HFXODIS_DEFAULT (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ #define CMU_OSCENCMD_AUXHFRCOEN (0x1UL << 4) /**< AUXHFRCO Enable */ #define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT 4 /**< Shift value for CMU_AUXHFRCOEN */ #define _CMU_OSCENCMD_AUXHFRCOEN_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOEN */ #define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ #define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ #define CMU_OSCENCMD_AUXHFRCODIS (0x1UL << 5) /**< AUXHFRCO Disable */ #define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT 5 /**< Shift value for CMU_AUXHFRCODIS */ #define _CMU_OSCENCMD_AUXHFRCODIS_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCODIS */ #define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ #define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ #define CMU_OSCENCMD_LFRCOEN (0x1UL << 6) /**< LFRCO Enable */ #define _CMU_OSCENCMD_LFRCOEN_SHIFT 6 /**< Shift value for CMU_LFRCOEN */ #define _CMU_OSCENCMD_LFRCOEN_MASK 0x40UL /**< Bit mask for CMU_LFRCOEN */ #define _CMU_OSCENCMD_LFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ #define CMU_OSCENCMD_LFRCOEN_DEFAULT (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ #define CMU_OSCENCMD_LFRCODIS (0x1UL << 7) /**< LFRCO Disable */ #define _CMU_OSCENCMD_LFRCODIS_SHIFT 7 /**< Shift value for CMU_LFRCODIS */ #define _CMU_OSCENCMD_LFRCODIS_MASK 0x80UL /**< Bit mask for CMU_LFRCODIS */ #define _CMU_OSCENCMD_LFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ #define CMU_OSCENCMD_LFRCODIS_DEFAULT (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ #define CMU_OSCENCMD_LFXOEN (0x1UL << 8) /**< LFXO Enable */ #define _CMU_OSCENCMD_LFXOEN_SHIFT 8 /**< Shift value for CMU_LFXOEN */ #define _CMU_OSCENCMD_LFXOEN_MASK 0x100UL /**< Bit mask for CMU_LFXOEN */ #define _CMU_OSCENCMD_LFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ #define CMU_OSCENCMD_LFXOEN_DEFAULT (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ #define CMU_OSCENCMD_LFXODIS (0x1UL << 9) /**< LFXO Disable */ #define _CMU_OSCENCMD_LFXODIS_SHIFT 9 /**< Shift value for CMU_LFXODIS */ #define _CMU_OSCENCMD_LFXODIS_MASK 0x200UL /**< Bit mask for CMU_LFXODIS */ #define _CMU_OSCENCMD_LFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ #define CMU_OSCENCMD_LFXODIS_DEFAULT (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ #define CMU_OSCENCMD_DPLLEN (0x1UL << 12) /**< DPLL Enable */ #define _CMU_OSCENCMD_DPLLEN_SHIFT 12 /**< Shift value for CMU_DPLLEN */ #define _CMU_OSCENCMD_DPLLEN_MASK 0x1000UL /**< Bit mask for CMU_DPLLEN */ #define _CMU_OSCENCMD_DPLLEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ #define CMU_OSCENCMD_DPLLEN_DEFAULT (_CMU_OSCENCMD_DPLLEN_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ #define CMU_OSCENCMD_DPLLDIS (0x1UL << 13) /**< DPLL Disable */ #define _CMU_OSCENCMD_DPLLDIS_SHIFT 13 /**< Shift value for CMU_DPLLDIS */ #define _CMU_OSCENCMD_DPLLDIS_MASK 0x2000UL /**< Bit mask for CMU_DPLLDIS */ #define _CMU_OSCENCMD_DPLLDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ #define CMU_OSCENCMD_DPLLDIS_DEFAULT (_CMU_OSCENCMD_DPLLDIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ /* Bit fields for CMU CMD */ #define _CMU_CMD_RESETVALUE 0x00000000UL /**< Default value for CMU_CMD */ #define _CMU_CMD_MASK 0x00000033UL /**< Mask for CMU_CMD */ #define CMU_CMD_CALSTART (0x1UL << 0) /**< Calibration Start */ #define _CMU_CMD_CALSTART_SHIFT 0 /**< Shift value for CMU_CALSTART */ #define _CMU_CMD_CALSTART_MASK 0x1UL /**< Bit mask for CMU_CALSTART */ #define _CMU_CMD_CALSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ #define CMU_CMD_CALSTART_DEFAULT (_CMU_CMD_CALSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CMD */ #define CMU_CMD_CALSTOP (0x1UL << 1) /**< Calibration Stop */ #define _CMU_CMD_CALSTOP_SHIFT 1 /**< Shift value for CMU_CALSTOP */ #define _CMU_CMD_CALSTOP_MASK 0x2UL /**< Bit mask for CMU_CALSTOP */ #define _CMU_CMD_CALSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ #define CMU_CMD_CALSTOP_DEFAULT (_CMU_CMD_CALSTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_CMD */ #define CMU_CMD_HFXOPEAKDETSTART (0x1UL << 4) /**< HFXO Peak Detection Start */ #define _CMU_CMD_HFXOPEAKDETSTART_SHIFT 4 /**< Shift value for CMU_HFXOPEAKDETSTART */ #define _CMU_CMD_HFXOPEAKDETSTART_MASK 0x10UL /**< Bit mask for CMU_HFXOPEAKDETSTART */ #define _CMU_CMD_HFXOPEAKDETSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ #define CMU_CMD_HFXOPEAKDETSTART_DEFAULT (_CMU_CMD_HFXOPEAKDETSTART_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CMD */ #define CMU_CMD_HFXOSHUNTOPTSTART (0x1UL << 5) /**< HFXO Shunt Current Optimization Start */ #define _CMU_CMD_HFXOSHUNTOPTSTART_SHIFT 5 /**< Shift value for CMU_HFXOSHUNTOPTSTART */ #define _CMU_CMD_HFXOSHUNTOPTSTART_MASK 0x20UL /**< Bit mask for CMU_HFXOSHUNTOPTSTART */ #define _CMU_CMD_HFXOSHUNTOPTSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ #define CMU_CMD_HFXOSHUNTOPTSTART_DEFAULT (_CMU_CMD_HFXOSHUNTOPTSTART_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CMD */ /* Bit fields for CMU DBGCLKSEL */ #define _CMU_DBGCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_DBGCLKSEL */ #define _CMU_DBGCLKSEL_MASK 0x00000001UL /**< Mask for CMU_DBGCLKSEL */ #define _CMU_DBGCLKSEL_DBG_SHIFT 0 /**< Shift value for CMU_DBG */ #define _CMU_DBGCLKSEL_DBG_MASK 0x1UL /**< Bit mask for CMU_DBG */ #define _CMU_DBGCLKSEL_DBG_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DBGCLKSEL */ #define _CMU_DBGCLKSEL_DBG_AUXHFRCO 0x00000000UL /**< Mode AUXHFRCO for CMU_DBGCLKSEL */ #define _CMU_DBGCLKSEL_DBG_HFCLK 0x00000001UL /**< Mode HFCLK for CMU_DBGCLKSEL */ #define CMU_DBGCLKSEL_DBG_DEFAULT (_CMU_DBGCLKSEL_DBG_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DBGCLKSEL */ #define CMU_DBGCLKSEL_DBG_AUXHFRCO (_CMU_DBGCLKSEL_DBG_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_DBGCLKSEL */ #define CMU_DBGCLKSEL_DBG_HFCLK (_CMU_DBGCLKSEL_DBG_HFCLK << 0) /**< Shifted mode HFCLK for CMU_DBGCLKSEL */ /* Bit fields for CMU HFCLKSEL */ #define _CMU_HFCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCLKSEL */ #define _CMU_HFCLKSEL_MASK 0x00000007UL /**< Mask for CMU_HFCLKSEL */ #define _CMU_HFCLKSEL_HF_SHIFT 0 /**< Shift value for CMU_HF */ #define _CMU_HFCLKSEL_HF_MASK 0x7UL /**< Bit mask for CMU_HF */ #define _CMU_HFCLKSEL_HF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCLKSEL */ #define _CMU_HFCLKSEL_HF_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_HFCLKSEL */ #define _CMU_HFCLKSEL_HF_HFXO 0x00000002UL /**< Mode HFXO for CMU_HFCLKSEL */ #define _CMU_HFCLKSEL_HF_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_HFCLKSEL */ #define _CMU_HFCLKSEL_HF_LFXO 0x00000004UL /**< Mode LFXO for CMU_HFCLKSEL */ #define _CMU_HFCLKSEL_HF_HFRCODIV2 0x00000005UL /**< Mode HFRCODIV2 for CMU_HFCLKSEL */ #define _CMU_HFCLKSEL_HF_CLKIN0 0x00000007UL /**< Mode CLKIN0 for CMU_HFCLKSEL */ #define CMU_HFCLKSEL_HF_DEFAULT (_CMU_HFCLKSEL_HF_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCLKSEL */ #define CMU_HFCLKSEL_HF_HFRCO (_CMU_HFCLKSEL_HF_HFRCO << 0) /**< Shifted mode HFRCO for CMU_HFCLKSEL */ #define CMU_HFCLKSEL_HF_HFXO (_CMU_HFCLKSEL_HF_HFXO << 0) /**< Shifted mode HFXO for CMU_HFCLKSEL */ #define CMU_HFCLKSEL_HF_LFRCO (_CMU_HFCLKSEL_HF_LFRCO << 0) /**< Shifted mode LFRCO for CMU_HFCLKSEL */ #define CMU_HFCLKSEL_HF_LFXO (_CMU_HFCLKSEL_HF_LFXO << 0) /**< Shifted mode LFXO for CMU_HFCLKSEL */ #define CMU_HFCLKSEL_HF_HFRCODIV2 (_CMU_HFCLKSEL_HF_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_HFCLKSEL */ #define CMU_HFCLKSEL_HF_CLKIN0 (_CMU_HFCLKSEL_HF_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_HFCLKSEL */ /* Bit fields for CMU LFACLKSEL */ #define _CMU_LFACLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKSEL */ #define _CMU_LFACLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFACLKSEL */ #define _CMU_LFACLKSEL_LFA_SHIFT 0 /**< Shift value for CMU_LFA */ #define _CMU_LFACLKSEL_LFA_MASK 0x7UL /**< Bit mask for CMU_LFA */ #define _CMU_LFACLKSEL_LFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKSEL */ #define _CMU_LFACLKSEL_LFA_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFACLKSEL */ #define _CMU_LFACLKSEL_LFA_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFACLKSEL */ #define _CMU_LFACLKSEL_LFA_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFACLKSEL */ #define _CMU_LFACLKSEL_LFA_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFACLKSEL */ #define CMU_LFACLKSEL_LFA_DEFAULT (_CMU_LFACLKSEL_LFA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKSEL */ #define CMU_LFACLKSEL_LFA_DISABLED (_CMU_LFACLKSEL_LFA_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFACLKSEL */ #define CMU_LFACLKSEL_LFA_LFRCO (_CMU_LFACLKSEL_LFA_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFACLKSEL */ #define CMU_LFACLKSEL_LFA_LFXO (_CMU_LFACLKSEL_LFA_LFXO << 0) /**< Shifted mode LFXO for CMU_LFACLKSEL */ #define CMU_LFACLKSEL_LFA_ULFRCO (_CMU_LFACLKSEL_LFA_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFACLKSEL */ /* Bit fields for CMU LFBCLKSEL */ #define _CMU_LFBCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKSEL */ #define _CMU_LFBCLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFBCLKSEL */ #define _CMU_LFBCLKSEL_LFB_SHIFT 0 /**< Shift value for CMU_LFB */ #define _CMU_LFBCLKSEL_LFB_MASK 0x7UL /**< Bit mask for CMU_LFB */ #define _CMU_LFBCLKSEL_LFB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKSEL */ #define _CMU_LFBCLKSEL_LFB_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFBCLKSEL */ #define _CMU_LFBCLKSEL_LFB_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFBCLKSEL */ #define _CMU_LFBCLKSEL_LFB_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFBCLKSEL */ #define _CMU_LFBCLKSEL_LFB_HFCLKLE 0x00000003UL /**< Mode HFCLKLE for CMU_LFBCLKSEL */ #define _CMU_LFBCLKSEL_LFB_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFBCLKSEL */ #define CMU_LFBCLKSEL_LFB_DEFAULT (_CMU_LFBCLKSEL_LFB_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKSEL */ #define CMU_LFBCLKSEL_LFB_DISABLED (_CMU_LFBCLKSEL_LFB_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFBCLKSEL */ #define CMU_LFBCLKSEL_LFB_LFRCO (_CMU_LFBCLKSEL_LFB_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFBCLKSEL */ #define CMU_LFBCLKSEL_LFB_LFXO (_CMU_LFBCLKSEL_LFB_LFXO << 0) /**< Shifted mode LFXO for CMU_LFBCLKSEL */ #define CMU_LFBCLKSEL_LFB_HFCLKLE (_CMU_LFBCLKSEL_LFB_HFCLKLE << 0) /**< Shifted mode HFCLKLE for CMU_LFBCLKSEL */ #define CMU_LFBCLKSEL_LFB_ULFRCO (_CMU_LFBCLKSEL_LFB_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFBCLKSEL */ /* Bit fields for CMU LFECLKSEL */ #define _CMU_LFECLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFECLKSEL */ #define _CMU_LFECLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFECLKSEL */ #define _CMU_LFECLKSEL_LFE_SHIFT 0 /**< Shift value for CMU_LFE */ #define _CMU_LFECLKSEL_LFE_MASK 0x7UL /**< Bit mask for CMU_LFE */ #define _CMU_LFECLKSEL_LFE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFECLKSEL */ #define _CMU_LFECLKSEL_LFE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFECLKSEL */ #define _CMU_LFECLKSEL_LFE_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFECLKSEL */ #define _CMU_LFECLKSEL_LFE_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFECLKSEL */ #define _CMU_LFECLKSEL_LFE_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFECLKSEL */ #define CMU_LFECLKSEL_LFE_DEFAULT (_CMU_LFECLKSEL_LFE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFECLKSEL */ #define CMU_LFECLKSEL_LFE_DISABLED (_CMU_LFECLKSEL_LFE_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFECLKSEL */ #define CMU_LFECLKSEL_LFE_LFRCO (_CMU_LFECLKSEL_LFE_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFECLKSEL */ #define CMU_LFECLKSEL_LFE_LFXO (_CMU_LFECLKSEL_LFE_LFXO << 0) /**< Shifted mode LFXO for CMU_LFECLKSEL */ #define CMU_LFECLKSEL_LFE_ULFRCO (_CMU_LFECLKSEL_LFE_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFECLKSEL */ /* Bit fields for CMU STATUS */ #define _CMU_STATUS_RESETVALUE 0x00010003UL /**< Default value for CMU_STATUS */ #define _CMU_STATUS_MASK 0x07E133FFUL /**< Mask for CMU_STATUS */ #define CMU_STATUS_HFRCOENS (0x1UL << 0) /**< HFRCO Enable Status */ #define _CMU_STATUS_HFRCOENS_SHIFT 0 /**< Shift value for CMU_HFRCOENS */ #define _CMU_STATUS_HFRCOENS_MASK 0x1UL /**< Bit mask for CMU_HFRCOENS */ #define _CMU_STATUS_HFRCOENS_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ #define CMU_STATUS_HFRCOENS_DEFAULT (_CMU_STATUS_HFRCOENS_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_STATUS */ #define CMU_STATUS_HFRCORDY (0x1UL << 1) /**< HFRCO Ready */ #define _CMU_STATUS_HFRCORDY_SHIFT 1 /**< Shift value for CMU_HFRCORDY */ #define _CMU_STATUS_HFRCORDY_MASK 0x2UL /**< Bit mask for CMU_HFRCORDY */ #define _CMU_STATUS_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ #define CMU_STATUS_HFRCORDY_DEFAULT (_CMU_STATUS_HFRCORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_STATUS */ #define CMU_STATUS_HFXOENS (0x1UL << 2) /**< HFXO Enable Status */ #define _CMU_STATUS_HFXOENS_SHIFT 2 /**< Shift value for CMU_HFXOENS */ #define _CMU_STATUS_HFXOENS_MASK 0x4UL /**< Bit mask for CMU_HFXOENS */ #define _CMU_STATUS_HFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ #define CMU_STATUS_HFXOENS_DEFAULT (_CMU_STATUS_HFXOENS_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_STATUS */ #define CMU_STATUS_HFXORDY (0x1UL << 3) /**< HFXO Ready */ #define _CMU_STATUS_HFXORDY_SHIFT 3 /**< Shift value for CMU_HFXORDY */ #define _CMU_STATUS_HFXORDY_MASK 0x8UL /**< Bit mask for CMU_HFXORDY */ #define _CMU_STATUS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ #define CMU_STATUS_HFXORDY_DEFAULT (_CMU_STATUS_HFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_STATUS */ #define CMU_STATUS_AUXHFRCOENS (0x1UL << 4) /**< AUXHFRCO Enable Status */ #define _CMU_STATUS_AUXHFRCOENS_SHIFT 4 /**< Shift value for CMU_AUXHFRCOENS */ #define _CMU_STATUS_AUXHFRCOENS_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOENS */ #define _CMU_STATUS_AUXHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ #define CMU_STATUS_AUXHFRCOENS_DEFAULT (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_STATUS */ #define CMU_STATUS_AUXHFRCORDY (0x1UL << 5) /**< AUXHFRCO Ready */ #define _CMU_STATUS_AUXHFRCORDY_SHIFT 5 /**< Shift value for CMU_AUXHFRCORDY */ #define _CMU_STATUS_AUXHFRCORDY_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCORDY */ #define _CMU_STATUS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ #define CMU_STATUS_AUXHFRCORDY_DEFAULT (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_STATUS */ #define CMU_STATUS_LFRCOENS (0x1UL << 6) /**< LFRCO Enable Status */ #define _CMU_STATUS_LFRCOENS_SHIFT 6 /**< Shift value for CMU_LFRCOENS */ #define _CMU_STATUS_LFRCOENS_MASK 0x40UL /**< Bit mask for CMU_LFRCOENS */ #define _CMU_STATUS_LFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ #define CMU_STATUS_LFRCOENS_DEFAULT (_CMU_STATUS_LFRCOENS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_STATUS */ #define CMU_STATUS_LFRCORDY (0x1UL << 7) /**< LFRCO Ready */ #define _CMU_STATUS_LFRCORDY_SHIFT 7 /**< Shift value for CMU_LFRCORDY */ #define _CMU_STATUS_LFRCORDY_MASK 0x80UL /**< Bit mask for CMU_LFRCORDY */ #define _CMU_STATUS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ #define CMU_STATUS_LFRCORDY_DEFAULT (_CMU_STATUS_LFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_STATUS */ #define CMU_STATUS_LFXOENS (0x1UL << 8) /**< LFXO Enable Status */ #define _CMU_STATUS_LFXOENS_SHIFT 8 /**< Shift value for CMU_LFXOENS */ #define _CMU_STATUS_LFXOENS_MASK 0x100UL /**< Bit mask for CMU_LFXOENS */ #define _CMU_STATUS_LFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ #define CMU_STATUS_LFXOENS_DEFAULT (_CMU_STATUS_LFXOENS_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_STATUS */ #define CMU_STATUS_LFXORDY (0x1UL << 9) /**< LFXO Ready */ #define _CMU_STATUS_LFXORDY_SHIFT 9 /**< Shift value for CMU_LFXORDY */ #define _CMU_STATUS_LFXORDY_MASK 0x200UL /**< Bit mask for CMU_LFXORDY */ #define _CMU_STATUS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ #define CMU_STATUS_LFXORDY_DEFAULT (_CMU_STATUS_LFXORDY_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_STATUS */ #define CMU_STATUS_DPLLENS (0x1UL << 12) /**< DPLL Enable Status */ #define _CMU_STATUS_DPLLENS_SHIFT 12 /**< Shift value for CMU_DPLLENS */ #define _CMU_STATUS_DPLLENS_MASK 0x1000UL /**< Bit mask for CMU_DPLLENS */ #define _CMU_STATUS_DPLLENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ #define CMU_STATUS_DPLLENS_DEFAULT (_CMU_STATUS_DPLLENS_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_STATUS */ #define CMU_STATUS_DPLLRDY (0x1UL << 13) /**< DPLL Ready */ #define _CMU_STATUS_DPLLRDY_SHIFT 13 /**< Shift value for CMU_DPLLRDY */ #define _CMU_STATUS_DPLLRDY_MASK 0x2000UL /**< Bit mask for CMU_DPLLRDY */ #define _CMU_STATUS_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ #define CMU_STATUS_DPLLRDY_DEFAULT (_CMU_STATUS_DPLLRDY_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_STATUS */ #define CMU_STATUS_CALRDY (0x1UL << 16) /**< Calibration Ready */ #define _CMU_STATUS_CALRDY_SHIFT 16 /**< Shift value for CMU_CALRDY */ #define _CMU_STATUS_CALRDY_MASK 0x10000UL /**< Bit mask for CMU_CALRDY */ #define _CMU_STATUS_CALRDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ #define CMU_STATUS_CALRDY_DEFAULT (_CMU_STATUS_CALRDY_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_STATUS */ #define CMU_STATUS_HFXOREQ (0x1UL << 21) /**< HFXO is Required By Hardware */ #define _CMU_STATUS_HFXOREQ_SHIFT 21 /**< Shift value for CMU_HFXOREQ */ #define _CMU_STATUS_HFXOREQ_MASK 0x200000UL /**< Bit mask for CMU_HFXOREQ */ #define _CMU_STATUS_HFXOREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ #define CMU_STATUS_HFXOREQ_DEFAULT (_CMU_STATUS_HFXOREQ_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_STATUS */ #define CMU_STATUS_HFXOPEAKDETRDY (0x1UL << 22) /**< HFXO Peak Detection Ready */ #define _CMU_STATUS_HFXOPEAKDETRDY_SHIFT 22 /**< Shift value for CMU_HFXOPEAKDETRDY */ #define _CMU_STATUS_HFXOPEAKDETRDY_MASK 0x400000UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ #define _CMU_STATUS_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ #define CMU_STATUS_HFXOPEAKDETRDY_DEFAULT (_CMU_STATUS_HFXOPEAKDETRDY_DEFAULT << 22) /**< Shifted mode DEFAULT for CMU_STATUS */ #define CMU_STATUS_HFXOSHUNTOPTRDY (0x1UL << 23) /**< HFXO Shunt Current Optimization Ready */ #define _CMU_STATUS_HFXOSHUNTOPTRDY_SHIFT 23 /**< Shift value for CMU_HFXOSHUNTOPTRDY */ #define _CMU_STATUS_HFXOSHUNTOPTRDY_MASK 0x800000UL /**< Bit mask for CMU_HFXOSHUNTOPTRDY */ #define _CMU_STATUS_HFXOSHUNTOPTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ #define CMU_STATUS_HFXOSHUNTOPTRDY_DEFAULT (_CMU_STATUS_HFXOSHUNTOPTRDY_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_STATUS */ #define CMU_STATUS_HFXOAMPHIGH (0x1UL << 24) /**< HFXO Oscillation Amplitude is Too High */ #define _CMU_STATUS_HFXOAMPHIGH_SHIFT 24 /**< Shift value for CMU_HFXOAMPHIGH */ #define _CMU_STATUS_HFXOAMPHIGH_MASK 0x1000000UL /**< Bit mask for CMU_HFXOAMPHIGH */ #define _CMU_STATUS_HFXOAMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ #define CMU_STATUS_HFXOAMPHIGH_DEFAULT (_CMU_STATUS_HFXOAMPHIGH_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_STATUS */ #define CMU_STATUS_HFXOAMPLOW (0x1UL << 25) /**< HFXO Amplitude Tuning Value Too Low */ #define _CMU_STATUS_HFXOAMPLOW_SHIFT 25 /**< Shift value for CMU_HFXOAMPLOW */ #define _CMU_STATUS_HFXOAMPLOW_MASK 0x2000000UL /**< Bit mask for CMU_HFXOAMPLOW */ #define _CMU_STATUS_HFXOAMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ #define CMU_STATUS_HFXOAMPLOW_DEFAULT (_CMU_STATUS_HFXOAMPLOW_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_STATUS */ #define CMU_STATUS_HFXOREGILOW (0x1UL << 26) /**< HFXO Regulator Shunt Current Too Low */ #define _CMU_STATUS_HFXOREGILOW_SHIFT 26 /**< Shift value for CMU_HFXOREGILOW */ #define _CMU_STATUS_HFXOREGILOW_MASK 0x4000000UL /**< Bit mask for CMU_HFXOREGILOW */ #define _CMU_STATUS_HFXOREGILOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ #define CMU_STATUS_HFXOREGILOW_DEFAULT (_CMU_STATUS_HFXOREGILOW_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_STATUS */ /* Bit fields for CMU HFCLKSTATUS */ #define _CMU_HFCLKSTATUS_RESETVALUE 0x00000001UL /**< Default value for CMU_HFCLKSTATUS */ #define _CMU_HFCLKSTATUS_MASK 0x00000007UL /**< Mask for CMU_HFCLKSTATUS */ #define _CMU_HFCLKSTATUS_SELECTED_SHIFT 0 /**< Shift value for CMU_SELECTED */ #define _CMU_HFCLKSTATUS_SELECTED_MASK 0x7UL /**< Bit mask for CMU_SELECTED */ #define _CMU_HFCLKSTATUS_SELECTED_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFCLKSTATUS */ #define _CMU_HFCLKSTATUS_SELECTED_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_HFCLKSTATUS */ #define _CMU_HFCLKSTATUS_SELECTED_HFXO 0x00000002UL /**< Mode HFXO for CMU_HFCLKSTATUS */ #define _CMU_HFCLKSTATUS_SELECTED_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_HFCLKSTATUS */ #define _CMU_HFCLKSTATUS_SELECTED_LFXO 0x00000004UL /**< Mode LFXO for CMU_HFCLKSTATUS */ #define _CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 0x00000005UL /**< Mode HFRCODIV2 for CMU_HFCLKSTATUS */ #define _CMU_HFCLKSTATUS_SELECTED_CLKIN0 0x00000007UL /**< Mode CLKIN0 for CMU_HFCLKSTATUS */ #define CMU_HFCLKSTATUS_SELECTED_DEFAULT (_CMU_HFCLKSTATUS_SELECTED_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCLKSTATUS */ #define CMU_HFCLKSTATUS_SELECTED_HFRCO (_CMU_HFCLKSTATUS_SELECTED_HFRCO << 0) /**< Shifted mode HFRCO for CMU_HFCLKSTATUS */ #define CMU_HFCLKSTATUS_SELECTED_HFXO (_CMU_HFCLKSTATUS_SELECTED_HFXO << 0) /**< Shifted mode HFXO for CMU_HFCLKSTATUS */ #define CMU_HFCLKSTATUS_SELECTED_LFRCO (_CMU_HFCLKSTATUS_SELECTED_LFRCO << 0) /**< Shifted mode LFRCO for CMU_HFCLKSTATUS */ #define CMU_HFCLKSTATUS_SELECTED_LFXO (_CMU_HFCLKSTATUS_SELECTED_LFXO << 0) /**< Shifted mode LFXO for CMU_HFCLKSTATUS */ #define CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 (_CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_HFCLKSTATUS */ #define CMU_HFCLKSTATUS_SELECTED_CLKIN0 (_CMU_HFCLKSTATUS_SELECTED_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_HFCLKSTATUS */ /* Bit fields for CMU HFXOTRIMSTATUS */ #define _CMU_HFXOTRIMSTATUS_RESETVALUE 0x00000500UL /**< Default value for CMU_HFXOTRIMSTATUS */ #define _CMU_HFXOTRIMSTATUS_MASK 0x000007FFUL /**< Mask for CMU_HFXOTRIMSTATUS */ #define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ #define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_MASK 0x7FUL /**< Bit mask for CMU_IBTRIMXOCORE */ #define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ #define CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT (_CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ #define _CMU_HFXOTRIMSTATUS_REGISH_SHIFT 7 /**< Shift value for CMU_REGISH */ #define _CMU_HFXOTRIMSTATUS_REGISH_MASK 0x780UL /**< Bit mask for CMU_REGISH */ #define _CMU_HFXOTRIMSTATUS_REGISH_DEFAULT 0x0000000AUL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ #define CMU_HFXOTRIMSTATUS_REGISH_DEFAULT (_CMU_HFXOTRIMSTATUS_REGISH_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ /* Bit fields for CMU IF */ #define _CMU_IF_RESETVALUE 0x00000001UL /**< Default value for CMU_IF */ #define _CMU_IF_MASK 0x8003FF7FUL /**< Mask for CMU_IF */ #define CMU_IF_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag */ #define _CMU_IF_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ #define _CMU_IF_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ #define _CMU_IF_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_IF */ #define CMU_IF_HFRCORDY_DEFAULT (_CMU_IF_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IF */ #define CMU_IF_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag */ #define _CMU_IF_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ #define _CMU_IF_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ #define _CMU_IF_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ #define CMU_IF_HFXORDY_DEFAULT (_CMU_IF_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IF */ #define CMU_IF_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag */ #define _CMU_IF_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ #define _CMU_IF_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ #define _CMU_IF_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ #define CMU_IF_LFRCORDY_DEFAULT (_CMU_IF_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IF */ #define CMU_IF_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag */ #define _CMU_IF_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ #define _CMU_IF_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ #define _CMU_IF_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ #define CMU_IF_LFXORDY_DEFAULT (_CMU_IF_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IF */ #define CMU_IF_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag */ #define _CMU_IF_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ #define _CMU_IF_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ #define _CMU_IF_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ #define CMU_IF_AUXHFRCORDY_DEFAULT (_CMU_IF_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IF */ #define CMU_IF_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag */ #define _CMU_IF_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ #define _CMU_IF_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ #define _CMU_IF_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ #define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IF */ #define CMU_IF_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag */ #define _CMU_IF_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ #define _CMU_IF_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ #define _CMU_IF_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ #define CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IF */ #define CMU_IF_HFXODISERR (0x1UL << 8) /**< HFXO Disable Error Interrupt Flag */ #define _CMU_IF_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ #define _CMU_IF_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ #define _CMU_IF_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ #define CMU_IF_HFXODISERR_DEFAULT (_CMU_IF_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IF */ #define CMU_IF_HFXOAUTOSW (0x1UL << 9) /**< HFXO Automatic Switch Interrupt Flag */ #define _CMU_IF_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ #define _CMU_IF_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ #define _CMU_IF_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ #define CMU_IF_HFXOAUTOSW_DEFAULT (_CMU_IF_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IF */ #define CMU_IF_HFXOPEAKDETERR (0x1UL << 10) /**< HFXO Automatic Peak Detection Error Interrupt Flag */ #define _CMU_IF_HFXOPEAKDETERR_SHIFT 10 /**< Shift value for CMU_HFXOPEAKDETERR */ #define _CMU_IF_HFXOPEAKDETERR_MASK 0x400UL /**< Bit mask for CMU_HFXOPEAKDETERR */ #define _CMU_IF_HFXOPEAKDETERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ #define CMU_IF_HFXOPEAKDETERR_DEFAULT (_CMU_IF_HFXOPEAKDETERR_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_IF */ #define CMU_IF_HFXOPEAKDETRDY (0x1UL << 11) /**< HFXO Automatic Peak Detection Ready Interrupt Flag */ #define _CMU_IF_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ #define _CMU_IF_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ #define _CMU_IF_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ #define CMU_IF_HFXOPEAKDETRDY_DEFAULT (_CMU_IF_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IF */ #define CMU_IF_HFXOSHUNTOPTRDY (0x1UL << 12) /**< HFXO Automatic Shunt Current Optimization Ready Interrupt Flag */ #define _CMU_IF_HFXOSHUNTOPTRDY_SHIFT 12 /**< Shift value for CMU_HFXOSHUNTOPTRDY */ #define _CMU_IF_HFXOSHUNTOPTRDY_MASK 0x1000UL /**< Bit mask for CMU_HFXOSHUNTOPTRDY */ #define _CMU_IF_HFXOSHUNTOPTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ #define CMU_IF_HFXOSHUNTOPTRDY_DEFAULT (_CMU_IF_HFXOSHUNTOPTRDY_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_IF */ #define CMU_IF_HFRCODIS (0x1UL << 13) /**< HFRCO Disable Interrupt Flag */ #define _CMU_IF_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ #define _CMU_IF_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ #define _CMU_IF_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ #define CMU_IF_HFRCODIS_DEFAULT (_CMU_IF_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IF */ #define CMU_IF_LFTIMEOUTERR (0x1UL << 14) /**< Low Frequency Timeout Error Interrupt Flag */ #define _CMU_IF_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ #define _CMU_IF_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ #define _CMU_IF_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ #define CMU_IF_LFTIMEOUTERR_DEFAULT (_CMU_IF_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IF */ #define CMU_IF_DPLLRDY (0x1UL << 15) /**< DPLL Lock Interrupt Flag */ #define _CMU_IF_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ #define _CMU_IF_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ #define _CMU_IF_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ #define CMU_IF_DPLLRDY_DEFAULT (_CMU_IF_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IF */ #define CMU_IF_DPLLLOCKFAILLOW (0x1UL << 16) /**< DPLL Lock Failure Low Interrupt Flag */ #define _CMU_IF_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ #define _CMU_IF_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ #define _CMU_IF_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ #define CMU_IF_DPLLLOCKFAILLOW_DEFAULT (_CMU_IF_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IF */ #define CMU_IF_DPLLLOCKFAILHIGH (0x1UL << 17) /**< DPLL Lock Failure Low Interrupt Flag */ #define _CMU_IF_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ #define _CMU_IF_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ #define _CMU_IF_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ #define CMU_IF_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IF_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IF */ #define CMU_IF_CMUERR (0x1UL << 31) /**< CMU Error Interrupt Flag */ #define _CMU_IF_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ #define _CMU_IF_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ #define _CMU_IF_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ #define CMU_IF_CMUERR_DEFAULT (_CMU_IF_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IF */ /* Bit fields for CMU IFS */ #define _CMU_IFS_RESETVALUE 0x00000000UL /**< Default value for CMU_IFS */ #define _CMU_IFS_MASK 0x8003FF7FUL /**< Mask for CMU_IFS */ #define CMU_IFS_HFRCORDY (0x1UL << 0) /**< Set HFRCORDY Interrupt Flag */ #define _CMU_IFS_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ #define _CMU_IFS_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ #define _CMU_IFS_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ #define CMU_IFS_HFRCORDY_DEFAULT (_CMU_IFS_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFS */ #define CMU_IFS_HFXORDY (0x1UL << 1) /**< Set HFXORDY Interrupt Flag */ #define _CMU_IFS_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ #define _CMU_IFS_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ #define _CMU_IFS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ #define CMU_IFS_HFXORDY_DEFAULT (_CMU_IFS_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFS */ #define CMU_IFS_LFRCORDY (0x1UL << 2) /**< Set LFRCORDY Interrupt Flag */ #define _CMU_IFS_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ #define _CMU_IFS_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ #define _CMU_IFS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ #define CMU_IFS_LFRCORDY_DEFAULT (_CMU_IFS_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFS */ #define CMU_IFS_LFXORDY (0x1UL << 3) /**< Set LFXORDY Interrupt Flag */ #define _CMU_IFS_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ #define _CMU_IFS_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ #define _CMU_IFS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ #define CMU_IFS_LFXORDY_DEFAULT (_CMU_IFS_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFS */ #define CMU_IFS_AUXHFRCORDY (0x1UL << 4) /**< Set AUXHFRCORDY Interrupt Flag */ #define _CMU_IFS_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ #define _CMU_IFS_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ #define _CMU_IFS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ #define CMU_IFS_AUXHFRCORDY_DEFAULT (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFS */ #define CMU_IFS_CALRDY (0x1UL << 5) /**< Set CALRDY Interrupt Flag */ #define _CMU_IFS_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ #define _CMU_IFS_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ #define _CMU_IFS_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ #define CMU_IFS_CALRDY_DEFAULT (_CMU_IFS_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFS */ #define CMU_IFS_CALOF (0x1UL << 6) /**< Set CALOF Interrupt Flag */ #define _CMU_IFS_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ #define _CMU_IFS_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ #define _CMU_IFS_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ #define CMU_IFS_CALOF_DEFAULT (_CMU_IFS_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFS */ #define CMU_IFS_HFXODISERR (0x1UL << 8) /**< Set HFXODISERR Interrupt Flag */ #define _CMU_IFS_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ #define _CMU_IFS_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ #define _CMU_IFS_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ #define CMU_IFS_HFXODISERR_DEFAULT (_CMU_IFS_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IFS */ #define CMU_IFS_HFXOAUTOSW (0x1UL << 9) /**< Set HFXOAUTOSW Interrupt Flag */ #define _CMU_IFS_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ #define _CMU_IFS_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ #define _CMU_IFS_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ #define CMU_IFS_HFXOAUTOSW_DEFAULT (_CMU_IFS_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IFS */ #define CMU_IFS_HFXOPEAKDETERR (0x1UL << 10) /**< Set HFXOPEAKDETERR Interrupt Flag */ #define _CMU_IFS_HFXOPEAKDETERR_SHIFT 10 /**< Shift value for CMU_HFXOPEAKDETERR */ #define _CMU_IFS_HFXOPEAKDETERR_MASK 0x400UL /**< Bit mask for CMU_HFXOPEAKDETERR */ #define _CMU_IFS_HFXOPEAKDETERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ #define CMU_IFS_HFXOPEAKDETERR_DEFAULT (_CMU_IFS_HFXOPEAKDETERR_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_IFS */ #define CMU_IFS_HFXOPEAKDETRDY (0x1UL << 11) /**< Set HFXOPEAKDETRDY Interrupt Flag */ #define _CMU_IFS_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ #define _CMU_IFS_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ #define _CMU_IFS_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ #define CMU_IFS_HFXOPEAKDETRDY_DEFAULT (_CMU_IFS_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IFS */ #define CMU_IFS_HFXOSHUNTOPTRDY (0x1UL << 12) /**< Set HFXOSHUNTOPTRDY Interrupt Flag */ #define _CMU_IFS_HFXOSHUNTOPTRDY_SHIFT 12 /**< Shift value for CMU_HFXOSHUNTOPTRDY */ #define _CMU_IFS_HFXOSHUNTOPTRDY_MASK 0x1000UL /**< Bit mask for CMU_HFXOSHUNTOPTRDY */ #define _CMU_IFS_HFXOSHUNTOPTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ #define CMU_IFS_HFXOSHUNTOPTRDY_DEFAULT (_CMU_IFS_HFXOSHUNTOPTRDY_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_IFS */ #define CMU_IFS_HFRCODIS (0x1UL << 13) /**< Set HFRCODIS Interrupt Flag */ #define _CMU_IFS_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ #define _CMU_IFS_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ #define _CMU_IFS_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ #define CMU_IFS_HFRCODIS_DEFAULT (_CMU_IFS_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IFS */ #define CMU_IFS_LFTIMEOUTERR (0x1UL << 14) /**< Set LFTIMEOUTERR Interrupt Flag */ #define _CMU_IFS_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ #define _CMU_IFS_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ #define _CMU_IFS_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ #define CMU_IFS_LFTIMEOUTERR_DEFAULT (_CMU_IFS_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IFS */ #define CMU_IFS_DPLLRDY (0x1UL << 15) /**< Set DPLLRDY Interrupt Flag */ #define _CMU_IFS_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ #define _CMU_IFS_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ #define _CMU_IFS_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ #define CMU_IFS_DPLLRDY_DEFAULT (_CMU_IFS_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IFS */ #define CMU_IFS_DPLLLOCKFAILLOW (0x1UL << 16) /**< Set DPLLLOCKFAILLOW Interrupt Flag */ #define _CMU_IFS_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ #define _CMU_IFS_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ #define _CMU_IFS_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ #define CMU_IFS_DPLLLOCKFAILLOW_DEFAULT (_CMU_IFS_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IFS */ #define CMU_IFS_DPLLLOCKFAILHIGH (0x1UL << 17) /**< Set DPLLLOCKFAILHIGH Interrupt Flag */ #define _CMU_IFS_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ #define _CMU_IFS_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ #define _CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ #define CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IFS */ #define CMU_IFS_CMUERR (0x1UL << 31) /**< Set CMUERR Interrupt Flag */ #define _CMU_IFS_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ #define _CMU_IFS_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ #define _CMU_IFS_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ #define CMU_IFS_CMUERR_DEFAULT (_CMU_IFS_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IFS */ /* Bit fields for CMU IFC */ #define _CMU_IFC_RESETVALUE 0x00000000UL /**< Default value for CMU_IFC */ #define _CMU_IFC_MASK 0x8003FF7FUL /**< Mask for CMU_IFC */ #define CMU_IFC_HFRCORDY (0x1UL << 0) /**< Clear HFRCORDY Interrupt Flag */ #define _CMU_IFC_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ #define _CMU_IFC_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ #define _CMU_IFC_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ #define CMU_IFC_HFRCORDY_DEFAULT (_CMU_IFC_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFC */ #define CMU_IFC_HFXORDY (0x1UL << 1) /**< Clear HFXORDY Interrupt Flag */ #define _CMU_IFC_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ #define _CMU_IFC_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ #define _CMU_IFC_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ #define CMU_IFC_HFXORDY_DEFAULT (_CMU_IFC_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFC */ #define CMU_IFC_LFRCORDY (0x1UL << 2) /**< Clear LFRCORDY Interrupt Flag */ #define _CMU_IFC_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ #define _CMU_IFC_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ #define _CMU_IFC_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ #define CMU_IFC_LFRCORDY_DEFAULT (_CMU_IFC_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFC */ #define CMU_IFC_LFXORDY (0x1UL << 3) /**< Clear LFXORDY Interrupt Flag */ #define _CMU_IFC_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ #define _CMU_IFC_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ #define _CMU_IFC_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ #define CMU_IFC_LFXORDY_DEFAULT (_CMU_IFC_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFC */ #define CMU_IFC_AUXHFRCORDY (0x1UL << 4) /**< Clear AUXHFRCORDY Interrupt Flag */ #define _CMU_IFC_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ #define _CMU_IFC_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ #define _CMU_IFC_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ #define CMU_IFC_AUXHFRCORDY_DEFAULT (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFC */ #define CMU_IFC_CALRDY (0x1UL << 5) /**< Clear CALRDY Interrupt Flag */ #define _CMU_IFC_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ #define _CMU_IFC_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ #define _CMU_IFC_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ #define CMU_IFC_CALRDY_DEFAULT (_CMU_IFC_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFC */ #define CMU_IFC_CALOF (0x1UL << 6) /**< Clear CALOF Interrupt Flag */ #define _CMU_IFC_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ #define _CMU_IFC_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ #define _CMU_IFC_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ #define CMU_IFC_CALOF_DEFAULT (_CMU_IFC_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFC */ #define CMU_IFC_HFXODISERR (0x1UL << 8) /**< Clear HFXODISERR Interrupt Flag */ #define _CMU_IFC_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ #define _CMU_IFC_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ #define _CMU_IFC_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ #define CMU_IFC_HFXODISERR_DEFAULT (_CMU_IFC_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IFC */ #define CMU_IFC_HFXOAUTOSW (0x1UL << 9) /**< Clear HFXOAUTOSW Interrupt Flag */ #define _CMU_IFC_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ #define _CMU_IFC_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ #define _CMU_IFC_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ #define CMU_IFC_HFXOAUTOSW_DEFAULT (_CMU_IFC_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IFC */ #define CMU_IFC_HFXOPEAKDETERR (0x1UL << 10) /**< Clear HFXOPEAKDETERR Interrupt Flag */ #define _CMU_IFC_HFXOPEAKDETERR_SHIFT 10 /**< Shift value for CMU_HFXOPEAKDETERR */ #define _CMU_IFC_HFXOPEAKDETERR_MASK 0x400UL /**< Bit mask for CMU_HFXOPEAKDETERR */ #define _CMU_IFC_HFXOPEAKDETERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ #define CMU_IFC_HFXOPEAKDETERR_DEFAULT (_CMU_IFC_HFXOPEAKDETERR_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_IFC */ #define CMU_IFC_HFXOPEAKDETRDY (0x1UL << 11) /**< Clear HFXOPEAKDETRDY Interrupt Flag */ #define _CMU_IFC_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ #define _CMU_IFC_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ #define _CMU_IFC_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ #define CMU_IFC_HFXOPEAKDETRDY_DEFAULT (_CMU_IFC_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IFC */ #define CMU_IFC_HFXOSHUNTOPTRDY (0x1UL << 12) /**< Clear HFXOSHUNTOPTRDY Interrupt Flag */ #define _CMU_IFC_HFXOSHUNTOPTRDY_SHIFT 12 /**< Shift value for CMU_HFXOSHUNTOPTRDY */ #define _CMU_IFC_HFXOSHUNTOPTRDY_MASK 0x1000UL /**< Bit mask for CMU_HFXOSHUNTOPTRDY */ #define _CMU_IFC_HFXOSHUNTOPTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ #define CMU_IFC_HFXOSHUNTOPTRDY_DEFAULT (_CMU_IFC_HFXOSHUNTOPTRDY_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_IFC */ #define CMU_IFC_HFRCODIS (0x1UL << 13) /**< Clear HFRCODIS Interrupt Flag */ #define _CMU_IFC_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ #define _CMU_IFC_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ #define _CMU_IFC_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ #define CMU_IFC_HFRCODIS_DEFAULT (_CMU_IFC_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IFC */ #define CMU_IFC_LFTIMEOUTERR (0x1UL << 14) /**< Clear LFTIMEOUTERR Interrupt Flag */ #define _CMU_IFC_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ #define _CMU_IFC_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ #define _CMU_IFC_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ #define CMU_IFC_LFTIMEOUTERR_DEFAULT (_CMU_IFC_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IFC */ #define CMU_IFC_DPLLRDY (0x1UL << 15) /**< Clear DPLLRDY Interrupt Flag */ #define _CMU_IFC_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ #define _CMU_IFC_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ #define _CMU_IFC_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ #define CMU_IFC_DPLLRDY_DEFAULT (_CMU_IFC_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IFC */ #define CMU_IFC_DPLLLOCKFAILLOW (0x1UL << 16) /**< Clear DPLLLOCKFAILLOW Interrupt Flag */ #define _CMU_IFC_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ #define _CMU_IFC_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ #define _CMU_IFC_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ #define CMU_IFC_DPLLLOCKFAILLOW_DEFAULT (_CMU_IFC_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IFC */ #define CMU_IFC_DPLLLOCKFAILHIGH (0x1UL << 17) /**< Clear DPLLLOCKFAILHIGH Interrupt Flag */ #define _CMU_IFC_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ #define _CMU_IFC_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ #define _CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ #define CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IFC */ #define CMU_IFC_CMUERR (0x1UL << 31) /**< Clear CMUERR Interrupt Flag */ #define _CMU_IFC_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ #define _CMU_IFC_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ #define _CMU_IFC_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ #define CMU_IFC_CMUERR_DEFAULT (_CMU_IFC_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IFC */ /* Bit fields for CMU IEN */ #define _CMU_IEN_RESETVALUE 0x00000000UL /**< Default value for CMU_IEN */ #define _CMU_IEN_MASK 0x8003FF7FUL /**< Mask for CMU_IEN */ #define CMU_IEN_HFRCORDY (0x1UL << 0) /**< HFRCORDY Interrupt Enable */ #define _CMU_IEN_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ #define _CMU_IEN_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ #define _CMU_IEN_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ #define CMU_IEN_HFRCORDY_DEFAULT (_CMU_IEN_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IEN */ #define CMU_IEN_HFXORDY (0x1UL << 1) /**< HFXORDY Interrupt Enable */ #define _CMU_IEN_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ #define _CMU_IEN_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ #define _CMU_IEN_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ #define CMU_IEN_HFXORDY_DEFAULT (_CMU_IEN_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IEN */ #define CMU_IEN_LFRCORDY (0x1UL << 2) /**< LFRCORDY Interrupt Enable */ #define _CMU_IEN_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ #define _CMU_IEN_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ #define _CMU_IEN_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ #define CMU_IEN_LFRCORDY_DEFAULT (_CMU_IEN_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IEN */ #define CMU_IEN_LFXORDY (0x1UL << 3) /**< LFXORDY Interrupt Enable */ #define _CMU_IEN_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ #define _CMU_IEN_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ #define _CMU_IEN_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ #define CMU_IEN_LFXORDY_DEFAULT (_CMU_IEN_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IEN */ #define CMU_IEN_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCORDY Interrupt Enable */ #define _CMU_IEN_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ #define _CMU_IEN_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ #define _CMU_IEN_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ #define CMU_IEN_AUXHFRCORDY_DEFAULT (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IEN */ #define CMU_IEN_CALRDY (0x1UL << 5) /**< CALRDY Interrupt Enable */ #define _CMU_IEN_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ #define _CMU_IEN_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ #define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ #define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IEN */ #define CMU_IEN_CALOF (0x1UL << 6) /**< CALOF Interrupt Enable */ #define _CMU_IEN_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ #define _CMU_IEN_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ #define _CMU_IEN_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ #define CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IEN */ #define CMU_IEN_HFXODISERR (0x1UL << 8) /**< HFXODISERR Interrupt Enable */ #define _CMU_IEN_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ #define _CMU_IEN_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ #define _CMU_IEN_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ #define CMU_IEN_HFXODISERR_DEFAULT (_CMU_IEN_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IEN */ #define CMU_IEN_HFXOAUTOSW (0x1UL << 9) /**< HFXOAUTOSW Interrupt Enable */ #define _CMU_IEN_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ #define _CMU_IEN_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ #define _CMU_IEN_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ #define CMU_IEN_HFXOAUTOSW_DEFAULT (_CMU_IEN_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IEN */ #define CMU_IEN_HFXOPEAKDETERR (0x1UL << 10) /**< HFXOPEAKDETERR Interrupt Enable */ #define _CMU_IEN_HFXOPEAKDETERR_SHIFT 10 /**< Shift value for CMU_HFXOPEAKDETERR */ #define _CMU_IEN_HFXOPEAKDETERR_MASK 0x400UL /**< Bit mask for CMU_HFXOPEAKDETERR */ #define _CMU_IEN_HFXOPEAKDETERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ #define CMU_IEN_HFXOPEAKDETERR_DEFAULT (_CMU_IEN_HFXOPEAKDETERR_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_IEN */ #define CMU_IEN_HFXOPEAKDETRDY (0x1UL << 11) /**< HFXOPEAKDETRDY Interrupt Enable */ #define _CMU_IEN_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ #define _CMU_IEN_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ #define _CMU_IEN_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ #define CMU_IEN_HFXOPEAKDETRDY_DEFAULT (_CMU_IEN_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IEN */ #define CMU_IEN_HFXOSHUNTOPTRDY (0x1UL << 12) /**< HFXOSHUNTOPTRDY Interrupt Enable */ #define _CMU_IEN_HFXOSHUNTOPTRDY_SHIFT 12 /**< Shift value for CMU_HFXOSHUNTOPTRDY */ #define _CMU_IEN_HFXOSHUNTOPTRDY_MASK 0x1000UL /**< Bit mask for CMU_HFXOSHUNTOPTRDY */ #define _CMU_IEN_HFXOSHUNTOPTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ #define CMU_IEN_HFXOSHUNTOPTRDY_DEFAULT (_CMU_IEN_HFXOSHUNTOPTRDY_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_IEN */ #define CMU_IEN_HFRCODIS (0x1UL << 13) /**< HFRCODIS Interrupt Enable */ #define _CMU_IEN_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ #define _CMU_IEN_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ #define _CMU_IEN_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ #define CMU_IEN_HFRCODIS_DEFAULT (_CMU_IEN_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IEN */ #define CMU_IEN_LFTIMEOUTERR (0x1UL << 14) /**< LFTIMEOUTERR Interrupt Enable */ #define _CMU_IEN_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ #define _CMU_IEN_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ #define _CMU_IEN_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ #define CMU_IEN_LFTIMEOUTERR_DEFAULT (_CMU_IEN_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IEN */ #define CMU_IEN_DPLLRDY (0x1UL << 15) /**< DPLLRDY Interrupt Enable */ #define _CMU_IEN_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ #define _CMU_IEN_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ #define _CMU_IEN_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ #define CMU_IEN_DPLLRDY_DEFAULT (_CMU_IEN_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IEN */ #define CMU_IEN_DPLLLOCKFAILLOW (0x1UL << 16) /**< DPLLLOCKFAILLOW Interrupt Enable */ #define _CMU_IEN_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ #define _CMU_IEN_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ #define _CMU_IEN_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ #define CMU_IEN_DPLLLOCKFAILLOW_DEFAULT (_CMU_IEN_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IEN */ #define CMU_IEN_DPLLLOCKFAILHIGH (0x1UL << 17) /**< DPLLLOCKFAILHIGH Interrupt Enable */ #define _CMU_IEN_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ #define _CMU_IEN_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ #define _CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ #define CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IEN */ #define CMU_IEN_CMUERR (0x1UL << 31) /**< CMUERR Interrupt Enable */ #define _CMU_IEN_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ #define _CMU_IEN_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ #define _CMU_IEN_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ #define CMU_IEN_CMUERR_DEFAULT (_CMU_IEN_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IEN */ /* Bit fields for CMU HFBUSCLKEN0 */ #define _CMU_HFBUSCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFBUSCLKEN0 */ #define _CMU_HFBUSCLKEN0_MASK 0x0000007FUL /**< Mask for CMU_HFBUSCLKEN0 */ #define CMU_HFBUSCLKEN0_CRYPTO0 (0x1UL << 0) /**< Advanced Encryption Standard Accelerator 0 Clock Enable */ #define CMU_HFBUSCLKEN0_CRYPTO CMU_HFBUSCLKEN0_CRYPTO0 /**< Alias for CRYPTO0 */ #define _CMU_HFBUSCLKEN0_CRYPTO0_SHIFT 0 /**< Shift value for CMU_CRYPTO0 */ #define _CMU_HFBUSCLKEN0_CRYPTO0_MASK 0x1UL /**< Bit mask for CMU_CRYPTO0 */ #define _CMU_HFBUSCLKEN0_CRYPTO_SHIFT _CMU_HFBUSCLKEN0_CRYPTO0_SHIFT /**< Alias for CMU_CRYPTO0 */ #define _CMU_HFBUSCLKEN0_CRYPTO_MASK _CMU_HFBUSCLKEN0_CRYPTO0_MASK /**< Alias for CMU_CRYPTO0 */ #define _CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ #define _CMU_HFBUSCLKEN0_CRYPTO_DEFAULT _CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT /**< Alias for CRYPTO0 mode DEFAULT */ #define CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT (_CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ #define CMU_HFBUSCLKEN0_CRYPTO_DEFAULT CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT /**< Alias for CRYPTO0 mode DEFAULT*/ #define CMU_HFBUSCLKEN0_CRYPTO1 (0x1UL << 1) /**< Advanced Encryption Standard Accelerator 1 Clock Enable */ #define _CMU_HFBUSCLKEN0_CRYPTO1_SHIFT 1 /**< Shift value for CMU_CRYPTO1 */ #define _CMU_HFBUSCLKEN0_CRYPTO1_MASK 0x2UL /**< Bit mask for CMU_CRYPTO1 */ #define _CMU_HFBUSCLKEN0_CRYPTO1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ #define CMU_HFBUSCLKEN0_CRYPTO1_DEFAULT (_CMU_HFBUSCLKEN0_CRYPTO1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ #define CMU_HFBUSCLKEN0_LE (0x1UL << 2) /**< Low Energy Peripheral Interface Clock Enable */ #define _CMU_HFBUSCLKEN0_LE_SHIFT 2 /**< Shift value for CMU_LE */ #define _CMU_HFBUSCLKEN0_LE_MASK 0x4UL /**< Bit mask for CMU_LE */ #define _CMU_HFBUSCLKEN0_LE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ #define CMU_HFBUSCLKEN0_LE_DEFAULT (_CMU_HFBUSCLKEN0_LE_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ #define CMU_HFBUSCLKEN0_GPIO (0x1UL << 3) /**< General purpose Input/Output Clock Enable */ #define _CMU_HFBUSCLKEN0_GPIO_SHIFT 3 /**< Shift value for CMU_GPIO */ #define _CMU_HFBUSCLKEN0_GPIO_MASK 0x8UL /**< Bit mask for CMU_GPIO */ #define _CMU_HFBUSCLKEN0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ #define CMU_HFBUSCLKEN0_GPIO_DEFAULT (_CMU_HFBUSCLKEN0_GPIO_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ #define CMU_HFBUSCLKEN0_PRS (0x1UL << 4) /**< Peripheral Reflex System Clock Enable */ #define _CMU_HFBUSCLKEN0_PRS_SHIFT 4 /**< Shift value for CMU_PRS */ #define _CMU_HFBUSCLKEN0_PRS_MASK 0x10UL /**< Bit mask for CMU_PRS */ #define _CMU_HFBUSCLKEN0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ #define CMU_HFBUSCLKEN0_PRS_DEFAULT (_CMU_HFBUSCLKEN0_PRS_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ #define CMU_HFBUSCLKEN0_LDMA (0x1UL << 5) /**< Linked Direct Memory Access Controller Clock Enable */ #define _CMU_HFBUSCLKEN0_LDMA_SHIFT 5 /**< Shift value for CMU_LDMA */ #define _CMU_HFBUSCLKEN0_LDMA_MASK 0x20UL /**< Bit mask for CMU_LDMA */ #define _CMU_HFBUSCLKEN0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ #define CMU_HFBUSCLKEN0_LDMA_DEFAULT (_CMU_HFBUSCLKEN0_LDMA_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ #define CMU_HFBUSCLKEN0_GPCRC (0x1UL << 6) /**< General Purpose CRC Clock Enable */ #define _CMU_HFBUSCLKEN0_GPCRC_SHIFT 6 /**< Shift value for CMU_GPCRC */ #define _CMU_HFBUSCLKEN0_GPCRC_MASK 0x40UL /**< Bit mask for CMU_GPCRC */ #define _CMU_HFBUSCLKEN0_GPCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ #define CMU_HFBUSCLKEN0_GPCRC_DEFAULT (_CMU_HFBUSCLKEN0_GPCRC_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ /* Bit fields for CMU HFPERCLKEN0 */ #define _CMU_HFPERCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN0 */ #define _CMU_HFPERCLKEN0_MASK 0x0003FFFFUL /**< Mask for CMU_HFPERCLKEN0 */ #define CMU_HFPERCLKEN0_TIMER0 (0x1UL << 0) /**< Timer 0 Clock Enable */ #define _CMU_HFPERCLKEN0_TIMER0_SHIFT 0 /**< Shift value for CMU_TIMER0 */ #define _CMU_HFPERCLKEN0_TIMER0_MASK 0x1UL /**< Bit mask for CMU_TIMER0 */ #define _CMU_HFPERCLKEN0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ #define CMU_HFPERCLKEN0_TIMER0_DEFAULT (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ #define CMU_HFPERCLKEN0_TIMER1 (0x1UL << 1) /**< Timer 1 Clock Enable */ #define _CMU_HFPERCLKEN0_TIMER1_SHIFT 1 /**< Shift value for CMU_TIMER1 */ #define _CMU_HFPERCLKEN0_TIMER1_MASK 0x2UL /**< Bit mask for CMU_TIMER1 */ #define _CMU_HFPERCLKEN0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ #define CMU_HFPERCLKEN0_TIMER1_DEFAULT (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ #define CMU_HFPERCLKEN0_WTIMER0 (0x1UL << 2) /**< Wide Timer 0 Clock Enable */ #define _CMU_HFPERCLKEN0_WTIMER0_SHIFT 2 /**< Shift value for CMU_WTIMER0 */ #define _CMU_HFPERCLKEN0_WTIMER0_MASK 0x4UL /**< Bit mask for CMU_WTIMER0 */ #define _CMU_HFPERCLKEN0_WTIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ #define CMU_HFPERCLKEN0_WTIMER0_DEFAULT (_CMU_HFPERCLKEN0_WTIMER0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ #define CMU_HFPERCLKEN0_WTIMER1 (0x1UL << 3) /**< Wide Timer 1 Clock Enable */ #define _CMU_HFPERCLKEN0_WTIMER1_SHIFT 3 /**< Shift value for CMU_WTIMER1 */ #define _CMU_HFPERCLKEN0_WTIMER1_MASK 0x8UL /**< Bit mask for CMU_WTIMER1 */ #define _CMU_HFPERCLKEN0_WTIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ #define CMU_HFPERCLKEN0_WTIMER1_DEFAULT (_CMU_HFPERCLKEN0_WTIMER1_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ #define CMU_HFPERCLKEN0_USART0 (0x1UL << 4) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable */ #define _CMU_HFPERCLKEN0_USART0_SHIFT 4 /**< Shift value for CMU_USART0 */ #define _CMU_HFPERCLKEN0_USART0_MASK 0x10UL /**< Bit mask for CMU_USART0 */ #define _CMU_HFPERCLKEN0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ #define CMU_HFPERCLKEN0_USART0_DEFAULT (_CMU_HFPERCLKEN0_USART0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ #define CMU_HFPERCLKEN0_USART1 (0x1UL << 5) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable */ #define _CMU_HFPERCLKEN0_USART1_SHIFT 5 /**< Shift value for CMU_USART1 */ #define _CMU_HFPERCLKEN0_USART1_MASK 0x20UL /**< Bit mask for CMU_USART1 */ #define _CMU_HFPERCLKEN0_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ #define CMU_HFPERCLKEN0_USART1_DEFAULT (_CMU_HFPERCLKEN0_USART1_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ #define CMU_HFPERCLKEN0_USART2 (0x1UL << 6) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable */ #define _CMU_HFPERCLKEN0_USART2_SHIFT 6 /**< Shift value for CMU_USART2 */ #define _CMU_HFPERCLKEN0_USART2_MASK 0x40UL /**< Bit mask for CMU_USART2 */ #define _CMU_HFPERCLKEN0_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ #define CMU_HFPERCLKEN0_USART2_DEFAULT (_CMU_HFPERCLKEN0_USART2_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ #define CMU_HFPERCLKEN0_USART3 (0x1UL << 7) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 3 Clock Enable */ #define _CMU_HFPERCLKEN0_USART3_SHIFT 7 /**< Shift value for CMU_USART3 */ #define _CMU_HFPERCLKEN0_USART3_MASK 0x80UL /**< Bit mask for CMU_USART3 */ #define _CMU_HFPERCLKEN0_USART3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ #define CMU_HFPERCLKEN0_USART3_DEFAULT (_CMU_HFPERCLKEN0_USART3_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ #define CMU_HFPERCLKEN0_I2C0 (0x1UL << 8) /**< I2C 0 Clock Enable */ #define _CMU_HFPERCLKEN0_I2C0_SHIFT 8 /**< Shift value for CMU_I2C0 */ #define _CMU_HFPERCLKEN0_I2C0_MASK 0x100UL /**< Bit mask for CMU_I2C0 */ #define _CMU_HFPERCLKEN0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ #define CMU_HFPERCLKEN0_I2C0_DEFAULT (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ #define CMU_HFPERCLKEN0_I2C1 (0x1UL << 9) /**< I2C 1 Clock Enable */ #define _CMU_HFPERCLKEN0_I2C1_SHIFT 9 /**< Shift value for CMU_I2C1 */ #define _CMU_HFPERCLKEN0_I2C1_MASK 0x200UL /**< Bit mask for CMU_I2C1 */ #define _CMU_HFPERCLKEN0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ #define CMU_HFPERCLKEN0_I2C1_DEFAULT (_CMU_HFPERCLKEN0_I2C1_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ #define CMU_HFPERCLKEN0_ACMP0 (0x1UL << 10) /**< Analog Comparator 0 Clock Enable */ #define _CMU_HFPERCLKEN0_ACMP0_SHIFT 10 /**< Shift value for CMU_ACMP0 */ #define _CMU_HFPERCLKEN0_ACMP0_MASK 0x400UL /**< Bit mask for CMU_ACMP0 */ #define _CMU_HFPERCLKEN0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ #define CMU_HFPERCLKEN0_ACMP0_DEFAULT (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ #define CMU_HFPERCLKEN0_ACMP1 (0x1UL << 11) /**< Analog Comparator 1 Clock Enable */ #define _CMU_HFPERCLKEN0_ACMP1_SHIFT 11 /**< Shift value for CMU_ACMP1 */ #define _CMU_HFPERCLKEN0_ACMP1_MASK 0x800UL /**< Bit mask for CMU_ACMP1 */ #define _CMU_HFPERCLKEN0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ #define CMU_HFPERCLKEN0_ACMP1_DEFAULT (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ #define CMU_HFPERCLKEN0_CRYOTIMER (0x1UL << 12) /**< CryoTimer Clock Enable */ #define _CMU_HFPERCLKEN0_CRYOTIMER_SHIFT 12 /**< Shift value for CMU_CRYOTIMER */ #define _CMU_HFPERCLKEN0_CRYOTIMER_MASK 0x1000UL /**< Bit mask for CMU_CRYOTIMER */ #define _CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ #define CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT (_CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ #define CMU_HFPERCLKEN0_ADC0 (0x1UL << 13) /**< Analog to Digital Converter 0 Clock Enable */ #define _CMU_HFPERCLKEN0_ADC0_SHIFT 13 /**< Shift value for CMU_ADC0 */ #define _CMU_HFPERCLKEN0_ADC0_MASK 0x2000UL /**< Bit mask for CMU_ADC0 */ #define _CMU_HFPERCLKEN0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ #define CMU_HFPERCLKEN0_ADC0_DEFAULT (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ #define CMU_HFPERCLKEN0_IDAC0 (0x1UL << 14) /**< Current Digital to Analog Converter 0 Clock Enable */ #define _CMU_HFPERCLKEN0_IDAC0_SHIFT 14 /**< Shift value for CMU_IDAC0 */ #define _CMU_HFPERCLKEN0_IDAC0_MASK 0x4000UL /**< Bit mask for CMU_IDAC0 */ #define _CMU_HFPERCLKEN0_IDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ #define CMU_HFPERCLKEN0_IDAC0_DEFAULT (_CMU_HFPERCLKEN0_IDAC0_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ #define CMU_HFPERCLKEN0_VDAC0 (0x1UL << 15) /**< Digital to Analog Converter 0 Clock Enable */ #define _CMU_HFPERCLKEN0_VDAC0_SHIFT 15 /**< Shift value for CMU_VDAC0 */ #define _CMU_HFPERCLKEN0_VDAC0_MASK 0x8000UL /**< Bit mask for CMU_VDAC0 */ #define _CMU_HFPERCLKEN0_VDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ #define CMU_HFPERCLKEN0_VDAC0_DEFAULT (_CMU_HFPERCLKEN0_VDAC0_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ #define CMU_HFPERCLKEN0_CSEN (0x1UL << 16) /**< Capacitive touch sense module Clock Enable */ #define _CMU_HFPERCLKEN0_CSEN_SHIFT 16 /**< Shift value for CMU_CSEN */ #define _CMU_HFPERCLKEN0_CSEN_MASK 0x10000UL /**< Bit mask for CMU_CSEN */ #define _CMU_HFPERCLKEN0_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ #define CMU_HFPERCLKEN0_CSEN_DEFAULT (_CMU_HFPERCLKEN0_CSEN_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ #define CMU_HFPERCLKEN0_TRNG0 (0x1UL << 17) /**< True Random Number Generator 0 Clock Enable */ #define _CMU_HFPERCLKEN0_TRNG0_SHIFT 17 /**< Shift value for CMU_TRNG0 */ #define _CMU_HFPERCLKEN0_TRNG0_MASK 0x20000UL /**< Bit mask for CMU_TRNG0 */ #define _CMU_HFPERCLKEN0_TRNG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ #define CMU_HFPERCLKEN0_TRNG0_DEFAULT (_CMU_HFPERCLKEN0_TRNG0_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ /* Bit fields for CMU LFACLKEN0 */ #define _CMU_LFACLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKEN0 */ #define _CMU_LFACLKEN0_MASK 0x00000003UL /**< Mask for CMU_LFACLKEN0 */ #define CMU_LFACLKEN0_LETIMER0 (0x1UL << 0) /**< Low Energy Timer 0 Clock Enable */ #define _CMU_LFACLKEN0_LETIMER0_SHIFT 0 /**< Shift value for CMU_LETIMER0 */ #define _CMU_LFACLKEN0_LETIMER0_MASK 0x1UL /**< Bit mask for CMU_LETIMER0 */ #define _CMU_LFACLKEN0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ #define CMU_LFACLKEN0_LETIMER0_DEFAULT (_CMU_LFACLKEN0_LETIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ #define CMU_LFACLKEN0_LESENSE (0x1UL << 1) /**< Low Energy Sensor Interface Clock Enable */ #define _CMU_LFACLKEN0_LESENSE_SHIFT 1 /**< Shift value for CMU_LESENSE */ #define _CMU_LFACLKEN0_LESENSE_MASK 0x2UL /**< Bit mask for CMU_LESENSE */ #define _CMU_LFACLKEN0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ #define CMU_LFACLKEN0_LESENSE_DEFAULT (_CMU_LFACLKEN0_LESENSE_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ /* Bit fields for CMU LFBCLKEN0 */ #define _CMU_LFBCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKEN0 */ #define _CMU_LFBCLKEN0_MASK 0x00000007UL /**< Mask for CMU_LFBCLKEN0 */ #define CMU_LFBCLKEN0_SYSTICK (0x1UL << 0) /**< Clock Enable */ #define _CMU_LFBCLKEN0_SYSTICK_SHIFT 0 /**< Shift value for CMU_SYSTICK */ #define _CMU_LFBCLKEN0_SYSTICK_MASK 0x1UL /**< Bit mask for CMU_SYSTICK */ #define _CMU_LFBCLKEN0_SYSTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ #define CMU_LFBCLKEN0_SYSTICK_DEFAULT (_CMU_LFBCLKEN0_SYSTICK_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ #define CMU_LFBCLKEN0_LEUART0 (0x1UL << 1) /**< Low Energy UART 0 Clock Enable */ #define _CMU_LFBCLKEN0_LEUART0_SHIFT 1 /**< Shift value for CMU_LEUART0 */ #define _CMU_LFBCLKEN0_LEUART0_MASK 0x2UL /**< Bit mask for CMU_LEUART0 */ #define _CMU_LFBCLKEN0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ #define CMU_LFBCLKEN0_LEUART0_DEFAULT (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ #define CMU_LFBCLKEN0_CSEN (0x1UL << 2) /**< Capacitive touch sense module Clock Enable */ #define _CMU_LFBCLKEN0_CSEN_SHIFT 2 /**< Shift value for CMU_CSEN */ #define _CMU_LFBCLKEN0_CSEN_MASK 0x4UL /**< Bit mask for CMU_CSEN */ #define _CMU_LFBCLKEN0_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ #define CMU_LFBCLKEN0_CSEN_DEFAULT (_CMU_LFBCLKEN0_CSEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ /* Bit fields for CMU LFECLKEN0 */ #define _CMU_LFECLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFECLKEN0 */ #define _CMU_LFECLKEN0_MASK 0x00000001UL /**< Mask for CMU_LFECLKEN0 */ #define CMU_LFECLKEN0_RTCC (0x1UL << 0) /**< Real-Time Counter and Calendar Clock Enable */ #define _CMU_LFECLKEN0_RTCC_SHIFT 0 /**< Shift value for CMU_RTCC */ #define _CMU_LFECLKEN0_RTCC_MASK 0x1UL /**< Bit mask for CMU_RTCC */ #define _CMU_LFECLKEN0_RTCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFECLKEN0 */ #define CMU_LFECLKEN0_RTCC_DEFAULT (_CMU_LFECLKEN0_RTCC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFECLKEN0 */ /* Bit fields for CMU HFPRESC */ #define _CMU_HFPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPRESC */ #define _CMU_HFPRESC_MASK 0x01001F00UL /**< Mask for CMU_HFPRESC */ #define _CMU_HFPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ #define _CMU_HFPRESC_PRESC_MASK 0x1F00UL /**< Bit mask for CMU_PRESC */ #define _CMU_HFPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPRESC */ #define _CMU_HFPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPRESC */ #define CMU_HFPRESC_PRESC_DEFAULT (_CMU_HFPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPRESC */ #define CMU_HFPRESC_PRESC_NODIVISION (_CMU_HFPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPRESC */ #define _CMU_HFPRESC_HFCLKLEPRESC_SHIFT 24 /**< Shift value for CMU_HFCLKLEPRESC */ #define _CMU_HFPRESC_HFCLKLEPRESC_MASK 0x1000000UL /**< Bit mask for CMU_HFCLKLEPRESC */ #define _CMU_HFPRESC_HFCLKLEPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPRESC */ #define _CMU_HFPRESC_HFCLKLEPRESC_DIV2 0x00000000UL /**< Mode DIV2 for CMU_HFPRESC */ #define _CMU_HFPRESC_HFCLKLEPRESC_DIV4 0x00000001UL /**< Mode DIV4 for CMU_HFPRESC */ #define CMU_HFPRESC_HFCLKLEPRESC_DEFAULT (_CMU_HFPRESC_HFCLKLEPRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFPRESC */ #define CMU_HFPRESC_HFCLKLEPRESC_DIV2 (_CMU_HFPRESC_HFCLKLEPRESC_DIV2 << 24) /**< Shifted mode DIV2 for CMU_HFPRESC */ #define CMU_HFPRESC_HFCLKLEPRESC_DIV4 (_CMU_HFPRESC_HFCLKLEPRESC_DIV4 << 24) /**< Shifted mode DIV4 for CMU_HFPRESC */ /* Bit fields for CMU HFCOREPRESC */ #define _CMU_HFCOREPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCOREPRESC */ #define _CMU_HFCOREPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFCOREPRESC */ #define _CMU_HFCOREPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ #define _CMU_HFCOREPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ #define _CMU_HFCOREPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCOREPRESC */ #define _CMU_HFCOREPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFCOREPRESC */ #define CMU_HFCOREPRESC_PRESC_DEFAULT (_CMU_HFCOREPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFCOREPRESC */ #define CMU_HFCOREPRESC_PRESC_NODIVISION (_CMU_HFCOREPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFCOREPRESC */ /* Bit fields for CMU HFPERPRESC */ #define _CMU_HFPERPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERPRESC */ #define _CMU_HFPERPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFPERPRESC */ #define _CMU_HFPERPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ #define _CMU_HFPERPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ #define _CMU_HFPERPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERPRESC */ #define _CMU_HFPERPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPERPRESC */ #define CMU_HFPERPRESC_PRESC_DEFAULT (_CMU_HFPERPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERPRESC */ #define CMU_HFPERPRESC_PRESC_NODIVISION (_CMU_HFPERPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPERPRESC */ /* Bit fields for CMU HFEXPPRESC */ #define _CMU_HFEXPPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFEXPPRESC */ #define _CMU_HFEXPPRESC_MASK 0x00001F00UL /**< Mask for CMU_HFEXPPRESC */ #define _CMU_HFEXPPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ #define _CMU_HFEXPPRESC_PRESC_MASK 0x1F00UL /**< Bit mask for CMU_PRESC */ #define _CMU_HFEXPPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFEXPPRESC */ #define _CMU_HFEXPPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFEXPPRESC */ #define CMU_HFEXPPRESC_PRESC_DEFAULT (_CMU_HFEXPPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFEXPPRESC */ #define CMU_HFEXPPRESC_PRESC_NODIVISION (_CMU_HFEXPPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFEXPPRESC */ /* Bit fields for CMU LFAPRESC0 */ #define _CMU_LFAPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFAPRESC0 */ #define _CMU_LFAPRESC0_MASK 0x0000003FUL /**< Mask for CMU_LFAPRESC0 */ #define _CMU_LFAPRESC0_LETIMER0_SHIFT 0 /**< Shift value for CMU_LETIMER0 */ #define _CMU_LFAPRESC0_LETIMER0_MASK 0xFUL /**< Bit mask for CMU_LETIMER0 */ #define _CMU_LFAPRESC0_LETIMER0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ #define _CMU_LFAPRESC0_LETIMER0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ #define _CMU_LFAPRESC0_LETIMER0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ #define _CMU_LFAPRESC0_LETIMER0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ #define _CMU_LFAPRESC0_LETIMER0_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ #define _CMU_LFAPRESC0_LETIMER0_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ #define _CMU_LFAPRESC0_LETIMER0_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ #define _CMU_LFAPRESC0_LETIMER0_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ #define _CMU_LFAPRESC0_LETIMER0_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */ #define _CMU_LFAPRESC0_LETIMER0_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */ #define _CMU_LFAPRESC0_LETIMER0_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */ #define _CMU_LFAPRESC0_LETIMER0_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */ #define _CMU_LFAPRESC0_LETIMER0_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */ #define _CMU_LFAPRESC0_LETIMER0_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */ #define _CMU_LFAPRESC0_LETIMER0_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */ #define _CMU_LFAPRESC0_LETIMER0_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */ #define CMU_LFAPRESC0_LETIMER0_DIV1 (_CMU_LFAPRESC0_LETIMER0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ #define CMU_LFAPRESC0_LETIMER0_DIV2 (_CMU_LFAPRESC0_LETIMER0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ #define CMU_LFAPRESC0_LETIMER0_DIV4 (_CMU_LFAPRESC0_LETIMER0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ #define CMU_LFAPRESC0_LETIMER0_DIV8 (_CMU_LFAPRESC0_LETIMER0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ #define CMU_LFAPRESC0_LETIMER0_DIV16 (_CMU_LFAPRESC0_LETIMER0_DIV16 << 0) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ #define CMU_LFAPRESC0_LETIMER0_DIV32 (_CMU_LFAPRESC0_LETIMER0_DIV32 << 0) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ #define CMU_LFAPRESC0_LETIMER0_DIV64 (_CMU_LFAPRESC0_LETIMER0_DIV64 << 0) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ #define CMU_LFAPRESC0_LETIMER0_DIV128 (_CMU_LFAPRESC0_LETIMER0_DIV128 << 0) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ #define CMU_LFAPRESC0_LETIMER0_DIV256 (_CMU_LFAPRESC0_LETIMER0_DIV256 << 0) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */ #define CMU_LFAPRESC0_LETIMER0_DIV512 (_CMU_LFAPRESC0_LETIMER0_DIV512 << 0) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */ #define CMU_LFAPRESC0_LETIMER0_DIV1024 (_CMU_LFAPRESC0_LETIMER0_DIV1024 << 0) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */ #define CMU_LFAPRESC0_LETIMER0_DIV2048 (_CMU_LFAPRESC0_LETIMER0_DIV2048 << 0) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */ #define CMU_LFAPRESC0_LETIMER0_DIV4096 (_CMU_LFAPRESC0_LETIMER0_DIV4096 << 0) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */ #define CMU_LFAPRESC0_LETIMER0_DIV8192 (_CMU_LFAPRESC0_LETIMER0_DIV8192 << 0) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */ #define CMU_LFAPRESC0_LETIMER0_DIV16384 (_CMU_LFAPRESC0_LETIMER0_DIV16384 << 0) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */ #define CMU_LFAPRESC0_LETIMER0_DIV32768 (_CMU_LFAPRESC0_LETIMER0_DIV32768 << 0) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */ #define _CMU_LFAPRESC0_LESENSE_SHIFT 4 /**< Shift value for CMU_LESENSE */ #define _CMU_LFAPRESC0_LESENSE_MASK 0x30UL /**< Bit mask for CMU_LESENSE */ #define _CMU_LFAPRESC0_LESENSE_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ #define _CMU_LFAPRESC0_LESENSE_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ #define _CMU_LFAPRESC0_LESENSE_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ #define _CMU_LFAPRESC0_LESENSE_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ #define CMU_LFAPRESC0_LESENSE_DIV1 (_CMU_LFAPRESC0_LESENSE_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ #define CMU_LFAPRESC0_LESENSE_DIV2 (_CMU_LFAPRESC0_LESENSE_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ #define CMU_LFAPRESC0_LESENSE_DIV4 (_CMU_LFAPRESC0_LESENSE_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ #define CMU_LFAPRESC0_LESENSE_DIV8 (_CMU_LFAPRESC0_LESENSE_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ /* Bit fields for CMU LFBPRESC0 */ #define _CMU_LFBPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBPRESC0 */ #define _CMU_LFBPRESC0_MASK 0x0000033FUL /**< Mask for CMU_LFBPRESC0 */ #define _CMU_LFBPRESC0_SYSTICK_SHIFT 0 /**< Shift value for CMU_SYSTICK */ #define _CMU_LFBPRESC0_SYSTICK_MASK 0xFUL /**< Bit mask for CMU_SYSTICK */ #define _CMU_LFBPRESC0_SYSTICK_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ #define CMU_LFBPRESC0_SYSTICK_DIV1 (_CMU_LFBPRESC0_SYSTICK_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ #define _CMU_LFBPRESC0_LEUART0_SHIFT 4 /**< Shift value for CMU_LEUART0 */ #define _CMU_LFBPRESC0_LEUART0_MASK 0x30UL /**< Bit mask for CMU_LEUART0 */ #define _CMU_LFBPRESC0_LEUART0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ #define _CMU_LFBPRESC0_LEUART0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */ #define _CMU_LFBPRESC0_LEUART0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */ #define _CMU_LFBPRESC0_LEUART0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */ #define CMU_LFBPRESC0_LEUART0_DIV1 (_CMU_LFBPRESC0_LEUART0_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ #define CMU_LFBPRESC0_LEUART0_DIV2 (_CMU_LFBPRESC0_LEUART0_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */ #define CMU_LFBPRESC0_LEUART0_DIV4 (_CMU_LFBPRESC0_LEUART0_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */ #define CMU_LFBPRESC0_LEUART0_DIV8 (_CMU_LFBPRESC0_LEUART0_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */ #define _CMU_LFBPRESC0_CSEN_SHIFT 8 /**< Shift value for CMU_CSEN */ #define _CMU_LFBPRESC0_CSEN_MASK 0x300UL /**< Bit mask for CMU_CSEN */ #define _CMU_LFBPRESC0_CSEN_DIV16 0x00000000UL /**< Mode DIV16 for CMU_LFBPRESC0 */ #define _CMU_LFBPRESC0_CSEN_DIV32 0x00000001UL /**< Mode DIV32 for CMU_LFBPRESC0 */ #define _CMU_LFBPRESC0_CSEN_DIV64 0x00000002UL /**< Mode DIV64 for CMU_LFBPRESC0 */ #define _CMU_LFBPRESC0_CSEN_DIV128 0x00000003UL /**< Mode DIV128 for CMU_LFBPRESC0 */ #define CMU_LFBPRESC0_CSEN_DIV16 (_CMU_LFBPRESC0_CSEN_DIV16 << 8) /**< Shifted mode DIV16 for CMU_LFBPRESC0 */ #define CMU_LFBPRESC0_CSEN_DIV32 (_CMU_LFBPRESC0_CSEN_DIV32 << 8) /**< Shifted mode DIV32 for CMU_LFBPRESC0 */ #define CMU_LFBPRESC0_CSEN_DIV64 (_CMU_LFBPRESC0_CSEN_DIV64 << 8) /**< Shifted mode DIV64 for CMU_LFBPRESC0 */ #define CMU_LFBPRESC0_CSEN_DIV128 (_CMU_LFBPRESC0_CSEN_DIV128 << 8) /**< Shifted mode DIV128 for CMU_LFBPRESC0 */ /* Bit fields for CMU LFEPRESC0 */ #define _CMU_LFEPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFEPRESC0 */ #define _CMU_LFEPRESC0_MASK 0x00000003UL /**< Mask for CMU_LFEPRESC0 */ #define _CMU_LFEPRESC0_RTCC_SHIFT 0 /**< Shift value for CMU_RTCC */ #define _CMU_LFEPRESC0_RTCC_MASK 0x3UL /**< Bit mask for CMU_RTCC */ #define _CMU_LFEPRESC0_RTCC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFEPRESC0 */ #define _CMU_LFEPRESC0_RTCC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFEPRESC0 */ #define _CMU_LFEPRESC0_RTCC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFEPRESC0 */ #define CMU_LFEPRESC0_RTCC_DIV1 (_CMU_LFEPRESC0_RTCC_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFEPRESC0 */ #define CMU_LFEPRESC0_RTCC_DIV2 (_CMU_LFEPRESC0_RTCC_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFEPRESC0 */ #define CMU_LFEPRESC0_RTCC_DIV4 (_CMU_LFEPRESC0_RTCC_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFEPRESC0 */ /* Bit fields for CMU SYNCBUSY */ #define _CMU_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for CMU_SYNCBUSY */ #define _CMU_SYNCBUSY_MASK 0x3F050055UL /**< Mask for CMU_SYNCBUSY */ #define CMU_SYNCBUSY_LFACLKEN0 (0x1UL << 0) /**< Low Frequency a Clock Enable 0 Busy */ #define _CMU_SYNCBUSY_LFACLKEN0_SHIFT 0 /**< Shift value for CMU_LFACLKEN0 */ #define _CMU_SYNCBUSY_LFACLKEN0_MASK 0x1UL /**< Bit mask for CMU_LFACLKEN0 */ #define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ #define CMU_SYNCBUSY_LFACLKEN0_DEFAULT (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ #define CMU_SYNCBUSY_LFAPRESC0 (0x1UL << 2) /**< Low Frequency a Prescaler 0 Busy */ #define _CMU_SYNCBUSY_LFAPRESC0_SHIFT 2 /**< Shift value for CMU_LFAPRESC0 */ #define _CMU_SYNCBUSY_LFAPRESC0_MASK 0x4UL /**< Bit mask for CMU_LFAPRESC0 */ #define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ #define CMU_SYNCBUSY_LFAPRESC0_DEFAULT (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ #define CMU_SYNCBUSY_LFBCLKEN0 (0x1UL << 4) /**< Low Frequency B Clock Enable 0 Busy */ #define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT 4 /**< Shift value for CMU_LFBCLKEN0 */ #define _CMU_SYNCBUSY_LFBCLKEN0_MASK 0x10UL /**< Bit mask for CMU_LFBCLKEN0 */ #define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ #define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ #define CMU_SYNCBUSY_LFBPRESC0 (0x1UL << 6) /**< Low Frequency B Prescaler 0 Busy */ #define _CMU_SYNCBUSY_LFBPRESC0_SHIFT 6 /**< Shift value for CMU_LFBPRESC0 */ #define _CMU_SYNCBUSY_LFBPRESC0_MASK 0x40UL /**< Bit mask for CMU_LFBPRESC0 */ #define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ #define CMU_SYNCBUSY_LFBPRESC0_DEFAULT (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ #define CMU_SYNCBUSY_LFECLKEN0 (0x1UL << 16) /**< Low Frequency E Clock Enable 0 Busy */ #define _CMU_SYNCBUSY_LFECLKEN0_SHIFT 16 /**< Shift value for CMU_LFECLKEN0 */ #define _CMU_SYNCBUSY_LFECLKEN0_MASK 0x10000UL /**< Bit mask for CMU_LFECLKEN0 */ #define _CMU_SYNCBUSY_LFECLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ #define CMU_SYNCBUSY_LFECLKEN0_DEFAULT (_CMU_SYNCBUSY_LFECLKEN0_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ #define CMU_SYNCBUSY_LFEPRESC0 (0x1UL << 18) /**< Low Frequency E Prescaler 0 Busy */ #define _CMU_SYNCBUSY_LFEPRESC0_SHIFT 18 /**< Shift value for CMU_LFEPRESC0 */ #define _CMU_SYNCBUSY_LFEPRESC0_MASK 0x40000UL /**< Bit mask for CMU_LFEPRESC0 */ #define _CMU_SYNCBUSY_LFEPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ #define CMU_SYNCBUSY_LFEPRESC0_DEFAULT (_CMU_SYNCBUSY_LFEPRESC0_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ #define CMU_SYNCBUSY_HFRCOBSY (0x1UL << 24) /**< HFRCO Busy */ #define _CMU_SYNCBUSY_HFRCOBSY_SHIFT 24 /**< Shift value for CMU_HFRCOBSY */ #define _CMU_SYNCBUSY_HFRCOBSY_MASK 0x1000000UL /**< Bit mask for CMU_HFRCOBSY */ #define _CMU_SYNCBUSY_HFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ #define CMU_SYNCBUSY_HFRCOBSY_DEFAULT (_CMU_SYNCBUSY_HFRCOBSY_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ #define CMU_SYNCBUSY_AUXHFRCOBSY (0x1UL << 25) /**< AUXHFRCO Busy */ #define _CMU_SYNCBUSY_AUXHFRCOBSY_SHIFT 25 /**< Shift value for CMU_AUXHFRCOBSY */ #define _CMU_SYNCBUSY_AUXHFRCOBSY_MASK 0x2000000UL /**< Bit mask for CMU_AUXHFRCOBSY */ #define _CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ #define CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT (_CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ #define CMU_SYNCBUSY_LFRCOBSY (0x1UL << 26) /**< LFRCO Busy */ #define _CMU_SYNCBUSY_LFRCOBSY_SHIFT 26 /**< Shift value for CMU_LFRCOBSY */ #define _CMU_SYNCBUSY_LFRCOBSY_MASK 0x4000000UL /**< Bit mask for CMU_LFRCOBSY */ #define _CMU_SYNCBUSY_LFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ #define CMU_SYNCBUSY_LFRCOBSY_DEFAULT (_CMU_SYNCBUSY_LFRCOBSY_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ #define CMU_SYNCBUSY_LFRCOVREFBSY (0x1UL << 27) /**< LFRCO VREF Busy */ #define _CMU_SYNCBUSY_LFRCOVREFBSY_SHIFT 27 /**< Shift value for CMU_LFRCOVREFBSY */ #define _CMU_SYNCBUSY_LFRCOVREFBSY_MASK 0x8000000UL /**< Bit mask for CMU_LFRCOVREFBSY */ #define _CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ #define CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT (_CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ #define CMU_SYNCBUSY_HFXOBSY (0x1UL << 28) /**< HFXO Busy */ #define _CMU_SYNCBUSY_HFXOBSY_SHIFT 28 /**< Shift value for CMU_HFXOBSY */ #define _CMU_SYNCBUSY_HFXOBSY_MASK 0x10000000UL /**< Bit mask for CMU_HFXOBSY */ #define _CMU_SYNCBUSY_HFXOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ #define CMU_SYNCBUSY_HFXOBSY_DEFAULT (_CMU_SYNCBUSY_HFXOBSY_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ #define CMU_SYNCBUSY_LFXOBSY (0x1UL << 29) /**< LFXO Busy */ #define _CMU_SYNCBUSY_LFXOBSY_SHIFT 29 /**< Shift value for CMU_LFXOBSY */ #define _CMU_SYNCBUSY_LFXOBSY_MASK 0x20000000UL /**< Bit mask for CMU_LFXOBSY */ #define _CMU_SYNCBUSY_LFXOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ #define CMU_SYNCBUSY_LFXOBSY_DEFAULT (_CMU_SYNCBUSY_LFXOBSY_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ /* Bit fields for CMU FREEZE */ #define _CMU_FREEZE_RESETVALUE 0x00000000UL /**< Default value for CMU_FREEZE */ #define _CMU_FREEZE_MASK 0x00000001UL /**< Mask for CMU_FREEZE */ #define CMU_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */ #define _CMU_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for CMU_REGFREEZE */ #define _CMU_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for CMU_REGFREEZE */ #define _CMU_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_FREEZE */ #define _CMU_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for CMU_FREEZE */ #define _CMU_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for CMU_FREEZE */ #define CMU_FREEZE_REGFREEZE_DEFAULT (_CMU_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_FREEZE */ #define CMU_FREEZE_REGFREEZE_UPDATE (_CMU_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for CMU_FREEZE */ #define CMU_FREEZE_REGFREEZE_FREEZE (_CMU_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for CMU_FREEZE */ /* Bit fields for CMU PCNTCTRL */ #define _CMU_PCNTCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_PCNTCTRL */ #define _CMU_PCNTCTRL_MASK 0x0000003FUL /**< Mask for CMU_PCNTCTRL */ #define CMU_PCNTCTRL_PCNT0CLKEN (0x1UL << 0) /**< PCNT0 Clock Enable */ #define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT 0 /**< Shift value for CMU_PCNT0CLKEN */ #define _CMU_PCNTCTRL_PCNT0CLKEN_MASK 0x1UL /**< Bit mask for CMU_PCNT0CLKEN */ #define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ #define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ #define CMU_PCNTCTRL_PCNT0CLKSEL (0x1UL << 1) /**< PCNT0 Clock Select */ #define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT 1 /**< Shift value for CMU_PCNT0CLKSEL */ #define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK 0x2UL /**< Bit mask for CMU_PCNT0CLKSEL */ #define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ #define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ #define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 0x00000001UL /**< Mode PCNT0S0 for CMU_PCNTCTRL */ #define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ #define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ #define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1) /**< Shifted mode PCNT0S0 for CMU_PCNTCTRL */ #define CMU_PCNTCTRL_PCNT1CLKEN (0x1UL << 2) /**< PCNT1 Clock Enable */ #define _CMU_PCNTCTRL_PCNT1CLKEN_SHIFT 2 /**< Shift value for CMU_PCNT1CLKEN */ #define _CMU_PCNTCTRL_PCNT1CLKEN_MASK 0x4UL /**< Bit mask for CMU_PCNT1CLKEN */ #define _CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ #define CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ #define CMU_PCNTCTRL_PCNT1CLKSEL (0x1UL << 3) /**< PCNT1 Clock Select */ #define _CMU_PCNTCTRL_PCNT1CLKSEL_SHIFT 3 /**< Shift value for CMU_PCNT1CLKSEL */ #define _CMU_PCNTCTRL_PCNT1CLKSEL_MASK 0x8UL /**< Bit mask for CMU_PCNT1CLKSEL */ #define _CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ #define _CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ #define _CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 0x00000001UL /**< Mode PCNT1S0 for CMU_PCNTCTRL */ #define CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ #define CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK << 3) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ #define CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 (_CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 << 3) /**< Shifted mode PCNT1S0 for CMU_PCNTCTRL */ #define CMU_PCNTCTRL_PCNT2CLKEN (0x1UL << 4) /**< PCNT2 Clock Enable */ #define _CMU_PCNTCTRL_PCNT2CLKEN_SHIFT 4 /**< Shift value for CMU_PCNT2CLKEN */ #define _CMU_PCNTCTRL_PCNT2CLKEN_MASK 0x10UL /**< Bit mask for CMU_PCNT2CLKEN */ #define _CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ #define CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ #define CMU_PCNTCTRL_PCNT2CLKSEL (0x1UL << 5) /**< PCNT2 Clock Select */ #define _CMU_PCNTCTRL_PCNT2CLKSEL_SHIFT 5 /**< Shift value for CMU_PCNT2CLKSEL */ #define _CMU_PCNTCTRL_PCNT2CLKSEL_MASK 0x20UL /**< Bit mask for CMU_PCNT2CLKSEL */ #define _CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ #define _CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ #define _CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 0x00000001UL /**< Mode PCNT2S0 for CMU_PCNTCTRL */ #define CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ #define CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK << 5) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ #define CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 (_CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 << 5) /**< Shifted mode PCNT2S0 for CMU_PCNTCTRL */ /* Bit fields for CMU ADCCTRL */ #define _CMU_ADCCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_ADCCTRL */ #define _CMU_ADCCTRL_MASK 0x00000130UL /**< Mask for CMU_ADCCTRL */ #define _CMU_ADCCTRL_ADC0CLKSEL_SHIFT 4 /**< Shift value for CMU_ADC0CLKSEL */ #define _CMU_ADCCTRL_ADC0CLKSEL_MASK 0x30UL /**< Bit mask for CMU_ADC0CLKSEL */ #define _CMU_ADCCTRL_ADC0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ #define _CMU_ADCCTRL_ADC0CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_ADCCTRL */ #define _CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO 0x00000001UL /**< Mode AUXHFRCO for CMU_ADCCTRL */ #define _CMU_ADCCTRL_ADC0CLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_ADCCTRL */ #define _CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK 0x00000003UL /**< Mode HFSRCCLK for CMU_ADCCTRL */ #define CMU_ADCCTRL_ADC0CLKSEL_DEFAULT (_CMU_ADCCTRL_ADC0CLKSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ #define CMU_ADCCTRL_ADC0CLKSEL_DISABLED (_CMU_ADCCTRL_ADC0CLKSEL_DISABLED << 4) /**< Shifted mode DISABLED for CMU_ADCCTRL */ #define CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO (_CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO << 4) /**< Shifted mode AUXHFRCO for CMU_ADCCTRL */ #define CMU_ADCCTRL_ADC0CLKSEL_HFXO (_CMU_ADCCTRL_ADC0CLKSEL_HFXO << 4) /**< Shifted mode HFXO for CMU_ADCCTRL */ #define CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK (_CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK << 4) /**< Shifted mode HFSRCCLK for CMU_ADCCTRL */ #define CMU_ADCCTRL_ADC0CLKINV (0x1UL << 8) /**< Invert Clock Selected By ADC0CLKSEL */ #define _CMU_ADCCTRL_ADC0CLKINV_SHIFT 8 /**< Shift value for CMU_ADC0CLKINV */ #define _CMU_ADCCTRL_ADC0CLKINV_MASK 0x100UL /**< Bit mask for CMU_ADC0CLKINV */ #define _CMU_ADCCTRL_ADC0CLKINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ #define CMU_ADCCTRL_ADC0CLKINV_DEFAULT (_CMU_ADCCTRL_ADC0CLKINV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ /* Bit fields for CMU ROUTEPEN */ #define _CMU_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTEPEN */ #define _CMU_ROUTEPEN_MASK 0x10000003UL /**< Mask for CMU_ROUTEPEN */ #define CMU_ROUTEPEN_CLKOUT0PEN (0x1UL << 0) /**< CLKOUT0 Pin Enable */ #define _CMU_ROUTEPEN_CLKOUT0PEN_SHIFT 0 /**< Shift value for CMU_CLKOUT0PEN */ #define _CMU_ROUTEPEN_CLKOUT0PEN_MASK 0x1UL /**< Bit mask for CMU_CLKOUT0PEN */ #define _CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ #define CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ #define CMU_ROUTEPEN_CLKOUT1PEN (0x1UL << 1) /**< CLKOUT1 Pin Enable */ #define _CMU_ROUTEPEN_CLKOUT1PEN_SHIFT 1 /**< Shift value for CMU_CLKOUT1PEN */ #define _CMU_ROUTEPEN_CLKOUT1PEN_MASK 0x2UL /**< Bit mask for CMU_CLKOUT1PEN */ #define _CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ #define CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ #define CMU_ROUTEPEN_CLKIN0PEN (0x1UL << 28) /**< CLKIN0 Pin Enable */ #define _CMU_ROUTEPEN_CLKIN0PEN_SHIFT 28 /**< Shift value for CMU_CLKIN0PEN */ #define _CMU_ROUTEPEN_CLKIN0PEN_MASK 0x10000000UL /**< Bit mask for CMU_CLKIN0PEN */ #define _CMU_ROUTEPEN_CLKIN0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ #define CMU_ROUTEPEN_CLKIN0PEN_DEFAULT (_CMU_ROUTEPEN_CLKIN0PEN_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ /* Bit fields for CMU ROUTELOC0 */ #define _CMU_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTELOC0 */ #define _CMU_ROUTELOC0_MASK 0x00000707UL /**< Mask for CMU_ROUTELOC0 */ #define _CMU_ROUTELOC0_CLKOUT0LOC_SHIFT 0 /**< Shift value for CMU_CLKOUT0LOC */ #define _CMU_ROUTELOC0_CLKOUT0LOC_MASK 0x7UL /**< Bit mask for CMU_CLKOUT0LOC */ #define _CMU_ROUTELOC0_CLKOUT0LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */ #define _CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */ #define _CMU_ROUTELOC0_CLKOUT0LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */ #define _CMU_ROUTELOC0_CLKOUT0LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */ #define _CMU_ROUTELOC0_CLKOUT0LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */ #define _CMU_ROUTELOC0_CLKOUT0LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */ #define _CMU_ROUTELOC0_CLKOUT0LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */ #define _CMU_ROUTELOC0_CLKOUT0LOC_LOC6 0x00000006UL /**< Mode LOC6 for CMU_ROUTELOC0 */ #define _CMU_ROUTELOC0_CLKOUT0LOC_LOC7 0x00000007UL /**< Mode LOC7 for CMU_ROUTELOC0 */ #define CMU_ROUTELOC0_CLKOUT0LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC0 << 0) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */ #define CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */ #define CMU_ROUTELOC0_CLKOUT0LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC1 << 0) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */ #define CMU_ROUTELOC0_CLKOUT0LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC2 << 0) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */ #define CMU_ROUTELOC0_CLKOUT0LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC3 << 0) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */ #define CMU_ROUTELOC0_CLKOUT0LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC4 << 0) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */ #define CMU_ROUTELOC0_CLKOUT0LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC5 << 0) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */ #define CMU_ROUTELOC0_CLKOUT0LOC_LOC6 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC6 << 0) /**< Shifted mode LOC6 for CMU_ROUTELOC0 */ #define CMU_ROUTELOC0_CLKOUT0LOC_LOC7 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC7 << 0) /**< Shifted mode LOC7 for CMU_ROUTELOC0 */ #define _CMU_ROUTELOC0_CLKOUT1LOC_SHIFT 8 /**< Shift value for CMU_CLKOUT1LOC */ #define _CMU_ROUTELOC0_CLKOUT1LOC_MASK 0x700UL /**< Bit mask for CMU_CLKOUT1LOC */ #define _CMU_ROUTELOC0_CLKOUT1LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */ #define _CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */ #define _CMU_ROUTELOC0_CLKOUT1LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */ #define _CMU_ROUTELOC0_CLKOUT1LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */ #define _CMU_ROUTELOC0_CLKOUT1LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */ #define _CMU_ROUTELOC0_CLKOUT1LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */ #define _CMU_ROUTELOC0_CLKOUT1LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */ #define _CMU_ROUTELOC0_CLKOUT1LOC_LOC6 0x00000006UL /**< Mode LOC6 for CMU_ROUTELOC0 */ #define _CMU_ROUTELOC0_CLKOUT1LOC_LOC7 0x00000007UL /**< Mode LOC7 for CMU_ROUTELOC0 */ #define CMU_ROUTELOC0_CLKOUT1LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC0 << 8) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */ #define CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */ #define CMU_ROUTELOC0_CLKOUT1LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC1 << 8) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */ #define CMU_ROUTELOC0_CLKOUT1LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC2 << 8) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */ #define CMU_ROUTELOC0_CLKOUT1LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC3 << 8) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */ #define CMU_ROUTELOC0_CLKOUT1LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC4 << 8) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */ #define CMU_ROUTELOC0_CLKOUT1LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC5 << 8) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */ #define CMU_ROUTELOC0_CLKOUT1LOC_LOC6 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC6 << 8) /**< Shifted mode LOC6 for CMU_ROUTELOC0 */ #define CMU_ROUTELOC0_CLKOUT1LOC_LOC7 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC7 << 8) /**< Shifted mode LOC7 for CMU_ROUTELOC0 */ /* Bit fields for CMU ROUTELOC1 */ #define _CMU_ROUTELOC1_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTELOC1 */ #define _CMU_ROUTELOC1_MASK 0x00000007UL /**< Mask for CMU_ROUTELOC1 */ #define _CMU_ROUTELOC1_CLKIN0LOC_SHIFT 0 /**< Shift value for CMU_CLKIN0LOC */ #define _CMU_ROUTELOC1_CLKIN0LOC_MASK 0x7UL /**< Bit mask for CMU_CLKIN0LOC */ #define _CMU_ROUTELOC1_CLKIN0LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC1 */ #define _CMU_ROUTELOC1_CLKIN0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC1 */ #define _CMU_ROUTELOC1_CLKIN0LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC1 */ #define _CMU_ROUTELOC1_CLKIN0LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC1 */ #define _CMU_ROUTELOC1_CLKIN0LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC1 */ #define _CMU_ROUTELOC1_CLKIN0LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC1 */ #define CMU_ROUTELOC1_CLKIN0LOC_LOC0 (_CMU_ROUTELOC1_CLKIN0LOC_LOC0 << 0) /**< Shifted mode LOC0 for CMU_ROUTELOC1 */ #define CMU_ROUTELOC1_CLKIN0LOC_DEFAULT (_CMU_ROUTELOC1_CLKIN0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTELOC1 */ #define CMU_ROUTELOC1_CLKIN0LOC_LOC1 (_CMU_ROUTELOC1_CLKIN0LOC_LOC1 << 0) /**< Shifted mode LOC1 for CMU_ROUTELOC1 */ #define CMU_ROUTELOC1_CLKIN0LOC_LOC2 (_CMU_ROUTELOC1_CLKIN0LOC_LOC2 << 0) /**< Shifted mode LOC2 for CMU_ROUTELOC1 */ #define CMU_ROUTELOC1_CLKIN0LOC_LOC3 (_CMU_ROUTELOC1_CLKIN0LOC_LOC3 << 0) /**< Shifted mode LOC3 for CMU_ROUTELOC1 */ #define CMU_ROUTELOC1_CLKIN0LOC_LOC4 (_CMU_ROUTELOC1_CLKIN0LOC_LOC4 << 0) /**< Shifted mode LOC4 for CMU_ROUTELOC1 */ /* Bit fields for CMU LOCK */ #define _CMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for CMU_LOCK */ #define _CMU_LOCK_MASK 0x0000FFFFUL /**< Mask for CMU_LOCK */ #define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */ #define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */ #define _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LOCK */ #define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for CMU_LOCK */ #define _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_LOCK */ #define _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_LOCK */ #define _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for CMU_LOCK */ #define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LOCK */ #define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for CMU_LOCK */ #define CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for CMU_LOCK */ #define CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for CMU_LOCK */ #define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */ /* Bit fields for CMU HFRCOSS */ #define _CMU_HFRCOSS_RESETVALUE 0x00000000UL /**< Default value for CMU_HFRCOSS */ #define _CMU_HFRCOSS_MASK 0x00001F07UL /**< Mask for CMU_HFRCOSS */ #define _CMU_HFRCOSS_SSAMP_SHIFT 0 /**< Shift value for CMU_SSAMP */ #define _CMU_HFRCOSS_SSAMP_MASK 0x7UL /**< Bit mask for CMU_SSAMP */ #define _CMU_HFRCOSS_SSAMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOSS */ #define CMU_HFRCOSS_SSAMP_DEFAULT (_CMU_HFRCOSS_SSAMP_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOSS */ #define _CMU_HFRCOSS_SSINV_SHIFT 8 /**< Shift value for CMU_SSINV */ #define _CMU_HFRCOSS_SSINV_MASK 0x1F00UL /**< Bit mask for CMU_SSINV */ #define _CMU_HFRCOSS_SSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOSS */ #define CMU_HFRCOSS_SSINV_DEFAULT (_CMU_HFRCOSS_SSINV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOSS */ /** @} */ /** @} End of group EFR32MG12P_CMU */ /** @} End of group Parts */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_cryotimer.h.
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/***************************************************************************//** * @file * @brief EFR32MG12P_CRYOTIMER register and bit field definitions * @version 5.7.0 ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * SPDX-License-Identifier: Zlib * * The licensor of this software is Silicon Laboratories Inc. * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be * appreciated but is not required. * 2. Altered source versions must be plainly marked as such, and must not be * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * ******************************************************************************/ #if defined(__ICCARM__) #pragma system_include /* Treat file as system include file. */ #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang system_header /* Treat file as system include file. */ #endif /***************************************************************************//** * @addtogroup Parts * @{ ******************************************************************************/ /***************************************************************************//** * @defgroup EFR32MG12P_CRYOTIMER CRYOTIMER * @{ * @brief EFR32MG12P_CRYOTIMER Register Declaration ******************************************************************************/ /** CRYOTIMER Register Declaration */ typedef struct { __IOM uint32_t CTRL; /**< Control Register */ __IOM uint32_t PERIODSEL; /**< Interrupt Duration */ __IM uint32_t CNT; /**< Counter Value */ __IOM uint32_t EM4WUEN; /**< Wake Up Enable */ __IM uint32_t IF; /**< Interrupt Flag Register */ __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ __IOM uint32_t IEN; /**< Interrupt Enable Register */ } CRYOTIMER_TypeDef; /** @} */ /***************************************************************************//** * @addtogroup EFR32MG12P_CRYOTIMER * @{ * @defgroup EFR32MG12P_CRYOTIMER_BitFields CRYOTIMER Bit Fields * @{ ******************************************************************************/ /* Bit fields for CRYOTIMER CTRL */ #define _CRYOTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for CRYOTIMER_CTRL */ #define _CRYOTIMER_CTRL_MASK 0x000000EFUL /**< Mask for CRYOTIMER_CTRL */ #define CRYOTIMER_CTRL_EN (0x1UL << 0) /**< Enable CRYOTIMER */ #define _CRYOTIMER_CTRL_EN_SHIFT 0 /**< Shift value for CRYOTIMER_EN */ #define _CRYOTIMER_CTRL_EN_MASK 0x1UL /**< Bit mask for CRYOTIMER_EN */ #define _CRYOTIMER_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_CTRL */ #define CRYOTIMER_CTRL_EN_DEFAULT (_CRYOTIMER_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_CTRL */ #define CRYOTIMER_CTRL_DEBUGRUN (0x1UL << 1) /**< Debug Mode Run Enable */ #define _CRYOTIMER_CTRL_DEBUGRUN_SHIFT 1 /**< Shift value for CRYOTIMER_DEBUGRUN */ #define _CRYOTIMER_CTRL_DEBUGRUN_MASK 0x2UL /**< Bit mask for CRYOTIMER_DEBUGRUN */ #define _CRYOTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_CTRL */ #define CRYOTIMER_CTRL_DEBUGRUN_DEFAULT (_CRYOTIMER_CTRL_DEBUGRUN_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYOTIMER_CTRL */ #define _CRYOTIMER_CTRL_OSCSEL_SHIFT 2 /**< Shift value for CRYOTIMER_OSCSEL */ #define _CRYOTIMER_CTRL_OSCSEL_MASK 0xCUL /**< Bit mask for CRYOTIMER_OSCSEL */ #define _CRYOTIMER_CTRL_OSCSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_CTRL */ #define _CRYOTIMER_CTRL_OSCSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CRYOTIMER_CTRL */ #define _CRYOTIMER_CTRL_OSCSEL_LFRCO 0x00000001UL /**< Mode LFRCO for CRYOTIMER_CTRL */ #define _CRYOTIMER_CTRL_OSCSEL_LFXO 0x00000002UL /**< Mode LFXO for CRYOTIMER_CTRL */ #define _CRYOTIMER_CTRL_OSCSEL_ULFRCO 0x00000003UL /**< Mode ULFRCO for CRYOTIMER_CTRL */ #define CRYOTIMER_CTRL_OSCSEL_DEFAULT (_CRYOTIMER_CTRL_OSCSEL_DEFAULT << 2) /**< Shifted mode DEFAULT for CRYOTIMER_CTRL */ #define CRYOTIMER_CTRL_OSCSEL_DISABLED (_CRYOTIMER_CTRL_OSCSEL_DISABLED << 2) /**< Shifted mode DISABLED for CRYOTIMER_CTRL */ #define CRYOTIMER_CTRL_OSCSEL_LFRCO (_CRYOTIMER_CTRL_OSCSEL_LFRCO << 2) /**< Shifted mode LFRCO for CRYOTIMER_CTRL */ #define CRYOTIMER_CTRL_OSCSEL_LFXO (_CRYOTIMER_CTRL_OSCSEL_LFXO << 2) /**< Shifted mode LFXO for CRYOTIMER_CTRL */ #define CRYOTIMER_CTRL_OSCSEL_ULFRCO (_CRYOTIMER_CTRL_OSCSEL_ULFRCO << 2) /**< Shifted mode ULFRCO for CRYOTIMER_CTRL */ #define _CRYOTIMER_CTRL_PRESC_SHIFT 5 /**< Shift value for CRYOTIMER_PRESC */ #define _CRYOTIMER_CTRL_PRESC_MASK 0xE0UL /**< Bit mask for CRYOTIMER_PRESC */ #define _CRYOTIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_CTRL */ #define _CRYOTIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for CRYOTIMER_CTRL */ #define _CRYOTIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for CRYOTIMER_CTRL */ #define _CRYOTIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for CRYOTIMER_CTRL */ #define _CRYOTIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for CRYOTIMER_CTRL */ #define _CRYOTIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for CRYOTIMER_CTRL */ #define _CRYOTIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for CRYOTIMER_CTRL */ #define _CRYOTIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for CRYOTIMER_CTRL */ #define _CRYOTIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for CRYOTIMER_CTRL */ #define CRYOTIMER_CTRL_PRESC_DEFAULT (_CRYOTIMER_CTRL_PRESC_DEFAULT << 5) /**< Shifted mode DEFAULT for CRYOTIMER_CTRL */ #define CRYOTIMER_CTRL_PRESC_DIV1 (_CRYOTIMER_CTRL_PRESC_DIV1 << 5) /**< Shifted mode DIV1 for CRYOTIMER_CTRL */ #define CRYOTIMER_CTRL_PRESC_DIV2 (_CRYOTIMER_CTRL_PRESC_DIV2 << 5) /**< Shifted mode DIV2 for CRYOTIMER_CTRL */ #define CRYOTIMER_CTRL_PRESC_DIV4 (_CRYOTIMER_CTRL_PRESC_DIV4 << 5) /**< Shifted mode DIV4 for CRYOTIMER_CTRL */ #define CRYOTIMER_CTRL_PRESC_DIV8 (_CRYOTIMER_CTRL_PRESC_DIV8 << 5) /**< Shifted mode DIV8 for CRYOTIMER_CTRL */ #define CRYOTIMER_CTRL_PRESC_DIV16 (_CRYOTIMER_CTRL_PRESC_DIV16 << 5) /**< Shifted mode DIV16 for CRYOTIMER_CTRL */ #define CRYOTIMER_CTRL_PRESC_DIV32 (_CRYOTIMER_CTRL_PRESC_DIV32 << 5) /**< Shifted mode DIV32 for CRYOTIMER_CTRL */ #define CRYOTIMER_CTRL_PRESC_DIV64 (_CRYOTIMER_CTRL_PRESC_DIV64 << 5) /**< Shifted mode DIV64 for CRYOTIMER_CTRL */ #define CRYOTIMER_CTRL_PRESC_DIV128 (_CRYOTIMER_CTRL_PRESC_DIV128 << 5) /**< Shifted mode DIV128 for CRYOTIMER_CTRL */ /* Bit fields for CRYOTIMER PERIODSEL */ #define _CRYOTIMER_PERIODSEL_RESETVALUE 0x00000020UL /**< Default value for CRYOTIMER_PERIODSEL */ #define _CRYOTIMER_PERIODSEL_MASK 0x0000003FUL /**< Mask for CRYOTIMER_PERIODSEL */ #define _CRYOTIMER_PERIODSEL_PERIODSEL_SHIFT 0 /**< Shift value for CRYOTIMER_PERIODSEL */ #define _CRYOTIMER_PERIODSEL_PERIODSEL_MASK 0x3FUL /**< Bit mask for CRYOTIMER_PERIODSEL */ #define _CRYOTIMER_PERIODSEL_PERIODSEL_DEFAULT 0x00000020UL /**< Mode DEFAULT for CRYOTIMER_PERIODSEL */ #define CRYOTIMER_PERIODSEL_PERIODSEL_DEFAULT (_CRYOTIMER_PERIODSEL_PERIODSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_PERIODSEL */ /* Bit fields for CRYOTIMER CNT */ #define _CRYOTIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for CRYOTIMER_CNT */ #define _CRYOTIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for CRYOTIMER_CNT */ #define _CRYOTIMER_CNT_CNT_SHIFT 0 /**< Shift value for CRYOTIMER_CNT */ #define _CRYOTIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for CRYOTIMER_CNT */ #define _CRYOTIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_CNT */ #define CRYOTIMER_CNT_CNT_DEFAULT (_CRYOTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_CNT */ /* Bit fields for CRYOTIMER EM4WUEN */ #define _CRYOTIMER_EM4WUEN_RESETVALUE 0x00000000UL /**< Default value for CRYOTIMER_EM4WUEN */ #define _CRYOTIMER_EM4WUEN_MASK 0x00000001UL /**< Mask for CRYOTIMER_EM4WUEN */ #define CRYOTIMER_EM4WUEN_EM4WU (0x1UL << 0) /**< EM4 Wake-up Enable */ #define _CRYOTIMER_EM4WUEN_EM4WU_SHIFT 0 /**< Shift value for CRYOTIMER_EM4WU */ #define _CRYOTIMER_EM4WUEN_EM4WU_MASK 0x1UL /**< Bit mask for CRYOTIMER_EM4WU */ #define _CRYOTIMER_EM4WUEN_EM4WU_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_EM4WUEN */ #define CRYOTIMER_EM4WUEN_EM4WU_DEFAULT (_CRYOTIMER_EM4WUEN_EM4WU_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_EM4WUEN */ /* Bit fields for CRYOTIMER IF */ #define _CRYOTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for CRYOTIMER_IF */ #define _CRYOTIMER_IF_MASK 0x00000001UL /**< Mask for CRYOTIMER_IF */ #define CRYOTIMER_IF_PERIOD (0x1UL << 0) /**< Wakeup Event/Interrupt */ #define _CRYOTIMER_IF_PERIOD_SHIFT 0 /**< Shift value for CRYOTIMER_PERIOD */ #define _CRYOTIMER_IF_PERIOD_MASK 0x1UL /**< Bit mask for CRYOTIMER_PERIOD */ #define _CRYOTIMER_IF_PERIOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_IF */ #define CRYOTIMER_IF_PERIOD_DEFAULT (_CRYOTIMER_IF_PERIOD_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_IF */ /* Bit fields for CRYOTIMER IFS */ #define _CRYOTIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for CRYOTIMER_IFS */ #define _CRYOTIMER_IFS_MASK 0x00000001UL /**< Mask for CRYOTIMER_IFS */ #define CRYOTIMER_IFS_PERIOD (0x1UL << 0) /**< Set PERIOD Interrupt Flag */ #define _CRYOTIMER_IFS_PERIOD_SHIFT 0 /**< Shift value for CRYOTIMER_PERIOD */ #define _CRYOTIMER_IFS_PERIOD_MASK 0x1UL /**< Bit mask for CRYOTIMER_PERIOD */ #define _CRYOTIMER_IFS_PERIOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_IFS */ #define CRYOTIMER_IFS_PERIOD_DEFAULT (_CRYOTIMER_IFS_PERIOD_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_IFS */ /* Bit fields for CRYOTIMER IFC */ #define _CRYOTIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for CRYOTIMER_IFC */ #define _CRYOTIMER_IFC_MASK 0x00000001UL /**< Mask for CRYOTIMER_IFC */ #define CRYOTIMER_IFC_PERIOD (0x1UL << 0) /**< Clear PERIOD Interrupt Flag */ #define _CRYOTIMER_IFC_PERIOD_SHIFT 0 /**< Shift value for CRYOTIMER_PERIOD */ #define _CRYOTIMER_IFC_PERIOD_MASK 0x1UL /**< Bit mask for CRYOTIMER_PERIOD */ #define _CRYOTIMER_IFC_PERIOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_IFC */ #define CRYOTIMER_IFC_PERIOD_DEFAULT (_CRYOTIMER_IFC_PERIOD_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_IFC */ /* Bit fields for CRYOTIMER IEN */ #define _CRYOTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for CRYOTIMER_IEN */ #define _CRYOTIMER_IEN_MASK 0x00000001UL /**< Mask for CRYOTIMER_IEN */ #define CRYOTIMER_IEN_PERIOD (0x1UL << 0) /**< PERIOD Interrupt Enable */ #define _CRYOTIMER_IEN_PERIOD_SHIFT 0 /**< Shift value for CRYOTIMER_PERIOD */ #define _CRYOTIMER_IEN_PERIOD_MASK 0x1UL /**< Bit mask for CRYOTIMER_PERIOD */ #define _CRYOTIMER_IEN_PERIOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_IEN */ #define CRYOTIMER_IEN_PERIOD_DEFAULT (_CRYOTIMER_IEN_PERIOD_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_IEN */ /** @} */ /** @} End of group EFR32MG12P_CRYOTIMER */ /** @} End of group Parts */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_crypto.h.
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/***************************************************************************//** * @file * @brief EFR32MG12P_CRYPTO register and bit field definitions * @version 5.7.0 ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * SPDX-License-Identifier: Zlib * * The licensor of this software is Silicon Laboratories Inc. * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be * appreciated but is not required. * 2. Altered source versions must be plainly marked as such, and must not be * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * ******************************************************************************/ #if defined(__ICCARM__) #pragma system_include /* Treat file as system include file. */ #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang system_header /* Treat file as system include file. */ #endif /***************************************************************************//** * @addtogroup Parts * @{ ******************************************************************************/ /***************************************************************************//** * @defgroup EFR32MG12P_CRYPTO CRYPTO * @{ * @brief EFR32MG12P_CRYPTO Register Declaration ******************************************************************************/ /** CRYPTO Register Declaration */ typedef struct { __IOM uint32_t CTRL; /**< Control Register */ __IOM uint32_t WAC; /**< Wide Arithmetic Configuration */ __IOM uint32_t CMD; /**< Command Register */ uint32_t RESERVED0[1U]; /**< Reserved for future use **/ __IM uint32_t STATUS; /**< Status Register */ __IM uint32_t DSTATUS; /**< Data Status Register */ __IM uint32_t CSTATUS; /**< Control Status Register */ uint32_t RESERVED1[1U]; /**< Reserved for future use **/ __IOM uint32_t KEY; /**< KEY Register Access */ __IOM uint32_t KEYBUF; /**< KEY Buffer Register Access */ uint32_t RESERVED2[2U]; /**< Reserved for future use **/ __IOM uint32_t SEQCTRL; /**< Sequence Control */ __IOM uint32_t SEQCTRLB; /**< Sequence Control B */ uint32_t RESERVED3[2U]; /**< Reserved for future use **/ __IM uint32_t IF; /**< AES Interrupt Flags */ __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ __IOM uint32_t IEN; /**< Interrupt Enable Register */ __IOM uint32_t SEQ0; /**< Sequence Register 0 */ __IOM uint32_t SEQ1; /**< Sequence Register 1 */ __IOM uint32_t SEQ2; /**< Sequence Register 2 */ __IOM uint32_t SEQ3; /**< Sequence Register 3 */ __IOM uint32_t SEQ4; /**< Sequence Register 4 */ uint32_t RESERVED4[7U]; /**< Reserved for future use **/ __IOM uint32_t DATA0; /**< DATA0 Register Access */ __IOM uint32_t DATA1; /**< DATA1 Register Access */ __IOM uint32_t DATA2; /**< DATA2 Register Access */ __IOM uint32_t DATA3; /**< DATA3 Register Access */ uint32_t RESERVED5[4U]; /**< Reserved for future use **/ __IOM uint32_t DATA0XOR; /**< DATA0XOR Register Access */ uint32_t RESERVED6[3U]; /**< Reserved for future use **/ __IOM uint32_t DATA0BYTE; /**< DATA0 Register Byte Access */ __IOM uint32_t DATA1BYTE; /**< DATA1 Register Byte Access */ uint32_t RESERVED7[1U]; /**< Reserved for future use **/ __IOM uint32_t DATA0XORBYTE; /**< DATA0 Register Byte XOR Access */ __IOM uint32_t DATA0BYTE12; /**< DATA0 Register Byte 12 Access */ __IOM uint32_t DATA0BYTE13; /**< DATA0 Register Byte 13 Access */ __IOM uint32_t DATA0BYTE14; /**< DATA0 Register Byte 14 Access */ __IOM uint32_t DATA0BYTE15; /**< DATA0 Register Byte 15 Access */ uint32_t RESERVED8[12U]; /**< Reserved for future use **/ __IOM uint32_t DDATA0; /**< DDATA0 Register Access */ __IOM uint32_t DDATA1; /**< DDATA1 Register Access */ __IOM uint32_t DDATA2; /**< DDATA2 Register Access */ __IOM uint32_t DDATA3; /**< DDATA3 Register Access */ __IOM uint32_t DDATA4; /**< DDATA4 Register Access */ uint32_t RESERVED9[7U]; /**< Reserved for future use **/ __IOM uint32_t DDATA0BIG; /**< DDATA0 Register Big Endian Access */ uint32_t RESERVED10[3U]; /**< Reserved for future use **/ __IOM uint32_t DDATA0BYTE; /**< DDATA0 Register Byte Access */ __IOM uint32_t DDATA1BYTE; /**< DDATA1 Register Byte Access */ __IOM uint32_t DDATA0BYTE32; /**< DDATA0 Register Byte 32 Access */ uint32_t RESERVED11[13U]; /**< Reserved for future use **/ __IOM uint32_t QDATA0; /**< QDATA0 Register Access */ __IOM uint32_t QDATA1; /**< QDATA1 Register Access */ uint32_t RESERVED12[7U]; /**< Reserved for future use **/ __IOM uint32_t QDATA1BIG; /**< QDATA1 Register Big Endian Access */ uint32_t RESERVED13[6U]; /**< Reserved for future use **/ __IOM uint32_t QDATA0BYTE; /**< QDATA0 Register Byte Access */ __IOM uint32_t QDATA1BYTE; /**< QDATA1 Register Byte Access */ } CRYPTO_TypeDef; /** @} */ /***************************************************************************//** * @addtogroup EFR32MG12P_CRYPTO * @{ * @defgroup EFR32MG12P_CRYPTO_BitFields CRYPTO Bit Fields * @{ ******************************************************************************/ /* Bit fields for CRYPTO CTRL */ #define _CRYPTO_CTRL_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_CTRL */ #define _CRYPTO_CTRL_MASK 0xB333C407UL /**< Mask for CRYPTO_CTRL */ #define CRYPTO_CTRL_AES (0x1UL << 0) /**< AES Mode */ #define _CRYPTO_CTRL_AES_SHIFT 0 /**< Shift value for CRYPTO_AES */ #define _CRYPTO_CTRL_AES_MASK 0x1UL /**< Bit mask for CRYPTO_AES */ #define _CRYPTO_CTRL_AES_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CTRL */ #define _CRYPTO_CTRL_AES_AES128 0x00000000UL /**< Mode AES128 for CRYPTO_CTRL */ #define _CRYPTO_CTRL_AES_AES256 0x00000001UL /**< Mode AES256 for CRYPTO_CTRL */ #define CRYPTO_CTRL_AES_DEFAULT (_CRYPTO_CTRL_AES_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_CTRL */ #define CRYPTO_CTRL_AES_AES128 (_CRYPTO_CTRL_AES_AES128 << 0) /**< Shifted mode AES128 for CRYPTO_CTRL */ #define CRYPTO_CTRL_AES_AES256 (_CRYPTO_CTRL_AES_AES256 << 0) /**< Shifted mode AES256 for CRYPTO_CTRL */ #define CRYPTO_CTRL_KEYBUFDIS (0x1UL << 1) /**< Key Buffer Disable */ #define _CRYPTO_CTRL_KEYBUFDIS_SHIFT 1 /**< Shift value for CRYPTO_KEYBUFDIS */ #define _CRYPTO_CTRL_KEYBUFDIS_MASK 0x2UL /**< Bit mask for CRYPTO_KEYBUFDIS */ #define _CRYPTO_CTRL_KEYBUFDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CTRL */ #define CRYPTO_CTRL_KEYBUFDIS_DEFAULT (_CRYPTO_CTRL_KEYBUFDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYPTO_CTRL */ #define CRYPTO_CTRL_SHA (0x1UL << 2) /**< SHA Mode */ #define _CRYPTO_CTRL_SHA_SHIFT 2 /**< Shift value for CRYPTO_SHA */ #define _CRYPTO_CTRL_SHA_MASK 0x4UL /**< Bit mask for CRYPTO_SHA */ #define _CRYPTO_CTRL_SHA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CTRL */ #define _CRYPTO_CTRL_SHA_SHA1 0x00000000UL /**< Mode SHA1 for CRYPTO_CTRL */ #define _CRYPTO_CTRL_SHA_SHA2 0x00000001UL /**< Mode SHA2 for CRYPTO_CTRL */ #define CRYPTO_CTRL_SHA_DEFAULT (_CRYPTO_CTRL_SHA_DEFAULT << 2) /**< Shifted mode DEFAULT for CRYPTO_CTRL */ #define CRYPTO_CTRL_SHA_SHA1 (_CRYPTO_CTRL_SHA_SHA1 << 2) /**< Shifted mode SHA1 for CRYPTO_CTRL */ #define CRYPTO_CTRL_SHA_SHA2 (_CRYPTO_CTRL_SHA_SHA2 << 2) /**< Shifted mode SHA2 for CRYPTO_CTRL */ #define CRYPTO_CTRL_NOBUSYSTALL (0x1UL << 10) /**< No Stalling of Bus When Busy */ #define _CRYPTO_CTRL_NOBUSYSTALL_SHIFT 10 /**< Shift value for CRYPTO_NOBUSYSTALL */ #define _CRYPTO_CTRL_NOBUSYSTALL_MASK 0x400UL /**< Bit mask for CRYPTO_NOBUSYSTALL */ #define _CRYPTO_CTRL_NOBUSYSTALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CTRL */ #define CRYPTO_CTRL_NOBUSYSTALL_DEFAULT (_CRYPTO_CTRL_NOBUSYSTALL_DEFAULT << 10) /**< Shifted mode DEFAULT for CRYPTO_CTRL */ #define _CRYPTO_CTRL_INCWIDTH_SHIFT 14 /**< Shift value for CRYPTO_INCWIDTH */ #define _CRYPTO_CTRL_INCWIDTH_MASK 0xC000UL /**< Bit mask for CRYPTO_INCWIDTH */ #define _CRYPTO_CTRL_INCWIDTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CTRL */ #define _CRYPTO_CTRL_INCWIDTH_INCWIDTH1 0x00000000UL /**< Mode INCWIDTH1 for CRYPTO_CTRL */ #define _CRYPTO_CTRL_INCWIDTH_INCWIDTH2 0x00000001UL /**< Mode INCWIDTH2 for CRYPTO_CTRL */ #define _CRYPTO_CTRL_INCWIDTH_INCWIDTH3 0x00000002UL /**< Mode INCWIDTH3 for CRYPTO_CTRL */ #define _CRYPTO_CTRL_INCWIDTH_INCWIDTH4 0x00000003UL /**< Mode INCWIDTH4 for CRYPTO_CTRL */ #define CRYPTO_CTRL_INCWIDTH_DEFAULT (_CRYPTO_CTRL_INCWIDTH_DEFAULT << 14) /**< Shifted mode DEFAULT for CRYPTO_CTRL */ #define CRYPTO_CTRL_INCWIDTH_INCWIDTH1 (_CRYPTO_CTRL_INCWIDTH_INCWIDTH1 << 14) /**< Shifted mode INCWIDTH1 for CRYPTO_CTRL */ #define CRYPTO_CTRL_INCWIDTH_INCWIDTH2 (_CRYPTO_CTRL_INCWIDTH_INCWIDTH2 << 14) /**< Shifted mode INCWIDTH2 for CRYPTO_CTRL */ #define CRYPTO_CTRL_INCWIDTH_INCWIDTH3 (_CRYPTO_CTRL_INCWIDTH_INCWIDTH3 << 14) /**< Shifted mode INCWIDTH3 for CRYPTO_CTRL */ #define CRYPTO_CTRL_INCWIDTH_INCWIDTH4 (_CRYPTO_CTRL_INCWIDTH_INCWIDTH4 << 14) /**< Shifted mode INCWIDTH4 for CRYPTO_CTRL */ #define _CRYPTO_CTRL_DMA0MODE_SHIFT 16 /**< Shift value for CRYPTO_DMA0MODE */ #define _CRYPTO_CTRL_DMA0MODE_MASK 0x30000UL /**< Bit mask for CRYPTO_DMA0MODE */ #define _CRYPTO_CTRL_DMA0MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CTRL */ #define _CRYPTO_CTRL_DMA0MODE_FULL 0x00000000UL /**< Mode FULL for CRYPTO_CTRL */ #define _CRYPTO_CTRL_DMA0MODE_LENLIMIT 0x00000001UL /**< Mode LENLIMIT for CRYPTO_CTRL */ #define _CRYPTO_CTRL_DMA0MODE_FULLBYTE 0x00000002UL /**< Mode FULLBYTE for CRYPTO_CTRL */ #define _CRYPTO_CTRL_DMA0MODE_LENLIMITBYTE 0x00000003UL /**< Mode LENLIMITBYTE for CRYPTO_CTRL */ #define CRYPTO_CTRL_DMA0MODE_DEFAULT (_CRYPTO_CTRL_DMA0MODE_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTO_CTRL */ #define CRYPTO_CTRL_DMA0MODE_FULL (_CRYPTO_CTRL_DMA0MODE_FULL << 16) /**< Shifted mode FULL for CRYPTO_CTRL */ #define CRYPTO_CTRL_DMA0MODE_LENLIMIT (_CRYPTO_CTRL_DMA0MODE_LENLIMIT << 16) /**< Shifted mode LENLIMIT for CRYPTO_CTRL */ #define CRYPTO_CTRL_DMA0MODE_FULLBYTE (_CRYPTO_CTRL_DMA0MODE_FULLBYTE << 16) /**< Shifted mode FULLBYTE for CRYPTO_CTRL */ #define CRYPTO_CTRL_DMA0MODE_LENLIMITBYTE (_CRYPTO_CTRL_DMA0MODE_LENLIMITBYTE << 16) /**< Shifted mode LENLIMITBYTE for CRYPTO_CTRL */ #define _CRYPTO_CTRL_DMA0RSEL_SHIFT 20 /**< Shift value for CRYPTO_DMA0RSEL */ #define _CRYPTO_CTRL_DMA0RSEL_MASK 0x300000UL /**< Bit mask for CRYPTO_DMA0RSEL */ #define _CRYPTO_CTRL_DMA0RSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CTRL */ #define _CRYPTO_CTRL_DMA0RSEL_DATA0 0x00000000UL /**< Mode DATA0 for CRYPTO_CTRL */ #define _CRYPTO_CTRL_DMA0RSEL_DDATA0 0x00000001UL /**< Mode DDATA0 for CRYPTO_CTRL */ #define _CRYPTO_CTRL_DMA0RSEL_DDATA0BIG 0x00000002UL /**< Mode DDATA0BIG for CRYPTO_CTRL */ #define _CRYPTO_CTRL_DMA0RSEL_QDATA0 0x00000003UL /**< Mode QDATA0 for CRYPTO_CTRL */ #define CRYPTO_CTRL_DMA0RSEL_DEFAULT (_CRYPTO_CTRL_DMA0RSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for CRYPTO_CTRL */ #define CRYPTO_CTRL_DMA0RSEL_DATA0 (_CRYPTO_CTRL_DMA0RSEL_DATA0 << 20) /**< Shifted mode DATA0 for CRYPTO_CTRL */ #define CRYPTO_CTRL_DMA0RSEL_DDATA0 (_CRYPTO_CTRL_DMA0RSEL_DDATA0 << 20) /**< Shifted mode DDATA0 for CRYPTO_CTRL */ #define CRYPTO_CTRL_DMA0RSEL_DDATA0BIG (_CRYPTO_CTRL_DMA0RSEL_DDATA0BIG << 20) /**< Shifted mode DDATA0BIG for CRYPTO_CTRL */ #define CRYPTO_CTRL_DMA0RSEL_QDATA0 (_CRYPTO_CTRL_DMA0RSEL_QDATA0 << 20) /**< Shifted mode QDATA0 for CRYPTO_CTRL */ #define _CRYPTO_CTRL_DMA1MODE_SHIFT 24 /**< Shift value for CRYPTO_DMA1MODE */ #define _CRYPTO_CTRL_DMA1MODE_MASK 0x3000000UL /**< Bit mask for CRYPTO_DMA1MODE */ #define _CRYPTO_CTRL_DMA1MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CTRL */ #define _CRYPTO_CTRL_DMA1MODE_FULL 0x00000000UL /**< Mode FULL for CRYPTO_CTRL */ #define _CRYPTO_CTRL_DMA1MODE_LENLIMIT 0x00000001UL /**< Mode LENLIMIT for CRYPTO_CTRL */ #define _CRYPTO_CTRL_DMA1MODE_FULLBYTE 0x00000002UL /**< Mode FULLBYTE for CRYPTO_CTRL */ #define _CRYPTO_CTRL_DMA1MODE_LENLIMITBYTE 0x00000003UL /**< Mode LENLIMITBYTE for CRYPTO_CTRL */ #define CRYPTO_CTRL_DMA1MODE_DEFAULT (_CRYPTO_CTRL_DMA1MODE_DEFAULT << 24) /**< Shifted mode DEFAULT for CRYPTO_CTRL */ #define CRYPTO_CTRL_DMA1MODE_FULL (_CRYPTO_CTRL_DMA1MODE_FULL << 24) /**< Shifted mode FULL for CRYPTO_CTRL */ #define CRYPTO_CTRL_DMA1MODE_LENLIMIT (_CRYPTO_CTRL_DMA1MODE_LENLIMIT << 24) /**< Shifted mode LENLIMIT for CRYPTO_CTRL */ #define CRYPTO_CTRL_DMA1MODE_FULLBYTE (_CRYPTO_CTRL_DMA1MODE_FULLBYTE << 24) /**< Shifted mode FULLBYTE for CRYPTO_CTRL */ #define CRYPTO_CTRL_DMA1MODE_LENLIMITBYTE (_CRYPTO_CTRL_DMA1MODE_LENLIMITBYTE << 24) /**< Shifted mode LENLIMITBYTE for CRYPTO_CTRL */ #define _CRYPTO_CTRL_DMA1RSEL_SHIFT 28 /**< Shift value for CRYPTO_DMA1RSEL */ #define _CRYPTO_CTRL_DMA1RSEL_MASK 0x30000000UL /**< Bit mask for CRYPTO_DMA1RSEL */ #define _CRYPTO_CTRL_DMA1RSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CTRL */ #define _CRYPTO_CTRL_DMA1RSEL_DATA1 0x00000000UL /**< Mode DATA1 for CRYPTO_CTRL */ #define _CRYPTO_CTRL_DMA1RSEL_DDATA1 0x00000001UL /**< Mode DDATA1 for CRYPTO_CTRL */ #define _CRYPTO_CTRL_DMA1RSEL_QDATA1 0x00000002UL /**< Mode QDATA1 for CRYPTO_CTRL */ #define _CRYPTO_CTRL_DMA1RSEL_QDATA1BIG 0x00000003UL /**< Mode QDATA1BIG for CRYPTO_CTRL */ #define CRYPTO_CTRL_DMA1RSEL_DEFAULT (_CRYPTO_CTRL_DMA1RSEL_DEFAULT << 28) /**< Shifted mode DEFAULT for CRYPTO_CTRL */ #define CRYPTO_CTRL_DMA1RSEL_DATA1 (_CRYPTO_CTRL_DMA1RSEL_DATA1 << 28) /**< Shifted mode DATA1 for CRYPTO_CTRL */ #define CRYPTO_CTRL_DMA1RSEL_DDATA1 (_CRYPTO_CTRL_DMA1RSEL_DDATA1 << 28) /**< Shifted mode DDATA1 for CRYPTO_CTRL */ #define CRYPTO_CTRL_DMA1RSEL_QDATA1 (_CRYPTO_CTRL_DMA1RSEL_QDATA1 << 28) /**< Shifted mode QDATA1 for CRYPTO_CTRL */ #define CRYPTO_CTRL_DMA1RSEL_QDATA1BIG (_CRYPTO_CTRL_DMA1RSEL_QDATA1BIG << 28) /**< Shifted mode QDATA1BIG for CRYPTO_CTRL */ #define CRYPTO_CTRL_COMBDMA0WEREQ (0x1UL << 31) /**< Combined Data0 Write DMA Request */ #define _CRYPTO_CTRL_COMBDMA0WEREQ_SHIFT 31 /**< Shift value for CRYPTO_COMBDMA0WEREQ */ #define _CRYPTO_CTRL_COMBDMA0WEREQ_MASK 0x80000000UL /**< Bit mask for CRYPTO_COMBDMA0WEREQ */ #define _CRYPTO_CTRL_COMBDMA0WEREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CTRL */ #define CRYPTO_CTRL_COMBDMA0WEREQ_DEFAULT (_CRYPTO_CTRL_COMBDMA0WEREQ_DEFAULT << 31) /**< Shifted mode DEFAULT for CRYPTO_CTRL */ /* Bit fields for CRYPTO WAC */ #define _CRYPTO_WAC_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_WAC */ #define _CRYPTO_WAC_MASK 0x00000F1FUL /**< Mask for CRYPTO_WAC */ #define _CRYPTO_WAC_MODULUS_SHIFT 0 /**< Shift value for CRYPTO_MODULUS */ #define _CRYPTO_WAC_MODULUS_MASK 0xFUL /**< Bit mask for CRYPTO_MODULUS */ #define _CRYPTO_WAC_MODULUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_WAC */ #define _CRYPTO_WAC_MODULUS_BIN256 0x00000000UL /**< Mode BIN256 for CRYPTO_WAC */ #define _CRYPTO_WAC_MODULUS_BIN128 0x00000001UL /**< Mode BIN128 for CRYPTO_WAC */ #define _CRYPTO_WAC_MODULUS_ECCBIN233P 0x00000002UL /**< Mode ECCBIN233P for CRYPTO_WAC */ #define _CRYPTO_WAC_MODULUS_ECCBIN163P 0x00000003UL /**< Mode ECCBIN163P for CRYPTO_WAC */ #define _CRYPTO_WAC_MODULUS_GCMBIN128 0x00000004UL /**< Mode GCMBIN128 for CRYPTO_WAC */ #define _CRYPTO_WAC_MODULUS_ECCPRIME256P 0x00000005UL /**< Mode ECCPRIME256P for CRYPTO_WAC */ #define _CRYPTO_WAC_MODULUS_ECCPRIME224P 0x00000006UL /**< Mode ECCPRIME224P for CRYPTO_WAC */ #define _CRYPTO_WAC_MODULUS_ECCPRIME192P 0x00000007UL /**< Mode ECCPRIME192P for CRYPTO_WAC */ #define _CRYPTO_WAC_MODULUS_ECCBIN233N 0x00000008UL /**< Mode ECCBIN233N for CRYPTO_WAC */ #define _CRYPTO_WAC_MODULUS_ECCBIN233KN 0x00000009UL /**< Mode ECCBIN233KN for CRYPTO_WAC */ #define _CRYPTO_WAC_MODULUS_ECCBIN163N 0x0000000AUL /**< Mode ECCBIN163N for CRYPTO_WAC */ #define _CRYPTO_WAC_MODULUS_ECCBIN163KN 0x0000000BUL /**< Mode ECCBIN163KN for CRYPTO_WAC */ #define _CRYPTO_WAC_MODULUS_ECCPRIME256N 0x0000000CUL /**< Mode ECCPRIME256N for CRYPTO_WAC */ #define _CRYPTO_WAC_MODULUS_ECCPRIME224N 0x0000000DUL /**< Mode ECCPRIME224N for CRYPTO_WAC */ #define _CRYPTO_WAC_MODULUS_ECCPRIME192N 0x0000000EUL /**< Mode ECCPRIME192N for CRYPTO_WAC */ #define CRYPTO_WAC_MODULUS_DEFAULT (_CRYPTO_WAC_MODULUS_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_WAC */ #define CRYPTO_WAC_MODULUS_BIN256 (_CRYPTO_WAC_MODULUS_BIN256 << 0) /**< Shifted mode BIN256 for CRYPTO_WAC */ #define CRYPTO_WAC_MODULUS_BIN128 (_CRYPTO_WAC_MODULUS_BIN128 << 0) /**< Shifted mode BIN128 for CRYPTO_WAC */ #define CRYPTO_WAC_MODULUS_ECCBIN233P (_CRYPTO_WAC_MODULUS_ECCBIN233P << 0) /**< Shifted mode ECCBIN233P for CRYPTO_WAC */ #define CRYPTO_WAC_MODULUS_ECCBIN163P (_CRYPTO_WAC_MODULUS_ECCBIN163P << 0) /**< Shifted mode ECCBIN163P for CRYPTO_WAC */ #define CRYPTO_WAC_MODULUS_GCMBIN128 (_CRYPTO_WAC_MODULUS_GCMBIN128 << 0) /**< Shifted mode GCMBIN128 for CRYPTO_WAC */ #define CRYPTO_WAC_MODULUS_ECCPRIME256P (_CRYPTO_WAC_MODULUS_ECCPRIME256P << 0) /**< Shifted mode ECCPRIME256P for CRYPTO_WAC */ #define CRYPTO_WAC_MODULUS_ECCPRIME224P (_CRYPTO_WAC_MODULUS_ECCPRIME224P << 0) /**< Shifted mode ECCPRIME224P for CRYPTO_WAC */ #define CRYPTO_WAC_MODULUS_ECCPRIME192P (_CRYPTO_WAC_MODULUS_ECCPRIME192P << 0) /**< Shifted mode ECCPRIME192P for CRYPTO_WAC */ #define CRYPTO_WAC_MODULUS_ECCBIN233N (_CRYPTO_WAC_MODULUS_ECCBIN233N << 0) /**< Shifted mode ECCBIN233N for CRYPTO_WAC */ #define CRYPTO_WAC_MODULUS_ECCBIN233KN (_CRYPTO_WAC_MODULUS_ECCBIN233KN << 0) /**< Shifted mode ECCBIN233KN for CRYPTO_WAC */ #define CRYPTO_WAC_MODULUS_ECCBIN163N (_CRYPTO_WAC_MODULUS_ECCBIN163N << 0) /**< Shifted mode ECCBIN163N for CRYPTO_WAC */ #define CRYPTO_WAC_MODULUS_ECCBIN163KN (_CRYPTO_WAC_MODULUS_ECCBIN163KN << 0) /**< Shifted mode ECCBIN163KN for CRYPTO_WAC */ #define CRYPTO_WAC_MODULUS_ECCPRIME256N (_CRYPTO_WAC_MODULUS_ECCPRIME256N << 0) /**< Shifted mode ECCPRIME256N for CRYPTO_WAC */ #define CRYPTO_WAC_MODULUS_ECCPRIME224N (_CRYPTO_WAC_MODULUS_ECCPRIME224N << 0) /**< Shifted mode ECCPRIME224N for CRYPTO_WAC */ #define CRYPTO_WAC_MODULUS_ECCPRIME192N (_CRYPTO_WAC_MODULUS_ECCPRIME192N << 0) /**< Shifted mode ECCPRIME192N for CRYPTO_WAC */ #define CRYPTO_WAC_MODOP (0x1UL << 4) /**< Modular Operation Field Type */ #define _CRYPTO_WAC_MODOP_SHIFT 4 /**< Shift value for CRYPTO_MODOP */ #define _CRYPTO_WAC_MODOP_MASK 0x10UL /**< Bit mask for CRYPTO_MODOP */ #define _CRYPTO_WAC_MODOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_WAC */ #define _CRYPTO_WAC_MODOP_BINARY 0x00000000UL /**< Mode BINARY for CRYPTO_WAC */ #define _CRYPTO_WAC_MODOP_REGULAR 0x00000001UL /**< Mode REGULAR for CRYPTO_WAC */ #define CRYPTO_WAC_MODOP_DEFAULT (_CRYPTO_WAC_MODOP_DEFAULT << 4) /**< Shifted mode DEFAULT for CRYPTO_WAC */ #define CRYPTO_WAC_MODOP_BINARY (_CRYPTO_WAC_MODOP_BINARY << 4) /**< Shifted mode BINARY for CRYPTO_WAC */ #define CRYPTO_WAC_MODOP_REGULAR (_CRYPTO_WAC_MODOP_REGULAR << 4) /**< Shifted mode REGULAR for CRYPTO_WAC */ #define _CRYPTO_WAC_MULWIDTH_SHIFT 8 /**< Shift value for CRYPTO_MULWIDTH */ #define _CRYPTO_WAC_MULWIDTH_MASK 0x300UL /**< Bit mask for CRYPTO_MULWIDTH */ #define _CRYPTO_WAC_MULWIDTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_WAC */ #define _CRYPTO_WAC_MULWIDTH_MUL256 0x00000000UL /**< Mode MUL256 for CRYPTO_WAC */ #define _CRYPTO_WAC_MULWIDTH_MUL128 0x00000001UL /**< Mode MUL128 for CRYPTO_WAC */ #define _CRYPTO_WAC_MULWIDTH_MULMOD 0x00000002UL /**< Mode MULMOD for CRYPTO_WAC */ #define CRYPTO_WAC_MULWIDTH_DEFAULT (_CRYPTO_WAC_MULWIDTH_DEFAULT << 8) /**< Shifted mode DEFAULT for CRYPTO_WAC */ #define CRYPTO_WAC_MULWIDTH_MUL256 (_CRYPTO_WAC_MULWIDTH_MUL256 << 8) /**< Shifted mode MUL256 for CRYPTO_WAC */ #define CRYPTO_WAC_MULWIDTH_MUL128 (_CRYPTO_WAC_MULWIDTH_MUL128 << 8) /**< Shifted mode MUL128 for CRYPTO_WAC */ #define CRYPTO_WAC_MULWIDTH_MULMOD (_CRYPTO_WAC_MULWIDTH_MULMOD << 8) /**< Shifted mode MULMOD for CRYPTO_WAC */ #define _CRYPTO_WAC_RESULTWIDTH_SHIFT 10 /**< Shift value for CRYPTO_RESULTWIDTH */ #define _CRYPTO_WAC_RESULTWIDTH_MASK 0xC00UL /**< Bit mask for CRYPTO_RESULTWIDTH */ #define _CRYPTO_WAC_RESULTWIDTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_WAC */ #define _CRYPTO_WAC_RESULTWIDTH_256BIT 0x00000000UL /**< Mode 256BIT for CRYPTO_WAC */ #define _CRYPTO_WAC_RESULTWIDTH_128BIT 0x00000001UL /**< Mode 128BIT for CRYPTO_WAC */ #define _CRYPTO_WAC_RESULTWIDTH_260BIT 0x00000002UL /**< Mode 260BIT for CRYPTO_WAC */ #define CRYPTO_WAC_RESULTWIDTH_DEFAULT (_CRYPTO_WAC_RESULTWIDTH_DEFAULT << 10) /**< Shifted mode DEFAULT for CRYPTO_WAC */ #define CRYPTO_WAC_RESULTWIDTH_256BIT (_CRYPTO_WAC_RESULTWIDTH_256BIT << 10) /**< Shifted mode 256BIT for CRYPTO_WAC */ #define CRYPTO_WAC_RESULTWIDTH_128BIT (_CRYPTO_WAC_RESULTWIDTH_128BIT << 10) /**< Shifted mode 128BIT for CRYPTO_WAC */ #define CRYPTO_WAC_RESULTWIDTH_260BIT (_CRYPTO_WAC_RESULTWIDTH_260BIT << 10) /**< Shifted mode 260BIT for CRYPTO_WAC */ /* Bit fields for CRYPTO CMD */ #define _CRYPTO_CMD_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_CMD */ #define _CRYPTO_CMD_MASK 0x00000EFFUL /**< Mask for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_SHIFT 0 /**< Shift value for CRYPTO_INSTR */ #define _CRYPTO_CMD_INSTR_MASK 0xFFUL /**< Bit mask for CRYPTO_INSTR */ #define _CRYPTO_CMD_INSTR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_END 0x00000000UL /**< Mode END for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_EXEC 0x00000001UL /**< Mode EXEC for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_DATA1INC 0x00000003UL /**< Mode DATA1INC for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_DATA1INCCLR 0x00000004UL /**< Mode DATA1INCCLR for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_AESENC 0x00000005UL /**< Mode AESENC for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_AESDEC 0x00000006UL /**< Mode AESDEC for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_SHA 0x00000007UL /**< Mode SHA for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_ADD 0x00000008UL /**< Mode ADD for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_ADDC 0x00000009UL /**< Mode ADDC for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_LADD 0x0000000AUL /**< Mode LADD for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_LADDC 0x0000000BUL /**< Mode LADDC for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_MADD 0x0000000CUL /**< Mode MADD for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_MADD32 0x0000000DUL /**< Mode MADD32 for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_SUB 0x00000010UL /**< Mode SUB for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_SUBC 0x00000011UL /**< Mode SUBC for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_LSUB 0x00000012UL /**< Mode LSUB for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_LSUBC 0x00000013UL /**< Mode LSUBC for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_MSUB 0x00000014UL /**< Mode MSUB for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_MUL 0x00000018UL /**< Mode MUL for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_MULC 0x00000019UL /**< Mode MULC for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_LMUL 0x0000001AUL /**< Mode LMUL for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_MMUL 0x0000001CUL /**< Mode MMUL for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_MULO 0x0000001DUL /**< Mode MULO for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_LMULO 0x0000001FUL /**< Mode LMULO for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_SHL 0x00000020UL /**< Mode SHL for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_SHLC 0x00000021UL /**< Mode SHLC for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_SHLB 0x00000022UL /**< Mode SHLB for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_SHL1 0x00000023UL /**< Mode SHL1 for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_SHR 0x00000024UL /**< Mode SHR for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_SHRC 0x00000025UL /**< Mode SHRC for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_SHRB 0x00000026UL /**< Mode SHRB for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_SHR1 0x00000027UL /**< Mode SHR1 for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_ADDO 0x00000028UL /**< Mode ADDO for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_ADDIC 0x00000029UL /**< Mode ADDIC for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_LADDO 0x0000002AUL /**< Mode LADDO for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_LADDIC 0x0000002BUL /**< Mode LADDIC for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_CLR 0x00000030UL /**< Mode CLR for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_XOR 0x00000031UL /**< Mode XOR for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_INV 0x00000032UL /**< Mode INV for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_CSET 0x00000034UL /**< Mode CSET for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_CCLR 0x00000035UL /**< Mode CCLR for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_BBSWAP128 0x00000036UL /**< Mode BBSWAP128 for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_INC 0x00000038UL /**< Mode INC for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_DEC 0x00000039UL /**< Mode DEC for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_LINC 0x0000003AUL /**< Mode LINC for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_LDEC 0x0000003BUL /**< Mode LDEC for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_SHRA 0x0000003EUL /**< Mode SHRA for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_DATA0TODATA0 0x00000040UL /**< Mode DATA0TODATA0 for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_DATA0TODATA0XOR 0x00000041UL /**< Mode DATA0TODATA0XOR for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_DATA0TODATA0XORLEN 0x00000042UL /**< Mode DATA0TODATA0XORLEN for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_DATA0TODATA1 0x00000044UL /**< Mode DATA0TODATA1 for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_DATA0TODATA2 0x00000045UL /**< Mode DATA0TODATA2 for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_DATA0TODATA3 0x00000046UL /**< Mode DATA0TODATA3 for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_DATA1TODATA0 0x00000048UL /**< Mode DATA1TODATA0 for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_DATA1TODATA0XOR 0x00000049UL /**< Mode DATA1TODATA0XOR for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_DATA1TODATA0XORLEN 0x0000004AUL /**< Mode DATA1TODATA0XORLEN for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_DATA1TODATA2 0x0000004DUL /**< Mode DATA1TODATA2 for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_DATA1TODATA3 0x0000004EUL /**< Mode DATA1TODATA3 for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_DATA2TODATA0 0x00000050UL /**< Mode DATA2TODATA0 for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_DATA2TODATA0XOR 0x00000051UL /**< Mode DATA2TODATA0XOR for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_DATA2TODATA0XORLEN 0x00000052UL /**< Mode DATA2TODATA0XORLEN for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_DATA2TODATA1 0x00000054UL /**< Mode DATA2TODATA1 for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_DATA2TODATA3 0x00000056UL /**< Mode DATA2TODATA3 for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_DATA3TODATA0 0x00000058UL /**< Mode DATA3TODATA0 for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_DATA3TODATA0XOR 0x00000059UL /**< Mode DATA3TODATA0XOR for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_DATA3TODATA0XORLEN 0x0000005AUL /**< Mode DATA3TODATA0XORLEN for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_DATA3TODATA1 0x0000005CUL /**< Mode DATA3TODATA1 for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_DATA3TODATA2 0x0000005DUL /**< Mode DATA3TODATA2 for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_DATATODMA0 0x00000063UL /**< Mode DATATODMA0 for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_DATA0TOBUF 0x00000064UL /**< Mode DATA0TOBUF for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_DATA0TOBUFXOR 0x00000065UL /**< Mode DATA0TOBUFXOR for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_DATATODMA1 0x0000006BUL /**< Mode DATATODMA1 for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_DATA1TOBUF 0x0000006CUL /**< Mode DATA1TOBUF for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_DATA1TOBUFXOR 0x0000006DUL /**< Mode DATA1TOBUFXOR for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_DMA0TODATA 0x00000070UL /**< Mode DMA0TODATA for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_DMA0TODATAXOR 0x00000071UL /**< Mode DMA0TODATAXOR for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_DMA1TODATA 0x00000072UL /**< Mode DMA1TODATA for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_BUFTODATA0 0x00000078UL /**< Mode BUFTODATA0 for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_BUFTODATA0XOR 0x00000079UL /**< Mode BUFTODATA0XOR for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_BUFTODATA1 0x0000007AUL /**< Mode BUFTODATA1 for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_DDATA0TODDATA1 0x00000081UL /**< Mode DDATA0TODDATA1 for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_DDATA0TODDATA2 0x00000082UL /**< Mode DDATA0TODDATA2 for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_DDATA0TODDATA3 0x00000083UL /**< Mode DDATA0TODDATA3 for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_DDATA0TODDATA4 0x00000084UL /**< Mode DDATA0TODDATA4 for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_DDATA0LTODATA0 0x00000085UL /**< Mode DDATA0LTODATA0 for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_DDATA0HTODATA1 0x00000086UL /**< Mode DDATA0HTODATA1 for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_DDATA0LTODATA2 0x00000087UL /**< Mode DDATA0LTODATA2 for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_DDATA1TODDATA0 0x00000088UL /**< Mode DDATA1TODDATA0 for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_DDATA1TODDATA2 0x0000008AUL /**< Mode DDATA1TODDATA2 for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_DDATA1TODDATA3 0x0000008BUL /**< Mode DDATA1TODDATA3 for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_DDATA1TODDATA4 0x0000008CUL /**< Mode DDATA1TODDATA4 for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_DDATA1LTODATA0 0x0000008DUL /**< Mode DDATA1LTODATA0 for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_DDATA1HTODATA1 0x0000008EUL /**< Mode DDATA1HTODATA1 for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_DDATA1LTODATA2 0x0000008FUL /**< Mode DDATA1LTODATA2 for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_DDATA2TODDATA0 0x00000090UL /**< Mode DDATA2TODDATA0 for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_DDATA2TODDATA1 0x00000091UL /**< Mode DDATA2TODDATA1 for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_DDATA2TODDATA3 0x00000093UL /**< Mode DDATA2TODDATA3 for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_DDATA2TODDATA4 0x00000094UL /**< Mode DDATA2TODDATA4 for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_DDATA2LTODATA2 0x00000097UL /**< Mode DDATA2LTODATA2 for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_DDATA3TODDATA0 0x00000098UL /**< Mode DDATA3TODDATA0 for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_DDATA3TODDATA1 0x00000099UL /**< Mode DDATA3TODDATA1 for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_DDATA3TODDATA2 0x0000009AUL /**< Mode DDATA3TODDATA2 for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_DDATA3TODDATA4 0x0000009CUL /**< Mode DDATA3TODDATA4 for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_DDATA3LTODATA0 0x0000009DUL /**< Mode DDATA3LTODATA0 for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_DDATA3HTODATA1 0x0000009EUL /**< Mode DDATA3HTODATA1 for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_DDATA4TODDATA0 0x000000A0UL /**< Mode DDATA4TODDATA0 for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_DDATA4TODDATA1 0x000000A1UL /**< Mode DDATA4TODDATA1 for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_DDATA4TODDATA2 0x000000A2UL /**< Mode DDATA4TODDATA2 for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_DDATA4TODDATA3 0x000000A3UL /**< Mode DDATA4TODDATA3 for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_DDATA4LTODATA0 0x000000A5UL /**< Mode DDATA4LTODATA0 for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_DDATA4HTODATA1 0x000000A6UL /**< Mode DDATA4HTODATA1 for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_DDATA4LTODATA2 0x000000A7UL /**< Mode DDATA4LTODATA2 for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_DATA0TODDATA0 0x000000A8UL /**< Mode DATA0TODDATA0 for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_DATA0TODDATA1 0x000000A9UL /**< Mode DATA0TODDATA1 for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_DATA1TODDATA0 0x000000B0UL /**< Mode DATA1TODDATA0 for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_DATA1TODDATA1 0x000000B1UL /**< Mode DATA1TODDATA1 for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_DATA2TODDATA0 0x000000B8UL /**< Mode DATA2TODDATA0 for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_DATA2TODDATA1 0x000000B9UL /**< Mode DATA2TODDATA1 for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_DATA2TODDATA2 0x000000BAUL /**< Mode DATA2TODDATA2 for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_SELDDATA0DDATA0 0x000000C0UL /**< Mode SELDDATA0DDATA0 for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_SELDDATA1DDATA0 0x000000C1UL /**< Mode SELDDATA1DDATA0 for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_SELDDATA2DDATA0 0x000000C2UL /**< Mode SELDDATA2DDATA0 for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_SELDDATA3DDATA0 0x000000C3UL /**< Mode SELDDATA3DDATA0 for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_SELDDATA4DDATA0 0x000000C4UL /**< Mode SELDDATA4DDATA0 for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_SELDATA0DDATA0 0x000000C5UL /**< Mode SELDATA0DDATA0 for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_SELDATA1DDATA0 0x000000C6UL /**< Mode SELDATA1DDATA0 for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_SELDATA2DDATA0 0x000000C7UL /**< Mode SELDATA2DDATA0 for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_SELDDATA0DDATA1 0x000000C8UL /**< Mode SELDDATA0DDATA1 for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_SELDDATA1DDATA1 0x000000C9UL /**< Mode SELDDATA1DDATA1 for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_SELDDATA2DDATA1 0x000000CAUL /**< Mode SELDDATA2DDATA1 for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_SELDDATA3DDATA1 0x000000CBUL /**< Mode SELDDATA3DDATA1 for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_SELDDATA4DDATA1 0x000000CCUL /**< Mode SELDDATA4DDATA1 for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_SELDATA0DDATA1 0x000000CDUL /**< Mode SELDATA0DDATA1 for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_SELDATA1DDATA1 0x000000CEUL /**< Mode SELDATA1DDATA1 for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_SELDATA2DDATA1 0x000000CFUL /**< Mode SELDATA2DDATA1 for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_SELDDATA0DDATA2 0x000000D0UL /**< Mode SELDDATA0DDATA2 for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_SELDDATA1DDATA2 0x000000D1UL /**< Mode SELDDATA1DDATA2 for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_SELDDATA2DDATA2 0x000000D2UL /**< Mode SELDDATA2DDATA2 for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_SELDDATA3DDATA2 0x000000D3UL /**< Mode SELDDATA3DDATA2 for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_SELDDATA4DDATA2 0x000000D4UL /**< Mode SELDDATA4DDATA2 for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_SELDATA0DDATA2 0x000000D5UL /**< Mode SELDATA0DDATA2 for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_SELDATA1DDATA2 0x000000D6UL /**< Mode SELDATA1DDATA2 for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_SELDATA2DDATA2 0x000000D7UL /**< Mode SELDATA2DDATA2 for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_SELDDATA0DDATA3 0x000000D8UL /**< Mode SELDDATA0DDATA3 for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_SELDDATA1DDATA3 0x000000D9UL /**< Mode SELDDATA1DDATA3 for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_SELDDATA2DDATA3 0x000000DAUL /**< Mode SELDDATA2DDATA3 for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_SELDDATA3DDATA3 0x000000DBUL /**< Mode SELDDATA3DDATA3 for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_SELDDATA4DDATA3 0x000000DCUL /**< Mode SELDDATA4DDATA3 for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_SELDATA0DDATA3 0x000000DDUL /**< Mode SELDATA0DDATA3 for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_SELDATA1DDATA3 0x000000DEUL /**< Mode SELDATA1DDATA3 for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_SELDATA2DDATA3 0x000000DFUL /**< Mode SELDATA2DDATA3 for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_SELDDATA0DDATA4 0x000000E0UL /**< Mode SELDDATA0DDATA4 for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_SELDDATA1DDATA4 0x000000E1UL /**< Mode SELDDATA1DDATA4 for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_SELDDATA2DDATA4 0x000000E2UL /**< Mode SELDDATA2DDATA4 for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_SELDDATA3DDATA4 0x000000E3UL /**< Mode SELDDATA3DDATA4 for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_SELDDATA4DDATA4 0x000000E4UL /**< Mode SELDDATA4DDATA4 for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_SELDATA0DDATA4 0x000000E5UL /**< Mode SELDATA0DDATA4 for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_SELDATA1DDATA4 0x000000E6UL /**< Mode SELDATA1DDATA4 for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_SELDATA2DDATA4 0x000000E7UL /**< Mode SELDATA2DDATA4 for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_SELDDATA0DATA0 0x000000E8UL /**< Mode SELDDATA0DATA0 for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_SELDDATA1DATA0 0x000000E9UL /**< Mode SELDDATA1DATA0 for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_SELDDATA2DATA0 0x000000EAUL /**< Mode SELDDATA2DATA0 for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_SELDDATA3DATA0 0x000000EBUL /**< Mode SELDDATA3DATA0 for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_SELDDATA4DATA0 0x000000ECUL /**< Mode SELDDATA4DATA0 for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_SELDATA0DATA0 0x000000EDUL /**< Mode SELDATA0DATA0 for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_SELDATA1DATA0 0x000000EEUL /**< Mode SELDATA1DATA0 for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_SELDATA2DATA0 0x000000EFUL /**< Mode SELDATA2DATA0 for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_SELDDATA0DATA1 0x000000F0UL /**< Mode SELDDATA0DATA1 for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_SELDDATA1DATA1 0x000000F1UL /**< Mode SELDDATA1DATA1 for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_SELDDATA2DATA1 0x000000F2UL /**< Mode SELDDATA2DATA1 for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_SELDDATA3DATA1 0x000000F3UL /**< Mode SELDDATA3DATA1 for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_SELDDATA4DATA1 0x000000F4UL /**< Mode SELDDATA4DATA1 for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_SELDATA0DATA1 0x000000F5UL /**< Mode SELDATA0DATA1 for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_SELDATA1DATA1 0x000000F6UL /**< Mode SELDATA1DATA1 for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_SELDATA2DATA1 0x000000F7UL /**< Mode SELDATA2DATA1 for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_EXECIFA 0x000000F8UL /**< Mode EXECIFA for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_EXECIFB 0x000000F9UL /**< Mode EXECIFB for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_EXECIFNLAST 0x000000FAUL /**< Mode EXECIFNLAST for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_EXECIFLAST 0x000000FBUL /**< Mode EXECIFLAST for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_EXECIFCARRY 0x000000FCUL /**< Mode EXECIFCARRY for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_EXECIFNCARRY 0x000000FDUL /**< Mode EXECIFNCARRY for CRYPTO_CMD */ #define _CRYPTO_CMD_INSTR_EXECALWAYS 0x000000FEUL /**< Mode EXECALWAYS for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_DEFAULT (_CRYPTO_CMD_INSTR_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_END (_CRYPTO_CMD_INSTR_END << 0) /**< Shifted mode END for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_EXEC (_CRYPTO_CMD_INSTR_EXEC << 0) /**< Shifted mode EXEC for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_DATA1INC (_CRYPTO_CMD_INSTR_DATA1INC << 0) /**< Shifted mode DATA1INC for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_DATA1INCCLR (_CRYPTO_CMD_INSTR_DATA1INCCLR << 0) /**< Shifted mode DATA1INCCLR for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_AESENC (_CRYPTO_CMD_INSTR_AESENC << 0) /**< Shifted mode AESENC for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_AESDEC (_CRYPTO_CMD_INSTR_AESDEC << 0) /**< Shifted mode AESDEC for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_SHA (_CRYPTO_CMD_INSTR_SHA << 0) /**< Shifted mode SHA for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_ADD (_CRYPTO_CMD_INSTR_ADD << 0) /**< Shifted mode ADD for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_ADDC (_CRYPTO_CMD_INSTR_ADDC << 0) /**< Shifted mode ADDC for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_LADD (_CRYPTO_CMD_INSTR_LADD << 0) /**< Shifted mode LADD for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_LADDC (_CRYPTO_CMD_INSTR_LADDC << 0) /**< Shifted mode LADDC for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_MADD (_CRYPTO_CMD_INSTR_MADD << 0) /**< Shifted mode MADD for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_MADD32 (_CRYPTO_CMD_INSTR_MADD32 << 0) /**< Shifted mode MADD32 for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_SUB (_CRYPTO_CMD_INSTR_SUB << 0) /**< Shifted mode SUB for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_SUBC (_CRYPTO_CMD_INSTR_SUBC << 0) /**< Shifted mode SUBC for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_LSUB (_CRYPTO_CMD_INSTR_LSUB << 0) /**< Shifted mode LSUB for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_LSUBC (_CRYPTO_CMD_INSTR_LSUBC << 0) /**< Shifted mode LSUBC for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_MSUB (_CRYPTO_CMD_INSTR_MSUB << 0) /**< Shifted mode MSUB for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_MUL (_CRYPTO_CMD_INSTR_MUL << 0) /**< Shifted mode MUL for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_MULC (_CRYPTO_CMD_INSTR_MULC << 0) /**< Shifted mode MULC for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_LMUL (_CRYPTO_CMD_INSTR_LMUL << 0) /**< Shifted mode LMUL for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_MMUL (_CRYPTO_CMD_INSTR_MMUL << 0) /**< Shifted mode MMUL for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_MULO (_CRYPTO_CMD_INSTR_MULO << 0) /**< Shifted mode MULO for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_LMULO (_CRYPTO_CMD_INSTR_LMULO << 0) /**< Shifted mode LMULO for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_SHL (_CRYPTO_CMD_INSTR_SHL << 0) /**< Shifted mode SHL for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_SHLC (_CRYPTO_CMD_INSTR_SHLC << 0) /**< Shifted mode SHLC for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_SHLB (_CRYPTO_CMD_INSTR_SHLB << 0) /**< Shifted mode SHLB for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_SHL1 (_CRYPTO_CMD_INSTR_SHL1 << 0) /**< Shifted mode SHL1 for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_SHR (_CRYPTO_CMD_INSTR_SHR << 0) /**< Shifted mode SHR for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_SHRC (_CRYPTO_CMD_INSTR_SHRC << 0) /**< Shifted mode SHRC for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_SHRB (_CRYPTO_CMD_INSTR_SHRB << 0) /**< Shifted mode SHRB for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_SHR1 (_CRYPTO_CMD_INSTR_SHR1 << 0) /**< Shifted mode SHR1 for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_ADDO (_CRYPTO_CMD_INSTR_ADDO << 0) /**< Shifted mode ADDO for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_ADDIC (_CRYPTO_CMD_INSTR_ADDIC << 0) /**< Shifted mode ADDIC for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_LADDO (_CRYPTO_CMD_INSTR_LADDO << 0) /**< Shifted mode LADDO for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_LADDIC (_CRYPTO_CMD_INSTR_LADDIC << 0) /**< Shifted mode LADDIC for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_CLR (_CRYPTO_CMD_INSTR_CLR << 0) /**< Shifted mode CLR for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_XOR (_CRYPTO_CMD_INSTR_XOR << 0) /**< Shifted mode XOR for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_INV (_CRYPTO_CMD_INSTR_INV << 0) /**< Shifted mode INV for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_CSET (_CRYPTO_CMD_INSTR_CSET << 0) /**< Shifted mode CSET for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_CCLR (_CRYPTO_CMD_INSTR_CCLR << 0) /**< Shifted mode CCLR for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_BBSWAP128 (_CRYPTO_CMD_INSTR_BBSWAP128 << 0) /**< Shifted mode BBSWAP128 for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_INC (_CRYPTO_CMD_INSTR_INC << 0) /**< Shifted mode INC for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_DEC (_CRYPTO_CMD_INSTR_DEC << 0) /**< Shifted mode DEC for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_LINC (_CRYPTO_CMD_INSTR_LINC << 0) /**< Shifted mode LINC for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_LDEC (_CRYPTO_CMD_INSTR_LDEC << 0) /**< Shifted mode LDEC for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_SHRA (_CRYPTO_CMD_INSTR_SHRA << 0) /**< Shifted mode SHRA for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_DATA0TODATA0 (_CRYPTO_CMD_INSTR_DATA0TODATA0 << 0) /**< Shifted mode DATA0TODATA0 for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_DATA0TODATA0XOR (_CRYPTO_CMD_INSTR_DATA0TODATA0XOR << 0) /**< Shifted mode DATA0TODATA0XOR for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_DATA0TODATA0XORLEN (_CRYPTO_CMD_INSTR_DATA0TODATA0XORLEN << 0) /**< Shifted mode DATA0TODATA0XORLEN for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_DATA0TODATA1 (_CRYPTO_CMD_INSTR_DATA0TODATA1 << 0) /**< Shifted mode DATA0TODATA1 for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_DATA0TODATA2 (_CRYPTO_CMD_INSTR_DATA0TODATA2 << 0) /**< Shifted mode DATA0TODATA2 for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_DATA0TODATA3 (_CRYPTO_CMD_INSTR_DATA0TODATA3 << 0) /**< Shifted mode DATA0TODATA3 for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_DATA1TODATA0 (_CRYPTO_CMD_INSTR_DATA1TODATA0 << 0) /**< Shifted mode DATA1TODATA0 for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_DATA1TODATA0XOR (_CRYPTO_CMD_INSTR_DATA1TODATA0XOR << 0) /**< Shifted mode DATA1TODATA0XOR for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_DATA1TODATA0XORLEN (_CRYPTO_CMD_INSTR_DATA1TODATA0XORLEN << 0) /**< Shifted mode DATA1TODATA0XORLEN for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_DATA1TODATA2 (_CRYPTO_CMD_INSTR_DATA1TODATA2 << 0) /**< Shifted mode DATA1TODATA2 for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_DATA1TODATA3 (_CRYPTO_CMD_INSTR_DATA1TODATA3 << 0) /**< Shifted mode DATA1TODATA3 for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_DATA2TODATA0 (_CRYPTO_CMD_INSTR_DATA2TODATA0 << 0) /**< Shifted mode DATA2TODATA0 for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_DATA2TODATA0XOR (_CRYPTO_CMD_INSTR_DATA2TODATA0XOR << 0) /**< Shifted mode DATA2TODATA0XOR for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_DATA2TODATA0XORLEN (_CRYPTO_CMD_INSTR_DATA2TODATA0XORLEN << 0) /**< Shifted mode DATA2TODATA0XORLEN for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_DATA2TODATA1 (_CRYPTO_CMD_INSTR_DATA2TODATA1 << 0) /**< Shifted mode DATA2TODATA1 for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_DATA2TODATA3 (_CRYPTO_CMD_INSTR_DATA2TODATA3 << 0) /**< Shifted mode DATA2TODATA3 for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_DATA3TODATA0 (_CRYPTO_CMD_INSTR_DATA3TODATA0 << 0) /**< Shifted mode DATA3TODATA0 for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_DATA3TODATA0XOR (_CRYPTO_CMD_INSTR_DATA3TODATA0XOR << 0) /**< Shifted mode DATA3TODATA0XOR for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_DATA3TODATA0XORLEN (_CRYPTO_CMD_INSTR_DATA3TODATA0XORLEN << 0) /**< Shifted mode DATA3TODATA0XORLEN for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_DATA3TODATA1 (_CRYPTO_CMD_INSTR_DATA3TODATA1 << 0) /**< Shifted mode DATA3TODATA1 for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_DATA3TODATA2 (_CRYPTO_CMD_INSTR_DATA3TODATA2 << 0) /**< Shifted mode DATA3TODATA2 for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_DATATODMA0 (_CRYPTO_CMD_INSTR_DATATODMA0 << 0) /**< Shifted mode DATATODMA0 for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_DATA0TOBUF (_CRYPTO_CMD_INSTR_DATA0TOBUF << 0) /**< Shifted mode DATA0TOBUF for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_DATA0TOBUFXOR (_CRYPTO_CMD_INSTR_DATA0TOBUFXOR << 0) /**< Shifted mode DATA0TOBUFXOR for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_DATATODMA1 (_CRYPTO_CMD_INSTR_DATATODMA1 << 0) /**< Shifted mode DATATODMA1 for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_DATA1TOBUF (_CRYPTO_CMD_INSTR_DATA1TOBUF << 0) /**< Shifted mode DATA1TOBUF for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_DATA1TOBUFXOR (_CRYPTO_CMD_INSTR_DATA1TOBUFXOR << 0) /**< Shifted mode DATA1TOBUFXOR for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_DMA0TODATA (_CRYPTO_CMD_INSTR_DMA0TODATA << 0) /**< Shifted mode DMA0TODATA for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_DMA0TODATAXOR (_CRYPTO_CMD_INSTR_DMA0TODATAXOR << 0) /**< Shifted mode DMA0TODATAXOR for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_DMA1TODATA (_CRYPTO_CMD_INSTR_DMA1TODATA << 0) /**< Shifted mode DMA1TODATA for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_BUFTODATA0 (_CRYPTO_CMD_INSTR_BUFTODATA0 << 0) /**< Shifted mode BUFTODATA0 for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_BUFTODATA0XOR (_CRYPTO_CMD_INSTR_BUFTODATA0XOR << 0) /**< Shifted mode BUFTODATA0XOR for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_BUFTODATA1 (_CRYPTO_CMD_INSTR_BUFTODATA1 << 0) /**< Shifted mode BUFTODATA1 for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_DDATA0TODDATA1 (_CRYPTO_CMD_INSTR_DDATA0TODDATA1 << 0) /**< Shifted mode DDATA0TODDATA1 for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_DDATA0TODDATA2 (_CRYPTO_CMD_INSTR_DDATA0TODDATA2 << 0) /**< Shifted mode DDATA0TODDATA2 for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_DDATA0TODDATA3 (_CRYPTO_CMD_INSTR_DDATA0TODDATA3 << 0) /**< Shifted mode DDATA0TODDATA3 for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_DDATA0TODDATA4 (_CRYPTO_CMD_INSTR_DDATA0TODDATA4 << 0) /**< Shifted mode DDATA0TODDATA4 for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_DDATA0LTODATA0 (_CRYPTO_CMD_INSTR_DDATA0LTODATA0 << 0) /**< Shifted mode DDATA0LTODATA0 for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_DDATA0HTODATA1 (_CRYPTO_CMD_INSTR_DDATA0HTODATA1 << 0) /**< Shifted mode DDATA0HTODATA1 for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_DDATA0LTODATA2 (_CRYPTO_CMD_INSTR_DDATA0LTODATA2 << 0) /**< Shifted mode DDATA0LTODATA2 for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_DDATA1TODDATA0 (_CRYPTO_CMD_INSTR_DDATA1TODDATA0 << 0) /**< Shifted mode DDATA1TODDATA0 for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_DDATA1TODDATA2 (_CRYPTO_CMD_INSTR_DDATA1TODDATA2 << 0) /**< Shifted mode DDATA1TODDATA2 for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_DDATA1TODDATA3 (_CRYPTO_CMD_INSTR_DDATA1TODDATA3 << 0) /**< Shifted mode DDATA1TODDATA3 for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_DDATA1TODDATA4 (_CRYPTO_CMD_INSTR_DDATA1TODDATA4 << 0) /**< Shifted mode DDATA1TODDATA4 for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_DDATA1LTODATA0 (_CRYPTO_CMD_INSTR_DDATA1LTODATA0 << 0) /**< Shifted mode DDATA1LTODATA0 for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_DDATA1HTODATA1 (_CRYPTO_CMD_INSTR_DDATA1HTODATA1 << 0) /**< Shifted mode DDATA1HTODATA1 for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_DDATA1LTODATA2 (_CRYPTO_CMD_INSTR_DDATA1LTODATA2 << 0) /**< Shifted mode DDATA1LTODATA2 for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_DDATA2TODDATA0 (_CRYPTO_CMD_INSTR_DDATA2TODDATA0 << 0) /**< Shifted mode DDATA2TODDATA0 for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_DDATA2TODDATA1 (_CRYPTO_CMD_INSTR_DDATA2TODDATA1 << 0) /**< Shifted mode DDATA2TODDATA1 for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_DDATA2TODDATA3 (_CRYPTO_CMD_INSTR_DDATA2TODDATA3 << 0) /**< Shifted mode DDATA2TODDATA3 for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_DDATA2TODDATA4 (_CRYPTO_CMD_INSTR_DDATA2TODDATA4 << 0) /**< Shifted mode DDATA2TODDATA4 for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_DDATA2LTODATA2 (_CRYPTO_CMD_INSTR_DDATA2LTODATA2 << 0) /**< Shifted mode DDATA2LTODATA2 for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_DDATA3TODDATA0 (_CRYPTO_CMD_INSTR_DDATA3TODDATA0 << 0) /**< Shifted mode DDATA3TODDATA0 for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_DDATA3TODDATA1 (_CRYPTO_CMD_INSTR_DDATA3TODDATA1 << 0) /**< Shifted mode DDATA3TODDATA1 for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_DDATA3TODDATA2 (_CRYPTO_CMD_INSTR_DDATA3TODDATA2 << 0) /**< Shifted mode DDATA3TODDATA2 for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_DDATA3TODDATA4 (_CRYPTO_CMD_INSTR_DDATA3TODDATA4 << 0) /**< Shifted mode DDATA3TODDATA4 for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_DDATA3LTODATA0 (_CRYPTO_CMD_INSTR_DDATA3LTODATA0 << 0) /**< Shifted mode DDATA3LTODATA0 for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_DDATA3HTODATA1 (_CRYPTO_CMD_INSTR_DDATA3HTODATA1 << 0) /**< Shifted mode DDATA3HTODATA1 for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_DDATA4TODDATA0 (_CRYPTO_CMD_INSTR_DDATA4TODDATA0 << 0) /**< Shifted mode DDATA4TODDATA0 for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_DDATA4TODDATA1 (_CRYPTO_CMD_INSTR_DDATA4TODDATA1 << 0) /**< Shifted mode DDATA4TODDATA1 for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_DDATA4TODDATA2 (_CRYPTO_CMD_INSTR_DDATA4TODDATA2 << 0) /**< Shifted mode DDATA4TODDATA2 for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_DDATA4TODDATA3 (_CRYPTO_CMD_INSTR_DDATA4TODDATA3 << 0) /**< Shifted mode DDATA4TODDATA3 for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_DDATA4LTODATA0 (_CRYPTO_CMD_INSTR_DDATA4LTODATA0 << 0) /**< Shifted mode DDATA4LTODATA0 for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_DDATA4HTODATA1 (_CRYPTO_CMD_INSTR_DDATA4HTODATA1 << 0) /**< Shifted mode DDATA4HTODATA1 for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_DDATA4LTODATA2 (_CRYPTO_CMD_INSTR_DDATA4LTODATA2 << 0) /**< Shifted mode DDATA4LTODATA2 for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_DATA0TODDATA0 (_CRYPTO_CMD_INSTR_DATA0TODDATA0 << 0) /**< Shifted mode DATA0TODDATA0 for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_DATA0TODDATA1 (_CRYPTO_CMD_INSTR_DATA0TODDATA1 << 0) /**< Shifted mode DATA0TODDATA1 for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_DATA1TODDATA0 (_CRYPTO_CMD_INSTR_DATA1TODDATA0 << 0) /**< Shifted mode DATA1TODDATA0 for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_DATA1TODDATA1 (_CRYPTO_CMD_INSTR_DATA1TODDATA1 << 0) /**< Shifted mode DATA1TODDATA1 for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_DATA2TODDATA0 (_CRYPTO_CMD_INSTR_DATA2TODDATA0 << 0) /**< Shifted mode DATA2TODDATA0 for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_DATA2TODDATA1 (_CRYPTO_CMD_INSTR_DATA2TODDATA1 << 0) /**< Shifted mode DATA2TODDATA1 for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_DATA2TODDATA2 (_CRYPTO_CMD_INSTR_DATA2TODDATA2 << 0) /**< Shifted mode DATA2TODDATA2 for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_SELDDATA0DDATA0 (_CRYPTO_CMD_INSTR_SELDDATA0DDATA0 << 0) /**< Shifted mode SELDDATA0DDATA0 for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_SELDDATA1DDATA0 (_CRYPTO_CMD_INSTR_SELDDATA1DDATA0 << 0) /**< Shifted mode SELDDATA1DDATA0 for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_SELDDATA2DDATA0 (_CRYPTO_CMD_INSTR_SELDDATA2DDATA0 << 0) /**< Shifted mode SELDDATA2DDATA0 for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_SELDDATA3DDATA0 (_CRYPTO_CMD_INSTR_SELDDATA3DDATA0 << 0) /**< Shifted mode SELDDATA3DDATA0 for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_SELDDATA4DDATA0 (_CRYPTO_CMD_INSTR_SELDDATA4DDATA0 << 0) /**< Shifted mode SELDDATA4DDATA0 for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_SELDATA0DDATA0 (_CRYPTO_CMD_INSTR_SELDATA0DDATA0 << 0) /**< Shifted mode SELDATA0DDATA0 for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_SELDATA1DDATA0 (_CRYPTO_CMD_INSTR_SELDATA1DDATA0 << 0) /**< Shifted mode SELDATA1DDATA0 for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_SELDATA2DDATA0 (_CRYPTO_CMD_INSTR_SELDATA2DDATA0 << 0) /**< Shifted mode SELDATA2DDATA0 for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_SELDDATA0DDATA1 (_CRYPTO_CMD_INSTR_SELDDATA0DDATA1 << 0) /**< Shifted mode SELDDATA0DDATA1 for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_SELDDATA1DDATA1 (_CRYPTO_CMD_INSTR_SELDDATA1DDATA1 << 0) /**< Shifted mode SELDDATA1DDATA1 for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_SELDDATA2DDATA1 (_CRYPTO_CMD_INSTR_SELDDATA2DDATA1 << 0) /**< Shifted mode SELDDATA2DDATA1 for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_SELDDATA3DDATA1 (_CRYPTO_CMD_INSTR_SELDDATA3DDATA1 << 0) /**< Shifted mode SELDDATA3DDATA1 for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_SELDDATA4DDATA1 (_CRYPTO_CMD_INSTR_SELDDATA4DDATA1 << 0) /**< Shifted mode SELDDATA4DDATA1 for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_SELDATA0DDATA1 (_CRYPTO_CMD_INSTR_SELDATA0DDATA1 << 0) /**< Shifted mode SELDATA0DDATA1 for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_SELDATA1DDATA1 (_CRYPTO_CMD_INSTR_SELDATA1DDATA1 << 0) /**< Shifted mode SELDATA1DDATA1 for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_SELDATA2DDATA1 (_CRYPTO_CMD_INSTR_SELDATA2DDATA1 << 0) /**< Shifted mode SELDATA2DDATA1 for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_SELDDATA0DDATA2 (_CRYPTO_CMD_INSTR_SELDDATA0DDATA2 << 0) /**< Shifted mode SELDDATA0DDATA2 for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_SELDDATA1DDATA2 (_CRYPTO_CMD_INSTR_SELDDATA1DDATA2 << 0) /**< Shifted mode SELDDATA1DDATA2 for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_SELDDATA2DDATA2 (_CRYPTO_CMD_INSTR_SELDDATA2DDATA2 << 0) /**< Shifted mode SELDDATA2DDATA2 for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_SELDDATA3DDATA2 (_CRYPTO_CMD_INSTR_SELDDATA3DDATA2 << 0) /**< Shifted mode SELDDATA3DDATA2 for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_SELDDATA4DDATA2 (_CRYPTO_CMD_INSTR_SELDDATA4DDATA2 << 0) /**< Shifted mode SELDDATA4DDATA2 for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_SELDATA0DDATA2 (_CRYPTO_CMD_INSTR_SELDATA0DDATA2 << 0) /**< Shifted mode SELDATA0DDATA2 for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_SELDATA1DDATA2 (_CRYPTO_CMD_INSTR_SELDATA1DDATA2 << 0) /**< Shifted mode SELDATA1DDATA2 for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_SELDATA2DDATA2 (_CRYPTO_CMD_INSTR_SELDATA2DDATA2 << 0) /**< Shifted mode SELDATA2DDATA2 for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_SELDDATA0DDATA3 (_CRYPTO_CMD_INSTR_SELDDATA0DDATA3 << 0) /**< Shifted mode SELDDATA0DDATA3 for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_SELDDATA1DDATA3 (_CRYPTO_CMD_INSTR_SELDDATA1DDATA3 << 0) /**< Shifted mode SELDDATA1DDATA3 for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_SELDDATA2DDATA3 (_CRYPTO_CMD_INSTR_SELDDATA2DDATA3 << 0) /**< Shifted mode SELDDATA2DDATA3 for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_SELDDATA3DDATA3 (_CRYPTO_CMD_INSTR_SELDDATA3DDATA3 << 0) /**< Shifted mode SELDDATA3DDATA3 for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_SELDDATA4DDATA3 (_CRYPTO_CMD_INSTR_SELDDATA4DDATA3 << 0) /**< Shifted mode SELDDATA4DDATA3 for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_SELDATA0DDATA3 (_CRYPTO_CMD_INSTR_SELDATA0DDATA3 << 0) /**< Shifted mode SELDATA0DDATA3 for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_SELDATA1DDATA3 (_CRYPTO_CMD_INSTR_SELDATA1DDATA3 << 0) /**< Shifted mode SELDATA1DDATA3 for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_SELDATA2DDATA3 (_CRYPTO_CMD_INSTR_SELDATA2DDATA3 << 0) /**< Shifted mode SELDATA2DDATA3 for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_SELDDATA0DDATA4 (_CRYPTO_CMD_INSTR_SELDDATA0DDATA4 << 0) /**< Shifted mode SELDDATA0DDATA4 for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_SELDDATA1DDATA4 (_CRYPTO_CMD_INSTR_SELDDATA1DDATA4 << 0) /**< Shifted mode SELDDATA1DDATA4 for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_SELDDATA2DDATA4 (_CRYPTO_CMD_INSTR_SELDDATA2DDATA4 << 0) /**< Shifted mode SELDDATA2DDATA4 for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_SELDDATA3DDATA4 (_CRYPTO_CMD_INSTR_SELDDATA3DDATA4 << 0) /**< Shifted mode SELDDATA3DDATA4 for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_SELDDATA4DDATA4 (_CRYPTO_CMD_INSTR_SELDDATA4DDATA4 << 0) /**< Shifted mode SELDDATA4DDATA4 for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_SELDATA0DDATA4 (_CRYPTO_CMD_INSTR_SELDATA0DDATA4 << 0) /**< Shifted mode SELDATA0DDATA4 for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_SELDATA1DDATA4 (_CRYPTO_CMD_INSTR_SELDATA1DDATA4 << 0) /**< Shifted mode SELDATA1DDATA4 for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_SELDATA2DDATA4 (_CRYPTO_CMD_INSTR_SELDATA2DDATA4 << 0) /**< Shifted mode SELDATA2DDATA4 for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_SELDDATA0DATA0 (_CRYPTO_CMD_INSTR_SELDDATA0DATA0 << 0) /**< Shifted mode SELDDATA0DATA0 for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_SELDDATA1DATA0 (_CRYPTO_CMD_INSTR_SELDDATA1DATA0 << 0) /**< Shifted mode SELDDATA1DATA0 for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_SELDDATA2DATA0 (_CRYPTO_CMD_INSTR_SELDDATA2DATA0 << 0) /**< Shifted mode SELDDATA2DATA0 for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_SELDDATA3DATA0 (_CRYPTO_CMD_INSTR_SELDDATA3DATA0 << 0) /**< Shifted mode SELDDATA3DATA0 for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_SELDDATA4DATA0 (_CRYPTO_CMD_INSTR_SELDDATA4DATA0 << 0) /**< Shifted mode SELDDATA4DATA0 for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_SELDATA0DATA0 (_CRYPTO_CMD_INSTR_SELDATA0DATA0 << 0) /**< Shifted mode SELDATA0DATA0 for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_SELDATA1DATA0 (_CRYPTO_CMD_INSTR_SELDATA1DATA0 << 0) /**< Shifted mode SELDATA1DATA0 for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_SELDATA2DATA0 (_CRYPTO_CMD_INSTR_SELDATA2DATA0 << 0) /**< Shifted mode SELDATA2DATA0 for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_SELDDATA0DATA1 (_CRYPTO_CMD_INSTR_SELDDATA0DATA1 << 0) /**< Shifted mode SELDDATA0DATA1 for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_SELDDATA1DATA1 (_CRYPTO_CMD_INSTR_SELDDATA1DATA1 << 0) /**< Shifted mode SELDDATA1DATA1 for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_SELDDATA2DATA1 (_CRYPTO_CMD_INSTR_SELDDATA2DATA1 << 0) /**< Shifted mode SELDDATA2DATA1 for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_SELDDATA3DATA1 (_CRYPTO_CMD_INSTR_SELDDATA3DATA1 << 0) /**< Shifted mode SELDDATA3DATA1 for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_SELDDATA4DATA1 (_CRYPTO_CMD_INSTR_SELDDATA4DATA1 << 0) /**< Shifted mode SELDDATA4DATA1 for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_SELDATA0DATA1 (_CRYPTO_CMD_INSTR_SELDATA0DATA1 << 0) /**< Shifted mode SELDATA0DATA1 for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_SELDATA1DATA1 (_CRYPTO_CMD_INSTR_SELDATA1DATA1 << 0) /**< Shifted mode SELDATA1DATA1 for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_SELDATA2DATA1 (_CRYPTO_CMD_INSTR_SELDATA2DATA1 << 0) /**< Shifted mode SELDATA2DATA1 for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_EXECIFA (_CRYPTO_CMD_INSTR_EXECIFA << 0) /**< Shifted mode EXECIFA for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_EXECIFB (_CRYPTO_CMD_INSTR_EXECIFB << 0) /**< Shifted mode EXECIFB for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_EXECIFNLAST (_CRYPTO_CMD_INSTR_EXECIFNLAST << 0) /**< Shifted mode EXECIFNLAST for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_EXECIFLAST (_CRYPTO_CMD_INSTR_EXECIFLAST << 0) /**< Shifted mode EXECIFLAST for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_EXECIFCARRY (_CRYPTO_CMD_INSTR_EXECIFCARRY << 0) /**< Shifted mode EXECIFCARRY for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_EXECIFNCARRY (_CRYPTO_CMD_INSTR_EXECIFNCARRY << 0) /**< Shifted mode EXECIFNCARRY for CRYPTO_CMD */ #define CRYPTO_CMD_INSTR_EXECALWAYS (_CRYPTO_CMD_INSTR_EXECALWAYS << 0) /**< Shifted mode EXECALWAYS for CRYPTO_CMD */ #define CRYPTO_CMD_SEQSTART (0x1UL << 9) /**< Encryption/Decryption SEQUENCE Start */ #define _CRYPTO_CMD_SEQSTART_SHIFT 9 /**< Shift value for CRYPTO_SEQSTART */ #define _CRYPTO_CMD_SEQSTART_MASK 0x200UL /**< Bit mask for CRYPTO_SEQSTART */ #define _CRYPTO_CMD_SEQSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CMD */ #define CRYPTO_CMD_SEQSTART_DEFAULT (_CRYPTO_CMD_SEQSTART_DEFAULT << 9) /**< Shifted mode DEFAULT for CRYPTO_CMD */ #define CRYPTO_CMD_SEQSTOP (0x1UL << 10) /**< Sequence Stop */ #define _CRYPTO_CMD_SEQSTOP_SHIFT 10 /**< Shift value for CRYPTO_SEQSTOP */ #define _CRYPTO_CMD_SEQSTOP_MASK 0x400UL /**< Bit mask for CRYPTO_SEQSTOP */ #define _CRYPTO_CMD_SEQSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CMD */ #define CRYPTO_CMD_SEQSTOP_DEFAULT (_CRYPTO_CMD_SEQSTOP_DEFAULT << 10) /**< Shifted mode DEFAULT for CRYPTO_CMD */ #define CRYPTO_CMD_SEQSTEP (0x1UL << 11) /**< Sequence Step */ #define _CRYPTO_CMD_SEQSTEP_SHIFT 11 /**< Shift value for CRYPTO_SEQSTEP */ #define _CRYPTO_CMD_SEQSTEP_MASK 0x800UL /**< Bit mask for CRYPTO_SEQSTEP */ #define _CRYPTO_CMD_SEQSTEP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CMD */ #define CRYPTO_CMD_SEQSTEP_DEFAULT (_CRYPTO_CMD_SEQSTEP_DEFAULT << 11) /**< Shifted mode DEFAULT for CRYPTO_CMD */ /* Bit fields for CRYPTO STATUS */ #define _CRYPTO_STATUS_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_STATUS */ #define _CRYPTO_STATUS_MASK 0x00000007UL /**< Mask for CRYPTO_STATUS */ #define CRYPTO_STATUS_SEQRUNNING (0x1UL << 0) /**< AES SEQUENCE Running */ #define _CRYPTO_STATUS_SEQRUNNING_SHIFT 0 /**< Shift value for CRYPTO_SEQRUNNING */ #define _CRYPTO_STATUS_SEQRUNNING_MASK 0x1UL /**< Bit mask for CRYPTO_SEQRUNNING */ #define _CRYPTO_STATUS_SEQRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_STATUS */ #define CRYPTO_STATUS_SEQRUNNING_DEFAULT (_CRYPTO_STATUS_SEQRUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_STATUS */ #define CRYPTO_STATUS_INSTRRUNNING (0x1UL << 1) /**< Action is Active */ #define _CRYPTO_STATUS_INSTRRUNNING_SHIFT 1 /**< Shift value for CRYPTO_INSTRRUNNING */ #define _CRYPTO_STATUS_INSTRRUNNING_MASK 0x2UL /**< Bit mask for CRYPTO_INSTRRUNNING */ #define _CRYPTO_STATUS_INSTRRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_STATUS */ #define CRYPTO_STATUS_INSTRRUNNING_DEFAULT (_CRYPTO_STATUS_INSTRRUNNING_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYPTO_STATUS */ #define CRYPTO_STATUS_DMAACTIVE (0x1UL << 2) /**< DMA Action is Active */ #define _CRYPTO_STATUS_DMAACTIVE_SHIFT 2 /**< Shift value for CRYPTO_DMAACTIVE */ #define _CRYPTO_STATUS_DMAACTIVE_MASK 0x4UL /**< Bit mask for CRYPTO_DMAACTIVE */ #define _CRYPTO_STATUS_DMAACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_STATUS */ #define CRYPTO_STATUS_DMAACTIVE_DEFAULT (_CRYPTO_STATUS_DMAACTIVE_DEFAULT << 2) /**< Shifted mode DEFAULT for CRYPTO_STATUS */ /* Bit fields for CRYPTO DSTATUS */ #define _CRYPTO_DSTATUS_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DSTATUS */ #define _CRYPTO_DSTATUS_MASK 0x011F0F0FUL /**< Mask for CRYPTO_DSTATUS */ #define _CRYPTO_DSTATUS_DATA0ZERO_SHIFT 0 /**< Shift value for CRYPTO_DATA0ZERO */ #define _CRYPTO_DSTATUS_DATA0ZERO_MASK 0xFUL /**< Bit mask for CRYPTO_DATA0ZERO */ #define _CRYPTO_DSTATUS_DATA0ZERO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DSTATUS */ #define _CRYPTO_DSTATUS_DATA0ZERO_ZERO0TO31 0x00000001UL /**< Mode ZERO0TO31 for CRYPTO_DSTATUS */ #define _CRYPTO_DSTATUS_DATA0ZERO_ZERO32TO63 0x00000002UL /**< Mode ZERO32TO63 for CRYPTO_DSTATUS */ #define _CRYPTO_DSTATUS_DATA0ZERO_ZERO64TO95 0x00000004UL /**< Mode ZERO64TO95 for CRYPTO_DSTATUS */ #define _CRYPTO_DSTATUS_DATA0ZERO_ZERO96TO127 0x00000008UL /**< Mode ZERO96TO127 for CRYPTO_DSTATUS */ #define CRYPTO_DSTATUS_DATA0ZERO_DEFAULT (_CRYPTO_DSTATUS_DATA0ZERO_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DSTATUS */ #define CRYPTO_DSTATUS_DATA0ZERO_ZERO0TO31 (_CRYPTO_DSTATUS_DATA0ZERO_ZERO0TO31 << 0) /**< Shifted mode ZERO0TO31 for CRYPTO_DSTATUS */ #define CRYPTO_DSTATUS_DATA0ZERO_ZERO32TO63 (_CRYPTO_DSTATUS_DATA0ZERO_ZERO32TO63 << 0) /**< Shifted mode ZERO32TO63 for CRYPTO_DSTATUS */ #define CRYPTO_DSTATUS_DATA0ZERO_ZERO64TO95 (_CRYPTO_DSTATUS_DATA0ZERO_ZERO64TO95 << 0) /**< Shifted mode ZERO64TO95 for CRYPTO_DSTATUS */ #define CRYPTO_DSTATUS_DATA0ZERO_ZERO96TO127 (_CRYPTO_DSTATUS_DATA0ZERO_ZERO96TO127 << 0) /**< Shifted mode ZERO96TO127 for CRYPTO_DSTATUS */ #define _CRYPTO_DSTATUS_DDATA0LSBS_SHIFT 8 /**< Shift value for CRYPTO_DDATA0LSBS */ #define _CRYPTO_DSTATUS_DDATA0LSBS_MASK 0xF00UL /**< Bit mask for CRYPTO_DDATA0LSBS */ #define _CRYPTO_DSTATUS_DDATA0LSBS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DSTATUS */ #define CRYPTO_DSTATUS_DDATA0LSBS_DEFAULT (_CRYPTO_DSTATUS_DDATA0LSBS_DEFAULT << 8) /**< Shifted mode DEFAULT for CRYPTO_DSTATUS */ #define _CRYPTO_DSTATUS_DDATA0MSBS_SHIFT 16 /**< Shift value for CRYPTO_DDATA0MSBS */ #define _CRYPTO_DSTATUS_DDATA0MSBS_MASK 0xF0000UL /**< Bit mask for CRYPTO_DDATA0MSBS */ #define _CRYPTO_DSTATUS_DDATA0MSBS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DSTATUS */ #define CRYPTO_DSTATUS_DDATA0MSBS_DEFAULT (_CRYPTO_DSTATUS_DDATA0MSBS_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTO_DSTATUS */ #define CRYPTO_DSTATUS_DDATA1MSB (0x1UL << 20) /**< MSB in DDATA1 */ #define _CRYPTO_DSTATUS_DDATA1MSB_SHIFT 20 /**< Shift value for CRYPTO_DDATA1MSB */ #define _CRYPTO_DSTATUS_DDATA1MSB_MASK 0x100000UL /**< Bit mask for CRYPTO_DDATA1MSB */ #define _CRYPTO_DSTATUS_DDATA1MSB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DSTATUS */ #define CRYPTO_DSTATUS_DDATA1MSB_DEFAULT (_CRYPTO_DSTATUS_DDATA1MSB_DEFAULT << 20) /**< Shifted mode DEFAULT for CRYPTO_DSTATUS */ #define CRYPTO_DSTATUS_CARRY (0x1UL << 24) /**< Carry From Arithmetic Operation */ #define _CRYPTO_DSTATUS_CARRY_SHIFT 24 /**< Shift value for CRYPTO_CARRY */ #define _CRYPTO_DSTATUS_CARRY_MASK 0x1000000UL /**< Bit mask for CRYPTO_CARRY */ #define _CRYPTO_DSTATUS_CARRY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DSTATUS */ #define CRYPTO_DSTATUS_CARRY_DEFAULT (_CRYPTO_DSTATUS_CARRY_DEFAULT << 24) /**< Shifted mode DEFAULT for CRYPTO_DSTATUS */ /* Bit fields for CRYPTO CSTATUS */ #define _CRYPTO_CSTATUS_RESETVALUE 0x00000201UL /**< Default value for CRYPTO_CSTATUS */ #define _CRYPTO_CSTATUS_MASK 0x01F30707UL /**< Mask for CRYPTO_CSTATUS */ #define _CRYPTO_CSTATUS_V0_SHIFT 0 /**< Shift value for CRYPTO_V0 */ #define _CRYPTO_CSTATUS_V0_MASK 0x7UL /**< Bit mask for CRYPTO_V0 */ #define _CRYPTO_CSTATUS_V0_DDATA0 0x00000000UL /**< Mode DDATA0 for CRYPTO_CSTATUS */ #define _CRYPTO_CSTATUS_V0_DEFAULT 0x00000001UL /**< Mode DEFAULT for CRYPTO_CSTATUS */ #define _CRYPTO_CSTATUS_V0_DDATA1 0x00000001UL /**< Mode DDATA1 for CRYPTO_CSTATUS */ #define _CRYPTO_CSTATUS_V0_DDATA2 0x00000002UL /**< Mode DDATA2 for CRYPTO_CSTATUS */ #define _CRYPTO_CSTATUS_V0_DDATA3 0x00000003UL /**< Mode DDATA3 for CRYPTO_CSTATUS */ #define _CRYPTO_CSTATUS_V0_DDATA4 0x00000004UL /**< Mode DDATA4 for CRYPTO_CSTATUS */ #define _CRYPTO_CSTATUS_V0_DATA0 0x00000005UL /**< Mode DATA0 for CRYPTO_CSTATUS */ #define _CRYPTO_CSTATUS_V0_DATA1 0x00000006UL /**< Mode DATA1 for CRYPTO_CSTATUS */ #define _CRYPTO_CSTATUS_V0_DATA2 0x00000007UL /**< Mode DATA2 for CRYPTO_CSTATUS */ #define CRYPTO_CSTATUS_V0_DDATA0 (_CRYPTO_CSTATUS_V0_DDATA0 << 0) /**< Shifted mode DDATA0 for CRYPTO_CSTATUS */ #define CRYPTO_CSTATUS_V0_DEFAULT (_CRYPTO_CSTATUS_V0_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_CSTATUS */ #define CRYPTO_CSTATUS_V0_DDATA1 (_CRYPTO_CSTATUS_V0_DDATA1 << 0) /**< Shifted mode DDATA1 for CRYPTO_CSTATUS */ #define CRYPTO_CSTATUS_V0_DDATA2 (_CRYPTO_CSTATUS_V0_DDATA2 << 0) /**< Shifted mode DDATA2 for CRYPTO_CSTATUS */ #define CRYPTO_CSTATUS_V0_DDATA3 (_CRYPTO_CSTATUS_V0_DDATA3 << 0) /**< Shifted mode DDATA3 for CRYPTO_CSTATUS */ #define CRYPTO_CSTATUS_V0_DDATA4 (_CRYPTO_CSTATUS_V0_DDATA4 << 0) /**< Shifted mode DDATA4 for CRYPTO_CSTATUS */ #define CRYPTO_CSTATUS_V0_DATA0 (_CRYPTO_CSTATUS_V0_DATA0 << 0) /**< Shifted mode DATA0 for CRYPTO_CSTATUS */ #define CRYPTO_CSTATUS_V0_DATA1 (_CRYPTO_CSTATUS_V0_DATA1 << 0) /**< Shifted mode DATA1 for CRYPTO_CSTATUS */ #define CRYPTO_CSTATUS_V0_DATA2 (_CRYPTO_CSTATUS_V0_DATA2 << 0) /**< Shifted mode DATA2 for CRYPTO_CSTATUS */ #define _CRYPTO_CSTATUS_V1_SHIFT 8 /**< Shift value for CRYPTO_V1 */ #define _CRYPTO_CSTATUS_V1_MASK 0x700UL /**< Bit mask for CRYPTO_V1 */ #define _CRYPTO_CSTATUS_V1_DDATA0 0x00000000UL /**< Mode DDATA0 for CRYPTO_CSTATUS */ #define _CRYPTO_CSTATUS_V1_DDATA1 0x00000001UL /**< Mode DDATA1 for CRYPTO_CSTATUS */ #define _CRYPTO_CSTATUS_V1_DEFAULT 0x00000002UL /**< Mode DEFAULT for CRYPTO_CSTATUS */ #define _CRYPTO_CSTATUS_V1_DDATA2 0x00000002UL /**< Mode DDATA2 for CRYPTO_CSTATUS */ #define _CRYPTO_CSTATUS_V1_DDATA3 0x00000003UL /**< Mode DDATA3 for CRYPTO_CSTATUS */ #define _CRYPTO_CSTATUS_V1_DDATA4 0x00000004UL /**< Mode DDATA4 for CRYPTO_CSTATUS */ #define _CRYPTO_CSTATUS_V1_DATA0 0x00000005UL /**< Mode DATA0 for CRYPTO_CSTATUS */ #define _CRYPTO_CSTATUS_V1_DATA1 0x00000006UL /**< Mode DATA1 for CRYPTO_CSTATUS */ #define _CRYPTO_CSTATUS_V1_DATA2 0x00000007UL /**< Mode DATA2 for CRYPTO_CSTATUS */ #define CRYPTO_CSTATUS_V1_DDATA0 (_CRYPTO_CSTATUS_V1_DDATA0 << 8) /**< Shifted mode DDATA0 for CRYPTO_CSTATUS */ #define CRYPTO_CSTATUS_V1_DDATA1 (_CRYPTO_CSTATUS_V1_DDATA1 << 8) /**< Shifted mode DDATA1 for CRYPTO_CSTATUS */ #define CRYPTO_CSTATUS_V1_DEFAULT (_CRYPTO_CSTATUS_V1_DEFAULT << 8) /**< Shifted mode DEFAULT for CRYPTO_CSTATUS */ #define CRYPTO_CSTATUS_V1_DDATA2 (_CRYPTO_CSTATUS_V1_DDATA2 << 8) /**< Shifted mode DDATA2 for CRYPTO_CSTATUS */ #define CRYPTO_CSTATUS_V1_DDATA3 (_CRYPTO_CSTATUS_V1_DDATA3 << 8) /**< Shifted mode DDATA3 for CRYPTO_CSTATUS */ #define CRYPTO_CSTATUS_V1_DDATA4 (_CRYPTO_CSTATUS_V1_DDATA4 << 8) /**< Shifted mode DDATA4 for CRYPTO_CSTATUS */ #define CRYPTO_CSTATUS_V1_DATA0 (_CRYPTO_CSTATUS_V1_DATA0 << 8) /**< Shifted mode DATA0 for CRYPTO_CSTATUS */ #define CRYPTO_CSTATUS_V1_DATA1 (_CRYPTO_CSTATUS_V1_DATA1 << 8) /**< Shifted mode DATA1 for CRYPTO_CSTATUS */ #define CRYPTO_CSTATUS_V1_DATA2 (_CRYPTO_CSTATUS_V1_DATA2 << 8) /**< Shifted mode DATA2 for CRYPTO_CSTATUS */ #define CRYPTO_CSTATUS_SEQPART (0x1UL << 16) /**< Sequence Part */ #define _CRYPTO_CSTATUS_SEQPART_SHIFT 16 /**< Shift value for CRYPTO_SEQPART */ #define _CRYPTO_CSTATUS_SEQPART_MASK 0x10000UL /**< Bit mask for CRYPTO_SEQPART */ #define _CRYPTO_CSTATUS_SEQPART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CSTATUS */ #define _CRYPTO_CSTATUS_SEQPART_SEQA 0x00000000UL /**< Mode SEQA for CRYPTO_CSTATUS */ #define _CRYPTO_CSTATUS_SEQPART_SEQB 0x00000001UL /**< Mode SEQB for CRYPTO_CSTATUS */ #define CRYPTO_CSTATUS_SEQPART_DEFAULT (_CRYPTO_CSTATUS_SEQPART_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTO_CSTATUS */ #define CRYPTO_CSTATUS_SEQPART_SEQA (_CRYPTO_CSTATUS_SEQPART_SEQA << 16) /**< Shifted mode SEQA for CRYPTO_CSTATUS */ #define CRYPTO_CSTATUS_SEQPART_SEQB (_CRYPTO_CSTATUS_SEQPART_SEQB << 16) /**< Shifted mode SEQB for CRYPTO_CSTATUS */ #define CRYPTO_CSTATUS_SEQSKIP (0x1UL << 17) /**< Sequence Skip Next Instruction */ #define _CRYPTO_CSTATUS_SEQSKIP_SHIFT 17 /**< Shift value for CRYPTO_SEQSKIP */ #define _CRYPTO_CSTATUS_SEQSKIP_MASK 0x20000UL /**< Bit mask for CRYPTO_SEQSKIP */ #define _CRYPTO_CSTATUS_SEQSKIP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CSTATUS */ #define CRYPTO_CSTATUS_SEQSKIP_DEFAULT (_CRYPTO_CSTATUS_SEQSKIP_DEFAULT << 17) /**< Shifted mode DEFAULT for CRYPTO_CSTATUS */ #define _CRYPTO_CSTATUS_SEQIP_SHIFT 20 /**< Shift value for CRYPTO_SEQIP */ #define _CRYPTO_CSTATUS_SEQIP_MASK 0x1F00000UL /**< Bit mask for CRYPTO_SEQIP */ #define _CRYPTO_CSTATUS_SEQIP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CSTATUS */ #define CRYPTO_CSTATUS_SEQIP_DEFAULT (_CRYPTO_CSTATUS_SEQIP_DEFAULT << 20) /**< Shifted mode DEFAULT for CRYPTO_CSTATUS */ /* Bit fields for CRYPTO KEY */ #define _CRYPTO_KEY_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_KEY */ #define _CRYPTO_KEY_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_KEY */ #define _CRYPTO_KEY_KEY_SHIFT 0 /**< Shift value for CRYPTO_KEY */ #define _CRYPTO_KEY_KEY_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_KEY */ #define _CRYPTO_KEY_KEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_KEY */ #define CRYPTO_KEY_KEY_DEFAULT (_CRYPTO_KEY_KEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_KEY */ /* Bit fields for CRYPTO KEYBUF */ #define _CRYPTO_KEYBUF_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_KEYBUF */ #define _CRYPTO_KEYBUF_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_KEYBUF */ #define _CRYPTO_KEYBUF_KEYBUF_SHIFT 0 /**< Shift value for CRYPTO_KEYBUF */ #define _CRYPTO_KEYBUF_KEYBUF_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_KEYBUF */ #define _CRYPTO_KEYBUF_KEYBUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_KEYBUF */ #define CRYPTO_KEYBUF_KEYBUF_DEFAULT (_CRYPTO_KEYBUF_KEYBUF_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_KEYBUF */ /* Bit fields for CRYPTO SEQCTRL */ #define _CRYPTO_SEQCTRL_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_SEQCTRL */ #define _CRYPTO_SEQCTRL_MASK 0xBF303FFFUL /**< Mask for CRYPTO_SEQCTRL */ #define _CRYPTO_SEQCTRL_LENGTHA_SHIFT 0 /**< Shift value for CRYPTO_LENGTHA */ #define _CRYPTO_SEQCTRL_LENGTHA_MASK 0x3FFFUL /**< Bit mask for CRYPTO_LENGTHA */ #define _CRYPTO_SEQCTRL_LENGTHA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQCTRL */ #define CRYPTO_SEQCTRL_LENGTHA_DEFAULT (_CRYPTO_SEQCTRL_LENGTHA_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_SEQCTRL */ #define _CRYPTO_SEQCTRL_BLOCKSIZE_SHIFT 20 /**< Shift value for CRYPTO_BLOCKSIZE */ #define _CRYPTO_SEQCTRL_BLOCKSIZE_MASK 0x300000UL /**< Bit mask for CRYPTO_BLOCKSIZE */ #define _CRYPTO_SEQCTRL_BLOCKSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQCTRL */ #define _CRYPTO_SEQCTRL_BLOCKSIZE_16BYTES 0x00000000UL /**< Mode 16BYTES for CRYPTO_SEQCTRL */ #define _CRYPTO_SEQCTRL_BLOCKSIZE_32BYTES 0x00000001UL /**< Mode 32BYTES for CRYPTO_SEQCTRL */ #define _CRYPTO_SEQCTRL_BLOCKSIZE_64BYTES 0x00000002UL /**< Mode 64BYTES for CRYPTO_SEQCTRL */ #define CRYPTO_SEQCTRL_BLOCKSIZE_DEFAULT (_CRYPTO_SEQCTRL_BLOCKSIZE_DEFAULT << 20) /**< Shifted mode DEFAULT for CRYPTO_SEQCTRL */ #define CRYPTO_SEQCTRL_BLOCKSIZE_16BYTES (_CRYPTO_SEQCTRL_BLOCKSIZE_16BYTES << 20) /**< Shifted mode 16BYTES for CRYPTO_SEQCTRL */ #define CRYPTO_SEQCTRL_BLOCKSIZE_32BYTES (_CRYPTO_SEQCTRL_BLOCKSIZE_32BYTES << 20) /**< Shifted mode 32BYTES for CRYPTO_SEQCTRL */ #define CRYPTO_SEQCTRL_BLOCKSIZE_64BYTES (_CRYPTO_SEQCTRL_BLOCKSIZE_64BYTES << 20) /**< Shifted mode 64BYTES for CRYPTO_SEQCTRL */ #define _CRYPTO_SEQCTRL_DMA0SKIP_SHIFT 24 /**< Shift value for CRYPTO_DMA0SKIP */ #define _CRYPTO_SEQCTRL_DMA0SKIP_MASK 0x3000000UL /**< Bit mask for CRYPTO_DMA0SKIP */ #define _CRYPTO_SEQCTRL_DMA0SKIP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQCTRL */ #define CRYPTO_SEQCTRL_DMA0SKIP_DEFAULT (_CRYPTO_SEQCTRL_DMA0SKIP_DEFAULT << 24) /**< Shifted mode DEFAULT for CRYPTO_SEQCTRL */ #define _CRYPTO_SEQCTRL_DMA1SKIP_SHIFT 26 /**< Shift value for CRYPTO_DMA1SKIP */ #define _CRYPTO_SEQCTRL_DMA1SKIP_MASK 0xC000000UL /**< Bit mask for CRYPTO_DMA1SKIP */ #define _CRYPTO_SEQCTRL_DMA1SKIP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQCTRL */ #define CRYPTO_SEQCTRL_DMA1SKIP_DEFAULT (_CRYPTO_SEQCTRL_DMA1SKIP_DEFAULT << 26) /**< Shifted mode DEFAULT for CRYPTO_SEQCTRL */ #define CRYPTO_SEQCTRL_DMA0PRESA (0x1UL << 28) /**< DMA0 Preserve a */ #define _CRYPTO_SEQCTRL_DMA0PRESA_SHIFT 28 /**< Shift value for CRYPTO_DMA0PRESA */ #define _CRYPTO_SEQCTRL_DMA0PRESA_MASK 0x10000000UL /**< Bit mask for CRYPTO_DMA0PRESA */ #define _CRYPTO_SEQCTRL_DMA0PRESA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQCTRL */ #define CRYPTO_SEQCTRL_DMA0PRESA_DEFAULT (_CRYPTO_SEQCTRL_DMA0PRESA_DEFAULT << 28) /**< Shifted mode DEFAULT for CRYPTO_SEQCTRL */ #define CRYPTO_SEQCTRL_DMA1PRESA (0x1UL << 29) /**< DMA1 Preserve a */ #define _CRYPTO_SEQCTRL_DMA1PRESA_SHIFT 29 /**< Shift value for CRYPTO_DMA1PRESA */ #define _CRYPTO_SEQCTRL_DMA1PRESA_MASK 0x20000000UL /**< Bit mask for CRYPTO_DMA1PRESA */ #define _CRYPTO_SEQCTRL_DMA1PRESA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQCTRL */ #define CRYPTO_SEQCTRL_DMA1PRESA_DEFAULT (_CRYPTO_SEQCTRL_DMA1PRESA_DEFAULT << 29) /**< Shifted mode DEFAULT for CRYPTO_SEQCTRL */ #define CRYPTO_SEQCTRL_HALT (0x1UL << 31) /**< Halt Sequence */ #define _CRYPTO_SEQCTRL_HALT_SHIFT 31 /**< Shift value for CRYPTO_HALT */ #define _CRYPTO_SEQCTRL_HALT_MASK 0x80000000UL /**< Bit mask for CRYPTO_HALT */ #define _CRYPTO_SEQCTRL_HALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQCTRL */ #define CRYPTO_SEQCTRL_HALT_DEFAULT (_CRYPTO_SEQCTRL_HALT_DEFAULT << 31) /**< Shifted mode DEFAULT for CRYPTO_SEQCTRL */ /* Bit fields for CRYPTO SEQCTRLB */ #define _CRYPTO_SEQCTRLB_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_SEQCTRLB */ #define _CRYPTO_SEQCTRLB_MASK 0x30003FFFUL /**< Mask for CRYPTO_SEQCTRLB */ #define _CRYPTO_SEQCTRLB_LENGTHB_SHIFT 0 /**< Shift value for CRYPTO_LENGTHB */ #define _CRYPTO_SEQCTRLB_LENGTHB_MASK 0x3FFFUL /**< Bit mask for CRYPTO_LENGTHB */ #define _CRYPTO_SEQCTRLB_LENGTHB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQCTRLB */ #define CRYPTO_SEQCTRLB_LENGTHB_DEFAULT (_CRYPTO_SEQCTRLB_LENGTHB_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_SEQCTRLB */ #define CRYPTO_SEQCTRLB_DMA0PRESB (0x1UL << 28) /**< DMA0 Preserve B */ #define _CRYPTO_SEQCTRLB_DMA0PRESB_SHIFT 28 /**< Shift value for CRYPTO_DMA0PRESB */ #define _CRYPTO_SEQCTRLB_DMA0PRESB_MASK 0x10000000UL /**< Bit mask for CRYPTO_DMA0PRESB */ #define _CRYPTO_SEQCTRLB_DMA0PRESB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQCTRLB */ #define CRYPTO_SEQCTRLB_DMA0PRESB_DEFAULT (_CRYPTO_SEQCTRLB_DMA0PRESB_DEFAULT << 28) /**< Shifted mode DEFAULT for CRYPTO_SEQCTRLB */ #define CRYPTO_SEQCTRLB_DMA1PRESB (0x1UL << 29) /**< DMA1 Preserve B */ #define _CRYPTO_SEQCTRLB_DMA1PRESB_SHIFT 29 /**< Shift value for CRYPTO_DMA1PRESB */ #define _CRYPTO_SEQCTRLB_DMA1PRESB_MASK 0x20000000UL /**< Bit mask for CRYPTO_DMA1PRESB */ #define _CRYPTO_SEQCTRLB_DMA1PRESB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQCTRLB */ #define CRYPTO_SEQCTRLB_DMA1PRESB_DEFAULT (_CRYPTO_SEQCTRLB_DMA1PRESB_DEFAULT << 29) /**< Shifted mode DEFAULT for CRYPTO_SEQCTRLB */ /* Bit fields for CRYPTO IF */ #define _CRYPTO_IF_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_IF */ #define _CRYPTO_IF_MASK 0x00000003UL /**< Mask for CRYPTO_IF */ #define CRYPTO_IF_INSTRDONE (0x1UL << 0) /**< Instruction Done */ #define _CRYPTO_IF_INSTRDONE_SHIFT 0 /**< Shift value for CRYPTO_INSTRDONE */ #define _CRYPTO_IF_INSTRDONE_MASK 0x1UL /**< Bit mask for CRYPTO_INSTRDONE */ #define _CRYPTO_IF_INSTRDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_IF */ #define CRYPTO_IF_INSTRDONE_DEFAULT (_CRYPTO_IF_INSTRDONE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_IF */ #define CRYPTO_IF_SEQDONE (0x1UL << 1) /**< Sequence Done */ #define _CRYPTO_IF_SEQDONE_SHIFT 1 /**< Shift value for CRYPTO_SEQDONE */ #define _CRYPTO_IF_SEQDONE_MASK 0x2UL /**< Bit mask for CRYPTO_SEQDONE */ #define _CRYPTO_IF_SEQDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_IF */ #define CRYPTO_IF_SEQDONE_DEFAULT (_CRYPTO_IF_SEQDONE_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYPTO_IF */ /* Bit fields for CRYPTO IFS */ #define _CRYPTO_IFS_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_IFS */ #define _CRYPTO_IFS_MASK 0x00000003UL /**< Mask for CRYPTO_IFS */ #define CRYPTO_IFS_INSTRDONE (0x1UL << 0) /**< Set INSTRDONE Interrupt Flag */ #define _CRYPTO_IFS_INSTRDONE_SHIFT 0 /**< Shift value for CRYPTO_INSTRDONE */ #define _CRYPTO_IFS_INSTRDONE_MASK 0x1UL /**< Bit mask for CRYPTO_INSTRDONE */ #define _CRYPTO_IFS_INSTRDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_IFS */ #define CRYPTO_IFS_INSTRDONE_DEFAULT (_CRYPTO_IFS_INSTRDONE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_IFS */ #define CRYPTO_IFS_SEQDONE (0x1UL << 1) /**< Set SEQDONE Interrupt Flag */ #define _CRYPTO_IFS_SEQDONE_SHIFT 1 /**< Shift value for CRYPTO_SEQDONE */ #define _CRYPTO_IFS_SEQDONE_MASK 0x2UL /**< Bit mask for CRYPTO_SEQDONE */ #define _CRYPTO_IFS_SEQDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_IFS */ #define CRYPTO_IFS_SEQDONE_DEFAULT (_CRYPTO_IFS_SEQDONE_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYPTO_IFS */ /* Bit fields for CRYPTO IFC */ #define _CRYPTO_IFC_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_IFC */ #define _CRYPTO_IFC_MASK 0x00000003UL /**< Mask for CRYPTO_IFC */ #define CRYPTO_IFC_INSTRDONE (0x1UL << 0) /**< Clear INSTRDONE Interrupt Flag */ #define _CRYPTO_IFC_INSTRDONE_SHIFT 0 /**< Shift value for CRYPTO_INSTRDONE */ #define _CRYPTO_IFC_INSTRDONE_MASK 0x1UL /**< Bit mask for CRYPTO_INSTRDONE */ #define _CRYPTO_IFC_INSTRDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_IFC */ #define CRYPTO_IFC_INSTRDONE_DEFAULT (_CRYPTO_IFC_INSTRDONE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_IFC */ #define CRYPTO_IFC_SEQDONE (0x1UL << 1) /**< Clear SEQDONE Interrupt Flag */ #define _CRYPTO_IFC_SEQDONE_SHIFT 1 /**< Shift value for CRYPTO_SEQDONE */ #define _CRYPTO_IFC_SEQDONE_MASK 0x2UL /**< Bit mask for CRYPTO_SEQDONE */ #define _CRYPTO_IFC_SEQDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_IFC */ #define CRYPTO_IFC_SEQDONE_DEFAULT (_CRYPTO_IFC_SEQDONE_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYPTO_IFC */ /* Bit fields for CRYPTO IEN */ #define _CRYPTO_IEN_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_IEN */ #define _CRYPTO_IEN_MASK 0x00000003UL /**< Mask for CRYPTO_IEN */ #define CRYPTO_IEN_INSTRDONE (0x1UL << 0) /**< INSTRDONE Interrupt Enable */ #define _CRYPTO_IEN_INSTRDONE_SHIFT 0 /**< Shift value for CRYPTO_INSTRDONE */ #define _CRYPTO_IEN_INSTRDONE_MASK 0x1UL /**< Bit mask for CRYPTO_INSTRDONE */ #define _CRYPTO_IEN_INSTRDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_IEN */ #define CRYPTO_IEN_INSTRDONE_DEFAULT (_CRYPTO_IEN_INSTRDONE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_IEN */ #define CRYPTO_IEN_SEQDONE (0x1UL << 1) /**< SEQDONE Interrupt Enable */ #define _CRYPTO_IEN_SEQDONE_SHIFT 1 /**< Shift value for CRYPTO_SEQDONE */ #define _CRYPTO_IEN_SEQDONE_MASK 0x2UL /**< Bit mask for CRYPTO_SEQDONE */ #define _CRYPTO_IEN_SEQDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_IEN */ #define CRYPTO_IEN_SEQDONE_DEFAULT (_CRYPTO_IEN_SEQDONE_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYPTO_IEN */ /* Bit fields for CRYPTO SEQ0 */ #define _CRYPTO_SEQ0_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_SEQ0 */ #define _CRYPTO_SEQ0_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_SEQ0 */ #define _CRYPTO_SEQ0_INSTR0_SHIFT 0 /**< Shift value for CRYPTO_INSTR0 */ #define _CRYPTO_SEQ0_INSTR0_MASK 0xFFUL /**< Bit mask for CRYPTO_INSTR0 */ #define _CRYPTO_SEQ0_INSTR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ0 */ #define CRYPTO_SEQ0_INSTR0_DEFAULT (_CRYPTO_SEQ0_INSTR0_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_SEQ0 */ #define _CRYPTO_SEQ0_INSTR1_SHIFT 8 /**< Shift value for CRYPTO_INSTR1 */ #define _CRYPTO_SEQ0_INSTR1_MASK 0xFF00UL /**< Bit mask for CRYPTO_INSTR1 */ #define _CRYPTO_SEQ0_INSTR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ0 */ #define CRYPTO_SEQ0_INSTR1_DEFAULT (_CRYPTO_SEQ0_INSTR1_DEFAULT << 8) /**< Shifted mode DEFAULT for CRYPTO_SEQ0 */ #define _CRYPTO_SEQ0_INSTR2_SHIFT 16 /**< Shift value for CRYPTO_INSTR2 */ #define _CRYPTO_SEQ0_INSTR2_MASK 0xFF0000UL /**< Bit mask for CRYPTO_INSTR2 */ #define _CRYPTO_SEQ0_INSTR2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ0 */ #define CRYPTO_SEQ0_INSTR2_DEFAULT (_CRYPTO_SEQ0_INSTR2_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTO_SEQ0 */ #define _CRYPTO_SEQ0_INSTR3_SHIFT 24 /**< Shift value for CRYPTO_INSTR3 */ #define _CRYPTO_SEQ0_INSTR3_MASK 0xFF000000UL /**< Bit mask for CRYPTO_INSTR3 */ #define _CRYPTO_SEQ0_INSTR3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ0 */ #define CRYPTO_SEQ0_INSTR3_DEFAULT (_CRYPTO_SEQ0_INSTR3_DEFAULT << 24) /**< Shifted mode DEFAULT for CRYPTO_SEQ0 */ /* Bit fields for CRYPTO SEQ1 */ #define _CRYPTO_SEQ1_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_SEQ1 */ #define _CRYPTO_SEQ1_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_SEQ1 */ #define _CRYPTO_SEQ1_INSTR4_SHIFT 0 /**< Shift value for CRYPTO_INSTR4 */ #define _CRYPTO_SEQ1_INSTR4_MASK 0xFFUL /**< Bit mask for CRYPTO_INSTR4 */ #define _CRYPTO_SEQ1_INSTR4_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ1 */ #define CRYPTO_SEQ1_INSTR4_DEFAULT (_CRYPTO_SEQ1_INSTR4_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_SEQ1 */ #define _CRYPTO_SEQ1_INSTR5_SHIFT 8 /**< Shift value for CRYPTO_INSTR5 */ #define _CRYPTO_SEQ1_INSTR5_MASK 0xFF00UL /**< Bit mask for CRYPTO_INSTR5 */ #define _CRYPTO_SEQ1_INSTR5_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ1 */ #define CRYPTO_SEQ1_INSTR5_DEFAULT (_CRYPTO_SEQ1_INSTR5_DEFAULT << 8) /**< Shifted mode DEFAULT for CRYPTO_SEQ1 */ #define _CRYPTO_SEQ1_INSTR6_SHIFT 16 /**< Shift value for CRYPTO_INSTR6 */ #define _CRYPTO_SEQ1_INSTR6_MASK 0xFF0000UL /**< Bit mask for CRYPTO_INSTR6 */ #define _CRYPTO_SEQ1_INSTR6_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ1 */ #define CRYPTO_SEQ1_INSTR6_DEFAULT (_CRYPTO_SEQ1_INSTR6_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTO_SEQ1 */ #define _CRYPTO_SEQ1_INSTR7_SHIFT 24 /**< Shift value for CRYPTO_INSTR7 */ #define _CRYPTO_SEQ1_INSTR7_MASK 0xFF000000UL /**< Bit mask for CRYPTO_INSTR7 */ #define _CRYPTO_SEQ1_INSTR7_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ1 */ #define CRYPTO_SEQ1_INSTR7_DEFAULT (_CRYPTO_SEQ1_INSTR7_DEFAULT << 24) /**< Shifted mode DEFAULT for CRYPTO_SEQ1 */ /* Bit fields for CRYPTO SEQ2 */ #define _CRYPTO_SEQ2_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_SEQ2 */ #define _CRYPTO_SEQ2_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_SEQ2 */ #define _CRYPTO_SEQ2_INSTR8_SHIFT 0 /**< Shift value for CRYPTO_INSTR8 */ #define _CRYPTO_SEQ2_INSTR8_MASK 0xFFUL /**< Bit mask for CRYPTO_INSTR8 */ #define _CRYPTO_SEQ2_INSTR8_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ2 */ #define CRYPTO_SEQ2_INSTR8_DEFAULT (_CRYPTO_SEQ2_INSTR8_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_SEQ2 */ #define _CRYPTO_SEQ2_INSTR9_SHIFT 8 /**< Shift value for CRYPTO_INSTR9 */ #define _CRYPTO_SEQ2_INSTR9_MASK 0xFF00UL /**< Bit mask for CRYPTO_INSTR9 */ #define _CRYPTO_SEQ2_INSTR9_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ2 */ #define CRYPTO_SEQ2_INSTR9_DEFAULT (_CRYPTO_SEQ2_INSTR9_DEFAULT << 8) /**< Shifted mode DEFAULT for CRYPTO_SEQ2 */ #define _CRYPTO_SEQ2_INSTR10_SHIFT 16 /**< Shift value for CRYPTO_INSTR10 */ #define _CRYPTO_SEQ2_INSTR10_MASK 0xFF0000UL /**< Bit mask for CRYPTO_INSTR10 */ #define _CRYPTO_SEQ2_INSTR10_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ2 */ #define CRYPTO_SEQ2_INSTR10_DEFAULT (_CRYPTO_SEQ2_INSTR10_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTO_SEQ2 */ #define _CRYPTO_SEQ2_INSTR11_SHIFT 24 /**< Shift value for CRYPTO_INSTR11 */ #define _CRYPTO_SEQ2_INSTR11_MASK 0xFF000000UL /**< Bit mask for CRYPTO_INSTR11 */ #define _CRYPTO_SEQ2_INSTR11_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ2 */ #define CRYPTO_SEQ2_INSTR11_DEFAULT (_CRYPTO_SEQ2_INSTR11_DEFAULT << 24) /**< Shifted mode DEFAULT for CRYPTO_SEQ2 */ /* Bit fields for CRYPTO SEQ3 */ #define _CRYPTO_SEQ3_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_SEQ3 */ #define _CRYPTO_SEQ3_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_SEQ3 */ #define _CRYPTO_SEQ3_INSTR12_SHIFT 0 /**< Shift value for CRYPTO_INSTR12 */ #define _CRYPTO_SEQ3_INSTR12_MASK 0xFFUL /**< Bit mask for CRYPTO_INSTR12 */ #define _CRYPTO_SEQ3_INSTR12_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ3 */ #define CRYPTO_SEQ3_INSTR12_DEFAULT (_CRYPTO_SEQ3_INSTR12_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_SEQ3 */ #define _CRYPTO_SEQ3_INSTR13_SHIFT 8 /**< Shift value for CRYPTO_INSTR13 */ #define _CRYPTO_SEQ3_INSTR13_MASK 0xFF00UL /**< Bit mask for CRYPTO_INSTR13 */ #define _CRYPTO_SEQ3_INSTR13_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ3 */ #define CRYPTO_SEQ3_INSTR13_DEFAULT (_CRYPTO_SEQ3_INSTR13_DEFAULT << 8) /**< Shifted mode DEFAULT for CRYPTO_SEQ3 */ #define _CRYPTO_SEQ3_INSTR14_SHIFT 16 /**< Shift value for CRYPTO_INSTR14 */ #define _CRYPTO_SEQ3_INSTR14_MASK 0xFF0000UL /**< Bit mask for CRYPTO_INSTR14 */ #define _CRYPTO_SEQ3_INSTR14_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ3 */ #define CRYPTO_SEQ3_INSTR14_DEFAULT (_CRYPTO_SEQ3_INSTR14_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTO_SEQ3 */ #define _CRYPTO_SEQ3_INSTR15_SHIFT 24 /**< Shift value for CRYPTO_INSTR15 */ #define _CRYPTO_SEQ3_INSTR15_MASK 0xFF000000UL /**< Bit mask for CRYPTO_INSTR15 */ #define _CRYPTO_SEQ3_INSTR15_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ3 */ #define CRYPTO_SEQ3_INSTR15_DEFAULT (_CRYPTO_SEQ3_INSTR15_DEFAULT << 24) /**< Shifted mode DEFAULT for CRYPTO_SEQ3 */ /* Bit fields for CRYPTO SEQ4 */ #define _CRYPTO_SEQ4_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_SEQ4 */ #define _CRYPTO_SEQ4_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_SEQ4 */ #define _CRYPTO_SEQ4_INSTR16_SHIFT 0 /**< Shift value for CRYPTO_INSTR16 */ #define _CRYPTO_SEQ4_INSTR16_MASK 0xFFUL /**< Bit mask for CRYPTO_INSTR16 */ #define _CRYPTO_SEQ4_INSTR16_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ4 */ #define CRYPTO_SEQ4_INSTR16_DEFAULT (_CRYPTO_SEQ4_INSTR16_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_SEQ4 */ #define _CRYPTO_SEQ4_INSTR17_SHIFT 8 /**< Shift value for CRYPTO_INSTR17 */ #define _CRYPTO_SEQ4_INSTR17_MASK 0xFF00UL /**< Bit mask for CRYPTO_INSTR17 */ #define _CRYPTO_SEQ4_INSTR17_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ4 */ #define CRYPTO_SEQ4_INSTR17_DEFAULT (_CRYPTO_SEQ4_INSTR17_DEFAULT << 8) /**< Shifted mode DEFAULT for CRYPTO_SEQ4 */ #define _CRYPTO_SEQ4_INSTR18_SHIFT 16 /**< Shift value for CRYPTO_INSTR18 */ #define _CRYPTO_SEQ4_INSTR18_MASK 0xFF0000UL /**< Bit mask for CRYPTO_INSTR18 */ #define _CRYPTO_SEQ4_INSTR18_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ4 */ #define CRYPTO_SEQ4_INSTR18_DEFAULT (_CRYPTO_SEQ4_INSTR18_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTO_SEQ4 */ #define _CRYPTO_SEQ4_INSTR19_SHIFT 24 /**< Shift value for CRYPTO_INSTR19 */ #define _CRYPTO_SEQ4_INSTR19_MASK 0xFF000000UL /**< Bit mask for CRYPTO_INSTR19 */ #define _CRYPTO_SEQ4_INSTR19_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ4 */ #define CRYPTO_SEQ4_INSTR19_DEFAULT (_CRYPTO_SEQ4_INSTR19_DEFAULT << 24) /**< Shifted mode DEFAULT for CRYPTO_SEQ4 */ /* Bit fields for CRYPTO DATA0 */ #define _CRYPTO_DATA0_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DATA0 */ #define _CRYPTO_DATA0_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_DATA0 */ #define _CRYPTO_DATA0_DATA0_SHIFT 0 /**< Shift value for CRYPTO_DATA0 */ #define _CRYPTO_DATA0_DATA0_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_DATA0 */ #define _CRYPTO_DATA0_DATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DATA0 */ #define CRYPTO_DATA0_DATA0_DEFAULT (_CRYPTO_DATA0_DATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA0 */ /* Bit fields for CRYPTO DATA1 */ #define _CRYPTO_DATA1_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DATA1 */ #define _CRYPTO_DATA1_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_DATA1 */ #define _CRYPTO_DATA1_DATA1_SHIFT 0 /**< Shift value for CRYPTO_DATA1 */ #define _CRYPTO_DATA1_DATA1_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_DATA1 */ #define _CRYPTO_DATA1_DATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DATA1 */ #define CRYPTO_DATA1_DATA1_DEFAULT (_CRYPTO_DATA1_DATA1_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA1 */ /* Bit fields for CRYPTO DATA2 */ #define _CRYPTO_DATA2_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DATA2 */ #define _CRYPTO_DATA2_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_DATA2 */ #define _CRYPTO_DATA2_DATA2_SHIFT 0 /**< Shift value for CRYPTO_DATA2 */ #define _CRYPTO_DATA2_DATA2_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_DATA2 */ #define _CRYPTO_DATA2_DATA2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DATA2 */ #define CRYPTO_DATA2_DATA2_DEFAULT (_CRYPTO_DATA2_DATA2_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA2 */ /* Bit fields for CRYPTO DATA3 */ #define _CRYPTO_DATA3_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DATA3 */ #define _CRYPTO_DATA3_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_DATA3 */ #define _CRYPTO_DATA3_DATA3_SHIFT 0 /**< Shift value for CRYPTO_DATA3 */ #define _CRYPTO_DATA3_DATA3_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_DATA3 */ #define _CRYPTO_DATA3_DATA3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DATA3 */ #define CRYPTO_DATA3_DATA3_DEFAULT (_CRYPTO_DATA3_DATA3_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA3 */ /* Bit fields for CRYPTO DATA0XOR */ #define _CRYPTO_DATA0XOR_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DATA0XOR */ #define _CRYPTO_DATA0XOR_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_DATA0XOR */ #define _CRYPTO_DATA0XOR_DATA0XOR_SHIFT 0 /**< Shift value for CRYPTO_DATA0XOR */ #define _CRYPTO_DATA0XOR_DATA0XOR_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_DATA0XOR */ #define _CRYPTO_DATA0XOR_DATA0XOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DATA0XOR */ #define CRYPTO_DATA0XOR_DATA0XOR_DEFAULT (_CRYPTO_DATA0XOR_DATA0XOR_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA0XOR */ /* Bit fields for CRYPTO DATA0BYTE */ #define _CRYPTO_DATA0BYTE_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DATA0BYTE */ #define _CRYPTO_DATA0BYTE_MASK 0x000000FFUL /**< Mask for CRYPTO_DATA0BYTE */ #define _CRYPTO_DATA0BYTE_DATA0BYTE_SHIFT 0 /**< Shift value for CRYPTO_DATA0BYTE */ #define _CRYPTO_DATA0BYTE_DATA0BYTE_MASK 0xFFUL /**< Bit mask for CRYPTO_DATA0BYTE */ #define _CRYPTO_DATA0BYTE_DATA0BYTE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DATA0BYTE */ #define CRYPTO_DATA0BYTE_DATA0BYTE_DEFAULT (_CRYPTO_DATA0BYTE_DATA0BYTE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA0BYTE */ /* Bit fields for CRYPTO DATA1BYTE */ #define _CRYPTO_DATA1BYTE_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DATA1BYTE */ #define _CRYPTO_DATA1BYTE_MASK 0x000000FFUL /**< Mask for CRYPTO_DATA1BYTE */ #define _CRYPTO_DATA1BYTE_DATA1BYTE_SHIFT 0 /**< Shift value for CRYPTO_DATA1BYTE */ #define _CRYPTO_DATA1BYTE_DATA1BYTE_MASK 0xFFUL /**< Bit mask for CRYPTO_DATA1BYTE */ #define _CRYPTO_DATA1BYTE_DATA1BYTE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DATA1BYTE */ #define CRYPTO_DATA1BYTE_DATA1BYTE_DEFAULT (_CRYPTO_DATA1BYTE_DATA1BYTE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA1BYTE */ /* Bit fields for CRYPTO DATA0XORBYTE */ #define _CRYPTO_DATA0XORBYTE_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DATA0XORBYTE */ #define _CRYPTO_DATA0XORBYTE_MASK 0x000000FFUL /**< Mask for CRYPTO_DATA0XORBYTE */ #define _CRYPTO_DATA0XORBYTE_DATA0XORBYTE_SHIFT 0 /**< Shift value for CRYPTO_DATA0XORBYTE */ #define _CRYPTO_DATA0XORBYTE_DATA0XORBYTE_MASK 0xFFUL /**< Bit mask for CRYPTO_DATA0XORBYTE */ #define _CRYPTO_DATA0XORBYTE_DATA0XORBYTE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DATA0XORBYTE */ #define CRYPTO_DATA0XORBYTE_DATA0XORBYTE_DEFAULT (_CRYPTO_DATA0XORBYTE_DATA0XORBYTE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA0XORBYTE */ /* Bit fields for CRYPTO DATA0BYTE12 */ #define _CRYPTO_DATA0BYTE12_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DATA0BYTE12 */ #define _CRYPTO_DATA0BYTE12_MASK 0x000000FFUL /**< Mask for CRYPTO_DATA0BYTE12 */ #define _CRYPTO_DATA0BYTE12_DATA0BYTE12_SHIFT 0 /**< Shift value for CRYPTO_DATA0BYTE12 */ #define _CRYPTO_DATA0BYTE12_DATA0BYTE12_MASK 0xFFUL /**< Bit mask for CRYPTO_DATA0BYTE12 */ #define _CRYPTO_DATA0BYTE12_DATA0BYTE12_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DATA0BYTE12 */ #define CRYPTO_DATA0BYTE12_DATA0BYTE12_DEFAULT (_CRYPTO_DATA0BYTE12_DATA0BYTE12_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA0BYTE12 */ /* Bit fields for CRYPTO DATA0BYTE13 */ #define _CRYPTO_DATA0BYTE13_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DATA0BYTE13 */ #define _CRYPTO_DATA0BYTE13_MASK 0x000000FFUL /**< Mask for CRYPTO_DATA0BYTE13 */ #define _CRYPTO_DATA0BYTE13_DATA0BYTE13_SHIFT 0 /**< Shift value for CRYPTO_DATA0BYTE13 */ #define _CRYPTO_DATA0BYTE13_DATA0BYTE13_MASK 0xFFUL /**< Bit mask for CRYPTO_DATA0BYTE13 */ #define _CRYPTO_DATA0BYTE13_DATA0BYTE13_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DATA0BYTE13 */ #define CRYPTO_DATA0BYTE13_DATA0BYTE13_DEFAULT (_CRYPTO_DATA0BYTE13_DATA0BYTE13_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA0BYTE13 */ /* Bit fields for CRYPTO DATA0BYTE14 */ #define _CRYPTO_DATA0BYTE14_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DATA0BYTE14 */ #define _CRYPTO_DATA0BYTE14_MASK 0x000000FFUL /**< Mask for CRYPTO_DATA0BYTE14 */ #define _CRYPTO_DATA0BYTE14_DATA0BYTE14_SHIFT 0 /**< Shift value for CRYPTO_DATA0BYTE14 */ #define _CRYPTO_DATA0BYTE14_DATA0BYTE14_MASK 0xFFUL /**< Bit mask for CRYPTO_DATA0BYTE14 */ #define _CRYPTO_DATA0BYTE14_DATA0BYTE14_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DATA0BYTE14 */ #define CRYPTO_DATA0BYTE14_DATA0BYTE14_DEFAULT (_CRYPTO_DATA0BYTE14_DATA0BYTE14_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA0BYTE14 */ /* Bit fields for CRYPTO DATA0BYTE15 */ #define _CRYPTO_DATA0BYTE15_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DATA0BYTE15 */ #define _CRYPTO_DATA0BYTE15_MASK 0x000000FFUL /**< Mask for CRYPTO_DATA0BYTE15 */ #define _CRYPTO_DATA0BYTE15_DATA0BYTE15_SHIFT 0 /**< Shift value for CRYPTO_DATA0BYTE15 */ #define _CRYPTO_DATA0BYTE15_DATA0BYTE15_MASK 0xFFUL /**< Bit mask for CRYPTO_DATA0BYTE15 */ #define _CRYPTO_DATA0BYTE15_DATA0BYTE15_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DATA0BYTE15 */ #define CRYPTO_DATA0BYTE15_DATA0BYTE15_DEFAULT (_CRYPTO_DATA0BYTE15_DATA0BYTE15_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA0BYTE15 */ /* Bit fields for CRYPTO DDATA0 */ #define _CRYPTO_DDATA0_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DDATA0 */ #define _CRYPTO_DDATA0_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_DDATA0 */ #define _CRYPTO_DDATA0_DDATA0_SHIFT 0 /**< Shift value for CRYPTO_DDATA0 */ #define _CRYPTO_DDATA0_DDATA0_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_DDATA0 */ #define _CRYPTO_DDATA0_DDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DDATA0 */ #define CRYPTO_DDATA0_DDATA0_DEFAULT (_CRYPTO_DDATA0_DDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DDATA0 */ /* Bit fields for CRYPTO DDATA1 */ #define _CRYPTO_DDATA1_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DDATA1 */ #define _CRYPTO_DDATA1_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_DDATA1 */ #define _CRYPTO_DDATA1_DDATA1_SHIFT 0 /**< Shift value for CRYPTO_DDATA1 */ #define _CRYPTO_DDATA1_DDATA1_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_DDATA1 */ #define _CRYPTO_DDATA1_DDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DDATA1 */ #define CRYPTO_DDATA1_DDATA1_DEFAULT (_CRYPTO_DDATA1_DDATA1_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DDATA1 */ /* Bit fields for CRYPTO DDATA2 */ #define _CRYPTO_DDATA2_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DDATA2 */ #define _CRYPTO_DDATA2_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_DDATA2 */ #define _CRYPTO_DDATA2_DDATA2_SHIFT 0 /**< Shift value for CRYPTO_DDATA2 */ #define _CRYPTO_DDATA2_DDATA2_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_DDATA2 */ #define _CRYPTO_DDATA2_DDATA2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DDATA2 */ #define CRYPTO_DDATA2_DDATA2_DEFAULT (_CRYPTO_DDATA2_DDATA2_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DDATA2 */ /* Bit fields for CRYPTO DDATA3 */ #define _CRYPTO_DDATA3_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DDATA3 */ #define _CRYPTO_DDATA3_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_DDATA3 */ #define _CRYPTO_DDATA3_DDATA3_SHIFT 0 /**< Shift value for CRYPTO_DDATA3 */ #define _CRYPTO_DDATA3_DDATA3_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_DDATA3 */ #define _CRYPTO_DDATA3_DDATA3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DDATA3 */ #define CRYPTO_DDATA3_DDATA3_DEFAULT (_CRYPTO_DDATA3_DDATA3_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DDATA3 */ /* Bit fields for CRYPTO DDATA4 */ #define _CRYPTO_DDATA4_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DDATA4 */ #define _CRYPTO_DDATA4_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_DDATA4 */ #define _CRYPTO_DDATA4_DDATA4_SHIFT 0 /**< Shift value for CRYPTO_DDATA4 */ #define _CRYPTO_DDATA4_DDATA4_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_DDATA4 */ #define _CRYPTO_DDATA4_DDATA4_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DDATA4 */ #define CRYPTO_DDATA4_DDATA4_DEFAULT (_CRYPTO_DDATA4_DDATA4_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DDATA4 */ /* Bit fields for CRYPTO DDATA0BIG */ #define _CRYPTO_DDATA0BIG_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DDATA0BIG */ #define _CRYPTO_DDATA0BIG_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_DDATA0BIG */ #define _CRYPTO_DDATA0BIG_DDATA0BIG_SHIFT 0 /**< Shift value for CRYPTO_DDATA0BIG */ #define _CRYPTO_DDATA0BIG_DDATA0BIG_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_DDATA0BIG */ #define _CRYPTO_DDATA0BIG_DDATA0BIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DDATA0BIG */ #define CRYPTO_DDATA0BIG_DDATA0BIG_DEFAULT (_CRYPTO_DDATA0BIG_DDATA0BIG_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DDATA0BIG */ /* Bit fields for CRYPTO DDATA0BYTE */ #define _CRYPTO_DDATA0BYTE_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DDATA0BYTE */ #define _CRYPTO_DDATA0BYTE_MASK 0x000000FFUL /**< Mask for CRYPTO_DDATA0BYTE */ #define _CRYPTO_DDATA0BYTE_DDATA0BYTE_SHIFT 0 /**< Shift value for CRYPTO_DDATA0BYTE */ #define _CRYPTO_DDATA0BYTE_DDATA0BYTE_MASK 0xFFUL /**< Bit mask for CRYPTO_DDATA0BYTE */ #define _CRYPTO_DDATA0BYTE_DDATA0BYTE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DDATA0BYTE */ #define CRYPTO_DDATA0BYTE_DDATA0BYTE_DEFAULT (_CRYPTO_DDATA0BYTE_DDATA0BYTE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DDATA0BYTE */ /* Bit fields for CRYPTO DDATA1BYTE */ #define _CRYPTO_DDATA1BYTE_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DDATA1BYTE */ #define _CRYPTO_DDATA1BYTE_MASK 0x000000FFUL /**< Mask for CRYPTO_DDATA1BYTE */ #define _CRYPTO_DDATA1BYTE_DDATA1BYTE_SHIFT 0 /**< Shift value for CRYPTO_DDATA1BYTE */ #define _CRYPTO_DDATA1BYTE_DDATA1BYTE_MASK 0xFFUL /**< Bit mask for CRYPTO_DDATA1BYTE */ #define _CRYPTO_DDATA1BYTE_DDATA1BYTE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DDATA1BYTE */ #define CRYPTO_DDATA1BYTE_DDATA1BYTE_DEFAULT (_CRYPTO_DDATA1BYTE_DDATA1BYTE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DDATA1BYTE */ /* Bit fields for CRYPTO DDATA0BYTE32 */ #define _CRYPTO_DDATA0BYTE32_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DDATA0BYTE32 */ #define _CRYPTO_DDATA0BYTE32_MASK 0x0000000FUL /**< Mask for CRYPTO_DDATA0BYTE32 */ #define _CRYPTO_DDATA0BYTE32_DDATA0BYTE32_SHIFT 0 /**< Shift value for CRYPTO_DDATA0BYTE32 */ #define _CRYPTO_DDATA0BYTE32_DDATA0BYTE32_MASK 0xFUL /**< Bit mask for CRYPTO_DDATA0BYTE32 */ #define _CRYPTO_DDATA0BYTE32_DDATA0BYTE32_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DDATA0BYTE32 */ #define CRYPTO_DDATA0BYTE32_DDATA0BYTE32_DEFAULT (_CRYPTO_DDATA0BYTE32_DDATA0BYTE32_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DDATA0BYTE32 */ /* Bit fields for CRYPTO QDATA0 */ #define _CRYPTO_QDATA0_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_QDATA0 */ #define _CRYPTO_QDATA0_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_QDATA0 */ #define _CRYPTO_QDATA0_QDATA0_SHIFT 0 /**< Shift value for CRYPTO_QDATA0 */ #define _CRYPTO_QDATA0_QDATA0_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_QDATA0 */ #define _CRYPTO_QDATA0_QDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_QDATA0 */ #define CRYPTO_QDATA0_QDATA0_DEFAULT (_CRYPTO_QDATA0_QDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_QDATA0 */ /* Bit fields for CRYPTO QDATA1 */ #define _CRYPTO_QDATA1_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_QDATA1 */ #define _CRYPTO_QDATA1_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_QDATA1 */ #define _CRYPTO_QDATA1_QDATA1_SHIFT 0 /**< Shift value for CRYPTO_QDATA1 */ #define _CRYPTO_QDATA1_QDATA1_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_QDATA1 */ #define _CRYPTO_QDATA1_QDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_QDATA1 */ #define CRYPTO_QDATA1_QDATA1_DEFAULT (_CRYPTO_QDATA1_QDATA1_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_QDATA1 */ /* Bit fields for CRYPTO QDATA1BIG */ #define _CRYPTO_QDATA1BIG_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_QDATA1BIG */ #define _CRYPTO_QDATA1BIG_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_QDATA1BIG */ #define _CRYPTO_QDATA1BIG_QDATA1BIG_SHIFT 0 /**< Shift value for CRYPTO_QDATA1BIG */ #define _CRYPTO_QDATA1BIG_QDATA1BIG_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_QDATA1BIG */ #define _CRYPTO_QDATA1BIG_QDATA1BIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_QDATA1BIG */ #define CRYPTO_QDATA1BIG_QDATA1BIG_DEFAULT (_CRYPTO_QDATA1BIG_QDATA1BIG_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_QDATA1BIG */ /* Bit fields for CRYPTO QDATA0BYTE */ #define _CRYPTO_QDATA0BYTE_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_QDATA0BYTE */ #define _CRYPTO_QDATA0BYTE_MASK 0x000000FFUL /**< Mask for CRYPTO_QDATA0BYTE */ #define _CRYPTO_QDATA0BYTE_QDATA0BYTE_SHIFT 0 /**< Shift value for CRYPTO_QDATA0BYTE */ #define _CRYPTO_QDATA0BYTE_QDATA0BYTE_MASK 0xFFUL /**< Bit mask for CRYPTO_QDATA0BYTE */ #define _CRYPTO_QDATA0BYTE_QDATA0BYTE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_QDATA0BYTE */ #define CRYPTO_QDATA0BYTE_QDATA0BYTE_DEFAULT (_CRYPTO_QDATA0BYTE_QDATA0BYTE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_QDATA0BYTE */ /* Bit fields for CRYPTO QDATA1BYTE */ #define _CRYPTO_QDATA1BYTE_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_QDATA1BYTE */ #define _CRYPTO_QDATA1BYTE_MASK 0x000000FFUL /**< Mask for CRYPTO_QDATA1BYTE */ #define _CRYPTO_QDATA1BYTE_QDATA1BYTE_SHIFT 0 /**< Shift value for CRYPTO_QDATA1BYTE */ #define _CRYPTO_QDATA1BYTE_QDATA1BYTE_MASK 0xFFUL /**< Bit mask for CRYPTO_QDATA1BYTE */ #define _CRYPTO_QDATA1BYTE_QDATA1BYTE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_QDATA1BYTE */ #define CRYPTO_QDATA1BYTE_QDATA1BYTE_DEFAULT (_CRYPTO_QDATA1BYTE_QDATA1BYTE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_QDATA1BYTE */ /** @} */ /** @} End of group EFR32MG12P_CRYPTO */ /** @} End of group Parts */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_csen.h.
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/***************************************************************************//** * @file * @brief EFR32MG12P_CSEN register and bit field definitions * @version 5.7.0 ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * SPDX-License-Identifier: Zlib * * The licensor of this software is Silicon Laboratories Inc. * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be * appreciated but is not required. * 2. Altered source versions must be plainly marked as such, and must not be * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * ******************************************************************************/ #if defined(__ICCARM__) #pragma system_include /* Treat file as system include file. */ #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang system_header /* Treat file as system include file. */ #endif /***************************************************************************//** * @addtogroup Parts * @{ ******************************************************************************/ /***************************************************************************//** * @defgroup EFR32MG12P_CSEN CSEN * @{ * @brief EFR32MG12P_CSEN Register Declaration ******************************************************************************/ /** CSEN Register Declaration */ typedef struct { __IOM uint32_t CTRL; /**< Control */ __IOM uint32_t TIMCTRL; /**< Timing Control */ __IOM uint32_t CMD; /**< Command */ __IM uint32_t STATUS; /**< Status */ __IOM uint32_t PRSSEL; /**< PRS Select */ __IOM uint32_t DATA; /**< Output Data */ __IOM uint32_t SCANMASK0; /**< Scan Channel Mask 0 */ __IOM uint32_t SCANINPUTSEL0; /**< Scan Input Selection 0 */ __IOM uint32_t SCANMASK1; /**< Scan Channel Mask 1 */ __IOM uint32_t SCANINPUTSEL1; /**< Scan Input Selection 1 */ __IM uint32_t APORTREQ; /**< APORT Request Status */ __IM uint32_t APORTCONFLICT; /**< APORT Request Conflict */ __IOM uint32_t CMPTHR; /**< Comparator Threshold */ __IOM uint32_t EMA; /**< Exponential Moving Average */ __IOM uint32_t EMACTRL; /**< Exponential Moving Average Control */ __IOM uint32_t SINGLECTRL; /**< Single Conversion Control */ __IOM uint32_t DMBASELINE; /**< Delta Modulation Baseline */ __IOM uint32_t DMCFG; /**< Delta Modulation Configuration */ __IOM uint32_t ANACTRL; /**< Analog Control */ uint32_t RESERVED0[2U]; /**< Reserved for future use **/ __IM uint32_t IF; /**< Interrupt Flag */ __IOM uint32_t IFS; /**< Interrupt Flag Set */ __IOM uint32_t IFC; /**< Interrupt Flag Clear */ __IOM uint32_t IEN; /**< Interrupt Enable */ } CSEN_TypeDef; /** @} */ /***************************************************************************//** * @addtogroup EFR32MG12P_CSEN * @{ * @defgroup EFR32MG12P_CSEN_BitFields CSEN Bit Fields * @{ ******************************************************************************/ /* Bit fields for CSEN CTRL */ #define _CSEN_CTRL_RESETVALUE 0x00030000UL /**< Default value for CSEN_CTRL */ #define _CSEN_CTRL_MASK 0x1FFFF336UL /**< Mask for CSEN_CTRL */ #define CSEN_CTRL_EN (0x1UL << 1) /**< CSEN Enable */ #define _CSEN_CTRL_EN_SHIFT 1 /**< Shift value for CSEN_EN */ #define _CSEN_CTRL_EN_MASK 0x2UL /**< Bit mask for CSEN_EN */ #define _CSEN_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ #define _CSEN_CTRL_EN_DISABLE 0x00000000UL /**< Mode DISABLE for CSEN_CTRL */ #define _CSEN_CTRL_EN_ENABLE 0x00000001UL /**< Mode ENABLE for CSEN_CTRL */ #define CSEN_CTRL_EN_DEFAULT (_CSEN_CTRL_EN_DEFAULT << 1) /**< Shifted mode DEFAULT for CSEN_CTRL */ #define CSEN_CTRL_EN_DISABLE (_CSEN_CTRL_EN_DISABLE << 1) /**< Shifted mode DISABLE for CSEN_CTRL */ #define CSEN_CTRL_EN_ENABLE (_CSEN_CTRL_EN_ENABLE << 1) /**< Shifted mode ENABLE for CSEN_CTRL */ #define CSEN_CTRL_CMPPOL (0x1UL << 2) /**< CSEN Digital Comparator Polarity Select */ #define _CSEN_CTRL_CMPPOL_SHIFT 2 /**< Shift value for CSEN_CMPPOL */ #define _CSEN_CTRL_CMPPOL_MASK 0x4UL /**< Bit mask for CSEN_CMPPOL */ #define _CSEN_CTRL_CMPPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ #define _CSEN_CTRL_CMPPOL_GT 0x00000000UL /**< Mode GT for CSEN_CTRL */ #define _CSEN_CTRL_CMPPOL_LTE 0x00000001UL /**< Mode LTE for CSEN_CTRL */ #define CSEN_CTRL_CMPPOL_DEFAULT (_CSEN_CTRL_CMPPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for CSEN_CTRL */ #define CSEN_CTRL_CMPPOL_GT (_CSEN_CTRL_CMPPOL_GT << 2) /**< Shifted mode GT for CSEN_CTRL */ #define CSEN_CTRL_CMPPOL_LTE (_CSEN_CTRL_CMPPOL_LTE << 2) /**< Shifted mode LTE for CSEN_CTRL */ #define _CSEN_CTRL_CM_SHIFT 4 /**< Shift value for CSEN_CM */ #define _CSEN_CTRL_CM_MASK 0x30UL /**< Bit mask for CSEN_CM */ #define _CSEN_CTRL_CM_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ #define _CSEN_CTRL_CM_SGL 0x00000000UL /**< Mode SGL for CSEN_CTRL */ #define _CSEN_CTRL_CM_SCAN 0x00000001UL /**< Mode SCAN for CSEN_CTRL */ #define _CSEN_CTRL_CM_CONTSGL 0x00000002UL /**< Mode CONTSGL for CSEN_CTRL */ #define _CSEN_CTRL_CM_CONTSCAN 0x00000003UL /**< Mode CONTSCAN for CSEN_CTRL */ #define CSEN_CTRL_CM_DEFAULT (_CSEN_CTRL_CM_DEFAULT << 4) /**< Shifted mode DEFAULT for CSEN_CTRL */ #define CSEN_CTRL_CM_SGL (_CSEN_CTRL_CM_SGL << 4) /**< Shifted mode SGL for CSEN_CTRL */ #define CSEN_CTRL_CM_SCAN (_CSEN_CTRL_CM_SCAN << 4) /**< Shifted mode SCAN for CSEN_CTRL */ #define CSEN_CTRL_CM_CONTSGL (_CSEN_CTRL_CM_CONTSGL << 4) /**< Shifted mode CONTSGL for CSEN_CTRL */ #define CSEN_CTRL_CM_CONTSCAN (_CSEN_CTRL_CM_CONTSCAN << 4) /**< Shifted mode CONTSCAN for CSEN_CTRL */ #define _CSEN_CTRL_SARCR_SHIFT 8 /**< Shift value for CSEN_SARCR */ #define _CSEN_CTRL_SARCR_MASK 0x300UL /**< Bit mask for CSEN_SARCR */ #define _CSEN_CTRL_SARCR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ #define _CSEN_CTRL_SARCR_CLK10 0x00000000UL /**< Mode CLK10 for CSEN_CTRL */ #define _CSEN_CTRL_SARCR_CLK12 0x00000001UL /**< Mode CLK12 for CSEN_CTRL */ #define _CSEN_CTRL_SARCR_CLK14 0x00000002UL /**< Mode CLK14 for CSEN_CTRL */ #define _CSEN_CTRL_SARCR_CLK16 0x00000003UL /**< Mode CLK16 for CSEN_CTRL */ #define CSEN_CTRL_SARCR_DEFAULT (_CSEN_CTRL_SARCR_DEFAULT << 8) /**< Shifted mode DEFAULT for CSEN_CTRL */ #define CSEN_CTRL_SARCR_CLK10 (_CSEN_CTRL_SARCR_CLK10 << 8) /**< Shifted mode CLK10 for CSEN_CTRL */ #define CSEN_CTRL_SARCR_CLK12 (_CSEN_CTRL_SARCR_CLK12 << 8) /**< Shifted mode CLK12 for CSEN_CTRL */ #define CSEN_CTRL_SARCR_CLK14 (_CSEN_CTRL_SARCR_CLK14 << 8) /**< Shifted mode CLK14 for CSEN_CTRL */ #define CSEN_CTRL_SARCR_CLK16 (_CSEN_CTRL_SARCR_CLK16 << 8) /**< Shifted mode CLK16 for CSEN_CTRL */ #define _CSEN_CTRL_ACU_SHIFT 12 /**< Shift value for CSEN_ACU */ #define _CSEN_CTRL_ACU_MASK 0x7000UL /**< Bit mask for CSEN_ACU */ #define _CSEN_CTRL_ACU_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ #define _CSEN_CTRL_ACU_ACC1 0x00000000UL /**< Mode ACC1 for CSEN_CTRL */ #define _CSEN_CTRL_ACU_ACC2 0x00000001UL /**< Mode ACC2 for CSEN_CTRL */ #define _CSEN_CTRL_ACU_ACC4 0x00000002UL /**< Mode ACC4 for CSEN_CTRL */ #define _CSEN_CTRL_ACU_ACC8 0x00000003UL /**< Mode ACC8 for CSEN_CTRL */ #define _CSEN_CTRL_ACU_ACC16 0x00000004UL /**< Mode ACC16 for CSEN_CTRL */ #define _CSEN_CTRL_ACU_ACC32 0x00000005UL /**< Mode ACC32 for CSEN_CTRL */ #define _CSEN_CTRL_ACU_ACC64 0x00000006UL /**< Mode ACC64 for CSEN_CTRL */ #define CSEN_CTRL_ACU_DEFAULT (_CSEN_CTRL_ACU_DEFAULT << 12) /**< Shifted mode DEFAULT for CSEN_CTRL */ #define CSEN_CTRL_ACU_ACC1 (_CSEN_CTRL_ACU_ACC1 << 12) /**< Shifted mode ACC1 for CSEN_CTRL */ #define CSEN_CTRL_ACU_ACC2 (_CSEN_CTRL_ACU_ACC2 << 12) /**< Shifted mode ACC2 for CSEN_CTRL */ #define CSEN_CTRL_ACU_ACC4 (_CSEN_CTRL_ACU_ACC4 << 12) /**< Shifted mode ACC4 for CSEN_CTRL */ #define CSEN_CTRL_ACU_ACC8 (_CSEN_CTRL_ACU_ACC8 << 12) /**< Shifted mode ACC8 for CSEN_CTRL */ #define CSEN_CTRL_ACU_ACC16 (_CSEN_CTRL_ACU_ACC16 << 12) /**< Shifted mode ACC16 for CSEN_CTRL */ #define CSEN_CTRL_ACU_ACC32 (_CSEN_CTRL_ACU_ACC32 << 12) /**< Shifted mode ACC32 for CSEN_CTRL */ #define CSEN_CTRL_ACU_ACC64 (_CSEN_CTRL_ACU_ACC64 << 12) /**< Shifted mode ACC64 for CSEN_CTRL */ #define CSEN_CTRL_MCEN (0x1UL << 15) /**< CSEN Multiple Channel Enable */ #define _CSEN_CTRL_MCEN_SHIFT 15 /**< Shift value for CSEN_MCEN */ #define _CSEN_CTRL_MCEN_MASK 0x8000UL /**< Bit mask for CSEN_MCEN */ #define _CSEN_CTRL_MCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ #define _CSEN_CTRL_MCEN_DISABLE 0x00000000UL /**< Mode DISABLE for CSEN_CTRL */ #define _CSEN_CTRL_MCEN_ENABLE 0x00000001UL /**< Mode ENABLE for CSEN_CTRL */ #define CSEN_CTRL_MCEN_DEFAULT (_CSEN_CTRL_MCEN_DEFAULT << 15) /**< Shifted mode DEFAULT for CSEN_CTRL */ #define CSEN_CTRL_MCEN_DISABLE (_CSEN_CTRL_MCEN_DISABLE << 15) /**< Shifted mode DISABLE for CSEN_CTRL */ #define CSEN_CTRL_MCEN_ENABLE (_CSEN_CTRL_MCEN_ENABLE << 15) /**< Shifted mode ENABLE for CSEN_CTRL */ #define _CSEN_CTRL_STM_SHIFT 16 /**< Shift value for CSEN_STM */ #define _CSEN_CTRL_STM_MASK 0x30000UL /**< Bit mask for CSEN_STM */ #define _CSEN_CTRL_STM_PRS 0x00000000UL /**< Mode PRS for CSEN_CTRL */ #define _CSEN_CTRL_STM_TIMER 0x00000001UL /**< Mode TIMER for CSEN_CTRL */ #define _CSEN_CTRL_STM_START 0x00000002UL /**< Mode START for CSEN_CTRL */ #define _CSEN_CTRL_STM_DEFAULT 0x00000003UL /**< Mode DEFAULT for CSEN_CTRL */ #define _CSEN_CTRL_STM_DEFAULT 0x00000003UL /**< Mode DEFAULT for CSEN_CTRL */ #define CSEN_CTRL_STM_PRS (_CSEN_CTRL_STM_PRS << 16) /**< Shifted mode PRS for CSEN_CTRL */ #define CSEN_CTRL_STM_TIMER (_CSEN_CTRL_STM_TIMER << 16) /**< Shifted mode TIMER for CSEN_CTRL */ #define CSEN_CTRL_STM_START (_CSEN_CTRL_STM_START << 16) /**< Shifted mode START for CSEN_CTRL */ #define CSEN_CTRL_STM_DEFAULT (_CSEN_CTRL_STM_DEFAULT << 16) /**< Shifted mode DEFAULT for CSEN_CTRL */ #define CSEN_CTRL_STM_DEFAULT (_CSEN_CTRL_STM_DEFAULT << 16) /**< Shifted mode DEFAULT for CSEN_CTRL */ #define CSEN_CTRL_CMPEN (0x1UL << 18) /**< CSEN Digital Comparator Enable */ #define _CSEN_CTRL_CMPEN_SHIFT 18 /**< Shift value for CSEN_CMPEN */ #define _CSEN_CTRL_CMPEN_MASK 0x40000UL /**< Bit mask for CSEN_CMPEN */ #define _CSEN_CTRL_CMPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ #define _CSEN_CTRL_CMPEN_DISABLE 0x00000000UL /**< Mode DISABLE for CSEN_CTRL */ #define _CSEN_CTRL_CMPEN_ENABLE 0x00000001UL /**< Mode ENABLE for CSEN_CTRL */ #define CSEN_CTRL_CMPEN_DEFAULT (_CSEN_CTRL_CMPEN_DEFAULT << 18) /**< Shifted mode DEFAULT for CSEN_CTRL */ #define CSEN_CTRL_CMPEN_DISABLE (_CSEN_CTRL_CMPEN_DISABLE << 18) /**< Shifted mode DISABLE for CSEN_CTRL */ #define CSEN_CTRL_CMPEN_ENABLE (_CSEN_CTRL_CMPEN_ENABLE << 18) /**< Shifted mode ENABLE for CSEN_CTRL */ #define CSEN_CTRL_DRSF (0x1UL << 19) /**< CSEN Disable Right-Shift */ #define _CSEN_CTRL_DRSF_SHIFT 19 /**< Shift value for CSEN_DRSF */ #define _CSEN_CTRL_DRSF_MASK 0x80000UL /**< Bit mask for CSEN_DRSF */ #define _CSEN_CTRL_DRSF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ #define _CSEN_CTRL_DRSF_DISABLE 0x00000000UL /**< Mode DISABLE for CSEN_CTRL */ #define _CSEN_CTRL_DRSF_ENABLE 0x00000001UL /**< Mode ENABLE for CSEN_CTRL */ #define CSEN_CTRL_DRSF_DEFAULT (_CSEN_CTRL_DRSF_DEFAULT << 19) /**< Shifted mode DEFAULT for CSEN_CTRL */ #define CSEN_CTRL_DRSF_DISABLE (_CSEN_CTRL_DRSF_DISABLE << 19) /**< Shifted mode DISABLE for CSEN_CTRL */ #define CSEN_CTRL_DRSF_ENABLE (_CSEN_CTRL_DRSF_ENABLE << 19) /**< Shifted mode ENABLE for CSEN_CTRL */ #define CSEN_CTRL_DMAEN (0x1UL << 20) /**< CSEN DMA Enable Bit */ #define _CSEN_CTRL_DMAEN_SHIFT 20 /**< Shift value for CSEN_DMAEN */ #define _CSEN_CTRL_DMAEN_MASK 0x100000UL /**< Bit mask for CSEN_DMAEN */ #define _CSEN_CTRL_DMAEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ #define _CSEN_CTRL_DMAEN_DISABLE 0x00000000UL /**< Mode DISABLE for CSEN_CTRL */ #define _CSEN_CTRL_DMAEN_ENABLE 0x00000001UL /**< Mode ENABLE for CSEN_CTRL */ #define CSEN_CTRL_DMAEN_DEFAULT (_CSEN_CTRL_DMAEN_DEFAULT << 20) /**< Shifted mode DEFAULT for CSEN_CTRL */ #define CSEN_CTRL_DMAEN_DISABLE (_CSEN_CTRL_DMAEN_DISABLE << 20) /**< Shifted mode DISABLE for CSEN_CTRL */ #define CSEN_CTRL_DMAEN_ENABLE (_CSEN_CTRL_DMAEN_ENABLE << 20) /**< Shifted mode ENABLE for CSEN_CTRL */ #define CSEN_CTRL_CONVSEL (0x1UL << 21) /**< CSEN Converter Select */ #define _CSEN_CTRL_CONVSEL_SHIFT 21 /**< Shift value for CSEN_CONVSEL */ #define _CSEN_CTRL_CONVSEL_MASK 0x200000UL /**< Bit mask for CSEN_CONVSEL */ #define _CSEN_CTRL_CONVSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ #define _CSEN_CTRL_CONVSEL_SAR 0x00000000UL /**< Mode SAR for CSEN_CTRL */ #define _CSEN_CTRL_CONVSEL_DM 0x00000001UL /**< Mode DM for CSEN_CTRL */ #define CSEN_CTRL_CONVSEL_DEFAULT (_CSEN_CTRL_CONVSEL_DEFAULT << 21) /**< Shifted mode DEFAULT for CSEN_CTRL */ #define CSEN_CTRL_CONVSEL_SAR (_CSEN_CTRL_CONVSEL_SAR << 21) /**< Shifted mode SAR for CSEN_CTRL */ #define CSEN_CTRL_CONVSEL_DM (_CSEN_CTRL_CONVSEL_DM << 21) /**< Shifted mode DM for CSEN_CTRL */ #define CSEN_CTRL_CHOPEN (0x1UL << 22) /**< CSEN Chop Enable */ #define _CSEN_CTRL_CHOPEN_SHIFT 22 /**< Shift value for CSEN_CHOPEN */ #define _CSEN_CTRL_CHOPEN_MASK 0x400000UL /**< Bit mask for CSEN_CHOPEN */ #define _CSEN_CTRL_CHOPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ #define _CSEN_CTRL_CHOPEN_DISABLE 0x00000000UL /**< Mode DISABLE for CSEN_CTRL */ #define _CSEN_CTRL_CHOPEN_ENABLE 0x00000001UL /**< Mode ENABLE for CSEN_CTRL */ #define CSEN_CTRL_CHOPEN_DEFAULT (_CSEN_CTRL_CHOPEN_DEFAULT << 22) /**< Shifted mode DEFAULT for CSEN_CTRL */ #define CSEN_CTRL_CHOPEN_DISABLE (_CSEN_CTRL_CHOPEN_DISABLE << 22) /**< Shifted mode DISABLE for CSEN_CTRL */ #define CSEN_CTRL_CHOPEN_ENABLE (_CSEN_CTRL_CHOPEN_ENABLE << 22) /**< Shifted mode ENABLE for CSEN_CTRL */ #define CSEN_CTRL_AUTOGND (0x1UL << 23) /**< CSEN Automatic Ground Enable */ #define _CSEN_CTRL_AUTOGND_SHIFT 23 /**< Shift value for CSEN_AUTOGND */ #define _CSEN_CTRL_AUTOGND_MASK 0x800000UL /**< Bit mask for CSEN_AUTOGND */ #define _CSEN_CTRL_AUTOGND_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ #define _CSEN_CTRL_AUTOGND_DISABLE 0x00000000UL /**< Mode DISABLE for CSEN_CTRL */ #define _CSEN_CTRL_AUTOGND_ENABLE 0x00000001UL /**< Mode ENABLE for CSEN_CTRL */ #define CSEN_CTRL_AUTOGND_DEFAULT (_CSEN_CTRL_AUTOGND_DEFAULT << 23) /**< Shifted mode DEFAULT for CSEN_CTRL */ #define CSEN_CTRL_AUTOGND_DISABLE (_CSEN_CTRL_AUTOGND_DISABLE << 23) /**< Shifted mode DISABLE for CSEN_CTRL */ #define CSEN_CTRL_AUTOGND_ENABLE (_CSEN_CTRL_AUTOGND_ENABLE << 23) /**< Shifted mode ENABLE for CSEN_CTRL */ #define CSEN_CTRL_MXUC (0x1UL << 24) /**< CSEN Mux Disconnect */ #define _CSEN_CTRL_MXUC_SHIFT 24 /**< Shift value for CSEN_MXUC */ #define _CSEN_CTRL_MXUC_MASK 0x1000000UL /**< Bit mask for CSEN_MXUC */ #define _CSEN_CTRL_MXUC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ #define _CSEN_CTRL_MXUC_CONN 0x00000000UL /**< Mode CONN for CSEN_CTRL */ #define _CSEN_CTRL_MXUC_UNC 0x00000001UL /**< Mode UNC for CSEN_CTRL */ #define CSEN_CTRL_MXUC_DEFAULT (_CSEN_CTRL_MXUC_DEFAULT << 24) /**< Shifted mode DEFAULT for CSEN_CTRL */ #define CSEN_CTRL_MXUC_CONN (_CSEN_CTRL_MXUC_CONN << 24) /**< Shifted mode CONN for CSEN_CTRL */ #define CSEN_CTRL_MXUC_UNC (_CSEN_CTRL_MXUC_UNC << 24) /**< Shifted mode UNC for CSEN_CTRL */ #define CSEN_CTRL_EMACMPEN (0x1UL << 25) /**< Greater and Less Than Comparison Using the Exponential Moving Average (EMA) is Enabled */ #define _CSEN_CTRL_EMACMPEN_SHIFT 25 /**< Shift value for CSEN_EMACMPEN */ #define _CSEN_CTRL_EMACMPEN_MASK 0x2000000UL /**< Bit mask for CSEN_EMACMPEN */ #define _CSEN_CTRL_EMACMPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ #define CSEN_CTRL_EMACMPEN_DEFAULT (_CSEN_CTRL_EMACMPEN_DEFAULT << 25) /**< Shifted mode DEFAULT for CSEN_CTRL */ #define CSEN_CTRL_WARMUPMODE (0x1UL << 26) /**< Select Warmup Mode for CSEN */ #define _CSEN_CTRL_WARMUPMODE_SHIFT 26 /**< Shift value for CSEN_WARMUPMODE */ #define _CSEN_CTRL_WARMUPMODE_MASK 0x4000000UL /**< Bit mask for CSEN_WARMUPMODE */ #define _CSEN_CTRL_WARMUPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ #define _CSEN_CTRL_WARMUPMODE_NORMAL 0x00000000UL /**< Mode NORMAL for CSEN_CTRL */ #define _CSEN_CTRL_WARMUPMODE_KEEPCSENWARM 0x00000001UL /**< Mode KEEPCSENWARM for CSEN_CTRL */ #define CSEN_CTRL_WARMUPMODE_DEFAULT (_CSEN_CTRL_WARMUPMODE_DEFAULT << 26) /**< Shifted mode DEFAULT for CSEN_CTRL */ #define CSEN_CTRL_WARMUPMODE_NORMAL (_CSEN_CTRL_WARMUPMODE_NORMAL << 26) /**< Shifted mode NORMAL for CSEN_CTRL */ #define CSEN_CTRL_WARMUPMODE_KEEPCSENWARM (_CSEN_CTRL_WARMUPMODE_KEEPCSENWARM << 26) /**< Shifted mode KEEPCSENWARM for CSEN_CTRL */ #define CSEN_CTRL_LOCALSENS (0x1UL << 27) /**< Local Sensing Enable */ #define _CSEN_CTRL_LOCALSENS_SHIFT 27 /**< Shift value for CSEN_LOCALSENS */ #define _CSEN_CTRL_LOCALSENS_MASK 0x8000000UL /**< Bit mask for CSEN_LOCALSENS */ #define _CSEN_CTRL_LOCALSENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ #define CSEN_CTRL_LOCALSENS_DEFAULT (_CSEN_CTRL_LOCALSENS_DEFAULT << 27) /**< Shifted mode DEFAULT for CSEN_CTRL */ #define CSEN_CTRL_CPACCURACY (0x1UL << 28) /**< Charge Pump Accuracy */ #define _CSEN_CTRL_CPACCURACY_SHIFT 28 /**< Shift value for CSEN_CPACCURACY */ #define _CSEN_CTRL_CPACCURACY_MASK 0x10000000UL /**< Bit mask for CSEN_CPACCURACY */ #define _CSEN_CTRL_CPACCURACY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ #define _CSEN_CTRL_CPACCURACY_LO 0x00000000UL /**< Mode LO for CSEN_CTRL */ #define _CSEN_CTRL_CPACCURACY_HI 0x00000001UL /**< Mode HI for CSEN_CTRL */ #define CSEN_CTRL_CPACCURACY_DEFAULT (_CSEN_CTRL_CPACCURACY_DEFAULT << 28) /**< Shifted mode DEFAULT for CSEN_CTRL */ #define CSEN_CTRL_CPACCURACY_LO (_CSEN_CTRL_CPACCURACY_LO << 28) /**< Shifted mode LO for CSEN_CTRL */ #define CSEN_CTRL_CPACCURACY_HI (_CSEN_CTRL_CPACCURACY_HI << 28) /**< Shifted mode HI for CSEN_CTRL */ /* Bit fields for CSEN TIMCTRL */ #define _CSEN_TIMCTRL_RESETVALUE 0x00000000UL /**< Default value for CSEN_TIMCTRL */ #define _CSEN_TIMCTRL_MASK 0x0003FF07UL /**< Mask for CSEN_TIMCTRL */ #define _CSEN_TIMCTRL_PCPRESC_SHIFT 0 /**< Shift value for CSEN_PCPRESC */ #define _CSEN_TIMCTRL_PCPRESC_MASK 0x7UL /**< Bit mask for CSEN_PCPRESC */ #define _CSEN_TIMCTRL_PCPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_TIMCTRL */ #define _CSEN_TIMCTRL_PCPRESC_DIV1 0x00000000UL /**< Mode DIV1 for CSEN_TIMCTRL */ #define _CSEN_TIMCTRL_PCPRESC_DIV2 0x00000001UL /**< Mode DIV2 for CSEN_TIMCTRL */ #define _CSEN_TIMCTRL_PCPRESC_DIV4 0x00000002UL /**< Mode DIV4 for CSEN_TIMCTRL */ #define _CSEN_TIMCTRL_PCPRESC_DIV8 0x00000003UL /**< Mode DIV8 for CSEN_TIMCTRL */ #define _CSEN_TIMCTRL_PCPRESC_DIV16 0x00000004UL /**< Mode DIV16 for CSEN_TIMCTRL */ #define _CSEN_TIMCTRL_PCPRESC_DIV32 0x00000005UL /**< Mode DIV32 for CSEN_TIMCTRL */ #define _CSEN_TIMCTRL_PCPRESC_DIV64 0x00000006UL /**< Mode DIV64 for CSEN_TIMCTRL */ #define _CSEN_TIMCTRL_PCPRESC_DIV128 0x00000007UL /**< Mode DIV128 for CSEN_TIMCTRL */ #define CSEN_TIMCTRL_PCPRESC_DEFAULT (_CSEN_TIMCTRL_PCPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_TIMCTRL */ #define CSEN_TIMCTRL_PCPRESC_DIV1 (_CSEN_TIMCTRL_PCPRESC_DIV1 << 0) /**< Shifted mode DIV1 for CSEN_TIMCTRL */ #define CSEN_TIMCTRL_PCPRESC_DIV2 (_CSEN_TIMCTRL_PCPRESC_DIV2 << 0) /**< Shifted mode DIV2 for CSEN_TIMCTRL */ #define CSEN_TIMCTRL_PCPRESC_DIV4 (_CSEN_TIMCTRL_PCPRESC_DIV4 << 0) /**< Shifted mode DIV4 for CSEN_TIMCTRL */ #define CSEN_TIMCTRL_PCPRESC_DIV8 (_CSEN_TIMCTRL_PCPRESC_DIV8 << 0) /**< Shifted mode DIV8 for CSEN_TIMCTRL */ #define CSEN_TIMCTRL_PCPRESC_DIV16 (_CSEN_TIMCTRL_PCPRESC_DIV16 << 0) /**< Shifted mode DIV16 for CSEN_TIMCTRL */ #define CSEN_TIMCTRL_PCPRESC_DIV32 (_CSEN_TIMCTRL_PCPRESC_DIV32 << 0) /**< Shifted mode DIV32 for CSEN_TIMCTRL */ #define CSEN_TIMCTRL_PCPRESC_DIV64 (_CSEN_TIMCTRL_PCPRESC_DIV64 << 0) /**< Shifted mode DIV64 for CSEN_TIMCTRL */ #define CSEN_TIMCTRL_PCPRESC_DIV128 (_CSEN_TIMCTRL_PCPRESC_DIV128 << 0) /**< Shifted mode DIV128 for CSEN_TIMCTRL */ #define _CSEN_TIMCTRL_PCTOP_SHIFT 8 /**< Shift value for CSEN_PCTOP */ #define _CSEN_TIMCTRL_PCTOP_MASK 0xFF00UL /**< Bit mask for CSEN_PCTOP */ #define _CSEN_TIMCTRL_PCTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_TIMCTRL */ #define CSEN_TIMCTRL_PCTOP_DEFAULT (_CSEN_TIMCTRL_PCTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for CSEN_TIMCTRL */ #define _CSEN_TIMCTRL_WARMUPCNT_SHIFT 16 /**< Shift value for CSEN_WARMUPCNT */ #define _CSEN_TIMCTRL_WARMUPCNT_MASK 0x30000UL /**< Bit mask for CSEN_WARMUPCNT */ #define _CSEN_TIMCTRL_WARMUPCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_TIMCTRL */ #define CSEN_TIMCTRL_WARMUPCNT_DEFAULT (_CSEN_TIMCTRL_WARMUPCNT_DEFAULT << 16) /**< Shifted mode DEFAULT for CSEN_TIMCTRL */ /* Bit fields for CSEN CMD */ #define _CSEN_CMD_RESETVALUE 0x00000000UL /**< Default value for CSEN_CMD */ #define _CSEN_CMD_MASK 0x00000001UL /**< Mask for CSEN_CMD */ #define CSEN_CMD_START (0x1UL << 0) /**< Start Software-Triggered Conversions */ #define _CSEN_CMD_START_SHIFT 0 /**< Shift value for CSEN_START */ #define _CSEN_CMD_START_MASK 0x1UL /**< Bit mask for CSEN_START */ #define _CSEN_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CMD */ #define CSEN_CMD_START_DEFAULT (_CSEN_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_CMD */ /* Bit fields for CSEN STATUS */ #define _CSEN_STATUS_RESETVALUE 0x00000000UL /**< Default value for CSEN_STATUS */ #define _CSEN_STATUS_MASK 0x00000001UL /**< Mask for CSEN_STATUS */ #define CSEN_STATUS_CSENBUSY (0x1UL << 0) /**< Busy Flag */ #define _CSEN_STATUS_CSENBUSY_SHIFT 0 /**< Shift value for CSEN_CSENBUSY */ #define _CSEN_STATUS_CSENBUSY_MASK 0x1UL /**< Bit mask for CSEN_CSENBUSY */ #define _CSEN_STATUS_CSENBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_STATUS */ #define _CSEN_STATUS_CSENBUSY_IDLE 0x00000000UL /**< Mode IDLE for CSEN_STATUS */ #define _CSEN_STATUS_CSENBUSY_BUSY 0x00000001UL /**< Mode BUSY for CSEN_STATUS */ #define CSEN_STATUS_CSENBUSY_DEFAULT (_CSEN_STATUS_CSENBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_STATUS */ #define CSEN_STATUS_CSENBUSY_IDLE (_CSEN_STATUS_CSENBUSY_IDLE << 0) /**< Shifted mode IDLE for CSEN_STATUS */ #define CSEN_STATUS_CSENBUSY_BUSY (_CSEN_STATUS_CSENBUSY_BUSY << 0) /**< Shifted mode BUSY for CSEN_STATUS */ /* Bit fields for CSEN PRSSEL */ #define _CSEN_PRSSEL_RESETVALUE 0x00000000UL /**< Default value for CSEN_PRSSEL */ #define _CSEN_PRSSEL_MASK 0x0000000FUL /**< Mask for CSEN_PRSSEL */ #define _CSEN_PRSSEL_PRSSEL_SHIFT 0 /**< Shift value for CSEN_PRSSEL */ #define _CSEN_PRSSEL_PRSSEL_MASK 0xFUL /**< Bit mask for CSEN_PRSSEL */ #define _CSEN_PRSSEL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_PRSSEL */ #define _CSEN_PRSSEL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for CSEN_PRSSEL */ #define _CSEN_PRSSEL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for CSEN_PRSSEL */ #define _CSEN_PRSSEL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for CSEN_PRSSEL */ #define _CSEN_PRSSEL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for CSEN_PRSSEL */ #define _CSEN_PRSSEL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for CSEN_PRSSEL */ #define _CSEN_PRSSEL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for CSEN_PRSSEL */ #define _CSEN_PRSSEL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for CSEN_PRSSEL */ #define _CSEN_PRSSEL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for CSEN_PRSSEL */ #define _CSEN_PRSSEL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for CSEN_PRSSEL */ #define _CSEN_PRSSEL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for CSEN_PRSSEL */ #define _CSEN_PRSSEL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for CSEN_PRSSEL */ #define _CSEN_PRSSEL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for CSEN_PRSSEL */ #define CSEN_PRSSEL_PRSSEL_DEFAULT (_CSEN_PRSSEL_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_PRSSEL */ #define CSEN_PRSSEL_PRSSEL_PRSCH0 (_CSEN_PRSSEL_PRSSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for CSEN_PRSSEL */ #define CSEN_PRSSEL_PRSSEL_PRSCH1 (_CSEN_PRSSEL_PRSSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for CSEN_PRSSEL */ #define CSEN_PRSSEL_PRSSEL_PRSCH2 (_CSEN_PRSSEL_PRSSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for CSEN_PRSSEL */ #define CSEN_PRSSEL_PRSSEL_PRSCH3 (_CSEN_PRSSEL_PRSSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for CSEN_PRSSEL */ #define CSEN_PRSSEL_PRSSEL_PRSCH4 (_CSEN_PRSSEL_PRSSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for CSEN_PRSSEL */ #define CSEN_PRSSEL_PRSSEL_PRSCH5 (_CSEN_PRSSEL_PRSSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for CSEN_PRSSEL */ #define CSEN_PRSSEL_PRSSEL_PRSCH6 (_CSEN_PRSSEL_PRSSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for CSEN_PRSSEL */ #define CSEN_PRSSEL_PRSSEL_PRSCH7 (_CSEN_PRSSEL_PRSSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for CSEN_PRSSEL */ #define CSEN_PRSSEL_PRSSEL_PRSCH8 (_CSEN_PRSSEL_PRSSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for CSEN_PRSSEL */ #define CSEN_PRSSEL_PRSSEL_PRSCH9 (_CSEN_PRSSEL_PRSSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for CSEN_PRSSEL */ #define CSEN_PRSSEL_PRSSEL_PRSCH10 (_CSEN_PRSSEL_PRSSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for CSEN_PRSSEL */ #define CSEN_PRSSEL_PRSSEL_PRSCH11 (_CSEN_PRSSEL_PRSSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for CSEN_PRSSEL */ /* Bit fields for CSEN DATA */ #define _CSEN_DATA_RESETVALUE 0x00000000UL /**< Default value for CSEN_DATA */ #define _CSEN_DATA_MASK 0xFFFFFFFFUL /**< Mask for CSEN_DATA */ #define _CSEN_DATA_DATA_SHIFT 0 /**< Shift value for CSEN_DATA */ #define _CSEN_DATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for CSEN_DATA */ #define _CSEN_DATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_DATA */ #define CSEN_DATA_DATA_DEFAULT (_CSEN_DATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_DATA */ /* Bit fields for CSEN SCANMASK0 */ #define _CSEN_SCANMASK0_RESETVALUE 0x00000000UL /**< Default value for CSEN_SCANMASK0 */ #define _CSEN_SCANMASK0_MASK 0xFFFFFFFFUL /**< Mask for CSEN_SCANMASK0 */ #define _CSEN_SCANMASK0_SCANINPUTEN_SHIFT 0 /**< Shift value for CSEN_SCANINPUTEN */ #define _CSEN_SCANMASK0_SCANINPUTEN_MASK 0xFFFFFFFFUL /**< Bit mask for CSEN_SCANINPUTEN */ #define _CSEN_SCANMASK0_SCANINPUTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_SCANMASK0 */ #define CSEN_SCANMASK0_SCANINPUTEN_DEFAULT (_CSEN_SCANMASK0_SCANINPUTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_SCANMASK0 */ /* Bit fields for CSEN SCANINPUTSEL0 */ #define _CSEN_SCANINPUTSEL0_RESETVALUE 0x00000000UL /**< Default value for CSEN_SCANINPUTSEL0 */ #define _CSEN_SCANINPUTSEL0_MASK 0x0F0F0F0FUL /**< Mask for CSEN_SCANINPUTSEL0 */ #define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_SHIFT 0 /**< Shift value for CSEN_INPUT0TO7SEL */ #define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_MASK 0xFUL /**< Bit mask for CSEN_INPUT0TO7SEL */ #define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_SCANINPUTSEL0 */ #define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH0TO7 0x00000004UL /**< Mode APORT1CH0TO7 for CSEN_SCANINPUTSEL0 */ #define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH8TO15 0x00000005UL /**< Mode APORT1CH8TO15 for CSEN_SCANINPUTSEL0 */ #define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH16TO23 0x00000006UL /**< Mode APORT1CH16TO23 for CSEN_SCANINPUTSEL0 */ #define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH24TO31 0x00000007UL /**< Mode APORT1CH24TO31 for CSEN_SCANINPUTSEL0 */ #define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH0TO7 0x0000000CUL /**< Mode APORT3CH0TO7 for CSEN_SCANINPUTSEL0 */ #define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH8TO15 0x0000000DUL /**< Mode APORT3CH8TO15 for CSEN_SCANINPUTSEL0 */ #define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH16TO23 0x0000000EUL /**< Mode APORT3CH16TO23 for CSEN_SCANINPUTSEL0 */ #define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH24TO31 0x0000000FUL /**< Mode APORT3CH24TO31 for CSEN_SCANINPUTSEL0 */ #define CSEN_SCANINPUTSEL0_INPUT0TO7SEL_DEFAULT (_CSEN_SCANINPUTSEL0_INPUT0TO7SEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_SCANINPUTSEL0 */ #define CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH0TO7 (_CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH0TO7 << 0) /**< Shifted mode APORT1CH0TO7 for CSEN_SCANINPUTSEL0 */ #define CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH8TO15 (_CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH8TO15 << 0) /**< Shifted mode APORT1CH8TO15 for CSEN_SCANINPUTSEL0 */ #define CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH16TO23 (_CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH16TO23 << 0) /**< Shifted mode APORT1CH16TO23 for CSEN_SCANINPUTSEL0 */ #define CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH24TO31 (_CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH24TO31 << 0) /**< Shifted mode APORT1CH24TO31 for CSEN_SCANINPUTSEL0 */ #define CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH0TO7 (_CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH0TO7 << 0) /**< Shifted mode APORT3CH0TO7 for CSEN_SCANINPUTSEL0 */ #define CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH8TO15 (_CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH8TO15 << 0) /**< Shifted mode APORT3CH8TO15 for CSEN_SCANINPUTSEL0 */ #define CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH16TO23 (_CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH16TO23 << 0) /**< Shifted mode APORT3CH16TO23 for CSEN_SCANINPUTSEL0 */ #define CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH24TO31 (_CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH24TO31 << 0) /**< Shifted mode APORT3CH24TO31 for CSEN_SCANINPUTSEL0 */ #define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_SHIFT 8 /**< Shift value for CSEN_INPUT8TO15SEL */ #define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_MASK 0xF00UL /**< Bit mask for CSEN_INPUT8TO15SEL */ #define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_SCANINPUTSEL0 */ #define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH0TO7 0x00000004UL /**< Mode APORT1CH0TO7 for CSEN_SCANINPUTSEL0 */ #define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH8TO15 0x00000005UL /**< Mode APORT1CH8TO15 for CSEN_SCANINPUTSEL0 */ #define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH16TO23 0x00000006UL /**< Mode APORT1CH16TO23 for CSEN_SCANINPUTSEL0 */ #define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH24TO31 0x00000007UL /**< Mode APORT1CH24TO31 for CSEN_SCANINPUTSEL0 */ #define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH0TO7 0x0000000CUL /**< Mode APORT3CH0TO7 for CSEN_SCANINPUTSEL0 */ #define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH8TO15 0x0000000DUL /**< Mode APORT3CH8TO15 for CSEN_SCANINPUTSEL0 */ #define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH16TO23 0x0000000EUL /**< Mode APORT3CH16TO23 for CSEN_SCANINPUTSEL0 */ #define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH24TO31 0x0000000FUL /**< Mode APORT3CH24TO31 for CSEN_SCANINPUTSEL0 */ #define CSEN_SCANINPUTSEL0_INPUT8TO15SEL_DEFAULT (_CSEN_SCANINPUTSEL0_INPUT8TO15SEL_DEFAULT << 8) /**< Shifted mode DEFAULT for CSEN_SCANINPUTSEL0 */ #define CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH0TO7 (_CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH0TO7 << 8) /**< Shifted mode APORT1CH0TO7 for CSEN_SCANINPUTSEL0 */ #define CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH8TO15 (_CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH8TO15 << 8) /**< Shifted mode APORT1CH8TO15 for CSEN_SCANINPUTSEL0 */ #define CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH16TO23 (_CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH16TO23 << 8) /**< Shifted mode APORT1CH16TO23 for CSEN_SCANINPUTSEL0 */ #define CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH24TO31 (_CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH24TO31 << 8) /**< Shifted mode APORT1CH24TO31 for CSEN_SCANINPUTSEL0 */ #define CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH0TO7 (_CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH0TO7 << 8) /**< Shifted mode APORT3CH0TO7 for CSEN_SCANINPUTSEL0 */ #define CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH8TO15 (_CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH8TO15 << 8) /**< Shifted mode APORT3CH8TO15 for CSEN_SCANINPUTSEL0 */ #define CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH16TO23 (_CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH16TO23 << 8) /**< Shifted mode APORT3CH16TO23 for CSEN_SCANINPUTSEL0 */ #define CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH24TO31 (_CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH24TO31 << 8) /**< Shifted mode APORT3CH24TO31 for CSEN_SCANINPUTSEL0 */ #define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_SHIFT 16 /**< Shift value for CSEN_INPUT16TO23SEL */ #define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_MASK 0xF0000UL /**< Bit mask for CSEN_INPUT16TO23SEL */ #define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_SCANINPUTSEL0 */ #define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH0TO7 0x00000004UL /**< Mode APORT1CH0TO7 for CSEN_SCANINPUTSEL0 */ #define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH8TO15 0x00000005UL /**< Mode APORT1CH8TO15 for CSEN_SCANINPUTSEL0 */ #define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH16TO23 0x00000006UL /**< Mode APORT1CH16TO23 for CSEN_SCANINPUTSEL0 */ #define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH24TO31 0x00000007UL /**< Mode APORT1CH24TO31 for CSEN_SCANINPUTSEL0 */ #define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH0TO7 0x0000000CUL /**< Mode APORT3CH0TO7 for CSEN_SCANINPUTSEL0 */ #define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH8TO15 0x0000000DUL /**< Mode APORT3CH8TO15 for CSEN_SCANINPUTSEL0 */ #define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH16TO23 0x0000000EUL /**< Mode APORT3CH16TO23 for CSEN_SCANINPUTSEL0 */ #define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH24TO31 0x0000000FUL /**< Mode APORT3CH24TO31 for CSEN_SCANINPUTSEL0 */ #define CSEN_SCANINPUTSEL0_INPUT16TO23SEL_DEFAULT (_CSEN_SCANINPUTSEL0_INPUT16TO23SEL_DEFAULT << 16) /**< Shifted mode DEFAULT for CSEN_SCANINPUTSEL0 */ #define CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH0TO7 (_CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH0TO7 << 16) /**< Shifted mode APORT1CH0TO7 for CSEN_SCANINPUTSEL0 */ #define CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH8TO15 (_CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH8TO15 << 16) /**< Shifted mode APORT1CH8TO15 for CSEN_SCANINPUTSEL0 */ #define CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH16TO23 (_CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH16TO23 << 16) /**< Shifted mode APORT1CH16TO23 for CSEN_SCANINPUTSEL0 */ #define CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH24TO31 (_CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH24TO31 << 16) /**< Shifted mode APORT1CH24TO31 for CSEN_SCANINPUTSEL0 */ #define CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH0TO7 (_CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH0TO7 << 16) /**< Shifted mode APORT3CH0TO7 for CSEN_SCANINPUTSEL0 */ #define CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH8TO15 (_CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH8TO15 << 16) /**< Shifted mode APORT3CH8TO15 for CSEN_SCANINPUTSEL0 */ #define CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH16TO23 (_CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH16TO23 << 16) /**< Shifted mode APORT3CH16TO23 for CSEN_SCANINPUTSEL0 */ #define CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH24TO31 (_CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH24TO31 << 16) /**< Shifted mode APORT3CH24TO31 for CSEN_SCANINPUTSEL0 */ #define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_SHIFT 24 /**< Shift value for CSEN_INPUT24TO31SEL */ #define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_MASK 0xF000000UL /**< Bit mask for CSEN_INPUT24TO31SEL */ #define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_SCANINPUTSEL0 */ #define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH0TO7 0x00000004UL /**< Mode APORT1CH0TO7 for CSEN_SCANINPUTSEL0 */ #define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH8TO15 0x00000005UL /**< Mode APORT1CH8TO15 for CSEN_SCANINPUTSEL0 */ #define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH16TO23 0x00000006UL /**< Mode APORT1CH16TO23 for CSEN_SCANINPUTSEL0 */ #define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH24TO31 0x00000007UL /**< Mode APORT1CH24TO31 for CSEN_SCANINPUTSEL0 */ #define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH0TO7 0x0000000CUL /**< Mode APORT3CH0TO7 for CSEN_SCANINPUTSEL0 */ #define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH8TO15 0x0000000DUL /**< Mode APORT3CH8TO15 for CSEN_SCANINPUTSEL0 */ #define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH16TO23 0x0000000EUL /**< Mode APORT3CH16TO23 for CSEN_SCANINPUTSEL0 */ #define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH24TO31 0x0000000FUL /**< Mode APORT3CH24TO31 for CSEN_SCANINPUTSEL0 */ #define CSEN_SCANINPUTSEL0_INPUT24TO31SEL_DEFAULT (_CSEN_SCANINPUTSEL0_INPUT24TO31SEL_DEFAULT << 24) /**< Shifted mode DEFAULT for CSEN_SCANINPUTSEL0 */ #define CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH0TO7 (_CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH0TO7 << 24) /**< Shifted mode APORT1CH0TO7 for CSEN_SCANINPUTSEL0 */ #define CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH8TO15 (_CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH8TO15 << 24) /**< Shifted mode APORT1CH8TO15 for CSEN_SCANINPUTSEL0 */ #define CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH16TO23 (_CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH16TO23 << 24) /**< Shifted mode APORT1CH16TO23 for CSEN_SCANINPUTSEL0 */ #define CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH24TO31 (_CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH24TO31 << 24) /**< Shifted mode APORT1CH24TO31 for CSEN_SCANINPUTSEL0 */ #define CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH0TO7 (_CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH0TO7 << 24) /**< Shifted mode APORT3CH0TO7 for CSEN_SCANINPUTSEL0 */ #define CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH8TO15 (_CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH8TO15 << 24) /**< Shifted mode APORT3CH8TO15 for CSEN_SCANINPUTSEL0 */ #define CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH16TO23 (_CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH16TO23 << 24) /**< Shifted mode APORT3CH16TO23 for CSEN_SCANINPUTSEL0 */ #define CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH24TO31 (_CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH24TO31 << 24) /**< Shifted mode APORT3CH24TO31 for CSEN_SCANINPUTSEL0 */ /* Bit fields for CSEN SCANMASK1 */ #define _CSEN_SCANMASK1_RESETVALUE 0x00000000UL /**< Default value for CSEN_SCANMASK1 */ #define _CSEN_SCANMASK1_MASK 0xFFFFFFFFUL /**< Mask for CSEN_SCANMASK1 */ #define _CSEN_SCANMASK1_SCANINPUTEN_SHIFT 0 /**< Shift value for CSEN_SCANINPUTEN */ #define _CSEN_SCANMASK1_SCANINPUTEN_MASK 0xFFFFFFFFUL /**< Bit mask for CSEN_SCANINPUTEN */ #define _CSEN_SCANMASK1_SCANINPUTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_SCANMASK1 */ #define CSEN_SCANMASK1_SCANINPUTEN_DEFAULT (_CSEN_SCANMASK1_SCANINPUTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_SCANMASK1 */ /* Bit fields for CSEN SCANINPUTSEL1 */ #define _CSEN_SCANINPUTSEL1_RESETVALUE 0x00000000UL /**< Default value for CSEN_SCANINPUTSEL1 */ #define _CSEN_SCANINPUTSEL1_MASK 0x0F0F0F0FUL /**< Mask for CSEN_SCANINPUTSEL1 */ #define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_SHIFT 0 /**< Shift value for CSEN_INPUT32TO39SEL */ #define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_MASK 0xFUL /**< Bit mask for CSEN_INPUT32TO39SEL */ #define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_SCANINPUTSEL1 */ #define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH0TO7 0x00000004UL /**< Mode APORT1CH0TO7 for CSEN_SCANINPUTSEL1 */ #define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH8TO15 0x00000005UL /**< Mode APORT1CH8TO15 for CSEN_SCANINPUTSEL1 */ #define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH16TO23 0x00000006UL /**< Mode APORT1CH16TO23 for CSEN_SCANINPUTSEL1 */ #define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH24TO31 0x00000007UL /**< Mode APORT1CH24TO31 for CSEN_SCANINPUTSEL1 */ #define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH0TO7 0x0000000CUL /**< Mode APORT3CH0TO7 for CSEN_SCANINPUTSEL1 */ #define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH8TO15 0x0000000DUL /**< Mode APORT3CH8TO15 for CSEN_SCANINPUTSEL1 */ #define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH16TO23 0x0000000EUL /**< Mode APORT3CH16TO23 for CSEN_SCANINPUTSEL1 */ #define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH24TO31 0x0000000FUL /**< Mode APORT3CH24TO31 for CSEN_SCANINPUTSEL1 */ #define CSEN_SCANINPUTSEL1_INPUT32TO39SEL_DEFAULT (_CSEN_SCANINPUTSEL1_INPUT32TO39SEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_SCANINPUTSEL1 */ #define CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH0TO7 (_CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH0TO7 << 0) /**< Shifted mode APORT1CH0TO7 for CSEN_SCANINPUTSEL1 */ #define CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH8TO15 (_CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH8TO15 << 0) /**< Shifted mode APORT1CH8TO15 for CSEN_SCANINPUTSEL1 */ #define CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH16TO23 (_CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH16TO23 << 0) /**< Shifted mode APORT1CH16TO23 for CSEN_SCANINPUTSEL1 */ #define CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH24TO31 (_CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH24TO31 << 0) /**< Shifted mode APORT1CH24TO31 for CSEN_SCANINPUTSEL1 */ #define CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH0TO7 (_CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH0TO7 << 0) /**< Shifted mode APORT3CH0TO7 for CSEN_SCANINPUTSEL1 */ #define CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH8TO15 (_CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH8TO15 << 0) /**< Shifted mode APORT3CH8TO15 for CSEN_SCANINPUTSEL1 */ #define CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH16TO23 (_CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH16TO23 << 0) /**< Shifted mode APORT3CH16TO23 for CSEN_SCANINPUTSEL1 */ #define CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH24TO31 (_CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH24TO31 << 0) /**< Shifted mode APORT3CH24TO31 for CSEN_SCANINPUTSEL1 */ #define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_SHIFT 8 /**< Shift value for CSEN_INPUT40TO47SEL */ #define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_MASK 0xF00UL /**< Bit mask for CSEN_INPUT40TO47SEL */ #define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_SCANINPUTSEL1 */ #define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH0TO7 0x00000004UL /**< Mode APORT1CH0TO7 for CSEN_SCANINPUTSEL1 */ #define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH8TO15 0x00000005UL /**< Mode APORT1CH8TO15 for CSEN_SCANINPUTSEL1 */ #define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH16TO23 0x00000006UL /**< Mode APORT1CH16TO23 for CSEN_SCANINPUTSEL1 */ #define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH24TO31 0x00000007UL /**< Mode APORT1CH24TO31 for CSEN_SCANINPUTSEL1 */ #define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH0TO7 0x0000000CUL /**< Mode APORT3CH0TO7 for CSEN_SCANINPUTSEL1 */ #define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH8TO15 0x0000000DUL /**< Mode APORT3CH8TO15 for CSEN_SCANINPUTSEL1 */ #define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH16TO23 0x0000000EUL /**< Mode APORT3CH16TO23 for CSEN_SCANINPUTSEL1 */ #define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH24TO31 0x0000000FUL /**< Mode APORT3CH24TO31 for CSEN_SCANINPUTSEL1 */ #define CSEN_SCANINPUTSEL1_INPUT40TO47SEL_DEFAULT (_CSEN_SCANINPUTSEL1_INPUT40TO47SEL_DEFAULT << 8) /**< Shifted mode DEFAULT for CSEN_SCANINPUTSEL1 */ #define CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH0TO7 (_CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH0TO7 << 8) /**< Shifted mode APORT1CH0TO7 for CSEN_SCANINPUTSEL1 */ #define CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH8TO15 (_CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH8TO15 << 8) /**< Shifted mode APORT1CH8TO15 for CSEN_SCANINPUTSEL1 */ #define CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH16TO23 (_CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH16TO23 << 8) /**< Shifted mode APORT1CH16TO23 for CSEN_SCANINPUTSEL1 */ #define CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH24TO31 (_CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH24TO31 << 8) /**< Shifted mode APORT1CH24TO31 for CSEN_SCANINPUTSEL1 */ #define CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH0TO7 (_CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH0TO7 << 8) /**< Shifted mode APORT3CH0TO7 for CSEN_SCANINPUTSEL1 */ #define CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH8TO15 (_CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH8TO15 << 8) /**< Shifted mode APORT3CH8TO15 for CSEN_SCANINPUTSEL1 */ #define CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH16TO23 (_CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH16TO23 << 8) /**< Shifted mode APORT3CH16TO23 for CSEN_SCANINPUTSEL1 */ #define CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH24TO31 (_CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH24TO31 << 8) /**< Shifted mode APORT3CH24TO31 for CSEN_SCANINPUTSEL1 */ #define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_SHIFT 16 /**< Shift value for CSEN_INPUT48TO55SEL */ #define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_MASK 0xF0000UL /**< Bit mask for CSEN_INPUT48TO55SEL */ #define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_SCANINPUTSEL1 */ #define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH0TO7 0x00000004UL /**< Mode APORT1CH0TO7 for CSEN_SCANINPUTSEL1 */ #define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH8TO15 0x00000005UL /**< Mode APORT1CH8TO15 for CSEN_SCANINPUTSEL1 */ #define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH16TO23 0x00000006UL /**< Mode APORT1CH16TO23 for CSEN_SCANINPUTSEL1 */ #define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH24TO31 0x00000007UL /**< Mode APORT1CH24TO31 for CSEN_SCANINPUTSEL1 */ #define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH0TO7 0x0000000CUL /**< Mode APORT3CH0TO7 for CSEN_SCANINPUTSEL1 */ #define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH8TO15 0x0000000DUL /**< Mode APORT3CH8TO15 for CSEN_SCANINPUTSEL1 */ #define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH16TO23 0x0000000EUL /**< Mode APORT3CH16TO23 for CSEN_SCANINPUTSEL1 */ #define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH24TO31 0x0000000FUL /**< Mode APORT3CH24TO31 for CSEN_SCANINPUTSEL1 */ #define CSEN_SCANINPUTSEL1_INPUT48TO55SEL_DEFAULT (_CSEN_SCANINPUTSEL1_INPUT48TO55SEL_DEFAULT << 16) /**< Shifted mode DEFAULT for CSEN_SCANINPUTSEL1 */ #define CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH0TO7 (_CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH0TO7 << 16) /**< Shifted mode APORT1CH0TO7 for CSEN_SCANINPUTSEL1 */ #define CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH8TO15 (_CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH8TO15 << 16) /**< Shifted mode APORT1CH8TO15 for CSEN_SCANINPUTSEL1 */ #define CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH16TO23 (_CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH16TO23 << 16) /**< Shifted mode APORT1CH16TO23 for CSEN_SCANINPUTSEL1 */ #define CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH24TO31 (_CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH24TO31 << 16) /**< Shifted mode APORT1CH24TO31 for CSEN_SCANINPUTSEL1 */ #define CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH0TO7 (_CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH0TO7 << 16) /**< Shifted mode APORT3CH0TO7 for CSEN_SCANINPUTSEL1 */ #define CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH8TO15 (_CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH8TO15 << 16) /**< Shifted mode APORT3CH8TO15 for CSEN_SCANINPUTSEL1 */ #define CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH16TO23 (_CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH16TO23 << 16) /**< Shifted mode APORT3CH16TO23 for CSEN_SCANINPUTSEL1 */ #define CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH24TO31 (_CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH24TO31 << 16) /**< Shifted mode APORT3CH24TO31 for CSEN_SCANINPUTSEL1 */ #define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_SHIFT 24 /**< Shift value for CSEN_INPUT56TO63SEL */ #define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_MASK 0xF000000UL /**< Bit mask for CSEN_INPUT56TO63SEL */ #define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_SCANINPUTSEL1 */ #define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH0TO7 0x00000004UL /**< Mode APORT1CH0TO7 for CSEN_SCANINPUTSEL1 */ #define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH8TO15 0x00000005UL /**< Mode APORT1CH8TO15 for CSEN_SCANINPUTSEL1 */ #define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH16TO23 0x00000006UL /**< Mode APORT1CH16TO23 for CSEN_SCANINPUTSEL1 */ #define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH24TO31 0x00000007UL /**< Mode APORT1CH24TO31 for CSEN_SCANINPUTSEL1 */ #define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH0TO7 0x0000000CUL /**< Mode APORT3CH0TO7 for CSEN_SCANINPUTSEL1 */ #define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH8TO15 0x0000000DUL /**< Mode APORT3CH8TO15 for CSEN_SCANINPUTSEL1 */ #define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH16TO23 0x0000000EUL /**< Mode APORT3CH16TO23 for CSEN_SCANINPUTSEL1 */ #define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH24TO31 0x0000000FUL /**< Mode APORT3CH24TO31 for CSEN_SCANINPUTSEL1 */ #define CSEN_SCANINPUTSEL1_INPUT56TO63SEL_DEFAULT (_CSEN_SCANINPUTSEL1_INPUT56TO63SEL_DEFAULT << 24) /**< Shifted mode DEFAULT for CSEN_SCANINPUTSEL1 */ #define CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH0TO7 (_CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH0TO7 << 24) /**< Shifted mode APORT1CH0TO7 for CSEN_SCANINPUTSEL1 */ #define CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH8TO15 (_CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH8TO15 << 24) /**< Shifted mode APORT1CH8TO15 for CSEN_SCANINPUTSEL1 */ #define CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH16TO23 (_CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH16TO23 << 24) /**< Shifted mode APORT1CH16TO23 for CSEN_SCANINPUTSEL1 */ #define CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH24TO31 (_CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH24TO31 << 24) /**< Shifted mode APORT1CH24TO31 for CSEN_SCANINPUTSEL1 */ #define CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH0TO7 (_CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH0TO7 << 24) /**< Shifted mode APORT3CH0TO7 for CSEN_SCANINPUTSEL1 */ #define CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH8TO15 (_CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH8TO15 << 24) /**< Shifted mode APORT3CH8TO15 for CSEN_SCANINPUTSEL1 */ #define CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH16TO23 (_CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH16TO23 << 24) /**< Shifted mode APORT3CH16TO23 for CSEN_SCANINPUTSEL1 */ #define CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH24TO31 (_CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH24TO31 << 24) /**< Shifted mode APORT3CH24TO31 for CSEN_SCANINPUTSEL1 */ /* Bit fields for CSEN APORTREQ */ #define _CSEN_APORTREQ_RESETVALUE 0x00000000UL /**< Default value for CSEN_APORTREQ */ #define _CSEN_APORTREQ_MASK 0x000003FCUL /**< Mask for CSEN_APORTREQ */ #define CSEN_APORTREQ_APORT1XREQ (0x1UL << 2) /**< 1 If the Bus Connected to APORT2X is Requested */ #define _CSEN_APORTREQ_APORT1XREQ_SHIFT 2 /**< Shift value for CSEN_APORT1XREQ */ #define _CSEN_APORTREQ_APORT1XREQ_MASK 0x4UL /**< Bit mask for CSEN_APORT1XREQ */ #define _CSEN_APORTREQ_APORT1XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTREQ */ #define CSEN_APORTREQ_APORT1XREQ_DEFAULT (_CSEN_APORTREQ_APORT1XREQ_DEFAULT << 2) /**< Shifted mode DEFAULT for CSEN_APORTREQ */ #define CSEN_APORTREQ_APORT1YREQ (0x1UL << 3) /**< 1 If the Bus Connected to APORT1X is Requested */ #define _CSEN_APORTREQ_APORT1YREQ_SHIFT 3 /**< Shift value for CSEN_APORT1YREQ */ #define _CSEN_APORTREQ_APORT1YREQ_MASK 0x8UL /**< Bit mask for CSEN_APORT1YREQ */ #define _CSEN_APORTREQ_APORT1YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTREQ */ #define CSEN_APORTREQ_APORT1YREQ_DEFAULT (_CSEN_APORTREQ_APORT1YREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for CSEN_APORTREQ */ #define CSEN_APORTREQ_APORT2XREQ (0x1UL << 4) /**< 1 If the Bus Connected to APORT2X is Requested */ #define _CSEN_APORTREQ_APORT2XREQ_SHIFT 4 /**< Shift value for CSEN_APORT2XREQ */ #define _CSEN_APORTREQ_APORT2XREQ_MASK 0x10UL /**< Bit mask for CSEN_APORT2XREQ */ #define _CSEN_APORTREQ_APORT2XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTREQ */ #define CSEN_APORTREQ_APORT2XREQ_DEFAULT (_CSEN_APORTREQ_APORT2XREQ_DEFAULT << 4) /**< Shifted mode DEFAULT for CSEN_APORTREQ */ #define CSEN_APORTREQ_APORT2YREQ (0x1UL << 5) /**< 1 If the Bus Connected to APORT2Y is Requested */ #define _CSEN_APORTREQ_APORT2YREQ_SHIFT 5 /**< Shift value for CSEN_APORT2YREQ */ #define _CSEN_APORTREQ_APORT2YREQ_MASK 0x20UL /**< Bit mask for CSEN_APORT2YREQ */ #define _CSEN_APORTREQ_APORT2YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTREQ */ #define CSEN_APORTREQ_APORT2YREQ_DEFAULT (_CSEN_APORTREQ_APORT2YREQ_DEFAULT << 5) /**< Shifted mode DEFAULT for CSEN_APORTREQ */ #define CSEN_APORTREQ_APORT3XREQ (0x1UL << 6) /**< 1 If the Bus Connected to APORT3X is Requested */ #define _CSEN_APORTREQ_APORT3XREQ_SHIFT 6 /**< Shift value for CSEN_APORT3XREQ */ #define _CSEN_APORTREQ_APORT3XREQ_MASK 0x40UL /**< Bit mask for CSEN_APORT3XREQ */ #define _CSEN_APORTREQ_APORT3XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTREQ */ #define CSEN_APORTREQ_APORT3XREQ_DEFAULT (_CSEN_APORTREQ_APORT3XREQ_DEFAULT << 6) /**< Shifted mode DEFAULT for CSEN_APORTREQ */ #define CSEN_APORTREQ_APORT3YREQ (0x1UL << 7) /**< 1 If the Bus Connected to APORT3Y is Requested */ #define _CSEN_APORTREQ_APORT3YREQ_SHIFT 7 /**< Shift value for CSEN_APORT3YREQ */ #define _CSEN_APORTREQ_APORT3YREQ_MASK 0x80UL /**< Bit mask for CSEN_APORT3YREQ */ #define _CSEN_APORTREQ_APORT3YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTREQ */ #define CSEN_APORTREQ_APORT3YREQ_DEFAULT (_CSEN_APORTREQ_APORT3YREQ_DEFAULT << 7) /**< Shifted mode DEFAULT for CSEN_APORTREQ */ #define CSEN_APORTREQ_APORT4XREQ (0x1UL << 8) /**< 1 If the Bus Connected to APORT4X is Requested */ #define _CSEN_APORTREQ_APORT4XREQ_SHIFT 8 /**< Shift value for CSEN_APORT4XREQ */ #define _CSEN_APORTREQ_APORT4XREQ_MASK 0x100UL /**< Bit mask for CSEN_APORT4XREQ */ #define _CSEN_APORTREQ_APORT4XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTREQ */ #define CSEN_APORTREQ_APORT4XREQ_DEFAULT (_CSEN_APORTREQ_APORT4XREQ_DEFAULT << 8) /**< Shifted mode DEFAULT for CSEN_APORTREQ */ #define CSEN_APORTREQ_APORT4YREQ (0x1UL << 9) /**< 1 If the Bus Connected to APORT4Y is Requested */ #define _CSEN_APORTREQ_APORT4YREQ_SHIFT 9 /**< Shift value for CSEN_APORT4YREQ */ #define _CSEN_APORTREQ_APORT4YREQ_MASK 0x200UL /**< Bit mask for CSEN_APORT4YREQ */ #define _CSEN_APORTREQ_APORT4YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTREQ */ #define CSEN_APORTREQ_APORT4YREQ_DEFAULT (_CSEN_APORTREQ_APORT4YREQ_DEFAULT << 9) /**< Shifted mode DEFAULT for CSEN_APORTREQ */ /* Bit fields for CSEN APORTCONFLICT */ #define _CSEN_APORTCONFLICT_RESETVALUE 0x00000000UL /**< Default value for CSEN_APORTCONFLICT */ #define _CSEN_APORTCONFLICT_MASK 0x000003FCUL /**< Mask for CSEN_APORTCONFLICT */ #define CSEN_APORTCONFLICT_APORT1XCONFLICT (0x1UL << 2) /**< 1 If the Bus Connected to APORT1X is in Conflict With Another Peripheral */ #define _CSEN_APORTCONFLICT_APORT1XCONFLICT_SHIFT 2 /**< Shift value for CSEN_APORT1XCONFLICT */ #define _CSEN_APORTCONFLICT_APORT1XCONFLICT_MASK 0x4UL /**< Bit mask for CSEN_APORT1XCONFLICT */ #define _CSEN_APORTCONFLICT_APORT1XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTCONFLICT */ #define CSEN_APORTCONFLICT_APORT1XCONFLICT_DEFAULT (_CSEN_APORTCONFLICT_APORT1XCONFLICT_DEFAULT << 2) /**< Shifted mode DEFAULT for CSEN_APORTCONFLICT */ #define CSEN_APORTCONFLICT_APORT1YCONFLICT (0x1UL << 3) /**< 1 If the Bus Connected to APORT1Y is in Conflict With Another Peripheral */ #define _CSEN_APORTCONFLICT_APORT1YCONFLICT_SHIFT 3 /**< Shift value for CSEN_APORT1YCONFLICT */ #define _CSEN_APORTCONFLICT_APORT1YCONFLICT_MASK 0x8UL /**< Bit mask for CSEN_APORT1YCONFLICT */ #define _CSEN_APORTCONFLICT_APORT1YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTCONFLICT */ #define CSEN_APORTCONFLICT_APORT1YCONFLICT_DEFAULT (_CSEN_APORTCONFLICT_APORT1YCONFLICT_DEFAULT << 3) /**< Shifted mode DEFAULT for CSEN_APORTCONFLICT */ #define CSEN_APORTCONFLICT_APORT2XCONFLICT (0x1UL << 4) /**< 1 If the Bus Connected to APORT2X is in Conflict With Another Peripheral */ #define _CSEN_APORTCONFLICT_APORT2XCONFLICT_SHIFT 4 /**< Shift value for CSEN_APORT2XCONFLICT */ #define _CSEN_APORTCONFLICT_APORT2XCONFLICT_MASK 0x10UL /**< Bit mask for CSEN_APORT2XCONFLICT */ #define _CSEN_APORTCONFLICT_APORT2XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTCONFLICT */ #define CSEN_APORTCONFLICT_APORT2XCONFLICT_DEFAULT (_CSEN_APORTCONFLICT_APORT2XCONFLICT_DEFAULT << 4) /**< Shifted mode DEFAULT for CSEN_APORTCONFLICT */ #define CSEN_APORTCONFLICT_APORT2YCONFLICT (0x1UL << 5) /**< 1 If the Bus Connected to APORT2Y is in Conflict With Another Peripheral */ #define _CSEN_APORTCONFLICT_APORT2YCONFLICT_SHIFT 5 /**< Shift value for CSEN_APORT2YCONFLICT */ #define _CSEN_APORTCONFLICT_APORT2YCONFLICT_MASK 0x20UL /**< Bit mask for CSEN_APORT2YCONFLICT */ #define _CSEN_APORTCONFLICT_APORT2YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTCONFLICT */ #define CSEN_APORTCONFLICT_APORT2YCONFLICT_DEFAULT (_CSEN_APORTCONFLICT_APORT2YCONFLICT_DEFAULT << 5) /**< Shifted mode DEFAULT for CSEN_APORTCONFLICT */ #define CSEN_APORTCONFLICT_APORT3XCONFLICT (0x1UL << 6) /**< 1 If the Bus Connected to APORT3X is in Conflict With Another Peripheral */ #define _CSEN_APORTCONFLICT_APORT3XCONFLICT_SHIFT 6 /**< Shift value for CSEN_APORT3XCONFLICT */ #define _CSEN_APORTCONFLICT_APORT3XCONFLICT_MASK 0x40UL /**< Bit mask for CSEN_APORT3XCONFLICT */ #define _CSEN_APORTCONFLICT_APORT3XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTCONFLICT */ #define CSEN_APORTCONFLICT_APORT3XCONFLICT_DEFAULT (_CSEN_APORTCONFLICT_APORT3XCONFLICT_DEFAULT << 6) /**< Shifted mode DEFAULT for CSEN_APORTCONFLICT */ #define CSEN_APORTCONFLICT_APORT3YCONFLICT (0x1UL << 7) /**< 1 If the Bus Connected to APORT3Y is in Conflict With Another Peripheral */ #define _CSEN_APORTCONFLICT_APORT3YCONFLICT_SHIFT 7 /**< Shift value for CSEN_APORT3YCONFLICT */ #define _CSEN_APORTCONFLICT_APORT3YCONFLICT_MASK 0x80UL /**< Bit mask for CSEN_APORT3YCONFLICT */ #define _CSEN_APORTCONFLICT_APORT3YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTCONFLICT */ #define CSEN_APORTCONFLICT_APORT3YCONFLICT_DEFAULT (_CSEN_APORTCONFLICT_APORT3YCONFLICT_DEFAULT << 7) /**< Shifted mode DEFAULT for CSEN_APORTCONFLICT */ #define CSEN_APORTCONFLICT_APORT4XCONFLICT (0x1UL << 8) /**< 1 If the Bus Connected to APORT4X is in Conflict With Another Peripheral */ #define _CSEN_APORTCONFLICT_APORT4XCONFLICT_SHIFT 8 /**< Shift value for CSEN_APORT4XCONFLICT */ #define _CSEN_APORTCONFLICT_APORT4XCONFLICT_MASK 0x100UL /**< Bit mask for CSEN_APORT4XCONFLICT */ #define _CSEN_APORTCONFLICT_APORT4XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTCONFLICT */ #define CSEN_APORTCONFLICT_APORT4XCONFLICT_DEFAULT (_CSEN_APORTCONFLICT_APORT4XCONFLICT_DEFAULT << 8) /**< Shifted mode DEFAULT for CSEN_APORTCONFLICT */ #define CSEN_APORTCONFLICT_APORT4YCONFLICT (0x1UL << 9) /**< 1 If the Bus Connected to APORT4Y is in Conflict With Another Peripheral */ #define _CSEN_APORTCONFLICT_APORT4YCONFLICT_SHIFT 9 /**< Shift value for CSEN_APORT4YCONFLICT */ #define _CSEN_APORTCONFLICT_APORT4YCONFLICT_MASK 0x200UL /**< Bit mask for CSEN_APORT4YCONFLICT */ #define _CSEN_APORTCONFLICT_APORT4YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTCONFLICT */ #define CSEN_APORTCONFLICT_APORT4YCONFLICT_DEFAULT (_CSEN_APORTCONFLICT_APORT4YCONFLICT_DEFAULT << 9) /**< Shifted mode DEFAULT for CSEN_APORTCONFLICT */ /* Bit fields for CSEN CMPTHR */ #define _CSEN_CMPTHR_RESETVALUE 0x00000000UL /**< Default value for CSEN_CMPTHR */ #define _CSEN_CMPTHR_MASK 0x0000FFFFUL /**< Mask for CSEN_CMPTHR */ #define _CSEN_CMPTHR_CMPTHR_SHIFT 0 /**< Shift value for CSEN_CMPTHR */ #define _CSEN_CMPTHR_CMPTHR_MASK 0xFFFFUL /**< Bit mask for CSEN_CMPTHR */ #define _CSEN_CMPTHR_CMPTHR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CMPTHR */ #define CSEN_CMPTHR_CMPTHR_DEFAULT (_CSEN_CMPTHR_CMPTHR_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_CMPTHR */ /* Bit fields for CSEN EMA */ #define _CSEN_EMA_RESETVALUE 0x00000000UL /**< Default value for CSEN_EMA */ #define _CSEN_EMA_MASK 0x003FFFFFUL /**< Mask for CSEN_EMA */ #define _CSEN_EMA_EMA_SHIFT 0 /**< Shift value for CSEN_EMA */ #define _CSEN_EMA_EMA_MASK 0x3FFFFFUL /**< Bit mask for CSEN_EMA */ #define _CSEN_EMA_EMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_EMA */ #define CSEN_EMA_EMA_DEFAULT (_CSEN_EMA_EMA_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_EMA */ /* Bit fields for CSEN EMACTRL */ #define _CSEN_EMACTRL_RESETVALUE 0x00000000UL /**< Default value for CSEN_EMACTRL */ #define _CSEN_EMACTRL_MASK 0x00000007UL /**< Mask for CSEN_EMACTRL */ #define _CSEN_EMACTRL_EMASAMPLE_SHIFT 0 /**< Shift value for CSEN_EMASAMPLE */ #define _CSEN_EMACTRL_EMASAMPLE_MASK 0x7UL /**< Bit mask for CSEN_EMASAMPLE */ #define _CSEN_EMACTRL_EMASAMPLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_EMACTRL */ #define _CSEN_EMACTRL_EMASAMPLE_W1 0x00000000UL /**< Mode W1 for CSEN_EMACTRL */ #define _CSEN_EMACTRL_EMASAMPLE_W2 0x00000001UL /**< Mode W2 for CSEN_EMACTRL */ #define _CSEN_EMACTRL_EMASAMPLE_W4 0x00000002UL /**< Mode W4 for CSEN_EMACTRL */ #define _CSEN_EMACTRL_EMASAMPLE_W8 0x00000003UL /**< Mode W8 for CSEN_EMACTRL */ #define _CSEN_EMACTRL_EMASAMPLE_W16 0x00000004UL /**< Mode W16 for CSEN_EMACTRL */ #define _CSEN_EMACTRL_EMASAMPLE_W32 0x00000005UL /**< Mode W32 for CSEN_EMACTRL */ #define _CSEN_EMACTRL_EMASAMPLE_W64 0x00000006UL /**< Mode W64 for CSEN_EMACTRL */ #define CSEN_EMACTRL_EMASAMPLE_DEFAULT (_CSEN_EMACTRL_EMASAMPLE_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_EMACTRL */ #define CSEN_EMACTRL_EMASAMPLE_W1 (_CSEN_EMACTRL_EMASAMPLE_W1 << 0) /**< Shifted mode W1 for CSEN_EMACTRL */ #define CSEN_EMACTRL_EMASAMPLE_W2 (_CSEN_EMACTRL_EMASAMPLE_W2 << 0) /**< Shifted mode W2 for CSEN_EMACTRL */ #define CSEN_EMACTRL_EMASAMPLE_W4 (_CSEN_EMACTRL_EMASAMPLE_W4 << 0) /**< Shifted mode W4 for CSEN_EMACTRL */ #define CSEN_EMACTRL_EMASAMPLE_W8 (_CSEN_EMACTRL_EMASAMPLE_W8 << 0) /**< Shifted mode W8 for CSEN_EMACTRL */ #define CSEN_EMACTRL_EMASAMPLE_W16 (_CSEN_EMACTRL_EMASAMPLE_W16 << 0) /**< Shifted mode W16 for CSEN_EMACTRL */ #define CSEN_EMACTRL_EMASAMPLE_W32 (_CSEN_EMACTRL_EMASAMPLE_W32 << 0) /**< Shifted mode W32 for CSEN_EMACTRL */ #define CSEN_EMACTRL_EMASAMPLE_W64 (_CSEN_EMACTRL_EMASAMPLE_W64 << 0) /**< Shifted mode W64 for CSEN_EMACTRL */ /* Bit fields for CSEN SINGLECTRL */ #define _CSEN_SINGLECTRL_RESETVALUE 0x00000000UL /**< Default value for CSEN_SINGLECTRL */ #define _CSEN_SINGLECTRL_MASK 0x000007F0UL /**< Mask for CSEN_SINGLECTRL */ #define _CSEN_SINGLECTRL_SINGLESEL_SHIFT 4 /**< Shift value for CSEN_SINGLESEL */ #define _CSEN_SINGLECTRL_SINGLESEL_MASK 0x7F0UL /**< Bit mask for CSEN_SINGLESEL */ #define _CSEN_SINGLECTRL_SINGLESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_SINGLECTRL */ #define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH0 0x00000020UL /**< Mode APORT1XCH0 for CSEN_SINGLECTRL */ #define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH1 0x00000021UL /**< Mode APORT1YCH1 for CSEN_SINGLECTRL */ #define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH2 0x00000022UL /**< Mode APORT1XCH2 for CSEN_SINGLECTRL */ #define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH3 0x00000023UL /**< Mode APORT1YCH3 for CSEN_SINGLECTRL */ #define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH4 0x00000024UL /**< Mode APORT1XCH4 for CSEN_SINGLECTRL */ #define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH5 0x00000025UL /**< Mode APORT1YCH5 for CSEN_SINGLECTRL */ #define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH6 0x00000026UL /**< Mode APORT1XCH6 for CSEN_SINGLECTRL */ #define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH7 0x00000027UL /**< Mode APORT1YCH7 for CSEN_SINGLECTRL */ #define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH8 0x00000028UL /**< Mode APORT1XCH8 for CSEN_SINGLECTRL */ #define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH9 0x00000029UL /**< Mode APORT1YCH9 for CSEN_SINGLECTRL */ #define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH10 0x0000002AUL /**< Mode APORT1XCH10 for CSEN_SINGLECTRL */ #define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH11 0x0000002BUL /**< Mode APORT1YCH11 for CSEN_SINGLECTRL */ #define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH12 0x0000002CUL /**< Mode APORT1XCH12 for CSEN_SINGLECTRL */ #define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH13 0x0000002DUL /**< Mode APORT1YCH13 for CSEN_SINGLECTRL */ #define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH14 0x0000002EUL /**< Mode APORT1XCH14 for CSEN_SINGLECTRL */ #define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH15 0x0000002FUL /**< Mode APORT1YCH15 for CSEN_SINGLECTRL */ #define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH16 0x00000030UL /**< Mode APORT1XCH16 for CSEN_SINGLECTRL */ #define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH17 0x00000031UL /**< Mode APORT1YCH17 for CSEN_SINGLECTRL */ #define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH18 0x00000032UL /**< Mode APORT1XCH18 for CSEN_SINGLECTRL */ #define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH19 0x00000033UL /**< Mode APORT1YCH19 for CSEN_SINGLECTRL */ #define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH20 0x00000034UL /**< Mode APORT1XCH20 for CSEN_SINGLECTRL */ #define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH21 0x00000035UL /**< Mode APORT1YCH21 for CSEN_SINGLECTRL */ #define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH22 0x00000036UL /**< Mode APORT1XCH22 for CSEN_SINGLECTRL */ #define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH23 0x00000037UL /**< Mode APORT1YCH23 for CSEN_SINGLECTRL */ #define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH24 0x00000038UL /**< Mode APORT1XCH24 for CSEN_SINGLECTRL */ #define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH25 0x00000039UL /**< Mode APORT1YCH25 for CSEN_SINGLECTRL */ #define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH26 0x0000003AUL /**< Mode APORT1XCH26 for CSEN_SINGLECTRL */ #define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH27 0x0000003BUL /**< Mode APORT1YCH27 for CSEN_SINGLECTRL */ #define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH28 0x0000003CUL /**< Mode APORT1XCH28 for CSEN_SINGLECTRL */ #define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH29 0x0000003DUL /**< Mode APORT1YCH29 for CSEN_SINGLECTRL */ #define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH30 0x0000003EUL /**< Mode APORT1XCH30 for CSEN_SINGLECTRL */ #define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH31 0x0000003FUL /**< Mode APORT1YCH31 for CSEN_SINGLECTRL */ #define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH0 0x00000060UL /**< Mode APORT3XCH0 for CSEN_SINGLECTRL */ #define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH1 0x00000061UL /**< Mode APORT3YCH1 for CSEN_SINGLECTRL */ #define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH2 0x00000062UL /**< Mode APORT3XCH2 for CSEN_SINGLECTRL */ #define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH3 0x00000063UL /**< Mode APORT3YCH3 for CSEN_SINGLECTRL */ #define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH4 0x00000064UL /**< Mode APORT3XCH4 for CSEN_SINGLECTRL */ #define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH5 0x00000065UL /**< Mode APORT3YCH5 for CSEN_SINGLECTRL */ #define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH6 0x00000066UL /**< Mode APORT3XCH6 for CSEN_SINGLECTRL */ #define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH7 0x00000067UL /**< Mode APORT3YCH7 for CSEN_SINGLECTRL */ #define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH8 0x00000068UL /**< Mode APORT3XCH8 for CSEN_SINGLECTRL */ #define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH9 0x00000069UL /**< Mode APORT3YCH9 for CSEN_SINGLECTRL */ #define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH10 0x0000006AUL /**< Mode APORT3XCH10 for CSEN_SINGLECTRL */ #define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH11 0x0000006BUL /**< Mode APORT3YCH11 for CSEN_SINGLECTRL */ #define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH12 0x0000006CUL /**< Mode APORT3XCH12 for CSEN_SINGLECTRL */ #define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH13 0x0000006DUL /**< Mode APORT3YCH13 for CSEN_SINGLECTRL */ #define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH14 0x0000006EUL /**< Mode APORT3XCH14 for CSEN_SINGLECTRL */ #define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH15 0x0000006FUL /**< Mode APORT3YCH15 for CSEN_SINGLECTRL */ #define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH16 0x00000070UL /**< Mode APORT3XCH16 for CSEN_SINGLECTRL */ #define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH17 0x00000071UL /**< Mode APORT3YCH17 for CSEN_SINGLECTRL */ #define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH18 0x00000072UL /**< Mode APORT3XCH18 for CSEN_SINGLECTRL */ #define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH19 0x00000073UL /**< Mode APORT3YCH19 for CSEN_SINGLECTRL */ #define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH20 0x00000074UL /**< Mode APORT3XCH20 for CSEN_SINGLECTRL */ #define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH21 0x00000075UL /**< Mode APORT3YCH21 for CSEN_SINGLECTRL */ #define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH22 0x00000076UL /**< Mode APORT3XCH22 for CSEN_SINGLECTRL */ #define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH23 0x00000077UL /**< Mode APORT3YCH23 for CSEN_SINGLECTRL */ #define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH24 0x00000078UL /**< Mode APORT3XCH24 for CSEN_SINGLECTRL */ #define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH25 0x00000079UL /**< Mode APORT3YCH25 for CSEN_SINGLECTRL */ #define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH26 0x0000007AUL /**< Mode APORT3XCH26 for CSEN_SINGLECTRL */ #define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH27 0x0000007BUL /**< Mode APORT3YCH27 for CSEN_SINGLECTRL */ #define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH28 0x0000007CUL /**< Mode APORT3XCH28 for CSEN_SINGLECTRL */ #define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH29 0x0000007DUL /**< Mode APORT3YCH29 for CSEN_SINGLECTRL */ #define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH30 0x0000007EUL /**< Mode APORT3XCH30 for CSEN_SINGLECTRL */ #define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH31 0x0000007FUL /**< Mode APORT3YCH31 for CSEN_SINGLECTRL */ #define CSEN_SINGLECTRL_SINGLESEL_DEFAULT (_CSEN_SINGLECTRL_SINGLESEL_DEFAULT << 4) /**< Shifted mode DEFAULT for CSEN_SINGLECTRL */ #define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH0 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH0 << 4) /**< Shifted mode APORT1XCH0 for CSEN_SINGLECTRL */ #define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH1 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH1 << 4) /**< Shifted mode APORT1YCH1 for CSEN_SINGLECTRL */ #define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH2 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH2 << 4) /**< Shifted mode APORT1XCH2 for CSEN_SINGLECTRL */ #define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH3 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH3 << 4) /**< Shifted mode APORT1YCH3 for CSEN_SINGLECTRL */ #define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH4 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH4 << 4) /**< Shifted mode APORT1XCH4 for CSEN_SINGLECTRL */ #define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH5 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH5 << 4) /**< Shifted mode APORT1YCH5 for CSEN_SINGLECTRL */ #define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH6 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH6 << 4) /**< Shifted mode APORT1XCH6 for CSEN_SINGLECTRL */ #define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH7 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH7 << 4) /**< Shifted mode APORT1YCH7 for CSEN_SINGLECTRL */ #define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH8 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH8 << 4) /**< Shifted mode APORT1XCH8 for CSEN_SINGLECTRL */ #define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH9 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH9 << 4) /**< Shifted mode APORT1YCH9 for CSEN_SINGLECTRL */ #define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH10 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH10 << 4) /**< Shifted mode APORT1XCH10 for CSEN_SINGLECTRL */ #define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH11 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH11 << 4) /**< Shifted mode APORT1YCH11 for CSEN_SINGLECTRL */ #define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH12 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH12 << 4) /**< Shifted mode APORT1XCH12 for CSEN_SINGLECTRL */ #define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH13 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH13 << 4) /**< Shifted mode APORT1YCH13 for CSEN_SINGLECTRL */ #define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH14 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH14 << 4) /**< Shifted mode APORT1XCH14 for CSEN_SINGLECTRL */ #define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH15 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH15 << 4) /**< Shifted mode APORT1YCH15 for CSEN_SINGLECTRL */ #define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH16 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH16 << 4) /**< Shifted mode APORT1XCH16 for CSEN_SINGLECTRL */ #define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH17 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH17 << 4) /**< Shifted mode APORT1YCH17 for CSEN_SINGLECTRL */ #define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH18 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH18 << 4) /**< Shifted mode APORT1XCH18 for CSEN_SINGLECTRL */ #define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH19 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH19 << 4) /**< Shifted mode APORT1YCH19 for CSEN_SINGLECTRL */ #define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH20 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH20 << 4) /**< Shifted mode APORT1XCH20 for CSEN_SINGLECTRL */ #define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH21 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH21 << 4) /**< Shifted mode APORT1YCH21 for CSEN_SINGLECTRL */ #define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH22 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH22 << 4) /**< Shifted mode APORT1XCH22 for CSEN_SINGLECTRL */ #define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH23 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH23 << 4) /**< Shifted mode APORT1YCH23 for CSEN_SINGLECTRL */ #define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH24 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH24 << 4) /**< Shifted mode APORT1XCH24 for CSEN_SINGLECTRL */ #define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH25 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH25 << 4) /**< Shifted mode APORT1YCH25 for CSEN_SINGLECTRL */ #define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH26 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH26 << 4) /**< Shifted mode APORT1XCH26 for CSEN_SINGLECTRL */ #define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH27 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH27 << 4) /**< Shifted mode APORT1YCH27 for CSEN_SINGLECTRL */ #define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH28 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH28 << 4) /**< Shifted mode APORT1XCH28 for CSEN_SINGLECTRL */ #define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH29 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH29 << 4) /**< Shifted mode APORT1YCH29 for CSEN_SINGLECTRL */ #define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH30 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH30 << 4) /**< Shifted mode APORT1XCH30 for CSEN_SINGLECTRL */ #define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH31 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH31 << 4) /**< Shifted mode APORT1YCH31 for CSEN_SINGLECTRL */ #define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH0 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH0 << 4) /**< Shifted mode APORT3XCH0 for CSEN_SINGLECTRL */ #define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH1 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH1 << 4) /**< Shifted mode APORT3YCH1 for CSEN_SINGLECTRL */ #define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH2 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH2 << 4) /**< Shifted mode APORT3XCH2 for CSEN_SINGLECTRL */ #define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH3 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH3 << 4) /**< Shifted mode APORT3YCH3 for CSEN_SINGLECTRL */ #define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH4 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH4 << 4) /**< Shifted mode APORT3XCH4 for CSEN_SINGLECTRL */ #define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH5 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH5 << 4) /**< Shifted mode APORT3YCH5 for CSEN_SINGLECTRL */ #define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH6 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH6 << 4) /**< Shifted mode APORT3XCH6 for CSEN_SINGLECTRL */ #define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH7 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH7 << 4) /**< Shifted mode APORT3YCH7 for CSEN_SINGLECTRL */ #define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH8 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH8 << 4) /**< Shifted mode APORT3XCH8 for CSEN_SINGLECTRL */ #define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH9 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH9 << 4) /**< Shifted mode APORT3YCH9 for CSEN_SINGLECTRL */ #define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH10 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH10 << 4) /**< Shifted mode APORT3XCH10 for CSEN_SINGLECTRL */ #define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH11 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH11 << 4) /**< Shifted mode APORT3YCH11 for CSEN_SINGLECTRL */ #define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH12 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH12 << 4) /**< Shifted mode APORT3XCH12 for CSEN_SINGLECTRL */ #define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH13 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH13 << 4) /**< Shifted mode APORT3YCH13 for CSEN_SINGLECTRL */ #define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH14 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH14 << 4) /**< Shifted mode APORT3XCH14 for CSEN_SINGLECTRL */ #define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH15 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH15 << 4) /**< Shifted mode APORT3YCH15 for CSEN_SINGLECTRL */ #define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH16 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH16 << 4) /**< Shifted mode APORT3XCH16 for CSEN_SINGLECTRL */ #define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH17 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH17 << 4) /**< Shifted mode APORT3YCH17 for CSEN_SINGLECTRL */ #define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH18 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH18 << 4) /**< Shifted mode APORT3XCH18 for CSEN_SINGLECTRL */ #define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH19 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH19 << 4) /**< Shifted mode APORT3YCH19 for CSEN_SINGLECTRL */ #define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH20 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH20 << 4) /**< Shifted mode APORT3XCH20 for CSEN_SINGLECTRL */ #define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH21 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH21 << 4) /**< Shifted mode APORT3YCH21 for CSEN_SINGLECTRL */ #define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH22 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH22 << 4) /**< Shifted mode APORT3XCH22 for CSEN_SINGLECTRL */ #define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH23 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH23 << 4) /**< Shifted mode APORT3YCH23 for CSEN_SINGLECTRL */ #define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH24 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH24 << 4) /**< Shifted mode APORT3XCH24 for CSEN_SINGLECTRL */ #define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH25 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH25 << 4) /**< Shifted mode APORT3YCH25 for CSEN_SINGLECTRL */ #define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH26 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH26 << 4) /**< Shifted mode APORT3XCH26 for CSEN_SINGLECTRL */ #define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH27 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH27 << 4) /**< Shifted mode APORT3YCH27 for CSEN_SINGLECTRL */ #define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH28 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH28 << 4) /**< Shifted mode APORT3XCH28 for CSEN_SINGLECTRL */ #define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH29 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH29 << 4) /**< Shifted mode APORT3YCH29 for CSEN_SINGLECTRL */ #define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH30 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH30 << 4) /**< Shifted mode APORT3XCH30 for CSEN_SINGLECTRL */ #define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH31 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH31 << 4) /**< Shifted mode APORT3YCH31 for CSEN_SINGLECTRL */ /* Bit fields for CSEN DMBASELINE */ #define _CSEN_DMBASELINE_RESETVALUE 0x00000000UL /**< Default value for CSEN_DMBASELINE */ #define _CSEN_DMBASELINE_MASK 0xFFFFFFFFUL /**< Mask for CSEN_DMBASELINE */ #define _CSEN_DMBASELINE_BASELINEUP_SHIFT 0 /**< Shift value for CSEN_BASELINEUP */ #define _CSEN_DMBASELINE_BASELINEUP_MASK 0xFFFFUL /**< Bit mask for CSEN_BASELINEUP */ #define _CSEN_DMBASELINE_BASELINEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_DMBASELINE */ #define CSEN_DMBASELINE_BASELINEUP_DEFAULT (_CSEN_DMBASELINE_BASELINEUP_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_DMBASELINE */ #define _CSEN_DMBASELINE_BASELINEDN_SHIFT 16 /**< Shift value for CSEN_BASELINEDN */ #define _CSEN_DMBASELINE_BASELINEDN_MASK 0xFFFF0000UL /**< Bit mask for CSEN_BASELINEDN */ #define _CSEN_DMBASELINE_BASELINEDN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_DMBASELINE */ #define CSEN_DMBASELINE_BASELINEDN_DEFAULT (_CSEN_DMBASELINE_BASELINEDN_DEFAULT << 16) /**< Shifted mode DEFAULT for CSEN_DMBASELINE */ /* Bit fields for CSEN DMCFG */ #define _CSEN_DMCFG_RESETVALUE 0x00000000UL /**< Default value for CSEN_DMCFG */ #define _CSEN_DMCFG_MASK 0x103F0FFFUL /**< Mask for CSEN_DMCFG */ #define _CSEN_DMCFG_DMG_SHIFT 0 /**< Shift value for CSEN_DMG */ #define _CSEN_DMCFG_DMG_MASK 0xFFUL /**< Bit mask for CSEN_DMG */ #define _CSEN_DMCFG_DMG_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_DMCFG */ #define CSEN_DMCFG_DMG_DEFAULT (_CSEN_DMCFG_DMG_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_DMCFG */ #define _CSEN_DMCFG_DMR_SHIFT 8 /**< Shift value for CSEN_DMR */ #define _CSEN_DMCFG_DMR_MASK 0xF00UL /**< Bit mask for CSEN_DMR */ #define _CSEN_DMCFG_DMR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_DMCFG */ #define CSEN_DMCFG_DMR_DEFAULT (_CSEN_DMCFG_DMR_DEFAULT << 8) /**< Shifted mode DEFAULT for CSEN_DMCFG */ #define _CSEN_DMCFG_DMCR_SHIFT 16 /**< Shift value for CSEN_DMCR */ #define _CSEN_DMCFG_DMCR_MASK 0xF0000UL /**< Bit mask for CSEN_DMCR */ #define _CSEN_DMCFG_DMCR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_DMCFG */ #define CSEN_DMCFG_DMCR_DEFAULT (_CSEN_DMCFG_DMCR_DEFAULT << 16) /**< Shifted mode DEFAULT for CSEN_DMCFG */ #define _CSEN_DMCFG_CRMODE_SHIFT 20 /**< Shift value for CSEN_CRMODE */ #define _CSEN_DMCFG_CRMODE_MASK 0x300000UL /**< Bit mask for CSEN_CRMODE */ #define _CSEN_DMCFG_CRMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_DMCFG */ #define _CSEN_DMCFG_CRMODE_DM10 0x00000000UL /**< Mode DM10 for CSEN_DMCFG */ #define _CSEN_DMCFG_CRMODE_DM12 0x00000001UL /**< Mode DM12 for CSEN_DMCFG */ #define _CSEN_DMCFG_CRMODE_DM14 0x00000002UL /**< Mode DM14 for CSEN_DMCFG */ #define _CSEN_DMCFG_CRMODE_DM16 0x00000003UL /**< Mode DM16 for CSEN_DMCFG */ #define CSEN_DMCFG_CRMODE_DEFAULT (_CSEN_DMCFG_CRMODE_DEFAULT << 20) /**< Shifted mode DEFAULT for CSEN_DMCFG */ #define CSEN_DMCFG_CRMODE_DM10 (_CSEN_DMCFG_CRMODE_DM10 << 20) /**< Shifted mode DM10 for CSEN_DMCFG */ #define CSEN_DMCFG_CRMODE_DM12 (_CSEN_DMCFG_CRMODE_DM12 << 20) /**< Shifted mode DM12 for CSEN_DMCFG */ #define CSEN_DMCFG_CRMODE_DM14 (_CSEN_DMCFG_CRMODE_DM14 << 20) /**< Shifted mode DM14 for CSEN_DMCFG */ #define CSEN_DMCFG_CRMODE_DM16 (_CSEN_DMCFG_CRMODE_DM16 << 20) /**< Shifted mode DM16 for CSEN_DMCFG */ #define CSEN_DMCFG_DMGRDIS (0x1UL << 28) /**< Delta Modulation Gain Step Reduction Disable */ #define _CSEN_DMCFG_DMGRDIS_SHIFT 28 /**< Shift value for CSEN_DMGRDIS */ #define _CSEN_DMCFG_DMGRDIS_MASK 0x10000000UL /**< Bit mask for CSEN_DMGRDIS */ #define _CSEN_DMCFG_DMGRDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_DMCFG */ #define CSEN_DMCFG_DMGRDIS_DEFAULT (_CSEN_DMCFG_DMGRDIS_DEFAULT << 28) /**< Shifted mode DEFAULT for CSEN_DMCFG */ /* Bit fields for CSEN ANACTRL */ #define _CSEN_ANACTRL_RESETVALUE 0x00000070UL /**< Default value for CSEN_ANACTRL */ #define _CSEN_ANACTRL_MASK 0x00700770UL /**< Mask for CSEN_ANACTRL */ #define _CSEN_ANACTRL_IREFPROG_SHIFT 4 /**< Shift value for CSEN_IREFPROG */ #define _CSEN_ANACTRL_IREFPROG_MASK 0x70UL /**< Bit mask for CSEN_IREFPROG */ #define _CSEN_ANACTRL_IREFPROG_DEFAULT 0x00000007UL /**< Mode DEFAULT for CSEN_ANACTRL */ #define CSEN_ANACTRL_IREFPROG_DEFAULT (_CSEN_ANACTRL_IREFPROG_DEFAULT << 4) /**< Shifted mode DEFAULT for CSEN_ANACTRL */ #define _CSEN_ANACTRL_IDACIREFS_SHIFT 8 /**< Shift value for CSEN_IDACIREFS */ #define _CSEN_ANACTRL_IDACIREFS_MASK 0x700UL /**< Bit mask for CSEN_IDACIREFS */ #define _CSEN_ANACTRL_IDACIREFS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_ANACTRL */ #define CSEN_ANACTRL_IDACIREFS_DEFAULT (_CSEN_ANACTRL_IDACIREFS_DEFAULT << 8) /**< Shifted mode DEFAULT for CSEN_ANACTRL */ #define _CSEN_ANACTRL_TRSTPROG_SHIFT 20 /**< Shift value for CSEN_TRSTPROG */ #define _CSEN_ANACTRL_TRSTPROG_MASK 0x700000UL /**< Bit mask for CSEN_TRSTPROG */ #define _CSEN_ANACTRL_TRSTPROG_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_ANACTRL */ #define CSEN_ANACTRL_TRSTPROG_DEFAULT (_CSEN_ANACTRL_TRSTPROG_DEFAULT << 20) /**< Shifted mode DEFAULT for CSEN_ANACTRL */ /* Bit fields for CSEN IF */ #define _CSEN_IF_RESETVALUE 0x00000000UL /**< Default value for CSEN_IF */ #define _CSEN_IF_MASK 0x0000001FUL /**< Mask for CSEN_IF */ #define CSEN_IF_CMP (0x1UL << 0) /**< Digital Comparator Interrupt Flag */ #define _CSEN_IF_CMP_SHIFT 0 /**< Shift value for CSEN_CMP */ #define _CSEN_IF_CMP_MASK 0x1UL /**< Bit mask for CSEN_CMP */ #define _CSEN_IF_CMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IF */ #define CSEN_IF_CMP_DEFAULT (_CSEN_IF_CMP_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_IF */ #define CSEN_IF_CONV (0x1UL << 1) /**< Conversion Done Interrupt Flag */ #define _CSEN_IF_CONV_SHIFT 1 /**< Shift value for CSEN_CONV */ #define _CSEN_IF_CONV_MASK 0x2UL /**< Bit mask for CSEN_CONV */ #define _CSEN_IF_CONV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IF */ #define CSEN_IF_CONV_DEFAULT (_CSEN_IF_CONV_DEFAULT << 1) /**< Shifted mode DEFAULT for CSEN_IF */ #define CSEN_IF_EOS (0x1UL << 2) /**< End of Scan Interrupt Flag. */ #define _CSEN_IF_EOS_SHIFT 2 /**< Shift value for CSEN_EOS */ #define _CSEN_IF_EOS_MASK 0x4UL /**< Bit mask for CSEN_EOS */ #define _CSEN_IF_EOS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IF */ #define CSEN_IF_EOS_DEFAULT (_CSEN_IF_EOS_DEFAULT << 2) /**< Shifted mode DEFAULT for CSEN_IF */ #define CSEN_IF_DMAOF (0x1UL << 3) /**< DMA Overflow Interrupt Flag. */ #define _CSEN_IF_DMAOF_SHIFT 3 /**< Shift value for CSEN_DMAOF */ #define _CSEN_IF_DMAOF_MASK 0x8UL /**< Bit mask for CSEN_DMAOF */ #define _CSEN_IF_DMAOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IF */ #define CSEN_IF_DMAOF_DEFAULT (_CSEN_IF_DMAOF_DEFAULT << 3) /**< Shifted mode DEFAULT for CSEN_IF */ #define CSEN_IF_APORTCONFLICT (0x1UL << 4) /**< APORT Conflict Interrupt Flag */ #define _CSEN_IF_APORTCONFLICT_SHIFT 4 /**< Shift value for CSEN_APORTCONFLICT */ #define _CSEN_IF_APORTCONFLICT_MASK 0x10UL /**< Bit mask for CSEN_APORTCONFLICT */ #define _CSEN_IF_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IF */ #define CSEN_IF_APORTCONFLICT_DEFAULT (_CSEN_IF_APORTCONFLICT_DEFAULT << 4) /**< Shifted mode DEFAULT for CSEN_IF */ /* Bit fields for CSEN IFS */ #define _CSEN_IFS_RESETVALUE 0x00000000UL /**< Default value for CSEN_IFS */ #define _CSEN_IFS_MASK 0x0000001FUL /**< Mask for CSEN_IFS */ #define CSEN_IFS_CMP (0x1UL << 0) /**< Set CMP Interrupt Flag */ #define _CSEN_IFS_CMP_SHIFT 0 /**< Shift value for CSEN_CMP */ #define _CSEN_IFS_CMP_MASK 0x1UL /**< Bit mask for CSEN_CMP */ #define _CSEN_IFS_CMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IFS */ #define CSEN_IFS_CMP_DEFAULT (_CSEN_IFS_CMP_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_IFS */ #define CSEN_IFS_CONV (0x1UL << 1) /**< Set CONV Interrupt Flag */ #define _CSEN_IFS_CONV_SHIFT 1 /**< Shift value for CSEN_CONV */ #define _CSEN_IFS_CONV_MASK 0x2UL /**< Bit mask for CSEN_CONV */ #define _CSEN_IFS_CONV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IFS */ #define CSEN_IFS_CONV_DEFAULT (_CSEN_IFS_CONV_DEFAULT << 1) /**< Shifted mode DEFAULT for CSEN_IFS */ #define CSEN_IFS_EOS (0x1UL << 2) /**< Set EOS Interrupt Flag */ #define _CSEN_IFS_EOS_SHIFT 2 /**< Shift value for CSEN_EOS */ #define _CSEN_IFS_EOS_MASK 0x4UL /**< Bit mask for CSEN_EOS */ #define _CSEN_IFS_EOS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IFS */ #define CSEN_IFS_EOS_DEFAULT (_CSEN_IFS_EOS_DEFAULT << 2) /**< Shifted mode DEFAULT for CSEN_IFS */ #define CSEN_IFS_DMAOF (0x1UL << 3) /**< Set DMAOF Interrupt Flag */ #define _CSEN_IFS_DMAOF_SHIFT 3 /**< Shift value for CSEN_DMAOF */ #define _CSEN_IFS_DMAOF_MASK 0x8UL /**< Bit mask for CSEN_DMAOF */ #define _CSEN_IFS_DMAOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IFS */ #define CSEN_IFS_DMAOF_DEFAULT (_CSEN_IFS_DMAOF_DEFAULT << 3) /**< Shifted mode DEFAULT for CSEN_IFS */ #define CSEN_IFS_APORTCONFLICT (0x1UL << 4) /**< Set APORTCONFLICT Interrupt Flag */ #define _CSEN_IFS_APORTCONFLICT_SHIFT 4 /**< Shift value for CSEN_APORTCONFLICT */ #define _CSEN_IFS_APORTCONFLICT_MASK 0x10UL /**< Bit mask for CSEN_APORTCONFLICT */ #define _CSEN_IFS_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IFS */ #define CSEN_IFS_APORTCONFLICT_DEFAULT (_CSEN_IFS_APORTCONFLICT_DEFAULT << 4) /**< Shifted mode DEFAULT for CSEN_IFS */ /* Bit fields for CSEN IFC */ #define _CSEN_IFC_RESETVALUE 0x00000000UL /**< Default value for CSEN_IFC */ #define _CSEN_IFC_MASK 0x0000001FUL /**< Mask for CSEN_IFC */ #define CSEN_IFC_CMP (0x1UL << 0) /**< Clear CMP Interrupt Flag */ #define _CSEN_IFC_CMP_SHIFT 0 /**< Shift value for CSEN_CMP */ #define _CSEN_IFC_CMP_MASK 0x1UL /**< Bit mask for CSEN_CMP */ #define _CSEN_IFC_CMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IFC */ #define CSEN_IFC_CMP_DEFAULT (_CSEN_IFC_CMP_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_IFC */ #define CSEN_IFC_CONV (0x1UL << 1) /**< Clear CONV Interrupt Flag */ #define _CSEN_IFC_CONV_SHIFT 1 /**< Shift value for CSEN_CONV */ #define _CSEN_IFC_CONV_MASK 0x2UL /**< Bit mask for CSEN_CONV */ #define _CSEN_IFC_CONV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IFC */ #define CSEN_IFC_CONV_DEFAULT (_CSEN_IFC_CONV_DEFAULT << 1) /**< Shifted mode DEFAULT for CSEN_IFC */ #define CSEN_IFC_EOS (0x1UL << 2) /**< Clear EOS Interrupt Flag */ #define _CSEN_IFC_EOS_SHIFT 2 /**< Shift value for CSEN_EOS */ #define _CSEN_IFC_EOS_MASK 0x4UL /**< Bit mask for CSEN_EOS */ #define _CSEN_IFC_EOS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IFC */ #define CSEN_IFC_EOS_DEFAULT (_CSEN_IFC_EOS_DEFAULT << 2) /**< Shifted mode DEFAULT for CSEN_IFC */ #define CSEN_IFC_DMAOF (0x1UL << 3) /**< Clear DMAOF Interrupt Flag */ #define _CSEN_IFC_DMAOF_SHIFT 3 /**< Shift value for CSEN_DMAOF */ #define _CSEN_IFC_DMAOF_MASK 0x8UL /**< Bit mask for CSEN_DMAOF */ #define _CSEN_IFC_DMAOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IFC */ #define CSEN_IFC_DMAOF_DEFAULT (_CSEN_IFC_DMAOF_DEFAULT << 3) /**< Shifted mode DEFAULT for CSEN_IFC */ #define CSEN_IFC_APORTCONFLICT (0x1UL << 4) /**< Clear APORTCONFLICT Interrupt Flag */ #define _CSEN_IFC_APORTCONFLICT_SHIFT 4 /**< Shift value for CSEN_APORTCONFLICT */ #define _CSEN_IFC_APORTCONFLICT_MASK 0x10UL /**< Bit mask for CSEN_APORTCONFLICT */ #define _CSEN_IFC_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IFC */ #define CSEN_IFC_APORTCONFLICT_DEFAULT (_CSEN_IFC_APORTCONFLICT_DEFAULT << 4) /**< Shifted mode DEFAULT for CSEN_IFC */ /* Bit fields for CSEN IEN */ #define _CSEN_IEN_RESETVALUE 0x00000000UL /**< Default value for CSEN_IEN */ #define _CSEN_IEN_MASK 0x0000001FUL /**< Mask for CSEN_IEN */ #define CSEN_IEN_CMP (0x1UL << 0) /**< CMP Interrupt Enable */ #define _CSEN_IEN_CMP_SHIFT 0 /**< Shift value for CSEN_CMP */ #define _CSEN_IEN_CMP_MASK 0x1UL /**< Bit mask for CSEN_CMP */ #define _CSEN_IEN_CMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IEN */ #define CSEN_IEN_CMP_DEFAULT (_CSEN_IEN_CMP_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_IEN */ #define CSEN_IEN_CONV (0x1UL << 1) /**< CONV Interrupt Enable */ #define _CSEN_IEN_CONV_SHIFT 1 /**< Shift value for CSEN_CONV */ #define _CSEN_IEN_CONV_MASK 0x2UL /**< Bit mask for CSEN_CONV */ #define _CSEN_IEN_CONV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IEN */ #define CSEN_IEN_CONV_DEFAULT (_CSEN_IEN_CONV_DEFAULT << 1) /**< Shifted mode DEFAULT for CSEN_IEN */ #define CSEN_IEN_EOS (0x1UL << 2) /**< EOS Interrupt Enable */ #define _CSEN_IEN_EOS_SHIFT 2 /**< Shift value for CSEN_EOS */ #define _CSEN_IEN_EOS_MASK 0x4UL /**< Bit mask for CSEN_EOS */ #define _CSEN_IEN_EOS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IEN */ #define CSEN_IEN_EOS_DEFAULT (_CSEN_IEN_EOS_DEFAULT << 2) /**< Shifted mode DEFAULT for CSEN_IEN */ #define CSEN_IEN_DMAOF (0x1UL << 3) /**< DMAOF Interrupt Enable */ #define _CSEN_IEN_DMAOF_SHIFT 3 /**< Shift value for CSEN_DMAOF */ #define _CSEN_IEN_DMAOF_MASK 0x8UL /**< Bit mask for CSEN_DMAOF */ #define _CSEN_IEN_DMAOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IEN */ #define CSEN_IEN_DMAOF_DEFAULT (_CSEN_IEN_DMAOF_DEFAULT << 3) /**< Shifted mode DEFAULT for CSEN_IEN */ #define CSEN_IEN_APORTCONFLICT (0x1UL << 4) /**< APORTCONFLICT Interrupt Enable */ #define _CSEN_IEN_APORTCONFLICT_SHIFT 4 /**< Shift value for CSEN_APORTCONFLICT */ #define _CSEN_IEN_APORTCONFLICT_MASK 0x10UL /**< Bit mask for CSEN_APORTCONFLICT */ #define _CSEN_IEN_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IEN */ #define CSEN_IEN_APORTCONFLICT_DEFAULT (_CSEN_IEN_APORTCONFLICT_DEFAULT << 4) /**< Shifted mode DEFAULT for CSEN_IEN */ /** @} */ /** @} End of group EFR32MG12P_CSEN */ /** @} End of group Parts */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_devinfo.h.
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/***************************************************************************//** * @file * @brief EFR32MG12P_DEVINFO register and bit field definitions * @version 5.7.0 ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * SPDX-License-Identifier: Zlib * * The licensor of this software is Silicon Laboratories Inc. * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be * appreciated but is not required. * 2. Altered source versions must be plainly marked as such, and must not be * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * ******************************************************************************/ #if defined(__ICCARM__) #pragma system_include /* Treat file as system include file. */ #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang system_header /* Treat file as system include file. */ #endif /***************************************************************************//** * @addtogroup Parts * @{ ******************************************************************************/ /***************************************************************************//** * @defgroup EFR32MG12P_DEVINFO Device Information and Calibration * @{ ******************************************************************************/ /** DEVINFO Register Declaration */ typedef struct { __IM uint32_t CAL; /**< CRC of DI-page and calibration temperature */ __IM uint32_t MODULEINFO; /**< Module trace information */ __IM uint32_t MODXOCAL; /**< Module Crystal Oscillator Calibration */ uint32_t RESERVED0[5U]; /**< Reserved for future use **/ __IM uint32_t EXTINFO; /**< External Component description */ uint32_t RESERVED1[1U]; /**< Reserved for future use **/ __IM uint32_t EUI48L; /**< EUI48 OUI and Unique identifier */ __IM uint32_t EUI48H; /**< OUI */ __IM uint32_t CUSTOMINFO; /**< Custom information */ __IM uint32_t MEMINFO; /**< Flash page size and misc. chip information */ uint32_t RESERVED2[2U]; /**< Reserved for future use **/ __IM uint32_t UNIQUEL; /**< Low 32 bits of device unique number */ __IM uint32_t UNIQUEH; /**< High 32 bits of device unique number */ __IM uint32_t MSIZE; /**< Flash and SRAM Memory size in kB */ __IM uint32_t PART; /**< Part description */ __IM uint32_t DEVINFOREV; /**< Device information page revision */ __IM uint32_t EMUTEMP; /**< EMU Temperature Calibration Information */ uint32_t RESERVED3[2U]; /**< Reserved for future use **/ __IM uint32_t ADC0CAL0; /**< ADC0 calibration register 0 */ __IM uint32_t ADC0CAL1; /**< ADC0 calibration register 1 */ __IM uint32_t ADC0CAL2; /**< ADC0 calibration register 2 */ __IM uint32_t ADC0CAL3; /**< ADC0 calibration register 3 */ uint32_t RESERVED4[4U]; /**< Reserved for future use **/ __IM uint32_t HFRCOCAL0; /**< HFRCO Calibration Register (4 MHz) */ uint32_t RESERVED5[2U]; /**< Reserved for future use **/ __IM uint32_t HFRCOCAL3; /**< HFRCO Calibration Register (7 MHz) */ uint32_t RESERVED6[2U]; /**< Reserved for future use **/ __IM uint32_t HFRCOCAL6; /**< HFRCO Calibration Register (13 MHz) */ __IM uint32_t HFRCOCAL7; /**< HFRCO Calibration Register (16 MHz) */ __IM uint32_t HFRCOCAL8; /**< HFRCO Calibration Register (19 MHz) */ uint32_t RESERVED7[1U]; /**< Reserved for future use **/ __IM uint32_t HFRCOCAL10; /**< HFRCO Calibration Register (26 MHz) */ __IM uint32_t HFRCOCAL11; /**< HFRCO Calibration Register (32 MHz) */ __IM uint32_t HFRCOCAL12; /**< HFRCO Calibration Register (38 MHz) */ uint32_t RESERVED8[11U]; /**< Reserved for future use **/ __IM uint32_t AUXHFRCOCAL0; /**< AUXHFRCO Calibration Register (4 MHz) */ uint32_t RESERVED9[2U]; /**< Reserved for future use **/ __IM uint32_t AUXHFRCOCAL3; /**< AUXHFRCO Calibration Register (7 MHz) */ uint32_t RESERVED10[2U]; /**< Reserved for future use **/ __IM uint32_t AUXHFRCOCAL6; /**< AUXHFRCO Calibration Register (13 MHz) */ __IM uint32_t AUXHFRCOCAL7; /**< AUXHFRCO Calibration Register (16 MHz) */ __IM uint32_t AUXHFRCOCAL8; /**< AUXHFRCO Calibration Register (19 MHz) */ uint32_t RESERVED11[1U]; /**< Reserved for future use **/ __IM uint32_t AUXHFRCOCAL10; /**< AUXHFRCO Calibration Register (26 MHz) */ __IM uint32_t AUXHFRCOCAL11; /**< AUXHFRCO Calibration Register (32 MHz) */ __IM uint32_t AUXHFRCOCAL12; /**< AUXHFRCO Calibration Register (38 MHz) */ uint32_t RESERVED12[11U]; /**< Reserved for future use **/ __IM uint32_t VMONCAL0; /**< VMON Calibration Register 0 */ __IM uint32_t VMONCAL1; /**< VMON Calibration Register 1 */ __IM uint32_t VMONCAL2; /**< VMON Calibration Register 2 */ uint32_t RESERVED13[3U]; /**< Reserved for future use **/ __IM uint32_t IDAC0CAL0; /**< IDAC0 Calibration Register 0 */ __IM uint32_t IDAC0CAL1; /**< IDAC0 Calibration Register 1 */ uint32_t RESERVED14[2U]; /**< Reserved for future use **/ __IM uint32_t DCDCLNVCTRL0; /**< DCDC Low-noise VREF Trim Register 0 */ __IM uint32_t DCDCLPVCTRL0; /**< DCDC Low-power VREF Trim Register 0 */ __IM uint32_t DCDCLPVCTRL1; /**< DCDC Low-power VREF Trim Register 1 */ __IM uint32_t DCDCLPVCTRL2; /**< DCDC Low-power VREF Trim Register 2 */ __IM uint32_t DCDCLPVCTRL3; /**< DCDC Low-power VREF Trim Register 3 */ __IM uint32_t DCDCLPCMPHYSSEL0; /**< DCDC LPCMPHYSSEL Trim Register 0 */ __IM uint32_t DCDCLPCMPHYSSEL1; /**< DCDC LPCMPHYSSEL Trim Register 1 */ __IM uint32_t VDAC0MAINCAL; /**< VDAC0 Cals for Main Path */ __IM uint32_t VDAC0ALTCAL; /**< VDAC0 Cals for Alternate Path */ __IM uint32_t VDAC0CH1CAL; /**< VDAC0 CH1 Error Cal */ __IM uint32_t OPA0CAL0; /**< OPA0 Calibration Register for DRIVESTRENGTH 0, INCBW=1 */ __IM uint32_t OPA0CAL1; /**< OPA0 Calibration Register for DRIVESTRENGTH 1, INCBW=1 */ __IM uint32_t OPA0CAL2; /**< OPA0 Calibration Register for DRIVESTRENGTH 2, INCBW=1 */ __IM uint32_t OPA0CAL3; /**< OPA0 Calibration Register for DRIVESTRENGTH 3, INCBW=1 */ __IM uint32_t OPA1CAL0; /**< OPA1 Calibration Register for DRIVESTRENGTH 0, INCBW=1 */ __IM uint32_t OPA1CAL1; /**< OPA1 Calibration Register for DRIVESTRENGTH 1, INCBW=1 */ __IM uint32_t OPA1CAL2; /**< OPA1 Calibration Register for DRIVESTRENGTH 2, INCBW=1 */ __IM uint32_t OPA1CAL3; /**< OPA1 Calibration Register for DRIVESTRENGTH 3, INCBW=1 */ __IM uint32_t OPA2CAL0; /**< OPA2 Calibration Register for DRIVESTRENGTH 0, INCBW=1 */ __IM uint32_t OPA2CAL1; /**< OPA2 Calibration Register for DRIVESTRENGTH 1, INCBW=1 */ __IM uint32_t OPA2CAL2; /**< OPA2 Calibration Register for DRIVESTRENGTH 2, INCBW=1 */ __IM uint32_t OPA2CAL3; /**< OPA2 Calibration Register for DRIVESTRENGTH 3, INCBW=1 */ __IM uint32_t CSENGAINCAL; /**< Cap Sense Gain Adjustment */ uint32_t RESERVED15[3U]; /**< Reserved for future use **/ __IM uint32_t OPA0CAL4; /**< OPA0 Calibration Register for DRIVESTRENGTH 0, INCBW=0 */ __IM uint32_t OPA0CAL5; /**< OPA0 Calibration Register for DRIVESTRENGTH 1, INCBW=0 */ __IM uint32_t OPA0CAL6; /**< OPA0 Calibration Register for DRIVESTRENGTH 2, INCBW=0 */ __IM uint32_t OPA0CAL7; /**< OPA0 Calibration Register for DRIVESTRENGTH 3, INCBW=0 */ __IM uint32_t OPA1CAL4; /**< OPA1 Calibration Register for DRIVESTRENGTH 0, INCBW=0 */ __IM uint32_t OPA1CAL5; /**< OPA1 Calibration Register for DRIVESTRENGTH 1, INCBW=0 */ __IM uint32_t OPA1CAL6; /**< OPA1 Calibration Register for DRIVESTRENGTH 2, INCBW=0 */ __IM uint32_t OPA1CAL7; /**< OPA1 Calibration Register for DRIVESTRENGTH 3, INCBW=0 */ __IM uint32_t OPA2CAL4; /**< OPA2 Calibration Register for DRIVESTRENGTH 0, INCBW=0 */ __IM uint32_t OPA2CAL5; /**< OPA2 Calibration Register for DRIVESTRENGTH 1, INCBW=0 */ __IM uint32_t OPA2CAL6; /**< OPA2 Calibration Register for DRIVESTRENGTH 2, INCBW=0 */ __IM uint32_t OPA2CAL7; /**< OPA2 Calibration Register for DRIVESTRENGTH 3, INCBW=0 */ } DEVINFO_TypeDef; /** @} */ /***************************************************************************//** * @addtogroup EFR32MG12P_DEVINFO * @{ * @defgroup EFR32MG12P_DEVINFO_BitFields DEVINFO Bit Fields * @{ ******************************************************************************/ /* Bit fields for DEVINFO CAL */ #define _DEVINFO_CAL_MASK 0x00FFFFFFUL /**< Mask for DEVINFO_CAL */ #define _DEVINFO_CAL_CRC_SHIFT 0 /**< Shift value for CRC */ #define _DEVINFO_CAL_CRC_MASK 0xFFFFUL /**< Bit mask for CRC */ #define _DEVINFO_CAL_TEMP_SHIFT 16 /**< Shift value for TEMP */ #define _DEVINFO_CAL_TEMP_MASK 0xFF0000UL /**< Bit mask for TEMP */ /* Bit fields for DEVINFO MODULEINFO */ #define _DEVINFO_MODULEINFO_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MODULEINFO */ #define _DEVINFO_MODULEINFO_HWREV_SHIFT 0 /**< Shift value for HWREV */ #define _DEVINFO_MODULEINFO_HWREV_MASK 0x1FUL /**< Bit mask for HWREV */ #define _DEVINFO_MODULEINFO_ANTENNA_SHIFT 5 /**< Shift value for ANTENNA */ #define _DEVINFO_MODULEINFO_ANTENNA_MASK 0xE0UL /**< Bit mask for ANTENNA */ #define _DEVINFO_MODULEINFO_ANTENNA_BUILTIN 0x00000000UL /**< Mode BUILTIN for DEVINFO_MODULEINFO */ #define _DEVINFO_MODULEINFO_ANTENNA_CONNECTOR 0x00000001UL /**< Mode CONNECTOR for DEVINFO_MODULEINFO */ #define _DEVINFO_MODULEINFO_ANTENNA_RFPAD 0x00000002UL /**< Mode RFPAD for DEVINFO_MODULEINFO */ #define DEVINFO_MODULEINFO_ANTENNA_BUILTIN (_DEVINFO_MODULEINFO_ANTENNA_BUILTIN << 5) /**< Shifted mode BUILTIN for DEVINFO_MODULEINFO */ #define DEVINFO_MODULEINFO_ANTENNA_CONNECTOR (_DEVINFO_MODULEINFO_ANTENNA_CONNECTOR << 5) /**< Shifted mode CONNECTOR for DEVINFO_MODULEINFO */ #define DEVINFO_MODULEINFO_ANTENNA_RFPAD (_DEVINFO_MODULEINFO_ANTENNA_RFPAD << 5) /**< Shifted mode RFPAD for DEVINFO_MODULEINFO */ #define _DEVINFO_MODULEINFO_MODNUMBER_SHIFT 8 /**< Shift value for MODNUMBER */ #define _DEVINFO_MODULEINFO_MODNUMBER_MASK 0x7F00UL /**< Bit mask for MODNUMBER */ #define _DEVINFO_MODULEINFO_TYPE_SHIFT 15 /**< Shift value for TYPE */ #define _DEVINFO_MODULEINFO_TYPE_MASK 0x8000UL /**< Bit mask for TYPE */ #define _DEVINFO_MODULEINFO_TYPE_PCB 0x00000000UL /**< Mode PCB for DEVINFO_MODULEINFO */ #define _DEVINFO_MODULEINFO_TYPE_SIP 0x00000001UL /**< Mode SIP for DEVINFO_MODULEINFO */ #define DEVINFO_MODULEINFO_TYPE_PCB (_DEVINFO_MODULEINFO_TYPE_PCB << 15) /**< Shifted mode PCB for DEVINFO_MODULEINFO */ #define DEVINFO_MODULEINFO_TYPE_SIP (_DEVINFO_MODULEINFO_TYPE_SIP << 15) /**< Shifted mode SIP for DEVINFO_MODULEINFO */ #define _DEVINFO_MODULEINFO_LFXO_SHIFT 16 /**< Shift value for LFXO */ #define _DEVINFO_MODULEINFO_LFXO_MASK 0x10000UL /**< Bit mask for LFXO */ #define _DEVINFO_MODULEINFO_LFXO_NONE 0x00000000UL /**< Mode NONE for DEVINFO_MODULEINFO */ #define _DEVINFO_MODULEINFO_LFXO_PRESENT 0x00000001UL /**< Mode PRESENT for DEVINFO_MODULEINFO */ #define DEVINFO_MODULEINFO_LFXO_NONE (_DEVINFO_MODULEINFO_LFXO_NONE << 16) /**< Shifted mode NONE for DEVINFO_MODULEINFO */ #define DEVINFO_MODULEINFO_LFXO_PRESENT (_DEVINFO_MODULEINFO_LFXO_PRESENT << 16) /**< Shifted mode PRESENT for DEVINFO_MODULEINFO */ #define _DEVINFO_MODULEINFO_EXPRESS_SHIFT 17 /**< Shift value for EXPRESS */ #define _DEVINFO_MODULEINFO_EXPRESS_MASK 0x20000UL /**< Bit mask for EXPRESS */ #define _DEVINFO_MODULEINFO_EXPRESS_SUPPORTED 0x00000000UL /**< Mode SUPPORTED for DEVINFO_MODULEINFO */ #define _DEVINFO_MODULEINFO_EXPRESS_NONE 0x00000001UL /**< Mode NONE for DEVINFO_MODULEINFO */ #define DEVINFO_MODULEINFO_EXPRESS_SUPPORTED (_DEVINFO_MODULEINFO_EXPRESS_SUPPORTED << 17) /**< Shifted mode SUPPORTED for DEVINFO_MODULEINFO */ #define DEVINFO_MODULEINFO_EXPRESS_NONE (_DEVINFO_MODULEINFO_EXPRESS_NONE << 17) /**< Shifted mode NONE for DEVINFO_MODULEINFO */ #define _DEVINFO_MODULEINFO_LFXOCALVAL_SHIFT 18 /**< Shift value for LFXOCALVAL */ #define _DEVINFO_MODULEINFO_LFXOCALVAL_MASK 0x40000UL /**< Bit mask for LFXOCALVAL */ #define _DEVINFO_MODULEINFO_LFXOCALVAL_VALID 0x00000000UL /**< Mode VALID for DEVINFO_MODULEINFO */ #define _DEVINFO_MODULEINFO_LFXOCALVAL_NOTVALID 0x00000001UL /**< Mode NOTVALID for DEVINFO_MODULEINFO */ #define DEVINFO_MODULEINFO_LFXOCALVAL_VALID (_DEVINFO_MODULEINFO_LFXOCALVAL_VALID << 18) /**< Shifted mode VALID for DEVINFO_MODULEINFO */ #define DEVINFO_MODULEINFO_LFXOCALVAL_NOTVALID (_DEVINFO_MODULEINFO_LFXOCALVAL_NOTVALID << 18) /**< Shifted mode NOTVALID for DEVINFO_MODULEINFO */ #define _DEVINFO_MODULEINFO_HFXOCALVAL_SHIFT 19 /**< Shift value for HFXOCALVAL */ #define _DEVINFO_MODULEINFO_HFXOCALVAL_MASK 0x80000UL /**< Bit mask for HFXOCALVAL */ #define _DEVINFO_MODULEINFO_HFXOCALVAL_VALID 0x00000000UL /**< Mode VALID for DEVINFO_MODULEINFO */ #define _DEVINFO_MODULEINFO_HFXOCALVAL_NOTVALID 0x00000001UL /**< Mode NOTVALID for DEVINFO_MODULEINFO */ #define DEVINFO_MODULEINFO_HFXOCALVAL_VALID (_DEVINFO_MODULEINFO_HFXOCALVAL_VALID << 19) /**< Shifted mode VALID for DEVINFO_MODULEINFO */ #define DEVINFO_MODULEINFO_HFXOCALVAL_NOTVALID (_DEVINFO_MODULEINFO_HFXOCALVAL_NOTVALID << 19) /**< Shifted mode NOTVALID for DEVINFO_MODULEINFO */ #define _DEVINFO_MODULEINFO_RESERVED1_SHIFT 20 /**< Shift value for RESERVED1 */ #define _DEVINFO_MODULEINFO_RESERVED1_MASK 0xFFF00000UL /**< Bit mask for RESERVED1 */ /* Bit fields for DEVINFO MODXOCAL */ #define _DEVINFO_MODXOCAL_MASK 0x0000FFFFUL /**< Mask for DEVINFO_MODXOCAL */ #define _DEVINFO_MODXOCAL_HFXOCTUNE_SHIFT 0 /**< Shift value for HFXOCTUNE */ #define _DEVINFO_MODXOCAL_HFXOCTUNE_MASK 0x1FFUL /**< Bit mask for HFXOCTUNE */ #define _DEVINFO_MODXOCAL_LFXOTUNING_SHIFT 9 /**< Shift value for LFXOTUNING */ #define _DEVINFO_MODXOCAL_LFXOTUNING_MASK 0xFE00UL /**< Bit mask for LFXOTUNING */ /* Bit fields for DEVINFO EXTINFO */ #define _DEVINFO_EXTINFO_MASK 0x00FFFFFFUL /**< Mask for DEVINFO_EXTINFO */ #define _DEVINFO_EXTINFO_TYPE_SHIFT 0 /**< Shift value for TYPE */ #define _DEVINFO_EXTINFO_TYPE_MASK 0xFFUL /**< Bit mask for TYPE */ #define _DEVINFO_EXTINFO_TYPE_IS25LQ040B 0x00000001UL /**< Mode IS25LQ040B for DEVINFO_EXTINFO */ #define _DEVINFO_EXTINFO_TYPE_AT25S041 0x00000002UL /**< Mode AT25S041 for DEVINFO_EXTINFO */ #define _DEVINFO_EXTINFO_TYPE_WF200 0x00000003UL /**< Mode WF200 for DEVINFO_EXTINFO */ #define _DEVINFO_EXTINFO_TYPE_NONE 0x000000FFUL /**< Mode NONE for DEVINFO_EXTINFO */ #define DEVINFO_EXTINFO_TYPE_IS25LQ040B (_DEVINFO_EXTINFO_TYPE_IS25LQ040B << 0) /**< Shifted mode IS25LQ040B for DEVINFO_EXTINFO */ #define DEVINFO_EXTINFO_TYPE_AT25S041 (_DEVINFO_EXTINFO_TYPE_AT25S041 << 0) /**< Shifted mode AT25S041 for DEVINFO_EXTINFO */ #define DEVINFO_EXTINFO_TYPE_WF200 (_DEVINFO_EXTINFO_TYPE_WF200 << 0) /**< Shifted mode WF200 for DEVINFO_EXTINFO */ #define DEVINFO_EXTINFO_TYPE_NONE (_DEVINFO_EXTINFO_TYPE_NONE << 0) /**< Shifted mode NONE for DEVINFO_EXTINFO */ #define _DEVINFO_EXTINFO_CONNECTION_SHIFT 8 /**< Shift value for CONNECTION */ #define _DEVINFO_EXTINFO_CONNECTION_MASK 0xFF00UL /**< Bit mask for CONNECTION */ #define _DEVINFO_EXTINFO_CONNECTION_SPI 0x00000001UL /**< Mode SPI for DEVINFO_EXTINFO */ #define _DEVINFO_EXTINFO_CONNECTION_SDIO 0x00000002UL /**< Mode SDIO for DEVINFO_EXTINFO */ #define _DEVINFO_EXTINFO_CONNECTION_NONE 0x000000FFUL /**< Mode NONE for DEVINFO_EXTINFO */ #define DEVINFO_EXTINFO_CONNECTION_SPI (_DEVINFO_EXTINFO_CONNECTION_SPI << 8) /**< Shifted mode SPI for DEVINFO_EXTINFO */ #define DEVINFO_EXTINFO_CONNECTION_SDIO (_DEVINFO_EXTINFO_CONNECTION_SDIO << 8) /**< Shifted mode SDIO for DEVINFO_EXTINFO */ #define DEVINFO_EXTINFO_CONNECTION_NONE (_DEVINFO_EXTINFO_CONNECTION_NONE << 8) /**< Shifted mode NONE for DEVINFO_EXTINFO */ #define _DEVINFO_EXTINFO_REV_SHIFT 16 /**< Shift value for REV */ #define _DEVINFO_EXTINFO_REV_MASK 0xFF0000UL /**< Bit mask for REV */ #define _DEVINFO_EXTINFO_REV_REV1 0x00000001UL /**< Mode REV1 for DEVINFO_EXTINFO */ #define _DEVINFO_EXTINFO_REV_NONE 0x000000FFUL /**< Mode NONE for DEVINFO_EXTINFO */ #define DEVINFO_EXTINFO_REV_REV1 (_DEVINFO_EXTINFO_REV_REV1 << 16) /**< Shifted mode REV1 for DEVINFO_EXTINFO */ #define DEVINFO_EXTINFO_REV_NONE (_DEVINFO_EXTINFO_REV_NONE << 16) /**< Shifted mode NONE for DEVINFO_EXTINFO */ /* Bit fields for DEVINFO EUI48L */ #define _DEVINFO_EUI48L_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_EUI48L */ #define _DEVINFO_EUI48L_UNIQUEID_SHIFT 0 /**< Shift value for UNIQUEID */ #define _DEVINFO_EUI48L_UNIQUEID_MASK 0xFFFFFFUL /**< Bit mask for UNIQUEID */ #define _DEVINFO_EUI48L_OUI48L_SHIFT 24 /**< Shift value for OUI48L */ #define _DEVINFO_EUI48L_OUI48L_MASK 0xFF000000UL /**< Bit mask for OUI48L */ /* Bit fields for DEVINFO EUI48H */ #define _DEVINFO_EUI48H_MASK 0x0000FFFFUL /**< Mask for DEVINFO_EUI48H */ #define _DEVINFO_EUI48H_OUI48H_SHIFT 0 /**< Shift value for OUI48H */ #define _DEVINFO_EUI48H_OUI48H_MASK 0xFFFFUL /**< Bit mask for OUI48H */ /* Bit fields for DEVINFO CUSTOMINFO */ #define _DEVINFO_CUSTOMINFO_MASK 0xFFFF0000UL /**< Mask for DEVINFO_CUSTOMINFO */ #define _DEVINFO_CUSTOMINFO_PARTNO_SHIFT 16 /**< Shift value for PARTNO */ #define _DEVINFO_CUSTOMINFO_PARTNO_MASK 0xFFFF0000UL /**< Bit mask for PARTNO */ /* Bit fields for DEVINFO MEMINFO */ #define _DEVINFO_MEMINFO_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MEMINFO */ #define _DEVINFO_MEMINFO_TEMPGRADE_SHIFT 0 /**< Shift value for TEMPGRADE */ #define _DEVINFO_MEMINFO_TEMPGRADE_MASK 0xFFUL /**< Bit mask for TEMPGRADE */ #define _DEVINFO_MEMINFO_TEMPGRADE_N40TO85 0x00000000UL /**< Mode N40TO85 for DEVINFO_MEMINFO */ #define _DEVINFO_MEMINFO_TEMPGRADE_N40TO125 0x00000001UL /**< Mode N40TO125 for DEVINFO_MEMINFO */ #define _DEVINFO_MEMINFO_TEMPGRADE_N40TO105 0x00000002UL /**< Mode N40TO105 for DEVINFO_MEMINFO */ #define _DEVINFO_MEMINFO_TEMPGRADE_N0TO70 0x00000003UL /**< Mode N0TO70 for DEVINFO_MEMINFO */ #define DEVINFO_MEMINFO_TEMPGRADE_N40TO85 (_DEVINFO_MEMINFO_TEMPGRADE_N40TO85 << 0) /**< Shifted mode N40TO85 for DEVINFO_MEMINFO */ #define DEVINFO_MEMINFO_TEMPGRADE_N40TO125 (_DEVINFO_MEMINFO_TEMPGRADE_N40TO125 << 0) /**< Shifted mode N40TO125 for DEVINFO_MEMINFO */ #define DEVINFO_MEMINFO_TEMPGRADE_N40TO105 (_DEVINFO_MEMINFO_TEMPGRADE_N40TO105 << 0) /**< Shifted mode N40TO105 for DEVINFO_MEMINFO */ #define DEVINFO_MEMINFO_TEMPGRADE_N0TO70 (_DEVINFO_MEMINFO_TEMPGRADE_N0TO70 << 0) /**< Shifted mode N0TO70 for DEVINFO_MEMINFO */ #define _DEVINFO_MEMINFO_PKGTYPE_SHIFT 8 /**< Shift value for PKGTYPE */ #define _DEVINFO_MEMINFO_PKGTYPE_MASK 0xFF00UL /**< Bit mask for PKGTYPE */ #define _DEVINFO_MEMINFO_PKGTYPE_WLCSP 0x0000004AUL /**< Mode WLCSP for DEVINFO_MEMINFO */ #define _DEVINFO_MEMINFO_PKGTYPE_BGA 0x0000004CUL /**< Mode BGA for DEVINFO_MEMINFO */ #define _DEVINFO_MEMINFO_PKGTYPE_QFN 0x0000004DUL /**< Mode QFN for DEVINFO_MEMINFO */ #define _DEVINFO_MEMINFO_PKGTYPE_QFP 0x00000051UL /**< Mode QFP for DEVINFO_MEMINFO */ #define DEVINFO_MEMINFO_PKGTYPE_WLCSP (_DEVINFO_MEMINFO_PKGTYPE_WLCSP << 8) /**< Shifted mode WLCSP for DEVINFO_MEMINFO */ #define DEVINFO_MEMINFO_PKGTYPE_BGA (_DEVINFO_MEMINFO_PKGTYPE_BGA << 8) /**< Shifted mode BGA for DEVINFO_MEMINFO */ #define DEVINFO_MEMINFO_PKGTYPE_QFN (_DEVINFO_MEMINFO_PKGTYPE_QFN << 8) /**< Shifted mode QFN for DEVINFO_MEMINFO */ #define DEVINFO_MEMINFO_PKGTYPE_QFP (_DEVINFO_MEMINFO_PKGTYPE_QFP << 8) /**< Shifted mode QFP for DEVINFO_MEMINFO */ #define _DEVINFO_MEMINFO_PINCOUNT_SHIFT 16 /**< Shift value for PINCOUNT */ #define _DEVINFO_MEMINFO_PINCOUNT_MASK 0xFF0000UL /**< Bit mask for PINCOUNT */ #define _DEVINFO_MEMINFO_FLASH_PAGE_SIZE_SHIFT 24 /**< Shift value for FLASH_PAGE_SIZE */ #define _DEVINFO_MEMINFO_FLASH_PAGE_SIZE_MASK 0xFF000000UL /**< Bit mask for FLASH_PAGE_SIZE */ /* Bit fields for DEVINFO UNIQUEL */ #define _DEVINFO_UNIQUEL_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_UNIQUEL */ #define _DEVINFO_UNIQUEL_UNIQUEL_SHIFT 0 /**< Shift value for UNIQUEL */ #define _DEVINFO_UNIQUEL_UNIQUEL_MASK 0xFFFFFFFFUL /**< Bit mask for UNIQUEL */ /* Bit fields for DEVINFO UNIQUEH */ #define _DEVINFO_UNIQUEH_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_UNIQUEH */ #define _DEVINFO_UNIQUEH_UNIQUEH_SHIFT 0 /**< Shift value for UNIQUEH */ #define _DEVINFO_UNIQUEH_UNIQUEH_MASK 0xFFFFFFFFUL /**< Bit mask for UNIQUEH */ /* Bit fields for DEVINFO MSIZE */ #define _DEVINFO_MSIZE_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MSIZE */ #define _DEVINFO_MSIZE_FLASH_SHIFT 0 /**< Shift value for FLASH */ #define _DEVINFO_MSIZE_FLASH_MASK 0xFFFFUL /**< Bit mask for FLASH */ #define _DEVINFO_MSIZE_SRAM_SHIFT 16 /**< Shift value for SRAM */ #define _DEVINFO_MSIZE_SRAM_MASK 0xFFFF0000UL /**< Bit mask for SRAM */ /* Bit fields for DEVINFO PART */ #define _DEVINFO_PART_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_PART */ #define _DEVINFO_PART_DEVICE_NUMBER_SHIFT 0 /**< Shift value for DEVICE_NUMBER */ #define _DEVINFO_PART_DEVICE_NUMBER_MASK 0xFFFFUL /**< Bit mask for DEVICE_NUMBER */ #define _DEVINFO_PART_DEVICE_FAMILY_SHIFT 16 /**< Shift value for DEVICE_FAMILY */ #define _DEVINFO_PART_DEVICE_FAMILY_MASK 0xFF0000UL /**< Bit mask for DEVICE_FAMILY */ #define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1P 0x00000010UL /**< Mode EFR32MG1P for DEVINFO_PART */ #define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1B 0x00000011UL /**< Mode EFR32MG1B for DEVINFO_PART */ #define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1V 0x00000012UL /**< Mode EFR32MG1V for DEVINFO_PART */ #define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1P 0x00000013UL /**< Mode EFR32BG1P for DEVINFO_PART */ #define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1B 0x00000014UL /**< Mode EFR32BG1B for DEVINFO_PART */ #define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1V 0x00000015UL /**< Mode EFR32BG1V for DEVINFO_PART */ #define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1P 0x00000019UL /**< Mode EFR32FG1P for DEVINFO_PART */ #define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1B 0x0000001AUL /**< Mode EFR32FG1B for DEVINFO_PART */ #define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1V 0x0000001BUL /**< Mode EFR32FG1V for DEVINFO_PART */ #define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG12P 0x0000001CUL /**< Mode EFR32MG12P for DEVINFO_PART */ #define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG12B 0x0000001DUL /**< Mode EFR32MG12B for DEVINFO_PART */ #define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG12V 0x0000001EUL /**< Mode EFR32MG12V for DEVINFO_PART */ #define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG12P 0x0000001FUL /**< Mode EFR32BG12P for DEVINFO_PART */ #define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG12B 0x00000020UL /**< Mode EFR32BG12B for DEVINFO_PART */ #define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG12V 0x00000021UL /**< Mode EFR32BG12V for DEVINFO_PART */ #define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG12P 0x00000025UL /**< Mode EFR32FG12P for DEVINFO_PART */ #define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG12B 0x00000026UL /**< Mode EFR32FG12B for DEVINFO_PART */ #define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG12V 0x00000027UL /**< Mode EFR32FG12V for DEVINFO_PART */ #define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG13P 0x00000028UL /**< Mode EFR32MG13P for DEVINFO_PART */ #define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG13B 0x00000029UL /**< Mode EFR32MG13B for DEVINFO_PART */ #define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG13V 0x0000002AUL /**< Mode EFR32MG13V for DEVINFO_PART */ #define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG13P 0x0000002BUL /**< Mode EFR32BG13P for DEVINFO_PART */ #define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG13B 0x0000002CUL /**< Mode EFR32BG13B for DEVINFO_PART */ #define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG13V 0x0000002DUL /**< Mode EFR32BG13V for DEVINFO_PART */ #define _DEVINFO_PART_DEVICE_FAMILY_EFR32ZG13P 0x0000002EUL /**< Mode EFR32ZG13P for DEVINFO_PART */ #define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG13P 0x00000031UL /**< Mode EFR32FG13P for DEVINFO_PART */ #define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG13B 0x00000032UL /**< Mode EFR32FG13B for DEVINFO_PART */ #define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG13V 0x00000033UL /**< Mode EFR32FG13V for DEVINFO_PART */ #define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG14P 0x00000034UL /**< Mode EFR32MG14P for DEVINFO_PART */ #define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG14B 0x00000035UL /**< Mode EFR32MG14B for DEVINFO_PART */ #define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG14V 0x00000036UL /**< Mode EFR32MG14V for DEVINFO_PART */ #define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG14P 0x00000037UL /**< Mode EFR32BG14P for DEVINFO_PART */ #define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG14B 0x00000038UL /**< Mode EFR32BG14B for DEVINFO_PART */ #define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG14V 0x00000039UL /**< Mode EFR32BG14V for DEVINFO_PART */ #define _DEVINFO_PART_DEVICE_FAMILY_EFR32ZG14P 0x0000003AUL /**< Mode EFR32ZG14P for DEVINFO_PART */ #define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG14P 0x0000003DUL /**< Mode EFR32FG14P for DEVINFO_PART */ #define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG14B 0x0000003EUL /**< Mode EFR32FG14B for DEVINFO_PART */ #define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG14V 0x0000003FUL /**< Mode EFR32FG14V for DEVINFO_PART */ #define _DEVINFO_PART_DEVICE_FAMILY_EFM32G 0x00000047UL /**< Mode EFM32G for DEVINFO_PART */ #define _DEVINFO_PART_DEVICE_FAMILY_G 0x00000047UL /**< Mode G for DEVINFO_PART */ #define _DEVINFO_PART_DEVICE_FAMILY_EFM32GG 0x00000048UL /**< Mode EFM32GG for DEVINFO_PART */ #define _DEVINFO_PART_DEVICE_FAMILY_GG 0x00000048UL /**< Mode GG for DEVINFO_PART */ #define _DEVINFO_PART_DEVICE_FAMILY_TG 0x00000049UL /**< Mode TG for DEVINFO_PART */ #define _DEVINFO_PART_DEVICE_FAMILY_EFM32TG 0x00000049UL /**< Mode EFM32TG for DEVINFO_PART */ #define _DEVINFO_PART_DEVICE_FAMILY_EFM32LG 0x0000004AUL /**< Mode EFM32LG for DEVINFO_PART */ #define _DEVINFO_PART_DEVICE_FAMILY_LG 0x0000004AUL /**< Mode LG for DEVINFO_PART */ #define _DEVINFO_PART_DEVICE_FAMILY_EFM32WG 0x0000004BUL /**< Mode EFM32WG for DEVINFO_PART */ #define _DEVINFO_PART_DEVICE_FAMILY_WG 0x0000004BUL /**< Mode WG for DEVINFO_PART */ #define _DEVINFO_PART_DEVICE_FAMILY_ZG 0x0000004CUL /**< Mode ZG for DEVINFO_PART */ #define _DEVINFO_PART_DEVICE_FAMILY_EFM32ZG 0x0000004CUL /**< Mode EFM32ZG for DEVINFO_PART */ #define _DEVINFO_PART_DEVICE_FAMILY_HG 0x0000004DUL /**< Mode HG for DEVINFO_PART */ #define _DEVINFO_PART_DEVICE_FAMILY_EFM32HG 0x0000004DUL /**< Mode EFM32HG for DEVINFO_PART */ #define _DEVINFO_PART_DEVICE_FAMILY_EFM32PG1B 0x00000051UL /**< Mode EFM32PG1B for DEVINFO_PART */ #define _DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B 0x00000053UL /**< Mode EFM32JG1B for DEVINFO_PART */ #define _DEVINFO_PART_DEVICE_FAMILY_EFM32PG12B 0x00000055UL /**< Mode EFM32PG12B for DEVINFO_PART */ #define _DEVINFO_PART_DEVICE_FAMILY_EFM32JG12B 0x00000057UL /**< Mode EFM32JG12B for DEVINFO_PART */ #define _DEVINFO_PART_DEVICE_FAMILY_EFM32GG11B 0x00000064UL /**< Mode EFM32GG11B for DEVINFO_PART */ #define _DEVINFO_PART_DEVICE_FAMILY_EFM32TG11B 0x00000067UL /**< Mode EFM32TG11B for DEVINFO_PART */ #define _DEVINFO_PART_DEVICE_FAMILY_EFM32GG12B 0x0000006AUL /**< Mode EFM32GG12B for DEVINFO_PART */ #define _DEVINFO_PART_DEVICE_FAMILY_EZR32LG 0x00000078UL /**< Mode EZR32LG for DEVINFO_PART */ #define _DEVINFO_PART_DEVICE_FAMILY_EZR32WG 0x00000079UL /**< Mode EZR32WG for DEVINFO_PART */ #define _DEVINFO_PART_DEVICE_FAMILY_EZR32HG 0x0000007AUL /**< Mode EZR32HG for DEVINFO_PART */ #define DEVINFO_PART_DEVICE_FAMILY_EFR32MG1P (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG1P << 16) /**< Shifted mode EFR32MG1P for DEVINFO_PART */ #define DEVINFO_PART_DEVICE_FAMILY_EFR32MG1B (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG1B << 16) /**< Shifted mode EFR32MG1B for DEVINFO_PART */ #define DEVINFO_PART_DEVICE_FAMILY_EFR32MG1V (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG1V << 16) /**< Shifted mode EFR32MG1V for DEVINFO_PART */ #define DEVINFO_PART_DEVICE_FAMILY_EFR32BG1P (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG1P << 16) /**< Shifted mode EFR32BG1P for DEVINFO_PART */ #define DEVINFO_PART_DEVICE_FAMILY_EFR32BG1B (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG1B << 16) /**< Shifted mode EFR32BG1B for DEVINFO_PART */ #define DEVINFO_PART_DEVICE_FAMILY_EFR32BG1V (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG1V << 16) /**< Shifted mode EFR32BG1V for DEVINFO_PART */ #define DEVINFO_PART_DEVICE_FAMILY_EFR32FG1P (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG1P << 16) /**< Shifted mode EFR32FG1P for DEVINFO_PART */ #define DEVINFO_PART_DEVICE_FAMILY_EFR32FG1B (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG1B << 16) /**< Shifted mode EFR32FG1B for DEVINFO_PART */ #define DEVINFO_PART_DEVICE_FAMILY_EFR32FG1V (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG1V << 16) /**< Shifted mode EFR32FG1V for DEVINFO_PART */ #define DEVINFO_PART_DEVICE_FAMILY_EFR32MG12P (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG12P << 16) /**< Shifted mode EFR32MG12P for DEVINFO_PART */ #define DEVINFO_PART_DEVICE_FAMILY_EFR32MG12B (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG12B << 16) /**< Shifted mode EFR32MG12B for DEVINFO_PART */ #define DEVINFO_PART_DEVICE_FAMILY_EFR32MG12V (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG12V << 16) /**< Shifted mode EFR32MG12V for DEVINFO_PART */ #define DEVINFO_PART_DEVICE_FAMILY_EFR32BG12P (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG12P << 16) /**< Shifted mode EFR32BG12P for DEVINFO_PART */ #define DEVINFO_PART_DEVICE_FAMILY_EFR32BG12B (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG12B << 16) /**< Shifted mode EFR32BG12B for DEVINFO_PART */ #define DEVINFO_PART_DEVICE_FAMILY_EFR32BG12V (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG12V << 16) /**< Shifted mode EFR32BG12V for DEVINFO_PART */ #define DEVINFO_PART_DEVICE_FAMILY_EFR32FG12P (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG12P << 16) /**< Shifted mode EFR32FG12P for DEVINFO_PART */ #define DEVINFO_PART_DEVICE_FAMILY_EFR32FG12B (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG12B << 16) /**< Shifted mode EFR32FG12B for DEVINFO_PART */ #define DEVINFO_PART_DEVICE_FAMILY_EFR32FG12V (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG12V << 16) /**< Shifted mode EFR32FG12V for DEVINFO_PART */ #define DEVINFO_PART_DEVICE_FAMILY_EFR32MG13P (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG13P << 16) /**< Shifted mode EFR32MG13P for DEVINFO_PART */ #define DEVINFO_PART_DEVICE_FAMILY_EFR32MG13B (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG13B << 16) /**< Shifted mode EFR32MG13B for DEVINFO_PART */ #define DEVINFO_PART_DEVICE_FAMILY_EFR32MG13V (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG13V << 16) /**< Shifted mode EFR32MG13V for DEVINFO_PART */ #define DEVINFO_PART_DEVICE_FAMILY_EFR32BG13P (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG13P << 16) /**< Shifted mode EFR32BG13P for DEVINFO_PART */ #define DEVINFO_PART_DEVICE_FAMILY_EFR32BG13B (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG13B << 16) /**< Shifted mode EFR32BG13B for DEVINFO_PART */ #define DEVINFO_PART_DEVICE_FAMILY_EFR32BG13V (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG13V << 16) /**< Shifted mode EFR32BG13V for DEVINFO_PART */ #define DEVINFO_PART_DEVICE_FAMILY_EFR32ZG13P (_DEVINFO_PART_DEVICE_FAMILY_EFR32ZG13P << 16) /**< Shifted mode EFR32ZG13P for DEVINFO_PART */ #define DEVINFO_PART_DEVICE_FAMILY_EFR32FG13P (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG13P << 16) /**< Shifted mode EFR32FG13P for DEVINFO_PART */ #define DEVINFO_PART_DEVICE_FAMILY_EFR32FG13B (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG13B << 16) /**< Shifted mode EFR32FG13B for DEVINFO_PART */ #define DEVINFO_PART_DEVICE_FAMILY_EFR32FG13V (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG13V << 16) /**< Shifted mode EFR32FG13V for DEVINFO_PART */ #define DEVINFO_PART_DEVICE_FAMILY_EFR32MG14P (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG14P << 16) /**< Shifted mode EFR32MG14P for DEVINFO_PART */ #define DEVINFO_PART_DEVICE_FAMILY_EFR32MG14B (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG14B << 16) /**< Shifted mode EFR32MG14B for DEVINFO_PART */ #define DEVINFO_PART_DEVICE_FAMILY_EFR32MG14V (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG14V << 16) /**< Shifted mode EFR32MG14V for DEVINFO_PART */ #define DEVINFO_PART_DEVICE_FAMILY_EFR32BG14P (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG14P << 16) /**< Shifted mode EFR32BG14P for DEVINFO_PART */ #define DEVINFO_PART_DEVICE_FAMILY_EFR32BG14B (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG14B << 16) /**< Shifted mode EFR32BG14B for DEVINFO_PART */ #define DEVINFO_PART_DEVICE_FAMILY_EFR32BG14V (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG14V << 16) /**< Shifted mode EFR32BG14V for DEVINFO_PART */ #define DEVINFO_PART_DEVICE_FAMILY_EFR32ZG14P (_DEVINFO_PART_DEVICE_FAMILY_EFR32ZG14P << 16) /**< Shifted mode EFR32ZG14P for DEVINFO_PART */ #define DEVINFO_PART_DEVICE_FAMILY_EFR32FG14P (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG14P << 16) /**< Shifted mode EFR32FG14P for DEVINFO_PART */ #define DEVINFO_PART_DEVICE_FAMILY_EFR32FG14B (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG14B << 16) /**< Shifted mode EFR32FG14B for DEVINFO_PART */ #define DEVINFO_PART_DEVICE_FAMILY_EFR32FG14V (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG14V << 16) /**< Shifted mode EFR32FG14V for DEVINFO_PART */ #define DEVINFO_PART_DEVICE_FAMILY_EFM32G (_DEVINFO_PART_DEVICE_FAMILY_EFM32G << 16) /**< Shifted mode EFM32G for DEVINFO_PART */ #define DEVINFO_PART_DEVICE_FAMILY_G (_DEVINFO_PART_DEVICE_FAMILY_G << 16) /**< Shifted mode G for DEVINFO_PART */ #define DEVINFO_PART_DEVICE_FAMILY_EFM32GG (_DEVINFO_PART_DEVICE_FAMILY_EFM32GG << 16) /**< Shifted mode EFM32GG for DEVINFO_PART */ #define DEVINFO_PART_DEVICE_FAMILY_GG (_DEVINFO_PART_DEVICE_FAMILY_GG << 16) /**< Shifted mode GG for DEVINFO_PART */ #define DEVINFO_PART_DEVICE_FAMILY_TG (_DEVINFO_PART_DEVICE_FAMILY_TG << 16) /**< Shifted mode TG for DEVINFO_PART */ #define DEVINFO_PART_DEVICE_FAMILY_EFM32TG (_DEVINFO_PART_DEVICE_FAMILY_EFM32TG << 16) /**< Shifted mode EFM32TG for DEVINFO_PART */ #define DEVINFO_PART_DEVICE_FAMILY_EFM32LG (_DEVINFO_PART_DEVICE_FAMILY_EFM32LG << 16) /**< Shifted mode EFM32LG for DEVINFO_PART */ #define DEVINFO_PART_DEVICE_FAMILY_LG (_DEVINFO_PART_DEVICE_FAMILY_LG << 16) /**< Shifted mode LG for DEVINFO_PART */ #define DEVINFO_PART_DEVICE_FAMILY_EFM32WG (_DEVINFO_PART_DEVICE_FAMILY_EFM32WG << 16) /**< Shifted mode EFM32WG for DEVINFO_PART */ #define DEVINFO_PART_DEVICE_FAMILY_WG (_DEVINFO_PART_DEVICE_FAMILY_WG << 16) /**< Shifted mode WG for DEVINFO_PART */ #define DEVINFO_PART_DEVICE_FAMILY_ZG (_DEVINFO_PART_DEVICE_FAMILY_ZG << 16) /**< Shifted mode ZG for DEVINFO_PART */ #define DEVINFO_PART_DEVICE_FAMILY_EFM32ZG (_DEVINFO_PART_DEVICE_FAMILY_EFM32ZG << 16) /**< Shifted mode EFM32ZG for DEVINFO_PART */ #define DEVINFO_PART_DEVICE_FAMILY_HG (_DEVINFO_PART_DEVICE_FAMILY_HG << 16) /**< Shifted mode HG for DEVINFO_PART */ #define DEVINFO_PART_DEVICE_FAMILY_EFM32HG (_DEVINFO_PART_DEVICE_FAMILY_EFM32HG << 16) /**< Shifted mode EFM32HG for DEVINFO_PART */ #define DEVINFO_PART_DEVICE_FAMILY_EFM32PG1B (_DEVINFO_PART_DEVICE_FAMILY_EFM32PG1B << 16) /**< Shifted mode EFM32PG1B for DEVINFO_PART */ #define DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B (_DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B << 16) /**< Shifted mode EFM32JG1B for DEVINFO_PART */ #define DEVINFO_PART_DEVICE_FAMILY_EFM32PG12B (_DEVINFO_PART_DEVICE_FAMILY_EFM32PG12B << 16) /**< Shifted mode EFM32PG12B for DEVINFO_PART */ #define DEVINFO_PART_DEVICE_FAMILY_EFM32JG12B (_DEVINFO_PART_DEVICE_FAMILY_EFM32JG12B << 16) /**< Shifted mode EFM32JG12B for DEVINFO_PART */ #define DEVINFO_PART_DEVICE_FAMILY_EFM32GG11B (_DEVINFO_PART_DEVICE_FAMILY_EFM32GG11B << 16) /**< Shifted mode EFM32GG11B for DEVINFO_PART */ #define DEVINFO_PART_DEVICE_FAMILY_EFM32TG11B (_DEVINFO_PART_DEVICE_FAMILY_EFM32TG11B << 16) /**< Shifted mode EFM32TG11B for DEVINFO_PART */ #define DEVINFO_PART_DEVICE_FAMILY_EFM32GG12B (_DEVINFO_PART_DEVICE_FAMILY_EFM32GG12B << 16) /**< Shifted mode EFM32GG12B for DEVINFO_PART */ #define DEVINFO_PART_DEVICE_FAMILY_EZR32LG (_DEVINFO_PART_DEVICE_FAMILY_EZR32LG << 16) /**< Shifted mode EZR32LG for DEVINFO_PART */ #define DEVINFO_PART_DEVICE_FAMILY_EZR32WG (_DEVINFO_PART_DEVICE_FAMILY_EZR32WG << 16) /**< Shifted mode EZR32WG for DEVINFO_PART */ #define DEVINFO_PART_DEVICE_FAMILY_EZR32HG (_DEVINFO_PART_DEVICE_FAMILY_EZR32HG << 16) /**< Shifted mode EZR32HG for DEVINFO_PART */ #define _DEVINFO_PART_PROD_REV_SHIFT 24 /**< Shift value for PROD_REV */ #define _DEVINFO_PART_PROD_REV_MASK 0xFF000000UL /**< Bit mask for PROD_REV */ /* Bit fields for DEVINFO DEVINFOREV */ #define _DEVINFO_DEVINFOREV_MASK 0x000000FFUL /**< Mask for DEVINFO_DEVINFOREV */ #define _DEVINFO_DEVINFOREV_DEVINFOREV_SHIFT 0 /**< Shift value for DEVINFOREV */ #define _DEVINFO_DEVINFOREV_DEVINFOREV_MASK 0xFFUL /**< Bit mask for DEVINFOREV */ /* Bit fields for DEVINFO EMUTEMP */ #define _DEVINFO_EMUTEMP_MASK 0x000000FFUL /**< Mask for DEVINFO_EMUTEMP */ #define _DEVINFO_EMUTEMP_EMUTEMPROOM_SHIFT 0 /**< Shift value for EMUTEMPROOM */ #define _DEVINFO_EMUTEMP_EMUTEMPROOM_MASK 0xFFUL /**< Bit mask for EMUTEMPROOM */ /* Bit fields for DEVINFO ADC0CAL0 */ #define _DEVINFO_ADC0CAL0_MASK 0x7FFF7FFFUL /**< Mask for DEVINFO_ADC0CAL0 */ #define _DEVINFO_ADC0CAL0_OFFSET1V25_SHIFT 0 /**< Shift value for OFFSET1V25 */ #define _DEVINFO_ADC0CAL0_OFFSET1V25_MASK 0xFUL /**< Bit mask for OFFSET1V25 */ #define _DEVINFO_ADC0CAL0_NEGSEOFFSET1V25_SHIFT 4 /**< Shift value for NEGSEOFFSET1V25 */ #define _DEVINFO_ADC0CAL0_NEGSEOFFSET1V25_MASK 0xF0UL /**< Bit mask for NEGSEOFFSET1V25 */ #define _DEVINFO_ADC0CAL0_GAIN1V25_SHIFT 8 /**< Shift value for GAIN1V25 */ #define _DEVINFO_ADC0CAL0_GAIN1V25_MASK 0x7F00UL /**< Bit mask for GAIN1V25 */ #define _DEVINFO_ADC0CAL0_OFFSET2V5_SHIFT 16 /**< Shift value for OFFSET2V5 */ #define _DEVINFO_ADC0CAL0_OFFSET2V5_MASK 0xF0000UL /**< Bit mask for OFFSET2V5 */ #define _DEVINFO_ADC0CAL0_NEGSEOFFSET2V5_SHIFT 20 /**< Shift value for NEGSEOFFSET2V5 */ #define _DEVINFO_ADC0CAL0_NEGSEOFFSET2V5_MASK 0xF00000UL /**< Bit mask for NEGSEOFFSET2V5 */ #define _DEVINFO_ADC0CAL0_GAIN2V5_SHIFT 24 /**< Shift value for GAIN2V5 */ #define _DEVINFO_ADC0CAL0_GAIN2V5_MASK 0x7F000000UL /**< Bit mask for GAIN2V5 */ /* Bit fields for DEVINFO ADC0CAL1 */ #define _DEVINFO_ADC0CAL1_MASK 0x7FFF7FFFUL /**< Mask for DEVINFO_ADC0CAL1 */ #define _DEVINFO_ADC0CAL1_OFFSETVDD_SHIFT 0 /**< Shift value for OFFSETVDD */ #define _DEVINFO_ADC0CAL1_OFFSETVDD_MASK 0xFUL /**< Bit mask for OFFSETVDD */ #define _DEVINFO_ADC0CAL1_NEGSEOFFSETVDD_SHIFT 4 /**< Shift value for NEGSEOFFSETVDD */ #define _DEVINFO_ADC0CAL1_NEGSEOFFSETVDD_MASK 0xF0UL /**< Bit mask for NEGSEOFFSETVDD */ #define _DEVINFO_ADC0CAL1_GAINVDD_SHIFT 8 /**< Shift value for GAINVDD */ #define _DEVINFO_ADC0CAL1_GAINVDD_MASK 0x7F00UL /**< Bit mask for GAINVDD */ #define _DEVINFO_ADC0CAL1_OFFSET5VDIFF_SHIFT 16 /**< Shift value for OFFSET5VDIFF */ #define _DEVINFO_ADC0CAL1_OFFSET5VDIFF_MASK 0xF0000UL /**< Bit mask for OFFSET5VDIFF */ #define _DEVINFO_ADC0CAL1_NEGSEOFFSET5VDIFF_SHIFT 20 /**< Shift value for NEGSEOFFSET5VDIFF */ #define _DEVINFO_ADC0CAL1_NEGSEOFFSET5VDIFF_MASK 0xF00000UL /**< Bit mask for NEGSEOFFSET5VDIFF */ #define _DEVINFO_ADC0CAL1_GAIN5VDIFF_SHIFT 24 /**< Shift value for GAIN5VDIFF */ #define _DEVINFO_ADC0CAL1_GAIN5VDIFF_MASK 0x7F000000UL /**< Bit mask for GAIN5VDIFF */ /* Bit fields for DEVINFO ADC0CAL2 */ #define _DEVINFO_ADC0CAL2_MASK 0x000000FFUL /**< Mask for DEVINFO_ADC0CAL2 */ #define _DEVINFO_ADC0CAL2_OFFSET2XVDD_SHIFT 0 /**< Shift value for OFFSET2XVDD */ #define _DEVINFO_ADC0CAL2_OFFSET2XVDD_MASK 0xFUL /**< Bit mask for OFFSET2XVDD */ #define _DEVINFO_ADC0CAL2_NEGSEOFFSET2XVDD_SHIFT 4 /**< Shift value for NEGSEOFFSET2XVDD */ #define _DEVINFO_ADC0CAL2_NEGSEOFFSET2XVDD_MASK 0xF0UL /**< Bit mask for NEGSEOFFSET2XVDD */ /* Bit fields for DEVINFO ADC0CAL3 */ #define _DEVINFO_ADC0CAL3_MASK 0x0000FFF0UL /**< Mask for DEVINFO_ADC0CAL3 */ #define _DEVINFO_ADC0CAL3_TEMPREAD1V25_SHIFT 4 /**< Shift value for TEMPREAD1V25 */ #define _DEVINFO_ADC0CAL3_TEMPREAD1V25_MASK 0xFFF0UL /**< Bit mask for TEMPREAD1V25 */ /* Bit fields for DEVINFO HFRCOCAL0 */ #define _DEVINFO_HFRCOCAL0_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL0 */ #define _DEVINFO_HFRCOCAL0_TUNING_SHIFT 0 /**< Shift value for TUNING */ #define _DEVINFO_HFRCOCAL0_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ #define _DEVINFO_HFRCOCAL0_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ #define _DEVINFO_HFRCOCAL0_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ #define _DEVINFO_HFRCOCAL0_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ #define _DEVINFO_HFRCOCAL0_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ #define _DEVINFO_HFRCOCAL0_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ #define _DEVINFO_HFRCOCAL0_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ #define _DEVINFO_HFRCOCAL0_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ #define _DEVINFO_HFRCOCAL0_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ #define _DEVINFO_HFRCOCAL0_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ #define _DEVINFO_HFRCOCAL0_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ #define _DEVINFO_HFRCOCAL0_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ #define _DEVINFO_HFRCOCAL0_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ #define _DEVINFO_HFRCOCAL0_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ #define _DEVINFO_HFRCOCAL0_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ /* Bit fields for DEVINFO HFRCOCAL3 */ #define _DEVINFO_HFRCOCAL3_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL3 */ #define _DEVINFO_HFRCOCAL3_TUNING_SHIFT 0 /**< Shift value for TUNING */ #define _DEVINFO_HFRCOCAL3_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ #define _DEVINFO_HFRCOCAL3_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ #define _DEVINFO_HFRCOCAL3_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ #define _DEVINFO_HFRCOCAL3_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ #define _DEVINFO_HFRCOCAL3_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ #define _DEVINFO_HFRCOCAL3_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ #define _DEVINFO_HFRCOCAL3_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ #define _DEVINFO_HFRCOCAL3_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ #define _DEVINFO_HFRCOCAL3_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ #define _DEVINFO_HFRCOCAL3_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ #define _DEVINFO_HFRCOCAL3_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ #define _DEVINFO_HFRCOCAL3_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ #define _DEVINFO_HFRCOCAL3_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ #define _DEVINFO_HFRCOCAL3_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ #define _DEVINFO_HFRCOCAL3_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ /* Bit fields for DEVINFO HFRCOCAL6 */ #define _DEVINFO_HFRCOCAL6_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL6 */ #define _DEVINFO_HFRCOCAL6_TUNING_SHIFT 0 /**< Shift value for TUNING */ #define _DEVINFO_HFRCOCAL6_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ #define _DEVINFO_HFRCOCAL6_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ #define _DEVINFO_HFRCOCAL6_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ #define _DEVINFO_HFRCOCAL6_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ #define _DEVINFO_HFRCOCAL6_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ #define _DEVINFO_HFRCOCAL6_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ #define _DEVINFO_HFRCOCAL6_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ #define _DEVINFO_HFRCOCAL6_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ #define _DEVINFO_HFRCOCAL6_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ #define _DEVINFO_HFRCOCAL6_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ #define _DEVINFO_HFRCOCAL6_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ #define _DEVINFO_HFRCOCAL6_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ #define _DEVINFO_HFRCOCAL6_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ #define _DEVINFO_HFRCOCAL6_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ #define _DEVINFO_HFRCOCAL6_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ /* Bit fields for DEVINFO HFRCOCAL7 */ #define _DEVINFO_HFRCOCAL7_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL7 */ #define _DEVINFO_HFRCOCAL7_TUNING_SHIFT 0 /**< Shift value for TUNING */ #define _DEVINFO_HFRCOCAL7_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ #define _DEVINFO_HFRCOCAL7_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ #define _DEVINFO_HFRCOCAL7_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ #define _DEVINFO_HFRCOCAL7_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ #define _DEVINFO_HFRCOCAL7_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ #define _DEVINFO_HFRCOCAL7_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ #define _DEVINFO_HFRCOCAL7_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ #define _DEVINFO_HFRCOCAL7_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ #define _DEVINFO_HFRCOCAL7_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ #define _DEVINFO_HFRCOCAL7_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ #define _DEVINFO_HFRCOCAL7_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ #define _DEVINFO_HFRCOCAL7_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ #define _DEVINFO_HFRCOCAL7_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ #define _DEVINFO_HFRCOCAL7_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ #define _DEVINFO_HFRCOCAL7_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ /* Bit fields for DEVINFO HFRCOCAL8 */ #define _DEVINFO_HFRCOCAL8_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL8 */ #define _DEVINFO_HFRCOCAL8_TUNING_SHIFT 0 /**< Shift value for TUNING */ #define _DEVINFO_HFRCOCAL8_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ #define _DEVINFO_HFRCOCAL8_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ #define _DEVINFO_HFRCOCAL8_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ #define _DEVINFO_HFRCOCAL8_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ #define _DEVINFO_HFRCOCAL8_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ #define _DEVINFO_HFRCOCAL8_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ #define _DEVINFO_HFRCOCAL8_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ #define _DEVINFO_HFRCOCAL8_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ #define _DEVINFO_HFRCOCAL8_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ #define _DEVINFO_HFRCOCAL8_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ #define _DEVINFO_HFRCOCAL8_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ #define _DEVINFO_HFRCOCAL8_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ #define _DEVINFO_HFRCOCAL8_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ #define _DEVINFO_HFRCOCAL8_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ #define _DEVINFO_HFRCOCAL8_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ /* Bit fields for DEVINFO HFRCOCAL10 */ #define _DEVINFO_HFRCOCAL10_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL10 */ #define _DEVINFO_HFRCOCAL10_TUNING_SHIFT 0 /**< Shift value for TUNING */ #define _DEVINFO_HFRCOCAL10_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ #define _DEVINFO_HFRCOCAL10_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ #define _DEVINFO_HFRCOCAL10_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ #define _DEVINFO_HFRCOCAL10_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ #define _DEVINFO_HFRCOCAL10_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ #define _DEVINFO_HFRCOCAL10_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ #define _DEVINFO_HFRCOCAL10_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ #define _DEVINFO_HFRCOCAL10_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ #define _DEVINFO_HFRCOCAL10_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ #define _DEVINFO_HFRCOCAL10_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ #define _DEVINFO_HFRCOCAL10_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ #define _DEVINFO_HFRCOCAL10_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ #define _DEVINFO_HFRCOCAL10_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ #define _DEVINFO_HFRCOCAL10_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ #define _DEVINFO_HFRCOCAL10_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ /* Bit fields for DEVINFO HFRCOCAL11 */ #define _DEVINFO_HFRCOCAL11_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL11 */ #define _DEVINFO_HFRCOCAL11_TUNING_SHIFT 0 /**< Shift value for TUNING */ #define _DEVINFO_HFRCOCAL11_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ #define _DEVINFO_HFRCOCAL11_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ #define _DEVINFO_HFRCOCAL11_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ #define _DEVINFO_HFRCOCAL11_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ #define _DEVINFO_HFRCOCAL11_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ #define _DEVINFO_HFRCOCAL11_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ #define _DEVINFO_HFRCOCAL11_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ #define _DEVINFO_HFRCOCAL11_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ #define _DEVINFO_HFRCOCAL11_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ #define _DEVINFO_HFRCOCAL11_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ #define _DEVINFO_HFRCOCAL11_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ #define _DEVINFO_HFRCOCAL11_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ #define _DEVINFO_HFRCOCAL11_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ #define _DEVINFO_HFRCOCAL11_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ #define _DEVINFO_HFRCOCAL11_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ /* Bit fields for DEVINFO HFRCOCAL12 */ #define _DEVINFO_HFRCOCAL12_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL12 */ #define _DEVINFO_HFRCOCAL12_TUNING_SHIFT 0 /**< Shift value for TUNING */ #define _DEVINFO_HFRCOCAL12_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ #define _DEVINFO_HFRCOCAL12_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ #define _DEVINFO_HFRCOCAL12_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ #define _DEVINFO_HFRCOCAL12_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ #define _DEVINFO_HFRCOCAL12_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ #define _DEVINFO_HFRCOCAL12_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ #define _DEVINFO_HFRCOCAL12_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ #define _DEVINFO_HFRCOCAL12_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ #define _DEVINFO_HFRCOCAL12_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ #define _DEVINFO_HFRCOCAL12_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ #define _DEVINFO_HFRCOCAL12_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ #define _DEVINFO_HFRCOCAL12_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ #define _DEVINFO_HFRCOCAL12_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ #define _DEVINFO_HFRCOCAL12_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ #define _DEVINFO_HFRCOCAL12_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ /* Bit fields for DEVINFO AUXHFRCOCAL0 */ #define _DEVINFO_AUXHFRCOCAL0_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL0 */ #define _DEVINFO_AUXHFRCOCAL0_TUNING_SHIFT 0 /**< Shift value for TUNING */ #define _DEVINFO_AUXHFRCOCAL0_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ #define _DEVINFO_AUXHFRCOCAL0_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ #define _DEVINFO_AUXHFRCOCAL0_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ #define _DEVINFO_AUXHFRCOCAL0_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ #define _DEVINFO_AUXHFRCOCAL0_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ #define _DEVINFO_AUXHFRCOCAL0_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ #define _DEVINFO_AUXHFRCOCAL0_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ #define _DEVINFO_AUXHFRCOCAL0_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ #define _DEVINFO_AUXHFRCOCAL0_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ #define _DEVINFO_AUXHFRCOCAL0_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ #define _DEVINFO_AUXHFRCOCAL0_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ #define _DEVINFO_AUXHFRCOCAL0_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ #define _DEVINFO_AUXHFRCOCAL0_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ #define _DEVINFO_AUXHFRCOCAL0_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ #define _DEVINFO_AUXHFRCOCAL0_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ /* Bit fields for DEVINFO AUXHFRCOCAL3 */ #define _DEVINFO_AUXHFRCOCAL3_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL3 */ #define _DEVINFO_AUXHFRCOCAL3_TUNING_SHIFT 0 /**< Shift value for TUNING */ #define _DEVINFO_AUXHFRCOCAL3_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ #define _DEVINFO_AUXHFRCOCAL3_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ #define _DEVINFO_AUXHFRCOCAL3_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ #define _DEVINFO_AUXHFRCOCAL3_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ #define _DEVINFO_AUXHFRCOCAL3_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ #define _DEVINFO_AUXHFRCOCAL3_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ #define _DEVINFO_AUXHFRCOCAL3_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ #define _DEVINFO_AUXHFRCOCAL3_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ #define _DEVINFO_AUXHFRCOCAL3_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ #define _DEVINFO_AUXHFRCOCAL3_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ #define _DEVINFO_AUXHFRCOCAL3_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ #define _DEVINFO_AUXHFRCOCAL3_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ #define _DEVINFO_AUXHFRCOCAL3_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ #define _DEVINFO_AUXHFRCOCAL3_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ #define _DEVINFO_AUXHFRCOCAL3_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ /* Bit fields for DEVINFO AUXHFRCOCAL6 */ #define _DEVINFO_AUXHFRCOCAL6_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL6 */ #define _DEVINFO_AUXHFRCOCAL6_TUNING_SHIFT 0 /**< Shift value for TUNING */ #define _DEVINFO_AUXHFRCOCAL6_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ #define _DEVINFO_AUXHFRCOCAL6_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ #define _DEVINFO_AUXHFRCOCAL6_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ #define _DEVINFO_AUXHFRCOCAL6_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ #define _DEVINFO_AUXHFRCOCAL6_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ #define _DEVINFO_AUXHFRCOCAL6_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ #define _DEVINFO_AUXHFRCOCAL6_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ #define _DEVINFO_AUXHFRCOCAL6_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ #define _DEVINFO_AUXHFRCOCAL6_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ #define _DEVINFO_AUXHFRCOCAL6_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ #define _DEVINFO_AUXHFRCOCAL6_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ #define _DEVINFO_AUXHFRCOCAL6_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ #define _DEVINFO_AUXHFRCOCAL6_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ #define _DEVINFO_AUXHFRCOCAL6_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ #define _DEVINFO_AUXHFRCOCAL6_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ /* Bit fields for DEVINFO AUXHFRCOCAL7 */ #define _DEVINFO_AUXHFRCOCAL7_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL7 */ #define _DEVINFO_AUXHFRCOCAL7_TUNING_SHIFT 0 /**< Shift value for TUNING */ #define _DEVINFO_AUXHFRCOCAL7_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ #define _DEVINFO_AUXHFRCOCAL7_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ #define _DEVINFO_AUXHFRCOCAL7_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ #define _DEVINFO_AUXHFRCOCAL7_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ #define _DEVINFO_AUXHFRCOCAL7_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ #define _DEVINFO_AUXHFRCOCAL7_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ #define _DEVINFO_AUXHFRCOCAL7_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ #define _DEVINFO_AUXHFRCOCAL7_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ #define _DEVINFO_AUXHFRCOCAL7_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ #define _DEVINFO_AUXHFRCOCAL7_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ #define _DEVINFO_AUXHFRCOCAL7_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ #define _DEVINFO_AUXHFRCOCAL7_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ #define _DEVINFO_AUXHFRCOCAL7_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ #define _DEVINFO_AUXHFRCOCAL7_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ #define _DEVINFO_AUXHFRCOCAL7_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ /* Bit fields for DEVINFO AUXHFRCOCAL8 */ #define _DEVINFO_AUXHFRCOCAL8_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL8 */ #define _DEVINFO_AUXHFRCOCAL8_TUNING_SHIFT 0 /**< Shift value for TUNING */ #define _DEVINFO_AUXHFRCOCAL8_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ #define _DEVINFO_AUXHFRCOCAL8_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ #define _DEVINFO_AUXHFRCOCAL8_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ #define _DEVINFO_AUXHFRCOCAL8_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ #define _DEVINFO_AUXHFRCOCAL8_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ #define _DEVINFO_AUXHFRCOCAL8_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ #define _DEVINFO_AUXHFRCOCAL8_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ #define _DEVINFO_AUXHFRCOCAL8_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ #define _DEVINFO_AUXHFRCOCAL8_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ #define _DEVINFO_AUXHFRCOCAL8_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ #define _DEVINFO_AUXHFRCOCAL8_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ #define _DEVINFO_AUXHFRCOCAL8_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ #define _DEVINFO_AUXHFRCOCAL8_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ #define _DEVINFO_AUXHFRCOCAL8_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ #define _DEVINFO_AUXHFRCOCAL8_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ /* Bit fields for DEVINFO AUXHFRCOCAL10 */ #define _DEVINFO_AUXHFRCOCAL10_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL10 */ #define _DEVINFO_AUXHFRCOCAL10_TUNING_SHIFT 0 /**< Shift value for TUNING */ #define _DEVINFO_AUXHFRCOCAL10_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ #define _DEVINFO_AUXHFRCOCAL10_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ #define _DEVINFO_AUXHFRCOCAL10_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ #define _DEVINFO_AUXHFRCOCAL10_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ #define _DEVINFO_AUXHFRCOCAL10_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ #define _DEVINFO_AUXHFRCOCAL10_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ #define _DEVINFO_AUXHFRCOCAL10_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ #define _DEVINFO_AUXHFRCOCAL10_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ #define _DEVINFO_AUXHFRCOCAL10_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ #define _DEVINFO_AUXHFRCOCAL10_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ #define _DEVINFO_AUXHFRCOCAL10_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ #define _DEVINFO_AUXHFRCOCAL10_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ #define _DEVINFO_AUXHFRCOCAL10_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ #define _DEVINFO_AUXHFRCOCAL10_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ #define _DEVINFO_AUXHFRCOCAL10_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ /* Bit fields for DEVINFO AUXHFRCOCAL11 */ #define _DEVINFO_AUXHFRCOCAL11_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL11 */ #define _DEVINFO_AUXHFRCOCAL11_TUNING_SHIFT 0 /**< Shift value for TUNING */ #define _DEVINFO_AUXHFRCOCAL11_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ #define _DEVINFO_AUXHFRCOCAL11_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ #define _DEVINFO_AUXHFRCOCAL11_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ #define _DEVINFO_AUXHFRCOCAL11_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ #define _DEVINFO_AUXHFRCOCAL11_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ #define _DEVINFO_AUXHFRCOCAL11_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ #define _DEVINFO_AUXHFRCOCAL11_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ #define _DEVINFO_AUXHFRCOCAL11_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ #define _DEVINFO_AUXHFRCOCAL11_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ #define _DEVINFO_AUXHFRCOCAL11_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ #define _DEVINFO_AUXHFRCOCAL11_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ #define _DEVINFO_AUXHFRCOCAL11_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ #define _DEVINFO_AUXHFRCOCAL11_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ #define _DEVINFO_AUXHFRCOCAL11_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ #define _DEVINFO_AUXHFRCOCAL11_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ /* Bit fields for DEVINFO AUXHFRCOCAL12 */ #define _DEVINFO_AUXHFRCOCAL12_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL12 */ #define _DEVINFO_AUXHFRCOCAL12_TUNING_SHIFT 0 /**< Shift value for TUNING */ #define _DEVINFO_AUXHFRCOCAL12_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ #define _DEVINFO_AUXHFRCOCAL12_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ #define _DEVINFO_AUXHFRCOCAL12_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ #define _DEVINFO_AUXHFRCOCAL12_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ #define _DEVINFO_AUXHFRCOCAL12_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ #define _DEVINFO_AUXHFRCOCAL12_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ #define _DEVINFO_AUXHFRCOCAL12_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ #define _DEVINFO_AUXHFRCOCAL12_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ #define _DEVINFO_AUXHFRCOCAL12_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ #define _DEVINFO_AUXHFRCOCAL12_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ #define _DEVINFO_AUXHFRCOCAL12_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ #define _DEVINFO_AUXHFRCOCAL12_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ #define _DEVINFO_AUXHFRCOCAL12_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ #define _DEVINFO_AUXHFRCOCAL12_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ #define _DEVINFO_AUXHFRCOCAL12_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ /* Bit fields for DEVINFO VMONCAL0 */ #define _DEVINFO_VMONCAL0_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_VMONCAL0 */ #define _DEVINFO_VMONCAL0_AVDD1V86THRESFINE_SHIFT 0 /**< Shift value for AVDD1V86THRESFINE */ #define _DEVINFO_VMONCAL0_AVDD1V86THRESFINE_MASK 0xFUL /**< Bit mask for AVDD1V86THRESFINE */ #define _DEVINFO_VMONCAL0_AVDD1V86THRESCOARSE_SHIFT 4 /**< Shift value for AVDD1V86THRESCOARSE */ #define _DEVINFO_VMONCAL0_AVDD1V86THRESCOARSE_MASK 0xF0UL /**< Bit mask for AVDD1V86THRESCOARSE */ #define _DEVINFO_VMONCAL0_AVDD2V98THRESFINE_SHIFT 8 /**< Shift value for AVDD2V98THRESFINE */ #define _DEVINFO_VMONCAL0_AVDD2V98THRESFINE_MASK 0xF00UL /**< Bit mask for AVDD2V98THRESFINE */ #define _DEVINFO_VMONCAL0_AVDD2V98THRESCOARSE_SHIFT 12 /**< Shift value for AVDD2V98THRESCOARSE */ #define _DEVINFO_VMONCAL0_AVDD2V98THRESCOARSE_MASK 0xF000UL /**< Bit mask for AVDD2V98THRESCOARSE */ #define _DEVINFO_VMONCAL0_ALTAVDD1V86THRESFINE_SHIFT 16 /**< Shift value for ALTAVDD1V86THRESFINE */ #define _DEVINFO_VMONCAL0_ALTAVDD1V86THRESFINE_MASK 0xF0000UL /**< Bit mask for ALTAVDD1V86THRESFINE */ #define _DEVINFO_VMONCAL0_ALTAVDD1V86THRESCOARSE_SHIFT 20 /**< Shift value for ALTAVDD1V86THRESCOARSE */ #define _DEVINFO_VMONCAL0_ALTAVDD1V86THRESCOARSE_MASK 0xF00000UL /**< Bit mask for ALTAVDD1V86THRESCOARSE */ #define _DEVINFO_VMONCAL0_ALTAVDD2V98THRESFINE_SHIFT 24 /**< Shift value for ALTAVDD2V98THRESFINE */ #define _DEVINFO_VMONCAL0_ALTAVDD2V98THRESFINE_MASK 0xF000000UL /**< Bit mask for ALTAVDD2V98THRESFINE */ #define _DEVINFO_VMONCAL0_ALTAVDD2V98THRESCOARSE_SHIFT 28 /**< Shift value for ALTAVDD2V98THRESCOARSE */ #define _DEVINFO_VMONCAL0_ALTAVDD2V98THRESCOARSE_MASK 0xF0000000UL /**< Bit mask for ALTAVDD2V98THRESCOARSE */ /* Bit fields for DEVINFO VMONCAL1 */ #define _DEVINFO_VMONCAL1_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_VMONCAL1 */ #define _DEVINFO_VMONCAL1_DVDD1V86THRESFINE_SHIFT 0 /**< Shift value for DVDD1V86THRESFINE */ #define _DEVINFO_VMONCAL1_DVDD1V86THRESFINE_MASK 0xFUL /**< Bit mask for DVDD1V86THRESFINE */ #define _DEVINFO_VMONCAL1_DVDD1V86THRESCOARSE_SHIFT 4 /**< Shift value for DVDD1V86THRESCOARSE */ #define _DEVINFO_VMONCAL1_DVDD1V86THRESCOARSE_MASK 0xF0UL /**< Bit mask for DVDD1V86THRESCOARSE */ #define _DEVINFO_VMONCAL1_DVDD2V98THRESFINE_SHIFT 8 /**< Shift value for DVDD2V98THRESFINE */ #define _DEVINFO_VMONCAL1_DVDD2V98THRESFINE_MASK 0xF00UL /**< Bit mask for DVDD2V98THRESFINE */ #define _DEVINFO_VMONCAL1_DVDD2V98THRESCOARSE_SHIFT 12 /**< Shift value for DVDD2V98THRESCOARSE */ #define _DEVINFO_VMONCAL1_DVDD2V98THRESCOARSE_MASK 0xF000UL /**< Bit mask for DVDD2V98THRESCOARSE */ #define _DEVINFO_VMONCAL1_IO01V86THRESFINE_SHIFT 16 /**< Shift value for IO01V86THRESFINE */ #define _DEVINFO_VMONCAL1_IO01V86THRESFINE_MASK 0xF0000UL /**< Bit mask for IO01V86THRESFINE */ #define _DEVINFO_VMONCAL1_IO01V86THRESCOARSE_SHIFT 20 /**< Shift value for IO01V86THRESCOARSE */ #define _DEVINFO_VMONCAL1_IO01V86THRESCOARSE_MASK 0xF00000UL /**< Bit mask for IO01V86THRESCOARSE */ #define _DEVINFO_VMONCAL1_IO02V98THRESFINE_SHIFT 24 /**< Shift value for IO02V98THRESFINE */ #define _DEVINFO_VMONCAL1_IO02V98THRESFINE_MASK 0xF000000UL /**< Bit mask for IO02V98THRESFINE */ #define _DEVINFO_VMONCAL1_IO02V98THRESCOARSE_SHIFT 28 /**< Shift value for IO02V98THRESCOARSE */ #define _DEVINFO_VMONCAL1_IO02V98THRESCOARSE_MASK 0xF0000000UL /**< Bit mask for IO02V98THRESCOARSE */ /* Bit fields for DEVINFO VMONCAL2 */ #define _DEVINFO_VMONCAL2_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_VMONCAL2 */ #define _DEVINFO_VMONCAL2_PAVDD1V86THRESFINE_SHIFT 0 /**< Shift value for PAVDD1V86THRESFINE */ #define _DEVINFO_VMONCAL2_PAVDD1V86THRESFINE_MASK 0xFUL /**< Bit mask for PAVDD1V86THRESFINE */ #define _DEVINFO_VMONCAL2_PAVDD1V86THRESCOARSE_SHIFT 4 /**< Shift value for PAVDD1V86THRESCOARSE */ #define _DEVINFO_VMONCAL2_PAVDD1V86THRESCOARSE_MASK 0xF0UL /**< Bit mask for PAVDD1V86THRESCOARSE */ #define _DEVINFO_VMONCAL2_PAVDD2V98THRESFINE_SHIFT 8 /**< Shift value for PAVDD2V98THRESFINE */ #define _DEVINFO_VMONCAL2_PAVDD2V98THRESFINE_MASK 0xF00UL /**< Bit mask for PAVDD2V98THRESFINE */ #define _DEVINFO_VMONCAL2_PAVDD2V98THRESCOARSE_SHIFT 12 /**< Shift value for PAVDD2V98THRESCOARSE */ #define _DEVINFO_VMONCAL2_PAVDD2V98THRESCOARSE_MASK 0xF000UL /**< Bit mask for PAVDD2V98THRESCOARSE */ #define _DEVINFO_VMONCAL2_FVDD1V86THRESFINE_SHIFT 16 /**< Shift value for FVDD1V86THRESFINE */ #define _DEVINFO_VMONCAL2_FVDD1V86THRESFINE_MASK 0xF0000UL /**< Bit mask for FVDD1V86THRESFINE */ #define _DEVINFO_VMONCAL2_FVDD1V86THRESCOARSE_SHIFT 20 /**< Shift value for FVDD1V86THRESCOARSE */ #define _DEVINFO_VMONCAL2_FVDD1V86THRESCOARSE_MASK 0xF00000UL /**< Bit mask for FVDD1V86THRESCOARSE */ #define _DEVINFO_VMONCAL2_FVDD2V98THRESFINE_SHIFT 24 /**< Shift value for FVDD2V98THRESFINE */ #define _DEVINFO_VMONCAL2_FVDD2V98THRESFINE_MASK 0xF000000UL /**< Bit mask for FVDD2V98THRESFINE */ #define _DEVINFO_VMONCAL2_FVDD2V98THRESCOARSE_SHIFT 28 /**< Shift value for FVDD2V98THRESCOARSE */ #define _DEVINFO_VMONCAL2_FVDD2V98THRESCOARSE_MASK 0xF0000000UL /**< Bit mask for FVDD2V98THRESCOARSE */ /* Bit fields for DEVINFO IDAC0CAL0 */ #define _DEVINFO_IDAC0CAL0_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_IDAC0CAL0 */ #define _DEVINFO_IDAC0CAL0_SOURCERANGE0TUNING_SHIFT 0 /**< Shift value for SOURCERANGE0TUNING */ #define _DEVINFO_IDAC0CAL0_SOURCERANGE0TUNING_MASK 0xFFUL /**< Bit mask for SOURCERANGE0TUNING */ #define _DEVINFO_IDAC0CAL0_SOURCERANGE1TUNING_SHIFT 8 /**< Shift value for SOURCERANGE1TUNING */ #define _DEVINFO_IDAC0CAL0_SOURCERANGE1TUNING_MASK 0xFF00UL /**< Bit mask for SOURCERANGE1TUNING */ #define _DEVINFO_IDAC0CAL0_SOURCERANGE2TUNING_SHIFT 16 /**< Shift value for SOURCERANGE2TUNING */ #define _DEVINFO_IDAC0CAL0_SOURCERANGE2TUNING_MASK 0xFF0000UL /**< Bit mask for SOURCERANGE2TUNING */ #define _DEVINFO_IDAC0CAL0_SOURCERANGE3TUNING_SHIFT 24 /**< Shift value for SOURCERANGE3TUNING */ #define _DEVINFO_IDAC0CAL0_SOURCERANGE3TUNING_MASK 0xFF000000UL /**< Bit mask for SOURCERANGE3TUNING */ /* Bit fields for DEVINFO IDAC0CAL1 */ #define _DEVINFO_IDAC0CAL1_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_IDAC0CAL1 */ #define _DEVINFO_IDAC0CAL1_SINKRANGE0TUNING_SHIFT 0 /**< Shift value for SINKRANGE0TUNING */ #define _DEVINFO_IDAC0CAL1_SINKRANGE0TUNING_MASK 0xFFUL /**< Bit mask for SINKRANGE0TUNING */ #define _DEVINFO_IDAC0CAL1_SINKRANGE1TUNING_SHIFT 8 /**< Shift value for SINKRANGE1TUNING */ #define _DEVINFO_IDAC0CAL1_SINKRANGE1TUNING_MASK 0xFF00UL /**< Bit mask for SINKRANGE1TUNING */ #define _DEVINFO_IDAC0CAL1_SINKRANGE2TUNING_SHIFT 16 /**< Shift value for SINKRANGE2TUNING */ #define _DEVINFO_IDAC0CAL1_SINKRANGE2TUNING_MASK 0xFF0000UL /**< Bit mask for SINKRANGE2TUNING */ #define _DEVINFO_IDAC0CAL1_SINKRANGE3TUNING_SHIFT 24 /**< Shift value for SINKRANGE3TUNING */ #define _DEVINFO_IDAC0CAL1_SINKRANGE3TUNING_MASK 0xFF000000UL /**< Bit mask for SINKRANGE3TUNING */ /* Bit fields for DEVINFO DCDCLNVCTRL0 */ #define _DEVINFO_DCDCLNVCTRL0_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_DCDCLNVCTRL0 */ #define _DEVINFO_DCDCLNVCTRL0_1V2LNATT0_SHIFT 0 /**< Shift value for 1V2LNATT0 */ #define _DEVINFO_DCDCLNVCTRL0_1V2LNATT0_MASK 0xFFUL /**< Bit mask for 1V2LNATT0 */ #define _DEVINFO_DCDCLNVCTRL0_1V8LNATT0_SHIFT 8 /**< Shift value for 1V8LNATT0 */ #define _DEVINFO_DCDCLNVCTRL0_1V8LNATT0_MASK 0xFF00UL /**< Bit mask for 1V8LNATT0 */ #define _DEVINFO_DCDCLNVCTRL0_1V8LNATT1_SHIFT 16 /**< Shift value for 1V8LNATT1 */ #define _DEVINFO_DCDCLNVCTRL0_1V8LNATT1_MASK 0xFF0000UL /**< Bit mask for 1V8LNATT1 */ #define _DEVINFO_DCDCLNVCTRL0_3V0LNATT1_SHIFT 24 /**< Shift value for 3V0LNATT1 */ #define _DEVINFO_DCDCLNVCTRL0_3V0LNATT1_MASK 0xFF000000UL /**< Bit mask for 3V0LNATT1 */ /* Bit fields for DEVINFO DCDCLPVCTRL0 */ #define _DEVINFO_DCDCLPVCTRL0_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_DCDCLPVCTRL0 */ #define _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS0_SHIFT 0 /**< Shift value for 1V2LPATT0LPCMPBIAS0 */ #define _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS0_MASK 0xFFUL /**< Bit mask for 1V2LPATT0LPCMPBIAS0 */ #define _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS0_SHIFT 8 /**< Shift value for 1V8LPATT0LPCMPBIAS0 */ #define _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS0_MASK 0xFF00UL /**< Bit mask for 1V8LPATT0LPCMPBIAS0 */ #define _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS1_SHIFT 16 /**< Shift value for 1V2LPATT0LPCMPBIAS1 */ #define _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS1_MASK 0xFF0000UL /**< Bit mask for 1V2LPATT0LPCMPBIAS1 */ #define _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS1_SHIFT 24 /**< Shift value for 1V8LPATT0LPCMPBIAS1 */ #define _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS1_MASK 0xFF000000UL /**< Bit mask for 1V8LPATT0LPCMPBIAS1 */ /* Bit fields for DEVINFO DCDCLPVCTRL1 */ #define _DEVINFO_DCDCLPVCTRL1_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_DCDCLPVCTRL1 */ #define _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS2_SHIFT 0 /**< Shift value for 1V2LPATT0LPCMPBIAS2 */ #define _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS2_MASK 0xFFUL /**< Bit mask for 1V2LPATT0LPCMPBIAS2 */ #define _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS2_SHIFT 8 /**< Shift value for 1V8LPATT0LPCMPBIAS2 */ #define _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS2_MASK 0xFF00UL /**< Bit mask for 1V8LPATT0LPCMPBIAS2 */ #define _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS3_SHIFT 16 /**< Shift value for 1V2LPATT0LPCMPBIAS3 */ #define _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS3_MASK 0xFF0000UL /**< Bit mask for 1V2LPATT0LPCMPBIAS3 */ #define _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS3_SHIFT 24 /**< Shift value for 1V8LPATT0LPCMPBIAS3 */ #define _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS3_MASK 0xFF000000UL /**< Bit mask for 1V8LPATT0LPCMPBIAS3 */ /* Bit fields for DEVINFO DCDCLPVCTRL2 */ #define _DEVINFO_DCDCLPVCTRL2_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_DCDCLPVCTRL2 */ #define _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS0_SHIFT 0 /**< Shift value for 1V8LPATT1LPCMPBIAS0 */ #define _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS0_MASK 0xFFUL /**< Bit mask for 1V8LPATT1LPCMPBIAS0 */ #define _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS0_SHIFT 8 /**< Shift value for 3V0LPATT1LPCMPBIAS0 */ #define _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS0_MASK 0xFF00UL /**< Bit mask for 3V0LPATT1LPCMPBIAS0 */ #define _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS1_SHIFT 16 /**< Shift value for 1V8LPATT1LPCMPBIAS1 */ #define _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS1_MASK 0xFF0000UL /**< Bit mask for 1V8LPATT1LPCMPBIAS1 */ #define _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS1_SHIFT 24 /**< Shift value for 3V0LPATT1LPCMPBIAS1 */ #define _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS1_MASK 0xFF000000UL /**< Bit mask for 3V0LPATT1LPCMPBIAS1 */ /* Bit fields for DEVINFO DCDCLPVCTRL3 */ #define _DEVINFO_DCDCLPVCTRL3_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_DCDCLPVCTRL3 */ #define _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS2_SHIFT 0 /**< Shift value for 1V8LPATT1LPCMPBIAS2 */ #define _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS2_MASK 0xFFUL /**< Bit mask for 1V8LPATT1LPCMPBIAS2 */ #define _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS2_SHIFT 8 /**< Shift value for 3V0LPATT1LPCMPBIAS2 */ #define _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS2_MASK 0xFF00UL /**< Bit mask for 3V0LPATT1LPCMPBIAS2 */ #define _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS3_SHIFT 16 /**< Shift value for 1V8LPATT1LPCMPBIAS3 */ #define _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS3_MASK 0xFF0000UL /**< Bit mask for 1V8LPATT1LPCMPBIAS3 */ #define _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS3_SHIFT 24 /**< Shift value for 3V0LPATT1LPCMPBIAS3 */ #define _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS3_MASK 0xFF000000UL /**< Bit mask for 3V0LPATT1LPCMPBIAS3 */ /* Bit fields for DEVINFO DCDCLPCMPHYSSEL0 */ #define _DEVINFO_DCDCLPCMPHYSSEL0_MASK 0x0000FFFFUL /**< Mask for DEVINFO_DCDCLPCMPHYSSEL0 */ #define _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT0_SHIFT 0 /**< Shift value for LPCMPHYSSELLPATT0 */ #define _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT0_MASK 0xFFUL /**< Bit mask for LPCMPHYSSELLPATT0 */ #define _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT1_SHIFT 8 /**< Shift value for LPCMPHYSSELLPATT1 */ #define _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT1_MASK 0xFF00UL /**< Bit mask for LPCMPHYSSELLPATT1 */ /* Bit fields for DEVINFO DCDCLPCMPHYSSEL1 */ #define _DEVINFO_DCDCLPCMPHYSSEL1_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_DCDCLPCMPHYSSEL1 */ #define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS0_SHIFT 0 /**< Shift value for LPCMPHYSSELLPCMPBIAS0 */ #define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS0_MASK 0xFFUL /**< Bit mask for LPCMPHYSSELLPCMPBIAS0 */ #define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS1_SHIFT 8 /**< Shift value for LPCMPHYSSELLPCMPBIAS1 */ #define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS1_MASK 0xFF00UL /**< Bit mask for LPCMPHYSSELLPCMPBIAS1 */ #define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS2_SHIFT 16 /**< Shift value for LPCMPHYSSELLPCMPBIAS2 */ #define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS2_MASK 0xFF0000UL /**< Bit mask for LPCMPHYSSELLPCMPBIAS2 */ #define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS3_SHIFT 24 /**< Shift value for LPCMPHYSSELLPCMPBIAS3 */ #define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS3_MASK 0xFF000000UL /**< Bit mask for LPCMPHYSSELLPCMPBIAS3 */ /* Bit fields for DEVINFO VDAC0MAINCAL */ #define _DEVINFO_VDAC0MAINCAL_MASK 0x3FFFFFFFUL /**< Mask for DEVINFO_VDAC0MAINCAL */ #define _DEVINFO_VDAC0MAINCAL_GAINERRTRIM1V25LN_SHIFT 0 /**< Shift value for GAINERRTRIM1V25LN */ #define _DEVINFO_VDAC0MAINCAL_GAINERRTRIM1V25LN_MASK 0x3FUL /**< Bit mask for GAINERRTRIM1V25LN */ #define _DEVINFO_VDAC0MAINCAL_GAINERRTRIM2V5LN_SHIFT 6 /**< Shift value for GAINERRTRIM2V5LN */ #define _DEVINFO_VDAC0MAINCAL_GAINERRTRIM2V5LN_MASK 0xFC0UL /**< Bit mask for GAINERRTRIM2V5LN */ #define _DEVINFO_VDAC0MAINCAL_GAINERRTRIM1V25_SHIFT 12 /**< Shift value for GAINERRTRIM1V25 */ #define _DEVINFO_VDAC0MAINCAL_GAINERRTRIM1V25_MASK 0x3F000UL /**< Bit mask for GAINERRTRIM1V25 */ #define _DEVINFO_VDAC0MAINCAL_GAINERRTRIM2V5_SHIFT 18 /**< Shift value for GAINERRTRIM2V5 */ #define _DEVINFO_VDAC0MAINCAL_GAINERRTRIM2V5_MASK 0xFC0000UL /**< Bit mask for GAINERRTRIM2V5 */ #define _DEVINFO_VDAC0MAINCAL_GAINERRTRIMVDDANAEXTPIN_SHIFT 24 /**< Shift value for GAINERRTRIMVDDANAEXTPIN */ #define _DEVINFO_VDAC0MAINCAL_GAINERRTRIMVDDANAEXTPIN_MASK 0x3F000000UL /**< Bit mask for GAINERRTRIMVDDANAEXTPIN */ /* Bit fields for DEVINFO VDAC0ALTCAL */ #define _DEVINFO_VDAC0ALTCAL_MASK 0x3FFFFFFFUL /**< Mask for DEVINFO_VDAC0ALTCAL */ #define _DEVINFO_VDAC0ALTCAL_GAINERRTRIM1V25LNALT_SHIFT 0 /**< Shift value for GAINERRTRIM1V25LNALT */ #define _DEVINFO_VDAC0ALTCAL_GAINERRTRIM1V25LNALT_MASK 0x3FUL /**< Bit mask for GAINERRTRIM1V25LNALT */ #define _DEVINFO_VDAC0ALTCAL_GAINERRTRIM2V5LNALT_SHIFT 6 /**< Shift value for GAINERRTRIM2V5LNALT */ #define _DEVINFO_VDAC0ALTCAL_GAINERRTRIM2V5LNALT_MASK 0xFC0UL /**< Bit mask for GAINERRTRIM2V5LNALT */ #define _DEVINFO_VDAC0ALTCAL_GAINERRTRIM1V25ALT_SHIFT 12 /**< Shift value for GAINERRTRIM1V25ALT */ #define _DEVINFO_VDAC0ALTCAL_GAINERRTRIM1V25ALT_MASK 0x3F000UL /**< Bit mask for GAINERRTRIM1V25ALT */ #define _DEVINFO_VDAC0ALTCAL_GAINERRTRIM2V5ALT_SHIFT 18 /**< Shift value for GAINERRTRIM2V5ALT */ #define _DEVINFO_VDAC0ALTCAL_GAINERRTRIM2V5ALT_MASK 0xFC0000UL /**< Bit mask for GAINERRTRIM2V5ALT */ #define _DEVINFO_VDAC0ALTCAL_GAINERRTRIMVDDANAEXTPINALT_SHIFT 24 /**< Shift value for GAINERRTRIMVDDANAEXTPINALT */ #define _DEVINFO_VDAC0ALTCAL_GAINERRTRIMVDDANAEXTPINALT_MASK 0x3F000000UL /**< Bit mask for GAINERRTRIMVDDANAEXTPINALT */ /* Bit fields for DEVINFO VDAC0CH1CAL */ #define _DEVINFO_VDAC0CH1CAL_MASK 0x00000FF7UL /**< Mask for DEVINFO_VDAC0CH1CAL */ #define _DEVINFO_VDAC0CH1CAL_OFFSETTRIM_SHIFT 0 /**< Shift value for OFFSETTRIM */ #define _DEVINFO_VDAC0CH1CAL_OFFSETTRIM_MASK 0x7UL /**< Bit mask for OFFSETTRIM */ #define _DEVINFO_VDAC0CH1CAL_GAINERRTRIMCH1A_SHIFT 4 /**< Shift value for GAINERRTRIMCH1A */ #define _DEVINFO_VDAC0CH1CAL_GAINERRTRIMCH1A_MASK 0xF0UL /**< Bit mask for GAINERRTRIMCH1A */ #define _DEVINFO_VDAC0CH1CAL_GAINERRTRIMCH1B_SHIFT 8 /**< Shift value for GAINERRTRIMCH1B */ #define _DEVINFO_VDAC0CH1CAL_GAINERRTRIMCH1B_MASK 0xF00UL /**< Bit mask for GAINERRTRIMCH1B */ /* Bit fields for DEVINFO OPA0CAL0 */ #define _DEVINFO_OPA0CAL0_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA0CAL0 */ #define _DEVINFO_OPA0CAL0_CM1_SHIFT 0 /**< Shift value for CM1 */ #define _DEVINFO_OPA0CAL0_CM1_MASK 0xFUL /**< Bit mask for CM1 */ #define _DEVINFO_OPA0CAL0_CM2_SHIFT 5 /**< Shift value for CM2 */ #define _DEVINFO_OPA0CAL0_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ #define _DEVINFO_OPA0CAL0_CM3_SHIFT 10 /**< Shift value for CM3 */ #define _DEVINFO_OPA0CAL0_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ #define _DEVINFO_OPA0CAL0_GM_SHIFT 13 /**< Shift value for GM */ #define _DEVINFO_OPA0CAL0_GM_MASK 0xE000UL /**< Bit mask for GM */ #define _DEVINFO_OPA0CAL0_GM3_SHIFT 17 /**< Shift value for GM3 */ #define _DEVINFO_OPA0CAL0_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ #define _DEVINFO_OPA0CAL0_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ #define _DEVINFO_OPA0CAL0_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ #define _DEVINFO_OPA0CAL0_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ #define _DEVINFO_OPA0CAL0_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ /* Bit fields for DEVINFO OPA0CAL1 */ #define _DEVINFO_OPA0CAL1_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA0CAL1 */ #define _DEVINFO_OPA0CAL1_CM1_SHIFT 0 /**< Shift value for CM1 */ #define _DEVINFO_OPA0CAL1_CM1_MASK 0xFUL /**< Bit mask for CM1 */ #define _DEVINFO_OPA0CAL1_CM2_SHIFT 5 /**< Shift value for CM2 */ #define _DEVINFO_OPA0CAL1_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ #define _DEVINFO_OPA0CAL1_CM3_SHIFT 10 /**< Shift value for CM3 */ #define _DEVINFO_OPA0CAL1_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ #define _DEVINFO_OPA0CAL1_GM_SHIFT 13 /**< Shift value for GM */ #define _DEVINFO_OPA0CAL1_GM_MASK 0xE000UL /**< Bit mask for GM */ #define _DEVINFO_OPA0CAL1_GM3_SHIFT 17 /**< Shift value for GM3 */ #define _DEVINFO_OPA0CAL1_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ #define _DEVINFO_OPA0CAL1_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ #define _DEVINFO_OPA0CAL1_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ #define _DEVINFO_OPA0CAL1_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ #define _DEVINFO_OPA0CAL1_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ /* Bit fields for DEVINFO OPA0CAL2 */ #define _DEVINFO_OPA0CAL2_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA0CAL2 */ #define _DEVINFO_OPA0CAL2_CM1_SHIFT 0 /**< Shift value for CM1 */ #define _DEVINFO_OPA0CAL2_CM1_MASK 0xFUL /**< Bit mask for CM1 */ #define _DEVINFO_OPA0CAL2_CM2_SHIFT 5 /**< Shift value for CM2 */ #define _DEVINFO_OPA0CAL2_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ #define _DEVINFO_OPA0CAL2_CM3_SHIFT 10 /**< Shift value for CM3 */ #define _DEVINFO_OPA0CAL2_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ #define _DEVINFO_OPA0CAL2_GM_SHIFT 13 /**< Shift value for GM */ #define _DEVINFO_OPA0CAL2_GM_MASK 0xE000UL /**< Bit mask for GM */ #define _DEVINFO_OPA0CAL2_GM3_SHIFT 17 /**< Shift value for GM3 */ #define _DEVINFO_OPA0CAL2_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ #define _DEVINFO_OPA0CAL2_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ #define _DEVINFO_OPA0CAL2_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ #define _DEVINFO_OPA0CAL2_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ #define _DEVINFO_OPA0CAL2_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ /* Bit fields for DEVINFO OPA0CAL3 */ #define _DEVINFO_OPA0CAL3_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA0CAL3 */ #define _DEVINFO_OPA0CAL3_CM1_SHIFT 0 /**< Shift value for CM1 */ #define _DEVINFO_OPA0CAL3_CM1_MASK 0xFUL /**< Bit mask for CM1 */ #define _DEVINFO_OPA0CAL3_CM2_SHIFT 5 /**< Shift value for CM2 */ #define _DEVINFO_OPA0CAL3_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ #define _DEVINFO_OPA0CAL3_CM3_SHIFT 10 /**< Shift value for CM3 */ #define _DEVINFO_OPA0CAL3_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ #define _DEVINFO_OPA0CAL3_GM_SHIFT 13 /**< Shift value for GM */ #define _DEVINFO_OPA0CAL3_GM_MASK 0xE000UL /**< Bit mask for GM */ #define _DEVINFO_OPA0CAL3_GM3_SHIFT 17 /**< Shift value for GM3 */ #define _DEVINFO_OPA0CAL3_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ #define _DEVINFO_OPA0CAL3_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ #define _DEVINFO_OPA0CAL3_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ #define _DEVINFO_OPA0CAL3_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ #define _DEVINFO_OPA0CAL3_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ /* Bit fields for DEVINFO OPA1CAL0 */ #define _DEVINFO_OPA1CAL0_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA1CAL0 */ #define _DEVINFO_OPA1CAL0_CM1_SHIFT 0 /**< Shift value for CM1 */ #define _DEVINFO_OPA1CAL0_CM1_MASK 0xFUL /**< Bit mask for CM1 */ #define _DEVINFO_OPA1CAL0_CM2_SHIFT 5 /**< Shift value for CM2 */ #define _DEVINFO_OPA1CAL0_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ #define _DEVINFO_OPA1CAL0_CM3_SHIFT 10 /**< Shift value for CM3 */ #define _DEVINFO_OPA1CAL0_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ #define _DEVINFO_OPA1CAL0_GM_SHIFT 13 /**< Shift value for GM */ #define _DEVINFO_OPA1CAL0_GM_MASK 0xE000UL /**< Bit mask for GM */ #define _DEVINFO_OPA1CAL0_GM3_SHIFT 17 /**< Shift value for GM3 */ #define _DEVINFO_OPA1CAL0_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ #define _DEVINFO_OPA1CAL0_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ #define _DEVINFO_OPA1CAL0_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ #define _DEVINFO_OPA1CAL0_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ #define _DEVINFO_OPA1CAL0_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ /* Bit fields for DEVINFO OPA1CAL1 */ #define _DEVINFO_OPA1CAL1_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA1CAL1 */ #define _DEVINFO_OPA1CAL1_CM1_SHIFT 0 /**< Shift value for CM1 */ #define _DEVINFO_OPA1CAL1_CM1_MASK 0xFUL /**< Bit mask for CM1 */ #define _DEVINFO_OPA1CAL1_CM2_SHIFT 5 /**< Shift value for CM2 */ #define _DEVINFO_OPA1CAL1_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ #define _DEVINFO_OPA1CAL1_CM3_SHIFT 10 /**< Shift value for CM3 */ #define _DEVINFO_OPA1CAL1_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ #define _DEVINFO_OPA1CAL1_GM_SHIFT 13 /**< Shift value for GM */ #define _DEVINFO_OPA1CAL1_GM_MASK 0xE000UL /**< Bit mask for GM */ #define _DEVINFO_OPA1CAL1_GM3_SHIFT 17 /**< Shift value for GM3 */ #define _DEVINFO_OPA1CAL1_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ #define _DEVINFO_OPA1CAL1_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ #define _DEVINFO_OPA1CAL1_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ #define _DEVINFO_OPA1CAL1_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ #define _DEVINFO_OPA1CAL1_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ /* Bit fields for DEVINFO OPA1CAL2 */ #define _DEVINFO_OPA1CAL2_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA1CAL2 */ #define _DEVINFO_OPA1CAL2_CM1_SHIFT 0 /**< Shift value for CM1 */ #define _DEVINFO_OPA1CAL2_CM1_MASK 0xFUL /**< Bit mask for CM1 */ #define _DEVINFO_OPA1CAL2_CM2_SHIFT 5 /**< Shift value for CM2 */ #define _DEVINFO_OPA1CAL2_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ #define _DEVINFO_OPA1CAL2_CM3_SHIFT 10 /**< Shift value for CM3 */ #define _DEVINFO_OPA1CAL2_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ #define _DEVINFO_OPA1CAL2_GM_SHIFT 13 /**< Shift value for GM */ #define _DEVINFO_OPA1CAL2_GM_MASK 0xE000UL /**< Bit mask for GM */ #define _DEVINFO_OPA1CAL2_GM3_SHIFT 17 /**< Shift value for GM3 */ #define _DEVINFO_OPA1CAL2_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ #define _DEVINFO_OPA1CAL2_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ #define _DEVINFO_OPA1CAL2_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ #define _DEVINFO_OPA1CAL2_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ #define _DEVINFO_OPA1CAL2_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ /* Bit fields for DEVINFO OPA1CAL3 */ #define _DEVINFO_OPA1CAL3_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA1CAL3 */ #define _DEVINFO_OPA1CAL3_CM1_SHIFT 0 /**< Shift value for CM1 */ #define _DEVINFO_OPA1CAL3_CM1_MASK 0xFUL /**< Bit mask for CM1 */ #define _DEVINFO_OPA1CAL3_CM2_SHIFT 5 /**< Shift value for CM2 */ #define _DEVINFO_OPA1CAL3_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ #define _DEVINFO_OPA1CAL3_CM3_SHIFT 10 /**< Shift value for CM3 */ #define _DEVINFO_OPA1CAL3_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ #define _DEVINFO_OPA1CAL3_GM_SHIFT 13 /**< Shift value for GM */ #define _DEVINFO_OPA1CAL3_GM_MASK 0xE000UL /**< Bit mask for GM */ #define _DEVINFO_OPA1CAL3_GM3_SHIFT 17 /**< Shift value for GM3 */ #define _DEVINFO_OPA1CAL3_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ #define _DEVINFO_OPA1CAL3_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ #define _DEVINFO_OPA1CAL3_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ #define _DEVINFO_OPA1CAL3_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ #define _DEVINFO_OPA1CAL3_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ /* Bit fields for DEVINFO OPA2CAL0 */ #define _DEVINFO_OPA2CAL0_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA2CAL0 */ #define _DEVINFO_OPA2CAL0_CM1_SHIFT 0 /**< Shift value for CM1 */ #define _DEVINFO_OPA2CAL0_CM1_MASK 0xFUL /**< Bit mask for CM1 */ #define _DEVINFO_OPA2CAL0_CM2_SHIFT 5 /**< Shift value for CM2 */ #define _DEVINFO_OPA2CAL0_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ #define _DEVINFO_OPA2CAL0_CM3_SHIFT 10 /**< Shift value for CM3 */ #define _DEVINFO_OPA2CAL0_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ #define _DEVINFO_OPA2CAL0_GM_SHIFT 13 /**< Shift value for GM */ #define _DEVINFO_OPA2CAL0_GM_MASK 0xE000UL /**< Bit mask for GM */ #define _DEVINFO_OPA2CAL0_GM3_SHIFT 17 /**< Shift value for GM3 */ #define _DEVINFO_OPA2CAL0_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ #define _DEVINFO_OPA2CAL0_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ #define _DEVINFO_OPA2CAL0_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ #define _DEVINFO_OPA2CAL0_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ #define _DEVINFO_OPA2CAL0_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ /* Bit fields for DEVINFO OPA2CAL1 */ #define _DEVINFO_OPA2CAL1_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA2CAL1 */ #define _DEVINFO_OPA2CAL1_CM1_SHIFT 0 /**< Shift value for CM1 */ #define _DEVINFO_OPA2CAL1_CM1_MASK 0xFUL /**< Bit mask for CM1 */ #define _DEVINFO_OPA2CAL1_CM2_SHIFT 5 /**< Shift value for CM2 */ #define _DEVINFO_OPA2CAL1_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ #define _DEVINFO_OPA2CAL1_CM3_SHIFT 10 /**< Shift value for CM3 */ #define _DEVINFO_OPA2CAL1_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ #define _DEVINFO_OPA2CAL1_GM_SHIFT 13 /**< Shift value for GM */ #define _DEVINFO_OPA2CAL1_GM_MASK 0xE000UL /**< Bit mask for GM */ #define _DEVINFO_OPA2CAL1_GM3_SHIFT 17 /**< Shift value for GM3 */ #define _DEVINFO_OPA2CAL1_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ #define _DEVINFO_OPA2CAL1_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ #define _DEVINFO_OPA2CAL1_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ #define _DEVINFO_OPA2CAL1_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ #define _DEVINFO_OPA2CAL1_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ /* Bit fields for DEVINFO OPA2CAL2 */ #define _DEVINFO_OPA2CAL2_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA2CAL2 */ #define _DEVINFO_OPA2CAL2_CM1_SHIFT 0 /**< Shift value for CM1 */ #define _DEVINFO_OPA2CAL2_CM1_MASK 0xFUL /**< Bit mask for CM1 */ #define _DEVINFO_OPA2CAL2_CM2_SHIFT 5 /**< Shift value for CM2 */ #define _DEVINFO_OPA2CAL2_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ #define _DEVINFO_OPA2CAL2_CM3_SHIFT 10 /**< Shift value for CM3 */ #define _DEVINFO_OPA2CAL2_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ #define _DEVINFO_OPA2CAL2_GM_SHIFT 13 /**< Shift value for GM */ #define _DEVINFO_OPA2CAL2_GM_MASK 0xE000UL /**< Bit mask for GM */ #define _DEVINFO_OPA2CAL2_GM3_SHIFT 17 /**< Shift value for GM3 */ #define _DEVINFO_OPA2CAL2_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ #define _DEVINFO_OPA2CAL2_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ #define _DEVINFO_OPA2CAL2_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ #define _DEVINFO_OPA2CAL2_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ #define _DEVINFO_OPA2CAL2_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ /* Bit fields for DEVINFO OPA2CAL3 */ #define _DEVINFO_OPA2CAL3_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA2CAL3 */ #define _DEVINFO_OPA2CAL3_CM1_SHIFT 0 /**< Shift value for CM1 */ #define _DEVINFO_OPA2CAL3_CM1_MASK 0xFUL /**< Bit mask for CM1 */ #define _DEVINFO_OPA2CAL3_CM2_SHIFT 5 /**< Shift value for CM2 */ #define _DEVINFO_OPA2CAL3_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ #define _DEVINFO_OPA2CAL3_CM3_SHIFT 10 /**< Shift value for CM3 */ #define _DEVINFO_OPA2CAL3_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ #define _DEVINFO_OPA2CAL3_GM_SHIFT 13 /**< Shift value for GM */ #define _DEVINFO_OPA2CAL3_GM_MASK 0xE000UL /**< Bit mask for GM */ #define _DEVINFO_OPA2CAL3_GM3_SHIFT 17 /**< Shift value for GM3 */ #define _DEVINFO_OPA2CAL3_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ #define _DEVINFO_OPA2CAL3_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ #define _DEVINFO_OPA2CAL3_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ #define _DEVINFO_OPA2CAL3_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ #define _DEVINFO_OPA2CAL3_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ /* Bit fields for DEVINFO CSENGAINCAL */ #define _DEVINFO_CSENGAINCAL_MASK 0x000000FFUL /**< Mask for DEVINFO_CSENGAINCAL */ #define _DEVINFO_CSENGAINCAL_GAINCAL_SHIFT 0 /**< Shift value for GAINCAL */ #define _DEVINFO_CSENGAINCAL_GAINCAL_MASK 0xFFUL /**< Bit mask for GAINCAL */ /* Bit fields for DEVINFO OPA0CAL4 */ #define _DEVINFO_OPA0CAL4_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA0CAL4 */ #define _DEVINFO_OPA0CAL4_CM1_SHIFT 0 /**< Shift value for CM1 */ #define _DEVINFO_OPA0CAL4_CM1_MASK 0xFUL /**< Bit mask for CM1 */ #define _DEVINFO_OPA0CAL4_CM2_SHIFT 5 /**< Shift value for CM2 */ #define _DEVINFO_OPA0CAL4_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ #define _DEVINFO_OPA0CAL4_CM3_SHIFT 10 /**< Shift value for CM3 */ #define _DEVINFO_OPA0CAL4_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ #define _DEVINFO_OPA0CAL4_GM_SHIFT 13 /**< Shift value for GM */ #define _DEVINFO_OPA0CAL4_GM_MASK 0xE000UL /**< Bit mask for GM */ #define _DEVINFO_OPA0CAL4_GM3_SHIFT 17 /**< Shift value for GM3 */ #define _DEVINFO_OPA0CAL4_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ #define _DEVINFO_OPA0CAL4_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ #define _DEVINFO_OPA0CAL4_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ #define _DEVINFO_OPA0CAL4_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ #define _DEVINFO_OPA0CAL4_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ /* Bit fields for DEVINFO OPA0CAL5 */ #define _DEVINFO_OPA0CAL5_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA0CAL5 */ #define _DEVINFO_OPA0CAL5_CM1_SHIFT 0 /**< Shift value for CM1 */ #define _DEVINFO_OPA0CAL5_CM1_MASK 0xFUL /**< Bit mask for CM1 */ #define _DEVINFO_OPA0CAL5_CM2_SHIFT 5 /**< Shift value for CM2 */ #define _DEVINFO_OPA0CAL5_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ #define _DEVINFO_OPA0CAL5_CM3_SHIFT 10 /**< Shift value for CM3 */ #define _DEVINFO_OPA0CAL5_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ #define _DEVINFO_OPA0CAL5_GM_SHIFT 13 /**< Shift value for GM */ #define _DEVINFO_OPA0CAL5_GM_MASK 0xE000UL /**< Bit mask for GM */ #define _DEVINFO_OPA0CAL5_GM3_SHIFT 17 /**< Shift value for GM3 */ #define _DEVINFO_OPA0CAL5_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ #define _DEVINFO_OPA0CAL5_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ #define _DEVINFO_OPA0CAL5_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ #define _DEVINFO_OPA0CAL5_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ #define _DEVINFO_OPA0CAL5_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ /* Bit fields for DEVINFO OPA0CAL6 */ #define _DEVINFO_OPA0CAL6_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA0CAL6 */ #define _DEVINFO_OPA0CAL6_CM1_SHIFT 0 /**< Shift value for CM1 */ #define _DEVINFO_OPA0CAL6_CM1_MASK 0xFUL /**< Bit mask for CM1 */ #define _DEVINFO_OPA0CAL6_CM2_SHIFT 5 /**< Shift value for CM2 */ #define _DEVINFO_OPA0CAL6_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ #define _DEVINFO_OPA0CAL6_CM3_SHIFT 10 /**< Shift value for CM3 */ #define _DEVINFO_OPA0CAL6_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ #define _DEVINFO_OPA0CAL6_GM_SHIFT 13 /**< Shift value for GM */ #define _DEVINFO_OPA0CAL6_GM_MASK 0xE000UL /**< Bit mask for GM */ #define _DEVINFO_OPA0CAL6_GM3_SHIFT 17 /**< Shift value for GM3 */ #define _DEVINFO_OPA0CAL6_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ #define _DEVINFO_OPA0CAL6_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ #define _DEVINFO_OPA0CAL6_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ #define _DEVINFO_OPA0CAL6_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ #define _DEVINFO_OPA0CAL6_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ /* Bit fields for DEVINFO OPA0CAL7 */ #define _DEVINFO_OPA0CAL7_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA0CAL7 */ #define _DEVINFO_OPA0CAL7_CM1_SHIFT 0 /**< Shift value for CM1 */ #define _DEVINFO_OPA0CAL7_CM1_MASK 0xFUL /**< Bit mask for CM1 */ #define _DEVINFO_OPA0CAL7_CM2_SHIFT 5 /**< Shift value for CM2 */ #define _DEVINFO_OPA0CAL7_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ #define _DEVINFO_OPA0CAL7_CM3_SHIFT 10 /**< Shift value for CM3 */ #define _DEVINFO_OPA0CAL7_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ #define _DEVINFO_OPA0CAL7_GM_SHIFT 13 /**< Shift value for GM */ #define _DEVINFO_OPA0CAL7_GM_MASK 0xE000UL /**< Bit mask for GM */ #define _DEVINFO_OPA0CAL7_GM3_SHIFT 17 /**< Shift value for GM3 */ #define _DEVINFO_OPA0CAL7_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ #define _DEVINFO_OPA0CAL7_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ #define _DEVINFO_OPA0CAL7_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ #define _DEVINFO_OPA0CAL7_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ #define _DEVINFO_OPA0CAL7_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ /* Bit fields for DEVINFO OPA1CAL4 */ #define _DEVINFO_OPA1CAL4_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA1CAL4 */ #define _DEVINFO_OPA1CAL4_CM1_SHIFT 0 /**< Shift value for CM1 */ #define _DEVINFO_OPA1CAL4_CM1_MASK 0xFUL /**< Bit mask for CM1 */ #define _DEVINFO_OPA1CAL4_CM2_SHIFT 5 /**< Shift value for CM2 */ #define _DEVINFO_OPA1CAL4_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ #define _DEVINFO_OPA1CAL4_CM3_SHIFT 10 /**< Shift value for CM3 */ #define _DEVINFO_OPA1CAL4_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ #define _DEVINFO_OPA1CAL4_GM_SHIFT 13 /**< Shift value for GM */ #define _DEVINFO_OPA1CAL4_GM_MASK 0xE000UL /**< Bit mask for GM */ #define _DEVINFO_OPA1CAL4_GM3_SHIFT 17 /**< Shift value for GM3 */ #define _DEVINFO_OPA1CAL4_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ #define _DEVINFO_OPA1CAL4_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ #define _DEVINFO_OPA1CAL4_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ #define _DEVINFO_OPA1CAL4_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ #define _DEVINFO_OPA1CAL4_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ /* Bit fields for DEVINFO OPA1CAL5 */ #define _DEVINFO_OPA1CAL5_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA1CAL5 */ #define _DEVINFO_OPA1CAL5_CM1_SHIFT 0 /**< Shift value for CM1 */ #define _DEVINFO_OPA1CAL5_CM1_MASK 0xFUL /**< Bit mask for CM1 */ #define _DEVINFO_OPA1CAL5_CM2_SHIFT 5 /**< Shift value for CM2 */ #define _DEVINFO_OPA1CAL5_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ #define _DEVINFO_OPA1CAL5_CM3_SHIFT 10 /**< Shift value for CM3 */ #define _DEVINFO_OPA1CAL5_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ #define _DEVINFO_OPA1CAL5_GM_SHIFT 13 /**< Shift value for GM */ #define _DEVINFO_OPA1CAL5_GM_MASK 0xE000UL /**< Bit mask for GM */ #define _DEVINFO_OPA1CAL5_GM3_SHIFT 17 /**< Shift value for GM3 */ #define _DEVINFO_OPA1CAL5_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ #define _DEVINFO_OPA1CAL5_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ #define _DEVINFO_OPA1CAL5_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ #define _DEVINFO_OPA1CAL5_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ #define _DEVINFO_OPA1CAL5_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ /* Bit fields for DEVINFO OPA1CAL6 */ #define _DEVINFO_OPA1CAL6_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA1CAL6 */ #define _DEVINFO_OPA1CAL6_CM1_SHIFT 0 /**< Shift value for CM1 */ #define _DEVINFO_OPA1CAL6_CM1_MASK 0xFUL /**< Bit mask for CM1 */ #define _DEVINFO_OPA1CAL6_CM2_SHIFT 5 /**< Shift value for CM2 */ #define _DEVINFO_OPA1CAL6_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ #define _DEVINFO_OPA1CAL6_CM3_SHIFT 10 /**< Shift value for CM3 */ #define _DEVINFO_OPA1CAL6_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ #define _DEVINFO_OPA1CAL6_GM_SHIFT 13 /**< Shift value for GM */ #define _DEVINFO_OPA1CAL6_GM_MASK 0xE000UL /**< Bit mask for GM */ #define _DEVINFO_OPA1CAL6_GM3_SHIFT 17 /**< Shift value for GM3 */ #define _DEVINFO_OPA1CAL6_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ #define _DEVINFO_OPA1CAL6_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ #define _DEVINFO_OPA1CAL6_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ #define _DEVINFO_OPA1CAL6_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ #define _DEVINFO_OPA1CAL6_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ /* Bit fields for DEVINFO OPA1CAL7 */ #define _DEVINFO_OPA1CAL7_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA1CAL7 */ #define _DEVINFO_OPA1CAL7_CM1_SHIFT 0 /**< Shift value for CM1 */ #define _DEVINFO_OPA1CAL7_CM1_MASK 0xFUL /**< Bit mask for CM1 */ #define _DEVINFO_OPA1CAL7_CM2_SHIFT 5 /**< Shift value for CM2 */ #define _DEVINFO_OPA1CAL7_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ #define _DEVINFO_OPA1CAL7_CM3_SHIFT 10 /**< Shift value for CM3 */ #define _DEVINFO_OPA1CAL7_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ #define _DEVINFO_OPA1CAL7_GM_SHIFT 13 /**< Shift value for GM */ #define _DEVINFO_OPA1CAL7_GM_MASK 0xE000UL /**< Bit mask for GM */ #define _DEVINFO_OPA1CAL7_GM3_SHIFT 17 /**< Shift value for GM3 */ #define _DEVINFO_OPA1CAL7_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ #define _DEVINFO_OPA1CAL7_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ #define _DEVINFO_OPA1CAL7_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ #define _DEVINFO_OPA1CAL7_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ #define _DEVINFO_OPA1CAL7_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ /* Bit fields for DEVINFO OPA2CAL4 */ #define _DEVINFO_OPA2CAL4_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA2CAL4 */ #define _DEVINFO_OPA2CAL4_CM1_SHIFT 0 /**< Shift value for CM1 */ #define _DEVINFO_OPA2CAL4_CM1_MASK 0xFUL /**< Bit mask for CM1 */ #define _DEVINFO_OPA2CAL4_CM2_SHIFT 5 /**< Shift value for CM2 */ #define _DEVINFO_OPA2CAL4_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ #define _DEVINFO_OPA2CAL4_CM3_SHIFT 10 /**< Shift value for CM3 */ #define _DEVINFO_OPA2CAL4_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ #define _DEVINFO_OPA2CAL4_GM_SHIFT 13 /**< Shift value for GM */ #define _DEVINFO_OPA2CAL4_GM_MASK 0xE000UL /**< Bit mask for GM */ #define _DEVINFO_OPA2CAL4_GM3_SHIFT 17 /**< Shift value for GM3 */ #define _DEVINFO_OPA2CAL4_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ #define _DEVINFO_OPA2CAL4_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ #define _DEVINFO_OPA2CAL4_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ #define _DEVINFO_OPA2CAL4_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ #define _DEVINFO_OPA2CAL4_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ /* Bit fields for DEVINFO OPA2CAL5 */ #define _DEVINFO_OPA2CAL5_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA2CAL5 */ #define _DEVINFO_OPA2CAL5_CM1_SHIFT 0 /**< Shift value for CM1 */ #define _DEVINFO_OPA2CAL5_CM1_MASK 0xFUL /**< Bit mask for CM1 */ #define _DEVINFO_OPA2CAL5_CM2_SHIFT 5 /**< Shift value for CM2 */ #define _DEVINFO_OPA2CAL5_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ #define _DEVINFO_OPA2CAL5_CM3_SHIFT 10 /**< Shift value for CM3 */ #define _DEVINFO_OPA2CAL5_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ #define _DEVINFO_OPA2CAL5_GM_SHIFT 13 /**< Shift value for GM */ #define _DEVINFO_OPA2CAL5_GM_MASK 0xE000UL /**< Bit mask for GM */ #define _DEVINFO_OPA2CAL5_GM3_SHIFT 17 /**< Shift value for GM3 */ #define _DEVINFO_OPA2CAL5_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ #define _DEVINFO_OPA2CAL5_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ #define _DEVINFO_OPA2CAL5_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ #define _DEVINFO_OPA2CAL5_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ #define _DEVINFO_OPA2CAL5_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ /* Bit fields for DEVINFO OPA2CAL6 */ #define _DEVINFO_OPA2CAL6_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA2CAL6 */ #define _DEVINFO_OPA2CAL6_CM1_SHIFT 0 /**< Shift value for CM1 */ #define _DEVINFO_OPA2CAL6_CM1_MASK 0xFUL /**< Bit mask for CM1 */ #define _DEVINFO_OPA2CAL6_CM2_SHIFT 5 /**< Shift value for CM2 */ #define _DEVINFO_OPA2CAL6_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ #define _DEVINFO_OPA2CAL6_CM3_SHIFT 10 /**< Shift value for CM3 */ #define _DEVINFO_OPA2CAL6_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ #define _DEVINFO_OPA2CAL6_GM_SHIFT 13 /**< Shift value for GM */ #define _DEVINFO_OPA2CAL6_GM_MASK 0xE000UL /**< Bit mask for GM */ #define _DEVINFO_OPA2CAL6_GM3_SHIFT 17 /**< Shift value for GM3 */ #define _DEVINFO_OPA2CAL6_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ #define _DEVINFO_OPA2CAL6_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ #define _DEVINFO_OPA2CAL6_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ #define _DEVINFO_OPA2CAL6_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ #define _DEVINFO_OPA2CAL6_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ /* Bit fields for DEVINFO OPA2CAL7 */ #define _DEVINFO_OPA2CAL7_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA2CAL7 */ #define _DEVINFO_OPA2CAL7_CM1_SHIFT 0 /**< Shift value for CM1 */ #define _DEVINFO_OPA2CAL7_CM1_MASK 0xFUL /**< Bit mask for CM1 */ #define _DEVINFO_OPA2CAL7_CM2_SHIFT 5 /**< Shift value for CM2 */ #define _DEVINFO_OPA2CAL7_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ #define _DEVINFO_OPA2CAL7_CM3_SHIFT 10 /**< Shift value for CM3 */ #define _DEVINFO_OPA2CAL7_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ #define _DEVINFO_OPA2CAL7_GM_SHIFT 13 /**< Shift value for GM */ #define _DEVINFO_OPA2CAL7_GM_MASK 0xE000UL /**< Bit mask for GM */ #define _DEVINFO_OPA2CAL7_GM3_SHIFT 17 /**< Shift value for GM3 */ #define _DEVINFO_OPA2CAL7_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ #define _DEVINFO_OPA2CAL7_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ #define _DEVINFO_OPA2CAL7_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ #define _DEVINFO_OPA2CAL7_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ #define _DEVINFO_OPA2CAL7_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ /** @} */ /** @} End of group EFR32MG12P_DEVINFO */ /** @} End of group Parts */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_dma_descriptor.h.
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/***************************************************************************//** * @file * @brief EFR32MG12P_DMA_DESCRIPTOR register and bit field definitions * @version 5.7.0 ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * SPDX-License-Identifier: Zlib * * The licensor of this software is Silicon Laboratories Inc. * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be * appreciated but is not required. * 2. Altered source versions must be plainly marked as such, and must not be * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * ******************************************************************************/ #if defined(__ICCARM__) #pragma system_include /* Treat file as system include file. */ #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang system_header /* Treat file as system include file. */ #endif /***************************************************************************//** * @addtogroup Parts * @{ ******************************************************************************/ /***************************************************************************//** * @defgroup EFR32MG12P_DMA_DESCRIPTOR DMA Descriptor * @{ ******************************************************************************/ /** DMA_DESCRIPTOR Register Declaration */ typedef struct { /* Note! Use of double __IOM (volatile) qualifier to ensure that both */ /* pointer and referenced memory are declared volatile. */ __IOM uint32_t CTRL; /**< DMA control register */ __IOM void * __IOM SRC; /**< DMA source address */ __IOM void * __IOM DST; /**< DMA destination address */ __IOM void * __IOM LINK; /**< DMA link address */ } DMA_DESCRIPTOR_TypeDef; /**< @} */ /** @} End of group Parts */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_dmareq.h.
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/***************************************************************************//** * @file * @brief EFR32MG12P_DMAREQ register and bit field definitions * @version 5.7.0 ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * SPDX-License-Identifier: Zlib * * The licensor of this software is Silicon Laboratories Inc. * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be * appreciated but is not required. * 2. Altered source versions must be plainly marked as such, and must not be * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * ******************************************************************************/ #if defined(__ICCARM__) #pragma system_include /* Treat file as system include file. */ #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang system_header /* Treat file as system include file. */ #endif /***************************************************************************//** * @addtogroup Parts * @{ ******************************************************************************/ /***************************************************************************//** * @addtogroup EFR32MG12P_DMAREQ DMAREQ * @{ * @defgroup EFR32MG12P_DMAREQ_BitFields DMAREQ Bit Fields * @{ ******************************************************************************/ #define DMAREQ_PRS_REQ0 ((1 << 16) + 0) /**< DMA channel select for PRS_REQ0 */ #define DMAREQ_PRS_REQ1 ((1 << 16) + 1) /**< DMA channel select for PRS_REQ1 */ #define DMAREQ_ADC0_SINGLE ((8 << 16) + 0) /**< DMA channel select for ADC0_SINGLE */ #define DMAREQ_ADC0_SCAN ((8 << 16) + 1) /**< DMA channel select for ADC0_SCAN */ #define DMAREQ_VDAC0_CH0 ((10 << 16) + 0) /**< DMA channel select for VDAC0_CH0 */ #define DMAREQ_VDAC0_CH1 ((10 << 16) + 1) /**< DMA channel select for VDAC0_CH1 */ #define DMAREQ_USART0_RXDATAV ((12 << 16) + 0) /**< DMA channel select for USART0_RXDATAV */ #define DMAREQ_USART0_TXBL ((12 << 16) + 1) /**< DMA channel select for USART0_TXBL */ #define DMAREQ_USART0_TXEMPTY ((12 << 16) + 2) /**< DMA channel select for USART0_TXEMPTY */ #define DMAREQ_USART1_RXDATAV ((13 << 16) + 0) /**< DMA channel select for USART1_RXDATAV */ #define DMAREQ_USART1_TXBL ((13 << 16) + 1) /**< DMA channel select for USART1_TXBL */ #define DMAREQ_USART1_TXEMPTY ((13 << 16) + 2) /**< DMA channel select for USART1_TXEMPTY */ #define DMAREQ_USART1_RXDATAVRIGHT ((13 << 16) + 3) /**< DMA channel select for USART1_RXDATAVRIGHT */ #define DMAREQ_USART1_TXBLRIGHT ((13 << 16) + 4) /**< DMA channel select for USART1_TXBLRIGHT */ #define DMAREQ_USART2_RXDATAV ((14 << 16) + 0) /**< DMA channel select for USART2_RXDATAV */ #define DMAREQ_USART2_TXBL ((14 << 16) + 1) /**< DMA channel select for USART2_TXBL */ #define DMAREQ_USART2_TXEMPTY ((14 << 16) + 2) /**< DMA channel select for USART2_TXEMPTY */ #define DMAREQ_USART3_RXDATAV ((15 << 16) + 0) /**< DMA channel select for USART3_RXDATAV */ #define DMAREQ_USART3_TXBL ((15 << 16) + 1) /**< DMA channel select for USART3_TXBL */ #define DMAREQ_USART3_TXEMPTY ((15 << 16) + 2) /**< DMA channel select for USART3_TXEMPTY */ #define DMAREQ_USART3_RXDATAVRIGHT ((15 << 16) + 3) /**< DMA channel select for USART3_RXDATAVRIGHT */ #define DMAREQ_USART3_TXBLRIGHT ((15 << 16) + 4) /**< DMA channel select for USART3_TXBLRIGHT */ #define DMAREQ_LEUART0_RXDATAV ((16 << 16) + 0) /**< DMA channel select for LEUART0_RXDATAV */ #define DMAREQ_LEUART0_TXBL ((16 << 16) + 1) /**< DMA channel select for LEUART0_TXBL */ #define DMAREQ_LEUART0_TXEMPTY ((16 << 16) + 2) /**< DMA channel select for LEUART0_TXEMPTY */ #define DMAREQ_I2C0_RXDATAV ((20 << 16) + 0) /**< DMA channel select for I2C0_RXDATAV */ #define DMAREQ_I2C0_TXBL ((20 << 16) + 1) /**< DMA channel select for I2C0_TXBL */ #define DMAREQ_I2C1_RXDATAV ((21 << 16) + 0) /**< DMA channel select for I2C1_RXDATAV */ #define DMAREQ_I2C1_TXBL ((21 << 16) + 1) /**< DMA channel select for I2C1_TXBL */ #define DMAREQ_TIMER0_UFOF ((24 << 16) + 0) /**< DMA channel select for TIMER0_UFOF */ #define DMAREQ_TIMER0_CC0 ((24 << 16) + 1) /**< DMA channel select for TIMER0_CC0 */ #define DMAREQ_TIMER0_CC1 ((24 << 16) + 2) /**< DMA channel select for TIMER0_CC1 */ #define DMAREQ_TIMER0_CC2 ((24 << 16) + 3) /**< DMA channel select for TIMER0_CC2 */ #define DMAREQ_TIMER1_UFOF ((25 << 16) + 0) /**< DMA channel select for TIMER1_UFOF */ #define DMAREQ_TIMER1_CC0 ((25 << 16) + 1) /**< DMA channel select for TIMER1_CC0 */ #define DMAREQ_TIMER1_CC1 ((25 << 16) + 2) /**< DMA channel select for TIMER1_CC1 */ #define DMAREQ_TIMER1_CC2 ((25 << 16) + 3) /**< DMA channel select for TIMER1_CC2 */ #define DMAREQ_TIMER1_CC3 ((25 << 16) + 4) /**< DMA channel select for TIMER1_CC3 */ #define DMAREQ_WTIMER0_UFOF ((26 << 16) + 0) /**< DMA channel select for WTIMER0_UFOF */ #define DMAREQ_WTIMER0_CC0 ((26 << 16) + 1) /**< DMA channel select for WTIMER0_CC0 */ #define DMAREQ_WTIMER0_CC1 ((26 << 16) + 2) /**< DMA channel select for WTIMER0_CC1 */ #define DMAREQ_WTIMER0_CC2 ((26 << 16) + 3) /**< DMA channel select for WTIMER0_CC2 */ #define DMAREQ_WTIMER1_UFOF ((27 << 16) + 0) /**< DMA channel select for WTIMER1_UFOF */ #define DMAREQ_WTIMER1_CC0 ((27 << 16) + 1) /**< DMA channel select for WTIMER1_CC0 */ #define DMAREQ_WTIMER1_CC1 ((27 << 16) + 2) /**< DMA channel select for WTIMER1_CC1 */ #define DMAREQ_WTIMER1_CC2 ((27 << 16) + 3) /**< DMA channel select for WTIMER1_CC2 */ #define DMAREQ_WTIMER1_CC3 ((27 << 16) + 4) /**< DMA channel select for WTIMER1_CC3 */ #define DMAREQ_MSC_WDATA ((48 << 16) + 0) /**< DMA channel select for MSC_WDATA */ #define DMAREQ_CRYPTO0_DATA0WR ((49 << 16) + 0) /**< DMA channel select for CRYPTO0_DATA0WR */ #define DMAREQ_CRYPTO_DATA0WR DMAREQ_CRYPTO0_DATA0WR /**< Alias for DMAREQ_CRYPTO0_DATA0WR */ #define DMAREQ_CRYPTO0_DATA0XWR ((49 << 16) + 1) /**< DMA channel select for CRYPTO0_DATA0XWR */ #define DMAREQ_CRYPTO_DATA0XWR DMAREQ_CRYPTO0_DATA0XWR /**< Alias for DMAREQ_CRYPTO0_DATA0XWR */ #define DMAREQ_CRYPTO0_DATA0RD ((49 << 16) + 2) /**< DMA channel select for CRYPTO0_DATA0RD */ #define DMAREQ_CRYPTO_DATA0RD DMAREQ_CRYPTO0_DATA0RD /**< Alias for DMAREQ_CRYPTO0_DATA0RD */ #define DMAREQ_CRYPTO0_DATA1WR ((49 << 16) + 3) /**< DMA channel select for CRYPTO0_DATA1WR */ #define DMAREQ_CRYPTO_DATA1WR DMAREQ_CRYPTO0_DATA1WR /**< Alias for DMAREQ_CRYPTO0_DATA1WR */ #define DMAREQ_CRYPTO0_DATA1RD ((49 << 16) + 4) /**< DMA channel select for CRYPTO0_DATA1RD */ #define DMAREQ_CRYPTO_DATA1RD DMAREQ_CRYPTO0_DATA1RD /**< Alias for DMAREQ_CRYPTO0_DATA1RD */ #define DMAREQ_CSEN_DATA ((50 << 16) + 0) /**< DMA channel select for CSEN_DATA */ #define DMAREQ_CSEN_BSLN ((50 << 16) + 1) /**< DMA channel select for CSEN_BSLN */ #define DMAREQ_LESENSE_BUFDATAV ((51 << 16) + 0) /**< DMA channel select for LESENSE_BUFDATAV */ #define DMAREQ_CRYPTO1_DATA0WR ((52 << 16) + 0) /**< DMA channel select for CRYPTO1_DATA0WR */ #define DMAREQ_CRYPTO1_DATA0XWR ((52 << 16) + 1) /**< DMA channel select for CRYPTO1_DATA0XWR */ #define DMAREQ_CRYPTO1_DATA0RD ((52 << 16) + 2) /**< DMA channel select for CRYPTO1_DATA0RD */ #define DMAREQ_CRYPTO1_DATA1WR ((52 << 16) + 3) /**< DMA channel select for CRYPTO1_DATA1WR */ #define DMAREQ_CRYPTO1_DATA1RD ((52 << 16) + 4) /**< DMA channel select for CRYPTO1_DATA1RD */ /** @} */ /** @} End of group EFR32MG12P_DMAREQ */ /** @} End of group Parts */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_emu.h.
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/***************************************************************************//** * @file * @brief EFR32MG12P_EMU register and bit field definitions * @version 5.7.0 ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * SPDX-License-Identifier: Zlib * * The licensor of this software is Silicon Laboratories Inc. * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be * appreciated but is not required. * 2. Altered source versions must be plainly marked as such, and must not be * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * ******************************************************************************/ #if defined(__ICCARM__) #pragma system_include /* Treat file as system include file. */ #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang system_header /* Treat file as system include file. */ #endif /***************************************************************************//** * @addtogroup Parts * @{ ******************************************************************************/ /***************************************************************************//** * @defgroup EFR32MG12P_EMU EMU * @{ * @brief EFR32MG12P_EMU Register Declaration ******************************************************************************/ /** EMU Register Declaration */ typedef struct { __IOM uint32_t CTRL; /**< Control Register */ __IM uint32_t STATUS; /**< Status Register */ __IOM uint32_t LOCK; /**< Configuration Lock Register */ __IOM uint32_t RAM0CTRL; /**< Memory Control Register */ __IOM uint32_t CMD; /**< Command Register */ uint32_t RESERVED0[1U]; /**< Reserved for future use **/ __IOM uint32_t EM4CTRL; /**< EM4 Control Register */ __IOM uint32_t TEMPLIMITS; /**< Temperature Limits for Interrupt Generation */ __IM uint32_t TEMP; /**< Value of Last Temperature Measurement */ __IM uint32_t IF; /**< Interrupt Flag Register */ __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ __IOM uint32_t IEN; /**< Interrupt Enable Register */ __IOM uint32_t PWRLOCK; /**< Regulator and Supply Lock Register */ __IOM uint32_t PWRCFG; /**< Power Configuration Register */ __IOM uint32_t PWRCTRL; /**< Power Control Register */ __IOM uint32_t DCDCCTRL; /**< DCDC Control */ uint32_t RESERVED1[2U]; /**< Reserved for future use **/ __IOM uint32_t DCDCMISCCTRL; /**< DCDC Miscellaneous Control Register */ __IOM uint32_t DCDCZDETCTRL; /**< DCDC Power Train NFET Zero Current Detector Control Register */ __IOM uint32_t DCDCCLIMCTRL; /**< DCDC Power Train PFET Current Limiter Control Register */ __IOM uint32_t DCDCLNCOMPCTRL; /**< DCDC Low Noise Compensator Control Register */ __IOM uint32_t DCDCLNVCTRL; /**< DCDC Low Noise Voltage Register */ uint32_t RESERVED2[1U]; /**< Reserved for future use **/ __IOM uint32_t DCDCLPVCTRL; /**< DCDC Low Power Voltage Register */ uint32_t RESERVED3[1U]; /**< Reserved for future use **/ __IOM uint32_t DCDCLPCTRL; /**< DCDC Low Power Control Register */ __IOM uint32_t DCDCLNFREQCTRL; /**< DCDC Low Noise Controller Frequency Control */ uint32_t RESERVED4[1U]; /**< Reserved for future use **/ __IM uint32_t DCDCSYNC; /**< DCDC Read Status Register */ uint32_t RESERVED5[5U]; /**< Reserved for future use **/ __IOM uint32_t VMONAVDDCTRL; /**< VMON AVDD Channel Control */ __IOM uint32_t VMONALTAVDDCTRL; /**< Alternate VMON AVDD Channel Control */ __IOM uint32_t VMONDVDDCTRL; /**< VMON DVDD Channel Control */ __IOM uint32_t VMONIO0CTRL; /**< VMON IOVDD0 Channel Control */ uint32_t RESERVED6[5U]; /**< Reserved for future use **/ __IOM uint32_t RAM1CTRL; /**< Memory Control Register */ __IOM uint32_t RAM2CTRL; /**< Memory Control Register */ uint32_t RESERVED7[12U]; /**< Reserved for future use **/ __IOM uint32_t DCDCLPEM01CFG; /**< Configuration Bits for Low Power Mode to Be Applied During EM01, This Field is Only Relevant If LP Mode is Used in EM01 */ uint32_t RESERVED8[4U]; /**< Reserved for future use **/ __IOM uint32_t EM23PERNORETAINCMD; /**< Clears Corresponding Bits in EM23PERNORETAINSTATUS Unlocking Access to Peripheral */ __IM uint32_t EM23PERNORETAINSTATUS; /**< Status Indicating If Peripherals Were Powered Down in EM23, Subsequently Locking Access to It */ __IOM uint32_t EM23PERNORETAINCTRL; /**< When Set Corresponding Peripherals May Get Powered Down in EM23 */ } EMU_TypeDef; /** @} */ /***************************************************************************//** * @addtogroup EFR32MG12P_EMU * @{ * @defgroup EFR32MG12P_EMU_BitFields EMU Bit Fields * @{ ******************************************************************************/ /* Bit fields for EMU CTRL */ #define _EMU_CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_CTRL */ #define _EMU_CTRL_MASK 0x0003031EUL /**< Mask for EMU_CTRL */ #define EMU_CTRL_EM2BLOCK (0x1UL << 1) /**< Energy Mode 2 Block */ #define _EMU_CTRL_EM2BLOCK_SHIFT 1 /**< Shift value for EMU_EM2BLOCK */ #define _EMU_CTRL_EM2BLOCK_MASK 0x2UL /**< Bit mask for EMU_EM2BLOCK */ #define _EMU_CTRL_EM2BLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ #define EMU_CTRL_EM2BLOCK_DEFAULT (_EMU_CTRL_EM2BLOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_CTRL */ #define EMU_CTRL_EM2BODDIS (0x1UL << 2) /**< Disable BOD in EM2 */ #define _EMU_CTRL_EM2BODDIS_SHIFT 2 /**< Shift value for EMU_EM2BODDIS */ #define _EMU_CTRL_EM2BODDIS_MASK 0x4UL /**< Bit mask for EMU_EM2BODDIS */ #define _EMU_CTRL_EM2BODDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ #define EMU_CTRL_EM2BODDIS_DEFAULT (_EMU_CTRL_EM2BODDIS_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_CTRL */ #define EMU_CTRL_EM01LD (0x1UL << 3) /**< Reserved for internal use. Do not change. */ #define _EMU_CTRL_EM01LD_SHIFT 3 /**< Shift value for EMU_EM01LD */ #define _EMU_CTRL_EM01LD_MASK 0x8UL /**< Bit mask for EMU_EM01LD */ #define _EMU_CTRL_EM01LD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ #define EMU_CTRL_EM01LD_DEFAULT (_EMU_CTRL_EM01LD_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_CTRL */ #define EMU_CTRL_EM23VSCALEAUTOWSEN (0x1UL << 4) /**< Automatically Configures Flash and Frequency to Wakeup From EM2 or EM3 at Low Voltage */ #define _EMU_CTRL_EM23VSCALEAUTOWSEN_SHIFT 4 /**< Shift value for EMU_EM23VSCALEAUTOWSEN */ #define _EMU_CTRL_EM23VSCALEAUTOWSEN_MASK 0x10UL /**< Bit mask for EMU_EM23VSCALEAUTOWSEN */ #define _EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ #define EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT (_EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_CTRL */ #define _EMU_CTRL_EM23VSCALE_SHIFT 8 /**< Shift value for EMU_EM23VSCALE */ #define _EMU_CTRL_EM23VSCALE_MASK 0x300UL /**< Bit mask for EMU_EM23VSCALE */ #define _EMU_CTRL_EM23VSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ #define _EMU_CTRL_EM23VSCALE_VSCALE2 0x00000000UL /**< Mode VSCALE2 for EMU_CTRL */ #define _EMU_CTRL_EM23VSCALE_VSCALE0 0x00000002UL /**< Mode VSCALE0 for EMU_CTRL */ #define _EMU_CTRL_EM23VSCALE_RESV 0x00000003UL /**< Mode RESV for EMU_CTRL */ #define EMU_CTRL_EM23VSCALE_DEFAULT (_EMU_CTRL_EM23VSCALE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_CTRL */ #define EMU_CTRL_EM23VSCALE_VSCALE2 (_EMU_CTRL_EM23VSCALE_VSCALE2 << 8) /**< Shifted mode VSCALE2 for EMU_CTRL */ #define EMU_CTRL_EM23VSCALE_VSCALE0 (_EMU_CTRL_EM23VSCALE_VSCALE0 << 8) /**< Shifted mode VSCALE0 for EMU_CTRL */ #define EMU_CTRL_EM23VSCALE_RESV (_EMU_CTRL_EM23VSCALE_RESV << 8) /**< Shifted mode RESV for EMU_CTRL */ #define _EMU_CTRL_EM4HVSCALE_SHIFT 16 /**< Shift value for EMU_EM4HVSCALE */ #define _EMU_CTRL_EM4HVSCALE_MASK 0x30000UL /**< Bit mask for EMU_EM4HVSCALE */ #define _EMU_CTRL_EM4HVSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ #define _EMU_CTRL_EM4HVSCALE_VSCALE2 0x00000000UL /**< Mode VSCALE2 for EMU_CTRL */ #define _EMU_CTRL_EM4HVSCALE_VSCALE0 0x00000002UL /**< Mode VSCALE0 for EMU_CTRL */ #define _EMU_CTRL_EM4HVSCALE_RESV 0x00000003UL /**< Mode RESV for EMU_CTRL */ #define EMU_CTRL_EM4HVSCALE_DEFAULT (_EMU_CTRL_EM4HVSCALE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_CTRL */ #define EMU_CTRL_EM4HVSCALE_VSCALE2 (_EMU_CTRL_EM4HVSCALE_VSCALE2 << 16) /**< Shifted mode VSCALE2 for EMU_CTRL */ #define EMU_CTRL_EM4HVSCALE_VSCALE0 (_EMU_CTRL_EM4HVSCALE_VSCALE0 << 16) /**< Shifted mode VSCALE0 for EMU_CTRL */ #define EMU_CTRL_EM4HVSCALE_RESV (_EMU_CTRL_EM4HVSCALE_RESV << 16) /**< Shifted mode RESV for EMU_CTRL */ /* Bit fields for EMU STATUS */ #define _EMU_STATUS_RESETVALUE 0x00000000UL /**< Default value for EMU_STATUS */ #define _EMU_STATUS_MASK 0x0417011FUL /**< Mask for EMU_STATUS */ #define EMU_STATUS_VMONRDY (0x1UL << 0) /**< VMON Ready */ #define _EMU_STATUS_VMONRDY_SHIFT 0 /**< Shift value for EMU_VMONRDY */ #define _EMU_STATUS_VMONRDY_MASK 0x1UL /**< Bit mask for EMU_VMONRDY */ #define _EMU_STATUS_VMONRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ #define EMU_STATUS_VMONRDY_DEFAULT (_EMU_STATUS_VMONRDY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_STATUS */ #define EMU_STATUS_VMONAVDD (0x1UL << 1) /**< VMON AVDD Channel */ #define _EMU_STATUS_VMONAVDD_SHIFT 1 /**< Shift value for EMU_VMONAVDD */ #define _EMU_STATUS_VMONAVDD_MASK 0x2UL /**< Bit mask for EMU_VMONAVDD */ #define _EMU_STATUS_VMONAVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ #define EMU_STATUS_VMONAVDD_DEFAULT (_EMU_STATUS_VMONAVDD_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_STATUS */ #define EMU_STATUS_VMONALTAVDD (0x1UL << 2) /**< Alternate VMON AVDD Channel */ #define _EMU_STATUS_VMONALTAVDD_SHIFT 2 /**< Shift value for EMU_VMONALTAVDD */ #define _EMU_STATUS_VMONALTAVDD_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDD */ #define _EMU_STATUS_VMONALTAVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ #define EMU_STATUS_VMONALTAVDD_DEFAULT (_EMU_STATUS_VMONALTAVDD_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_STATUS */ #define EMU_STATUS_VMONDVDD (0x1UL << 3) /**< VMON DVDD Channel */ #define _EMU_STATUS_VMONDVDD_SHIFT 3 /**< Shift value for EMU_VMONDVDD */ #define _EMU_STATUS_VMONDVDD_MASK 0x8UL /**< Bit mask for EMU_VMONDVDD */ #define _EMU_STATUS_VMONDVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ #define EMU_STATUS_VMONDVDD_DEFAULT (_EMU_STATUS_VMONDVDD_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_STATUS */ #define EMU_STATUS_VMONIO0 (0x1UL << 4) /**< VMON IOVDD0 Channel */ #define _EMU_STATUS_VMONIO0_SHIFT 4 /**< Shift value for EMU_VMONIO0 */ #define _EMU_STATUS_VMONIO0_MASK 0x10UL /**< Bit mask for EMU_VMONIO0 */ #define _EMU_STATUS_VMONIO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ #define EMU_STATUS_VMONIO0_DEFAULT (_EMU_STATUS_VMONIO0_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_STATUS */ #define EMU_STATUS_VMONFVDD (0x1UL << 8) /**< VMON VDDFLASH Channel */ #define _EMU_STATUS_VMONFVDD_SHIFT 8 /**< Shift value for EMU_VMONFVDD */ #define _EMU_STATUS_VMONFVDD_MASK 0x100UL /**< Bit mask for EMU_VMONFVDD */ #define _EMU_STATUS_VMONFVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ #define EMU_STATUS_VMONFVDD_DEFAULT (_EMU_STATUS_VMONFVDD_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_STATUS */ #define _EMU_STATUS_VSCALE_SHIFT 16 /**< Shift value for EMU_VSCALE */ #define _EMU_STATUS_VSCALE_MASK 0x30000UL /**< Bit mask for EMU_VSCALE */ #define _EMU_STATUS_VSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ #define _EMU_STATUS_VSCALE_VSCALE2 0x00000000UL /**< Mode VSCALE2 for EMU_STATUS */ #define _EMU_STATUS_VSCALE_VSCALE0 0x00000002UL /**< Mode VSCALE0 for EMU_STATUS */ #define _EMU_STATUS_VSCALE_RESV 0x00000003UL /**< Mode RESV for EMU_STATUS */ #define EMU_STATUS_VSCALE_DEFAULT (_EMU_STATUS_VSCALE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_STATUS */ #define EMU_STATUS_VSCALE_VSCALE2 (_EMU_STATUS_VSCALE_VSCALE2 << 16) /**< Shifted mode VSCALE2 for EMU_STATUS */ #define EMU_STATUS_VSCALE_VSCALE0 (_EMU_STATUS_VSCALE_VSCALE0 << 16) /**< Shifted mode VSCALE0 for EMU_STATUS */ #define EMU_STATUS_VSCALE_RESV (_EMU_STATUS_VSCALE_RESV << 16) /**< Shifted mode RESV for EMU_STATUS */ #define EMU_STATUS_VSCALEBUSY (0x1UL << 18) /**< System is Busy Scaling Voltage */ #define _EMU_STATUS_VSCALEBUSY_SHIFT 18 /**< Shift value for EMU_VSCALEBUSY */ #define _EMU_STATUS_VSCALEBUSY_MASK 0x40000UL /**< Bit mask for EMU_VSCALEBUSY */ #define _EMU_STATUS_VSCALEBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ #define EMU_STATUS_VSCALEBUSY_DEFAULT (_EMU_STATUS_VSCALEBUSY_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_STATUS */ #define EMU_STATUS_EM4IORET (0x1UL << 20) /**< IO Retention Status */ #define _EMU_STATUS_EM4IORET_SHIFT 20 /**< Shift value for EMU_EM4IORET */ #define _EMU_STATUS_EM4IORET_MASK 0x100000UL /**< Bit mask for EMU_EM4IORET */ #define _EMU_STATUS_EM4IORET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ #define _EMU_STATUS_EM4IORET_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_STATUS */ #define _EMU_STATUS_EM4IORET_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_STATUS */ #define EMU_STATUS_EM4IORET_DEFAULT (_EMU_STATUS_EM4IORET_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_STATUS */ #define EMU_STATUS_EM4IORET_DISABLED (_EMU_STATUS_EM4IORET_DISABLED << 20) /**< Shifted mode DISABLED for EMU_STATUS */ #define EMU_STATUS_EM4IORET_ENABLED (_EMU_STATUS_EM4IORET_ENABLED << 20) /**< Shifted mode ENABLED for EMU_STATUS */ #define EMU_STATUS_TEMPACTIVE (0x1UL << 26) /**< Temperature Measurement Active */ #define _EMU_STATUS_TEMPACTIVE_SHIFT 26 /**< Shift value for EMU_TEMPACTIVE */ #define _EMU_STATUS_TEMPACTIVE_MASK 0x4000000UL /**< Bit mask for EMU_TEMPACTIVE */ #define _EMU_STATUS_TEMPACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ #define EMU_STATUS_TEMPACTIVE_DEFAULT (_EMU_STATUS_TEMPACTIVE_DEFAULT << 26) /**< Shifted mode DEFAULT for EMU_STATUS */ /* Bit fields for EMU LOCK */ #define _EMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for EMU_LOCK */ #define _EMU_LOCK_MASK 0x0000FFFFUL /**< Mask for EMU_LOCK */ #define _EMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */ #define _EMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */ #define _EMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_LOCK */ #define _EMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_LOCK */ #define _EMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_LOCK */ #define _EMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_LOCK */ #define _EMU_LOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_LOCK */ #define EMU_LOCK_LOCKKEY_DEFAULT (_EMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_LOCK */ #define EMU_LOCK_LOCKKEY_LOCK (_EMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_LOCK */ #define EMU_LOCK_LOCKKEY_UNLOCKED (_EMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_LOCK */ #define EMU_LOCK_LOCKKEY_LOCKED (_EMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_LOCK */ #define EMU_LOCK_LOCKKEY_UNLOCK (_EMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_LOCK */ /* Bit fields for EMU RAM0CTRL */ #define _EMU_RAM0CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM0CTRL */ #define _EMU_RAM0CTRL_MASK 0x0000000FUL /**< Mask for EMU_RAM0CTRL */ #define _EMU_RAM0CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */ #define _EMU_RAM0CTRL_RAMPOWERDOWN_MASK 0xFUL /**< Bit mask for EMU_RAMPOWERDOWN */ #define _EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM0CTRL */ #define _EMU_RAM0CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM0CTRL */ #define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK4 0x00000008UL /**< Mode BLK4 for EMU_RAM0CTRL */ #define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO4 0x0000000CUL /**< Mode BLK3TO4 for EMU_RAM0CTRL */ #define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO4 0x0000000EUL /**< Mode BLK2TO4 for EMU_RAM0CTRL */ #define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO4 0x0000000FUL /**< Mode BLK1TO4 for EMU_RAM0CTRL */ #define EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM0CTRL */ #define EMU_RAM0CTRL_RAMPOWERDOWN_NONE (_EMU_RAM0CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM0CTRL */ #define EMU_RAM0CTRL_RAMPOWERDOWN_BLK4 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK4 << 0) /**< Shifted mode BLK4 for EMU_RAM0CTRL */ #define EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO4 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO4 << 0) /**< Shifted mode BLK3TO4 for EMU_RAM0CTRL */ #define EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO4 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO4 << 0) /**< Shifted mode BLK2TO4 for EMU_RAM0CTRL */ #define EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO4 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO4 << 0) /**< Shifted mode BLK1TO4 for EMU_RAM0CTRL */ /* Bit fields for EMU CMD */ #define _EMU_CMD_RESETVALUE 0x00000000UL /**< Default value for EMU_CMD */ #define _EMU_CMD_MASK 0x00000051UL /**< Mask for EMU_CMD */ #define EMU_CMD_EM4UNLATCH (0x1UL << 0) /**< EM4 Unlatch */ #define _EMU_CMD_EM4UNLATCH_SHIFT 0 /**< Shift value for EMU_EM4UNLATCH */ #define _EMU_CMD_EM4UNLATCH_MASK 0x1UL /**< Bit mask for EMU_EM4UNLATCH */ #define _EMU_CMD_EM4UNLATCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ #define EMU_CMD_EM4UNLATCH_DEFAULT (_EMU_CMD_EM4UNLATCH_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_CMD */ #define EMU_CMD_EM01VSCALE0 (0x1UL << 4) /**< EM01 Voltage Scale Command to Scale to Voltage Scale Level 0 */ #define _EMU_CMD_EM01VSCALE0_SHIFT 4 /**< Shift value for EMU_EM01VSCALE0 */ #define _EMU_CMD_EM01VSCALE0_MASK 0x10UL /**< Bit mask for EMU_EM01VSCALE0 */ #define _EMU_CMD_EM01VSCALE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ #define EMU_CMD_EM01VSCALE0_DEFAULT (_EMU_CMD_EM01VSCALE0_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_CMD */ #define EMU_CMD_EM01VSCALE2 (0x1UL << 6) /**< EM01 Voltage Scale Command to Scale to Voltage Scale Level 2 */ #define _EMU_CMD_EM01VSCALE2_SHIFT 6 /**< Shift value for EMU_EM01VSCALE2 */ #define _EMU_CMD_EM01VSCALE2_MASK 0x40UL /**< Bit mask for EMU_EM01VSCALE2 */ #define _EMU_CMD_EM01VSCALE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ #define EMU_CMD_EM01VSCALE2_DEFAULT (_EMU_CMD_EM01VSCALE2_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_CMD */ /* Bit fields for EMU EM4CTRL */ #define _EMU_EM4CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_EM4CTRL */ #define _EMU_EM4CTRL_MASK 0x0003003FUL /**< Mask for EMU_EM4CTRL */ #define EMU_EM4CTRL_EM4STATE (0x1UL << 0) /**< Energy Mode 4 State */ #define _EMU_EM4CTRL_EM4STATE_SHIFT 0 /**< Shift value for EMU_EM4STATE */ #define _EMU_EM4CTRL_EM4STATE_MASK 0x1UL /**< Bit mask for EMU_EM4STATE */ #define _EMU_EM4CTRL_EM4STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ #define _EMU_EM4CTRL_EM4STATE_EM4S 0x00000000UL /**< Mode EM4S for EMU_EM4CTRL */ #define _EMU_EM4CTRL_EM4STATE_EM4H 0x00000001UL /**< Mode EM4H for EMU_EM4CTRL */ #define EMU_EM4CTRL_EM4STATE_DEFAULT (_EMU_EM4CTRL_EM4STATE_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ #define EMU_EM4CTRL_EM4STATE_EM4S (_EMU_EM4CTRL_EM4STATE_EM4S << 0) /**< Shifted mode EM4S for EMU_EM4CTRL */ #define EMU_EM4CTRL_EM4STATE_EM4H (_EMU_EM4CTRL_EM4STATE_EM4H << 0) /**< Shifted mode EM4H for EMU_EM4CTRL */ #define EMU_EM4CTRL_RETAINLFRCO (0x1UL << 1) /**< LFRCO Retain During EM4 */ #define _EMU_EM4CTRL_RETAINLFRCO_SHIFT 1 /**< Shift value for EMU_RETAINLFRCO */ #define _EMU_EM4CTRL_RETAINLFRCO_MASK 0x2UL /**< Bit mask for EMU_RETAINLFRCO */ #define _EMU_EM4CTRL_RETAINLFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ #define EMU_EM4CTRL_RETAINLFRCO_DEFAULT (_EMU_EM4CTRL_RETAINLFRCO_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ #define EMU_EM4CTRL_RETAINLFXO (0x1UL << 2) /**< LFXO Retain During EM4 */ #define _EMU_EM4CTRL_RETAINLFXO_SHIFT 2 /**< Shift value for EMU_RETAINLFXO */ #define _EMU_EM4CTRL_RETAINLFXO_MASK 0x4UL /**< Bit mask for EMU_RETAINLFXO */ #define _EMU_EM4CTRL_RETAINLFXO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ #define EMU_EM4CTRL_RETAINLFXO_DEFAULT (_EMU_EM4CTRL_RETAINLFXO_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ #define EMU_EM4CTRL_RETAINULFRCO (0x1UL << 3) /**< ULFRCO Retain During EM4S */ #define _EMU_EM4CTRL_RETAINULFRCO_SHIFT 3 /**< Shift value for EMU_RETAINULFRCO */ #define _EMU_EM4CTRL_RETAINULFRCO_MASK 0x8UL /**< Bit mask for EMU_RETAINULFRCO */ #define _EMU_EM4CTRL_RETAINULFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ #define EMU_EM4CTRL_RETAINULFRCO_DEFAULT (_EMU_EM4CTRL_RETAINULFRCO_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ #define _EMU_EM4CTRL_EM4IORETMODE_SHIFT 4 /**< Shift value for EMU_EM4IORETMODE */ #define _EMU_EM4CTRL_EM4IORETMODE_MASK 0x30UL /**< Bit mask for EMU_EM4IORETMODE */ #define _EMU_EM4CTRL_EM4IORETMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ #define _EMU_EM4CTRL_EM4IORETMODE_DISABLE 0x00000000UL /**< Mode DISABLE for EMU_EM4CTRL */ #define _EMU_EM4CTRL_EM4IORETMODE_EM4EXIT 0x00000001UL /**< Mode EM4EXIT for EMU_EM4CTRL */ #define _EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH 0x00000002UL /**< Mode SWUNLATCH for EMU_EM4CTRL */ #define EMU_EM4CTRL_EM4IORETMODE_DEFAULT (_EMU_EM4CTRL_EM4IORETMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ #define EMU_EM4CTRL_EM4IORETMODE_DISABLE (_EMU_EM4CTRL_EM4IORETMODE_DISABLE << 4) /**< Shifted mode DISABLE for EMU_EM4CTRL */ #define EMU_EM4CTRL_EM4IORETMODE_EM4EXIT (_EMU_EM4CTRL_EM4IORETMODE_EM4EXIT << 4) /**< Shifted mode EM4EXIT for EMU_EM4CTRL */ #define EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH (_EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH << 4) /**< Shifted mode SWUNLATCH for EMU_EM4CTRL */ #define _EMU_EM4CTRL_EM4ENTRY_SHIFT 16 /**< Shift value for EMU_EM4ENTRY */ #define _EMU_EM4CTRL_EM4ENTRY_MASK 0x30000UL /**< Bit mask for EMU_EM4ENTRY */ #define _EMU_EM4CTRL_EM4ENTRY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ #define EMU_EM4CTRL_EM4ENTRY_DEFAULT (_EMU_EM4CTRL_EM4ENTRY_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ /* Bit fields for EMU TEMPLIMITS */ #define _EMU_TEMPLIMITS_RESETVALUE 0x0000FF00UL /**< Default value for EMU_TEMPLIMITS */ #define _EMU_TEMPLIMITS_MASK 0x0001FFFFUL /**< Mask for EMU_TEMPLIMITS */ #define _EMU_TEMPLIMITS_TEMPLOW_SHIFT 0 /**< Shift value for EMU_TEMPLOW */ #define _EMU_TEMPLIMITS_TEMPLOW_MASK 0xFFUL /**< Bit mask for EMU_TEMPLOW */ #define _EMU_TEMPLIMITS_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMPLIMITS */ #define EMU_TEMPLIMITS_TEMPLOW_DEFAULT (_EMU_TEMPLIMITS_TEMPLOW_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ #define _EMU_TEMPLIMITS_TEMPHIGH_SHIFT 8 /**< Shift value for EMU_TEMPHIGH */ #define _EMU_TEMPLIMITS_TEMPHIGH_MASK 0xFF00UL /**< Bit mask for EMU_TEMPHIGH */ #define _EMU_TEMPLIMITS_TEMPHIGH_DEFAULT 0x000000FFUL /**< Mode DEFAULT for EMU_TEMPLIMITS */ #define EMU_TEMPLIMITS_TEMPHIGH_DEFAULT (_EMU_TEMPLIMITS_TEMPHIGH_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ #define EMU_TEMPLIMITS_EM4WUEN (0x1UL << 16) /**< Enable EM4 Wakeup Due to Low/high Temperature */ #define _EMU_TEMPLIMITS_EM4WUEN_SHIFT 16 /**< Shift value for EMU_EM4WUEN */ #define _EMU_TEMPLIMITS_EM4WUEN_MASK 0x10000UL /**< Bit mask for EMU_EM4WUEN */ #define _EMU_TEMPLIMITS_EM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMPLIMITS */ #define EMU_TEMPLIMITS_EM4WUEN_DEFAULT (_EMU_TEMPLIMITS_EM4WUEN_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ /* Bit fields for EMU TEMP */ #define _EMU_TEMP_RESETVALUE 0x00000000UL /**< Default value for EMU_TEMP */ #define _EMU_TEMP_MASK 0x000000FFUL /**< Mask for EMU_TEMP */ #define _EMU_TEMP_TEMP_SHIFT 0 /**< Shift value for EMU_TEMP */ #define _EMU_TEMP_TEMP_MASK 0xFFUL /**< Bit mask for EMU_TEMP */ #define _EMU_TEMP_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMP */ #define EMU_TEMP_TEMP_DEFAULT (_EMU_TEMP_TEMP_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMP */ /* Bit fields for EMU IF */ #define _EMU_IF_RESETVALUE 0x00000000UL /**< Default value for EMU_IF */ #define _EMU_IF_MASK 0xE31FC0FFUL /**< Mask for EMU_IF */ #define EMU_IF_VMONAVDDFALL (0x1UL << 0) /**< VMON AVDD Channel Fall */ #define _EMU_IF_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ #define _EMU_IF_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ #define _EMU_IF_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ #define EMU_IF_VMONAVDDFALL_DEFAULT (_EMU_IF_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IF */ #define EMU_IF_VMONAVDDRISE (0x1UL << 1) /**< VMON AVDD Channel Rise */ #define _EMU_IF_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ #define _EMU_IF_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ #define _EMU_IF_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ #define EMU_IF_VMONAVDDRISE_DEFAULT (_EMU_IF_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IF */ #define EMU_IF_VMONALTAVDDFALL (0x1UL << 2) /**< Alternate VMON AVDD Channel Fall */ #define _EMU_IF_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ #define _EMU_IF_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ #define _EMU_IF_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ #define EMU_IF_VMONALTAVDDFALL_DEFAULT (_EMU_IF_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IF */ #define EMU_IF_VMONALTAVDDRISE (0x1UL << 3) /**< Alternate VMON AVDD Channel Rise */ #define _EMU_IF_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ #define _EMU_IF_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ #define _EMU_IF_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ #define EMU_IF_VMONALTAVDDRISE_DEFAULT (_EMU_IF_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IF */ #define EMU_IF_VMONDVDDFALL (0x1UL << 4) /**< VMON DVDD Channel Fall */ #define _EMU_IF_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ #define _EMU_IF_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ #define _EMU_IF_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ #define EMU_IF_VMONDVDDFALL_DEFAULT (_EMU_IF_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IF */ #define EMU_IF_VMONDVDDRISE (0x1UL << 5) /**< VMON DVDD Channel Rise */ #define _EMU_IF_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ #define _EMU_IF_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ #define _EMU_IF_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ #define EMU_IF_VMONDVDDRISE_DEFAULT (_EMU_IF_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IF */ #define EMU_IF_VMONIO0FALL (0x1UL << 6) /**< VMON IOVDD0 Channel Fall */ #define _EMU_IF_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ #define _EMU_IF_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ #define _EMU_IF_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ #define EMU_IF_VMONIO0FALL_DEFAULT (_EMU_IF_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IF */ #define EMU_IF_VMONIO0RISE (0x1UL << 7) /**< VMON IOVDD0 Channel Rise */ #define _EMU_IF_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ #define _EMU_IF_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ #define _EMU_IF_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ #define EMU_IF_VMONIO0RISE_DEFAULT (_EMU_IF_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IF */ #define EMU_IF_VMONFVDDFALL (0x1UL << 14) /**< VMON VDDFLASH Channel Fall */ #define _EMU_IF_VMONFVDDFALL_SHIFT 14 /**< Shift value for EMU_VMONFVDDFALL */ #define _EMU_IF_VMONFVDDFALL_MASK 0x4000UL /**< Bit mask for EMU_VMONFVDDFALL */ #define _EMU_IF_VMONFVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ #define EMU_IF_VMONFVDDFALL_DEFAULT (_EMU_IF_VMONFVDDFALL_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_IF */ #define EMU_IF_VMONFVDDRISE (0x1UL << 15) /**< VMON VDDFLASH Channel Rise */ #define _EMU_IF_VMONFVDDRISE_SHIFT 15 /**< Shift value for EMU_VMONFVDDRISE */ #define _EMU_IF_VMONFVDDRISE_MASK 0x8000UL /**< Bit mask for EMU_VMONFVDDRISE */ #define _EMU_IF_VMONFVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ #define EMU_IF_VMONFVDDRISE_DEFAULT (_EMU_IF_VMONFVDDRISE_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_IF */ #define EMU_IF_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< PFET Current Limit Hit */ #define _EMU_IF_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ #define _EMU_IF_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ #define _EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ #define EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IF */ #define EMU_IF_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< NFET Current Limit Hit */ #define _EMU_IF_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ #define _EMU_IF_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ #define _EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ #define EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IF */ #define EMU_IF_DCDCLPRUNNING (0x1UL << 18) /**< LP Mode is Running */ #define _EMU_IF_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ #define _EMU_IF_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ #define _EMU_IF_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ #define EMU_IF_DCDCLPRUNNING_DEFAULT (_EMU_IF_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IF */ #define EMU_IF_DCDCLNRUNNING (0x1UL << 19) /**< LN Mode is Running */ #define _EMU_IF_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ #define _EMU_IF_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ #define _EMU_IF_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ #define EMU_IF_DCDCLNRUNNING_DEFAULT (_EMU_IF_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IF */ #define EMU_IF_DCDCINBYPASS (0x1UL << 20) /**< DCDC is in Bypass */ #define _EMU_IF_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ #define _EMU_IF_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ #define _EMU_IF_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ #define EMU_IF_DCDCINBYPASS_DEFAULT (_EMU_IF_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IF */ #define EMU_IF_EM23WAKEUP (0x1UL << 24) /**< Wakeup IRQ From EM2 and EM3 */ #define _EMU_IF_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ #define _EMU_IF_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ #define _EMU_IF_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ #define EMU_IF_EM23WAKEUP_DEFAULT (_EMU_IF_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IF */ #define EMU_IF_VSCALEDONE (0x1UL << 25) /**< Voltage Scale Steps Done IRQ */ #define _EMU_IF_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ #define _EMU_IF_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ #define _EMU_IF_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ #define EMU_IF_VSCALEDONE_DEFAULT (_EMU_IF_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IF */ #define EMU_IF_TEMP (0x1UL << 29) /**< New Temperature Measurement Valid */ #define _EMU_IF_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ #define _EMU_IF_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ #define _EMU_IF_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ #define EMU_IF_TEMP_DEFAULT (_EMU_IF_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IF */ #define EMU_IF_TEMPLOW (0x1UL << 30) /**< Temperature Low Limit Reached */ #define _EMU_IF_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ #define _EMU_IF_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ #define _EMU_IF_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ #define EMU_IF_TEMPLOW_DEFAULT (_EMU_IF_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IF */ #define EMU_IF_TEMPHIGH (0x1UL << 31) /**< Temperature High Limit Reached */ #define _EMU_IF_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ #define _EMU_IF_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ #define _EMU_IF_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ #define EMU_IF_TEMPHIGH_DEFAULT (_EMU_IF_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IF */ /* Bit fields for EMU IFS */ #define _EMU_IFS_RESETVALUE 0x00000000UL /**< Default value for EMU_IFS */ #define _EMU_IFS_MASK 0xE31FC0FFUL /**< Mask for EMU_IFS */ #define EMU_IFS_VMONAVDDFALL (0x1UL << 0) /**< Set VMONAVDDFALL Interrupt Flag */ #define _EMU_IFS_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ #define _EMU_IFS_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ #define _EMU_IFS_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ #define EMU_IFS_VMONAVDDFALL_DEFAULT (_EMU_IFS_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IFS */ #define EMU_IFS_VMONAVDDRISE (0x1UL << 1) /**< Set VMONAVDDRISE Interrupt Flag */ #define _EMU_IFS_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ #define _EMU_IFS_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ #define _EMU_IFS_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ #define EMU_IFS_VMONAVDDRISE_DEFAULT (_EMU_IFS_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IFS */ #define EMU_IFS_VMONALTAVDDFALL (0x1UL << 2) /**< Set VMONALTAVDDFALL Interrupt Flag */ #define _EMU_IFS_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ #define _EMU_IFS_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ #define _EMU_IFS_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ #define EMU_IFS_VMONALTAVDDFALL_DEFAULT (_EMU_IFS_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IFS */ #define EMU_IFS_VMONALTAVDDRISE (0x1UL << 3) /**< Set VMONALTAVDDRISE Interrupt Flag */ #define _EMU_IFS_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ #define _EMU_IFS_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ #define _EMU_IFS_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ #define EMU_IFS_VMONALTAVDDRISE_DEFAULT (_EMU_IFS_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IFS */ #define EMU_IFS_VMONDVDDFALL (0x1UL << 4) /**< Set VMONDVDDFALL Interrupt Flag */ #define _EMU_IFS_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ #define _EMU_IFS_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ #define _EMU_IFS_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ #define EMU_IFS_VMONDVDDFALL_DEFAULT (_EMU_IFS_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IFS */ #define EMU_IFS_VMONDVDDRISE (0x1UL << 5) /**< Set VMONDVDDRISE Interrupt Flag */ #define _EMU_IFS_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ #define _EMU_IFS_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ #define _EMU_IFS_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ #define EMU_IFS_VMONDVDDRISE_DEFAULT (_EMU_IFS_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IFS */ #define EMU_IFS_VMONIO0FALL (0x1UL << 6) /**< Set VMONIO0FALL Interrupt Flag */ #define _EMU_IFS_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ #define _EMU_IFS_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ #define _EMU_IFS_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ #define EMU_IFS_VMONIO0FALL_DEFAULT (_EMU_IFS_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IFS */ #define EMU_IFS_VMONIO0RISE (0x1UL << 7) /**< Set VMONIO0RISE Interrupt Flag */ #define _EMU_IFS_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ #define _EMU_IFS_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ #define _EMU_IFS_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ #define EMU_IFS_VMONIO0RISE_DEFAULT (_EMU_IFS_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IFS */ #define EMU_IFS_VMONFVDDFALL (0x1UL << 14) /**< Set VMONFVDDFALL Interrupt Flag */ #define _EMU_IFS_VMONFVDDFALL_SHIFT 14 /**< Shift value for EMU_VMONFVDDFALL */ #define _EMU_IFS_VMONFVDDFALL_MASK 0x4000UL /**< Bit mask for EMU_VMONFVDDFALL */ #define _EMU_IFS_VMONFVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ #define EMU_IFS_VMONFVDDFALL_DEFAULT (_EMU_IFS_VMONFVDDFALL_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_IFS */ #define EMU_IFS_VMONFVDDRISE (0x1UL << 15) /**< Set VMONFVDDRISE Interrupt Flag */ #define _EMU_IFS_VMONFVDDRISE_SHIFT 15 /**< Shift value for EMU_VMONFVDDRISE */ #define _EMU_IFS_VMONFVDDRISE_MASK 0x8000UL /**< Bit mask for EMU_VMONFVDDRISE */ #define _EMU_IFS_VMONFVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ #define EMU_IFS_VMONFVDDRISE_DEFAULT (_EMU_IFS_VMONFVDDRISE_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_IFS */ #define EMU_IFS_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< Set PFETOVERCURRENTLIMIT Interrupt Flag */ #define _EMU_IFS_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ #define _EMU_IFS_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ #define _EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ #define EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IFS */ #define EMU_IFS_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< Set NFETOVERCURRENTLIMIT Interrupt Flag */ #define _EMU_IFS_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ #define _EMU_IFS_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ #define _EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ #define EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IFS */ #define EMU_IFS_DCDCLPRUNNING (0x1UL << 18) /**< Set DCDCLPRUNNING Interrupt Flag */ #define _EMU_IFS_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ #define _EMU_IFS_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ #define _EMU_IFS_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ #define EMU_IFS_DCDCLPRUNNING_DEFAULT (_EMU_IFS_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IFS */ #define EMU_IFS_DCDCLNRUNNING (0x1UL << 19) /**< Set DCDCLNRUNNING Interrupt Flag */ #define _EMU_IFS_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ #define _EMU_IFS_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ #define _EMU_IFS_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ #define EMU_IFS_DCDCLNRUNNING_DEFAULT (_EMU_IFS_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IFS */ #define EMU_IFS_DCDCINBYPASS (0x1UL << 20) /**< Set DCDCINBYPASS Interrupt Flag */ #define _EMU_IFS_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ #define _EMU_IFS_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ #define _EMU_IFS_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ #define EMU_IFS_DCDCINBYPASS_DEFAULT (_EMU_IFS_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IFS */ #define EMU_IFS_EM23WAKEUP (0x1UL << 24) /**< Set EM23WAKEUP Interrupt Flag */ #define _EMU_IFS_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ #define _EMU_IFS_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ #define _EMU_IFS_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ #define EMU_IFS_EM23WAKEUP_DEFAULT (_EMU_IFS_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IFS */ #define EMU_IFS_VSCALEDONE (0x1UL << 25) /**< Set VSCALEDONE Interrupt Flag */ #define _EMU_IFS_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ #define _EMU_IFS_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ #define _EMU_IFS_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ #define EMU_IFS_VSCALEDONE_DEFAULT (_EMU_IFS_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IFS */ #define EMU_IFS_TEMP (0x1UL << 29) /**< Set TEMP Interrupt Flag */ #define _EMU_IFS_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ #define _EMU_IFS_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ #define _EMU_IFS_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ #define EMU_IFS_TEMP_DEFAULT (_EMU_IFS_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IFS */ #define EMU_IFS_TEMPLOW (0x1UL << 30) /**< Set TEMPLOW Interrupt Flag */ #define _EMU_IFS_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ #define _EMU_IFS_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ #define _EMU_IFS_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ #define EMU_IFS_TEMPLOW_DEFAULT (_EMU_IFS_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IFS */ #define EMU_IFS_TEMPHIGH (0x1UL << 31) /**< Set TEMPHIGH Interrupt Flag */ #define _EMU_IFS_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ #define _EMU_IFS_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ #define _EMU_IFS_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ #define EMU_IFS_TEMPHIGH_DEFAULT (_EMU_IFS_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IFS */ /* Bit fields for EMU IFC */ #define _EMU_IFC_RESETVALUE 0x00000000UL /**< Default value for EMU_IFC */ #define _EMU_IFC_MASK 0xE31FC0FFUL /**< Mask for EMU_IFC */ #define EMU_IFC_VMONAVDDFALL (0x1UL << 0) /**< Clear VMONAVDDFALL Interrupt Flag */ #define _EMU_IFC_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ #define _EMU_IFC_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ #define _EMU_IFC_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ #define EMU_IFC_VMONAVDDFALL_DEFAULT (_EMU_IFC_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IFC */ #define EMU_IFC_VMONAVDDRISE (0x1UL << 1) /**< Clear VMONAVDDRISE Interrupt Flag */ #define _EMU_IFC_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ #define _EMU_IFC_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ #define _EMU_IFC_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ #define EMU_IFC_VMONAVDDRISE_DEFAULT (_EMU_IFC_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IFC */ #define EMU_IFC_VMONALTAVDDFALL (0x1UL << 2) /**< Clear VMONALTAVDDFALL Interrupt Flag */ #define _EMU_IFC_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ #define _EMU_IFC_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ #define _EMU_IFC_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ #define EMU_IFC_VMONALTAVDDFALL_DEFAULT (_EMU_IFC_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IFC */ #define EMU_IFC_VMONALTAVDDRISE (0x1UL << 3) /**< Clear VMONALTAVDDRISE Interrupt Flag */ #define _EMU_IFC_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ #define _EMU_IFC_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ #define _EMU_IFC_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ #define EMU_IFC_VMONALTAVDDRISE_DEFAULT (_EMU_IFC_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IFC */ #define EMU_IFC_VMONDVDDFALL (0x1UL << 4) /**< Clear VMONDVDDFALL Interrupt Flag */ #define _EMU_IFC_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ #define _EMU_IFC_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ #define _EMU_IFC_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ #define EMU_IFC_VMONDVDDFALL_DEFAULT (_EMU_IFC_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IFC */ #define EMU_IFC_VMONDVDDRISE (0x1UL << 5) /**< Clear VMONDVDDRISE Interrupt Flag */ #define _EMU_IFC_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ #define _EMU_IFC_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ #define _EMU_IFC_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ #define EMU_IFC_VMONDVDDRISE_DEFAULT (_EMU_IFC_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IFC */ #define EMU_IFC_VMONIO0FALL (0x1UL << 6) /**< Clear VMONIO0FALL Interrupt Flag */ #define _EMU_IFC_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ #define _EMU_IFC_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ #define _EMU_IFC_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ #define EMU_IFC_VMONIO0FALL_DEFAULT (_EMU_IFC_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IFC */ #define EMU_IFC_VMONIO0RISE (0x1UL << 7) /**< Clear VMONIO0RISE Interrupt Flag */ #define _EMU_IFC_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ #define _EMU_IFC_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ #define _EMU_IFC_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ #define EMU_IFC_VMONIO0RISE_DEFAULT (_EMU_IFC_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IFC */ #define EMU_IFC_VMONFVDDFALL (0x1UL << 14) /**< Clear VMONFVDDFALL Interrupt Flag */ #define _EMU_IFC_VMONFVDDFALL_SHIFT 14 /**< Shift value for EMU_VMONFVDDFALL */ #define _EMU_IFC_VMONFVDDFALL_MASK 0x4000UL /**< Bit mask for EMU_VMONFVDDFALL */ #define _EMU_IFC_VMONFVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ #define EMU_IFC_VMONFVDDFALL_DEFAULT (_EMU_IFC_VMONFVDDFALL_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_IFC */ #define EMU_IFC_VMONFVDDRISE (0x1UL << 15) /**< Clear VMONFVDDRISE Interrupt Flag */ #define _EMU_IFC_VMONFVDDRISE_SHIFT 15 /**< Shift value for EMU_VMONFVDDRISE */ #define _EMU_IFC_VMONFVDDRISE_MASK 0x8000UL /**< Bit mask for EMU_VMONFVDDRISE */ #define _EMU_IFC_VMONFVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ #define EMU_IFC_VMONFVDDRISE_DEFAULT (_EMU_IFC_VMONFVDDRISE_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_IFC */ #define EMU_IFC_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< Clear PFETOVERCURRENTLIMIT Interrupt Flag */ #define _EMU_IFC_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ #define _EMU_IFC_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ #define _EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ #define EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IFC */ #define EMU_IFC_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< Clear NFETOVERCURRENTLIMIT Interrupt Flag */ #define _EMU_IFC_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ #define _EMU_IFC_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ #define _EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ #define EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IFC */ #define EMU_IFC_DCDCLPRUNNING (0x1UL << 18) /**< Clear DCDCLPRUNNING Interrupt Flag */ #define _EMU_IFC_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ #define _EMU_IFC_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ #define _EMU_IFC_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ #define EMU_IFC_DCDCLPRUNNING_DEFAULT (_EMU_IFC_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IFC */ #define EMU_IFC_DCDCLNRUNNING (0x1UL << 19) /**< Clear DCDCLNRUNNING Interrupt Flag */ #define _EMU_IFC_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ #define _EMU_IFC_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ #define _EMU_IFC_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ #define EMU_IFC_DCDCLNRUNNING_DEFAULT (_EMU_IFC_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IFC */ #define EMU_IFC_DCDCINBYPASS (0x1UL << 20) /**< Clear DCDCINBYPASS Interrupt Flag */ #define _EMU_IFC_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ #define _EMU_IFC_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ #define _EMU_IFC_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ #define EMU_IFC_DCDCINBYPASS_DEFAULT (_EMU_IFC_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IFC */ #define EMU_IFC_EM23WAKEUP (0x1UL << 24) /**< Clear EM23WAKEUP Interrupt Flag */ #define _EMU_IFC_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ #define _EMU_IFC_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ #define _EMU_IFC_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ #define EMU_IFC_EM23WAKEUP_DEFAULT (_EMU_IFC_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IFC */ #define EMU_IFC_VSCALEDONE (0x1UL << 25) /**< Clear VSCALEDONE Interrupt Flag */ #define _EMU_IFC_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ #define _EMU_IFC_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ #define _EMU_IFC_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ #define EMU_IFC_VSCALEDONE_DEFAULT (_EMU_IFC_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IFC */ #define EMU_IFC_TEMP (0x1UL << 29) /**< Clear TEMP Interrupt Flag */ #define _EMU_IFC_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ #define _EMU_IFC_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ #define _EMU_IFC_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ #define EMU_IFC_TEMP_DEFAULT (_EMU_IFC_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IFC */ #define EMU_IFC_TEMPLOW (0x1UL << 30) /**< Clear TEMPLOW Interrupt Flag */ #define _EMU_IFC_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ #define _EMU_IFC_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ #define _EMU_IFC_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ #define EMU_IFC_TEMPLOW_DEFAULT (_EMU_IFC_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IFC */ #define EMU_IFC_TEMPHIGH (0x1UL << 31) /**< Clear TEMPHIGH Interrupt Flag */ #define _EMU_IFC_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ #define _EMU_IFC_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ #define _EMU_IFC_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ #define EMU_IFC_TEMPHIGH_DEFAULT (_EMU_IFC_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IFC */ /* Bit fields for EMU IEN */ #define _EMU_IEN_RESETVALUE 0x00000000UL /**< Default value for EMU_IEN */ #define _EMU_IEN_MASK 0xE31FC0FFUL /**< Mask for EMU_IEN */ #define EMU_IEN_VMONAVDDFALL (0x1UL << 0) /**< VMONAVDDFALL Interrupt Enable */ #define _EMU_IEN_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ #define _EMU_IEN_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ #define _EMU_IEN_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ #define EMU_IEN_VMONAVDDFALL_DEFAULT (_EMU_IEN_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IEN */ #define EMU_IEN_VMONAVDDRISE (0x1UL << 1) /**< VMONAVDDRISE Interrupt Enable */ #define _EMU_IEN_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ #define _EMU_IEN_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ #define _EMU_IEN_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ #define EMU_IEN_VMONAVDDRISE_DEFAULT (_EMU_IEN_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IEN */ #define EMU_IEN_VMONALTAVDDFALL (0x1UL << 2) /**< VMONALTAVDDFALL Interrupt Enable */ #define _EMU_IEN_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ #define _EMU_IEN_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ #define _EMU_IEN_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ #define EMU_IEN_VMONALTAVDDFALL_DEFAULT (_EMU_IEN_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IEN */ #define EMU_IEN_VMONALTAVDDRISE (0x1UL << 3) /**< VMONALTAVDDRISE Interrupt Enable */ #define _EMU_IEN_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ #define _EMU_IEN_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ #define _EMU_IEN_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ #define EMU_IEN_VMONALTAVDDRISE_DEFAULT (_EMU_IEN_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IEN */ #define EMU_IEN_VMONDVDDFALL (0x1UL << 4) /**< VMONDVDDFALL Interrupt Enable */ #define _EMU_IEN_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ #define _EMU_IEN_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ #define _EMU_IEN_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ #define EMU_IEN_VMONDVDDFALL_DEFAULT (_EMU_IEN_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IEN */ #define EMU_IEN_VMONDVDDRISE (0x1UL << 5) /**< VMONDVDDRISE Interrupt Enable */ #define _EMU_IEN_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ #define _EMU_IEN_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ #define _EMU_IEN_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ #define EMU_IEN_VMONDVDDRISE_DEFAULT (_EMU_IEN_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IEN */ #define EMU_IEN_VMONIO0FALL (0x1UL << 6) /**< VMONIO0FALL Interrupt Enable */ #define _EMU_IEN_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ #define _EMU_IEN_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ #define _EMU_IEN_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ #define EMU_IEN_VMONIO0FALL_DEFAULT (_EMU_IEN_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IEN */ #define EMU_IEN_VMONIO0RISE (0x1UL << 7) /**< VMONIO0RISE Interrupt Enable */ #define _EMU_IEN_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ #define _EMU_IEN_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ #define _EMU_IEN_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ #define EMU_IEN_VMONIO0RISE_DEFAULT (_EMU_IEN_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IEN */ #define EMU_IEN_VMONFVDDFALL (0x1UL << 14) /**< VMONFVDDFALL Interrupt Enable */ #define _EMU_IEN_VMONFVDDFALL_SHIFT 14 /**< Shift value for EMU_VMONFVDDFALL */ #define _EMU_IEN_VMONFVDDFALL_MASK 0x4000UL /**< Bit mask for EMU_VMONFVDDFALL */ #define _EMU_IEN_VMONFVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ #define EMU_IEN_VMONFVDDFALL_DEFAULT (_EMU_IEN_VMONFVDDFALL_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_IEN */ #define EMU_IEN_VMONFVDDRISE (0x1UL << 15) /**< VMONFVDDRISE Interrupt Enable */ #define _EMU_IEN_VMONFVDDRISE_SHIFT 15 /**< Shift value for EMU_VMONFVDDRISE */ #define _EMU_IEN_VMONFVDDRISE_MASK 0x8000UL /**< Bit mask for EMU_VMONFVDDRISE */ #define _EMU_IEN_VMONFVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ #define EMU_IEN_VMONFVDDRISE_DEFAULT (_EMU_IEN_VMONFVDDRISE_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_IEN */ #define EMU_IEN_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< PFETOVERCURRENTLIMIT Interrupt Enable */ #define _EMU_IEN_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ #define _EMU_IEN_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ #define _EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ #define EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IEN */ #define EMU_IEN_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< NFETOVERCURRENTLIMIT Interrupt Enable */ #define _EMU_IEN_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ #define _EMU_IEN_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ #define _EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ #define EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IEN */ #define EMU_IEN_DCDCLPRUNNING (0x1UL << 18) /**< DCDCLPRUNNING Interrupt Enable */ #define _EMU_IEN_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ #define _EMU_IEN_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ #define _EMU_IEN_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ #define EMU_IEN_DCDCLPRUNNING_DEFAULT (_EMU_IEN_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IEN */ #define EMU_IEN_DCDCLNRUNNING (0x1UL << 19) /**< DCDCLNRUNNING Interrupt Enable */ #define _EMU_IEN_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ #define _EMU_IEN_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ #define _EMU_IEN_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ #define EMU_IEN_DCDCLNRUNNING_DEFAULT (_EMU_IEN_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IEN */ #define EMU_IEN_DCDCINBYPASS (0x1UL << 20) /**< DCDCINBYPASS Interrupt Enable */ #define _EMU_IEN_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ #define _EMU_IEN_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ #define _EMU_IEN_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ #define EMU_IEN_DCDCINBYPASS_DEFAULT (_EMU_IEN_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IEN */ #define EMU_IEN_EM23WAKEUP (0x1UL << 24) /**< EM23WAKEUP Interrupt Enable */ #define _EMU_IEN_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ #define _EMU_IEN_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ #define _EMU_IEN_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ #define EMU_IEN_EM23WAKEUP_DEFAULT (_EMU_IEN_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IEN */ #define EMU_IEN_VSCALEDONE (0x1UL << 25) /**< VSCALEDONE Interrupt Enable */ #define _EMU_IEN_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ #define _EMU_IEN_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ #define _EMU_IEN_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ #define EMU_IEN_VSCALEDONE_DEFAULT (_EMU_IEN_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IEN */ #define EMU_IEN_TEMP (0x1UL << 29) /**< TEMP Interrupt Enable */ #define _EMU_IEN_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ #define _EMU_IEN_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ #define _EMU_IEN_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ #define EMU_IEN_TEMP_DEFAULT (_EMU_IEN_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IEN */ #define EMU_IEN_TEMPLOW (0x1UL << 30) /**< TEMPLOW Interrupt Enable */ #define _EMU_IEN_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ #define _EMU_IEN_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ #define _EMU_IEN_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ #define EMU_IEN_TEMPLOW_DEFAULT (_EMU_IEN_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IEN */ #define EMU_IEN_TEMPHIGH (0x1UL << 31) /**< TEMPHIGH Interrupt Enable */ #define _EMU_IEN_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ #define _EMU_IEN_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ #define _EMU_IEN_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ #define EMU_IEN_TEMPHIGH_DEFAULT (_EMU_IEN_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IEN */ /* Bit fields for EMU PWRLOCK */ #define _EMU_PWRLOCK_RESETVALUE 0x00000000UL /**< Default value for EMU_PWRLOCK */ #define _EMU_PWRLOCK_MASK 0x0000FFFFUL /**< Mask for EMU_PWRLOCK */ #define _EMU_PWRLOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */ #define _EMU_PWRLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */ #define _EMU_PWRLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRLOCK */ #define _EMU_PWRLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_PWRLOCK */ #define _EMU_PWRLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_PWRLOCK */ #define _EMU_PWRLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_PWRLOCK */ #define _EMU_PWRLOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_PWRLOCK */ #define EMU_PWRLOCK_LOCKKEY_DEFAULT (_EMU_PWRLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_PWRLOCK */ #define EMU_PWRLOCK_LOCKKEY_LOCK (_EMU_PWRLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_PWRLOCK */ #define EMU_PWRLOCK_LOCKKEY_UNLOCKED (_EMU_PWRLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_PWRLOCK */ #define EMU_PWRLOCK_LOCKKEY_LOCKED (_EMU_PWRLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_PWRLOCK */ #define EMU_PWRLOCK_LOCKKEY_UNLOCK (_EMU_PWRLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_PWRLOCK */ /* Bit fields for EMU PWRCFG */ #define _EMU_PWRCFG_RESETVALUE 0x00000000UL /**< Default value for EMU_PWRCFG */ #define _EMU_PWRCFG_MASK 0x0000000FUL /**< Mask for EMU_PWRCFG */ #define _EMU_PWRCFG_PWRCFG_SHIFT 0 /**< Shift value for EMU_PWRCFG */ #define _EMU_PWRCFG_PWRCFG_MASK 0xFUL /**< Bit mask for EMU_PWRCFG */ #define _EMU_PWRCFG_PWRCFG_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCFG */ #define _EMU_PWRCFG_PWRCFG_UNCONFIGURED 0x00000000UL /**< Mode UNCONFIGURED for EMU_PWRCFG */ #define _EMU_PWRCFG_PWRCFG_DCDCTODVDD 0x00000002UL /**< Mode DCDCTODVDD for EMU_PWRCFG */ #define EMU_PWRCFG_PWRCFG_DEFAULT (_EMU_PWRCFG_PWRCFG_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_PWRCFG */ #define EMU_PWRCFG_PWRCFG_UNCONFIGURED (_EMU_PWRCFG_PWRCFG_UNCONFIGURED << 0) /**< Shifted mode UNCONFIGURED for EMU_PWRCFG */ #define EMU_PWRCFG_PWRCFG_DCDCTODVDD (_EMU_PWRCFG_PWRCFG_DCDCTODVDD << 0) /**< Shifted mode DCDCTODVDD for EMU_PWRCFG */ /* Bit fields for EMU PWRCTRL */ #define _EMU_PWRCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_PWRCTRL */ #define _EMU_PWRCTRL_MASK 0x00001420UL /**< Mask for EMU_PWRCTRL */ #define EMU_PWRCTRL_ANASW (0x1UL << 5) /**< Analog Switch Selection */ #define _EMU_PWRCTRL_ANASW_SHIFT 5 /**< Shift value for EMU_ANASW */ #define _EMU_PWRCTRL_ANASW_MASK 0x20UL /**< Bit mask for EMU_ANASW */ #define _EMU_PWRCTRL_ANASW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */ #define _EMU_PWRCTRL_ANASW_AVDD 0x00000000UL /**< Mode AVDD for EMU_PWRCTRL */ #define _EMU_PWRCTRL_ANASW_DVDD 0x00000001UL /**< Mode DVDD for EMU_PWRCTRL */ #define EMU_PWRCTRL_ANASW_DEFAULT (_EMU_PWRCTRL_ANASW_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_PWRCTRL */ #define EMU_PWRCTRL_ANASW_AVDD (_EMU_PWRCTRL_ANASW_AVDD << 5) /**< Shifted mode AVDD for EMU_PWRCTRL */ #define EMU_PWRCTRL_ANASW_DVDD (_EMU_PWRCTRL_ANASW_DVDD << 5) /**< Shifted mode DVDD for EMU_PWRCTRL */ #define EMU_PWRCTRL_REGPWRSEL (0x1UL << 10) /**< This Field Selects the Input Supply Pin for the Digital LDO */ #define _EMU_PWRCTRL_REGPWRSEL_SHIFT 10 /**< Shift value for EMU_REGPWRSEL */ #define _EMU_PWRCTRL_REGPWRSEL_MASK 0x400UL /**< Bit mask for EMU_REGPWRSEL */ #define _EMU_PWRCTRL_REGPWRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */ #define _EMU_PWRCTRL_REGPWRSEL_AVDD 0x00000000UL /**< Mode AVDD for EMU_PWRCTRL */ #define _EMU_PWRCTRL_REGPWRSEL_DVDD 0x00000001UL /**< Mode DVDD for EMU_PWRCTRL */ #define EMU_PWRCTRL_REGPWRSEL_DEFAULT (_EMU_PWRCTRL_REGPWRSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_PWRCTRL */ #define EMU_PWRCTRL_REGPWRSEL_AVDD (_EMU_PWRCTRL_REGPWRSEL_AVDD << 10) /**< Shifted mode AVDD for EMU_PWRCTRL */ #define EMU_PWRCTRL_REGPWRSEL_DVDD (_EMU_PWRCTRL_REGPWRSEL_DVDD << 10) /**< Shifted mode DVDD for EMU_PWRCTRL */ #define EMU_PWRCTRL_DVDDBODDIS (0x1UL << 12) /**< DVDD BOD Disable */ #define _EMU_PWRCTRL_DVDDBODDIS_SHIFT 12 /**< Shift value for EMU_DVDDBODDIS */ #define _EMU_PWRCTRL_DVDDBODDIS_MASK 0x1000UL /**< Bit mask for EMU_DVDDBODDIS */ #define _EMU_PWRCTRL_DVDDBODDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */ #define EMU_PWRCTRL_DVDDBODDIS_DEFAULT (_EMU_PWRCTRL_DVDDBODDIS_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_PWRCTRL */ /* Bit fields for EMU DCDCCTRL */ #define _EMU_DCDCCTRL_RESETVALUE 0x00000033UL /**< Default value for EMU_DCDCCTRL */ #define _EMU_DCDCCTRL_MASK 0x00000033UL /**< Mask for EMU_DCDCCTRL */ #define _EMU_DCDCCTRL_DCDCMODE_SHIFT 0 /**< Shift value for EMU_DCDCMODE */ #define _EMU_DCDCCTRL_DCDCMODE_MASK 0x3UL /**< Bit mask for EMU_DCDCMODE */ #define _EMU_DCDCCTRL_DCDCMODE_BYPASS 0x00000000UL /**< Mode BYPASS for EMU_DCDCCTRL */ #define _EMU_DCDCCTRL_DCDCMODE_LOWNOISE 0x00000001UL /**< Mode LOWNOISE for EMU_DCDCCTRL */ #define _EMU_DCDCCTRL_DCDCMODE_LOWPOWER 0x00000002UL /**< Mode LOWPOWER for EMU_DCDCCTRL */ #define _EMU_DCDCCTRL_DCDCMODE_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCCTRL */ #define _EMU_DCDCCTRL_DCDCMODE_OFF 0x00000003UL /**< Mode OFF for EMU_DCDCCTRL */ #define EMU_DCDCCTRL_DCDCMODE_BYPASS (_EMU_DCDCCTRL_DCDCMODE_BYPASS << 0) /**< Shifted mode BYPASS for EMU_DCDCCTRL */ #define EMU_DCDCCTRL_DCDCMODE_LOWNOISE (_EMU_DCDCCTRL_DCDCMODE_LOWNOISE << 0) /**< Shifted mode LOWNOISE for EMU_DCDCCTRL */ #define EMU_DCDCCTRL_DCDCMODE_LOWPOWER (_EMU_DCDCCTRL_DCDCMODE_LOWPOWER << 0) /**< Shifted mode LOWPOWER for EMU_DCDCCTRL */ #define EMU_DCDCCTRL_DCDCMODE_DEFAULT (_EMU_DCDCCTRL_DCDCMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */ #define EMU_DCDCCTRL_DCDCMODE_OFF (_EMU_DCDCCTRL_DCDCMODE_OFF << 0) /**< Shifted mode OFF for EMU_DCDCCTRL */ #define EMU_DCDCCTRL_DCDCMODEEM23 (0x1UL << 4) /**< DCDC Mode EM23 */ #define _EMU_DCDCCTRL_DCDCMODEEM23_SHIFT 4 /**< Shift value for EMU_DCDCMODEEM23 */ #define _EMU_DCDCCTRL_DCDCMODEEM23_MASK 0x10UL /**< Bit mask for EMU_DCDCMODEEM23 */ #define _EMU_DCDCCTRL_DCDCMODEEM23_EM23SW 0x00000000UL /**< Mode EM23SW for EMU_DCDCCTRL */ #define _EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCTRL */ #define _EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER 0x00000001UL /**< Mode EM23LOWPOWER for EMU_DCDCCTRL */ #define EMU_DCDCCTRL_DCDCMODEEM23_EM23SW (_EMU_DCDCCTRL_DCDCMODEEM23_EM23SW << 4) /**< Shifted mode EM23SW for EMU_DCDCCTRL */ #define EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT (_EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */ #define EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER (_EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER << 4) /**< Shifted mode EM23LOWPOWER for EMU_DCDCCTRL */ #define EMU_DCDCCTRL_DCDCMODEEM4 (0x1UL << 5) /**< DCDC Mode EM4H */ #define _EMU_DCDCCTRL_DCDCMODEEM4_SHIFT 5 /**< Shift value for EMU_DCDCMODEEM4 */ #define _EMU_DCDCCTRL_DCDCMODEEM4_MASK 0x20UL /**< Bit mask for EMU_DCDCMODEEM4 */ #define _EMU_DCDCCTRL_DCDCMODEEM4_EM4SW 0x00000000UL /**< Mode EM4SW for EMU_DCDCCTRL */ #define _EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCTRL */ #define _EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER 0x00000001UL /**< Mode EM4LOWPOWER for EMU_DCDCCTRL */ #define EMU_DCDCCTRL_DCDCMODEEM4_EM4SW (_EMU_DCDCCTRL_DCDCMODEEM4_EM4SW << 5) /**< Shifted mode EM4SW for EMU_DCDCCTRL */ #define EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT (_EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */ #define EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER (_EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER << 5) /**< Shifted mode EM4LOWPOWER for EMU_DCDCCTRL */ /* Bit fields for EMU DCDCMISCCTRL */ #define _EMU_DCDCMISCCTRL_RESETVALUE 0x03107706UL /**< Default value for EMU_DCDCMISCCTRL */ #define _EMU_DCDCMISCCTRL_MASK 0x377FFF27UL /**< Mask for EMU_DCDCMISCCTRL */ #define EMU_DCDCMISCCTRL_LNFORCECCM (0x1UL << 0) /**< Force DCDC Into CCM Mode in Low Noise Operation */ #define _EMU_DCDCMISCCTRL_LNFORCECCM_SHIFT 0 /**< Shift value for EMU_LNFORCECCM */ #define _EMU_DCDCMISCCTRL_LNFORCECCM_MASK 0x1UL /**< Bit mask for EMU_LNFORCECCM */ #define _EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ #define EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT (_EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ #define EMU_DCDCMISCCTRL_LPCMPHYSDIS (0x1UL << 1) /**< Disable LP Mode Hysteresis in the State Machine Control */ #define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_SHIFT 1 /**< Shift value for EMU_LPCMPHYSDIS */ #define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_MASK 0x2UL /**< Bit mask for EMU_LPCMPHYSDIS */ #define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ #define EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ #define EMU_DCDCMISCCTRL_LPCMPHYSHI (0x1UL << 2) /**< Comparator Threshold on the High Side */ #define _EMU_DCDCMISCCTRL_LPCMPHYSHI_SHIFT 2 /**< Shift value for EMU_LPCMPHYSHI */ #define _EMU_DCDCMISCCTRL_LPCMPHYSHI_MASK 0x4UL /**< Bit mask for EMU_LPCMPHYSHI */ #define _EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ #define EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ #define EMU_DCDCMISCCTRL_LNFORCECCMIMM (0x1UL << 5) /**< Force DCDC Into CCM Mode Immediately, Based on LNFORCECCM */ #define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_SHIFT 5 /**< Shift value for EMU_LNFORCECCMIMM */ #define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_MASK 0x20UL /**< Bit mask for EMU_LNFORCECCMIMM */ #define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ #define EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT (_EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ #define _EMU_DCDCMISCCTRL_PFETCNT_SHIFT 8 /**< Shift value for EMU_PFETCNT */ #define _EMU_DCDCMISCCTRL_PFETCNT_MASK 0xF00UL /**< Bit mask for EMU_PFETCNT */ #define _EMU_DCDCMISCCTRL_PFETCNT_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ #define EMU_DCDCMISCCTRL_PFETCNT_DEFAULT (_EMU_DCDCMISCCTRL_PFETCNT_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ #define _EMU_DCDCMISCCTRL_NFETCNT_SHIFT 12 /**< Shift value for EMU_NFETCNT */ #define _EMU_DCDCMISCCTRL_NFETCNT_MASK 0xF000UL /**< Bit mask for EMU_NFETCNT */ #define _EMU_DCDCMISCCTRL_NFETCNT_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ #define EMU_DCDCMISCCTRL_NFETCNT_DEFAULT (_EMU_DCDCMISCCTRL_NFETCNT_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ #define _EMU_DCDCMISCCTRL_BYPLIMSEL_SHIFT 16 /**< Shift value for EMU_BYPLIMSEL */ #define _EMU_DCDCMISCCTRL_BYPLIMSEL_MASK 0xF0000UL /**< Bit mask for EMU_BYPLIMSEL */ #define _EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ #define EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ #define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_SHIFT 20 /**< Shift value for EMU_LPCLIMILIMSEL */ #define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_MASK 0x700000UL /**< Bit mask for EMU_LPCLIMILIMSEL */ #define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ #define EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ #define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_SHIFT 24 /**< Shift value for EMU_LNCLIMILIMSEL */ #define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_MASK 0x7000000UL /**< Bit mask for EMU_LNCLIMILIMSEL */ #define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ #define EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ #define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT 28 /**< Shift value for EMU_LPCMPBIASEM234H */ #define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_MASK 0x30000000UL /**< Bit mask for EMU_LPCMPBIASEM234H */ #define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ #define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 0x00000000UL /**< Mode BIAS0 for EMU_DCDCMISCCTRL */ #define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 0x00000001UL /**< Mode BIAS1 for EMU_DCDCMISCCTRL */ #define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 0x00000002UL /**< Mode BIAS2 for EMU_DCDCMISCCTRL */ #define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 0x00000003UL /**< Mode BIAS3 for EMU_DCDCMISCCTRL */ #define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT << 28) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ #define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 << 28) /**< Shifted mode BIAS0 for EMU_DCDCMISCCTRL */ #define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 << 28) /**< Shifted mode BIAS1 for EMU_DCDCMISCCTRL */ #define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 << 28) /**< Shifted mode BIAS2 for EMU_DCDCMISCCTRL */ #define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 << 28) /**< Shifted mode BIAS3 for EMU_DCDCMISCCTRL */ /* Bit fields for EMU DCDCZDETCTRL */ #define _EMU_DCDCZDETCTRL_RESETVALUE 0x00000150UL /**< Default value for EMU_DCDCZDETCTRL */ #define _EMU_DCDCZDETCTRL_MASK 0x00000370UL /**< Mask for EMU_DCDCZDETCTRL */ #define _EMU_DCDCZDETCTRL_ZDETILIMSEL_SHIFT 4 /**< Shift value for EMU_ZDETILIMSEL */ #define _EMU_DCDCZDETCTRL_ZDETILIMSEL_MASK 0x70UL /**< Bit mask for EMU_ZDETILIMSEL */ #define _EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT 0x00000005UL /**< Mode DEFAULT for EMU_DCDCZDETCTRL */ #define EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT (_EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCZDETCTRL */ #define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_SHIFT 8 /**< Shift value for EMU_ZDETBLANKDLY */ #define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_MASK 0x300UL /**< Bit mask for EMU_ZDETBLANKDLY */ #define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCZDETCTRL */ #define EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT (_EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCZDETCTRL */ /* Bit fields for EMU DCDCCLIMCTRL */ #define _EMU_DCDCCLIMCTRL_RESETVALUE 0x00000100UL /**< Default value for EMU_DCDCCLIMCTRL */ #define _EMU_DCDCCLIMCTRL_MASK 0x00002300UL /**< Mask for EMU_DCDCCLIMCTRL */ #define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_SHIFT 8 /**< Shift value for EMU_CLIMBLANKDLY */ #define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_MASK 0x300UL /**< Bit mask for EMU_CLIMBLANKDLY */ #define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCLIMCTRL */ #define EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT (_EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCCLIMCTRL */ #define EMU_DCDCCLIMCTRL_BYPLIMEN (0x1UL << 13) /**< Bypass Current Limit Enable */ #define _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT 13 /**< Shift value for EMU_BYPLIMEN */ #define _EMU_DCDCCLIMCTRL_BYPLIMEN_MASK 0x2000UL /**< Bit mask for EMU_BYPLIMEN */ #define _EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCCLIMCTRL */ #define EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT (_EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_DCDCCLIMCTRL */ /* Bit fields for EMU DCDCLNCOMPCTRL */ #define _EMU_DCDCLNCOMPCTRL_RESETVALUE 0x57204077UL /**< Default value for EMU_DCDCLNCOMPCTRL */ #define _EMU_DCDCLNCOMPCTRL_MASK 0xF730F1F7UL /**< Mask for EMU_DCDCLNCOMPCTRL */ #define _EMU_DCDCLNCOMPCTRL_COMPENR1_SHIFT 0 /**< Shift value for EMU_COMPENR1 */ #define _EMU_DCDCLNCOMPCTRL_COMPENR1_MASK 0x7UL /**< Bit mask for EMU_COMPENR1 */ #define _EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ #define EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ #define _EMU_DCDCLNCOMPCTRL_COMPENR2_SHIFT 4 /**< Shift value for EMU_COMPENR2 */ #define _EMU_DCDCLNCOMPCTRL_COMPENR2_MASK 0x1F0UL /**< Bit mask for EMU_COMPENR2 */ #define _EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ #define EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ #define _EMU_DCDCLNCOMPCTRL_COMPENR3_SHIFT 12 /**< Shift value for EMU_COMPENR3 */ #define _EMU_DCDCLNCOMPCTRL_COMPENR3_MASK 0xF000UL /**< Bit mask for EMU_COMPENR3 */ #define _EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT 0x00000004UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ #define EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ #define _EMU_DCDCLNCOMPCTRL_COMPENC1_SHIFT 20 /**< Shift value for EMU_COMPENC1 */ #define _EMU_DCDCLNCOMPCTRL_COMPENC1_MASK 0x300000UL /**< Bit mask for EMU_COMPENC1 */ #define _EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT 0x00000002UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ #define EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ #define _EMU_DCDCLNCOMPCTRL_COMPENC2_SHIFT 24 /**< Shift value for EMU_COMPENC2 */ #define _EMU_DCDCLNCOMPCTRL_COMPENC2_MASK 0x7000000UL /**< Bit mask for EMU_COMPENC2 */ #define _EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ #define EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ #define _EMU_DCDCLNCOMPCTRL_COMPENC3_SHIFT 28 /**< Shift value for EMU_COMPENC3 */ #define _EMU_DCDCLNCOMPCTRL_COMPENC3_MASK 0xF0000000UL /**< Bit mask for EMU_COMPENC3 */ #define _EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT 0x00000005UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ #define EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT << 28) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ /* Bit fields for EMU DCDCLNVCTRL */ #define _EMU_DCDCLNVCTRL_RESETVALUE 0x00007100UL /**< Default value for EMU_DCDCLNVCTRL */ #define _EMU_DCDCLNVCTRL_MASK 0x00007F02UL /**< Mask for EMU_DCDCLNVCTRL */ #define EMU_DCDCLNVCTRL_LNATT (0x1UL << 1) /**< Low Noise Mode Feedback Attenuation */ #define _EMU_DCDCLNVCTRL_LNATT_SHIFT 1 /**< Shift value for EMU_LNATT */ #define _EMU_DCDCLNVCTRL_LNATT_MASK 0x2UL /**< Bit mask for EMU_LNATT */ #define _EMU_DCDCLNVCTRL_LNATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLNVCTRL */ #define _EMU_DCDCLNVCTRL_LNATT_DIV3 0x00000000UL /**< Mode DIV3 for EMU_DCDCLNVCTRL */ #define _EMU_DCDCLNVCTRL_LNATT_DIV6 0x00000001UL /**< Mode DIV6 for EMU_DCDCLNVCTRL */ #define EMU_DCDCLNVCTRL_LNATT_DEFAULT (_EMU_DCDCLNVCTRL_LNATT_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCLNVCTRL */ #define EMU_DCDCLNVCTRL_LNATT_DIV3 (_EMU_DCDCLNVCTRL_LNATT_DIV3 << 1) /**< Shifted mode DIV3 for EMU_DCDCLNVCTRL */ #define EMU_DCDCLNVCTRL_LNATT_DIV6 (_EMU_DCDCLNVCTRL_LNATT_DIV6 << 1) /**< Shifted mode DIV6 for EMU_DCDCLNVCTRL */ #define _EMU_DCDCLNVCTRL_LNVREF_SHIFT 8 /**< Shift value for EMU_LNVREF */ #define _EMU_DCDCLNVCTRL_LNVREF_MASK 0x7F00UL /**< Bit mask for EMU_LNVREF */ #define _EMU_DCDCLNVCTRL_LNVREF_DEFAULT 0x00000071UL /**< Mode DEFAULT for EMU_DCDCLNVCTRL */ #define EMU_DCDCLNVCTRL_LNVREF_DEFAULT (_EMU_DCDCLNVCTRL_LNVREF_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCLNVCTRL */ /* Bit fields for EMU DCDCLPVCTRL */ #define _EMU_DCDCLPVCTRL_RESETVALUE 0x00000168UL /**< Default value for EMU_DCDCLPVCTRL */ #define _EMU_DCDCLPVCTRL_MASK 0x000001FFUL /**< Mask for EMU_DCDCLPVCTRL */ #define EMU_DCDCLPVCTRL_LPATT (0x1UL << 0) /**< Low Power Feedback Attenuation */ #define _EMU_DCDCLPVCTRL_LPATT_SHIFT 0 /**< Shift value for EMU_LPATT */ #define _EMU_DCDCLPVCTRL_LPATT_MASK 0x1UL /**< Bit mask for EMU_LPATT */ #define _EMU_DCDCLPVCTRL_LPATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPVCTRL */ #define _EMU_DCDCLPVCTRL_LPATT_DIV4 0x00000000UL /**< Mode DIV4 for EMU_DCDCLPVCTRL */ #define _EMU_DCDCLPVCTRL_LPATT_DIV8 0x00000001UL /**< Mode DIV8 for EMU_DCDCLPVCTRL */ #define EMU_DCDCLPVCTRL_LPATT_DEFAULT (_EMU_DCDCLPVCTRL_LPATT_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLPVCTRL */ #define EMU_DCDCLPVCTRL_LPATT_DIV4 (_EMU_DCDCLPVCTRL_LPATT_DIV4 << 0) /**< Shifted mode DIV4 for EMU_DCDCLPVCTRL */ #define EMU_DCDCLPVCTRL_LPATT_DIV8 (_EMU_DCDCLPVCTRL_LPATT_DIV8 << 0) /**< Shifted mode DIV8 for EMU_DCDCLPVCTRL */ #define _EMU_DCDCLPVCTRL_LPVREF_SHIFT 1 /**< Shift value for EMU_LPVREF */ #define _EMU_DCDCLPVCTRL_LPVREF_MASK 0x1FEUL /**< Bit mask for EMU_LPVREF */ #define _EMU_DCDCLPVCTRL_LPVREF_DEFAULT 0x000000B4UL /**< Mode DEFAULT for EMU_DCDCLPVCTRL */ #define EMU_DCDCLPVCTRL_LPVREF_DEFAULT (_EMU_DCDCLPVCTRL_LPVREF_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCLPVCTRL */ /* Bit fields for EMU DCDCLPCTRL */ #define _EMU_DCDCLPCTRL_RESETVALUE 0x03000000UL /**< Default value for EMU_DCDCLPCTRL */ #define _EMU_DCDCLPCTRL_MASK 0x0700F000UL /**< Mask for EMU_DCDCLPCTRL */ #define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_SHIFT 12 /**< Shift value for EMU_LPCMPHYSSELEM234H */ #define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_MASK 0xF000UL /**< Bit mask for EMU_LPCMPHYSSELEM234H */ #define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */ #define EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT (_EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */ #define EMU_DCDCLPCTRL_LPVREFDUTYEN (0x1UL << 24) /**< LP Mode Duty Cycling Enable */ #define _EMU_DCDCLPCTRL_LPVREFDUTYEN_SHIFT 24 /**< Shift value for EMU_LPVREFDUTYEN */ #define _EMU_DCDCLPCTRL_LPVREFDUTYEN_MASK 0x1000000UL /**< Bit mask for EMU_LPVREFDUTYEN */ #define _EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */ #define EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT (_EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */ #define _EMU_DCDCLPCTRL_LPBLANK_SHIFT 25 /**< Shift value for EMU_LPBLANK */ #define _EMU_DCDCLPCTRL_LPBLANK_MASK 0x6000000UL /**< Bit mask for EMU_LPBLANK */ #define _EMU_DCDCLPCTRL_LPBLANK_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */ #define EMU_DCDCLPCTRL_LPBLANK_DEFAULT (_EMU_DCDCLPCTRL_LPBLANK_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */ /* Bit fields for EMU DCDCLNFREQCTRL */ #define _EMU_DCDCLNFREQCTRL_RESETVALUE 0x10000000UL /**< Default value for EMU_DCDCLNFREQCTRL */ #define _EMU_DCDCLNFREQCTRL_MASK 0x1F000007UL /**< Mask for EMU_DCDCLNFREQCTRL */ #define _EMU_DCDCLNFREQCTRL_RCOBAND_SHIFT 0 /**< Shift value for EMU_RCOBAND */ #define _EMU_DCDCLNFREQCTRL_RCOBAND_MASK 0x7UL /**< Bit mask for EMU_RCOBAND */ #define _EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLNFREQCTRL */ #define EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT (_EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLNFREQCTRL */ #define _EMU_DCDCLNFREQCTRL_RCOTRIM_SHIFT 24 /**< Shift value for EMU_RCOTRIM */ #define _EMU_DCDCLNFREQCTRL_RCOTRIM_MASK 0x1F000000UL /**< Bit mask for EMU_RCOTRIM */ #define _EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT 0x00000010UL /**< Mode DEFAULT for EMU_DCDCLNFREQCTRL */ #define EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT (_EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLNFREQCTRL */ /* Bit fields for EMU DCDCSYNC */ #define _EMU_DCDCSYNC_RESETVALUE 0x00000000UL /**< Default value for EMU_DCDCSYNC */ #define _EMU_DCDCSYNC_MASK 0x00000001UL /**< Mask for EMU_DCDCSYNC */ #define EMU_DCDCSYNC_DCDCCTRLBUSY (0x1UL << 0) /**< DCDC CTRL Register Transfer Busy */ #define _EMU_DCDCSYNC_DCDCCTRLBUSY_SHIFT 0 /**< Shift value for EMU_DCDCCTRLBUSY */ #define _EMU_DCDCSYNC_DCDCCTRLBUSY_MASK 0x1UL /**< Bit mask for EMU_DCDCCTRLBUSY */ #define _EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCSYNC */ #define EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT (_EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCSYNC */ /* Bit fields for EMU VMONAVDDCTRL */ #define _EMU_VMONAVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONAVDDCTRL */ #define _EMU_VMONAVDDCTRL_MASK 0x00FFFF0DUL /**< Mask for EMU_VMONAVDDCTRL */ #define EMU_VMONAVDDCTRL_EN (0x1UL << 0) /**< Enable */ #define _EMU_VMONAVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ #define _EMU_VMONAVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ #define _EMU_VMONAVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ #define EMU_VMONAVDDCTRL_EN_DEFAULT (_EMU_VMONAVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ #define EMU_VMONAVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ #define _EMU_VMONAVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ #define _EMU_VMONAVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ #define _EMU_VMONAVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ #define EMU_VMONAVDDCTRL_RISEWU_DEFAULT (_EMU_VMONAVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ #define EMU_VMONAVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ #define _EMU_VMONAVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ #define _EMU_VMONAVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ #define _EMU_VMONAVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ #define EMU_VMONAVDDCTRL_FALLWU_DEFAULT (_EMU_VMONAVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ #define _EMU_VMONAVDDCTRL_FALLTHRESFINE_SHIFT 8 /**< Shift value for EMU_FALLTHRESFINE */ #define _EMU_VMONAVDDCTRL_FALLTHRESFINE_MASK 0xF00UL /**< Bit mask for EMU_FALLTHRESFINE */ #define _EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ #define EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT (_EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ #define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_SHIFT 12 /**< Shift value for EMU_FALLTHRESCOARSE */ #define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_FALLTHRESCOARSE */ #define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ #define EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT (_EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ #define _EMU_VMONAVDDCTRL_RISETHRESFINE_SHIFT 16 /**< Shift value for EMU_RISETHRESFINE */ #define _EMU_VMONAVDDCTRL_RISETHRESFINE_MASK 0xF0000UL /**< Bit mask for EMU_RISETHRESFINE */ #define _EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ #define EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT (_EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ #define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_SHIFT 20 /**< Shift value for EMU_RISETHRESCOARSE */ #define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_MASK 0xF00000UL /**< Bit mask for EMU_RISETHRESCOARSE */ #define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ #define EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT (_EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ /* Bit fields for EMU VMONALTAVDDCTRL */ #define _EMU_VMONALTAVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONALTAVDDCTRL */ #define _EMU_VMONALTAVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONALTAVDDCTRL */ #define EMU_VMONALTAVDDCTRL_EN (0x1UL << 0) /**< Enable */ #define _EMU_VMONALTAVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ #define _EMU_VMONALTAVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ #define _EMU_VMONALTAVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ #define EMU_VMONALTAVDDCTRL_EN_DEFAULT (_EMU_VMONALTAVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ #define EMU_VMONALTAVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ #define _EMU_VMONALTAVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ #define _EMU_VMONALTAVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ #define _EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ #define EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT (_EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ #define EMU_VMONALTAVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ #define _EMU_VMONALTAVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ #define _EMU_VMONALTAVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ #define _EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ #define EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT (_EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ #define _EMU_VMONALTAVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ #define _EMU_VMONALTAVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ #define _EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ #define EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ #define _EMU_VMONALTAVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ #define _EMU_VMONALTAVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ #define _EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ #define EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ /* Bit fields for EMU VMONDVDDCTRL */ #define _EMU_VMONDVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONDVDDCTRL */ #define _EMU_VMONDVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONDVDDCTRL */ #define EMU_VMONDVDDCTRL_EN (0x1UL << 0) /**< Enable */ #define _EMU_VMONDVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ #define _EMU_VMONDVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ #define _EMU_VMONDVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ #define EMU_VMONDVDDCTRL_EN_DEFAULT (_EMU_VMONDVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ #define EMU_VMONDVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ #define _EMU_VMONDVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ #define _EMU_VMONDVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ #define _EMU_VMONDVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ #define EMU_VMONDVDDCTRL_RISEWU_DEFAULT (_EMU_VMONDVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ #define EMU_VMONDVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ #define _EMU_VMONDVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ #define _EMU_VMONDVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ #define _EMU_VMONDVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ #define EMU_VMONDVDDCTRL_FALLWU_DEFAULT (_EMU_VMONDVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ #define _EMU_VMONDVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ #define _EMU_VMONDVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ #define _EMU_VMONDVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ #define EMU_VMONDVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONDVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ #define _EMU_VMONDVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ #define _EMU_VMONDVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ #define _EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ #define EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ /* Bit fields for EMU VMONIO0CTRL */ #define _EMU_VMONIO0CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONIO0CTRL */ #define _EMU_VMONIO0CTRL_MASK 0x0000FF1DUL /**< Mask for EMU_VMONIO0CTRL */ #define EMU_VMONIO0CTRL_EN (0x1UL << 0) /**< Enable */ #define _EMU_VMONIO0CTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ #define _EMU_VMONIO0CTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ #define _EMU_VMONIO0CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ #define EMU_VMONIO0CTRL_EN_DEFAULT (_EMU_VMONIO0CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ #define EMU_VMONIO0CTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ #define _EMU_VMONIO0CTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ #define _EMU_VMONIO0CTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ #define _EMU_VMONIO0CTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ #define EMU_VMONIO0CTRL_RISEWU_DEFAULT (_EMU_VMONIO0CTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ #define EMU_VMONIO0CTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ #define _EMU_VMONIO0CTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ #define _EMU_VMONIO0CTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ #define _EMU_VMONIO0CTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ #define EMU_VMONIO0CTRL_FALLWU_DEFAULT (_EMU_VMONIO0CTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ #define EMU_VMONIO0CTRL_RETDIS (0x1UL << 4) /**< EM4 IO0 Retention Disable */ #define _EMU_VMONIO0CTRL_RETDIS_SHIFT 4 /**< Shift value for EMU_RETDIS */ #define _EMU_VMONIO0CTRL_RETDIS_MASK 0x10UL /**< Bit mask for EMU_RETDIS */ #define _EMU_VMONIO0CTRL_RETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ #define EMU_VMONIO0CTRL_RETDIS_DEFAULT (_EMU_VMONIO0CTRL_RETDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ #define _EMU_VMONIO0CTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ #define _EMU_VMONIO0CTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ #define _EMU_VMONIO0CTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ #define EMU_VMONIO0CTRL_THRESFINE_DEFAULT (_EMU_VMONIO0CTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ #define _EMU_VMONIO0CTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ #define _EMU_VMONIO0CTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ #define _EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ #define EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT (_EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ /* Bit fields for EMU RAM1CTRL */ #define _EMU_RAM1CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM1CTRL */ #define _EMU_RAM1CTRL_MASK 0x00000003UL /**< Mask for EMU_RAM1CTRL */ #define _EMU_RAM1CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */ #define _EMU_RAM1CTRL_RAMPOWERDOWN_MASK 0x3UL /**< Bit mask for EMU_RAMPOWERDOWN */ #define _EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM1CTRL */ #define _EMU_RAM1CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM1CTRL */ #define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK1 0x00000002UL /**< Mode BLK1 for EMU_RAM1CTRL */ #define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO1 0x00000003UL /**< Mode BLK0TO1 for EMU_RAM1CTRL */ #define EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM1CTRL */ #define EMU_RAM1CTRL_RAMPOWERDOWN_NONE (_EMU_RAM1CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM1CTRL */ #define EMU_RAM1CTRL_RAMPOWERDOWN_BLK1 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK1 << 0) /**< Shifted mode BLK1 for EMU_RAM1CTRL */ #define EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO1 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO1 << 0) /**< Shifted mode BLK0TO1 for EMU_RAM1CTRL */ /* Bit fields for EMU RAM2CTRL */ #define _EMU_RAM2CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM2CTRL */ #define _EMU_RAM2CTRL_MASK 0x00000001UL /**< Mask for EMU_RAM2CTRL */ #define _EMU_RAM2CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */ #define _EMU_RAM2CTRL_RAMPOWERDOWN_MASK 0x1UL /**< Bit mask for EMU_RAMPOWERDOWN */ #define _EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM2CTRL */ #define _EMU_RAM2CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM2CTRL */ #define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK 0x00000001UL /**< Mode BLK for EMU_RAM2CTRL */ #define EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM2CTRL */ #define EMU_RAM2CTRL_RAMPOWERDOWN_NONE (_EMU_RAM2CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM2CTRL */ #define EMU_RAM2CTRL_RAMPOWERDOWN_BLK (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK << 0) /**< Shifted mode BLK for EMU_RAM2CTRL */ /* Bit fields for EMU DCDCLPEM01CFG */ #define _EMU_DCDCLPEM01CFG_RESETVALUE 0x00000300UL /**< Default value for EMU_DCDCLPEM01CFG */ #define _EMU_DCDCLPEM01CFG_MASK 0x0000F300UL /**< Mask for EMU_DCDCLPEM01CFG */ #define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_SHIFT 8 /**< Shift value for EMU_LPCMPBIASEM01 */ #define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK 0x300UL /**< Bit mask for EMU_LPCMPBIASEM01 */ #define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 0x00000000UL /**< Mode BIAS0 for EMU_DCDCLPEM01CFG */ #define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 0x00000001UL /**< Mode BIAS1 for EMU_DCDCLPEM01CFG */ #define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 0x00000002UL /**< Mode BIAS2 for EMU_DCDCLPEM01CFG */ #define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCLPEM01CFG */ #define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 0x00000003UL /**< Mode BIAS3 for EMU_DCDCLPEM01CFG */ #define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 << 8) /**< Shifted mode BIAS0 for EMU_DCDCLPEM01CFG */ #define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 << 8) /**< Shifted mode BIAS1 for EMU_DCDCLPEM01CFG */ #define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 << 8) /**< Shifted mode BIAS2 for EMU_DCDCLPEM01CFG */ #define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCLPEM01CFG */ #define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 << 8) /**< Shifted mode BIAS3 for EMU_DCDCLPEM01CFG */ #define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_SHIFT 12 /**< Shift value for EMU_LPCMPHYSSELEM01 */ #define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_MASK 0xF000UL /**< Bit mask for EMU_LPCMPHYSSELEM01 */ #define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPEM01CFG */ #define EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT (_EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLPEM01CFG */ /* Bit fields for EMU EM23PERNORETAINCMD */ #define _EMU_EM23PERNORETAINCMD_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINCMD */ #define _EMU_EM23PERNORETAINCMD_MASK 0x0000FFFFUL /**< Mask for EMU_EM23PERNORETAINCMD */ #define EMU_EM23PERNORETAINCMD_ACMP0UNLOCK (0x1UL << 0) /**< Clears Status Bit of ACMP0 and Unlocks Access to It */ #define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_SHIFT 0 /**< Shift value for EMU_ACMP0UNLOCK */ #define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_MASK 0x1UL /**< Bit mask for EMU_ACMP0UNLOCK */ #define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ #define EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ #define EMU_EM23PERNORETAINCMD_ACMP1UNLOCK (0x1UL << 1) /**< Clears Status Bit of ACMP1 and Unlocks Access to It */ #define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_SHIFT 1 /**< Shift value for EMU_ACMP1UNLOCK */ #define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_MASK 0x2UL /**< Bit mask for EMU_ACMP1UNLOCK */ #define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ #define EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ #define EMU_EM23PERNORETAINCMD_PCNT0UNLOCK (0x1UL << 2) /**< Clears Status Bit of PCNT0 and Unlocks Access to It */ #define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_SHIFT 2 /**< Shift value for EMU_PCNT0UNLOCK */ #define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_MASK 0x4UL /**< Bit mask for EMU_PCNT0UNLOCK */ #define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ #define EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ #define EMU_EM23PERNORETAINCMD_PCNT1UNLOCK (0x1UL << 3) /**< Clears Status Bit of PCNT1 and Unlocks Access to It */ #define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_SHIFT 3 /**< Shift value for EMU_PCNT1UNLOCK */ #define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_MASK 0x8UL /**< Bit mask for EMU_PCNT1UNLOCK */ #define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ #define EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ #define EMU_EM23PERNORETAINCMD_PCNT2UNLOCK (0x1UL << 4) /**< Clears Status Bit of PCNT2 and Unlocks Access to It */ #define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_SHIFT 4 /**< Shift value for EMU_PCNT2UNLOCK */ #define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_MASK 0x10UL /**< Bit mask for EMU_PCNT2UNLOCK */ #define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ #define EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ #define EMU_EM23PERNORETAINCMD_I2C0UNLOCK (0x1UL << 5) /**< Clears Status Bit of I2C0 and Unlocks Access to It */ #define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_SHIFT 5 /**< Shift value for EMU_I2C0UNLOCK */ #define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_MASK 0x20UL /**< Bit mask for EMU_I2C0UNLOCK */ #define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ #define EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ #define EMU_EM23PERNORETAINCMD_I2C1UNLOCK (0x1UL << 6) /**< Clears Status Bit of I2C1 and Unlocks Access to It */ #define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_SHIFT 6 /**< Shift value for EMU_I2C1UNLOCK */ #define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_MASK 0x40UL /**< Bit mask for EMU_I2C1UNLOCK */ #define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ #define EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ #define EMU_EM23PERNORETAINCMD_DAC0UNLOCK (0x1UL << 7) /**< Clears Status Bit of DAC0 and Unlocks Access to It */ #define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_SHIFT 7 /**< Shift value for EMU_DAC0UNLOCK */ #define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_MASK 0x80UL /**< Bit mask for EMU_DAC0UNLOCK */ #define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ #define EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ #define EMU_EM23PERNORETAINCMD_IDAC0UNLOCK (0x1UL << 8) /**< Clears Status Bit of IDAC0 and Unlocks Access to It */ #define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_SHIFT 8 /**< Shift value for EMU_IDAC0UNLOCK */ #define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_MASK 0x100UL /**< Bit mask for EMU_IDAC0UNLOCK */ #define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ #define EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ #define EMU_EM23PERNORETAINCMD_ADC0UNLOCK (0x1UL << 9) /**< Clears Status Bit of ADC0 and Unlocks Access to It */ #define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_SHIFT 9 /**< Shift value for EMU_ADC0UNLOCK */ #define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_MASK 0x200UL /**< Bit mask for EMU_ADC0UNLOCK */ #define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ #define EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ #define EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK (0x1UL << 10) /**< Clears Status Bit of LETIMER0 and Unlocks Access to It */ #define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_SHIFT 10 /**< Shift value for EMU_LETIMER0UNLOCK */ #define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_MASK 0x400UL /**< Bit mask for EMU_LETIMER0UNLOCK */ #define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ #define EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ #define EMU_EM23PERNORETAINCMD_WDOG0UNLOCK (0x1UL << 11) /**< Clears Status Bit of WDOG0 and Unlocks Access to It */ #define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_SHIFT 11 /**< Shift value for EMU_WDOG0UNLOCK */ #define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_MASK 0x800UL /**< Bit mask for EMU_WDOG0UNLOCK */ #define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ #define EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ #define EMU_EM23PERNORETAINCMD_WDOG1UNLOCK (0x1UL << 12) /**< Clears Status Bit of WDOG1 and Unlocks Access to It */ #define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_SHIFT 12 /**< Shift value for EMU_WDOG1UNLOCK */ #define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_MASK 0x1000UL /**< Bit mask for EMU_WDOG1UNLOCK */ #define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ #define EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ #define EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK (0x1UL << 13) /**< Clears Status Bit of LESENSE0 and Unlocks Access to It */ #define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_SHIFT 13 /**< Shift value for EMU_LESENSE0UNLOCK */ #define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0UNLOCK */ #define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ #define EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ #define EMU_EM23PERNORETAINCMD_CSENUNLOCK (0x1UL << 14) /**< Clears Status Bit of CSEN and Unlocks Access to It */ #define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_SHIFT 14 /**< Shift value for EMU_CSENUNLOCK */ #define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_MASK 0x4000UL /**< Bit mask for EMU_CSENUNLOCK */ #define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ #define EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ #define EMU_EM23PERNORETAINCMD_LEUART0UNLOCK (0x1UL << 15) /**< Clears Status Bit of LEUART0 and Unlocks Access to It */ #define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_SHIFT 15 /**< Shift value for EMU_LEUART0UNLOCK */ #define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_MASK 0x8000UL /**< Bit mask for EMU_LEUART0UNLOCK */ #define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ #define EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ /* Bit fields for EMU EM23PERNORETAINSTATUS */ #define _EMU_EM23PERNORETAINSTATUS_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINSTATUS */ #define _EMU_EM23PERNORETAINSTATUS_MASK 0x0000FFFFUL /**< Mask for EMU_EM23PERNORETAINSTATUS */ #define EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED (0x1UL << 0) /**< Indicates If ACMP0 Powered Down During EM23 */ #define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_SHIFT 0 /**< Shift value for EMU_ACMP0LOCKED */ #define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_MASK 0x1UL /**< Bit mask for EMU_ACMP0LOCKED */ #define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ #define EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ #define EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED (0x1UL << 1) /**< Indicates If ACMP1 Powered Down During EM23 */ #define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_SHIFT 1 /**< Shift value for EMU_ACMP1LOCKED */ #define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_MASK 0x2UL /**< Bit mask for EMU_ACMP1LOCKED */ #define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ #define EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ #define EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED (0x1UL << 2) /**< Indicates If PCNT0 Powered Down During EM23 */ #define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_SHIFT 2 /**< Shift value for EMU_PCNT0LOCKED */ #define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_MASK 0x4UL /**< Bit mask for EMU_PCNT0LOCKED */ #define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ #define EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ #define EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED (0x1UL << 3) /**< Indicates If PCNT1 Powered Down During EM23 */ #define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_SHIFT 3 /**< Shift value for EMU_PCNT1LOCKED */ #define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_MASK 0x8UL /**< Bit mask for EMU_PCNT1LOCKED */ #define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ #define EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ #define EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED (0x1UL << 4) /**< Indicates If PCNT2 Powered Down During EM23 */ #define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_SHIFT 4 /**< Shift value for EMU_PCNT2LOCKED */ #define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_MASK 0x10UL /**< Bit mask for EMU_PCNT2LOCKED */ #define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ #define EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ #define EMU_EM23PERNORETAINSTATUS_I2C0LOCKED (0x1UL << 5) /**< Indicates If I2C0 Powered Down During EM23 */ #define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_SHIFT 5 /**< Shift value for EMU_I2C0LOCKED */ #define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_MASK 0x20UL /**< Bit mask for EMU_I2C0LOCKED */ #define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ #define EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ #define EMU_EM23PERNORETAINSTATUS_I2C1LOCKED (0x1UL << 6) /**< Indicates If I2C1 Powered Down During EM23 */ #define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_SHIFT 6 /**< Shift value for EMU_I2C1LOCKED */ #define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_MASK 0x40UL /**< Bit mask for EMU_I2C1LOCKED */ #define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ #define EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ #define EMU_EM23PERNORETAINSTATUS_DAC0LOCKED (0x1UL << 7) /**< Indicates If DAC0 Powered Down During EM23 */ #define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_SHIFT 7 /**< Shift value for EMU_DAC0LOCKED */ #define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_MASK 0x80UL /**< Bit mask for EMU_DAC0LOCKED */ #define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ #define EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ #define EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED (0x1UL << 8) /**< Indicates If IDAC0 Powered Down During EM23 */ #define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_SHIFT 8 /**< Shift value for EMU_IDAC0LOCKED */ #define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_MASK 0x100UL /**< Bit mask for EMU_IDAC0LOCKED */ #define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ #define EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ #define EMU_EM23PERNORETAINSTATUS_ADC0LOCKED (0x1UL << 9) /**< Indicates If ADC0 Powered Down During EM23 */ #define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_SHIFT 9 /**< Shift value for EMU_ADC0LOCKED */ #define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_MASK 0x200UL /**< Bit mask for EMU_ADC0LOCKED */ #define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ #define EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ #define EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED (0x1UL << 10) /**< Indicates If LETIMER0 Powered Down During EM23 */ #define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_SHIFT 10 /**< Shift value for EMU_LETIMER0LOCKED */ #define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_MASK 0x400UL /**< Bit mask for EMU_LETIMER0LOCKED */ #define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ #define EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ #define EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED (0x1UL << 11) /**< Indicates If WDOG0 Powered Down During EM23 */ #define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_SHIFT 11 /**< Shift value for EMU_WDOG0LOCKED */ #define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_MASK 0x800UL /**< Bit mask for EMU_WDOG0LOCKED */ #define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ #define EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ #define EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED (0x1UL << 12) /**< Indicates If WDOG1 Powered Down During EM23 */ #define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_SHIFT 12 /**< Shift value for EMU_WDOG1LOCKED */ #define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_MASK 0x1000UL /**< Bit mask for EMU_WDOG1LOCKED */ #define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ #define EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ #define EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED (0x1UL << 13) /**< Indicates If LESENSE0 Powered Down During EM23 */ #define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_SHIFT 13 /**< Shift value for EMU_LESENSE0LOCKED */ #define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0LOCKED */ #define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ #define EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ #define EMU_EM23PERNORETAINSTATUS_CSENLOCKED (0x1UL << 14) /**< Indicates If CSEN Powered Down During EM23 */ #define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_SHIFT 14 /**< Shift value for EMU_CSENLOCKED */ #define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_MASK 0x4000UL /**< Bit mask for EMU_CSENLOCKED */ #define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ #define EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ #define EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED (0x1UL << 15) /**< Indicates If LEUART0 Powered Down During EM23 */ #define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_SHIFT 15 /**< Shift value for EMU_LEUART0LOCKED */ #define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_MASK 0x8000UL /**< Bit mask for EMU_LEUART0LOCKED */ #define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ #define EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ /* Bit fields for EMU EM23PERNORETAINCTRL */ #define _EMU_EM23PERNORETAINCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINCTRL */ #define _EMU_EM23PERNORETAINCTRL_MASK 0x0000FFFFUL /**< Mask for EMU_EM23PERNORETAINCTRL */ #define EMU_EM23PERNORETAINCTRL_ACMP0DIS (0x1UL << 0) /**< Allow Power Down of ACMP0 During EM23 */ #define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_SHIFT 0 /**< Shift value for EMU_ACMP0DIS */ #define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_MASK 0x1UL /**< Bit mask for EMU_ACMP0DIS */ #define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ #define EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ #define EMU_EM23PERNORETAINCTRL_ACMP1DIS (0x1UL << 1) /**< Allow Power Down of ACMP1 During EM23 */ #define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_SHIFT 1 /**< Shift value for EMU_ACMP1DIS */ #define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_MASK 0x2UL /**< Bit mask for EMU_ACMP1DIS */ #define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ #define EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ #define EMU_EM23PERNORETAINCTRL_PCNT0DIS (0x1UL << 2) /**< Allow Power Down of PCNT0 During EM23 */ #define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_SHIFT 2 /**< Shift value for EMU_PCNT0DIS */ #define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_MASK 0x4UL /**< Bit mask for EMU_PCNT0DIS */ #define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ #define EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ #define EMU_EM23PERNORETAINCTRL_PCNT1DIS (0x1UL << 3) /**< Allow Power Down of PCNT1 During EM23 */ #define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_SHIFT 3 /**< Shift value for EMU_PCNT1DIS */ #define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_MASK 0x8UL /**< Bit mask for EMU_PCNT1DIS */ #define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ #define EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ #define EMU_EM23PERNORETAINCTRL_PCNT2DIS (0x1UL << 4) /**< Allow Power Down of PCNT2 During EM23 */ #define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_SHIFT 4 /**< Shift value for EMU_PCNT2DIS */ #define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_MASK 0x10UL /**< Bit mask for EMU_PCNT2DIS */ #define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ #define EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ #define EMU_EM23PERNORETAINCTRL_I2C0DIS (0x1UL << 5) /**< Allow Power Down of I2C0 During EM23 */ #define _EMU_EM23PERNORETAINCTRL_I2C0DIS_SHIFT 5 /**< Shift value for EMU_I2C0DIS */ #define _EMU_EM23PERNORETAINCTRL_I2C0DIS_MASK 0x20UL /**< Bit mask for EMU_I2C0DIS */ #define _EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ #define EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ #define EMU_EM23PERNORETAINCTRL_I2C1DIS (0x1UL << 6) /**< Allow Power Down of I2C1 During EM23 */ #define _EMU_EM23PERNORETAINCTRL_I2C1DIS_SHIFT 6 /**< Shift value for EMU_I2C1DIS */ #define _EMU_EM23PERNORETAINCTRL_I2C1DIS_MASK 0x40UL /**< Bit mask for EMU_I2C1DIS */ #define _EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ #define EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ #define EMU_EM23PERNORETAINCTRL_VDAC0DIS (0x1UL << 7) /**< Allow Power Down of DAC0 During EM23 */ #define _EMU_EM23PERNORETAINCTRL_VDAC0DIS_SHIFT 7 /**< Shift value for EMU_VDAC0DIS */ #define _EMU_EM23PERNORETAINCTRL_VDAC0DIS_MASK 0x80UL /**< Bit mask for EMU_VDAC0DIS */ #define _EMU_EM23PERNORETAINCTRL_VDAC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ #define EMU_EM23PERNORETAINCTRL_VDAC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_VDAC0DIS_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ #define EMU_EM23PERNORETAINCTRL_IDAC0DIS (0x1UL << 8) /**< Allow Power Down of IDAC0 During EM23 */ #define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_SHIFT 8 /**< Shift value for EMU_IDAC0DIS */ #define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_MASK 0x100UL /**< Bit mask for EMU_IDAC0DIS */ #define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ #define EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ #define EMU_EM23PERNORETAINCTRL_ADC0DIS (0x1UL << 9) /**< Allow Power Down of ADC0 During EM23 */ #define _EMU_EM23PERNORETAINCTRL_ADC0DIS_SHIFT 9 /**< Shift value for EMU_ADC0DIS */ #define _EMU_EM23PERNORETAINCTRL_ADC0DIS_MASK 0x200UL /**< Bit mask for EMU_ADC0DIS */ #define _EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ #define EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ #define EMU_EM23PERNORETAINCTRL_LETIMER0DIS (0x1UL << 10) /**< Allow Power Down of LETIMER0 During EM23 */ #define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_SHIFT 10 /**< Shift value for EMU_LETIMER0DIS */ #define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_MASK 0x400UL /**< Bit mask for EMU_LETIMER0DIS */ #define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ #define EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ #define EMU_EM23PERNORETAINCTRL_WDOG0DIS (0x1UL << 11) /**< Allow Power Down of WDOG0 During EM23 */ #define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_SHIFT 11 /**< Shift value for EMU_WDOG0DIS */ #define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_MASK 0x800UL /**< Bit mask for EMU_WDOG0DIS */ #define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ #define EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ #define EMU_EM23PERNORETAINCTRL_WDOG1DIS (0x1UL << 12) /**< Allow Power Down of WDOG1 During EM23 */ #define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_SHIFT 12 /**< Shift value for EMU_WDOG1DIS */ #define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_MASK 0x1000UL /**< Bit mask for EMU_WDOG1DIS */ #define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ #define EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ #define EMU_EM23PERNORETAINCTRL_LESENSE0DIS (0x1UL << 13) /**< Allow Power Down of LESENSE0 During EM23 */ #define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_SHIFT 13 /**< Shift value for EMU_LESENSE0DIS */ #define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0DIS */ #define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ #define EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ #define EMU_EM23PERNORETAINCTRL_CSENDIS (0x1UL << 14) /**< Allow Power Down of CSEN During EM23 */ #define _EMU_EM23PERNORETAINCTRL_CSENDIS_SHIFT 14 /**< Shift value for EMU_CSENDIS */ #define _EMU_EM23PERNORETAINCTRL_CSENDIS_MASK 0x4000UL /**< Bit mask for EMU_CSENDIS */ #define _EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ #define EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ #define EMU_EM23PERNORETAINCTRL_LEUART0DIS (0x1UL << 15) /**< Allow Power Down of LEUART0 During EM23 */ #define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_SHIFT 15 /**< Shift value for EMU_LEUART0DIS */ #define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_MASK 0x8000UL /**< Bit mask for EMU_LEUART0DIS */ #define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ #define EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ /** @} */ /** @} End of group EFR32MG12P_EMU */ /** @} End of group Parts */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_etm.h.
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/***************************************************************************//** * @file * @brief EFR32MG12P_ETM register and bit field definitions * @version 5.7.0 ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * SPDX-License-Identifier: Zlib * * The licensor of this software is Silicon Laboratories Inc. * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be * appreciated but is not required. * 2. Altered source versions must be plainly marked as such, and must not be * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * ******************************************************************************/ #if defined(__ICCARM__) #pragma system_include /* Treat file as system include file. */ #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang system_header /* Treat file as system include file. */ #endif /***************************************************************************//** * @addtogroup Parts * @{ ******************************************************************************/ /***************************************************************************//** * @defgroup EFR32MG12P_ETM ETM * @{ * @brief EFR32MG12P_ETM Register Declaration ******************************************************************************/ /** ETM Register Declaration */ typedef struct { __IOM uint32_t ETMCR; /**< Main Control Register */ __IM uint32_t ETMCCR; /**< Configuration Code Register */ __IOM uint32_t ETMTRIGGER; /**< ETM Trigger Event Register */ uint32_t RESERVED0[1U]; /**< Reserved for future use **/ __IOM uint32_t ETMSR; /**< ETM Status Register */ __IM uint32_t ETMSCR; /**< ETM System Configuration Register */ uint32_t RESERVED1[2U]; /**< Reserved for future use **/ __IOM uint32_t ETMTEEVR; /**< ETM TraceEnable Event Register */ __IOM uint32_t ETMTECR1; /**< ETM Trace control Register */ uint32_t RESERVED2[1U]; /**< Reserved for future use **/ __IOM uint32_t ETMFFLR; /**< ETM Fifo Full Level Register */ uint32_t RESERVED3[68U]; /**< Reserved for future use **/ __IOM uint32_t ETMCNTRLDVR1; /**< Counter Reload Value */ uint32_t RESERVED4[39U]; /**< Reserved for future use **/ __IOM uint32_t ETMSYNCFR; /**< Synchronisation Frequency Register */ __IM uint32_t ETMIDR; /**< ID Register */ __IM uint32_t ETMCCER; /**< Configuration Code Extension Register */ uint32_t RESERVED5[1U]; /**< Reserved for future use **/ __IOM uint32_t ETMTESSEICR; /**< TraceEnable Start/Stop EmbeddedICE Control Register */ uint32_t RESERVED6[1U]; /**< Reserved for future use **/ __IOM uint32_t ETMTSEVR; /**< Timestamp Event Register */ uint32_t RESERVED7[1U]; /**< Reserved for future use **/ __IOM uint32_t ETMTRACEIDR; /**< CoreSight Trace ID Register */ uint32_t RESERVED8[1U]; /**< Reserved for future use **/ __IM uint32_t ETMIDR2; /**< ETM ID Register 2 */ uint32_t RESERVED9[66U]; /**< Reserved for future use **/ __IM uint32_t ETMPDSR; /**< Device Power-down Status Register */ uint32_t RESERVED10[754U]; /**< Reserved for future use **/ __IOM uint32_t ETMISCIN; /**< Integration Test Miscellaneous Inputs Register */ uint32_t RESERVED11[1U]; /**< Reserved for future use **/ __IOM uint32_t ITTRIGOUT; /**< Integration Test Trigger Out Register */ uint32_t RESERVED12[1U]; /**< Reserved for future use **/ __IM uint32_t ETMITATBCTR2; /**< ETM Integration Test ATB Control 2 Register */ uint32_t RESERVED13[1U]; /**< Reserved for future use **/ __IOM uint32_t ETMITATBCTR0; /**< ETM Integration Test ATB Control 0 Register */ uint32_t RESERVED14[1U]; /**< Reserved for future use **/ __IOM uint32_t ETMITCTRL; /**< ETM Integration Control Register */ uint32_t RESERVED15[39U]; /**< Reserved for future use **/ __IOM uint32_t ETMCLAIMSET; /**< ETM Claim Tag Set Register */ __IOM uint32_t ETMCLAIMCLR; /**< ETM Claim Tag Clear Register */ uint32_t RESERVED16[2U]; /**< Reserved for future use **/ __IOM uint32_t ETMLAR; /**< ETM Lock Access Register */ __IM uint32_t ETMLSR; /**< Lock Status Register */ __IM uint32_t ETMAUTHSTATUS; /**< ETM Authentication Status Register */ uint32_t RESERVED17[4U]; /**< Reserved for future use **/ __IM uint32_t ETMDEVTYPE; /**< CoreSight Device Type Register */ __IM uint32_t ETMPIDR4; /**< Peripheral ID4 Register */ __OM uint32_t ETMPIDR5; /**< Peripheral ID5 Register */ __OM uint32_t ETMPIDR6; /**< Peripheral ID6 Register */ __OM uint32_t ETMPIDR7; /**< Peripheral ID7 Register */ __IM uint32_t ETMPIDR0; /**< Peripheral ID0 Register */ __IM uint32_t ETMPIDR1; /**< Peripheral ID1 Register */ __IM uint32_t ETMPIDR2; /**< Peripheral ID2 Register */ __IM uint32_t ETMPIDR3; /**< Peripheral ID3 Register */ __IM uint32_t ETMCIDR0; /**< Component ID0 Register */ __IM uint32_t ETMCIDR1; /**< Component ID1 Register */ __IM uint32_t ETMCIDR2; /**< Component ID2 Register */ __IM uint32_t ETMCIDR3; /**< Component ID3 Register */ } ETM_TypeDef; /** @} */ /***************************************************************************//** * @addtogroup EFR32MG12P_ETM * @{ * @defgroup EFR32MG12P_ETM_BitFields ETM Bit Fields * @{ ******************************************************************************/ /* Bit fields for ETM ETMCR */ #define _ETM_ETMCR_RESETVALUE 0x00000411UL /**< Default value for ETM_ETMCR */ #define _ETM_ETMCR_MASK 0x10632FF1UL /**< Mask for ETM_ETMCR */ #define ETM_ETMCR_POWERDWN (0x1UL << 0) /**< ETM Control in low power mode */ #define _ETM_ETMCR_POWERDWN_SHIFT 0 /**< Shift value for ETM_POWERDWN */ #define _ETM_ETMCR_POWERDWN_MASK 0x1UL /**< Bit mask for ETM_POWERDWN */ #define _ETM_ETMCR_POWERDWN_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCR */ #define ETM_ETMCR_POWERDWN_DEFAULT (_ETM_ETMCR_POWERDWN_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCR */ #define _ETM_ETMCR_PORTSIZE_SHIFT 4 /**< Shift value for ETM_PORTSIZE */ #define _ETM_ETMCR_PORTSIZE_MASK 0x70UL /**< Bit mask for ETM_PORTSIZE */ #define _ETM_ETMCR_PORTSIZE_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCR */ #define ETM_ETMCR_PORTSIZE_DEFAULT (_ETM_ETMCR_PORTSIZE_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMCR */ #define ETM_ETMCR_STALL (0x1UL << 7) /**< Stall Processor */ #define _ETM_ETMCR_STALL_SHIFT 7 /**< Shift value for ETM_STALL */ #define _ETM_ETMCR_STALL_MASK 0x80UL /**< Bit mask for ETM_STALL */ #define _ETM_ETMCR_STALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */ #define ETM_ETMCR_STALL_DEFAULT (_ETM_ETMCR_STALL_DEFAULT << 7) /**< Shifted mode DEFAULT for ETM_ETMCR */ #define ETM_ETMCR_BRANCHOUTPUT (0x1UL << 8) /**< Branch Output */ #define _ETM_ETMCR_BRANCHOUTPUT_SHIFT 8 /**< Shift value for ETM_BRANCHOUTPUT */ #define _ETM_ETMCR_BRANCHOUTPUT_MASK 0x100UL /**< Bit mask for ETM_BRANCHOUTPUT */ #define _ETM_ETMCR_BRANCHOUTPUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */ #define ETM_ETMCR_BRANCHOUTPUT_DEFAULT (_ETM_ETMCR_BRANCHOUTPUT_DEFAULT << 8) /**< Shifted mode DEFAULT for ETM_ETMCR */ #define ETM_ETMCR_DBGREQCTRL (0x1UL << 9) /**< Debug Request Control */ #define _ETM_ETMCR_DBGREQCTRL_SHIFT 9 /**< Shift value for ETM_DBGREQCTRL */ #define _ETM_ETMCR_DBGREQCTRL_MASK 0x200UL /**< Bit mask for ETM_DBGREQCTRL */ #define _ETM_ETMCR_DBGREQCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */ #define ETM_ETMCR_DBGREQCTRL_DEFAULT (_ETM_ETMCR_DBGREQCTRL_DEFAULT << 9) /**< Shifted mode DEFAULT for ETM_ETMCR */ #define ETM_ETMCR_ETMPROG (0x1UL << 10) /**< ETM Programming */ #define _ETM_ETMCR_ETMPROG_SHIFT 10 /**< Shift value for ETM_ETMPROG */ #define _ETM_ETMCR_ETMPROG_MASK 0x400UL /**< Bit mask for ETM_ETMPROG */ #define _ETM_ETMCR_ETMPROG_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCR */ #define ETM_ETMCR_ETMPROG_DEFAULT (_ETM_ETMCR_ETMPROG_DEFAULT << 10) /**< Shifted mode DEFAULT for ETM_ETMCR */ #define ETM_ETMCR_ETMPORTSEL (0x1UL << 11) /**< ETM Port Selection */ #define _ETM_ETMCR_ETMPORTSEL_SHIFT 11 /**< Shift value for ETM_ETMPORTSEL */ #define _ETM_ETMCR_ETMPORTSEL_MASK 0x800UL /**< Bit mask for ETM_ETMPORTSEL */ #define _ETM_ETMCR_ETMPORTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */ #define _ETM_ETMCR_ETMPORTSEL_ETMLOW 0x00000000UL /**< Mode ETMLOW for ETM_ETMCR */ #define _ETM_ETMCR_ETMPORTSEL_ETMHIGH 0x00000001UL /**< Mode ETMHIGH for ETM_ETMCR */ #define ETM_ETMCR_ETMPORTSEL_DEFAULT (_ETM_ETMCR_ETMPORTSEL_DEFAULT << 11) /**< Shifted mode DEFAULT for ETM_ETMCR */ #define ETM_ETMCR_ETMPORTSEL_ETMLOW (_ETM_ETMCR_ETMPORTSEL_ETMLOW << 11) /**< Shifted mode ETMLOW for ETM_ETMCR */ #define ETM_ETMCR_ETMPORTSEL_ETMHIGH (_ETM_ETMCR_ETMPORTSEL_ETMHIGH << 11) /**< Shifted mode ETMHIGH for ETM_ETMCR */ #define ETM_ETMCR_PORTMODE2 (0x1UL << 13) /**< Port Mode[2] */ #define _ETM_ETMCR_PORTMODE2_SHIFT 13 /**< Shift value for ETM_PORTMODE2 */ #define _ETM_ETMCR_PORTMODE2_MASK 0x2000UL /**< Bit mask for ETM_PORTMODE2 */ #define _ETM_ETMCR_PORTMODE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */ #define ETM_ETMCR_PORTMODE2_DEFAULT (_ETM_ETMCR_PORTMODE2_DEFAULT << 13) /**< Shifted mode DEFAULT for ETM_ETMCR */ #define _ETM_ETMCR_PORTMODE_SHIFT 16 /**< Shift value for ETM_PORTMODE */ #define _ETM_ETMCR_PORTMODE_MASK 0x30000UL /**< Bit mask for ETM_PORTMODE */ #define _ETM_ETMCR_PORTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */ #define ETM_ETMCR_PORTMODE_DEFAULT (_ETM_ETMCR_PORTMODE_DEFAULT << 16) /**< Shifted mode DEFAULT for ETM_ETMCR */ #define _ETM_ETMCR_EPORTSIZE_SHIFT 21 /**< Shift value for ETM_EPORTSIZE */ #define _ETM_ETMCR_EPORTSIZE_MASK 0x600000UL /**< Bit mask for ETM_EPORTSIZE */ #define _ETM_ETMCR_EPORTSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */ #define ETM_ETMCR_EPORTSIZE_DEFAULT (_ETM_ETMCR_EPORTSIZE_DEFAULT << 21) /**< Shifted mode DEFAULT for ETM_ETMCR */ #define ETM_ETMCR_TSTAMPEN (0x1UL << 28) /**< Time Stamp Enable */ #define _ETM_ETMCR_TSTAMPEN_SHIFT 28 /**< Shift value for ETM_TSTAMPEN */ #define _ETM_ETMCR_TSTAMPEN_MASK 0x10000000UL /**< Bit mask for ETM_TSTAMPEN */ #define _ETM_ETMCR_TSTAMPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */ #define ETM_ETMCR_TSTAMPEN_DEFAULT (_ETM_ETMCR_TSTAMPEN_DEFAULT << 28) /**< Shifted mode DEFAULT for ETM_ETMCR */ /* Bit fields for ETM ETMCCR */ #define _ETM_ETMCCR_RESETVALUE 0x8C802000UL /**< Default value for ETM_ETMCCR */ #define _ETM_ETMCCR_MASK 0x8FFFFFFFUL /**< Mask for ETM_ETMCCR */ #define _ETM_ETMCCR_ADRCMPPAIR_SHIFT 0 /**< Shift value for ETM_ADRCMPPAIR */ #define _ETM_ETMCCR_ADRCMPPAIR_MASK 0xFUL /**< Bit mask for ETM_ADRCMPPAIR */ #define _ETM_ETMCCR_ADRCMPPAIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCR */ #define ETM_ETMCCR_ADRCMPPAIR_DEFAULT (_ETM_ETMCCR_ADRCMPPAIR_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCCR */ #define _ETM_ETMCCR_DATACMPNUM_SHIFT 4 /**< Shift value for ETM_DATACMPNUM */ #define _ETM_ETMCCR_DATACMPNUM_MASK 0xF0UL /**< Bit mask for ETM_DATACMPNUM */ #define _ETM_ETMCCR_DATACMPNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCR */ #define ETM_ETMCCR_DATACMPNUM_DEFAULT (_ETM_ETMCCR_DATACMPNUM_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMCCR */ #define _ETM_ETMCCR_MMDECCNT_SHIFT 8 /**< Shift value for ETM_MMDECCNT */ #define _ETM_ETMCCR_MMDECCNT_MASK 0x1F00UL /**< Bit mask for ETM_MMDECCNT */ #define _ETM_ETMCCR_MMDECCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCR */ #define ETM_ETMCCR_MMDECCNT_DEFAULT (_ETM_ETMCCR_MMDECCNT_DEFAULT << 8) /**< Shifted mode DEFAULT for ETM_ETMCCR */ #define _ETM_ETMCCR_COUNTNUM_SHIFT 13 /**< Shift value for ETM_COUNTNUM */ #define _ETM_ETMCCR_COUNTNUM_MASK 0xE000UL /**< Bit mask for ETM_COUNTNUM */ #define _ETM_ETMCCR_COUNTNUM_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCR */ #define ETM_ETMCCR_COUNTNUM_DEFAULT (_ETM_ETMCCR_COUNTNUM_DEFAULT << 13) /**< Shifted mode DEFAULT for ETM_ETMCCR */ #define ETM_ETMCCR_SEQPRES (0x1UL << 16) /**< Sequencer Present */ #define _ETM_ETMCCR_SEQPRES_SHIFT 16 /**< Shift value for ETM_SEQPRES */ #define _ETM_ETMCCR_SEQPRES_MASK 0x10000UL /**< Bit mask for ETM_SEQPRES */ #define _ETM_ETMCCR_SEQPRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCR */ #define ETM_ETMCCR_SEQPRES_DEFAULT (_ETM_ETMCCR_SEQPRES_DEFAULT << 16) /**< Shifted mode DEFAULT for ETM_ETMCCR */ #define _ETM_ETMCCR_EXTINPNUM_SHIFT 17 /**< Shift value for ETM_EXTINPNUM */ #define _ETM_ETMCCR_EXTINPNUM_MASK 0xE0000UL /**< Bit mask for ETM_EXTINPNUM */ #define _ETM_ETMCCR_EXTINPNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCR */ #define _ETM_ETMCCR_EXTINPNUM_ZERO 0x00000000UL /**< Mode ZERO for ETM_ETMCCR */ #define _ETM_ETMCCR_EXTINPNUM_ONE 0x00000001UL /**< Mode ONE for ETM_ETMCCR */ #define _ETM_ETMCCR_EXTINPNUM_TWO 0x00000002UL /**< Mode TWO for ETM_ETMCCR */ #define ETM_ETMCCR_EXTINPNUM_DEFAULT (_ETM_ETMCCR_EXTINPNUM_DEFAULT << 17) /**< Shifted mode DEFAULT for ETM_ETMCCR */ #define ETM_ETMCCR_EXTINPNUM_ZERO (_ETM_ETMCCR_EXTINPNUM_ZERO << 17) /**< Shifted mode ZERO for ETM_ETMCCR */ #define ETM_ETMCCR_EXTINPNUM_ONE (_ETM_ETMCCR_EXTINPNUM_ONE << 17) /**< Shifted mode ONE for ETM_ETMCCR */ #define ETM_ETMCCR_EXTINPNUM_TWO (_ETM_ETMCCR_EXTINPNUM_TWO << 17) /**< Shifted mode TWO for ETM_ETMCCR */ #define _ETM_ETMCCR_EXTOUTNUM_SHIFT 20 /**< Shift value for ETM_EXTOUTNUM */ #define _ETM_ETMCCR_EXTOUTNUM_MASK 0x700000UL /**< Bit mask for ETM_EXTOUTNUM */ #define _ETM_ETMCCR_EXTOUTNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCR */ #define ETM_ETMCCR_EXTOUTNUM_DEFAULT (_ETM_ETMCCR_EXTOUTNUM_DEFAULT << 20) /**< Shifted mode DEFAULT for ETM_ETMCCR */ #define ETM_ETMCCR_FIFOFULLPRES (0x1UL << 23) /**< FIFIO FULL present */ #define _ETM_ETMCCR_FIFOFULLPRES_SHIFT 23 /**< Shift value for ETM_FIFOFULLPRES */ #define _ETM_ETMCCR_FIFOFULLPRES_MASK 0x800000UL /**< Bit mask for ETM_FIFOFULLPRES */ #define _ETM_ETMCCR_FIFOFULLPRES_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCR */ #define ETM_ETMCCR_FIFOFULLPRES_DEFAULT (_ETM_ETMCCR_FIFOFULLPRES_DEFAULT << 23) /**< Shifted mode DEFAULT for ETM_ETMCCR */ #define _ETM_ETMCCR_IDCOMPNUM_SHIFT 24 /**< Shift value for ETM_IDCOMPNUM */ #define _ETM_ETMCCR_IDCOMPNUM_MASK 0x3000000UL /**< Bit mask for ETM_IDCOMPNUM */ #define _ETM_ETMCCR_IDCOMPNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCR */ #define ETM_ETMCCR_IDCOMPNUM_DEFAULT (_ETM_ETMCCR_IDCOMPNUM_DEFAULT << 24) /**< Shifted mode DEFAULT for ETM_ETMCCR */ #define ETM_ETMCCR_TRACESS (0x1UL << 26) /**< Trace Start/Stop Block Present */ #define _ETM_ETMCCR_TRACESS_SHIFT 26 /**< Shift value for ETM_TRACESS */ #define _ETM_ETMCCR_TRACESS_MASK 0x4000000UL /**< Bit mask for ETM_TRACESS */ #define _ETM_ETMCCR_TRACESS_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCR */ #define ETM_ETMCCR_TRACESS_DEFAULT (_ETM_ETMCCR_TRACESS_DEFAULT << 26) /**< Shifted mode DEFAULT for ETM_ETMCCR */ #define ETM_ETMCCR_MMACCESS (0x1UL << 27) /**< Coprocessor and Memeory Access */ #define _ETM_ETMCCR_MMACCESS_SHIFT 27 /**< Shift value for ETM_MMACCESS */ #define _ETM_ETMCCR_MMACCESS_MASK 0x8000000UL /**< Bit mask for ETM_MMACCESS */ #define _ETM_ETMCCR_MMACCESS_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCR */ #define ETM_ETMCCR_MMACCESS_DEFAULT (_ETM_ETMCCR_MMACCESS_DEFAULT << 27) /**< Shifted mode DEFAULT for ETM_ETMCCR */ #define ETM_ETMCCR_ETMID (0x1UL << 31) /**< ETM ID Register Present */ #define _ETM_ETMCCR_ETMID_SHIFT 31 /**< Shift value for ETM_ETMID */ #define _ETM_ETMCCR_ETMID_MASK 0x80000000UL /**< Bit mask for ETM_ETMID */ #define _ETM_ETMCCR_ETMID_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCR */ #define ETM_ETMCCR_ETMID_DEFAULT (_ETM_ETMCCR_ETMID_DEFAULT << 31) /**< Shifted mode DEFAULT for ETM_ETMCCR */ /* Bit fields for ETM ETMTRIGGER */ #define _ETM_ETMTRIGGER_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMTRIGGER */ #define _ETM_ETMTRIGGER_MASK 0x0001FFFFUL /**< Mask for ETM_ETMTRIGGER */ #define _ETM_ETMTRIGGER_RESA_SHIFT 0 /**< Shift value for ETM_RESA */ #define _ETM_ETMTRIGGER_RESA_MASK 0x7FUL /**< Bit mask for ETM_RESA */ #define _ETM_ETMTRIGGER_RESA_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTRIGGER */ #define ETM_ETMTRIGGER_RESA_DEFAULT (_ETM_ETMTRIGGER_RESA_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMTRIGGER */ #define _ETM_ETMTRIGGER_RESB_SHIFT 7 /**< Shift value for ETM_RESB */ #define _ETM_ETMTRIGGER_RESB_MASK 0x3F80UL /**< Bit mask for ETM_RESB */ #define _ETM_ETMTRIGGER_RESB_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTRIGGER */ #define ETM_ETMTRIGGER_RESB_DEFAULT (_ETM_ETMTRIGGER_RESB_DEFAULT << 7) /**< Shifted mode DEFAULT for ETM_ETMTRIGGER */ #define _ETM_ETMTRIGGER_ETMFCN_SHIFT 14 /**< Shift value for ETM_ETMFCN */ #define _ETM_ETMTRIGGER_ETMFCN_MASK 0x1C000UL /**< Bit mask for ETM_ETMFCN */ #define _ETM_ETMTRIGGER_ETMFCN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTRIGGER */ #define ETM_ETMTRIGGER_ETMFCN_DEFAULT (_ETM_ETMTRIGGER_ETMFCN_DEFAULT << 14) /**< Shifted mode DEFAULT for ETM_ETMTRIGGER */ /* Bit fields for ETM ETMSR */ #define _ETM_ETMSR_RESETVALUE 0x00000002UL /**< Default value for ETM_ETMSR */ #define _ETM_ETMSR_MASK 0x0000000FUL /**< Mask for ETM_ETMSR */ #define ETM_ETMSR_ETHOF (0x1UL << 0) /**< ETM Overflow */ #define _ETM_ETMSR_ETHOF_SHIFT 0 /**< Shift value for ETM_ETHOF */ #define _ETM_ETMSR_ETHOF_MASK 0x1UL /**< Bit mask for ETM_ETHOF */ #define _ETM_ETMSR_ETHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMSR */ #define ETM_ETMSR_ETHOF_DEFAULT (_ETM_ETMSR_ETHOF_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMSR */ #define ETM_ETMSR_ETMPROGBIT (0x1UL << 1) /**< ETM Programming Bit Status */ #define _ETM_ETMSR_ETMPROGBIT_SHIFT 1 /**< Shift value for ETM_ETMPROGBIT */ #define _ETM_ETMSR_ETMPROGBIT_MASK 0x2UL /**< Bit mask for ETM_ETMPROGBIT */ #define _ETM_ETMSR_ETMPROGBIT_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMSR */ #define ETM_ETMSR_ETMPROGBIT_DEFAULT (_ETM_ETMSR_ETMPROGBIT_DEFAULT << 1) /**< Shifted mode DEFAULT for ETM_ETMSR */ #define ETM_ETMSR_TRACESTAT (0x1UL << 2) /**< Trace Start/Stop Status */ #define _ETM_ETMSR_TRACESTAT_SHIFT 2 /**< Shift value for ETM_TRACESTAT */ #define _ETM_ETMSR_TRACESTAT_MASK 0x4UL /**< Bit mask for ETM_TRACESTAT */ #define _ETM_ETMSR_TRACESTAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMSR */ #define ETM_ETMSR_TRACESTAT_DEFAULT (_ETM_ETMSR_TRACESTAT_DEFAULT << 2) /**< Shifted mode DEFAULT for ETM_ETMSR */ #define ETM_ETMSR_TRIGBIT (0x1UL << 3) /**< Trigger Bit */ #define _ETM_ETMSR_TRIGBIT_SHIFT 3 /**< Shift value for ETM_TRIGBIT */ #define _ETM_ETMSR_TRIGBIT_MASK 0x8UL /**< Bit mask for ETM_TRIGBIT */ #define _ETM_ETMSR_TRIGBIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMSR */ #define ETM_ETMSR_TRIGBIT_DEFAULT (_ETM_ETMSR_TRIGBIT_DEFAULT << 3) /**< Shifted mode DEFAULT for ETM_ETMSR */ /* Bit fields for ETM ETMSCR */ #define _ETM_ETMSCR_RESETVALUE 0x00020D09UL /**< Default value for ETM_ETMSCR */ #define _ETM_ETMSCR_MASK 0x00027F0FUL /**< Mask for ETM_ETMSCR */ #define _ETM_ETMSCR_MAXPORTSIZE_SHIFT 0 /**< Shift value for ETM_MAXPORTSIZE */ #define _ETM_ETMSCR_MAXPORTSIZE_MASK 0x7UL /**< Bit mask for ETM_MAXPORTSIZE */ #define _ETM_ETMSCR_MAXPORTSIZE_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMSCR */ #define ETM_ETMSCR_MAXPORTSIZE_DEFAULT (_ETM_ETMSCR_MAXPORTSIZE_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMSCR */ #define ETM_ETMSCR_FIFOFULL (0x1UL << 8) /**< FIFO FULL Supported */ #define _ETM_ETMSCR_FIFOFULL_SHIFT 8 /**< Shift value for ETM_FIFOFULL */ #define _ETM_ETMSCR_FIFOFULL_MASK 0x100UL /**< Bit mask for ETM_FIFOFULL */ #define _ETM_ETMSCR_FIFOFULL_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMSCR */ #define ETM_ETMSCR_FIFOFULL_DEFAULT (_ETM_ETMSCR_FIFOFULL_DEFAULT << 8) /**< Shifted mode DEFAULT for ETM_ETMSCR */ #define ETM_ETMSCR_MAXPORTSIZE3 (0x1UL << 9) /**< Max Port Size[3] */ #define _ETM_ETMSCR_MAXPORTSIZE3_SHIFT 9 /**< Shift value for ETM_MAXPORTSIZE3 */ #define _ETM_ETMSCR_MAXPORTSIZE3_MASK 0x200UL /**< Bit mask for ETM_MAXPORTSIZE3 */ #define _ETM_ETMSCR_MAXPORTSIZE3_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMSCR */ #define ETM_ETMSCR_MAXPORTSIZE3_DEFAULT (_ETM_ETMSCR_MAXPORTSIZE3_DEFAULT << 9) /**< Shifted mode DEFAULT for ETM_ETMSCR */ #define ETM_ETMSCR_PORTSIZE (0x1UL << 10) /**< Port Size Supported */ #define _ETM_ETMSCR_PORTSIZE_SHIFT 10 /**< Shift value for ETM_PORTSIZE */ #define _ETM_ETMSCR_PORTSIZE_MASK 0x400UL /**< Bit mask for ETM_PORTSIZE */ #define _ETM_ETMSCR_PORTSIZE_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMSCR */ #define ETM_ETMSCR_PORTSIZE_DEFAULT (_ETM_ETMSCR_PORTSIZE_DEFAULT << 10) /**< Shifted mode DEFAULT for ETM_ETMSCR */ #define ETM_ETMSCR_PORTMODE (0x1UL << 11) /**< Port Mode Supported */ #define _ETM_ETMSCR_PORTMODE_SHIFT 11 /**< Shift value for ETM_PORTMODE */ #define _ETM_ETMSCR_PORTMODE_MASK 0x800UL /**< Bit mask for ETM_PORTMODE */ #define _ETM_ETMSCR_PORTMODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMSCR */ #define ETM_ETMSCR_PORTMODE_DEFAULT (_ETM_ETMSCR_PORTMODE_DEFAULT << 11) /**< Shifted mode DEFAULT for ETM_ETMSCR */ #define _ETM_ETMSCR_PROCNUM_SHIFT 12 /**< Shift value for ETM_PROCNUM */ #define _ETM_ETMSCR_PROCNUM_MASK 0x7000UL /**< Bit mask for ETM_PROCNUM */ #define _ETM_ETMSCR_PROCNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMSCR */ #define ETM_ETMSCR_PROCNUM_DEFAULT (_ETM_ETMSCR_PROCNUM_DEFAULT << 12) /**< Shifted mode DEFAULT for ETM_ETMSCR */ #define ETM_ETMSCR_NOFETCHCOMP (0x1UL << 17) /**< No Fetch Comparison */ #define _ETM_ETMSCR_NOFETCHCOMP_SHIFT 17 /**< Shift value for ETM_NOFETCHCOMP */ #define _ETM_ETMSCR_NOFETCHCOMP_MASK 0x20000UL /**< Bit mask for ETM_NOFETCHCOMP */ #define _ETM_ETMSCR_NOFETCHCOMP_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMSCR */ #define ETM_ETMSCR_NOFETCHCOMP_DEFAULT (_ETM_ETMSCR_NOFETCHCOMP_DEFAULT << 17) /**< Shifted mode DEFAULT for ETM_ETMSCR */ /* Bit fields for ETM ETMTEEVR */ #define _ETM_ETMTEEVR_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMTEEVR */ #define _ETM_ETMTEEVR_MASK 0x0001FFFFUL /**< Mask for ETM_ETMTEEVR */ #define _ETM_ETMTEEVR_RESA_SHIFT 0 /**< Shift value for ETM_RESA */ #define _ETM_ETMTEEVR_RESA_MASK 0x7FUL /**< Bit mask for ETM_RESA */ #define _ETM_ETMTEEVR_RESA_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTEEVR */ #define ETM_ETMTEEVR_RESA_DEFAULT (_ETM_ETMTEEVR_RESA_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMTEEVR */ #define _ETM_ETMTEEVR_RESB_SHIFT 7 /**< Shift value for ETM_RESB */ #define _ETM_ETMTEEVR_RESB_MASK 0x3F80UL /**< Bit mask for ETM_RESB */ #define _ETM_ETMTEEVR_RESB_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTEEVR */ #define ETM_ETMTEEVR_RESB_DEFAULT (_ETM_ETMTEEVR_RESB_DEFAULT << 7) /**< Shifted mode DEFAULT for ETM_ETMTEEVR */ #define _ETM_ETMTEEVR_ETMFCNEN_SHIFT 14 /**< Shift value for ETM_ETMFCNEN */ #define _ETM_ETMTEEVR_ETMFCNEN_MASK 0x1C000UL /**< Bit mask for ETM_ETMFCNEN */ #define _ETM_ETMTEEVR_ETMFCNEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTEEVR */ #define ETM_ETMTEEVR_ETMFCNEN_DEFAULT (_ETM_ETMTEEVR_ETMFCNEN_DEFAULT << 14) /**< Shifted mode DEFAULT for ETM_ETMTEEVR */ /* Bit fields for ETM ETMTECR1 */ #define _ETM_ETMTECR1_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMTECR1 */ #define _ETM_ETMTECR1_MASK 0x03FFFFFFUL /**< Mask for ETM_ETMTECR1 */ #define _ETM_ETMTECR1_ADRCMP_SHIFT 0 /**< Shift value for ETM_ADRCMP */ #define _ETM_ETMTECR1_ADRCMP_MASK 0xFFUL /**< Bit mask for ETM_ADRCMP */ #define _ETM_ETMTECR1_ADRCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTECR1 */ #define ETM_ETMTECR1_ADRCMP_DEFAULT (_ETM_ETMTECR1_ADRCMP_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMTECR1 */ #define _ETM_ETMTECR1_MEMMAP_SHIFT 8 /**< Shift value for ETM_MEMMAP */ #define _ETM_ETMTECR1_MEMMAP_MASK 0xFFFF00UL /**< Bit mask for ETM_MEMMAP */ #define _ETM_ETMTECR1_MEMMAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTECR1 */ #define ETM_ETMTECR1_MEMMAP_DEFAULT (_ETM_ETMTECR1_MEMMAP_DEFAULT << 8) /**< Shifted mode DEFAULT for ETM_ETMTECR1 */ #define ETM_ETMTECR1_INCEXCTL (0x1UL << 24) /**< Trace Include/Exclude Flag */ #define _ETM_ETMTECR1_INCEXCTL_SHIFT 24 /**< Shift value for ETM_INCEXCTL */ #define _ETM_ETMTECR1_INCEXCTL_MASK 0x1000000UL /**< Bit mask for ETM_INCEXCTL */ #define _ETM_ETMTECR1_INCEXCTL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTECR1 */ #define _ETM_ETMTECR1_INCEXCTL_INC 0x00000000UL /**< Mode INC for ETM_ETMTECR1 */ #define _ETM_ETMTECR1_INCEXCTL_EXC 0x00000001UL /**< Mode EXC for ETM_ETMTECR1 */ #define ETM_ETMTECR1_INCEXCTL_DEFAULT (_ETM_ETMTECR1_INCEXCTL_DEFAULT << 24) /**< Shifted mode DEFAULT for ETM_ETMTECR1 */ #define ETM_ETMTECR1_INCEXCTL_INC (_ETM_ETMTECR1_INCEXCTL_INC << 24) /**< Shifted mode INC for ETM_ETMTECR1 */ #define ETM_ETMTECR1_INCEXCTL_EXC (_ETM_ETMTECR1_INCEXCTL_EXC << 24) /**< Shifted mode EXC for ETM_ETMTECR1 */ #define ETM_ETMTECR1_TCE (0x1UL << 25) /**< Trace Control Enable */ #define _ETM_ETMTECR1_TCE_SHIFT 25 /**< Shift value for ETM_TCE */ #define _ETM_ETMTECR1_TCE_MASK 0x2000000UL /**< Bit mask for ETM_TCE */ #define _ETM_ETMTECR1_TCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTECR1 */ #define _ETM_ETMTECR1_TCE_EN 0x00000000UL /**< Mode EN for ETM_ETMTECR1 */ #define _ETM_ETMTECR1_TCE_DIS 0x00000001UL /**< Mode DIS for ETM_ETMTECR1 */ #define ETM_ETMTECR1_TCE_DEFAULT (_ETM_ETMTECR1_TCE_DEFAULT << 25) /**< Shifted mode DEFAULT for ETM_ETMTECR1 */ #define ETM_ETMTECR1_TCE_EN (_ETM_ETMTECR1_TCE_EN << 25) /**< Shifted mode EN for ETM_ETMTECR1 */ #define ETM_ETMTECR1_TCE_DIS (_ETM_ETMTECR1_TCE_DIS << 25) /**< Shifted mode DIS for ETM_ETMTECR1 */ /* Bit fields for ETM ETMFFLR */ #define _ETM_ETMFFLR_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMFFLR */ #define _ETM_ETMFFLR_MASK 0x000000FFUL /**< Mask for ETM_ETMFFLR */ #define _ETM_ETMFFLR_BYTENUM_SHIFT 0 /**< Shift value for ETM_BYTENUM */ #define _ETM_ETMFFLR_BYTENUM_MASK 0xFFUL /**< Bit mask for ETM_BYTENUM */ #define _ETM_ETMFFLR_BYTENUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMFFLR */ #define ETM_ETMFFLR_BYTENUM_DEFAULT (_ETM_ETMFFLR_BYTENUM_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMFFLR */ /* Bit fields for ETM ETMCNTRLDVR1 */ #define _ETM_ETMCNTRLDVR1_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMCNTRLDVR1 */ #define _ETM_ETMCNTRLDVR1_MASK 0x0000FFFFUL /**< Mask for ETM_ETMCNTRLDVR1 */ #define _ETM_ETMCNTRLDVR1_COUNT_SHIFT 0 /**< Shift value for ETM_COUNT */ #define _ETM_ETMCNTRLDVR1_COUNT_MASK 0xFFFFUL /**< Bit mask for ETM_COUNT */ #define _ETM_ETMCNTRLDVR1_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCNTRLDVR1 */ #define ETM_ETMCNTRLDVR1_COUNT_DEFAULT (_ETM_ETMCNTRLDVR1_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCNTRLDVR1 */ /* Bit fields for ETM ETMSYNCFR */ #define _ETM_ETMSYNCFR_RESETVALUE 0x00000400UL /**< Default value for ETM_ETMSYNCFR */ #define _ETM_ETMSYNCFR_MASK 0x00000FFFUL /**< Mask for ETM_ETMSYNCFR */ #define _ETM_ETMSYNCFR_FREQ_SHIFT 0 /**< Shift value for ETM_FREQ */ #define _ETM_ETMSYNCFR_FREQ_MASK 0xFFFUL /**< Bit mask for ETM_FREQ */ #define _ETM_ETMSYNCFR_FREQ_DEFAULT 0x00000400UL /**< Mode DEFAULT for ETM_ETMSYNCFR */ #define ETM_ETMSYNCFR_FREQ_DEFAULT (_ETM_ETMSYNCFR_FREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMSYNCFR */ /* Bit fields for ETM ETMIDR */ #define _ETM_ETMIDR_RESETVALUE 0x4114F253UL /**< Default value for ETM_ETMIDR */ #define _ETM_ETMIDR_MASK 0xFF1DFFFFUL /**< Mask for ETM_ETMIDR */ #define _ETM_ETMIDR_IMPVER_SHIFT 0 /**< Shift value for ETM_IMPVER */ #define _ETM_ETMIDR_IMPVER_MASK 0xFUL /**< Bit mask for ETM_IMPVER */ #define _ETM_ETMIDR_IMPVER_DEFAULT 0x00000003UL /**< Mode DEFAULT for ETM_ETMIDR */ #define ETM_ETMIDR_IMPVER_DEFAULT (_ETM_ETMIDR_IMPVER_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMIDR */ #define _ETM_ETMIDR_ETMMINVER_SHIFT 4 /**< Shift value for ETM_ETMMINVER */ #define _ETM_ETMIDR_ETMMINVER_MASK 0xF0UL /**< Bit mask for ETM_ETMMINVER */ #define _ETM_ETMIDR_ETMMINVER_DEFAULT 0x00000005UL /**< Mode DEFAULT for ETM_ETMIDR */ #define ETM_ETMIDR_ETMMINVER_DEFAULT (_ETM_ETMIDR_ETMMINVER_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMIDR */ #define _ETM_ETMIDR_ETMMAJVER_SHIFT 8 /**< Shift value for ETM_ETMMAJVER */ #define _ETM_ETMIDR_ETMMAJVER_MASK 0xF00UL /**< Bit mask for ETM_ETMMAJVER */ #define _ETM_ETMIDR_ETMMAJVER_DEFAULT 0x00000002UL /**< Mode DEFAULT for ETM_ETMIDR */ #define ETM_ETMIDR_ETMMAJVER_DEFAULT (_ETM_ETMIDR_ETMMAJVER_DEFAULT << 8) /**< Shifted mode DEFAULT for ETM_ETMIDR */ #define _ETM_ETMIDR_PROCFAM_SHIFT 12 /**< Shift value for ETM_PROCFAM */ #define _ETM_ETMIDR_PROCFAM_MASK 0xF000UL /**< Bit mask for ETM_PROCFAM */ #define _ETM_ETMIDR_PROCFAM_DEFAULT 0x0000000FUL /**< Mode DEFAULT for ETM_ETMIDR */ #define ETM_ETMIDR_PROCFAM_DEFAULT (_ETM_ETMIDR_PROCFAM_DEFAULT << 12) /**< Shifted mode DEFAULT for ETM_ETMIDR */ #define ETM_ETMIDR_LPCF (0x1UL << 16) /**< Load PC First */ #define _ETM_ETMIDR_LPCF_SHIFT 16 /**< Shift value for ETM_LPCF */ #define _ETM_ETMIDR_LPCF_MASK 0x10000UL /**< Bit mask for ETM_LPCF */ #define _ETM_ETMIDR_LPCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMIDR */ #define ETM_ETMIDR_LPCF_DEFAULT (_ETM_ETMIDR_LPCF_DEFAULT << 16) /**< Shifted mode DEFAULT for ETM_ETMIDR */ #define ETM_ETMIDR_THUMBT (0x1UL << 18) /**< 32-bit Thumb Instruction Tracing */ #define _ETM_ETMIDR_THUMBT_SHIFT 18 /**< Shift value for ETM_THUMBT */ #define _ETM_ETMIDR_THUMBT_MASK 0x40000UL /**< Bit mask for ETM_THUMBT */ #define _ETM_ETMIDR_THUMBT_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMIDR */ #define ETM_ETMIDR_THUMBT_DEFAULT (_ETM_ETMIDR_THUMBT_DEFAULT << 18) /**< Shifted mode DEFAULT for ETM_ETMIDR */ #define ETM_ETMIDR_SECEXT (0x1UL << 19) /**< Security Extension Support */ #define _ETM_ETMIDR_SECEXT_SHIFT 19 /**< Shift value for ETM_SECEXT */ #define _ETM_ETMIDR_SECEXT_MASK 0x80000UL /**< Bit mask for ETM_SECEXT */ #define _ETM_ETMIDR_SECEXT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMIDR */ #define ETM_ETMIDR_SECEXT_DEFAULT (_ETM_ETMIDR_SECEXT_DEFAULT << 19) /**< Shifted mode DEFAULT for ETM_ETMIDR */ #define ETM_ETMIDR_BPE (0x1UL << 20) /**< Branch Packet Encoding */ #define _ETM_ETMIDR_BPE_SHIFT 20 /**< Shift value for ETM_BPE */ #define _ETM_ETMIDR_BPE_MASK 0x100000UL /**< Bit mask for ETM_BPE */ #define _ETM_ETMIDR_BPE_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMIDR */ #define ETM_ETMIDR_BPE_DEFAULT (_ETM_ETMIDR_BPE_DEFAULT << 20) /**< Shifted mode DEFAULT for ETM_ETMIDR */ #define _ETM_ETMIDR_IMPCODE_SHIFT 24 /**< Shift value for ETM_IMPCODE */ #define _ETM_ETMIDR_IMPCODE_MASK 0xFF000000UL /**< Bit mask for ETM_IMPCODE */ #define _ETM_ETMIDR_IMPCODE_DEFAULT 0x00000041UL /**< Mode DEFAULT for ETM_ETMIDR */ #define ETM_ETMIDR_IMPCODE_DEFAULT (_ETM_ETMIDR_IMPCODE_DEFAULT << 24) /**< Shifted mode DEFAULT for ETM_ETMIDR */ /* Bit fields for ETM ETMCCER */ #define _ETM_ETMCCER_RESETVALUE 0x18541800UL /**< Default value for ETM_ETMCCER */ #define _ETM_ETMCCER_MASK 0x387FFFFBUL /**< Mask for ETM_ETMCCER */ #define _ETM_ETMCCER_EXTINPSEL_SHIFT 0 /**< Shift value for ETM_EXTINPSEL */ #define _ETM_ETMCCER_EXTINPSEL_MASK 0x3UL /**< Bit mask for ETM_EXTINPSEL */ #define _ETM_ETMCCER_EXTINPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCER */ #define ETM_ETMCCER_EXTINPSEL_DEFAULT (_ETM_ETMCCER_EXTINPSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCCER */ #define _ETM_ETMCCER_EXTINPBUS_SHIFT 3 /**< Shift value for ETM_EXTINPBUS */ #define _ETM_ETMCCER_EXTINPBUS_MASK 0x7F8UL /**< Bit mask for ETM_EXTINPBUS */ #define _ETM_ETMCCER_EXTINPBUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCER */ #define ETM_ETMCCER_EXTINPBUS_DEFAULT (_ETM_ETMCCER_EXTINPBUS_DEFAULT << 3) /**< Shifted mode DEFAULT for ETM_ETMCCER */ #define ETM_ETMCCER_READREGS (0x1UL << 11) /**< Readable Registers */ #define _ETM_ETMCCER_READREGS_SHIFT 11 /**< Shift value for ETM_READREGS */ #define _ETM_ETMCCER_READREGS_MASK 0x800UL /**< Bit mask for ETM_READREGS */ #define _ETM_ETMCCER_READREGS_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCER */ #define ETM_ETMCCER_READREGS_DEFAULT (_ETM_ETMCCER_READREGS_DEFAULT << 11) /**< Shifted mode DEFAULT for ETM_ETMCCER */ #define ETM_ETMCCER_DADDRCMP (0x1UL << 12) /**< Data Address comparisons */ #define _ETM_ETMCCER_DADDRCMP_SHIFT 12 /**< Shift value for ETM_DADDRCMP */ #define _ETM_ETMCCER_DADDRCMP_MASK 0x1000UL /**< Bit mask for ETM_DADDRCMP */ #define _ETM_ETMCCER_DADDRCMP_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCER */ #define ETM_ETMCCER_DADDRCMP_DEFAULT (_ETM_ETMCCER_DADDRCMP_DEFAULT << 12) /**< Shifted mode DEFAULT for ETM_ETMCCER */ #define _ETM_ETMCCER_INSTRES_SHIFT 13 /**< Shift value for ETM_INSTRES */ #define _ETM_ETMCCER_INSTRES_MASK 0xE000UL /**< Bit mask for ETM_INSTRES */ #define _ETM_ETMCCER_INSTRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCER */ #define ETM_ETMCCER_INSTRES_DEFAULT (_ETM_ETMCCER_INSTRES_DEFAULT << 13) /**< Shifted mode DEFAULT for ETM_ETMCCER */ #define _ETM_ETMCCER_EICEWPNT_SHIFT 16 /**< Shift value for ETM_EICEWPNT */ #define _ETM_ETMCCER_EICEWPNT_MASK 0xF0000UL /**< Bit mask for ETM_EICEWPNT */ #define _ETM_ETMCCER_EICEWPNT_DEFAULT 0x00000004UL /**< Mode DEFAULT for ETM_ETMCCER */ #define ETM_ETMCCER_EICEWPNT_DEFAULT (_ETM_ETMCCER_EICEWPNT_DEFAULT << 16) /**< Shifted mode DEFAULT for ETM_ETMCCER */ #define ETM_ETMCCER_TEICEWPNT (0x1UL << 20) /**< Trace Sart/Stop Block Uses EmbeddedICE watchpoint inputs */ #define _ETM_ETMCCER_TEICEWPNT_SHIFT 20 /**< Shift value for ETM_TEICEWPNT */ #define _ETM_ETMCCER_TEICEWPNT_MASK 0x100000UL /**< Bit mask for ETM_TEICEWPNT */ #define _ETM_ETMCCER_TEICEWPNT_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCER */ #define ETM_ETMCCER_TEICEWPNT_DEFAULT (_ETM_ETMCCER_TEICEWPNT_DEFAULT << 20) /**< Shifted mode DEFAULT for ETM_ETMCCER */ #define ETM_ETMCCER_EICEIMP (0x1UL << 21) /**< EmbeddedICE Behavior control Implemented */ #define _ETM_ETMCCER_EICEIMP_SHIFT 21 /**< Shift value for ETM_EICEIMP */ #define _ETM_ETMCCER_EICEIMP_MASK 0x200000UL /**< Bit mask for ETM_EICEIMP */ #define _ETM_ETMCCER_EICEIMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCER */ #define ETM_ETMCCER_EICEIMP_DEFAULT (_ETM_ETMCCER_EICEIMP_DEFAULT << 21) /**< Shifted mode DEFAULT for ETM_ETMCCER */ #define ETM_ETMCCER_TIMP (0x1UL << 22) /**< Timestamping Implemented */ #define _ETM_ETMCCER_TIMP_SHIFT 22 /**< Shift value for ETM_TIMP */ #define _ETM_ETMCCER_TIMP_MASK 0x400000UL /**< Bit mask for ETM_TIMP */ #define _ETM_ETMCCER_TIMP_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCER */ #define ETM_ETMCCER_TIMP_DEFAULT (_ETM_ETMCCER_TIMP_DEFAULT << 22) /**< Shifted mode DEFAULT for ETM_ETMCCER */ #define ETM_ETMCCER_RFCNT (0x1UL << 27) /**< Reduced Function Counter */ #define _ETM_ETMCCER_RFCNT_SHIFT 27 /**< Shift value for ETM_RFCNT */ #define _ETM_ETMCCER_RFCNT_MASK 0x8000000UL /**< Bit mask for ETM_RFCNT */ #define _ETM_ETMCCER_RFCNT_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCER */ #define ETM_ETMCCER_RFCNT_DEFAULT (_ETM_ETMCCER_RFCNT_DEFAULT << 27) /**< Shifted mode DEFAULT for ETM_ETMCCER */ #define ETM_ETMCCER_TENC (0x1UL << 28) /**< Timestamp Encoding */ #define _ETM_ETMCCER_TENC_SHIFT 28 /**< Shift value for ETM_TENC */ #define _ETM_ETMCCER_TENC_MASK 0x10000000UL /**< Bit mask for ETM_TENC */ #define _ETM_ETMCCER_TENC_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCER */ #define ETM_ETMCCER_TENC_DEFAULT (_ETM_ETMCCER_TENC_DEFAULT << 28) /**< Shifted mode DEFAULT for ETM_ETMCCER */ #define ETM_ETMCCER_TSIZE (0x1UL << 29) /**< Timestamp Size */ #define _ETM_ETMCCER_TSIZE_SHIFT 29 /**< Shift value for ETM_TSIZE */ #define _ETM_ETMCCER_TSIZE_MASK 0x20000000UL /**< Bit mask for ETM_TSIZE */ #define _ETM_ETMCCER_TSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCER */ #define ETM_ETMCCER_TSIZE_DEFAULT (_ETM_ETMCCER_TSIZE_DEFAULT << 29) /**< Shifted mode DEFAULT for ETM_ETMCCER */ /* Bit fields for ETM ETMTESSEICR */ #define _ETM_ETMTESSEICR_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMTESSEICR */ #define _ETM_ETMTESSEICR_MASK 0x000F000FUL /**< Mask for ETM_ETMTESSEICR */ #define _ETM_ETMTESSEICR_STARTRSEL_SHIFT 0 /**< Shift value for ETM_STARTRSEL */ #define _ETM_ETMTESSEICR_STARTRSEL_MASK 0xFUL /**< Bit mask for ETM_STARTRSEL */ #define _ETM_ETMTESSEICR_STARTRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTESSEICR */ #define ETM_ETMTESSEICR_STARTRSEL_DEFAULT (_ETM_ETMTESSEICR_STARTRSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMTESSEICR */ #define _ETM_ETMTESSEICR_STOPRSEL_SHIFT 16 /**< Shift value for ETM_STOPRSEL */ #define _ETM_ETMTESSEICR_STOPRSEL_MASK 0xF0000UL /**< Bit mask for ETM_STOPRSEL */ #define _ETM_ETMTESSEICR_STOPRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTESSEICR */ #define ETM_ETMTESSEICR_STOPRSEL_DEFAULT (_ETM_ETMTESSEICR_STOPRSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for ETM_ETMTESSEICR */ /* Bit fields for ETM ETMTSEVR */ #define _ETM_ETMTSEVR_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMTSEVR */ #define _ETM_ETMTSEVR_MASK 0x0001FFFFUL /**< Mask for ETM_ETMTSEVR */ #define _ETM_ETMTSEVR_RESAEVT_SHIFT 0 /**< Shift value for ETM_RESAEVT */ #define _ETM_ETMTSEVR_RESAEVT_MASK 0x7FUL /**< Bit mask for ETM_RESAEVT */ #define _ETM_ETMTSEVR_RESAEVT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTSEVR */ #define ETM_ETMTSEVR_RESAEVT_DEFAULT (_ETM_ETMTSEVR_RESAEVT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMTSEVR */ #define _ETM_ETMTSEVR_RESBEVT_SHIFT 7 /**< Shift value for ETM_RESBEVT */ #define _ETM_ETMTSEVR_RESBEVT_MASK 0x3F80UL /**< Bit mask for ETM_RESBEVT */ #define _ETM_ETMTSEVR_RESBEVT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTSEVR */ #define ETM_ETMTSEVR_RESBEVT_DEFAULT (_ETM_ETMTSEVR_RESBEVT_DEFAULT << 7) /**< Shifted mode DEFAULT for ETM_ETMTSEVR */ #define _ETM_ETMTSEVR_ETMFCNEVT_SHIFT 14 /**< Shift value for ETM_ETMFCNEVT */ #define _ETM_ETMTSEVR_ETMFCNEVT_MASK 0x1C000UL /**< Bit mask for ETM_ETMFCNEVT */ #define _ETM_ETMTSEVR_ETMFCNEVT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTSEVR */ #define ETM_ETMTSEVR_ETMFCNEVT_DEFAULT (_ETM_ETMTSEVR_ETMFCNEVT_DEFAULT << 14) /**< Shifted mode DEFAULT for ETM_ETMTSEVR */ /* Bit fields for ETM ETMTRACEIDR */ #define _ETM_ETMTRACEIDR_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMTRACEIDR */ #define _ETM_ETMTRACEIDR_MASK 0x0000007FUL /**< Mask for ETM_ETMTRACEIDR */ #define _ETM_ETMTRACEIDR_TRACEID_SHIFT 0 /**< Shift value for ETM_TRACEID */ #define _ETM_ETMTRACEIDR_TRACEID_MASK 0x7FUL /**< Bit mask for ETM_TRACEID */ #define _ETM_ETMTRACEIDR_TRACEID_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTRACEIDR */ #define ETM_ETMTRACEIDR_TRACEID_DEFAULT (_ETM_ETMTRACEIDR_TRACEID_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMTRACEIDR */ /* Bit fields for ETM ETMIDR2 */ #define _ETM_ETMIDR2_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMIDR2 */ #define _ETM_ETMIDR2_MASK 0x00000003UL /**< Mask for ETM_ETMIDR2 */ #define ETM_ETMIDR2_RFE (0x1UL << 0) /**< RFE Transfer Order */ #define _ETM_ETMIDR2_RFE_SHIFT 0 /**< Shift value for ETM_RFE */ #define _ETM_ETMIDR2_RFE_MASK 0x1UL /**< Bit mask for ETM_RFE */ #define _ETM_ETMIDR2_RFE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMIDR2 */ #define _ETM_ETMIDR2_RFE_PC 0x00000000UL /**< Mode PC for ETM_ETMIDR2 */ #define _ETM_ETMIDR2_RFE_CPSR 0x00000001UL /**< Mode CPSR for ETM_ETMIDR2 */ #define ETM_ETMIDR2_RFE_DEFAULT (_ETM_ETMIDR2_RFE_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMIDR2 */ #define ETM_ETMIDR2_RFE_PC (_ETM_ETMIDR2_RFE_PC << 0) /**< Shifted mode PC for ETM_ETMIDR2 */ #define ETM_ETMIDR2_RFE_CPSR (_ETM_ETMIDR2_RFE_CPSR << 0) /**< Shifted mode CPSR for ETM_ETMIDR2 */ #define ETM_ETMIDR2_SWP (0x1UL << 1) /**< SWP Transfer Order */ #define _ETM_ETMIDR2_SWP_SHIFT 1 /**< Shift value for ETM_SWP */ #define _ETM_ETMIDR2_SWP_MASK 0x2UL /**< Bit mask for ETM_SWP */ #define _ETM_ETMIDR2_SWP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMIDR2 */ #define _ETM_ETMIDR2_SWP_LOAD 0x00000000UL /**< Mode LOAD for ETM_ETMIDR2 */ #define _ETM_ETMIDR2_SWP_STORE 0x00000001UL /**< Mode STORE for ETM_ETMIDR2 */ #define ETM_ETMIDR2_SWP_DEFAULT (_ETM_ETMIDR2_SWP_DEFAULT << 1) /**< Shifted mode DEFAULT for ETM_ETMIDR2 */ #define ETM_ETMIDR2_SWP_LOAD (_ETM_ETMIDR2_SWP_LOAD << 1) /**< Shifted mode LOAD for ETM_ETMIDR2 */ #define ETM_ETMIDR2_SWP_STORE (_ETM_ETMIDR2_SWP_STORE << 1) /**< Shifted mode STORE for ETM_ETMIDR2 */ /* Bit fields for ETM ETMPDSR */ #define _ETM_ETMPDSR_RESETVALUE 0x00000001UL /**< Default value for ETM_ETMPDSR */ #define _ETM_ETMPDSR_MASK 0x00000001UL /**< Mask for ETM_ETMPDSR */ #define ETM_ETMPDSR_ETMUP (0x1UL << 0) /**< ETM Powered Up */ #define _ETM_ETMPDSR_ETMUP_SHIFT 0 /**< Shift value for ETM_ETMUP */ #define _ETM_ETMPDSR_ETMUP_MASK 0x1UL /**< Bit mask for ETM_ETMUP */ #define _ETM_ETMPDSR_ETMUP_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMPDSR */ #define ETM_ETMPDSR_ETMUP_DEFAULT (_ETM_ETMPDSR_ETMUP_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMPDSR */ /* Bit fields for ETM ETMISCIN */ #define _ETM_ETMISCIN_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMISCIN */ #define _ETM_ETMISCIN_MASK 0x00000013UL /**< Mask for ETM_ETMISCIN */ #define _ETM_ETMISCIN_EXTIN_SHIFT 0 /**< Shift value for ETM_EXTIN */ #define _ETM_ETMISCIN_EXTIN_MASK 0x3UL /**< Bit mask for ETM_EXTIN */ #define _ETM_ETMISCIN_EXTIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMISCIN */ #define ETM_ETMISCIN_EXTIN_DEFAULT (_ETM_ETMISCIN_EXTIN_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMISCIN */ #define ETM_ETMISCIN_COREHALT (0x1UL << 4) /**< Core Halt */ #define _ETM_ETMISCIN_COREHALT_SHIFT 4 /**< Shift value for ETM_COREHALT */ #define _ETM_ETMISCIN_COREHALT_MASK 0x10UL /**< Bit mask for ETM_COREHALT */ #define _ETM_ETMISCIN_COREHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMISCIN */ #define ETM_ETMISCIN_COREHALT_DEFAULT (_ETM_ETMISCIN_COREHALT_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMISCIN */ /* Bit fields for ETM ITTRIGOUT */ #define _ETM_ITTRIGOUT_RESETVALUE 0x00000000UL /**< Default value for ETM_ITTRIGOUT */ #define _ETM_ITTRIGOUT_MASK 0x00000001UL /**< Mask for ETM_ITTRIGOUT */ #define ETM_ITTRIGOUT_TRIGGEROUT (0x1UL << 0) /**< Trigger output value */ #define _ETM_ITTRIGOUT_TRIGGEROUT_SHIFT 0 /**< Shift value for ETM_TRIGGEROUT */ #define _ETM_ITTRIGOUT_TRIGGEROUT_MASK 0x1UL /**< Bit mask for ETM_TRIGGEROUT */ #define _ETM_ITTRIGOUT_TRIGGEROUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ITTRIGOUT */ #define ETM_ITTRIGOUT_TRIGGEROUT_DEFAULT (_ETM_ITTRIGOUT_TRIGGEROUT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ITTRIGOUT */ /* Bit fields for ETM ETMITATBCTR2 */ #define _ETM_ETMITATBCTR2_RESETVALUE 0x00000001UL /**< Default value for ETM_ETMITATBCTR2 */ #define _ETM_ETMITATBCTR2_MASK 0x00000001UL /**< Mask for ETM_ETMITATBCTR2 */ #define ETM_ETMITATBCTR2_ATREADY (0x1UL << 0) /**< ATREADY Input Value */ #define _ETM_ETMITATBCTR2_ATREADY_SHIFT 0 /**< Shift value for ETM_ATREADY */ #define _ETM_ETMITATBCTR2_ATREADY_MASK 0x1UL /**< Bit mask for ETM_ATREADY */ #define _ETM_ETMITATBCTR2_ATREADY_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMITATBCTR2 */ #define ETM_ETMITATBCTR2_ATREADY_DEFAULT (_ETM_ETMITATBCTR2_ATREADY_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMITATBCTR2 */ /* Bit fields for ETM ETMITATBCTR0 */ #define _ETM_ETMITATBCTR0_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMITATBCTR0 */ #define _ETM_ETMITATBCTR0_MASK 0x00000001UL /**< Mask for ETM_ETMITATBCTR0 */ #define ETM_ETMITATBCTR0_ATVALID (0x1UL << 0) /**< ATVALID Output Value */ #define _ETM_ETMITATBCTR0_ATVALID_SHIFT 0 /**< Shift value for ETM_ATVALID */ #define _ETM_ETMITATBCTR0_ATVALID_MASK 0x1UL /**< Bit mask for ETM_ATVALID */ #define _ETM_ETMITATBCTR0_ATVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMITATBCTR0 */ #define ETM_ETMITATBCTR0_ATVALID_DEFAULT (_ETM_ETMITATBCTR0_ATVALID_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMITATBCTR0 */ /* Bit fields for ETM ETMITCTRL */ #define _ETM_ETMITCTRL_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMITCTRL */ #define _ETM_ETMITCTRL_MASK 0x00000001UL /**< Mask for ETM_ETMITCTRL */ #define ETM_ETMITCTRL_ITEN (0x1UL << 0) /**< Integration Mode Enable */ #define _ETM_ETMITCTRL_ITEN_SHIFT 0 /**< Shift value for ETM_ITEN */ #define _ETM_ETMITCTRL_ITEN_MASK 0x1UL /**< Bit mask for ETM_ITEN */ #define _ETM_ETMITCTRL_ITEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMITCTRL */ #define ETM_ETMITCTRL_ITEN_DEFAULT (_ETM_ETMITCTRL_ITEN_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMITCTRL */ /* Bit fields for ETM ETMCLAIMSET */ #define _ETM_ETMCLAIMSET_RESETVALUE 0x0000000FUL /**< Default value for ETM_ETMCLAIMSET */ #define _ETM_ETMCLAIMSET_MASK 0x000000FFUL /**< Mask for ETM_ETMCLAIMSET */ #define _ETM_ETMCLAIMSET_SETTAG_SHIFT 0 /**< Shift value for ETM_SETTAG */ #define _ETM_ETMCLAIMSET_SETTAG_MASK 0xFFUL /**< Bit mask for ETM_SETTAG */ #define _ETM_ETMCLAIMSET_SETTAG_DEFAULT 0x0000000FUL /**< Mode DEFAULT for ETM_ETMCLAIMSET */ #define ETM_ETMCLAIMSET_SETTAG_DEFAULT (_ETM_ETMCLAIMSET_SETTAG_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCLAIMSET */ /* Bit fields for ETM ETMCLAIMCLR */ #define _ETM_ETMCLAIMCLR_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMCLAIMCLR */ #define _ETM_ETMCLAIMCLR_MASK 0x00000001UL /**< Mask for ETM_ETMCLAIMCLR */ #define ETM_ETMCLAIMCLR_CLRTAG (0x1UL << 0) /**< Tag Bits */ #define _ETM_ETMCLAIMCLR_CLRTAG_SHIFT 0 /**< Shift value for ETM_CLRTAG */ #define _ETM_ETMCLAIMCLR_CLRTAG_MASK 0x1UL /**< Bit mask for ETM_CLRTAG */ #define _ETM_ETMCLAIMCLR_CLRTAG_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCLAIMCLR */ #define ETM_ETMCLAIMCLR_CLRTAG_DEFAULT (_ETM_ETMCLAIMCLR_CLRTAG_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCLAIMCLR */ /* Bit fields for ETM ETMLAR */ #define _ETM_ETMLAR_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMLAR */ #define _ETM_ETMLAR_MASK 0x00000001UL /**< Mask for ETM_ETMLAR */ #define ETM_ETMLAR_KEY (0x1UL << 0) /**< Key Value */ #define _ETM_ETMLAR_KEY_SHIFT 0 /**< Shift value for ETM_KEY */ #define _ETM_ETMLAR_KEY_MASK 0x1UL /**< Bit mask for ETM_KEY */ #define _ETM_ETMLAR_KEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMLAR */ #define ETM_ETMLAR_KEY_DEFAULT (_ETM_ETMLAR_KEY_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMLAR */ /* Bit fields for ETM ETMLSR */ #define _ETM_ETMLSR_RESETVALUE 0x00000003UL /**< Default value for ETM_ETMLSR */ #define _ETM_ETMLSR_MASK 0x00000003UL /**< Mask for ETM_ETMLSR */ #define ETM_ETMLSR_LOCKIMP (0x1UL << 0) /**< ETM Locking Implemented */ #define _ETM_ETMLSR_LOCKIMP_SHIFT 0 /**< Shift value for ETM_LOCKIMP */ #define _ETM_ETMLSR_LOCKIMP_MASK 0x1UL /**< Bit mask for ETM_LOCKIMP */ #define _ETM_ETMLSR_LOCKIMP_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMLSR */ #define ETM_ETMLSR_LOCKIMP_DEFAULT (_ETM_ETMLSR_LOCKIMP_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMLSR */ #define ETM_ETMLSR_LOCKED (0x1UL << 1) /**< ETM locked */ #define _ETM_ETMLSR_LOCKED_SHIFT 1 /**< Shift value for ETM_LOCKED */ #define _ETM_ETMLSR_LOCKED_MASK 0x2UL /**< Bit mask for ETM_LOCKED */ #define _ETM_ETMLSR_LOCKED_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMLSR */ #define ETM_ETMLSR_LOCKED_DEFAULT (_ETM_ETMLSR_LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for ETM_ETMLSR */ /* Bit fields for ETM ETMAUTHSTATUS */ #define _ETM_ETMAUTHSTATUS_RESETVALUE 0x000000C0UL /**< Default value for ETM_ETMAUTHSTATUS */ #define _ETM_ETMAUTHSTATUS_MASK 0x000000FFUL /**< Mask for ETM_ETMAUTHSTATUS */ #define _ETM_ETMAUTHSTATUS_NONSECINVDBG_SHIFT 0 /**< Shift value for ETM_NONSECINVDBG */ #define _ETM_ETMAUTHSTATUS_NONSECINVDBG_MASK 0x3UL /**< Bit mask for ETM_NONSECINVDBG */ #define _ETM_ETMAUTHSTATUS_NONSECINVDBG_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMAUTHSTATUS */ #define ETM_ETMAUTHSTATUS_NONSECINVDBG_DEFAULT (_ETM_ETMAUTHSTATUS_NONSECINVDBG_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMAUTHSTATUS */ #define _ETM_ETMAUTHSTATUS_NONSECNONINVDBG_SHIFT 2 /**< Shift value for ETM_NONSECNONINVDBG */ #define _ETM_ETMAUTHSTATUS_NONSECNONINVDBG_MASK 0xCUL /**< Bit mask for ETM_NONSECNONINVDBG */ #define _ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMAUTHSTATUS */ #define _ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DISABLE 0x00000002UL /**< Mode DISABLE for ETM_ETMAUTHSTATUS */ #define _ETM_ETMAUTHSTATUS_NONSECNONINVDBG_ENABLE 0x00000003UL /**< Mode ENABLE for ETM_ETMAUTHSTATUS */ #define ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DEFAULT (_ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DEFAULT << 2) /**< Shifted mode DEFAULT for ETM_ETMAUTHSTATUS */ #define ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DISABLE (_ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DISABLE << 2) /**< Shifted mode DISABLE for ETM_ETMAUTHSTATUS */ #define ETM_ETMAUTHSTATUS_NONSECNONINVDBG_ENABLE (_ETM_ETMAUTHSTATUS_NONSECNONINVDBG_ENABLE << 2) /**< Shifted mode ENABLE for ETM_ETMAUTHSTATUS */ #define _ETM_ETMAUTHSTATUS_SECINVDBG_SHIFT 4 /**< Shift value for ETM_SECINVDBG */ #define _ETM_ETMAUTHSTATUS_SECINVDBG_MASK 0x30UL /**< Bit mask for ETM_SECINVDBG */ #define _ETM_ETMAUTHSTATUS_SECINVDBG_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMAUTHSTATUS */ #define ETM_ETMAUTHSTATUS_SECINVDBG_DEFAULT (_ETM_ETMAUTHSTATUS_SECINVDBG_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMAUTHSTATUS */ #define _ETM_ETMAUTHSTATUS_SECNONINVDBG_SHIFT 6 /**< Shift value for ETM_SECNONINVDBG */ #define _ETM_ETMAUTHSTATUS_SECNONINVDBG_MASK 0xC0UL /**< Bit mask for ETM_SECNONINVDBG */ #define _ETM_ETMAUTHSTATUS_SECNONINVDBG_DEFAULT 0x00000003UL /**< Mode DEFAULT for ETM_ETMAUTHSTATUS */ #define ETM_ETMAUTHSTATUS_SECNONINVDBG_DEFAULT (_ETM_ETMAUTHSTATUS_SECNONINVDBG_DEFAULT << 6) /**< Shifted mode DEFAULT for ETM_ETMAUTHSTATUS */ /* Bit fields for ETM ETMDEVTYPE */ #define _ETM_ETMDEVTYPE_RESETVALUE 0x00000013UL /**< Default value for ETM_ETMDEVTYPE */ #define _ETM_ETMDEVTYPE_MASK 0x000000FFUL /**< Mask for ETM_ETMDEVTYPE */ #define _ETM_ETMDEVTYPE_TRACESRC_SHIFT 0 /**< Shift value for ETM_TRACESRC */ #define _ETM_ETMDEVTYPE_TRACESRC_MASK 0xFUL /**< Bit mask for ETM_TRACESRC */ #define _ETM_ETMDEVTYPE_TRACESRC_DEFAULT 0x00000003UL /**< Mode DEFAULT for ETM_ETMDEVTYPE */ #define ETM_ETMDEVTYPE_TRACESRC_DEFAULT (_ETM_ETMDEVTYPE_TRACESRC_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMDEVTYPE */ #define _ETM_ETMDEVTYPE_PROCTRACE_SHIFT 4 /**< Shift value for ETM_PROCTRACE */ #define _ETM_ETMDEVTYPE_PROCTRACE_MASK 0xF0UL /**< Bit mask for ETM_PROCTRACE */ #define _ETM_ETMDEVTYPE_PROCTRACE_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMDEVTYPE */ #define ETM_ETMDEVTYPE_PROCTRACE_DEFAULT (_ETM_ETMDEVTYPE_PROCTRACE_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMDEVTYPE */ /* Bit fields for ETM ETMPIDR4 */ #define _ETM_ETMPIDR4_RESETVALUE 0x00000004UL /**< Default value for ETM_ETMPIDR4 */ #define _ETM_ETMPIDR4_MASK 0x000000FFUL /**< Mask for ETM_ETMPIDR4 */ #define _ETM_ETMPIDR4_CONTCODE_SHIFT 0 /**< Shift value for ETM_CONTCODE */ #define _ETM_ETMPIDR4_CONTCODE_MASK 0xFUL /**< Bit mask for ETM_CONTCODE */ #define _ETM_ETMPIDR4_CONTCODE_DEFAULT 0x00000004UL /**< Mode DEFAULT for ETM_ETMPIDR4 */ #define ETM_ETMPIDR4_CONTCODE_DEFAULT (_ETM_ETMPIDR4_CONTCODE_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMPIDR4 */ #define _ETM_ETMPIDR4_COUNT_SHIFT 4 /**< Shift value for ETM_COUNT */ #define _ETM_ETMPIDR4_COUNT_MASK 0xF0UL /**< Bit mask for ETM_COUNT */ #define _ETM_ETMPIDR4_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMPIDR4 */ #define ETM_ETMPIDR4_COUNT_DEFAULT (_ETM_ETMPIDR4_COUNT_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMPIDR4 */ /* Bit fields for ETM ETMPIDR5 */ #define _ETM_ETMPIDR5_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMPIDR5 */ #define _ETM_ETMPIDR5_MASK 0x00000000UL /**< Mask for ETM_ETMPIDR5 */ /* Bit fields for ETM ETMPIDR6 */ #define _ETM_ETMPIDR6_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMPIDR6 */ #define _ETM_ETMPIDR6_MASK 0x00000000UL /**< Mask for ETM_ETMPIDR6 */ /* Bit fields for ETM ETMPIDR7 */ #define _ETM_ETMPIDR7_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMPIDR7 */ #define _ETM_ETMPIDR7_MASK 0x00000000UL /**< Mask for ETM_ETMPIDR7 */ /* Bit fields for ETM ETMPIDR0 */ #define _ETM_ETMPIDR0_RESETVALUE 0x00000025UL /**< Default value for ETM_ETMPIDR0 */ #define _ETM_ETMPIDR0_MASK 0x000000FFUL /**< Mask for ETM_ETMPIDR0 */ #define _ETM_ETMPIDR0_PARTNUM_SHIFT 0 /**< Shift value for ETM_PARTNUM */ #define _ETM_ETMPIDR0_PARTNUM_MASK 0xFFUL /**< Bit mask for ETM_PARTNUM */ #define _ETM_ETMPIDR0_PARTNUM_DEFAULT 0x00000025UL /**< Mode DEFAULT for ETM_ETMPIDR0 */ #define ETM_ETMPIDR0_PARTNUM_DEFAULT (_ETM_ETMPIDR0_PARTNUM_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMPIDR0 */ /* Bit fields for ETM ETMPIDR1 */ #define _ETM_ETMPIDR1_RESETVALUE 0x000000B9UL /**< Default value for ETM_ETMPIDR1 */ #define _ETM_ETMPIDR1_MASK 0x000000FFUL /**< Mask for ETM_ETMPIDR1 */ #define _ETM_ETMPIDR1_PARTNUM_SHIFT 0 /**< Shift value for ETM_PARTNUM */ #define _ETM_ETMPIDR1_PARTNUM_MASK 0xFUL /**< Bit mask for ETM_PARTNUM */ #define _ETM_ETMPIDR1_PARTNUM_DEFAULT 0x00000009UL /**< Mode DEFAULT for ETM_ETMPIDR1 */ #define ETM_ETMPIDR1_PARTNUM_DEFAULT (_ETM_ETMPIDR1_PARTNUM_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMPIDR1 */ #define _ETM_ETMPIDR1_IDCODE_SHIFT 4 /**< Shift value for ETM_IDCODE */ #define _ETM_ETMPIDR1_IDCODE_MASK 0xF0UL /**< Bit mask for ETM_IDCODE */ #define _ETM_ETMPIDR1_IDCODE_DEFAULT 0x0000000BUL /**< Mode DEFAULT for ETM_ETMPIDR1 */ #define ETM_ETMPIDR1_IDCODE_DEFAULT (_ETM_ETMPIDR1_IDCODE_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMPIDR1 */ /* Bit fields for ETM ETMPIDR2 */ #define _ETM_ETMPIDR2_RESETVALUE 0x0000000BUL /**< Default value for ETM_ETMPIDR2 */ #define _ETM_ETMPIDR2_MASK 0x000000FFUL /**< Mask for ETM_ETMPIDR2 */ #define _ETM_ETMPIDR2_IDCODE_SHIFT 0 /**< Shift value for ETM_IDCODE */ #define _ETM_ETMPIDR2_IDCODE_MASK 0x7UL /**< Bit mask for ETM_IDCODE */ #define _ETM_ETMPIDR2_IDCODE_DEFAULT 0x00000003UL /**< Mode DEFAULT for ETM_ETMPIDR2 */ #define ETM_ETMPIDR2_IDCODE_DEFAULT (_ETM_ETMPIDR2_IDCODE_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMPIDR2 */ #define ETM_ETMPIDR2_ALWAYS1 (0x1UL << 3) /**< Always 1 */ #define _ETM_ETMPIDR2_ALWAYS1_SHIFT 3 /**< Shift value for ETM_ALWAYS1 */ #define _ETM_ETMPIDR2_ALWAYS1_MASK 0x8UL /**< Bit mask for ETM_ALWAYS1 */ #define _ETM_ETMPIDR2_ALWAYS1_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMPIDR2 */ #define ETM_ETMPIDR2_ALWAYS1_DEFAULT (_ETM_ETMPIDR2_ALWAYS1_DEFAULT << 3) /**< Shifted mode DEFAULT for ETM_ETMPIDR2 */ #define _ETM_ETMPIDR2_REV_SHIFT 4 /**< Shift value for ETM_REV */ #define _ETM_ETMPIDR2_REV_MASK 0xF0UL /**< Bit mask for ETM_REV */ #define _ETM_ETMPIDR2_REV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMPIDR2 */ #define ETM_ETMPIDR2_REV_DEFAULT (_ETM_ETMPIDR2_REV_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMPIDR2 */ /* Bit fields for ETM ETMPIDR3 */ #define _ETM_ETMPIDR3_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMPIDR3 */ #define _ETM_ETMPIDR3_MASK 0x000000FFUL /**< Mask for ETM_ETMPIDR3 */ #define _ETM_ETMPIDR3_CUSTMOD_SHIFT 0 /**< Shift value for ETM_CUSTMOD */ #define _ETM_ETMPIDR3_CUSTMOD_MASK 0xFUL /**< Bit mask for ETM_CUSTMOD */ #define _ETM_ETMPIDR3_CUSTMOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMPIDR3 */ #define ETM_ETMPIDR3_CUSTMOD_DEFAULT (_ETM_ETMPIDR3_CUSTMOD_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMPIDR3 */ #define _ETM_ETMPIDR3_REVAND_SHIFT 4 /**< Shift value for ETM_REVAND */ #define _ETM_ETMPIDR3_REVAND_MASK 0xF0UL /**< Bit mask for ETM_REVAND */ #define _ETM_ETMPIDR3_REVAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMPIDR3 */ #define ETM_ETMPIDR3_REVAND_DEFAULT (_ETM_ETMPIDR3_REVAND_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMPIDR3 */ /* Bit fields for ETM ETMCIDR0 */ #define _ETM_ETMCIDR0_RESETVALUE 0x0000000DUL /**< Default value for ETM_ETMCIDR0 */ #define _ETM_ETMCIDR0_MASK 0x000000FFUL /**< Mask for ETM_ETMCIDR0 */ #define _ETM_ETMCIDR0_PREAMB_SHIFT 0 /**< Shift value for ETM_PREAMB */ #define _ETM_ETMCIDR0_PREAMB_MASK 0xFFUL /**< Bit mask for ETM_PREAMB */ #define _ETM_ETMCIDR0_PREAMB_DEFAULT 0x0000000DUL /**< Mode DEFAULT for ETM_ETMCIDR0 */ #define ETM_ETMCIDR0_PREAMB_DEFAULT (_ETM_ETMCIDR0_PREAMB_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCIDR0 */ /* Bit fields for ETM ETMCIDR1 */ #define _ETM_ETMCIDR1_RESETVALUE 0x00000090UL /**< Default value for ETM_ETMCIDR1 */ #define _ETM_ETMCIDR1_MASK 0x000000FFUL /**< Mask for ETM_ETMCIDR1 */ #define _ETM_ETMCIDR1_PREAMB_SHIFT 0 /**< Shift value for ETM_PREAMB */ #define _ETM_ETMCIDR1_PREAMB_MASK 0xFFUL /**< Bit mask for ETM_PREAMB */ #define _ETM_ETMCIDR1_PREAMB_DEFAULT 0x00000090UL /**< Mode DEFAULT for ETM_ETMCIDR1 */ #define ETM_ETMCIDR1_PREAMB_DEFAULT (_ETM_ETMCIDR1_PREAMB_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCIDR1 */ /* Bit fields for ETM ETMCIDR2 */ #define _ETM_ETMCIDR2_RESETVALUE 0x00000005UL /**< Default value for ETM_ETMCIDR2 */ #define _ETM_ETMCIDR2_MASK 0x000000FFUL /**< Mask for ETM_ETMCIDR2 */ #define _ETM_ETMCIDR2_PREAMB_SHIFT 0 /**< Shift value for ETM_PREAMB */ #define _ETM_ETMCIDR2_PREAMB_MASK 0xFFUL /**< Bit mask for ETM_PREAMB */ #define _ETM_ETMCIDR2_PREAMB_DEFAULT 0x00000005UL /**< Mode DEFAULT for ETM_ETMCIDR2 */ #define ETM_ETMCIDR2_PREAMB_DEFAULT (_ETM_ETMCIDR2_PREAMB_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCIDR2 */ /* Bit fields for ETM ETMCIDR3 */ #define _ETM_ETMCIDR3_RESETVALUE 0x000000B1UL /**< Default value for ETM_ETMCIDR3 */ #define _ETM_ETMCIDR3_MASK 0x000000FFUL /**< Mask for ETM_ETMCIDR3 */ #define _ETM_ETMCIDR3_PREAMB_SHIFT 0 /**< Shift value for ETM_PREAMB */ #define _ETM_ETMCIDR3_PREAMB_MASK 0xFFUL /**< Bit mask for ETM_PREAMB */ #define _ETM_ETMCIDR3_PREAMB_DEFAULT 0x000000B1UL /**< Mode DEFAULT for ETM_ETMCIDR3 */ #define ETM_ETMCIDR3_PREAMB_DEFAULT (_ETM_ETMCIDR3_PREAMB_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCIDR3 */ /** @} */ /** @} End of group EFR32MG12P_ETM */ /** @} End of group Parts */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_fpueh.h.
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/***************************************************************************//** * @file * @brief EFR32MG12P_FPUEH register and bit field definitions * @version 5.7.0 ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * SPDX-License-Identifier: Zlib * * The licensor of this software is Silicon Laboratories Inc. * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be * appreciated but is not required. * 2. Altered source versions must be plainly marked as such, and must not be * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * ******************************************************************************/ #if defined(__ICCARM__) #pragma system_include /* Treat file as system include file. */ #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang system_header /* Treat file as system include file. */ #endif /***************************************************************************//** * @addtogroup Parts * @{ ******************************************************************************/ /***************************************************************************//** * @defgroup EFR32MG12P_FPUEH FPUEH * @{ * @brief EFR32MG12P_FPUEH Register Declaration ******************************************************************************/ /** FPUEH Register Declaration */ typedef struct { __IM uint32_t IF; /**< Interrupt Flag Register */ __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ __IOM uint32_t IEN; /**< Interrupt Enable Register */ } FPUEH_TypeDef; /** @} */ /***************************************************************************//** * @addtogroup EFR32MG12P_FPUEH * @{ * @defgroup EFR32MG12P_FPUEH_BitFields FPUEH Bit Fields * @{ ******************************************************************************/ /* Bit fields for FPUEH IF */ #define _FPUEH_IF_RESETVALUE 0x00000000UL /**< Default value for FPUEH_IF */ #define _FPUEH_IF_MASK 0x0000003FUL /**< Mask for FPUEH_IF */ #define FPUEH_IF_FPIOC (0x1UL << 0) /**< FPU invalid operation */ #define _FPUEH_IF_FPIOC_SHIFT 0 /**< Shift value for FPUEH_FPIOC */ #define _FPUEH_IF_FPIOC_MASK 0x1UL /**< Bit mask for FPUEH_FPIOC */ #define _FPUEH_IF_FPIOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IF */ #define FPUEH_IF_FPIOC_DEFAULT (_FPUEH_IF_FPIOC_DEFAULT << 0) /**< Shifted mode DEFAULT for FPUEH_IF */ #define FPUEH_IF_FPDZC (0x1UL << 1) /**< FPU divide-by-zero exception */ #define _FPUEH_IF_FPDZC_SHIFT 1 /**< Shift value for FPUEH_FPDZC */ #define _FPUEH_IF_FPDZC_MASK 0x2UL /**< Bit mask for FPUEH_FPDZC */ #define _FPUEH_IF_FPDZC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IF */ #define FPUEH_IF_FPDZC_DEFAULT (_FPUEH_IF_FPDZC_DEFAULT << 1) /**< Shifted mode DEFAULT for FPUEH_IF */ #define FPUEH_IF_FPUFC (0x1UL << 2) /**< FPU underflow exception */ #define _FPUEH_IF_FPUFC_SHIFT 2 /**< Shift value for FPUEH_FPUFC */ #define _FPUEH_IF_FPUFC_MASK 0x4UL /**< Bit mask for FPUEH_FPUFC */ #define _FPUEH_IF_FPUFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IF */ #define FPUEH_IF_FPUFC_DEFAULT (_FPUEH_IF_FPUFC_DEFAULT << 2) /**< Shifted mode DEFAULT for FPUEH_IF */ #define FPUEH_IF_FPOFC (0x1UL << 3) /**< FPU overflow exception */ #define _FPUEH_IF_FPOFC_SHIFT 3 /**< Shift value for FPUEH_FPOFC */ #define _FPUEH_IF_FPOFC_MASK 0x8UL /**< Bit mask for FPUEH_FPOFC */ #define _FPUEH_IF_FPOFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IF */ #define FPUEH_IF_FPOFC_DEFAULT (_FPUEH_IF_FPOFC_DEFAULT << 3) /**< Shifted mode DEFAULT for FPUEH_IF */ #define FPUEH_IF_FPIDC (0x1UL << 4) /**< FPU input denormal exception */ #define _FPUEH_IF_FPIDC_SHIFT 4 /**< Shift value for FPUEH_FPIDC */ #define _FPUEH_IF_FPIDC_MASK 0x10UL /**< Bit mask for FPUEH_FPIDC */ #define _FPUEH_IF_FPIDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IF */ #define FPUEH_IF_FPIDC_DEFAULT (_FPUEH_IF_FPIDC_DEFAULT << 4) /**< Shifted mode DEFAULT for FPUEH_IF */ #define FPUEH_IF_FPIXC (0x1UL << 5) /**< FPU inexact exception */ #define _FPUEH_IF_FPIXC_SHIFT 5 /**< Shift value for FPUEH_FPIXC */ #define _FPUEH_IF_FPIXC_MASK 0x20UL /**< Bit mask for FPUEH_FPIXC */ #define _FPUEH_IF_FPIXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IF */ #define FPUEH_IF_FPIXC_DEFAULT (_FPUEH_IF_FPIXC_DEFAULT << 5) /**< Shifted mode DEFAULT for FPUEH_IF */ /* Bit fields for FPUEH IFS */ #define _FPUEH_IFS_RESETVALUE 0x00000000UL /**< Default value for FPUEH_IFS */ #define _FPUEH_IFS_MASK 0x0000003FUL /**< Mask for FPUEH_IFS */ #define FPUEH_IFS_FPIOC (0x1UL << 0) /**< Set FPIOC Interrupt Flag */ #define _FPUEH_IFS_FPIOC_SHIFT 0 /**< Shift value for FPUEH_FPIOC */ #define _FPUEH_IFS_FPIOC_MASK 0x1UL /**< Bit mask for FPUEH_FPIOC */ #define _FPUEH_IFS_FPIOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFS */ #define FPUEH_IFS_FPIOC_DEFAULT (_FPUEH_IFS_FPIOC_DEFAULT << 0) /**< Shifted mode DEFAULT for FPUEH_IFS */ #define FPUEH_IFS_FPDZC (0x1UL << 1) /**< Set FPDZC Interrupt Flag */ #define _FPUEH_IFS_FPDZC_SHIFT 1 /**< Shift value for FPUEH_FPDZC */ #define _FPUEH_IFS_FPDZC_MASK 0x2UL /**< Bit mask for FPUEH_FPDZC */ #define _FPUEH_IFS_FPDZC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFS */ #define FPUEH_IFS_FPDZC_DEFAULT (_FPUEH_IFS_FPDZC_DEFAULT << 1) /**< Shifted mode DEFAULT for FPUEH_IFS */ #define FPUEH_IFS_FPUFC (0x1UL << 2) /**< Set FPUFC Interrupt Flag */ #define _FPUEH_IFS_FPUFC_SHIFT 2 /**< Shift value for FPUEH_FPUFC */ #define _FPUEH_IFS_FPUFC_MASK 0x4UL /**< Bit mask for FPUEH_FPUFC */ #define _FPUEH_IFS_FPUFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFS */ #define FPUEH_IFS_FPUFC_DEFAULT (_FPUEH_IFS_FPUFC_DEFAULT << 2) /**< Shifted mode DEFAULT for FPUEH_IFS */ #define FPUEH_IFS_FPOFC (0x1UL << 3) /**< Set FPOFC Interrupt Flag */ #define _FPUEH_IFS_FPOFC_SHIFT 3 /**< Shift value for FPUEH_FPOFC */ #define _FPUEH_IFS_FPOFC_MASK 0x8UL /**< Bit mask for FPUEH_FPOFC */ #define _FPUEH_IFS_FPOFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFS */ #define FPUEH_IFS_FPOFC_DEFAULT (_FPUEH_IFS_FPOFC_DEFAULT << 3) /**< Shifted mode DEFAULT for FPUEH_IFS */ #define FPUEH_IFS_FPIDC (0x1UL << 4) /**< Set FPIDC Interrupt Flag */ #define _FPUEH_IFS_FPIDC_SHIFT 4 /**< Shift value for FPUEH_FPIDC */ #define _FPUEH_IFS_FPIDC_MASK 0x10UL /**< Bit mask for FPUEH_FPIDC */ #define _FPUEH_IFS_FPIDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFS */ #define FPUEH_IFS_FPIDC_DEFAULT (_FPUEH_IFS_FPIDC_DEFAULT << 4) /**< Shifted mode DEFAULT for FPUEH_IFS */ #define FPUEH_IFS_FPIXC (0x1UL << 5) /**< Set FPIXC Interrupt Flag */ #define _FPUEH_IFS_FPIXC_SHIFT 5 /**< Shift value for FPUEH_FPIXC */ #define _FPUEH_IFS_FPIXC_MASK 0x20UL /**< Bit mask for FPUEH_FPIXC */ #define _FPUEH_IFS_FPIXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFS */ #define FPUEH_IFS_FPIXC_DEFAULT (_FPUEH_IFS_FPIXC_DEFAULT << 5) /**< Shifted mode DEFAULT for FPUEH_IFS */ /* Bit fields for FPUEH IFC */ #define _FPUEH_IFC_RESETVALUE 0x00000000UL /**< Default value for FPUEH_IFC */ #define _FPUEH_IFC_MASK 0x0000003FUL /**< Mask for FPUEH_IFC */ #define FPUEH_IFC_FPIOC (0x1UL << 0) /**< Clear FPIOC Interrupt Flag */ #define _FPUEH_IFC_FPIOC_SHIFT 0 /**< Shift value for FPUEH_FPIOC */ #define _FPUEH_IFC_FPIOC_MASK 0x1UL /**< Bit mask for FPUEH_FPIOC */ #define _FPUEH_IFC_FPIOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFC */ #define FPUEH_IFC_FPIOC_DEFAULT (_FPUEH_IFC_FPIOC_DEFAULT << 0) /**< Shifted mode DEFAULT for FPUEH_IFC */ #define FPUEH_IFC_FPDZC (0x1UL << 1) /**< Clear FPDZC Interrupt Flag */ #define _FPUEH_IFC_FPDZC_SHIFT 1 /**< Shift value for FPUEH_FPDZC */ #define _FPUEH_IFC_FPDZC_MASK 0x2UL /**< Bit mask for FPUEH_FPDZC */ #define _FPUEH_IFC_FPDZC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFC */ #define FPUEH_IFC_FPDZC_DEFAULT (_FPUEH_IFC_FPDZC_DEFAULT << 1) /**< Shifted mode DEFAULT for FPUEH_IFC */ #define FPUEH_IFC_FPUFC (0x1UL << 2) /**< Clear FPUFC Interrupt Flag */ #define _FPUEH_IFC_FPUFC_SHIFT 2 /**< Shift value for FPUEH_FPUFC */ #define _FPUEH_IFC_FPUFC_MASK 0x4UL /**< Bit mask for FPUEH_FPUFC */ #define _FPUEH_IFC_FPUFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFC */ #define FPUEH_IFC_FPUFC_DEFAULT (_FPUEH_IFC_FPUFC_DEFAULT << 2) /**< Shifted mode DEFAULT for FPUEH_IFC */ #define FPUEH_IFC_FPOFC (0x1UL << 3) /**< Clear FPOFC Interrupt Flag */ #define _FPUEH_IFC_FPOFC_SHIFT 3 /**< Shift value for FPUEH_FPOFC */ #define _FPUEH_IFC_FPOFC_MASK 0x8UL /**< Bit mask for FPUEH_FPOFC */ #define _FPUEH_IFC_FPOFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFC */ #define FPUEH_IFC_FPOFC_DEFAULT (_FPUEH_IFC_FPOFC_DEFAULT << 3) /**< Shifted mode DEFAULT for FPUEH_IFC */ #define FPUEH_IFC_FPIDC (0x1UL << 4) /**< Clear FPIDC Interrupt Flag */ #define _FPUEH_IFC_FPIDC_SHIFT 4 /**< Shift value for FPUEH_FPIDC */ #define _FPUEH_IFC_FPIDC_MASK 0x10UL /**< Bit mask for FPUEH_FPIDC */ #define _FPUEH_IFC_FPIDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFC */ #define FPUEH_IFC_FPIDC_DEFAULT (_FPUEH_IFC_FPIDC_DEFAULT << 4) /**< Shifted mode DEFAULT for FPUEH_IFC */ #define FPUEH_IFC_FPIXC (0x1UL << 5) /**< Clear FPIXC Interrupt Flag */ #define _FPUEH_IFC_FPIXC_SHIFT 5 /**< Shift value for FPUEH_FPIXC */ #define _FPUEH_IFC_FPIXC_MASK 0x20UL /**< Bit mask for FPUEH_FPIXC */ #define _FPUEH_IFC_FPIXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFC */ #define FPUEH_IFC_FPIXC_DEFAULT (_FPUEH_IFC_FPIXC_DEFAULT << 5) /**< Shifted mode DEFAULT for FPUEH_IFC */ /* Bit fields for FPUEH IEN */ #define _FPUEH_IEN_RESETVALUE 0x00000000UL /**< Default value for FPUEH_IEN */ #define _FPUEH_IEN_MASK 0x0000003FUL /**< Mask for FPUEH_IEN */ #define FPUEH_IEN_FPIOC (0x1UL << 0) /**< FPIOC Interrupt Enable */ #define _FPUEH_IEN_FPIOC_SHIFT 0 /**< Shift value for FPUEH_FPIOC */ #define _FPUEH_IEN_FPIOC_MASK 0x1UL /**< Bit mask for FPUEH_FPIOC */ #define _FPUEH_IEN_FPIOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IEN */ #define FPUEH_IEN_FPIOC_DEFAULT (_FPUEH_IEN_FPIOC_DEFAULT << 0) /**< Shifted mode DEFAULT for FPUEH_IEN */ #define FPUEH_IEN_FPDZC (0x1UL << 1) /**< FPDZC Interrupt Enable */ #define _FPUEH_IEN_FPDZC_SHIFT 1 /**< Shift value for FPUEH_FPDZC */ #define _FPUEH_IEN_FPDZC_MASK 0x2UL /**< Bit mask for FPUEH_FPDZC */ #define _FPUEH_IEN_FPDZC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IEN */ #define FPUEH_IEN_FPDZC_DEFAULT (_FPUEH_IEN_FPDZC_DEFAULT << 1) /**< Shifted mode DEFAULT for FPUEH_IEN */ #define FPUEH_IEN_FPUFC (0x1UL << 2) /**< FPUFC Interrupt Enable */ #define _FPUEH_IEN_FPUFC_SHIFT 2 /**< Shift value for FPUEH_FPUFC */ #define _FPUEH_IEN_FPUFC_MASK 0x4UL /**< Bit mask for FPUEH_FPUFC */ #define _FPUEH_IEN_FPUFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IEN */ #define FPUEH_IEN_FPUFC_DEFAULT (_FPUEH_IEN_FPUFC_DEFAULT << 2) /**< Shifted mode DEFAULT for FPUEH_IEN */ #define FPUEH_IEN_FPOFC (0x1UL << 3) /**< FPOFC Interrupt Enable */ #define _FPUEH_IEN_FPOFC_SHIFT 3 /**< Shift value for FPUEH_FPOFC */ #define _FPUEH_IEN_FPOFC_MASK 0x8UL /**< Bit mask for FPUEH_FPOFC */ #define _FPUEH_IEN_FPOFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IEN */ #define FPUEH_IEN_FPOFC_DEFAULT (_FPUEH_IEN_FPOFC_DEFAULT << 3) /**< Shifted mode DEFAULT for FPUEH_IEN */ #define FPUEH_IEN_FPIDC (0x1UL << 4) /**< FPIDC Interrupt Enable */ #define _FPUEH_IEN_FPIDC_SHIFT 4 /**< Shift value for FPUEH_FPIDC */ #define _FPUEH_IEN_FPIDC_MASK 0x10UL /**< Bit mask for FPUEH_FPIDC */ #define _FPUEH_IEN_FPIDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IEN */ #define FPUEH_IEN_FPIDC_DEFAULT (_FPUEH_IEN_FPIDC_DEFAULT << 4) /**< Shifted mode DEFAULT for FPUEH_IEN */ #define FPUEH_IEN_FPIXC (0x1UL << 5) /**< FPIXC Interrupt Enable */ #define _FPUEH_IEN_FPIXC_SHIFT 5 /**< Shift value for FPUEH_FPIXC */ #define _FPUEH_IEN_FPIXC_MASK 0x20UL /**< Bit mask for FPUEH_FPIXC */ #define _FPUEH_IEN_FPIXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IEN */ #define FPUEH_IEN_FPIXC_DEFAULT (_FPUEH_IEN_FPIXC_DEFAULT << 5) /**< Shifted mode DEFAULT for FPUEH_IEN */ /** @} */ /** @} End of group EFR32MG12P_FPUEH */ /** @} End of group Parts */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_gpcrc.h.
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/***************************************************************************//** * @file * @brief EFR32MG12P_GPCRC register and bit field definitions * @version 5.7.0 ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * SPDX-License-Identifier: Zlib * * The licensor of this software is Silicon Laboratories Inc. * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be * appreciated but is not required. * 2. Altered source versions must be plainly marked as such, and must not be * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * ******************************************************************************/ #if defined(__ICCARM__) #pragma system_include /* Treat file as system include file. */ #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang system_header /* Treat file as system include file. */ #endif /***************************************************************************//** * @addtogroup Parts * @{ ******************************************************************************/ /***************************************************************************//** * @defgroup EFR32MG12P_GPCRC GPCRC * @{ * @brief EFR32MG12P_GPCRC Register Declaration ******************************************************************************/ /** GPCRC Register Declaration */ typedef struct { __IOM uint32_t CTRL; /**< Control Register */ __IOM uint32_t CMD; /**< Command Register */ __IOM uint32_t INIT; /**< CRC Init Value */ __IOM uint32_t POLY; /**< CRC Polynomial Value */ __IOM uint32_t INPUTDATA; /**< Input 32-bit Data Register */ __IOM uint32_t INPUTDATAHWORD; /**< Input 16-bit Data Register */ __IOM uint32_t INPUTDATABYTE; /**< Input 8-bit Data Register */ __IM uint32_t DATA; /**< CRC Data Register */ __IM uint32_t DATAREV; /**< CRC Data Reverse Register */ __IM uint32_t DATABYTEREV; /**< CRC Data Byte Reverse Register */ } GPCRC_TypeDef; /** @} */ /***************************************************************************//** * @addtogroup EFR32MG12P_GPCRC * @{ * @defgroup EFR32MG12P_GPCRC_BitFields GPCRC Bit Fields * @{ ******************************************************************************/ /* Bit fields for GPCRC CTRL */ #define _GPCRC_CTRL_RESETVALUE 0x00000000UL /**< Default value for GPCRC_CTRL */ #define _GPCRC_CTRL_MASK 0x00002711UL /**< Mask for GPCRC_CTRL */ #define GPCRC_CTRL_EN (0x1UL << 0) /**< CRC Functionality Enable */ #define _GPCRC_CTRL_EN_SHIFT 0 /**< Shift value for GPCRC_EN */ #define _GPCRC_CTRL_EN_MASK 0x1UL /**< Bit mask for GPCRC_EN */ #define _GPCRC_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */ #define _GPCRC_CTRL_EN_DISABLE 0x00000000UL /**< Mode DISABLE for GPCRC_CTRL */ #define _GPCRC_CTRL_EN_ENABLE 0x00000001UL /**< Mode ENABLE for GPCRC_CTRL */ #define GPCRC_CTRL_EN_DEFAULT (_GPCRC_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_CTRL */ #define GPCRC_CTRL_EN_DISABLE (_GPCRC_CTRL_EN_DISABLE << 0) /**< Shifted mode DISABLE for GPCRC_CTRL */ #define GPCRC_CTRL_EN_ENABLE (_GPCRC_CTRL_EN_ENABLE << 0) /**< Shifted mode ENABLE for GPCRC_CTRL */ #define GPCRC_CTRL_POLYSEL (0x1UL << 4) /**< Polynomial Select */ #define _GPCRC_CTRL_POLYSEL_SHIFT 4 /**< Shift value for GPCRC_POLYSEL */ #define _GPCRC_CTRL_POLYSEL_MASK 0x10UL /**< Bit mask for GPCRC_POLYSEL */ #define _GPCRC_CTRL_POLYSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */ #define _GPCRC_CTRL_POLYSEL_CRC32 0x00000000UL /**< Mode CRC32 for GPCRC_CTRL */ #define _GPCRC_CTRL_POLYSEL_16 0x00000001UL /**< Mode 16 for GPCRC_CTRL */ #define GPCRC_CTRL_POLYSEL_DEFAULT (_GPCRC_CTRL_POLYSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for GPCRC_CTRL */ #define GPCRC_CTRL_POLYSEL_CRC32 (_GPCRC_CTRL_POLYSEL_CRC32 << 4) /**< Shifted mode CRC32 for GPCRC_CTRL */ #define GPCRC_CTRL_POLYSEL_16 (_GPCRC_CTRL_POLYSEL_16 << 4) /**< Shifted mode 16 for GPCRC_CTRL */ #define GPCRC_CTRL_BYTEMODE (0x1UL << 8) /**< Byte Mode Enable */ #define _GPCRC_CTRL_BYTEMODE_SHIFT 8 /**< Shift value for GPCRC_BYTEMODE */ #define _GPCRC_CTRL_BYTEMODE_MASK 0x100UL /**< Bit mask for GPCRC_BYTEMODE */ #define _GPCRC_CTRL_BYTEMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */ #define GPCRC_CTRL_BYTEMODE_DEFAULT (_GPCRC_CTRL_BYTEMODE_DEFAULT << 8) /**< Shifted mode DEFAULT for GPCRC_CTRL */ #define GPCRC_CTRL_BITREVERSE (0x1UL << 9) /**< Byte-level Bit Reverse Enable */ #define _GPCRC_CTRL_BITREVERSE_SHIFT 9 /**< Shift value for GPCRC_BITREVERSE */ #define _GPCRC_CTRL_BITREVERSE_MASK 0x200UL /**< Bit mask for GPCRC_BITREVERSE */ #define _GPCRC_CTRL_BITREVERSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */ #define _GPCRC_CTRL_BITREVERSE_NORMAL 0x00000000UL /**< Mode NORMAL for GPCRC_CTRL */ #define _GPCRC_CTRL_BITREVERSE_REVERSED 0x00000001UL /**< Mode REVERSED for GPCRC_CTRL */ #define GPCRC_CTRL_BITREVERSE_DEFAULT (_GPCRC_CTRL_BITREVERSE_DEFAULT << 9) /**< Shifted mode DEFAULT for GPCRC_CTRL */ #define GPCRC_CTRL_BITREVERSE_NORMAL (_GPCRC_CTRL_BITREVERSE_NORMAL << 9) /**< Shifted mode NORMAL for GPCRC_CTRL */ #define GPCRC_CTRL_BITREVERSE_REVERSED (_GPCRC_CTRL_BITREVERSE_REVERSED << 9) /**< Shifted mode REVERSED for GPCRC_CTRL */ #define GPCRC_CTRL_BYTEREVERSE (0x1UL << 10) /**< Byte Reverse Mode */ #define _GPCRC_CTRL_BYTEREVERSE_SHIFT 10 /**< Shift value for GPCRC_BYTEREVERSE */ #define _GPCRC_CTRL_BYTEREVERSE_MASK 0x400UL /**< Bit mask for GPCRC_BYTEREVERSE */ #define _GPCRC_CTRL_BYTEREVERSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */ #define _GPCRC_CTRL_BYTEREVERSE_NORMAL 0x00000000UL /**< Mode NORMAL for GPCRC_CTRL */ #define _GPCRC_CTRL_BYTEREVERSE_REVERSED 0x00000001UL /**< Mode REVERSED for GPCRC_CTRL */ #define GPCRC_CTRL_BYTEREVERSE_DEFAULT (_GPCRC_CTRL_BYTEREVERSE_DEFAULT << 10) /**< Shifted mode DEFAULT for GPCRC_CTRL */ #define GPCRC_CTRL_BYTEREVERSE_NORMAL (_GPCRC_CTRL_BYTEREVERSE_NORMAL << 10) /**< Shifted mode NORMAL for GPCRC_CTRL */ #define GPCRC_CTRL_BYTEREVERSE_REVERSED (_GPCRC_CTRL_BYTEREVERSE_REVERSED << 10) /**< Shifted mode REVERSED for GPCRC_CTRL */ #define GPCRC_CTRL_AUTOINIT (0x1UL << 13) /**< Auto Init Enable */ #define _GPCRC_CTRL_AUTOINIT_SHIFT 13 /**< Shift value for GPCRC_AUTOINIT */ #define _GPCRC_CTRL_AUTOINIT_MASK 0x2000UL /**< Bit mask for GPCRC_AUTOINIT */ #define _GPCRC_CTRL_AUTOINIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */ #define GPCRC_CTRL_AUTOINIT_DEFAULT (_GPCRC_CTRL_AUTOINIT_DEFAULT << 13) /**< Shifted mode DEFAULT for GPCRC_CTRL */ /* Bit fields for GPCRC CMD */ #define _GPCRC_CMD_RESETVALUE 0x00000000UL /**< Default value for GPCRC_CMD */ #define _GPCRC_CMD_MASK 0x00000001UL /**< Mask for GPCRC_CMD */ #define GPCRC_CMD_INIT (0x1UL << 0) /**< Initialization Enable */ #define _GPCRC_CMD_INIT_SHIFT 0 /**< Shift value for GPCRC_INIT */ #define _GPCRC_CMD_INIT_MASK 0x1UL /**< Bit mask for GPCRC_INIT */ #define _GPCRC_CMD_INIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CMD */ #define GPCRC_CMD_INIT_DEFAULT (_GPCRC_CMD_INIT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_CMD */ /* Bit fields for GPCRC INIT */ #define _GPCRC_INIT_RESETVALUE 0x00000000UL /**< Default value for GPCRC_INIT */ #define _GPCRC_INIT_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_INIT */ #define _GPCRC_INIT_INIT_SHIFT 0 /**< Shift value for GPCRC_INIT */ #define _GPCRC_INIT_INIT_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_INIT */ #define _GPCRC_INIT_INIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_INIT */ #define GPCRC_INIT_INIT_DEFAULT (_GPCRC_INIT_INIT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INIT */ /* Bit fields for GPCRC POLY */ #define _GPCRC_POLY_RESETVALUE 0x00000000UL /**< Default value for GPCRC_POLY */ #define _GPCRC_POLY_MASK 0x0000FFFFUL /**< Mask for GPCRC_POLY */ #define _GPCRC_POLY_POLY_SHIFT 0 /**< Shift value for GPCRC_POLY */ #define _GPCRC_POLY_POLY_MASK 0xFFFFUL /**< Bit mask for GPCRC_POLY */ #define _GPCRC_POLY_POLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_POLY */ #define GPCRC_POLY_POLY_DEFAULT (_GPCRC_POLY_POLY_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_POLY */ /* Bit fields for GPCRC INPUTDATA */ #define _GPCRC_INPUTDATA_RESETVALUE 0x00000000UL /**< Default value for GPCRC_INPUTDATA */ #define _GPCRC_INPUTDATA_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_INPUTDATA */ #define _GPCRC_INPUTDATA_INPUTDATA_SHIFT 0 /**< Shift value for GPCRC_INPUTDATA */ #define _GPCRC_INPUTDATA_INPUTDATA_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_INPUTDATA */ #define _GPCRC_INPUTDATA_INPUTDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_INPUTDATA */ #define GPCRC_INPUTDATA_INPUTDATA_DEFAULT (_GPCRC_INPUTDATA_INPUTDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INPUTDATA */ /* Bit fields for GPCRC INPUTDATAHWORD */ #define _GPCRC_INPUTDATAHWORD_RESETVALUE 0x00000000UL /**< Default value for GPCRC_INPUTDATAHWORD */ #define _GPCRC_INPUTDATAHWORD_MASK 0x0000FFFFUL /**< Mask for GPCRC_INPUTDATAHWORD */ #define _GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_SHIFT 0 /**< Shift value for GPCRC_INPUTDATAHWORD */ #define _GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_MASK 0xFFFFUL /**< Bit mask for GPCRC_INPUTDATAHWORD */ #define _GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_INPUTDATAHWORD */ #define GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_DEFAULT (_GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INPUTDATAHWORD */ /* Bit fields for GPCRC INPUTDATABYTE */ #define _GPCRC_INPUTDATABYTE_RESETVALUE 0x00000000UL /**< Default value for GPCRC_INPUTDATABYTE */ #define _GPCRC_INPUTDATABYTE_MASK 0x000000FFUL /**< Mask for GPCRC_INPUTDATABYTE */ #define _GPCRC_INPUTDATABYTE_INPUTDATABYTE_SHIFT 0 /**< Shift value for GPCRC_INPUTDATABYTE */ #define _GPCRC_INPUTDATABYTE_INPUTDATABYTE_MASK 0xFFUL /**< Bit mask for GPCRC_INPUTDATABYTE */ #define _GPCRC_INPUTDATABYTE_INPUTDATABYTE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_INPUTDATABYTE */ #define GPCRC_INPUTDATABYTE_INPUTDATABYTE_DEFAULT (_GPCRC_INPUTDATABYTE_INPUTDATABYTE_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INPUTDATABYTE */ /* Bit fields for GPCRC DATA */ #define _GPCRC_DATA_RESETVALUE 0x00000000UL /**< Default value for GPCRC_DATA */ #define _GPCRC_DATA_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_DATA */ #define _GPCRC_DATA_DATA_SHIFT 0 /**< Shift value for GPCRC_DATA */ #define _GPCRC_DATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_DATA */ #define _GPCRC_DATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_DATA */ #define GPCRC_DATA_DATA_DEFAULT (_GPCRC_DATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_DATA */ /* Bit fields for GPCRC DATAREV */ #define _GPCRC_DATAREV_RESETVALUE 0x00000000UL /**< Default value for GPCRC_DATAREV */ #define _GPCRC_DATAREV_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_DATAREV */ #define _GPCRC_DATAREV_DATAREV_SHIFT 0 /**< Shift value for GPCRC_DATAREV */ #define _GPCRC_DATAREV_DATAREV_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_DATAREV */ #define _GPCRC_DATAREV_DATAREV_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_DATAREV */ #define GPCRC_DATAREV_DATAREV_DEFAULT (_GPCRC_DATAREV_DATAREV_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_DATAREV */ /* Bit fields for GPCRC DATABYTEREV */ #define _GPCRC_DATABYTEREV_RESETVALUE 0x00000000UL /**< Default value for GPCRC_DATABYTEREV */ #define _GPCRC_DATABYTEREV_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_DATABYTEREV */ #define _GPCRC_DATABYTEREV_DATABYTEREV_SHIFT 0 /**< Shift value for GPCRC_DATABYTEREV */ #define _GPCRC_DATABYTEREV_DATABYTEREV_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_DATABYTEREV */ #define _GPCRC_DATABYTEREV_DATABYTEREV_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_DATABYTEREV */ #define GPCRC_DATABYTEREV_DATABYTEREV_DEFAULT (_GPCRC_DATABYTEREV_DATABYTEREV_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_DATABYTEREV */ /** @} */ /** @} End of group EFR32MG12P_GPCRC */ /** @} End of group Parts */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_gpio.h.
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/***************************************************************************//** * @file * @brief EFR32MG12P_GPIO register and bit field definitions * @version 5.7.0 ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * SPDX-License-Identifier: Zlib * * The licensor of this software is Silicon Laboratories Inc. * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be * appreciated but is not required. * 2. Altered source versions must be plainly marked as such, and must not be * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * ******************************************************************************/ #if defined(__ICCARM__) #pragma system_include /* Treat file as system include file. */ #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang system_header /* Treat file as system include file. */ #endif /***************************************************************************//** * @addtogroup Parts * @{ ******************************************************************************/ /***************************************************************************//** * @defgroup EFR32MG12P_GPIO GPIO * @{ * @brief EFR32MG12P_GPIO Register Declaration ******************************************************************************/ /** GPIO Register Declaration */ typedef struct { GPIO_P_TypeDef P[12U]; /**< Port configuration bits */ uint32_t RESERVED0[112U]; /**< Reserved for future use **/ __IOM uint32_t EXTIPSELL; /**< External Interrupt Port Select Low Register */ __IOM uint32_t EXTIPSELH; /**< External Interrupt Port Select High Register */ __IOM uint32_t EXTIPINSELL; /**< External Interrupt Pin Select Low Register */ __IOM uint32_t EXTIPINSELH; /**< External Interrupt Pin Select High Register */ __IOM uint32_t EXTIRISE; /**< External Interrupt Rising Edge Trigger Register */ __IOM uint32_t EXTIFALL; /**< External Interrupt Falling Edge Trigger Register */ __IOM uint32_t EXTILEVEL; /**< External Interrupt Level Register */ __IM uint32_t IF; /**< Interrupt Flag Register */ __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ __IOM uint32_t IEN; /**< Interrupt Enable Register */ __IOM uint32_t EM4WUEN; /**< EM4 Wake Up Enable Register */ uint32_t RESERVED1[4U]; /**< Reserved for future use **/ __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ __IOM uint32_t ROUTELOC1; /**< I/O Routing Location Register 1 */ uint32_t RESERVED2[1U]; /**< Reserved for future use **/ __IOM uint32_t INSENSE; /**< Input Sense Register */ __IOM uint32_t LOCK; /**< Configuration Lock Register */ } GPIO_TypeDef; /** @} */ /***************************************************************************//** * @addtogroup EFR32MG12P_GPIO * @{ * @defgroup EFR32MG12P_GPIO_BitFields GPIO Bit Fields * @{ ******************************************************************************/ /* Bit fields for GPIO P_CTRL */ #define _GPIO_P_CTRL_RESETVALUE 0x00500050UL /**< Default value for GPIO_P_CTRL */ #define _GPIO_P_CTRL_MASK 0x10711071UL /**< Mask for GPIO_P_CTRL */ #define GPIO_P_CTRL_DRIVESTRENGTH (0x1UL << 0) /**< Drive Strength for Port */ #define _GPIO_P_CTRL_DRIVESTRENGTH_SHIFT 0 /**< Shift value for GPIO_DRIVESTRENGTH */ #define _GPIO_P_CTRL_DRIVESTRENGTH_MASK 0x1UL /**< Bit mask for GPIO_DRIVESTRENGTH */ #define _GPIO_P_CTRL_DRIVESTRENGTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_CTRL */ #define _GPIO_P_CTRL_DRIVESTRENGTH_STRONG 0x00000000UL /**< Mode STRONG for GPIO_P_CTRL */ #define _GPIO_P_CTRL_DRIVESTRENGTH_WEAK 0x00000001UL /**< Mode WEAK for GPIO_P_CTRL */ #define GPIO_P_CTRL_DRIVESTRENGTH_DEFAULT (_GPIO_P_CTRL_DRIVESTRENGTH_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_CTRL */ #define GPIO_P_CTRL_DRIVESTRENGTH_STRONG (_GPIO_P_CTRL_DRIVESTRENGTH_STRONG << 0) /**< Shifted mode STRONG for GPIO_P_CTRL */ #define GPIO_P_CTRL_DRIVESTRENGTH_WEAK (_GPIO_P_CTRL_DRIVESTRENGTH_WEAK << 0) /**< Shifted mode WEAK for GPIO_P_CTRL */ #define _GPIO_P_CTRL_SLEWRATE_SHIFT 4 /**< Shift value for GPIO_SLEWRATE */ #define _GPIO_P_CTRL_SLEWRATE_MASK 0x70UL /**< Bit mask for GPIO_SLEWRATE */ #define _GPIO_P_CTRL_SLEWRATE_DEFAULT 0x00000005UL /**< Mode DEFAULT for GPIO_P_CTRL */ #define GPIO_P_CTRL_SLEWRATE_DEFAULT (_GPIO_P_CTRL_SLEWRATE_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_P_CTRL */ #define GPIO_P_CTRL_DINDIS (0x1UL << 12) /**< Data in Disable */ #define _GPIO_P_CTRL_DINDIS_SHIFT 12 /**< Shift value for GPIO_DINDIS */ #define _GPIO_P_CTRL_DINDIS_MASK 0x1000UL /**< Bit mask for GPIO_DINDIS */ #define _GPIO_P_CTRL_DINDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_CTRL */ #define GPIO_P_CTRL_DINDIS_DEFAULT (_GPIO_P_CTRL_DINDIS_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_P_CTRL */ #define GPIO_P_CTRL_DRIVESTRENGTHALT (0x1UL << 16) /**< Alternate Drive Strength for Port */ #define _GPIO_P_CTRL_DRIVESTRENGTHALT_SHIFT 16 /**< Shift value for GPIO_DRIVESTRENGTHALT */ #define _GPIO_P_CTRL_DRIVESTRENGTHALT_MASK 0x10000UL /**< Bit mask for GPIO_DRIVESTRENGTHALT */ #define _GPIO_P_CTRL_DRIVESTRENGTHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_CTRL */ #define _GPIO_P_CTRL_DRIVESTRENGTHALT_STRONG 0x00000000UL /**< Mode STRONG for GPIO_P_CTRL */ #define _GPIO_P_CTRL_DRIVESTRENGTHALT_WEAK 0x00000001UL /**< Mode WEAK for GPIO_P_CTRL */ #define GPIO_P_CTRL_DRIVESTRENGTHALT_DEFAULT (_GPIO_P_CTRL_DRIVESTRENGTHALT_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_P_CTRL */ #define GPIO_P_CTRL_DRIVESTRENGTHALT_STRONG (_GPIO_P_CTRL_DRIVESTRENGTHALT_STRONG << 16) /**< Shifted mode STRONG for GPIO_P_CTRL */ #define GPIO_P_CTRL_DRIVESTRENGTHALT_WEAK (_GPIO_P_CTRL_DRIVESTRENGTHALT_WEAK << 16) /**< Shifted mode WEAK for GPIO_P_CTRL */ #define _GPIO_P_CTRL_SLEWRATEALT_SHIFT 20 /**< Shift value for GPIO_SLEWRATEALT */ #define _GPIO_P_CTRL_SLEWRATEALT_MASK 0x700000UL /**< Bit mask for GPIO_SLEWRATEALT */ #define _GPIO_P_CTRL_SLEWRATEALT_DEFAULT 0x00000005UL /**< Mode DEFAULT for GPIO_P_CTRL */ #define GPIO_P_CTRL_SLEWRATEALT_DEFAULT (_GPIO_P_CTRL_SLEWRATEALT_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_P_CTRL */ #define GPIO_P_CTRL_DINDISALT (0x1UL << 28) /**< Alternate Data in Disable */ #define _GPIO_P_CTRL_DINDISALT_SHIFT 28 /**< Shift value for GPIO_DINDISALT */ #define _GPIO_P_CTRL_DINDISALT_MASK 0x10000000UL /**< Bit mask for GPIO_DINDISALT */ #define _GPIO_P_CTRL_DINDISALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_CTRL */ #define GPIO_P_CTRL_DINDISALT_DEFAULT (_GPIO_P_CTRL_DINDISALT_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_P_CTRL */ /* Bit fields for GPIO P_MODEL */ #define _GPIO_P_MODEL_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MASK 0xFFFFFFFFUL /**< Mask for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE0_SHIFT 0 /**< Shift value for GPIO_MODE0 */ #define _GPIO_P_MODEL_MODE0_MASK 0xFUL /**< Bit mask for GPIO_MODE0 */ #define _GPIO_P_MODEL_MODE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE0_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE0_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE0_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE0_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE0_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE0_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE0_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE0_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE0_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE0_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE0_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE0_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE0_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE0_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE0_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE0_DEFAULT (_GPIO_P_MODEL_MODE0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE0_DISABLED (_GPIO_P_MODEL_MODE0_DISABLED << 0) /**< Shifted mode DISABLED for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE0_INPUT (_GPIO_P_MODEL_MODE0_INPUT << 0) /**< Shifted mode INPUT for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE0_INPUTPULL (_GPIO_P_MODEL_MODE0_INPUTPULL << 0) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE0_INPUTPULLFILTER (_GPIO_P_MODEL_MODE0_INPUTPULLFILTER << 0) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE0_PUSHPULL (_GPIO_P_MODEL_MODE0_PUSHPULL << 0) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE0_PUSHPULLALT (_GPIO_P_MODEL_MODE0_PUSHPULLALT << 0) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE0_WIREDOR (_GPIO_P_MODEL_MODE0_WIREDOR << 0) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE0_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE0_WIREDORPULLDOWN << 0) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE0_WIREDAND (_GPIO_P_MODEL_MODE0_WIREDAND << 0) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE0_WIREDANDFILTER (_GPIO_P_MODEL_MODE0_WIREDANDFILTER << 0) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE0_WIREDANDPULLUP (_GPIO_P_MODEL_MODE0_WIREDANDPULLUP << 0) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER << 0) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE0_WIREDANDALT (_GPIO_P_MODEL_MODE0_WIREDANDALT << 0) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE0_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE0_WIREDANDALTFILTER << 0) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE0_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE0_WIREDANDALTPULLUP << 0) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE0_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE0_WIREDANDALTPULLUPFILTER << 0) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE1_SHIFT 4 /**< Shift value for GPIO_MODE1 */ #define _GPIO_P_MODEL_MODE1_MASK 0xF0UL /**< Bit mask for GPIO_MODE1 */ #define _GPIO_P_MODEL_MODE1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE1_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE1_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE1_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE1_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE1_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE1_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE1_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE1_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE1_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE1_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE1_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE1_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE1_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE1_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE1_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE1_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE1_DEFAULT (_GPIO_P_MODEL_MODE1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE1_DISABLED (_GPIO_P_MODEL_MODE1_DISABLED << 4) /**< Shifted mode DISABLED for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE1_INPUT (_GPIO_P_MODEL_MODE1_INPUT << 4) /**< Shifted mode INPUT for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE1_INPUTPULL (_GPIO_P_MODEL_MODE1_INPUTPULL << 4) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE1_INPUTPULLFILTER (_GPIO_P_MODEL_MODE1_INPUTPULLFILTER << 4) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE1_PUSHPULL (_GPIO_P_MODEL_MODE1_PUSHPULL << 4) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE1_PUSHPULLALT (_GPIO_P_MODEL_MODE1_PUSHPULLALT << 4) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE1_WIREDOR (_GPIO_P_MODEL_MODE1_WIREDOR << 4) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE1_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE1_WIREDORPULLDOWN << 4) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE1_WIREDAND (_GPIO_P_MODEL_MODE1_WIREDAND << 4) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE1_WIREDANDFILTER (_GPIO_P_MODEL_MODE1_WIREDANDFILTER << 4) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE1_WIREDANDPULLUP (_GPIO_P_MODEL_MODE1_WIREDANDPULLUP << 4) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE1_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE1_WIREDANDPULLUPFILTER << 4) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE1_WIREDANDALT (_GPIO_P_MODEL_MODE1_WIREDANDALT << 4) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE1_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE1_WIREDANDALTFILTER << 4) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE1_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE1_WIREDANDALTPULLUP << 4) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE1_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE1_WIREDANDALTPULLUPFILTER << 4) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE2_SHIFT 8 /**< Shift value for GPIO_MODE2 */ #define _GPIO_P_MODEL_MODE2_MASK 0xF00UL /**< Bit mask for GPIO_MODE2 */ #define _GPIO_P_MODEL_MODE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE2_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE2_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE2_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE2_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE2_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE2_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE2_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE2_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE2_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE2_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE2_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE2_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE2_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE2_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE2_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE2_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE2_DEFAULT (_GPIO_P_MODEL_MODE2_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE2_DISABLED (_GPIO_P_MODEL_MODE2_DISABLED << 8) /**< Shifted mode DISABLED for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE2_INPUT (_GPIO_P_MODEL_MODE2_INPUT << 8) /**< Shifted mode INPUT for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE2_INPUTPULL (_GPIO_P_MODEL_MODE2_INPUTPULL << 8) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE2_INPUTPULLFILTER (_GPIO_P_MODEL_MODE2_INPUTPULLFILTER << 8) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE2_PUSHPULL (_GPIO_P_MODEL_MODE2_PUSHPULL << 8) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE2_PUSHPULLALT (_GPIO_P_MODEL_MODE2_PUSHPULLALT << 8) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE2_WIREDOR (_GPIO_P_MODEL_MODE2_WIREDOR << 8) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE2_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE2_WIREDORPULLDOWN << 8) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE2_WIREDAND (_GPIO_P_MODEL_MODE2_WIREDAND << 8) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE2_WIREDANDFILTER (_GPIO_P_MODEL_MODE2_WIREDANDFILTER << 8) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE2_WIREDANDPULLUP (_GPIO_P_MODEL_MODE2_WIREDANDPULLUP << 8) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE2_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE2_WIREDANDPULLUPFILTER << 8) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE2_WIREDANDALT (_GPIO_P_MODEL_MODE2_WIREDANDALT << 8) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE2_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE2_WIREDANDALTFILTER << 8) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE2_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE2_WIREDANDALTPULLUP << 8) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE2_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE2_WIREDANDALTPULLUPFILTER << 8) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE3_SHIFT 12 /**< Shift value for GPIO_MODE3 */ #define _GPIO_P_MODEL_MODE3_MASK 0xF000UL /**< Bit mask for GPIO_MODE3 */ #define _GPIO_P_MODEL_MODE3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE3_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE3_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE3_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE3_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE3_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE3_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE3_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE3_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE3_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE3_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE3_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE3_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE3_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE3_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE3_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE3_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE3_DEFAULT (_GPIO_P_MODEL_MODE3_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE3_DISABLED (_GPIO_P_MODEL_MODE3_DISABLED << 12) /**< Shifted mode DISABLED for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE3_INPUT (_GPIO_P_MODEL_MODE3_INPUT << 12) /**< Shifted mode INPUT for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE3_INPUTPULL (_GPIO_P_MODEL_MODE3_INPUTPULL << 12) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE3_INPUTPULLFILTER (_GPIO_P_MODEL_MODE3_INPUTPULLFILTER << 12) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE3_PUSHPULL (_GPIO_P_MODEL_MODE3_PUSHPULL << 12) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE3_PUSHPULLALT (_GPIO_P_MODEL_MODE3_PUSHPULLALT << 12) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE3_WIREDOR (_GPIO_P_MODEL_MODE3_WIREDOR << 12) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE3_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE3_WIREDORPULLDOWN << 12) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE3_WIREDAND (_GPIO_P_MODEL_MODE3_WIREDAND << 12) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE3_WIREDANDFILTER (_GPIO_P_MODEL_MODE3_WIREDANDFILTER << 12) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE3_WIREDANDPULLUP (_GPIO_P_MODEL_MODE3_WIREDANDPULLUP << 12) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE3_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE3_WIREDANDPULLUPFILTER << 12) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE3_WIREDANDALT (_GPIO_P_MODEL_MODE3_WIREDANDALT << 12) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE3_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE3_WIREDANDALTFILTER << 12) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE3_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE3_WIREDANDALTPULLUP << 12) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE3_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE3_WIREDANDALTPULLUPFILTER << 12) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE4_SHIFT 16 /**< Shift value for GPIO_MODE4 */ #define _GPIO_P_MODEL_MODE4_MASK 0xF0000UL /**< Bit mask for GPIO_MODE4 */ #define _GPIO_P_MODEL_MODE4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE4_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE4_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE4_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE4_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE4_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE4_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE4_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE4_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE4_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE4_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE4_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE4_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE4_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE4_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE4_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE4_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE4_DEFAULT (_GPIO_P_MODEL_MODE4_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE4_DISABLED (_GPIO_P_MODEL_MODE4_DISABLED << 16) /**< Shifted mode DISABLED for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE4_INPUT (_GPIO_P_MODEL_MODE4_INPUT << 16) /**< Shifted mode INPUT for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE4_INPUTPULL (_GPIO_P_MODEL_MODE4_INPUTPULL << 16) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE4_INPUTPULLFILTER (_GPIO_P_MODEL_MODE4_INPUTPULLFILTER << 16) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE4_PUSHPULL (_GPIO_P_MODEL_MODE4_PUSHPULL << 16) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE4_PUSHPULLALT (_GPIO_P_MODEL_MODE4_PUSHPULLALT << 16) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE4_WIREDOR (_GPIO_P_MODEL_MODE4_WIREDOR << 16) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE4_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE4_WIREDORPULLDOWN << 16) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE4_WIREDAND (_GPIO_P_MODEL_MODE4_WIREDAND << 16) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE4_WIREDANDFILTER (_GPIO_P_MODEL_MODE4_WIREDANDFILTER << 16) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE4_WIREDANDPULLUP (_GPIO_P_MODEL_MODE4_WIREDANDPULLUP << 16) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE4_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE4_WIREDANDPULLUPFILTER << 16) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE4_WIREDANDALT (_GPIO_P_MODEL_MODE4_WIREDANDALT << 16) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE4_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE4_WIREDANDALTFILTER << 16) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE4_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE4_WIREDANDALTPULLUP << 16) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE4_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE4_WIREDANDALTPULLUPFILTER << 16) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE5_SHIFT 20 /**< Shift value for GPIO_MODE5 */ #define _GPIO_P_MODEL_MODE5_MASK 0xF00000UL /**< Bit mask for GPIO_MODE5 */ #define _GPIO_P_MODEL_MODE5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE5_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE5_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE5_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE5_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE5_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE5_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE5_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE5_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE5_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE5_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE5_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE5_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE5_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE5_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE5_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE5_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE5_DEFAULT (_GPIO_P_MODEL_MODE5_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE5_DISABLED (_GPIO_P_MODEL_MODE5_DISABLED << 20) /**< Shifted mode DISABLED for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE5_INPUT (_GPIO_P_MODEL_MODE5_INPUT << 20) /**< Shifted mode INPUT for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE5_INPUTPULL (_GPIO_P_MODEL_MODE5_INPUTPULL << 20) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE5_INPUTPULLFILTER (_GPIO_P_MODEL_MODE5_INPUTPULLFILTER << 20) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE5_PUSHPULL (_GPIO_P_MODEL_MODE5_PUSHPULL << 20) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE5_PUSHPULLALT (_GPIO_P_MODEL_MODE5_PUSHPULLALT << 20) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE5_WIREDOR (_GPIO_P_MODEL_MODE5_WIREDOR << 20) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE5_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE5_WIREDORPULLDOWN << 20) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE5_WIREDAND (_GPIO_P_MODEL_MODE5_WIREDAND << 20) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE5_WIREDANDFILTER (_GPIO_P_MODEL_MODE5_WIREDANDFILTER << 20) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE5_WIREDANDPULLUP (_GPIO_P_MODEL_MODE5_WIREDANDPULLUP << 20) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE5_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE5_WIREDANDPULLUPFILTER << 20) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE5_WIREDANDALT (_GPIO_P_MODEL_MODE5_WIREDANDALT << 20) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE5_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE5_WIREDANDALTFILTER << 20) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE5_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE5_WIREDANDALTPULLUP << 20) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE5_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE5_WIREDANDALTPULLUPFILTER << 20) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE6_SHIFT 24 /**< Shift value for GPIO_MODE6 */ #define _GPIO_P_MODEL_MODE6_MASK 0xF000000UL /**< Bit mask for GPIO_MODE6 */ #define _GPIO_P_MODEL_MODE6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE6_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE6_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE6_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE6_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE6_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE6_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE6_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE6_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE6_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE6_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE6_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE6_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE6_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE6_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE6_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE6_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE6_DEFAULT (_GPIO_P_MODEL_MODE6_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE6_DISABLED (_GPIO_P_MODEL_MODE6_DISABLED << 24) /**< Shifted mode DISABLED for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE6_INPUT (_GPIO_P_MODEL_MODE6_INPUT << 24) /**< Shifted mode INPUT for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE6_INPUTPULL (_GPIO_P_MODEL_MODE6_INPUTPULL << 24) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE6_INPUTPULLFILTER (_GPIO_P_MODEL_MODE6_INPUTPULLFILTER << 24) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE6_PUSHPULL (_GPIO_P_MODEL_MODE6_PUSHPULL << 24) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE6_PUSHPULLALT (_GPIO_P_MODEL_MODE6_PUSHPULLALT << 24) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE6_WIREDOR (_GPIO_P_MODEL_MODE6_WIREDOR << 24) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE6_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE6_WIREDORPULLDOWN << 24) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE6_WIREDAND (_GPIO_P_MODEL_MODE6_WIREDAND << 24) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE6_WIREDANDFILTER (_GPIO_P_MODEL_MODE6_WIREDANDFILTER << 24) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE6_WIREDANDPULLUP (_GPIO_P_MODEL_MODE6_WIREDANDPULLUP << 24) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE6_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE6_WIREDANDPULLUPFILTER << 24) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE6_WIREDANDALT (_GPIO_P_MODEL_MODE6_WIREDANDALT << 24) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE6_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE6_WIREDANDALTFILTER << 24) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE6_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE6_WIREDANDALTPULLUP << 24) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE6_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE6_WIREDANDALTPULLUPFILTER << 24) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE7_SHIFT 28 /**< Shift value for GPIO_MODE7 */ #define _GPIO_P_MODEL_MODE7_MASK 0xF0000000UL /**< Bit mask for GPIO_MODE7 */ #define _GPIO_P_MODEL_MODE7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE7_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE7_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE7_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE7_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE7_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE7_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE7_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE7_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE7_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE7_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE7_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE7_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE7_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE7_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE7_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ #define _GPIO_P_MODEL_MODE7_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE7_DEFAULT (_GPIO_P_MODEL_MODE7_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE7_DISABLED (_GPIO_P_MODEL_MODE7_DISABLED << 28) /**< Shifted mode DISABLED for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE7_INPUT (_GPIO_P_MODEL_MODE7_INPUT << 28) /**< Shifted mode INPUT for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE7_INPUTPULL (_GPIO_P_MODEL_MODE7_INPUTPULL << 28) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE7_INPUTPULLFILTER (_GPIO_P_MODEL_MODE7_INPUTPULLFILTER << 28) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE7_PUSHPULL (_GPIO_P_MODEL_MODE7_PUSHPULL << 28) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE7_PUSHPULLALT (_GPIO_P_MODEL_MODE7_PUSHPULLALT << 28) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE7_WIREDOR (_GPIO_P_MODEL_MODE7_WIREDOR << 28) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE7_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE7_WIREDORPULLDOWN << 28) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE7_WIREDAND (_GPIO_P_MODEL_MODE7_WIREDAND << 28) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE7_WIREDANDFILTER (_GPIO_P_MODEL_MODE7_WIREDANDFILTER << 28) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE7_WIREDANDPULLUP (_GPIO_P_MODEL_MODE7_WIREDANDPULLUP << 28) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE7_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE7_WIREDANDPULLUPFILTER << 28) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE7_WIREDANDALT (_GPIO_P_MODEL_MODE7_WIREDANDALT << 28) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE7_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE7_WIREDANDALTFILTER << 28) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE7_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE7_WIREDANDALTPULLUP << 28) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL */ #define GPIO_P_MODEL_MODE7_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE7_WIREDANDALTPULLUPFILTER << 28) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */ /* Bit fields for GPIO P_MODEH */ #define _GPIO_P_MODEH_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MASK 0xFFFFFFFFUL /**< Mask for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE8_SHIFT 0 /**< Shift value for GPIO_MODE8 */ #define _GPIO_P_MODEH_MODE8_MASK 0xFUL /**< Bit mask for GPIO_MODE8 */ #define _GPIO_P_MODEH_MODE8_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE8_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE8_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE8_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE8_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE8_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE8_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE8_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE8_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE8_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE8_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE8_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE8_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE8_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE8_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE8_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE8_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE8_DEFAULT (_GPIO_P_MODEH_MODE8_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE8_DISABLED (_GPIO_P_MODEH_MODE8_DISABLED << 0) /**< Shifted mode DISABLED for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE8_INPUT (_GPIO_P_MODEH_MODE8_INPUT << 0) /**< Shifted mode INPUT for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE8_INPUTPULL (_GPIO_P_MODEH_MODE8_INPUTPULL << 0) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE8_INPUTPULLFILTER (_GPIO_P_MODEH_MODE8_INPUTPULLFILTER << 0) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE8_PUSHPULL (_GPIO_P_MODEH_MODE8_PUSHPULL << 0) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE8_PUSHPULLALT (_GPIO_P_MODEH_MODE8_PUSHPULLALT << 0) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE8_WIREDOR (_GPIO_P_MODEH_MODE8_WIREDOR << 0) /**< Shifted mode WIREDOR for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE8_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE8_WIREDORPULLDOWN << 0) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE8_WIREDAND (_GPIO_P_MODEH_MODE8_WIREDAND << 0) /**< Shifted mode WIREDAND for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE8_WIREDANDFILTER (_GPIO_P_MODEH_MODE8_WIREDANDFILTER << 0) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE8_WIREDANDPULLUP (_GPIO_P_MODEH_MODE8_WIREDANDPULLUP << 0) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE8_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE8_WIREDANDPULLUPFILTER << 0) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE8_WIREDANDALT (_GPIO_P_MODEH_MODE8_WIREDANDALT << 0) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE8_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE8_WIREDANDALTFILTER << 0) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE8_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE8_WIREDANDALTPULLUP << 0) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE8_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE8_WIREDANDALTPULLUPFILTER << 0) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE9_SHIFT 4 /**< Shift value for GPIO_MODE9 */ #define _GPIO_P_MODEH_MODE9_MASK 0xF0UL /**< Bit mask for GPIO_MODE9 */ #define _GPIO_P_MODEH_MODE9_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE9_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE9_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE9_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE9_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE9_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE9_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE9_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE9_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE9_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE9_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE9_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE9_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE9_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE9_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE9_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE9_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE9_DEFAULT (_GPIO_P_MODEH_MODE9_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE9_DISABLED (_GPIO_P_MODEH_MODE9_DISABLED << 4) /**< Shifted mode DISABLED for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE9_INPUT (_GPIO_P_MODEH_MODE9_INPUT << 4) /**< Shifted mode INPUT for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE9_INPUTPULL (_GPIO_P_MODEH_MODE9_INPUTPULL << 4) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE9_INPUTPULLFILTER (_GPIO_P_MODEH_MODE9_INPUTPULLFILTER << 4) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE9_PUSHPULL (_GPIO_P_MODEH_MODE9_PUSHPULL << 4) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE9_PUSHPULLALT (_GPIO_P_MODEH_MODE9_PUSHPULLALT << 4) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE9_WIREDOR (_GPIO_P_MODEH_MODE9_WIREDOR << 4) /**< Shifted mode WIREDOR for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE9_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE9_WIREDORPULLDOWN << 4) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE9_WIREDAND (_GPIO_P_MODEH_MODE9_WIREDAND << 4) /**< Shifted mode WIREDAND for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE9_WIREDANDFILTER (_GPIO_P_MODEH_MODE9_WIREDANDFILTER << 4) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE9_WIREDANDPULLUP (_GPIO_P_MODEH_MODE9_WIREDANDPULLUP << 4) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE9_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE9_WIREDANDPULLUPFILTER << 4) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE9_WIREDANDALT (_GPIO_P_MODEH_MODE9_WIREDANDALT << 4) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE9_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE9_WIREDANDALTFILTER << 4) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE9_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE9_WIREDANDALTPULLUP << 4) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE9_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE9_WIREDANDALTPULLUPFILTER << 4) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE10_SHIFT 8 /**< Shift value for GPIO_MODE10 */ #define _GPIO_P_MODEH_MODE10_MASK 0xF00UL /**< Bit mask for GPIO_MODE10 */ #define _GPIO_P_MODEH_MODE10_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE10_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE10_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE10_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE10_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE10_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE10_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE10_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE10_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE10_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE10_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE10_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE10_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE10_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE10_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE10_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE10_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE10_DEFAULT (_GPIO_P_MODEH_MODE10_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE10_DISABLED (_GPIO_P_MODEH_MODE10_DISABLED << 8) /**< Shifted mode DISABLED for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE10_INPUT (_GPIO_P_MODEH_MODE10_INPUT << 8) /**< Shifted mode INPUT for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE10_INPUTPULL (_GPIO_P_MODEH_MODE10_INPUTPULL << 8) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE10_INPUTPULLFILTER (_GPIO_P_MODEH_MODE10_INPUTPULLFILTER << 8) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE10_PUSHPULL (_GPIO_P_MODEH_MODE10_PUSHPULL << 8) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE10_PUSHPULLALT (_GPIO_P_MODEH_MODE10_PUSHPULLALT << 8) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE10_WIREDOR (_GPIO_P_MODEH_MODE10_WIREDOR << 8) /**< Shifted mode WIREDOR for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE10_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE10_WIREDORPULLDOWN << 8) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE10_WIREDAND (_GPIO_P_MODEH_MODE10_WIREDAND << 8) /**< Shifted mode WIREDAND for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE10_WIREDANDFILTER (_GPIO_P_MODEH_MODE10_WIREDANDFILTER << 8) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE10_WIREDANDPULLUP (_GPIO_P_MODEH_MODE10_WIREDANDPULLUP << 8) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE10_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE10_WIREDANDPULLUPFILTER << 8) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE10_WIREDANDALT (_GPIO_P_MODEH_MODE10_WIREDANDALT << 8) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE10_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE10_WIREDANDALTFILTER << 8) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE10_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE10_WIREDANDALTPULLUP << 8) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE10_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE10_WIREDANDALTPULLUPFILTER << 8) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE11_SHIFT 12 /**< Shift value for GPIO_MODE11 */ #define _GPIO_P_MODEH_MODE11_MASK 0xF000UL /**< Bit mask for GPIO_MODE11 */ #define _GPIO_P_MODEH_MODE11_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE11_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE11_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE11_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE11_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE11_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE11_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE11_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE11_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE11_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE11_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE11_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE11_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE11_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE11_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE11_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE11_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE11_DEFAULT (_GPIO_P_MODEH_MODE11_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE11_DISABLED (_GPIO_P_MODEH_MODE11_DISABLED << 12) /**< Shifted mode DISABLED for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE11_INPUT (_GPIO_P_MODEH_MODE11_INPUT << 12) /**< Shifted mode INPUT for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE11_INPUTPULL (_GPIO_P_MODEH_MODE11_INPUTPULL << 12) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE11_INPUTPULLFILTER (_GPIO_P_MODEH_MODE11_INPUTPULLFILTER << 12) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE11_PUSHPULL (_GPIO_P_MODEH_MODE11_PUSHPULL << 12) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE11_PUSHPULLALT (_GPIO_P_MODEH_MODE11_PUSHPULLALT << 12) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE11_WIREDOR (_GPIO_P_MODEH_MODE11_WIREDOR << 12) /**< Shifted mode WIREDOR for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE11_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE11_WIREDORPULLDOWN << 12) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE11_WIREDAND (_GPIO_P_MODEH_MODE11_WIREDAND << 12) /**< Shifted mode WIREDAND for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE11_WIREDANDFILTER (_GPIO_P_MODEH_MODE11_WIREDANDFILTER << 12) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE11_WIREDANDPULLUP (_GPIO_P_MODEH_MODE11_WIREDANDPULLUP << 12) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE11_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE11_WIREDANDPULLUPFILTER << 12) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE11_WIREDANDALT (_GPIO_P_MODEH_MODE11_WIREDANDALT << 12) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE11_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE11_WIREDANDALTFILTER << 12) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE11_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE11_WIREDANDALTPULLUP << 12) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE11_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE11_WIREDANDALTPULLUPFILTER << 12) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE12_SHIFT 16 /**< Shift value for GPIO_MODE12 */ #define _GPIO_P_MODEH_MODE12_MASK 0xF0000UL /**< Bit mask for GPIO_MODE12 */ #define _GPIO_P_MODEH_MODE12_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE12_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE12_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE12_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE12_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE12_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE12_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE12_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE12_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE12_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE12_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE12_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE12_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE12_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE12_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE12_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE12_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE12_DEFAULT (_GPIO_P_MODEH_MODE12_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE12_DISABLED (_GPIO_P_MODEH_MODE12_DISABLED << 16) /**< Shifted mode DISABLED for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE12_INPUT (_GPIO_P_MODEH_MODE12_INPUT << 16) /**< Shifted mode INPUT for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE12_INPUTPULL (_GPIO_P_MODEH_MODE12_INPUTPULL << 16) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE12_INPUTPULLFILTER (_GPIO_P_MODEH_MODE12_INPUTPULLFILTER << 16) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE12_PUSHPULL (_GPIO_P_MODEH_MODE12_PUSHPULL << 16) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE12_PUSHPULLALT (_GPIO_P_MODEH_MODE12_PUSHPULLALT << 16) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE12_WIREDOR (_GPIO_P_MODEH_MODE12_WIREDOR << 16) /**< Shifted mode WIREDOR for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE12_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE12_WIREDORPULLDOWN << 16) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE12_WIREDAND (_GPIO_P_MODEH_MODE12_WIREDAND << 16) /**< Shifted mode WIREDAND for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE12_WIREDANDFILTER (_GPIO_P_MODEH_MODE12_WIREDANDFILTER << 16) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE12_WIREDANDPULLUP (_GPIO_P_MODEH_MODE12_WIREDANDPULLUP << 16) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE12_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE12_WIREDANDPULLUPFILTER << 16) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE12_WIREDANDALT (_GPIO_P_MODEH_MODE12_WIREDANDALT << 16) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE12_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE12_WIREDANDALTFILTER << 16) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE12_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE12_WIREDANDALTPULLUP << 16) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE12_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE12_WIREDANDALTPULLUPFILTER << 16) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE13_SHIFT 20 /**< Shift value for GPIO_MODE13 */ #define _GPIO_P_MODEH_MODE13_MASK 0xF00000UL /**< Bit mask for GPIO_MODE13 */ #define _GPIO_P_MODEH_MODE13_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE13_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE13_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE13_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE13_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE13_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE13_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE13_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE13_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE13_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE13_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE13_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE13_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE13_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE13_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE13_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE13_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE13_DEFAULT (_GPIO_P_MODEH_MODE13_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE13_DISABLED (_GPIO_P_MODEH_MODE13_DISABLED << 20) /**< Shifted mode DISABLED for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE13_INPUT (_GPIO_P_MODEH_MODE13_INPUT << 20) /**< Shifted mode INPUT for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE13_INPUTPULL (_GPIO_P_MODEH_MODE13_INPUTPULL << 20) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE13_INPUTPULLFILTER (_GPIO_P_MODEH_MODE13_INPUTPULLFILTER << 20) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE13_PUSHPULL (_GPIO_P_MODEH_MODE13_PUSHPULL << 20) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE13_PUSHPULLALT (_GPIO_P_MODEH_MODE13_PUSHPULLALT << 20) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE13_WIREDOR (_GPIO_P_MODEH_MODE13_WIREDOR << 20) /**< Shifted mode WIREDOR for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE13_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE13_WIREDORPULLDOWN << 20) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE13_WIREDAND (_GPIO_P_MODEH_MODE13_WIREDAND << 20) /**< Shifted mode WIREDAND for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE13_WIREDANDFILTER (_GPIO_P_MODEH_MODE13_WIREDANDFILTER << 20) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE13_WIREDANDPULLUP (_GPIO_P_MODEH_MODE13_WIREDANDPULLUP << 20) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE13_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE13_WIREDANDPULLUPFILTER << 20) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE13_WIREDANDALT (_GPIO_P_MODEH_MODE13_WIREDANDALT << 20) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE13_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE13_WIREDANDALTFILTER << 20) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE13_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE13_WIREDANDALTPULLUP << 20) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE13_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE13_WIREDANDALTPULLUPFILTER << 20) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE14_SHIFT 24 /**< Shift value for GPIO_MODE14 */ #define _GPIO_P_MODEH_MODE14_MASK 0xF000000UL /**< Bit mask for GPIO_MODE14 */ #define _GPIO_P_MODEH_MODE14_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE14_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE14_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE14_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE14_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE14_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE14_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE14_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE14_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE14_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE14_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE14_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE14_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE14_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE14_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE14_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE14_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE14_DEFAULT (_GPIO_P_MODEH_MODE14_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE14_DISABLED (_GPIO_P_MODEH_MODE14_DISABLED << 24) /**< Shifted mode DISABLED for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE14_INPUT (_GPIO_P_MODEH_MODE14_INPUT << 24) /**< Shifted mode INPUT for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE14_INPUTPULL (_GPIO_P_MODEH_MODE14_INPUTPULL << 24) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE14_INPUTPULLFILTER (_GPIO_P_MODEH_MODE14_INPUTPULLFILTER << 24) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE14_PUSHPULL (_GPIO_P_MODEH_MODE14_PUSHPULL << 24) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE14_PUSHPULLALT (_GPIO_P_MODEH_MODE14_PUSHPULLALT << 24) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE14_WIREDOR (_GPIO_P_MODEH_MODE14_WIREDOR << 24) /**< Shifted mode WIREDOR for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE14_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE14_WIREDORPULLDOWN << 24) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE14_WIREDAND (_GPIO_P_MODEH_MODE14_WIREDAND << 24) /**< Shifted mode WIREDAND for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE14_WIREDANDFILTER (_GPIO_P_MODEH_MODE14_WIREDANDFILTER << 24) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE14_WIREDANDPULLUP (_GPIO_P_MODEH_MODE14_WIREDANDPULLUP << 24) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE14_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE14_WIREDANDPULLUPFILTER << 24) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE14_WIREDANDALT (_GPIO_P_MODEH_MODE14_WIREDANDALT << 24) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE14_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE14_WIREDANDALTFILTER << 24) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE14_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE14_WIREDANDALTPULLUP << 24) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE14_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE14_WIREDANDALTPULLUPFILTER << 24) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE15_SHIFT 28 /**< Shift value for GPIO_MODE15 */ #define _GPIO_P_MODEH_MODE15_MASK 0xF0000000UL /**< Bit mask for GPIO_MODE15 */ #define _GPIO_P_MODEH_MODE15_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE15_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE15_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE15_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE15_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE15_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE15_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE15_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE15_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE15_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE15_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE15_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE15_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE15_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE15_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE15_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */ #define _GPIO_P_MODEH_MODE15_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE15_DEFAULT (_GPIO_P_MODEH_MODE15_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE15_DISABLED (_GPIO_P_MODEH_MODE15_DISABLED << 28) /**< Shifted mode DISABLED for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE15_INPUT (_GPIO_P_MODEH_MODE15_INPUT << 28) /**< Shifted mode INPUT for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE15_INPUTPULL (_GPIO_P_MODEH_MODE15_INPUTPULL << 28) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE15_INPUTPULLFILTER (_GPIO_P_MODEH_MODE15_INPUTPULLFILTER << 28) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE15_PUSHPULL (_GPIO_P_MODEH_MODE15_PUSHPULL << 28) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE15_PUSHPULLALT (_GPIO_P_MODEH_MODE15_PUSHPULLALT << 28) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE15_WIREDOR (_GPIO_P_MODEH_MODE15_WIREDOR << 28) /**< Shifted mode WIREDOR for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE15_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE15_WIREDORPULLDOWN << 28) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE15_WIREDAND (_GPIO_P_MODEH_MODE15_WIREDAND << 28) /**< Shifted mode WIREDAND for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE15_WIREDANDFILTER (_GPIO_P_MODEH_MODE15_WIREDANDFILTER << 28) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE15_WIREDANDPULLUP (_GPIO_P_MODEH_MODE15_WIREDANDPULLUP << 28) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE15_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE15_WIREDANDPULLUPFILTER << 28) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE15_WIREDANDALT (_GPIO_P_MODEH_MODE15_WIREDANDALT << 28) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE15_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE15_WIREDANDALTFILTER << 28) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE15_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE15_WIREDANDALTPULLUP << 28) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH */ #define GPIO_P_MODEH_MODE15_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE15_WIREDANDALTPULLUPFILTER << 28) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */ /* Bit fields for GPIO P_DOUT */ #define _GPIO_P_DOUT_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_DOUT */ #define _GPIO_P_DOUT_MASK 0x0000FFFFUL /**< Mask for GPIO_P_DOUT */ #define _GPIO_P_DOUT_DOUT_SHIFT 0 /**< Shift value for GPIO_DOUT */ #define _GPIO_P_DOUT_DOUT_MASK 0xFFFFUL /**< Bit mask for GPIO_DOUT */ #define _GPIO_P_DOUT_DOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_DOUT */ #define GPIO_P_DOUT_DOUT_DEFAULT (_GPIO_P_DOUT_DOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_DOUT */ /* Bit fields for GPIO P_DOUTTGL */ #define _GPIO_P_DOUTTGL_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_DOUTTGL */ #define _GPIO_P_DOUTTGL_MASK 0x0000FFFFUL /**< Mask for GPIO_P_DOUTTGL */ #define _GPIO_P_DOUTTGL_DOUTTGL_SHIFT 0 /**< Shift value for GPIO_DOUTTGL */ #define _GPIO_P_DOUTTGL_DOUTTGL_MASK 0xFFFFUL /**< Bit mask for GPIO_DOUTTGL */ #define _GPIO_P_DOUTTGL_DOUTTGL_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_DOUTTGL */ #define GPIO_P_DOUTTGL_DOUTTGL_DEFAULT (_GPIO_P_DOUTTGL_DOUTTGL_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_DOUTTGL */ /* Bit fields for GPIO P_DIN */ #define _GPIO_P_DIN_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_DIN */ #define _GPIO_P_DIN_MASK 0x0000FFFFUL /**< Mask for GPIO_P_DIN */ #define _GPIO_P_DIN_DIN_SHIFT 0 /**< Shift value for GPIO_DIN */ #define _GPIO_P_DIN_DIN_MASK 0xFFFFUL /**< Bit mask for GPIO_DIN */ #define _GPIO_P_DIN_DIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_DIN */ #define GPIO_P_DIN_DIN_DEFAULT (_GPIO_P_DIN_DIN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_DIN */ /* Bit fields for GPIO P_PINLOCKN */ #define _GPIO_P_PINLOCKN_RESETVALUE 0x0000FFFFUL /**< Default value for GPIO_P_PINLOCKN */ #define _GPIO_P_PINLOCKN_MASK 0x0000FFFFUL /**< Mask for GPIO_P_PINLOCKN */ #define _GPIO_P_PINLOCKN_PINLOCKN_SHIFT 0 /**< Shift value for GPIO_PINLOCKN */ #define _GPIO_P_PINLOCKN_PINLOCKN_MASK 0xFFFFUL /**< Bit mask for GPIO_PINLOCKN */ #define _GPIO_P_PINLOCKN_PINLOCKN_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for GPIO_P_PINLOCKN */ #define GPIO_P_PINLOCKN_PINLOCKN_DEFAULT (_GPIO_P_PINLOCKN_PINLOCKN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_PINLOCKN */ /* Bit fields for GPIO P_OVTDIS */ #define _GPIO_P_OVTDIS_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_OVTDIS */ #define _GPIO_P_OVTDIS_MASK 0x0000FFFFUL /**< Mask for GPIO_P_OVTDIS */ #define _GPIO_P_OVTDIS_OVTDIS_SHIFT 0 /**< Shift value for GPIO_OVTDIS */ #define _GPIO_P_OVTDIS_OVTDIS_MASK 0xFFFFUL /**< Bit mask for GPIO_OVTDIS */ #define _GPIO_P_OVTDIS_OVTDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_OVTDIS */ #define GPIO_P_OVTDIS_OVTDIS_DEFAULT (_GPIO_P_OVTDIS_OVTDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_OVTDIS */ /* Bit fields for GPIO EXTIPSELL */ #define _GPIO_EXTIPSELL_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIPSELL */ #define _GPIO_EXTIPSELL_MASK 0xFFFFFFFFUL /**< Mask for GPIO_EXTIPSELL */ #define _GPIO_EXTIPSELL_EXTIPSEL0_SHIFT 0 /**< Shift value for GPIO_EXTIPSEL0 */ #define _GPIO_EXTIPSELL_EXTIPSEL0_MASK 0xFUL /**< Bit mask for GPIO_EXTIPSEL0 */ #define _GPIO_EXTIPSELL_EXTIPSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ #define _GPIO_EXTIPSELL_EXTIPSEL0_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ #define _GPIO_EXTIPSELL_EXTIPSEL0_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ #define _GPIO_EXTIPSELL_EXTIPSEL0_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ #define _GPIO_EXTIPSELL_EXTIPSEL0_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ #define _GPIO_EXTIPSELL_EXTIPSEL0_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELL */ #define _GPIO_EXTIPSELL_EXTIPSEL0_PORTI 0x00000008UL /**< Mode PORTI for GPIO_EXTIPSELL */ #define _GPIO_EXTIPSELL_EXTIPSEL0_PORTJ 0x00000009UL /**< Mode PORTJ for GPIO_EXTIPSELL */ #define _GPIO_EXTIPSELL_EXTIPSEL0_PORTK 0x0000000AUL /**< Mode PORTK for GPIO_EXTIPSELL */ #define GPIO_EXTIPSELL_EXTIPSEL0_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ #define GPIO_EXTIPSELL_EXTIPSEL0_PORTA (_GPIO_EXTIPSELL_EXTIPSEL0_PORTA << 0) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ #define GPIO_EXTIPSELL_EXTIPSEL0_PORTB (_GPIO_EXTIPSELL_EXTIPSEL0_PORTB << 0) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ #define GPIO_EXTIPSELL_EXTIPSEL0_PORTC (_GPIO_EXTIPSELL_EXTIPSEL0_PORTC << 0) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ #define GPIO_EXTIPSELL_EXTIPSEL0_PORTD (_GPIO_EXTIPSELL_EXTIPSEL0_PORTD << 0) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ #define GPIO_EXTIPSELL_EXTIPSEL0_PORTF (_GPIO_EXTIPSELL_EXTIPSEL0_PORTF << 0) /**< Shifted mode PORTF for GPIO_EXTIPSELL */ #define GPIO_EXTIPSELL_EXTIPSEL0_PORTI (_GPIO_EXTIPSELL_EXTIPSEL0_PORTI << 0) /**< Shifted mode PORTI for GPIO_EXTIPSELL */ #define GPIO_EXTIPSELL_EXTIPSEL0_PORTJ (_GPIO_EXTIPSELL_EXTIPSEL0_PORTJ << 0) /**< Shifted mode PORTJ for GPIO_EXTIPSELL */ #define GPIO_EXTIPSELL_EXTIPSEL0_PORTK (_GPIO_EXTIPSELL_EXTIPSEL0_PORTK << 0) /**< Shifted mode PORTK for GPIO_EXTIPSELL */ #define _GPIO_EXTIPSELL_EXTIPSEL1_SHIFT 4 /**< Shift value for GPIO_EXTIPSEL1 */ #define _GPIO_EXTIPSELL_EXTIPSEL1_MASK 0xF0UL /**< Bit mask for GPIO_EXTIPSEL1 */ #define _GPIO_EXTIPSELL_EXTIPSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ #define _GPIO_EXTIPSELL_EXTIPSEL1_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ #define _GPIO_EXTIPSELL_EXTIPSEL1_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ #define _GPIO_EXTIPSELL_EXTIPSEL1_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ #define _GPIO_EXTIPSELL_EXTIPSEL1_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ #define _GPIO_EXTIPSELL_EXTIPSEL1_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELL */ #define _GPIO_EXTIPSELL_EXTIPSEL1_PORTI 0x00000008UL /**< Mode PORTI for GPIO_EXTIPSELL */ #define _GPIO_EXTIPSELL_EXTIPSEL1_PORTJ 0x00000009UL /**< Mode PORTJ for GPIO_EXTIPSELL */ #define _GPIO_EXTIPSELL_EXTIPSEL1_PORTK 0x0000000AUL /**< Mode PORTK for GPIO_EXTIPSELL */ #define GPIO_EXTIPSELL_EXTIPSEL1_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ #define GPIO_EXTIPSELL_EXTIPSEL1_PORTA (_GPIO_EXTIPSELL_EXTIPSEL1_PORTA << 4) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ #define GPIO_EXTIPSELL_EXTIPSEL1_PORTB (_GPIO_EXTIPSELL_EXTIPSEL1_PORTB << 4) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ #define GPIO_EXTIPSELL_EXTIPSEL1_PORTC (_GPIO_EXTIPSELL_EXTIPSEL1_PORTC << 4) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ #define GPIO_EXTIPSELL_EXTIPSEL1_PORTD (_GPIO_EXTIPSELL_EXTIPSEL1_PORTD << 4) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ #define GPIO_EXTIPSELL_EXTIPSEL1_PORTF (_GPIO_EXTIPSELL_EXTIPSEL1_PORTF << 4) /**< Shifted mode PORTF for GPIO_EXTIPSELL */ #define GPIO_EXTIPSELL_EXTIPSEL1_PORTI (_GPIO_EXTIPSELL_EXTIPSEL1_PORTI << 4) /**< Shifted mode PORTI for GPIO_EXTIPSELL */ #define GPIO_EXTIPSELL_EXTIPSEL1_PORTJ (_GPIO_EXTIPSELL_EXTIPSEL1_PORTJ << 4) /**< Shifted mode PORTJ for GPIO_EXTIPSELL */ #define GPIO_EXTIPSELL_EXTIPSEL1_PORTK (_GPIO_EXTIPSELL_EXTIPSEL1_PORTK << 4) /**< Shifted mode PORTK for GPIO_EXTIPSELL */ #define _GPIO_EXTIPSELL_EXTIPSEL2_SHIFT 8 /**< Shift value for GPIO_EXTIPSEL2 */ #define _GPIO_EXTIPSELL_EXTIPSEL2_MASK 0xF00UL /**< Bit mask for GPIO_EXTIPSEL2 */ #define _GPIO_EXTIPSELL_EXTIPSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ #define _GPIO_EXTIPSELL_EXTIPSEL2_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ #define _GPIO_EXTIPSELL_EXTIPSEL2_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ #define _GPIO_EXTIPSELL_EXTIPSEL2_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ #define _GPIO_EXTIPSELL_EXTIPSEL2_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ #define _GPIO_EXTIPSELL_EXTIPSEL2_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELL */ #define _GPIO_EXTIPSELL_EXTIPSEL2_PORTI 0x00000008UL /**< Mode PORTI for GPIO_EXTIPSELL */ #define _GPIO_EXTIPSELL_EXTIPSEL2_PORTJ 0x00000009UL /**< Mode PORTJ for GPIO_EXTIPSELL */ #define _GPIO_EXTIPSELL_EXTIPSEL2_PORTK 0x0000000AUL /**< Mode PORTK for GPIO_EXTIPSELL */ #define GPIO_EXTIPSELL_EXTIPSEL2_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL2_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ #define GPIO_EXTIPSELL_EXTIPSEL2_PORTA (_GPIO_EXTIPSELL_EXTIPSEL2_PORTA << 8) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ #define GPIO_EXTIPSELL_EXTIPSEL2_PORTB (_GPIO_EXTIPSELL_EXTIPSEL2_PORTB << 8) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ #define GPIO_EXTIPSELL_EXTIPSEL2_PORTC (_GPIO_EXTIPSELL_EXTIPSEL2_PORTC << 8) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ #define GPIO_EXTIPSELL_EXTIPSEL2_PORTD (_GPIO_EXTIPSELL_EXTIPSEL2_PORTD << 8) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ #define GPIO_EXTIPSELL_EXTIPSEL2_PORTF (_GPIO_EXTIPSELL_EXTIPSEL2_PORTF << 8) /**< Shifted mode PORTF for GPIO_EXTIPSELL */ #define GPIO_EXTIPSELL_EXTIPSEL2_PORTI (_GPIO_EXTIPSELL_EXTIPSEL2_PORTI << 8) /**< Shifted mode PORTI for GPIO_EXTIPSELL */ #define GPIO_EXTIPSELL_EXTIPSEL2_PORTJ (_GPIO_EXTIPSELL_EXTIPSEL2_PORTJ << 8) /**< Shifted mode PORTJ for GPIO_EXTIPSELL */ #define GPIO_EXTIPSELL_EXTIPSEL2_PORTK (_GPIO_EXTIPSELL_EXTIPSEL2_PORTK << 8) /**< Shifted mode PORTK for GPIO_EXTIPSELL */ #define _GPIO_EXTIPSELL_EXTIPSEL3_SHIFT 12 /**< Shift value for GPIO_EXTIPSEL3 */ #define _GPIO_EXTIPSELL_EXTIPSEL3_MASK 0xF000UL /**< Bit mask for GPIO_EXTIPSEL3 */ #define _GPIO_EXTIPSELL_EXTIPSEL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ #define _GPIO_EXTIPSELL_EXTIPSEL3_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ #define _GPIO_EXTIPSELL_EXTIPSEL3_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ #define _GPIO_EXTIPSELL_EXTIPSEL3_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ #define _GPIO_EXTIPSELL_EXTIPSEL3_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ #define _GPIO_EXTIPSELL_EXTIPSEL3_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELL */ #define _GPIO_EXTIPSELL_EXTIPSEL3_PORTI 0x00000008UL /**< Mode PORTI for GPIO_EXTIPSELL */ #define _GPIO_EXTIPSELL_EXTIPSEL3_PORTJ 0x00000009UL /**< Mode PORTJ for GPIO_EXTIPSELL */ #define _GPIO_EXTIPSELL_EXTIPSEL3_PORTK 0x0000000AUL /**< Mode PORTK for GPIO_EXTIPSELL */ #define GPIO_EXTIPSELL_EXTIPSEL3_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL3_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ #define GPIO_EXTIPSELL_EXTIPSEL3_PORTA (_GPIO_EXTIPSELL_EXTIPSEL3_PORTA << 12) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ #define GPIO_EXTIPSELL_EXTIPSEL3_PORTB (_GPIO_EXTIPSELL_EXTIPSEL3_PORTB << 12) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ #define GPIO_EXTIPSELL_EXTIPSEL3_PORTC (_GPIO_EXTIPSELL_EXTIPSEL3_PORTC << 12) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ #define GPIO_EXTIPSELL_EXTIPSEL3_PORTD (_GPIO_EXTIPSELL_EXTIPSEL3_PORTD << 12) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ #define GPIO_EXTIPSELL_EXTIPSEL3_PORTF (_GPIO_EXTIPSELL_EXTIPSEL3_PORTF << 12) /**< Shifted mode PORTF for GPIO_EXTIPSELL */ #define GPIO_EXTIPSELL_EXTIPSEL3_PORTI (_GPIO_EXTIPSELL_EXTIPSEL3_PORTI << 12) /**< Shifted mode PORTI for GPIO_EXTIPSELL */ #define GPIO_EXTIPSELL_EXTIPSEL3_PORTJ (_GPIO_EXTIPSELL_EXTIPSEL3_PORTJ << 12) /**< Shifted mode PORTJ for GPIO_EXTIPSELL */ #define GPIO_EXTIPSELL_EXTIPSEL3_PORTK (_GPIO_EXTIPSELL_EXTIPSEL3_PORTK << 12) /**< Shifted mode PORTK for GPIO_EXTIPSELL */ #define _GPIO_EXTIPSELL_EXTIPSEL4_SHIFT 16 /**< Shift value for GPIO_EXTIPSEL4 */ #define _GPIO_EXTIPSELL_EXTIPSEL4_MASK 0xF0000UL /**< Bit mask for GPIO_EXTIPSEL4 */ #define _GPIO_EXTIPSELL_EXTIPSEL4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ #define _GPIO_EXTIPSELL_EXTIPSEL4_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ #define _GPIO_EXTIPSELL_EXTIPSEL4_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ #define _GPIO_EXTIPSELL_EXTIPSEL4_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ #define _GPIO_EXTIPSELL_EXTIPSEL4_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ #define _GPIO_EXTIPSELL_EXTIPSEL4_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELL */ #define _GPIO_EXTIPSELL_EXTIPSEL4_PORTI 0x00000008UL /**< Mode PORTI for GPIO_EXTIPSELL */ #define _GPIO_EXTIPSELL_EXTIPSEL4_PORTJ 0x00000009UL /**< Mode PORTJ for GPIO_EXTIPSELL */ #define _GPIO_EXTIPSELL_EXTIPSEL4_PORTK 0x0000000AUL /**< Mode PORTK for GPIO_EXTIPSELL */ #define GPIO_EXTIPSELL_EXTIPSEL4_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL4_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ #define GPIO_EXTIPSELL_EXTIPSEL4_PORTA (_GPIO_EXTIPSELL_EXTIPSEL4_PORTA << 16) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ #define GPIO_EXTIPSELL_EXTIPSEL4_PORTB (_GPIO_EXTIPSELL_EXTIPSEL4_PORTB << 16) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ #define GPIO_EXTIPSELL_EXTIPSEL4_PORTC (_GPIO_EXTIPSELL_EXTIPSEL4_PORTC << 16) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ #define GPIO_EXTIPSELL_EXTIPSEL4_PORTD (_GPIO_EXTIPSELL_EXTIPSEL4_PORTD << 16) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ #define GPIO_EXTIPSELL_EXTIPSEL4_PORTF (_GPIO_EXTIPSELL_EXTIPSEL4_PORTF << 16) /**< Shifted mode PORTF for GPIO_EXTIPSELL */ #define GPIO_EXTIPSELL_EXTIPSEL4_PORTI (_GPIO_EXTIPSELL_EXTIPSEL4_PORTI << 16) /**< Shifted mode PORTI for GPIO_EXTIPSELL */ #define GPIO_EXTIPSELL_EXTIPSEL4_PORTJ (_GPIO_EXTIPSELL_EXTIPSEL4_PORTJ << 16) /**< Shifted mode PORTJ for GPIO_EXTIPSELL */ #define GPIO_EXTIPSELL_EXTIPSEL4_PORTK (_GPIO_EXTIPSELL_EXTIPSEL4_PORTK << 16) /**< Shifted mode PORTK for GPIO_EXTIPSELL */ #define _GPIO_EXTIPSELL_EXTIPSEL5_SHIFT 20 /**< Shift value for GPIO_EXTIPSEL5 */ #define _GPIO_EXTIPSELL_EXTIPSEL5_MASK 0xF00000UL /**< Bit mask for GPIO_EXTIPSEL5 */ #define _GPIO_EXTIPSELL_EXTIPSEL5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ #define _GPIO_EXTIPSELL_EXTIPSEL5_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ #define _GPIO_EXTIPSELL_EXTIPSEL5_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ #define _GPIO_EXTIPSELL_EXTIPSEL5_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ #define _GPIO_EXTIPSELL_EXTIPSEL5_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ #define _GPIO_EXTIPSELL_EXTIPSEL5_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELL */ #define _GPIO_EXTIPSELL_EXTIPSEL5_PORTI 0x00000008UL /**< Mode PORTI for GPIO_EXTIPSELL */ #define _GPIO_EXTIPSELL_EXTIPSEL5_PORTJ 0x00000009UL /**< Mode PORTJ for GPIO_EXTIPSELL */ #define _GPIO_EXTIPSELL_EXTIPSEL5_PORTK 0x0000000AUL /**< Mode PORTK for GPIO_EXTIPSELL */ #define GPIO_EXTIPSELL_EXTIPSEL5_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL5_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ #define GPIO_EXTIPSELL_EXTIPSEL5_PORTA (_GPIO_EXTIPSELL_EXTIPSEL5_PORTA << 20) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ #define GPIO_EXTIPSELL_EXTIPSEL5_PORTB (_GPIO_EXTIPSELL_EXTIPSEL5_PORTB << 20) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ #define GPIO_EXTIPSELL_EXTIPSEL5_PORTC (_GPIO_EXTIPSELL_EXTIPSEL5_PORTC << 20) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ #define GPIO_EXTIPSELL_EXTIPSEL5_PORTD (_GPIO_EXTIPSELL_EXTIPSEL5_PORTD << 20) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ #define GPIO_EXTIPSELL_EXTIPSEL5_PORTF (_GPIO_EXTIPSELL_EXTIPSEL5_PORTF << 20) /**< Shifted mode PORTF for GPIO_EXTIPSELL */ #define GPIO_EXTIPSELL_EXTIPSEL5_PORTI (_GPIO_EXTIPSELL_EXTIPSEL5_PORTI << 20) /**< Shifted mode PORTI for GPIO_EXTIPSELL */ #define GPIO_EXTIPSELL_EXTIPSEL5_PORTJ (_GPIO_EXTIPSELL_EXTIPSEL5_PORTJ << 20) /**< Shifted mode PORTJ for GPIO_EXTIPSELL */ #define GPIO_EXTIPSELL_EXTIPSEL5_PORTK (_GPIO_EXTIPSELL_EXTIPSEL5_PORTK << 20) /**< Shifted mode PORTK for GPIO_EXTIPSELL */ #define _GPIO_EXTIPSELL_EXTIPSEL6_SHIFT 24 /**< Shift value for GPIO_EXTIPSEL6 */ #define _GPIO_EXTIPSELL_EXTIPSEL6_MASK 0xF000000UL /**< Bit mask for GPIO_EXTIPSEL6 */ #define _GPIO_EXTIPSELL_EXTIPSEL6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ #define _GPIO_EXTIPSELL_EXTIPSEL6_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ #define _GPIO_EXTIPSELL_EXTIPSEL6_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ #define _GPIO_EXTIPSELL_EXTIPSEL6_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ #define _GPIO_EXTIPSELL_EXTIPSEL6_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ #define _GPIO_EXTIPSELL_EXTIPSEL6_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELL */ #define _GPIO_EXTIPSELL_EXTIPSEL6_PORTI 0x00000008UL /**< Mode PORTI for GPIO_EXTIPSELL */ #define _GPIO_EXTIPSELL_EXTIPSEL6_PORTJ 0x00000009UL /**< Mode PORTJ for GPIO_EXTIPSELL */ #define _GPIO_EXTIPSELL_EXTIPSEL6_PORTK 0x0000000AUL /**< Mode PORTK for GPIO_EXTIPSELL */ #define GPIO_EXTIPSELL_EXTIPSEL6_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL6_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ #define GPIO_EXTIPSELL_EXTIPSEL6_PORTA (_GPIO_EXTIPSELL_EXTIPSEL6_PORTA << 24) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ #define GPIO_EXTIPSELL_EXTIPSEL6_PORTB (_GPIO_EXTIPSELL_EXTIPSEL6_PORTB << 24) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ #define GPIO_EXTIPSELL_EXTIPSEL6_PORTC (_GPIO_EXTIPSELL_EXTIPSEL6_PORTC << 24) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ #define GPIO_EXTIPSELL_EXTIPSEL6_PORTD (_GPIO_EXTIPSELL_EXTIPSEL6_PORTD << 24) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ #define GPIO_EXTIPSELL_EXTIPSEL6_PORTF (_GPIO_EXTIPSELL_EXTIPSEL6_PORTF << 24) /**< Shifted mode PORTF for GPIO_EXTIPSELL */ #define GPIO_EXTIPSELL_EXTIPSEL6_PORTI (_GPIO_EXTIPSELL_EXTIPSEL6_PORTI << 24) /**< Shifted mode PORTI for GPIO_EXTIPSELL */ #define GPIO_EXTIPSELL_EXTIPSEL6_PORTJ (_GPIO_EXTIPSELL_EXTIPSEL6_PORTJ << 24) /**< Shifted mode PORTJ for GPIO_EXTIPSELL */ #define GPIO_EXTIPSELL_EXTIPSEL6_PORTK (_GPIO_EXTIPSELL_EXTIPSEL6_PORTK << 24) /**< Shifted mode PORTK for GPIO_EXTIPSELL */ #define _GPIO_EXTIPSELL_EXTIPSEL7_SHIFT 28 /**< Shift value for GPIO_EXTIPSEL7 */ #define _GPIO_EXTIPSELL_EXTIPSEL7_MASK 0xF0000000UL /**< Bit mask for GPIO_EXTIPSEL7 */ #define _GPIO_EXTIPSELL_EXTIPSEL7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ #define _GPIO_EXTIPSELL_EXTIPSEL7_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ #define _GPIO_EXTIPSELL_EXTIPSEL7_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ #define _GPIO_EXTIPSELL_EXTIPSEL7_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ #define _GPIO_EXTIPSELL_EXTIPSEL7_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ #define _GPIO_EXTIPSELL_EXTIPSEL7_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELL */ #define _GPIO_EXTIPSELL_EXTIPSEL7_PORTI 0x00000008UL /**< Mode PORTI for GPIO_EXTIPSELL */ #define _GPIO_EXTIPSELL_EXTIPSEL7_PORTJ 0x00000009UL /**< Mode PORTJ for GPIO_EXTIPSELL */ #define _GPIO_EXTIPSELL_EXTIPSEL7_PORTK 0x0000000AUL /**< Mode PORTK for GPIO_EXTIPSELL */ #define GPIO_EXTIPSELL_EXTIPSEL7_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL7_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ #define GPIO_EXTIPSELL_EXTIPSEL7_PORTA (_GPIO_EXTIPSELL_EXTIPSEL7_PORTA << 28) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ #define GPIO_EXTIPSELL_EXTIPSEL7_PORTB (_GPIO_EXTIPSELL_EXTIPSEL7_PORTB << 28) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ #define GPIO_EXTIPSELL_EXTIPSEL7_PORTC (_GPIO_EXTIPSELL_EXTIPSEL7_PORTC << 28) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ #define GPIO_EXTIPSELL_EXTIPSEL7_PORTD (_GPIO_EXTIPSELL_EXTIPSEL7_PORTD << 28) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ #define GPIO_EXTIPSELL_EXTIPSEL7_PORTF (_GPIO_EXTIPSELL_EXTIPSEL7_PORTF << 28) /**< Shifted mode PORTF for GPIO_EXTIPSELL */ #define GPIO_EXTIPSELL_EXTIPSEL7_PORTI (_GPIO_EXTIPSELL_EXTIPSEL7_PORTI << 28) /**< Shifted mode PORTI for GPIO_EXTIPSELL */ #define GPIO_EXTIPSELL_EXTIPSEL7_PORTJ (_GPIO_EXTIPSELL_EXTIPSEL7_PORTJ << 28) /**< Shifted mode PORTJ for GPIO_EXTIPSELL */ #define GPIO_EXTIPSELL_EXTIPSEL7_PORTK (_GPIO_EXTIPSELL_EXTIPSEL7_PORTK << 28) /**< Shifted mode PORTK for GPIO_EXTIPSELL */ /* Bit fields for GPIO EXTIPSELH */ #define _GPIO_EXTIPSELH_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIPSELH */ #define _GPIO_EXTIPSELH_MASK 0xFFFFFFFFUL /**< Mask for GPIO_EXTIPSELH */ #define _GPIO_EXTIPSELH_EXTIPSEL8_SHIFT 0 /**< Shift value for GPIO_EXTIPSEL8 */ #define _GPIO_EXTIPSELH_EXTIPSEL8_MASK 0xFUL /**< Bit mask for GPIO_EXTIPSEL8 */ #define _GPIO_EXTIPSELH_EXTIPSEL8_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ #define _GPIO_EXTIPSELH_EXTIPSEL8_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ #define _GPIO_EXTIPSELH_EXTIPSEL8_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ #define _GPIO_EXTIPSELH_EXTIPSEL8_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ #define _GPIO_EXTIPSELH_EXTIPSEL8_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ #define _GPIO_EXTIPSELH_EXTIPSEL8_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELH */ #define _GPIO_EXTIPSELH_EXTIPSEL8_PORTI 0x00000008UL /**< Mode PORTI for GPIO_EXTIPSELH */ #define _GPIO_EXTIPSELH_EXTIPSEL8_PORTJ 0x00000009UL /**< Mode PORTJ for GPIO_EXTIPSELH */ #define _GPIO_EXTIPSELH_EXTIPSEL8_PORTK 0x0000000AUL /**< Mode PORTK for GPIO_EXTIPSELH */ #define GPIO_EXTIPSELH_EXTIPSEL8_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL8_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ #define GPIO_EXTIPSELH_EXTIPSEL8_PORTA (_GPIO_EXTIPSELH_EXTIPSEL8_PORTA << 0) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ #define GPIO_EXTIPSELH_EXTIPSEL8_PORTB (_GPIO_EXTIPSELH_EXTIPSEL8_PORTB << 0) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ #define GPIO_EXTIPSELH_EXTIPSEL8_PORTC (_GPIO_EXTIPSELH_EXTIPSEL8_PORTC << 0) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ #define GPIO_EXTIPSELH_EXTIPSEL8_PORTD (_GPIO_EXTIPSELH_EXTIPSEL8_PORTD << 0) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ #define GPIO_EXTIPSELH_EXTIPSEL8_PORTF (_GPIO_EXTIPSELH_EXTIPSEL8_PORTF << 0) /**< Shifted mode PORTF for GPIO_EXTIPSELH */ #define GPIO_EXTIPSELH_EXTIPSEL8_PORTI (_GPIO_EXTIPSELH_EXTIPSEL8_PORTI << 0) /**< Shifted mode PORTI for GPIO_EXTIPSELH */ #define GPIO_EXTIPSELH_EXTIPSEL8_PORTJ (_GPIO_EXTIPSELH_EXTIPSEL8_PORTJ << 0) /**< Shifted mode PORTJ for GPIO_EXTIPSELH */ #define GPIO_EXTIPSELH_EXTIPSEL8_PORTK (_GPIO_EXTIPSELH_EXTIPSEL8_PORTK << 0) /**< Shifted mode PORTK for GPIO_EXTIPSELH */ #define _GPIO_EXTIPSELH_EXTIPSEL9_SHIFT 4 /**< Shift value for GPIO_EXTIPSEL9 */ #define _GPIO_EXTIPSELH_EXTIPSEL9_MASK 0xF0UL /**< Bit mask for GPIO_EXTIPSEL9 */ #define _GPIO_EXTIPSELH_EXTIPSEL9_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ #define _GPIO_EXTIPSELH_EXTIPSEL9_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ #define _GPIO_EXTIPSELH_EXTIPSEL9_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ #define _GPIO_EXTIPSELH_EXTIPSEL9_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ #define _GPIO_EXTIPSELH_EXTIPSEL9_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ #define _GPIO_EXTIPSELH_EXTIPSEL9_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELH */ #define _GPIO_EXTIPSELH_EXTIPSEL9_PORTI 0x00000008UL /**< Mode PORTI for GPIO_EXTIPSELH */ #define _GPIO_EXTIPSELH_EXTIPSEL9_PORTJ 0x00000009UL /**< Mode PORTJ for GPIO_EXTIPSELH */ #define _GPIO_EXTIPSELH_EXTIPSEL9_PORTK 0x0000000AUL /**< Mode PORTK for GPIO_EXTIPSELH */ #define GPIO_EXTIPSELH_EXTIPSEL9_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL9_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ #define GPIO_EXTIPSELH_EXTIPSEL9_PORTA (_GPIO_EXTIPSELH_EXTIPSEL9_PORTA << 4) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ #define GPIO_EXTIPSELH_EXTIPSEL9_PORTB (_GPIO_EXTIPSELH_EXTIPSEL9_PORTB << 4) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ #define GPIO_EXTIPSELH_EXTIPSEL9_PORTC (_GPIO_EXTIPSELH_EXTIPSEL9_PORTC << 4) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ #define GPIO_EXTIPSELH_EXTIPSEL9_PORTD (_GPIO_EXTIPSELH_EXTIPSEL9_PORTD << 4) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ #define GPIO_EXTIPSELH_EXTIPSEL9_PORTF (_GPIO_EXTIPSELH_EXTIPSEL9_PORTF << 4) /**< Shifted mode PORTF for GPIO_EXTIPSELH */ #define GPIO_EXTIPSELH_EXTIPSEL9_PORTI (_GPIO_EXTIPSELH_EXTIPSEL9_PORTI << 4) /**< Shifted mode PORTI for GPIO_EXTIPSELH */ #define GPIO_EXTIPSELH_EXTIPSEL9_PORTJ (_GPIO_EXTIPSELH_EXTIPSEL9_PORTJ << 4) /**< Shifted mode PORTJ for GPIO_EXTIPSELH */ #define GPIO_EXTIPSELH_EXTIPSEL9_PORTK (_GPIO_EXTIPSELH_EXTIPSEL9_PORTK << 4) /**< Shifted mode PORTK for GPIO_EXTIPSELH */ #define _GPIO_EXTIPSELH_EXTIPSEL10_SHIFT 8 /**< Shift value for GPIO_EXTIPSEL10 */ #define _GPIO_EXTIPSELH_EXTIPSEL10_MASK 0xF00UL /**< Bit mask for GPIO_EXTIPSEL10 */ #define _GPIO_EXTIPSELH_EXTIPSEL10_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ #define _GPIO_EXTIPSELH_EXTIPSEL10_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ #define _GPIO_EXTIPSELH_EXTIPSEL10_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ #define _GPIO_EXTIPSELH_EXTIPSEL10_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ #define _GPIO_EXTIPSELH_EXTIPSEL10_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ #define _GPIO_EXTIPSELH_EXTIPSEL10_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELH */ #define _GPIO_EXTIPSELH_EXTIPSEL10_PORTI 0x00000008UL /**< Mode PORTI for GPIO_EXTIPSELH */ #define _GPIO_EXTIPSELH_EXTIPSEL10_PORTJ 0x00000009UL /**< Mode PORTJ for GPIO_EXTIPSELH */ #define _GPIO_EXTIPSELH_EXTIPSEL10_PORTK 0x0000000AUL /**< Mode PORTK for GPIO_EXTIPSELH */ #define GPIO_EXTIPSELH_EXTIPSEL10_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL10_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ #define GPIO_EXTIPSELH_EXTIPSEL10_PORTA (_GPIO_EXTIPSELH_EXTIPSEL10_PORTA << 8) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ #define GPIO_EXTIPSELH_EXTIPSEL10_PORTB (_GPIO_EXTIPSELH_EXTIPSEL10_PORTB << 8) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ #define GPIO_EXTIPSELH_EXTIPSEL10_PORTC (_GPIO_EXTIPSELH_EXTIPSEL10_PORTC << 8) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ #define GPIO_EXTIPSELH_EXTIPSEL10_PORTD (_GPIO_EXTIPSELH_EXTIPSEL10_PORTD << 8) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ #define GPIO_EXTIPSELH_EXTIPSEL10_PORTF (_GPIO_EXTIPSELH_EXTIPSEL10_PORTF << 8) /**< Shifted mode PORTF for GPIO_EXTIPSELH */ #define GPIO_EXTIPSELH_EXTIPSEL10_PORTI (_GPIO_EXTIPSELH_EXTIPSEL10_PORTI << 8) /**< Shifted mode PORTI for GPIO_EXTIPSELH */ #define GPIO_EXTIPSELH_EXTIPSEL10_PORTJ (_GPIO_EXTIPSELH_EXTIPSEL10_PORTJ << 8) /**< Shifted mode PORTJ for GPIO_EXTIPSELH */ #define GPIO_EXTIPSELH_EXTIPSEL10_PORTK (_GPIO_EXTIPSELH_EXTIPSEL10_PORTK << 8) /**< Shifted mode PORTK for GPIO_EXTIPSELH */ #define _GPIO_EXTIPSELH_EXTIPSEL11_SHIFT 12 /**< Shift value for GPIO_EXTIPSEL11 */ #define _GPIO_EXTIPSELH_EXTIPSEL11_MASK 0xF000UL /**< Bit mask for GPIO_EXTIPSEL11 */ #define _GPIO_EXTIPSELH_EXTIPSEL11_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ #define _GPIO_EXTIPSELH_EXTIPSEL11_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ #define _GPIO_EXTIPSELH_EXTIPSEL11_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ #define _GPIO_EXTIPSELH_EXTIPSEL11_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ #define _GPIO_EXTIPSELH_EXTIPSEL11_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ #define _GPIO_EXTIPSELH_EXTIPSEL11_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELH */ #define _GPIO_EXTIPSELH_EXTIPSEL11_PORTI 0x00000008UL /**< Mode PORTI for GPIO_EXTIPSELH */ #define _GPIO_EXTIPSELH_EXTIPSEL11_PORTJ 0x00000009UL /**< Mode PORTJ for GPIO_EXTIPSELH */ #define _GPIO_EXTIPSELH_EXTIPSEL11_PORTK 0x0000000AUL /**< Mode PORTK for GPIO_EXTIPSELH */ #define GPIO_EXTIPSELH_EXTIPSEL11_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL11_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ #define GPIO_EXTIPSELH_EXTIPSEL11_PORTA (_GPIO_EXTIPSELH_EXTIPSEL11_PORTA << 12) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ #define GPIO_EXTIPSELH_EXTIPSEL11_PORTB (_GPIO_EXTIPSELH_EXTIPSEL11_PORTB << 12) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ #define GPIO_EXTIPSELH_EXTIPSEL11_PORTC (_GPIO_EXTIPSELH_EXTIPSEL11_PORTC << 12) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ #define GPIO_EXTIPSELH_EXTIPSEL11_PORTD (_GPIO_EXTIPSELH_EXTIPSEL11_PORTD << 12) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ #define GPIO_EXTIPSELH_EXTIPSEL11_PORTF (_GPIO_EXTIPSELH_EXTIPSEL11_PORTF << 12) /**< Shifted mode PORTF for GPIO_EXTIPSELH */ #define GPIO_EXTIPSELH_EXTIPSEL11_PORTI (_GPIO_EXTIPSELH_EXTIPSEL11_PORTI << 12) /**< Shifted mode PORTI for GPIO_EXTIPSELH */ #define GPIO_EXTIPSELH_EXTIPSEL11_PORTJ (_GPIO_EXTIPSELH_EXTIPSEL11_PORTJ << 12) /**< Shifted mode PORTJ for GPIO_EXTIPSELH */ #define GPIO_EXTIPSELH_EXTIPSEL11_PORTK (_GPIO_EXTIPSELH_EXTIPSEL11_PORTK << 12) /**< Shifted mode PORTK for GPIO_EXTIPSELH */ #define _GPIO_EXTIPSELH_EXTIPSEL12_SHIFT 16 /**< Shift value for GPIO_EXTIPSEL12 */ #define _GPIO_EXTIPSELH_EXTIPSEL12_MASK 0xF0000UL /**< Bit mask for GPIO_EXTIPSEL12 */ #define _GPIO_EXTIPSELH_EXTIPSEL12_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ #define _GPIO_EXTIPSELH_EXTIPSEL12_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ #define _GPIO_EXTIPSELH_EXTIPSEL12_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ #define _GPIO_EXTIPSELH_EXTIPSEL12_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ #define _GPIO_EXTIPSELH_EXTIPSEL12_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ #define _GPIO_EXTIPSELH_EXTIPSEL12_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELH */ #define _GPIO_EXTIPSELH_EXTIPSEL12_PORTI 0x00000008UL /**< Mode PORTI for GPIO_EXTIPSELH */ #define _GPIO_EXTIPSELH_EXTIPSEL12_PORTJ 0x00000009UL /**< Mode PORTJ for GPIO_EXTIPSELH */ #define _GPIO_EXTIPSELH_EXTIPSEL12_PORTK 0x0000000AUL /**< Mode PORTK for GPIO_EXTIPSELH */ #define GPIO_EXTIPSELH_EXTIPSEL12_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL12_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ #define GPIO_EXTIPSELH_EXTIPSEL12_PORTA (_GPIO_EXTIPSELH_EXTIPSEL12_PORTA << 16) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ #define GPIO_EXTIPSELH_EXTIPSEL12_PORTB (_GPIO_EXTIPSELH_EXTIPSEL12_PORTB << 16) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ #define GPIO_EXTIPSELH_EXTIPSEL12_PORTC (_GPIO_EXTIPSELH_EXTIPSEL12_PORTC << 16) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ #define GPIO_EXTIPSELH_EXTIPSEL12_PORTD (_GPIO_EXTIPSELH_EXTIPSEL12_PORTD << 16) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ #define GPIO_EXTIPSELH_EXTIPSEL12_PORTF (_GPIO_EXTIPSELH_EXTIPSEL12_PORTF << 16) /**< Shifted mode PORTF for GPIO_EXTIPSELH */ #define GPIO_EXTIPSELH_EXTIPSEL12_PORTI (_GPIO_EXTIPSELH_EXTIPSEL12_PORTI << 16) /**< Shifted mode PORTI for GPIO_EXTIPSELH */ #define GPIO_EXTIPSELH_EXTIPSEL12_PORTJ (_GPIO_EXTIPSELH_EXTIPSEL12_PORTJ << 16) /**< Shifted mode PORTJ for GPIO_EXTIPSELH */ #define GPIO_EXTIPSELH_EXTIPSEL12_PORTK (_GPIO_EXTIPSELH_EXTIPSEL12_PORTK << 16) /**< Shifted mode PORTK for GPIO_EXTIPSELH */ #define _GPIO_EXTIPSELH_EXTIPSEL13_SHIFT 20 /**< Shift value for GPIO_EXTIPSEL13 */ #define _GPIO_EXTIPSELH_EXTIPSEL13_MASK 0xF00000UL /**< Bit mask for GPIO_EXTIPSEL13 */ #define _GPIO_EXTIPSELH_EXTIPSEL13_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ #define _GPIO_EXTIPSELH_EXTIPSEL13_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ #define _GPIO_EXTIPSELH_EXTIPSEL13_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ #define _GPIO_EXTIPSELH_EXTIPSEL13_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ #define _GPIO_EXTIPSELH_EXTIPSEL13_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ #define _GPIO_EXTIPSELH_EXTIPSEL13_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELH */ #define _GPIO_EXTIPSELH_EXTIPSEL13_PORTI 0x00000008UL /**< Mode PORTI for GPIO_EXTIPSELH */ #define _GPIO_EXTIPSELH_EXTIPSEL13_PORTJ 0x00000009UL /**< Mode PORTJ for GPIO_EXTIPSELH */ #define _GPIO_EXTIPSELH_EXTIPSEL13_PORTK 0x0000000AUL /**< Mode PORTK for GPIO_EXTIPSELH */ #define GPIO_EXTIPSELH_EXTIPSEL13_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL13_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ #define GPIO_EXTIPSELH_EXTIPSEL13_PORTA (_GPIO_EXTIPSELH_EXTIPSEL13_PORTA << 20) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ #define GPIO_EXTIPSELH_EXTIPSEL13_PORTB (_GPIO_EXTIPSELH_EXTIPSEL13_PORTB << 20) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ #define GPIO_EXTIPSELH_EXTIPSEL13_PORTC (_GPIO_EXTIPSELH_EXTIPSEL13_PORTC << 20) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ #define GPIO_EXTIPSELH_EXTIPSEL13_PORTD (_GPIO_EXTIPSELH_EXTIPSEL13_PORTD << 20) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ #define GPIO_EXTIPSELH_EXTIPSEL13_PORTF (_GPIO_EXTIPSELH_EXTIPSEL13_PORTF << 20) /**< Shifted mode PORTF for GPIO_EXTIPSELH */ #define GPIO_EXTIPSELH_EXTIPSEL13_PORTI (_GPIO_EXTIPSELH_EXTIPSEL13_PORTI << 20) /**< Shifted mode PORTI for GPIO_EXTIPSELH */ #define GPIO_EXTIPSELH_EXTIPSEL13_PORTJ (_GPIO_EXTIPSELH_EXTIPSEL13_PORTJ << 20) /**< Shifted mode PORTJ for GPIO_EXTIPSELH */ #define GPIO_EXTIPSELH_EXTIPSEL13_PORTK (_GPIO_EXTIPSELH_EXTIPSEL13_PORTK << 20) /**< Shifted mode PORTK for GPIO_EXTIPSELH */ #define _GPIO_EXTIPSELH_EXTIPSEL14_SHIFT 24 /**< Shift value for GPIO_EXTIPSEL14 */ #define _GPIO_EXTIPSELH_EXTIPSEL14_MASK 0xF000000UL /**< Bit mask for GPIO_EXTIPSEL14 */ #define _GPIO_EXTIPSELH_EXTIPSEL14_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ #define _GPIO_EXTIPSELH_EXTIPSEL14_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ #define _GPIO_EXTIPSELH_EXTIPSEL14_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ #define _GPIO_EXTIPSELH_EXTIPSEL14_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ #define _GPIO_EXTIPSELH_EXTIPSEL14_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ #define _GPIO_EXTIPSELH_EXTIPSEL14_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELH */ #define _GPIO_EXTIPSELH_EXTIPSEL14_PORTI 0x00000008UL /**< Mode PORTI for GPIO_EXTIPSELH */ #define _GPIO_EXTIPSELH_EXTIPSEL14_PORTJ 0x00000009UL /**< Mode PORTJ for GPIO_EXTIPSELH */ #define _GPIO_EXTIPSELH_EXTIPSEL14_PORTK 0x0000000AUL /**< Mode PORTK for GPIO_EXTIPSELH */ #define GPIO_EXTIPSELH_EXTIPSEL14_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL14_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ #define GPIO_EXTIPSELH_EXTIPSEL14_PORTA (_GPIO_EXTIPSELH_EXTIPSEL14_PORTA << 24) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ #define GPIO_EXTIPSELH_EXTIPSEL14_PORTB (_GPIO_EXTIPSELH_EXTIPSEL14_PORTB << 24) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ #define GPIO_EXTIPSELH_EXTIPSEL14_PORTC (_GPIO_EXTIPSELH_EXTIPSEL14_PORTC << 24) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ #define GPIO_EXTIPSELH_EXTIPSEL14_PORTD (_GPIO_EXTIPSELH_EXTIPSEL14_PORTD << 24) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ #define GPIO_EXTIPSELH_EXTIPSEL14_PORTF (_GPIO_EXTIPSELH_EXTIPSEL14_PORTF << 24) /**< Shifted mode PORTF for GPIO_EXTIPSELH */ #define GPIO_EXTIPSELH_EXTIPSEL14_PORTI (_GPIO_EXTIPSELH_EXTIPSEL14_PORTI << 24) /**< Shifted mode PORTI for GPIO_EXTIPSELH */ #define GPIO_EXTIPSELH_EXTIPSEL14_PORTJ (_GPIO_EXTIPSELH_EXTIPSEL14_PORTJ << 24) /**< Shifted mode PORTJ for GPIO_EXTIPSELH */ #define GPIO_EXTIPSELH_EXTIPSEL14_PORTK (_GPIO_EXTIPSELH_EXTIPSEL14_PORTK << 24) /**< Shifted mode PORTK for GPIO_EXTIPSELH */ #define _GPIO_EXTIPSELH_EXTIPSEL15_SHIFT 28 /**< Shift value for GPIO_EXTIPSEL15 */ #define _GPIO_EXTIPSELH_EXTIPSEL15_MASK 0xF0000000UL /**< Bit mask for GPIO_EXTIPSEL15 */ #define _GPIO_EXTIPSELH_EXTIPSEL15_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ #define _GPIO_EXTIPSELH_EXTIPSEL15_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ #define _GPIO_EXTIPSELH_EXTIPSEL15_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ #define _GPIO_EXTIPSELH_EXTIPSEL15_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ #define _GPIO_EXTIPSELH_EXTIPSEL15_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ #define _GPIO_EXTIPSELH_EXTIPSEL15_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELH */ #define _GPIO_EXTIPSELH_EXTIPSEL15_PORTI 0x00000008UL /**< Mode PORTI for GPIO_EXTIPSELH */ #define _GPIO_EXTIPSELH_EXTIPSEL15_PORTJ 0x00000009UL /**< Mode PORTJ for GPIO_EXTIPSELH */ #define _GPIO_EXTIPSELH_EXTIPSEL15_PORTK 0x0000000AUL /**< Mode PORTK for GPIO_EXTIPSELH */ #define GPIO_EXTIPSELH_EXTIPSEL15_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL15_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ #define GPIO_EXTIPSELH_EXTIPSEL15_PORTA (_GPIO_EXTIPSELH_EXTIPSEL15_PORTA << 28) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ #define GPIO_EXTIPSELH_EXTIPSEL15_PORTB (_GPIO_EXTIPSELH_EXTIPSEL15_PORTB << 28) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ #define GPIO_EXTIPSELH_EXTIPSEL15_PORTC (_GPIO_EXTIPSELH_EXTIPSEL15_PORTC << 28) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ #define GPIO_EXTIPSELH_EXTIPSEL15_PORTD (_GPIO_EXTIPSELH_EXTIPSEL15_PORTD << 28) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ #define GPIO_EXTIPSELH_EXTIPSEL15_PORTF (_GPIO_EXTIPSELH_EXTIPSEL15_PORTF << 28) /**< Shifted mode PORTF for GPIO_EXTIPSELH */ #define GPIO_EXTIPSELH_EXTIPSEL15_PORTI (_GPIO_EXTIPSELH_EXTIPSEL15_PORTI << 28) /**< Shifted mode PORTI for GPIO_EXTIPSELH */ #define GPIO_EXTIPSELH_EXTIPSEL15_PORTJ (_GPIO_EXTIPSELH_EXTIPSEL15_PORTJ << 28) /**< Shifted mode PORTJ for GPIO_EXTIPSELH */ #define GPIO_EXTIPSELH_EXTIPSEL15_PORTK (_GPIO_EXTIPSELH_EXTIPSEL15_PORTK << 28) /**< Shifted mode PORTK for GPIO_EXTIPSELH */ /* Bit fields for GPIO EXTIPINSELL */ #define _GPIO_EXTIPINSELL_RESETVALUE 0x32103210UL /**< Default value for GPIO_EXTIPINSELL */ #define _GPIO_EXTIPINSELL_MASK 0x33333333UL /**< Mask for GPIO_EXTIPINSELL */ #define _GPIO_EXTIPINSELL_EXTIPINSEL0_SHIFT 0 /**< Shift value for GPIO_EXTIPINSEL0 */ #define _GPIO_EXTIPINSELL_EXTIPINSEL0_MASK 0x3UL /**< Bit mask for GPIO_EXTIPINSEL0 */ #define _GPIO_EXTIPINSELL_EXTIPINSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ #define _GPIO_EXTIPINSELL_EXTIPINSEL0_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ #define _GPIO_EXTIPINSELL_EXTIPINSEL0_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ #define _GPIO_EXTIPINSELL_EXTIPINSEL0_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ #define _GPIO_EXTIPINSELL_EXTIPINSEL0_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ #define GPIO_EXTIPINSELL_EXTIPINSEL0_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ #define GPIO_EXTIPINSELL_EXTIPINSEL0_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL0_PIN0 << 0) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ #define GPIO_EXTIPINSELL_EXTIPINSEL0_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL0_PIN1 << 0) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ #define GPIO_EXTIPINSELL_EXTIPINSEL0_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL0_PIN2 << 0) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ #define GPIO_EXTIPINSELL_EXTIPINSEL0_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL0_PIN3 << 0) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ #define _GPIO_EXTIPINSELL_EXTIPINSEL1_SHIFT 4 /**< Shift value for GPIO_EXTIPINSEL1 */ #define _GPIO_EXTIPINSELL_EXTIPINSEL1_MASK 0x30UL /**< Bit mask for GPIO_EXTIPINSEL1 */ #define _GPIO_EXTIPINSELL_EXTIPINSEL1_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ #define _GPIO_EXTIPINSELL_EXTIPINSEL1_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ #define _GPIO_EXTIPINSELL_EXTIPINSEL1_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ #define _GPIO_EXTIPINSELL_EXTIPINSEL1_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ #define _GPIO_EXTIPINSELL_EXTIPINSEL1_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ #define GPIO_EXTIPINSELL_EXTIPINSEL1_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL1_PIN0 << 4) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ #define GPIO_EXTIPINSELL_EXTIPINSEL1_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ #define GPIO_EXTIPINSELL_EXTIPINSEL1_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL1_PIN1 << 4) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ #define GPIO_EXTIPINSELL_EXTIPINSEL1_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL1_PIN2 << 4) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ #define GPIO_EXTIPINSELL_EXTIPINSEL1_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL1_PIN3 << 4) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ #define _GPIO_EXTIPINSELL_EXTIPINSEL2_SHIFT 8 /**< Shift value for GPIO_EXTIPINSEL2 */ #define _GPIO_EXTIPINSELL_EXTIPINSEL2_MASK 0x300UL /**< Bit mask for GPIO_EXTIPINSEL2 */ #define _GPIO_EXTIPINSELL_EXTIPINSEL2_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ #define _GPIO_EXTIPINSELL_EXTIPINSEL2_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ #define _GPIO_EXTIPINSELL_EXTIPINSEL2_DEFAULT 0x00000002UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ #define _GPIO_EXTIPINSELL_EXTIPINSEL2_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ #define _GPIO_EXTIPINSELL_EXTIPINSEL2_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ #define GPIO_EXTIPINSELL_EXTIPINSEL2_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL2_PIN0 << 8) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ #define GPIO_EXTIPINSELL_EXTIPINSEL2_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL2_PIN1 << 8) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ #define GPIO_EXTIPINSELL_EXTIPINSEL2_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL2_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ #define GPIO_EXTIPINSELL_EXTIPINSEL2_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL2_PIN2 << 8) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ #define GPIO_EXTIPINSELL_EXTIPINSEL2_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL2_PIN3 << 8) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ #define _GPIO_EXTIPINSELL_EXTIPINSEL3_SHIFT 12 /**< Shift value for GPIO_EXTIPINSEL3 */ #define _GPIO_EXTIPINSELL_EXTIPINSEL3_MASK 0x3000UL /**< Bit mask for GPIO_EXTIPINSEL3 */ #define _GPIO_EXTIPINSELL_EXTIPINSEL3_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ #define _GPIO_EXTIPINSELL_EXTIPINSEL3_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ #define _GPIO_EXTIPINSELL_EXTIPINSEL3_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ #define _GPIO_EXTIPINSELL_EXTIPINSEL3_DEFAULT 0x00000003UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ #define _GPIO_EXTIPINSELL_EXTIPINSEL3_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ #define GPIO_EXTIPINSELL_EXTIPINSEL3_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL3_PIN0 << 12) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ #define GPIO_EXTIPINSELL_EXTIPINSEL3_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL3_PIN1 << 12) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ #define GPIO_EXTIPINSELL_EXTIPINSEL3_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL3_PIN2 << 12) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ #define GPIO_EXTIPINSELL_EXTIPINSEL3_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL3_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ #define GPIO_EXTIPINSELL_EXTIPINSEL3_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL3_PIN3 << 12) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ #define _GPIO_EXTIPINSELL_EXTIPINSEL4_SHIFT 16 /**< Shift value for GPIO_EXTIPINSEL4 */ #define _GPIO_EXTIPINSELL_EXTIPINSEL4_MASK 0x30000UL /**< Bit mask for GPIO_EXTIPINSEL4 */ #define _GPIO_EXTIPINSELL_EXTIPINSEL4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ #define _GPIO_EXTIPINSELL_EXTIPINSEL4_PIN4 0x00000000UL /**< Mode PIN4 for GPIO_EXTIPINSELL */ #define _GPIO_EXTIPINSELL_EXTIPINSEL4_PIN5 0x00000001UL /**< Mode PIN5 for GPIO_EXTIPINSELL */ #define _GPIO_EXTIPINSELL_EXTIPINSEL4_PIN6 0x00000002UL /**< Mode PIN6 for GPIO_EXTIPINSELL */ #define _GPIO_EXTIPINSELL_EXTIPINSEL4_PIN7 0x00000003UL /**< Mode PIN7 for GPIO_EXTIPINSELL */ #define GPIO_EXTIPINSELL_EXTIPINSEL4_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL4_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ #define GPIO_EXTIPINSELL_EXTIPINSEL4_PIN4 (_GPIO_EXTIPINSELL_EXTIPINSEL4_PIN4 << 16) /**< Shifted mode PIN4 for GPIO_EXTIPINSELL */ #define GPIO_EXTIPINSELL_EXTIPINSEL4_PIN5 (_GPIO_EXTIPINSELL_EXTIPINSEL4_PIN5 << 16) /**< Shifted mode PIN5 for GPIO_EXTIPINSELL */ #define GPIO_EXTIPINSELL_EXTIPINSEL4_PIN6 (_GPIO_EXTIPINSELL_EXTIPINSEL4_PIN6 << 16) /**< Shifted mode PIN6 for GPIO_EXTIPINSELL */ #define GPIO_EXTIPINSELL_EXTIPINSEL4_PIN7 (_GPIO_EXTIPINSELL_EXTIPINSEL4_PIN7 << 16) /**< Shifted mode PIN7 for GPIO_EXTIPINSELL */ #define _GPIO_EXTIPINSELL_EXTIPINSEL5_SHIFT 20 /**< Shift value for GPIO_EXTIPINSEL5 */ #define _GPIO_EXTIPINSELL_EXTIPINSEL5_MASK 0x300000UL /**< Bit mask for GPIO_EXTIPINSEL5 */ #define _GPIO_EXTIPINSELL_EXTIPINSEL5_PIN4 0x00000000UL /**< Mode PIN4 for GPIO_EXTIPINSELL */ #define _GPIO_EXTIPINSELL_EXTIPINSEL5_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ #define _GPIO_EXTIPINSELL_EXTIPINSEL5_PIN5 0x00000001UL /**< Mode PIN5 for GPIO_EXTIPINSELL */ #define _GPIO_EXTIPINSELL_EXTIPINSEL5_PIN6 0x00000002UL /**< Mode PIN6 for GPIO_EXTIPINSELL */ #define _GPIO_EXTIPINSELL_EXTIPINSEL5_PIN7 0x00000003UL /**< Mode PIN7 for GPIO_EXTIPINSELL */ #define GPIO_EXTIPINSELL_EXTIPINSEL5_PIN4 (_GPIO_EXTIPINSELL_EXTIPINSEL5_PIN4 << 20) /**< Shifted mode PIN4 for GPIO_EXTIPINSELL */ #define GPIO_EXTIPINSELL_EXTIPINSEL5_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL5_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ #define GPIO_EXTIPINSELL_EXTIPINSEL5_PIN5 (_GPIO_EXTIPINSELL_EXTIPINSEL5_PIN5 << 20) /**< Shifted mode PIN5 for GPIO_EXTIPINSELL */ #define GPIO_EXTIPINSELL_EXTIPINSEL5_PIN6 (_GPIO_EXTIPINSELL_EXTIPINSEL5_PIN6 << 20) /**< Shifted mode PIN6 for GPIO_EXTIPINSELL */ #define GPIO_EXTIPINSELL_EXTIPINSEL5_PIN7 (_GPIO_EXTIPINSELL_EXTIPINSEL5_PIN7 << 20) /**< Shifted mode PIN7 for GPIO_EXTIPINSELL */ #define _GPIO_EXTIPINSELL_EXTIPINSEL6_SHIFT 24 /**< Shift value for GPIO_EXTIPINSEL6 */ #define _GPIO_EXTIPINSELL_EXTIPINSEL6_MASK 0x3000000UL /**< Bit mask for GPIO_EXTIPINSEL6 */ #define _GPIO_EXTIPINSELL_EXTIPINSEL6_PIN4 0x00000000UL /**< Mode PIN4 for GPIO_EXTIPINSELL */ #define _GPIO_EXTIPINSELL_EXTIPINSEL6_PIN5 0x00000001UL /**< Mode PIN5 for GPIO_EXTIPINSELL */ #define _GPIO_EXTIPINSELL_EXTIPINSEL6_DEFAULT 0x00000002UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ #define _GPIO_EXTIPINSELL_EXTIPINSEL6_PIN6 0x00000002UL /**< Mode PIN6 for GPIO_EXTIPINSELL */ #define _GPIO_EXTIPINSELL_EXTIPINSEL6_PIN7 0x00000003UL /**< Mode PIN7 for GPIO_EXTIPINSELL */ #define GPIO_EXTIPINSELL_EXTIPINSEL6_PIN4 (_GPIO_EXTIPINSELL_EXTIPINSEL6_PIN4 << 24) /**< Shifted mode PIN4 for GPIO_EXTIPINSELL */ #define GPIO_EXTIPINSELL_EXTIPINSEL6_PIN5 (_GPIO_EXTIPINSELL_EXTIPINSEL6_PIN5 << 24) /**< Shifted mode PIN5 for GPIO_EXTIPINSELL */ #define GPIO_EXTIPINSELL_EXTIPINSEL6_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL6_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ #define GPIO_EXTIPINSELL_EXTIPINSEL6_PIN6 (_GPIO_EXTIPINSELL_EXTIPINSEL6_PIN6 << 24) /**< Shifted mode PIN6 for GPIO_EXTIPINSELL */ #define GPIO_EXTIPINSELL_EXTIPINSEL6_PIN7 (_GPIO_EXTIPINSELL_EXTIPINSEL6_PIN7 << 24) /**< Shifted mode PIN7 for GPIO_EXTIPINSELL */ #define _GPIO_EXTIPINSELL_EXTIPINSEL7_SHIFT 28 /**< Shift value for GPIO_EXTIPINSEL7 */ #define _GPIO_EXTIPINSELL_EXTIPINSEL7_MASK 0x30000000UL /**< Bit mask for GPIO_EXTIPINSEL7 */ #define _GPIO_EXTIPINSELL_EXTIPINSEL7_PIN4 0x00000000UL /**< Mode PIN4 for GPIO_EXTIPINSELL */ #define _GPIO_EXTIPINSELL_EXTIPINSEL7_PIN5 0x00000001UL /**< Mode PIN5 for GPIO_EXTIPINSELL */ #define _GPIO_EXTIPINSELL_EXTIPINSEL7_PIN6 0x00000002UL /**< Mode PIN6 for GPIO_EXTIPINSELL */ #define _GPIO_EXTIPINSELL_EXTIPINSEL7_DEFAULT 0x00000003UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ #define _GPIO_EXTIPINSELL_EXTIPINSEL7_PIN7 0x00000003UL /**< Mode PIN7 for GPIO_EXTIPINSELL */ #define GPIO_EXTIPINSELL_EXTIPINSEL7_PIN4 (_GPIO_EXTIPINSELL_EXTIPINSEL7_PIN4 << 28) /**< Shifted mode PIN4 for GPIO_EXTIPINSELL */ #define GPIO_EXTIPINSELL_EXTIPINSEL7_PIN5 (_GPIO_EXTIPINSELL_EXTIPINSEL7_PIN5 << 28) /**< Shifted mode PIN5 for GPIO_EXTIPINSELL */ #define GPIO_EXTIPINSELL_EXTIPINSEL7_PIN6 (_GPIO_EXTIPINSELL_EXTIPINSEL7_PIN6 << 28) /**< Shifted mode PIN6 for GPIO_EXTIPINSELL */ #define GPIO_EXTIPINSELL_EXTIPINSEL7_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL7_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ #define GPIO_EXTIPINSELL_EXTIPINSEL7_PIN7 (_GPIO_EXTIPINSELL_EXTIPINSEL7_PIN7 << 28) /**< Shifted mode PIN7 for GPIO_EXTIPINSELL */ /* Bit fields for GPIO EXTIPINSELH */ #define _GPIO_EXTIPINSELH_RESETVALUE 0x32103210UL /**< Default value for GPIO_EXTIPINSELH */ #define _GPIO_EXTIPINSELH_MASK 0x33333333UL /**< Mask for GPIO_EXTIPINSELH */ #define _GPIO_EXTIPINSELH_EXTIPINSEL8_SHIFT 0 /**< Shift value for GPIO_EXTIPINSEL8 */ #define _GPIO_EXTIPINSELH_EXTIPINSEL8_MASK 0x3UL /**< Bit mask for GPIO_EXTIPINSEL8 */ #define _GPIO_EXTIPINSELH_EXTIPINSEL8_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ #define _GPIO_EXTIPINSELH_EXTIPINSEL8_PIN8 0x00000000UL /**< Mode PIN8 for GPIO_EXTIPINSELH */ #define _GPIO_EXTIPINSELH_EXTIPINSEL8_PIN9 0x00000001UL /**< Mode PIN9 for GPIO_EXTIPINSELH */ #define _GPIO_EXTIPINSELH_EXTIPINSEL8_PIN10 0x00000002UL /**< Mode PIN10 for GPIO_EXTIPINSELH */ #define _GPIO_EXTIPINSELH_EXTIPINSEL8_PIN11 0x00000003UL /**< Mode PIN11 for GPIO_EXTIPINSELH */ #define GPIO_EXTIPINSELH_EXTIPINSEL8_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL8_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ #define GPIO_EXTIPINSELH_EXTIPINSEL8_PIN8 (_GPIO_EXTIPINSELH_EXTIPINSEL8_PIN8 << 0) /**< Shifted mode PIN8 for GPIO_EXTIPINSELH */ #define GPIO_EXTIPINSELH_EXTIPINSEL8_PIN9 (_GPIO_EXTIPINSELH_EXTIPINSEL8_PIN9 << 0) /**< Shifted mode PIN9 for GPIO_EXTIPINSELH */ #define GPIO_EXTIPINSELH_EXTIPINSEL8_PIN10 (_GPIO_EXTIPINSELH_EXTIPINSEL8_PIN10 << 0) /**< Shifted mode PIN10 for GPIO_EXTIPINSELH */ #define GPIO_EXTIPINSELH_EXTIPINSEL8_PIN11 (_GPIO_EXTIPINSELH_EXTIPINSEL8_PIN11 << 0) /**< Shifted mode PIN11 for GPIO_EXTIPINSELH */ #define _GPIO_EXTIPINSELH_EXTIPINSEL9_SHIFT 4 /**< Shift value for GPIO_EXTIPINSEL9 */ #define _GPIO_EXTIPINSELH_EXTIPINSEL9_MASK 0x30UL /**< Bit mask for GPIO_EXTIPINSEL9 */ #define _GPIO_EXTIPINSELH_EXTIPINSEL9_PIN8 0x00000000UL /**< Mode PIN8 for GPIO_EXTIPINSELH */ #define _GPIO_EXTIPINSELH_EXTIPINSEL9_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ #define _GPIO_EXTIPINSELH_EXTIPINSEL9_PIN9 0x00000001UL /**< Mode PIN9 for GPIO_EXTIPINSELH */ #define _GPIO_EXTIPINSELH_EXTIPINSEL9_PIN10 0x00000002UL /**< Mode PIN10 for GPIO_EXTIPINSELH */ #define _GPIO_EXTIPINSELH_EXTIPINSEL9_PIN11 0x00000003UL /**< Mode PIN11 for GPIO_EXTIPINSELH */ #define GPIO_EXTIPINSELH_EXTIPINSEL9_PIN8 (_GPIO_EXTIPINSELH_EXTIPINSEL9_PIN8 << 4) /**< Shifted mode PIN8 for GPIO_EXTIPINSELH */ #define GPIO_EXTIPINSELH_EXTIPINSEL9_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL9_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ #define GPIO_EXTIPINSELH_EXTIPINSEL9_PIN9 (_GPIO_EXTIPINSELH_EXTIPINSEL9_PIN9 << 4) /**< Shifted mode PIN9 for GPIO_EXTIPINSELH */ #define GPIO_EXTIPINSELH_EXTIPINSEL9_PIN10 (_GPIO_EXTIPINSELH_EXTIPINSEL9_PIN10 << 4) /**< Shifted mode PIN10 for GPIO_EXTIPINSELH */ #define GPIO_EXTIPINSELH_EXTIPINSEL9_PIN11 (_GPIO_EXTIPINSELH_EXTIPINSEL9_PIN11 << 4) /**< Shifted mode PIN11 for GPIO_EXTIPINSELH */ #define _GPIO_EXTIPINSELH_EXTIPINSEL10_SHIFT 8 /**< Shift value for GPIO_EXTIPINSEL10 */ #define _GPIO_EXTIPINSELH_EXTIPINSEL10_MASK 0x300UL /**< Bit mask for GPIO_EXTIPINSEL10 */ #define _GPIO_EXTIPINSELH_EXTIPINSEL10_PIN8 0x00000000UL /**< Mode PIN8 for GPIO_EXTIPINSELH */ #define _GPIO_EXTIPINSELH_EXTIPINSEL10_PIN9 0x00000001UL /**< Mode PIN9 for GPIO_EXTIPINSELH */ #define _GPIO_EXTIPINSELH_EXTIPINSEL10_DEFAULT 0x00000002UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ #define _GPIO_EXTIPINSELH_EXTIPINSEL10_PIN10 0x00000002UL /**< Mode PIN10 for GPIO_EXTIPINSELH */ #define _GPIO_EXTIPINSELH_EXTIPINSEL10_PIN11 0x00000003UL /**< Mode PIN11 for GPIO_EXTIPINSELH */ #define GPIO_EXTIPINSELH_EXTIPINSEL10_PIN8 (_GPIO_EXTIPINSELH_EXTIPINSEL10_PIN8 << 8) /**< Shifted mode PIN8 for GPIO_EXTIPINSELH */ #define GPIO_EXTIPINSELH_EXTIPINSEL10_PIN9 (_GPIO_EXTIPINSELH_EXTIPINSEL10_PIN9 << 8) /**< Shifted mode PIN9 for GPIO_EXTIPINSELH */ #define GPIO_EXTIPINSELH_EXTIPINSEL10_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL10_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ #define GPIO_EXTIPINSELH_EXTIPINSEL10_PIN10 (_GPIO_EXTIPINSELH_EXTIPINSEL10_PIN10 << 8) /**< Shifted mode PIN10 for GPIO_EXTIPINSELH */ #define GPIO_EXTIPINSELH_EXTIPINSEL10_PIN11 (_GPIO_EXTIPINSELH_EXTIPINSEL10_PIN11 << 8) /**< Shifted mode PIN11 for GPIO_EXTIPINSELH */ #define _GPIO_EXTIPINSELH_EXTIPINSEL11_SHIFT 12 /**< Shift value for GPIO_EXTIPINSEL11 */ #define _GPIO_EXTIPINSELH_EXTIPINSEL11_MASK 0x3000UL /**< Bit mask for GPIO_EXTIPINSEL11 */ #define _GPIO_EXTIPINSELH_EXTIPINSEL11_PIN8 0x00000000UL /**< Mode PIN8 for GPIO_EXTIPINSELH */ #define _GPIO_EXTIPINSELH_EXTIPINSEL11_PIN9 0x00000001UL /**< Mode PIN9 for GPIO_EXTIPINSELH */ #define _GPIO_EXTIPINSELH_EXTIPINSEL11_PIN10 0x00000002UL /**< Mode PIN10 for GPIO_EXTIPINSELH */ #define _GPIO_EXTIPINSELH_EXTIPINSEL11_DEFAULT 0x00000003UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ #define _GPIO_EXTIPINSELH_EXTIPINSEL11_PIN11 0x00000003UL /**< Mode PIN11 for GPIO_EXTIPINSELH */ #define GPIO_EXTIPINSELH_EXTIPINSEL11_PIN8 (_GPIO_EXTIPINSELH_EXTIPINSEL11_PIN8 << 12) /**< Shifted mode PIN8 for GPIO_EXTIPINSELH */ #define GPIO_EXTIPINSELH_EXTIPINSEL11_PIN9 (_GPIO_EXTIPINSELH_EXTIPINSEL11_PIN9 << 12) /**< Shifted mode PIN9 for GPIO_EXTIPINSELH */ #define GPIO_EXTIPINSELH_EXTIPINSEL11_PIN10 (_GPIO_EXTIPINSELH_EXTIPINSEL11_PIN10 << 12) /**< Shifted mode PIN10 for GPIO_EXTIPINSELH */ #define GPIO_EXTIPINSELH_EXTIPINSEL11_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL11_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ #define GPIO_EXTIPINSELH_EXTIPINSEL11_PIN11 (_GPIO_EXTIPINSELH_EXTIPINSEL11_PIN11 << 12) /**< Shifted mode PIN11 for GPIO_EXTIPINSELH */ #define _GPIO_EXTIPINSELH_EXTIPINSEL12_SHIFT 16 /**< Shift value for GPIO_EXTIPINSEL12 */ #define _GPIO_EXTIPINSELH_EXTIPINSEL12_MASK 0x30000UL /**< Bit mask for GPIO_EXTIPINSEL12 */ #define _GPIO_EXTIPINSELH_EXTIPINSEL12_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ #define _GPIO_EXTIPINSELH_EXTIPINSEL12_PIN12 0x00000000UL /**< Mode PIN12 for GPIO_EXTIPINSELH */ #define _GPIO_EXTIPINSELH_EXTIPINSEL12_PIN13 0x00000001UL /**< Mode PIN13 for GPIO_EXTIPINSELH */ #define _GPIO_EXTIPINSELH_EXTIPINSEL12_PIN14 0x00000002UL /**< Mode PIN14 for GPIO_EXTIPINSELH */ #define _GPIO_EXTIPINSELH_EXTIPINSEL12_PIN15 0x00000003UL /**< Mode PIN15 for GPIO_EXTIPINSELH */ #define GPIO_EXTIPINSELH_EXTIPINSEL12_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL12_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ #define GPIO_EXTIPINSELH_EXTIPINSEL12_PIN12 (_GPIO_EXTIPINSELH_EXTIPINSEL12_PIN12 << 16) /**< Shifted mode PIN12 for GPIO_EXTIPINSELH */ #define GPIO_EXTIPINSELH_EXTIPINSEL12_PIN13 (_GPIO_EXTIPINSELH_EXTIPINSEL12_PIN13 << 16) /**< Shifted mode PIN13 for GPIO_EXTIPINSELH */ #define GPIO_EXTIPINSELH_EXTIPINSEL12_PIN14 (_GPIO_EXTIPINSELH_EXTIPINSEL12_PIN14 << 16) /**< Shifted mode PIN14 for GPIO_EXTIPINSELH */ #define GPIO_EXTIPINSELH_EXTIPINSEL12_PIN15 (_GPIO_EXTIPINSELH_EXTIPINSEL12_PIN15 << 16) /**< Shifted mode PIN15 for GPIO_EXTIPINSELH */ #define _GPIO_EXTIPINSELH_EXTIPINSEL13_SHIFT 20 /**< Shift value for GPIO_EXTIPINSEL13 */ #define _GPIO_EXTIPINSELH_EXTIPINSEL13_MASK 0x300000UL /**< Bit mask for GPIO_EXTIPINSEL13 */ #define _GPIO_EXTIPINSELH_EXTIPINSEL13_PIN12 0x00000000UL /**< Mode PIN12 for GPIO_EXTIPINSELH */ #define _GPIO_EXTIPINSELH_EXTIPINSEL13_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ #define _GPIO_EXTIPINSELH_EXTIPINSEL13_PIN13 0x00000001UL /**< Mode PIN13 for GPIO_EXTIPINSELH */ #define _GPIO_EXTIPINSELH_EXTIPINSEL13_PIN14 0x00000002UL /**< Mode PIN14 for GPIO_EXTIPINSELH */ #define _GPIO_EXTIPINSELH_EXTIPINSEL13_PIN15 0x00000003UL /**< Mode PIN15 for GPIO_EXTIPINSELH */ #define GPIO_EXTIPINSELH_EXTIPINSEL13_PIN12 (_GPIO_EXTIPINSELH_EXTIPINSEL13_PIN12 << 20) /**< Shifted mode PIN12 for GPIO_EXTIPINSELH */ #define GPIO_EXTIPINSELH_EXTIPINSEL13_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL13_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ #define GPIO_EXTIPINSELH_EXTIPINSEL13_PIN13 (_GPIO_EXTIPINSELH_EXTIPINSEL13_PIN13 << 20) /**< Shifted mode PIN13 for GPIO_EXTIPINSELH */ #define GPIO_EXTIPINSELH_EXTIPINSEL13_PIN14 (_GPIO_EXTIPINSELH_EXTIPINSEL13_PIN14 << 20) /**< Shifted mode PIN14 for GPIO_EXTIPINSELH */ #define GPIO_EXTIPINSELH_EXTIPINSEL13_PIN15 (_GPIO_EXTIPINSELH_EXTIPINSEL13_PIN15 << 20) /**< Shifted mode PIN15 for GPIO_EXTIPINSELH */ #define _GPIO_EXTIPINSELH_EXTIPINSEL14_SHIFT 24 /**< Shift value for GPIO_EXTIPINSEL14 */ #define _GPIO_EXTIPINSELH_EXTIPINSEL14_MASK 0x3000000UL /**< Bit mask for GPIO_EXTIPINSEL14 */ #define _GPIO_EXTIPINSELH_EXTIPINSEL14_PIN12 0x00000000UL /**< Mode PIN12 for GPIO_EXTIPINSELH */ #define _GPIO_EXTIPINSELH_EXTIPINSEL14_PIN13 0x00000001UL /**< Mode PIN13 for GPIO_EXTIPINSELH */ #define _GPIO_EXTIPINSELH_EXTIPINSEL14_DEFAULT 0x00000002UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ #define _GPIO_EXTIPINSELH_EXTIPINSEL14_PIN14 0x00000002UL /**< Mode PIN14 for GPIO_EXTIPINSELH */ #define _GPIO_EXTIPINSELH_EXTIPINSEL14_PIN15 0x00000003UL /**< Mode PIN15 for GPIO_EXTIPINSELH */ #define GPIO_EXTIPINSELH_EXTIPINSEL14_PIN12 (_GPIO_EXTIPINSELH_EXTIPINSEL14_PIN12 << 24) /**< Shifted mode PIN12 for GPIO_EXTIPINSELH */ #define GPIO_EXTIPINSELH_EXTIPINSEL14_PIN13 (_GPIO_EXTIPINSELH_EXTIPINSEL14_PIN13 << 24) /**< Shifted mode PIN13 for GPIO_EXTIPINSELH */ #define GPIO_EXTIPINSELH_EXTIPINSEL14_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL14_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ #define GPIO_EXTIPINSELH_EXTIPINSEL14_PIN14 (_GPIO_EXTIPINSELH_EXTIPINSEL14_PIN14 << 24) /**< Shifted mode PIN14 for GPIO_EXTIPINSELH */ #define GPIO_EXTIPINSELH_EXTIPINSEL14_PIN15 (_GPIO_EXTIPINSELH_EXTIPINSEL14_PIN15 << 24) /**< Shifted mode PIN15 for GPIO_EXTIPINSELH */ #define _GPIO_EXTIPINSELH_EXTIPINSEL15_SHIFT 28 /**< Shift value for GPIO_EXTIPINSEL15 */ #define _GPIO_EXTIPINSELH_EXTIPINSEL15_MASK 0x30000000UL /**< Bit mask for GPIO_EXTIPINSEL15 */ #define _GPIO_EXTIPINSELH_EXTIPINSEL15_PIN12 0x00000000UL /**< Mode PIN12 for GPIO_EXTIPINSELH */ #define _GPIO_EXTIPINSELH_EXTIPINSEL15_PIN13 0x00000001UL /**< Mode PIN13 for GPIO_EXTIPINSELH */ #define _GPIO_EXTIPINSELH_EXTIPINSEL15_PIN14 0x00000002UL /**< Mode PIN14 for GPIO_EXTIPINSELH */ #define _GPIO_EXTIPINSELH_EXTIPINSEL15_DEFAULT 0x00000003UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ #define _GPIO_EXTIPINSELH_EXTIPINSEL15_PIN15 0x00000003UL /**< Mode PIN15 for GPIO_EXTIPINSELH */ #define GPIO_EXTIPINSELH_EXTIPINSEL15_PIN12 (_GPIO_EXTIPINSELH_EXTIPINSEL15_PIN12 << 28) /**< Shifted mode PIN12 for GPIO_EXTIPINSELH */ #define GPIO_EXTIPINSELH_EXTIPINSEL15_PIN13 (_GPIO_EXTIPINSELH_EXTIPINSEL15_PIN13 << 28) /**< Shifted mode PIN13 for GPIO_EXTIPINSELH */ #define GPIO_EXTIPINSELH_EXTIPINSEL15_PIN14 (_GPIO_EXTIPINSELH_EXTIPINSEL15_PIN14 << 28) /**< Shifted mode PIN14 for GPIO_EXTIPINSELH */ #define GPIO_EXTIPINSELH_EXTIPINSEL15_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL15_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ #define GPIO_EXTIPINSELH_EXTIPINSEL15_PIN15 (_GPIO_EXTIPINSELH_EXTIPINSEL15_PIN15 << 28) /**< Shifted mode PIN15 for GPIO_EXTIPINSELH */ /* Bit fields for GPIO EXTIRISE */ #define _GPIO_EXTIRISE_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIRISE */ #define _GPIO_EXTIRISE_MASK 0x0000FFFFUL /**< Mask for GPIO_EXTIRISE */ #define _GPIO_EXTIRISE_EXTIRISE_SHIFT 0 /**< Shift value for GPIO_EXTIRISE */ #define _GPIO_EXTIRISE_EXTIRISE_MASK 0xFFFFUL /**< Bit mask for GPIO_EXTIRISE */ #define _GPIO_EXTIRISE_EXTIRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIRISE */ #define GPIO_EXTIRISE_EXTIRISE_DEFAULT (_GPIO_EXTIRISE_EXTIRISE_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIRISE */ /* Bit fields for GPIO EXTIFALL */ #define _GPIO_EXTIFALL_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIFALL */ #define _GPIO_EXTIFALL_MASK 0x0000FFFFUL /**< Mask for GPIO_EXTIFALL */ #define _GPIO_EXTIFALL_EXTIFALL_SHIFT 0 /**< Shift value for GPIO_EXTIFALL */ #define _GPIO_EXTIFALL_EXTIFALL_MASK 0xFFFFUL /**< Bit mask for GPIO_EXTIFALL */ #define _GPIO_EXTIFALL_EXTIFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIFALL */ #define GPIO_EXTIFALL_EXTIFALL_DEFAULT (_GPIO_EXTIFALL_EXTIFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIFALL */ /* Bit fields for GPIO EXTILEVEL */ #define _GPIO_EXTILEVEL_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTILEVEL */ #define _GPIO_EXTILEVEL_MASK 0x13130000UL /**< Mask for GPIO_EXTILEVEL */ #define GPIO_EXTILEVEL_EM4WU0 (0x1UL << 16) /**< EM4 Wake Up Level for EM4WU0 Pin */ #define _GPIO_EXTILEVEL_EM4WU0_SHIFT 16 /**< Shift value for GPIO_EM4WU0 */ #define _GPIO_EXTILEVEL_EM4WU0_MASK 0x10000UL /**< Bit mask for GPIO_EM4WU0 */ #define _GPIO_EXTILEVEL_EM4WU0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTILEVEL */ #define GPIO_EXTILEVEL_EM4WU0_DEFAULT (_GPIO_EXTILEVEL_EM4WU0_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EXTILEVEL */ #define GPIO_EXTILEVEL_EM4WU1 (0x1UL << 17) /**< EM4 Wake Up Level for EM4WU1 Pin */ #define _GPIO_EXTILEVEL_EM4WU1_SHIFT 17 /**< Shift value for GPIO_EM4WU1 */ #define _GPIO_EXTILEVEL_EM4WU1_MASK 0x20000UL /**< Bit mask for GPIO_EM4WU1 */ #define _GPIO_EXTILEVEL_EM4WU1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTILEVEL */ #define GPIO_EXTILEVEL_EM4WU1_DEFAULT (_GPIO_EXTILEVEL_EM4WU1_DEFAULT << 17) /**< Shifted mode DEFAULT for GPIO_EXTILEVEL */ #define GPIO_EXTILEVEL_EM4WU4 (0x1UL << 20) /**< EM4 Wake Up Level for EM4WU4 Pin */ #define _GPIO_EXTILEVEL_EM4WU4_SHIFT 20 /**< Shift value for GPIO_EM4WU4 */ #define _GPIO_EXTILEVEL_EM4WU4_MASK 0x100000UL /**< Bit mask for GPIO_EM4WU4 */ #define _GPIO_EXTILEVEL_EM4WU4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTILEVEL */ #define GPIO_EXTILEVEL_EM4WU4_DEFAULT (_GPIO_EXTILEVEL_EM4WU4_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_EXTILEVEL */ #define GPIO_EXTILEVEL_EM4WU8 (0x1UL << 24) /**< EM4 Wake Up Level for EM4WU8 Pin */ #define _GPIO_EXTILEVEL_EM4WU8_SHIFT 24 /**< Shift value for GPIO_EM4WU8 */ #define _GPIO_EXTILEVEL_EM4WU8_MASK 0x1000000UL /**< Bit mask for GPIO_EM4WU8 */ #define _GPIO_EXTILEVEL_EM4WU8_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTILEVEL */ #define GPIO_EXTILEVEL_EM4WU8_DEFAULT (_GPIO_EXTILEVEL_EM4WU8_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_EXTILEVEL */ #define GPIO_EXTILEVEL_EM4WU9 (0x1UL << 25) /**< EM4 Wake Up Level for EM4WU9 Pin */ #define _GPIO_EXTILEVEL_EM4WU9_SHIFT 25 /**< Shift value for GPIO_EM4WU9 */ #define _GPIO_EXTILEVEL_EM4WU9_MASK 0x2000000UL /**< Bit mask for GPIO_EM4WU9 */ #define _GPIO_EXTILEVEL_EM4WU9_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTILEVEL */ #define GPIO_EXTILEVEL_EM4WU9_DEFAULT (_GPIO_EXTILEVEL_EM4WU9_DEFAULT << 25) /**< Shifted mode DEFAULT for GPIO_EXTILEVEL */ #define GPIO_EXTILEVEL_EM4WU12 (0x1UL << 28) /**< EM4 Wake Up Level for EM4WU12 Pin */ #define _GPIO_EXTILEVEL_EM4WU12_SHIFT 28 /**< Shift value for GPIO_EM4WU12 */ #define _GPIO_EXTILEVEL_EM4WU12_MASK 0x10000000UL /**< Bit mask for GPIO_EM4WU12 */ #define _GPIO_EXTILEVEL_EM4WU12_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTILEVEL */ #define GPIO_EXTILEVEL_EM4WU12_DEFAULT (_GPIO_EXTILEVEL_EM4WU12_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_EXTILEVEL */ /* Bit fields for GPIO IF */ #define _GPIO_IF_RESETVALUE 0x00000000UL /**< Default value for GPIO_IF */ #define _GPIO_IF_MASK 0xFFFFFFFFUL /**< Mask for GPIO_IF */ #define _GPIO_IF_EXT_SHIFT 0 /**< Shift value for GPIO_EXT */ #define _GPIO_IF_EXT_MASK 0xFFFFUL /**< Bit mask for GPIO_EXT */ #define _GPIO_IF_EXT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ #define GPIO_IF_EXT_DEFAULT (_GPIO_IF_EXT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_IF */ #define _GPIO_IF_EM4WU_SHIFT 16 /**< Shift value for GPIO_EM4WU */ #define _GPIO_IF_EM4WU_MASK 0xFFFF0000UL /**< Bit mask for GPIO_EM4WU */ #define _GPIO_IF_EM4WU_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ #define GPIO_IF_EM4WU_DEFAULT (_GPIO_IF_EM4WU_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_IF */ /* Bit fields for GPIO IFS */ #define _GPIO_IFS_RESETVALUE 0x00000000UL /**< Default value for GPIO_IFS */ #define _GPIO_IFS_MASK 0xFFFFFFFFUL /**< Mask for GPIO_IFS */ #define _GPIO_IFS_EXT_SHIFT 0 /**< Shift value for GPIO_EXT */ #define _GPIO_IFS_EXT_MASK 0xFFFFUL /**< Bit mask for GPIO_EXT */ #define _GPIO_IFS_EXT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IFS */ #define GPIO_IFS_EXT_DEFAULT (_GPIO_IFS_EXT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_IFS */ #define _GPIO_IFS_EM4WU_SHIFT 16 /**< Shift value for GPIO_EM4WU */ #define _GPIO_IFS_EM4WU_MASK 0xFFFF0000UL /**< Bit mask for GPIO_EM4WU */ #define _GPIO_IFS_EM4WU_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IFS */ #define GPIO_IFS_EM4WU_DEFAULT (_GPIO_IFS_EM4WU_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_IFS */ /* Bit fields for GPIO IFC */ #define _GPIO_IFC_RESETVALUE 0x00000000UL /**< Default value for GPIO_IFC */ #define _GPIO_IFC_MASK 0xFFFFFFFFUL /**< Mask for GPIO_IFC */ #define _GPIO_IFC_EXT_SHIFT 0 /**< Shift value for GPIO_EXT */ #define _GPIO_IFC_EXT_MASK 0xFFFFUL /**< Bit mask for GPIO_EXT */ #define _GPIO_IFC_EXT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IFC */ #define GPIO_IFC_EXT_DEFAULT (_GPIO_IFC_EXT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_IFC */ #define _GPIO_IFC_EM4WU_SHIFT 16 /**< Shift value for GPIO_EM4WU */ #define _GPIO_IFC_EM4WU_MASK 0xFFFF0000UL /**< Bit mask for GPIO_EM4WU */ #define _GPIO_IFC_EM4WU_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IFC */ #define GPIO_IFC_EM4WU_DEFAULT (_GPIO_IFC_EM4WU_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_IFC */ /* Bit fields for GPIO IEN */ #define _GPIO_IEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_IEN */ #define _GPIO_IEN_MASK 0xFFFFFFFFUL /**< Mask for GPIO_IEN */ #define _GPIO_IEN_EXT_SHIFT 0 /**< Shift value for GPIO_EXT */ #define _GPIO_IEN_EXT_MASK 0xFFFFUL /**< Bit mask for GPIO_EXT */ #define _GPIO_IEN_EXT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ #define GPIO_IEN_EXT_DEFAULT (_GPIO_IEN_EXT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_IEN */ #define _GPIO_IEN_EM4WU_SHIFT 16 /**< Shift value for GPIO_EM4WU */ #define _GPIO_IEN_EM4WU_MASK 0xFFFF0000UL /**< Bit mask for GPIO_EM4WU */ #define _GPIO_IEN_EM4WU_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ #define GPIO_IEN_EM4WU_DEFAULT (_GPIO_IEN_EM4WU_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_IEN */ /* Bit fields for GPIO EM4WUEN */ #define _GPIO_EM4WUEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_EM4WUEN */ #define _GPIO_EM4WUEN_MASK 0xFFFF0000UL /**< Mask for GPIO_EM4WUEN */ #define _GPIO_EM4WUEN_EM4WUEN_SHIFT 16 /**< Shift value for GPIO_EM4WUEN */ #define _GPIO_EM4WUEN_EM4WUEN_MASK 0xFFFF0000UL /**< Bit mask for GPIO_EM4WUEN */ #define _GPIO_EM4WUEN_EM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EM4WUEN */ #define GPIO_EM4WUEN_EM4WUEN_DEFAULT (_GPIO_EM4WUEN_EM4WUEN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EM4WUEN */ /* Bit fields for GPIO ROUTEPEN */ #define _GPIO_ROUTEPEN_RESETVALUE 0x0000000FUL /**< Default value for GPIO_ROUTEPEN */ #define _GPIO_ROUTEPEN_MASK 0x001F001FUL /**< Mask for GPIO_ROUTEPEN */ #define GPIO_ROUTEPEN_SWCLKTCKPEN (0x1UL << 0) /**< Serial Wire Clock and JTAG Test Clock Pin Enable */ #define _GPIO_ROUTEPEN_SWCLKTCKPEN_SHIFT 0 /**< Shift value for GPIO_SWCLKTCKPEN */ #define _GPIO_ROUTEPEN_SWCLKTCKPEN_MASK 0x1UL /**< Bit mask for GPIO_SWCLKTCKPEN */ #define _GPIO_ROUTEPEN_SWCLKTCKPEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_ROUTEPEN */ #define GPIO_ROUTEPEN_SWCLKTCKPEN_DEFAULT (_GPIO_ROUTEPEN_SWCLKTCKPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_ROUTEPEN */ #define GPIO_ROUTEPEN_SWDIOTMSPEN (0x1UL << 1) /**< Serial Wire Data and JTAG Test Mode Select Pin Enable */ #define _GPIO_ROUTEPEN_SWDIOTMSPEN_SHIFT 1 /**< Shift value for GPIO_SWDIOTMSPEN */ #define _GPIO_ROUTEPEN_SWDIOTMSPEN_MASK 0x2UL /**< Bit mask for GPIO_SWDIOTMSPEN */ #define _GPIO_ROUTEPEN_SWDIOTMSPEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_ROUTEPEN */ #define GPIO_ROUTEPEN_SWDIOTMSPEN_DEFAULT (_GPIO_ROUTEPEN_SWDIOTMSPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_ROUTEPEN */ #define GPIO_ROUTEPEN_TDOPEN (0x1UL << 2) /**< JTAG Test Debug Output Pin Enable */ #define _GPIO_ROUTEPEN_TDOPEN_SHIFT 2 /**< Shift value for GPIO_TDOPEN */ #define _GPIO_ROUTEPEN_TDOPEN_MASK 0x4UL /**< Bit mask for GPIO_TDOPEN */ #define _GPIO_ROUTEPEN_TDOPEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_ROUTEPEN */ #define GPIO_ROUTEPEN_TDOPEN_DEFAULT (_GPIO_ROUTEPEN_TDOPEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_ROUTEPEN */ #define GPIO_ROUTEPEN_TDIPEN (0x1UL << 3) /**< JTAG Test Debug Input Pin Enable */ #define _GPIO_ROUTEPEN_TDIPEN_SHIFT 3 /**< Shift value for GPIO_TDIPEN */ #define _GPIO_ROUTEPEN_TDIPEN_MASK 0x8UL /**< Bit mask for GPIO_TDIPEN */ #define _GPIO_ROUTEPEN_TDIPEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_ROUTEPEN */ #define GPIO_ROUTEPEN_TDIPEN_DEFAULT (_GPIO_ROUTEPEN_TDIPEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_ROUTEPEN */ #define GPIO_ROUTEPEN_SWVPEN (0x1UL << 4) /**< Serial Wire Viewer Output Pin Enable */ #define _GPIO_ROUTEPEN_SWVPEN_SHIFT 4 /**< Shift value for GPIO_SWVPEN */ #define _GPIO_ROUTEPEN_SWVPEN_MASK 0x10UL /**< Bit mask for GPIO_SWVPEN */ #define _GPIO_ROUTEPEN_SWVPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ROUTEPEN */ #define GPIO_ROUTEPEN_SWVPEN_DEFAULT (_GPIO_ROUTEPEN_SWVPEN_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_ROUTEPEN */ #define GPIO_ROUTEPEN_ETMTCLKPEN (0x1UL << 16) /**< ETM Trace Clock Pin Enable */ #define _GPIO_ROUTEPEN_ETMTCLKPEN_SHIFT 16 /**< Shift value for GPIO_ETMTCLKPEN */ #define _GPIO_ROUTEPEN_ETMTCLKPEN_MASK 0x10000UL /**< Bit mask for GPIO_ETMTCLKPEN */ #define _GPIO_ROUTEPEN_ETMTCLKPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ROUTEPEN */ #define GPIO_ROUTEPEN_ETMTCLKPEN_DEFAULT (_GPIO_ROUTEPEN_ETMTCLKPEN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_ROUTEPEN */ #define GPIO_ROUTEPEN_ETMTD0PEN (0x1UL << 17) /**< ETM Trace Data Pin Enable */ #define _GPIO_ROUTEPEN_ETMTD0PEN_SHIFT 17 /**< Shift value for GPIO_ETMTD0PEN */ #define _GPIO_ROUTEPEN_ETMTD0PEN_MASK 0x20000UL /**< Bit mask for GPIO_ETMTD0PEN */ #define _GPIO_ROUTEPEN_ETMTD0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ROUTEPEN */ #define GPIO_ROUTEPEN_ETMTD0PEN_DEFAULT (_GPIO_ROUTEPEN_ETMTD0PEN_DEFAULT << 17) /**< Shifted mode DEFAULT for GPIO_ROUTEPEN */ #define GPIO_ROUTEPEN_ETMTD1PEN (0x1UL << 18) /**< ETM Trace Data Pin Enable */ #define _GPIO_ROUTEPEN_ETMTD1PEN_SHIFT 18 /**< Shift value for GPIO_ETMTD1PEN */ #define _GPIO_ROUTEPEN_ETMTD1PEN_MASK 0x40000UL /**< Bit mask for GPIO_ETMTD1PEN */ #define _GPIO_ROUTEPEN_ETMTD1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ROUTEPEN */ #define GPIO_ROUTEPEN_ETMTD1PEN_DEFAULT (_GPIO_ROUTEPEN_ETMTD1PEN_DEFAULT << 18) /**< Shifted mode DEFAULT for GPIO_ROUTEPEN */ #define GPIO_ROUTEPEN_ETMTD2PEN (0x1UL << 19) /**< ETM Trace Data Pin Enable */ #define _GPIO_ROUTEPEN_ETMTD2PEN_SHIFT 19 /**< Shift value for GPIO_ETMTD2PEN */ #define _GPIO_ROUTEPEN_ETMTD2PEN_MASK 0x80000UL /**< Bit mask for GPIO_ETMTD2PEN */ #define _GPIO_ROUTEPEN_ETMTD2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ROUTEPEN */ #define GPIO_ROUTEPEN_ETMTD2PEN_DEFAULT (_GPIO_ROUTEPEN_ETMTD2PEN_DEFAULT << 19) /**< Shifted mode DEFAULT for GPIO_ROUTEPEN */ #define GPIO_ROUTEPEN_ETMTD3PEN (0x1UL << 20) /**< ETM Trace Data Pin Enable */ #define _GPIO_ROUTEPEN_ETMTD3PEN_SHIFT 20 /**< Shift value for GPIO_ETMTD3PEN */ #define _GPIO_ROUTEPEN_ETMTD3PEN_MASK 0x100000UL /**< Bit mask for GPIO_ETMTD3PEN */ #define _GPIO_ROUTEPEN_ETMTD3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ROUTEPEN */ #define GPIO_ROUTEPEN_ETMTD3PEN_DEFAULT (_GPIO_ROUTEPEN_ETMTD3PEN_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_ROUTEPEN */ /* Bit fields for GPIO ROUTELOC0 */ #define _GPIO_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for GPIO_ROUTELOC0 */ #define _GPIO_ROUTELOC0_MASK 0x00000003UL /**< Mask for GPIO_ROUTELOC0 */ #define _GPIO_ROUTELOC0_SWVLOC_SHIFT 0 /**< Shift value for GPIO_SWVLOC */ #define _GPIO_ROUTELOC0_SWVLOC_MASK 0x3UL /**< Bit mask for GPIO_SWVLOC */ #define _GPIO_ROUTELOC0_SWVLOC_LOC0 0x00000000UL /**< Mode LOC0 for GPIO_ROUTELOC0 */ #define _GPIO_ROUTELOC0_SWVLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ROUTELOC0 */ #define _GPIO_ROUTELOC0_SWVLOC_LOC1 0x00000001UL /**< Mode LOC1 for GPIO_ROUTELOC0 */ #define _GPIO_ROUTELOC0_SWVLOC_LOC2 0x00000002UL /**< Mode LOC2 for GPIO_ROUTELOC0 */ #define _GPIO_ROUTELOC0_SWVLOC_LOC3 0x00000003UL /**< Mode LOC3 for GPIO_ROUTELOC0 */ #define GPIO_ROUTELOC0_SWVLOC_LOC0 (_GPIO_ROUTELOC0_SWVLOC_LOC0 << 0) /**< Shifted mode LOC0 for GPIO_ROUTELOC0 */ #define GPIO_ROUTELOC0_SWVLOC_DEFAULT (_GPIO_ROUTELOC0_SWVLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_ROUTELOC0 */ #define GPIO_ROUTELOC0_SWVLOC_LOC1 (_GPIO_ROUTELOC0_SWVLOC_LOC1 << 0) /**< Shifted mode LOC1 for GPIO_ROUTELOC0 */ #define GPIO_ROUTELOC0_SWVLOC_LOC2 (_GPIO_ROUTELOC0_SWVLOC_LOC2 << 0) /**< Shifted mode LOC2 for GPIO_ROUTELOC0 */ #define GPIO_ROUTELOC0_SWVLOC_LOC3 (_GPIO_ROUTELOC0_SWVLOC_LOC3 << 0) /**< Shifted mode LOC3 for GPIO_ROUTELOC0 */ /* Bit fields for GPIO ROUTELOC1 */ #define _GPIO_ROUTELOC1_RESETVALUE 0x00000000UL /**< Default value for GPIO_ROUTELOC1 */ #define _GPIO_ROUTELOC1_MASK 0x0C30C303UL /**< Mask for GPIO_ROUTELOC1 */ #define _GPIO_ROUTELOC1_ETMTCLKLOC_SHIFT 0 /**< Shift value for GPIO_ETMTCLKLOC */ #define _GPIO_ROUTELOC1_ETMTCLKLOC_MASK 0x3UL /**< Bit mask for GPIO_ETMTCLKLOC */ #define _GPIO_ROUTELOC1_ETMTCLKLOC_LOC0 0x00000000UL /**< Mode LOC0 for GPIO_ROUTELOC1 */ #define _GPIO_ROUTELOC1_ETMTCLKLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ROUTELOC1 */ #define _GPIO_ROUTELOC1_ETMTCLKLOC_LOC1 0x00000001UL /**< Mode LOC1 for GPIO_ROUTELOC1 */ #define _GPIO_ROUTELOC1_ETMTCLKLOC_LOC2 0x00000002UL /**< Mode LOC2 for GPIO_ROUTELOC1 */ #define _GPIO_ROUTELOC1_ETMTCLKLOC_LOC3 0x00000003UL /**< Mode LOC3 for GPIO_ROUTELOC1 */ #define GPIO_ROUTELOC1_ETMTCLKLOC_LOC0 (_GPIO_ROUTELOC1_ETMTCLKLOC_LOC0 << 0) /**< Shifted mode LOC0 for GPIO_ROUTELOC1 */ #define GPIO_ROUTELOC1_ETMTCLKLOC_DEFAULT (_GPIO_ROUTELOC1_ETMTCLKLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_ROUTELOC1 */ #define GPIO_ROUTELOC1_ETMTCLKLOC_LOC1 (_GPIO_ROUTELOC1_ETMTCLKLOC_LOC1 << 0) /**< Shifted mode LOC1 for GPIO_ROUTELOC1 */ #define GPIO_ROUTELOC1_ETMTCLKLOC_LOC2 (_GPIO_ROUTELOC1_ETMTCLKLOC_LOC2 << 0) /**< Shifted mode LOC2 for GPIO_ROUTELOC1 */ #define GPIO_ROUTELOC1_ETMTCLKLOC_LOC3 (_GPIO_ROUTELOC1_ETMTCLKLOC_LOC3 << 0) /**< Shifted mode LOC3 for GPIO_ROUTELOC1 */ #define _GPIO_ROUTELOC1_ETMTD0LOC_SHIFT 8 /**< Shift value for GPIO_ETMTD0LOC */ #define _GPIO_ROUTELOC1_ETMTD0LOC_MASK 0x300UL /**< Bit mask for GPIO_ETMTD0LOC */ #define _GPIO_ROUTELOC1_ETMTD0LOC_LOC0 0x00000000UL /**< Mode LOC0 for GPIO_ROUTELOC1 */ #define _GPIO_ROUTELOC1_ETMTD0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ROUTELOC1 */ #define _GPIO_ROUTELOC1_ETMTD0LOC_LOC1 0x00000001UL /**< Mode LOC1 for GPIO_ROUTELOC1 */ #define _GPIO_ROUTELOC1_ETMTD0LOC_LOC2 0x00000002UL /**< Mode LOC2 for GPIO_ROUTELOC1 */ #define _GPIO_ROUTELOC1_ETMTD0LOC_LOC3 0x00000003UL /**< Mode LOC3 for GPIO_ROUTELOC1 */ #define GPIO_ROUTELOC1_ETMTD0LOC_LOC0 (_GPIO_ROUTELOC1_ETMTD0LOC_LOC0 << 8) /**< Shifted mode LOC0 for GPIO_ROUTELOC1 */ #define GPIO_ROUTELOC1_ETMTD0LOC_DEFAULT (_GPIO_ROUTELOC1_ETMTD0LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_ROUTELOC1 */ #define GPIO_ROUTELOC1_ETMTD0LOC_LOC1 (_GPIO_ROUTELOC1_ETMTD0LOC_LOC1 << 8) /**< Shifted mode LOC1 for GPIO_ROUTELOC1 */ #define GPIO_ROUTELOC1_ETMTD0LOC_LOC2 (_GPIO_ROUTELOC1_ETMTD0LOC_LOC2 << 8) /**< Shifted mode LOC2 for GPIO_ROUTELOC1 */ #define GPIO_ROUTELOC1_ETMTD0LOC_LOC3 (_GPIO_ROUTELOC1_ETMTD0LOC_LOC3 << 8) /**< Shifted mode LOC3 for GPIO_ROUTELOC1 */ #define _GPIO_ROUTELOC1_ETMTD1LOC_SHIFT 14 /**< Shift value for GPIO_ETMTD1LOC */ #define _GPIO_ROUTELOC1_ETMTD1LOC_MASK 0xC000UL /**< Bit mask for GPIO_ETMTD1LOC */ #define _GPIO_ROUTELOC1_ETMTD1LOC_LOC0 0x00000000UL /**< Mode LOC0 for GPIO_ROUTELOC1 */ #define _GPIO_ROUTELOC1_ETMTD1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ROUTELOC1 */ #define _GPIO_ROUTELOC1_ETMTD1LOC_LOC1 0x00000001UL /**< Mode LOC1 for GPIO_ROUTELOC1 */ #define _GPIO_ROUTELOC1_ETMTD1LOC_LOC2 0x00000002UL /**< Mode LOC2 for GPIO_ROUTELOC1 */ #define _GPIO_ROUTELOC1_ETMTD1LOC_LOC3 0x00000003UL /**< Mode LOC3 for GPIO_ROUTELOC1 */ #define GPIO_ROUTELOC1_ETMTD1LOC_LOC0 (_GPIO_ROUTELOC1_ETMTD1LOC_LOC0 << 14) /**< Shifted mode LOC0 for GPIO_ROUTELOC1 */ #define GPIO_ROUTELOC1_ETMTD1LOC_DEFAULT (_GPIO_ROUTELOC1_ETMTD1LOC_DEFAULT << 14) /**< Shifted mode DEFAULT for GPIO_ROUTELOC1 */ #define GPIO_ROUTELOC1_ETMTD1LOC_LOC1 (_GPIO_ROUTELOC1_ETMTD1LOC_LOC1 << 14) /**< Shifted mode LOC1 for GPIO_ROUTELOC1 */ #define GPIO_ROUTELOC1_ETMTD1LOC_LOC2 (_GPIO_ROUTELOC1_ETMTD1LOC_LOC2 << 14) /**< Shifted mode LOC2 for GPIO_ROUTELOC1 */ #define GPIO_ROUTELOC1_ETMTD1LOC_LOC3 (_GPIO_ROUTELOC1_ETMTD1LOC_LOC3 << 14) /**< Shifted mode LOC3 for GPIO_ROUTELOC1 */ #define _GPIO_ROUTELOC1_ETMTD2LOC_SHIFT 20 /**< Shift value for GPIO_ETMTD2LOC */ #define _GPIO_ROUTELOC1_ETMTD2LOC_MASK 0x300000UL /**< Bit mask for GPIO_ETMTD2LOC */ #define _GPIO_ROUTELOC1_ETMTD2LOC_LOC0 0x00000000UL /**< Mode LOC0 for GPIO_ROUTELOC1 */ #define _GPIO_ROUTELOC1_ETMTD2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ROUTELOC1 */ #define _GPIO_ROUTELOC1_ETMTD2LOC_LOC1 0x00000001UL /**< Mode LOC1 for GPIO_ROUTELOC1 */ #define _GPIO_ROUTELOC1_ETMTD2LOC_LOC2 0x00000002UL /**< Mode LOC2 for GPIO_ROUTELOC1 */ #define _GPIO_ROUTELOC1_ETMTD2LOC_LOC3 0x00000003UL /**< Mode LOC3 for GPIO_ROUTELOC1 */ #define GPIO_ROUTELOC1_ETMTD2LOC_LOC0 (_GPIO_ROUTELOC1_ETMTD2LOC_LOC0 << 20) /**< Shifted mode LOC0 for GPIO_ROUTELOC1 */ #define GPIO_ROUTELOC1_ETMTD2LOC_DEFAULT (_GPIO_ROUTELOC1_ETMTD2LOC_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_ROUTELOC1 */ #define GPIO_ROUTELOC1_ETMTD2LOC_LOC1 (_GPIO_ROUTELOC1_ETMTD2LOC_LOC1 << 20) /**< Shifted mode LOC1 for GPIO_ROUTELOC1 */ #define GPIO_ROUTELOC1_ETMTD2LOC_LOC2 (_GPIO_ROUTELOC1_ETMTD2LOC_LOC2 << 20) /**< Shifted mode LOC2 for GPIO_ROUTELOC1 */ #define GPIO_ROUTELOC1_ETMTD2LOC_LOC3 (_GPIO_ROUTELOC1_ETMTD2LOC_LOC3 << 20) /**< Shifted mode LOC3 for GPIO_ROUTELOC1 */ #define _GPIO_ROUTELOC1_ETMTD3LOC_SHIFT 26 /**< Shift value for GPIO_ETMTD3LOC */ #define _GPIO_ROUTELOC1_ETMTD3LOC_MASK 0xC000000UL /**< Bit mask for GPIO_ETMTD3LOC */ #define _GPIO_ROUTELOC1_ETMTD3LOC_LOC0 0x00000000UL /**< Mode LOC0 for GPIO_ROUTELOC1 */ #define _GPIO_ROUTELOC1_ETMTD3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ROUTELOC1 */ #define _GPIO_ROUTELOC1_ETMTD3LOC_LOC1 0x00000001UL /**< Mode LOC1 for GPIO_ROUTELOC1 */ #define _GPIO_ROUTELOC1_ETMTD3LOC_LOC2 0x00000002UL /**< Mode LOC2 for GPIO_ROUTELOC1 */ #define _GPIO_ROUTELOC1_ETMTD3LOC_LOC3 0x00000003UL /**< Mode LOC3 for GPIO_ROUTELOC1 */ #define GPIO_ROUTELOC1_ETMTD3LOC_LOC0 (_GPIO_ROUTELOC1_ETMTD3LOC_LOC0 << 26) /**< Shifted mode LOC0 for GPIO_ROUTELOC1 */ #define GPIO_ROUTELOC1_ETMTD3LOC_DEFAULT (_GPIO_ROUTELOC1_ETMTD3LOC_DEFAULT << 26) /**< Shifted mode DEFAULT for GPIO_ROUTELOC1 */ #define GPIO_ROUTELOC1_ETMTD3LOC_LOC1 (_GPIO_ROUTELOC1_ETMTD3LOC_LOC1 << 26) /**< Shifted mode LOC1 for GPIO_ROUTELOC1 */ #define GPIO_ROUTELOC1_ETMTD3LOC_LOC2 (_GPIO_ROUTELOC1_ETMTD3LOC_LOC2 << 26) /**< Shifted mode LOC2 for GPIO_ROUTELOC1 */ #define GPIO_ROUTELOC1_ETMTD3LOC_LOC3 (_GPIO_ROUTELOC1_ETMTD3LOC_LOC3 << 26) /**< Shifted mode LOC3 for GPIO_ROUTELOC1 */ /* Bit fields for GPIO INSENSE */ #define _GPIO_INSENSE_RESETVALUE 0x00000003UL /**< Default value for GPIO_INSENSE */ #define _GPIO_INSENSE_MASK 0x00000003UL /**< Mask for GPIO_INSENSE */ #define GPIO_INSENSE_INT (0x1UL << 0) /**< Interrupt Sense Enable */ #define _GPIO_INSENSE_INT_SHIFT 0 /**< Shift value for GPIO_INT */ #define _GPIO_INSENSE_INT_MASK 0x1UL /**< Bit mask for GPIO_INT */ #define _GPIO_INSENSE_INT_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_INSENSE */ #define GPIO_INSENSE_INT_DEFAULT (_GPIO_INSENSE_INT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_INSENSE */ #define GPIO_INSENSE_EM4WU (0x1UL << 1) /**< EM4WU Interrupt Sense Enable */ #define _GPIO_INSENSE_EM4WU_SHIFT 1 /**< Shift value for GPIO_EM4WU */ #define _GPIO_INSENSE_EM4WU_MASK 0x2UL /**< Bit mask for GPIO_EM4WU */ #define _GPIO_INSENSE_EM4WU_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_INSENSE */ #define GPIO_INSENSE_EM4WU_DEFAULT (_GPIO_INSENSE_EM4WU_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_INSENSE */ /* Bit fields for GPIO LOCK */ #define _GPIO_LOCK_RESETVALUE 0x00000000UL /**< Default value for GPIO_LOCK */ #define _GPIO_LOCK_MASK 0x0000FFFFUL /**< Mask for GPIO_LOCK */ #define _GPIO_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for GPIO_LOCKKEY */ #define _GPIO_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for GPIO_LOCKKEY */ #define _GPIO_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LOCK */ #define _GPIO_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for GPIO_LOCK */ #define _GPIO_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for GPIO_LOCK */ #define _GPIO_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for GPIO_LOCK */ #define _GPIO_LOCK_LOCKKEY_UNLOCK 0x0000A534UL /**< Mode UNLOCK for GPIO_LOCK */ #define GPIO_LOCK_LOCKKEY_DEFAULT (_GPIO_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LOCK */ #define GPIO_LOCK_LOCKKEY_LOCK (_GPIO_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for GPIO_LOCK */ #define GPIO_LOCK_LOCKKEY_UNLOCKED (_GPIO_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for GPIO_LOCK */ #define GPIO_LOCK_LOCKKEY_LOCKED (_GPIO_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for GPIO_LOCK */ #define GPIO_LOCK_LOCKKEY_UNLOCK (_GPIO_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for GPIO_LOCK */ /** @} */ /** @} End of group EFR32MG12P_GPIO */ /** @} End of group Parts */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_gpio_p.h.
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/***************************************************************************//** * @file * @brief EFR32MG12P_GPIO_P register and bit field definitions * @version 5.7.0 ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * SPDX-License-Identifier: Zlib * * The licensor of this software is Silicon Laboratories Inc. * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be * appreciated but is not required. * 2. Altered source versions must be plainly marked as such, and must not be * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * ******************************************************************************/ #if defined(__ICCARM__) #pragma system_include /* Treat file as system include file. */ #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang system_header /* Treat file as system include file. */ #endif /***************************************************************************//** * @addtogroup Parts * @{ ******************************************************************************/ /***************************************************************************//** * @brief GPIO_P GPIO P Register * @ingroup EFR32MG12P_GPIO ******************************************************************************/ typedef struct { __IOM uint32_t CTRL; /**< Port Control Register */ __IOM uint32_t MODEL; /**< Port Pin Mode Low Register */ __IOM uint32_t MODEH; /**< Port Pin Mode High Register */ __IOM uint32_t DOUT; /**< Port Data Out Register */ uint32_t RESERVED0[2U]; /**< Reserved for future use **/ __IOM uint32_t DOUTTGL; /**< Port Data Out Toggle Register */ __IM uint32_t DIN; /**< Port Data in Register */ __IOM uint32_t PINLOCKN; /**< Port Unlocked Pins Register */ uint32_t RESERVED1[1U]; /**< Reserved for future use **/ __IOM uint32_t OVTDIS; /**< Over Voltage Disable for All Modes */ uint32_t RESERVED2[1U]; /**< Reserved future */ } GPIO_P_TypeDef; /** @} End of group Parts */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_i2c.h.
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/***************************************************************************//** * @file * @brief EFR32MG12P_I2C register and bit field definitions * @version 5.7.0 ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * SPDX-License-Identifier: Zlib * * The licensor of this software is Silicon Laboratories Inc. * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be * appreciated but is not required. * 2. Altered source versions must be plainly marked as such, and must not be * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * ******************************************************************************/ #if defined(__ICCARM__) #pragma system_include /* Treat file as system include file. */ #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang system_header /* Treat file as system include file. */ #endif /***************************************************************************//** * @addtogroup Parts * @{ ******************************************************************************/ /***************************************************************************//** * @defgroup EFR32MG12P_I2C I2C * @{ * @brief EFR32MG12P_I2C Register Declaration ******************************************************************************/ /** I2C Register Declaration */ typedef struct { __IOM uint32_t CTRL; /**< Control Register */ __IOM uint32_t CMD; /**< Command Register */ __IM uint32_t STATE; /**< State Register */ __IM uint32_t STATUS; /**< Status Register */ __IOM uint32_t CLKDIV; /**< Clock Division Register */ __IOM uint32_t SADDR; /**< Slave Address Register */ __IOM uint32_t SADDRMASK; /**< Slave Address Mask Register */ __IM uint32_t RXDATA; /**< Receive Buffer Data Register */ __IM uint32_t RXDOUBLE; /**< Receive Buffer Double Data Register */ __IM uint32_t RXDATAP; /**< Receive Buffer Data Peek Register */ __IM uint32_t RXDOUBLEP; /**< Receive Buffer Double Data Peek Register */ __IOM uint32_t TXDATA; /**< Transmit Buffer Data Register */ __IOM uint32_t TXDOUBLE; /**< Transmit Buffer Double Data Register */ __IM uint32_t IF; /**< Interrupt Flag Register */ __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ __IOM uint32_t IEN; /**< Interrupt Enable Register */ __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ } I2C_TypeDef; /** @} */ /***************************************************************************//** * @addtogroup EFR32MG12P_I2C * @{ * @defgroup EFR32MG12P_I2C_BitFields I2C Bit Fields * @{ ******************************************************************************/ /* Bit fields for I2C CTRL */ #define _I2C_CTRL_RESETVALUE 0x00000000UL /**< Default value for I2C_CTRL */ #define _I2C_CTRL_MASK 0x0007B3FFUL /**< Mask for I2C_CTRL */ #define I2C_CTRL_EN (0x1UL << 0) /**< I2C Enable */ #define _I2C_CTRL_EN_SHIFT 0 /**< Shift value for I2C_EN */ #define _I2C_CTRL_EN_MASK 0x1UL /**< Bit mask for I2C_EN */ #define _I2C_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ #define I2C_CTRL_EN_DEFAULT (_I2C_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CTRL */ #define I2C_CTRL_SLAVE (0x1UL << 1) /**< Addressable as Slave */ #define _I2C_CTRL_SLAVE_SHIFT 1 /**< Shift value for I2C_SLAVE */ #define _I2C_CTRL_SLAVE_MASK 0x2UL /**< Bit mask for I2C_SLAVE */ #define _I2C_CTRL_SLAVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ #define I2C_CTRL_SLAVE_DEFAULT (_I2C_CTRL_SLAVE_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_CTRL */ #define I2C_CTRL_AUTOACK (0x1UL << 2) /**< Automatic Acknowledge */ #define _I2C_CTRL_AUTOACK_SHIFT 2 /**< Shift value for I2C_AUTOACK */ #define _I2C_CTRL_AUTOACK_MASK 0x4UL /**< Bit mask for I2C_AUTOACK */ #define _I2C_CTRL_AUTOACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ #define I2C_CTRL_AUTOACK_DEFAULT (_I2C_CTRL_AUTOACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_CTRL */ #define I2C_CTRL_AUTOSE (0x1UL << 3) /**< Automatic STOP When Empty */ #define _I2C_CTRL_AUTOSE_SHIFT 3 /**< Shift value for I2C_AUTOSE */ #define _I2C_CTRL_AUTOSE_MASK 0x8UL /**< Bit mask for I2C_AUTOSE */ #define _I2C_CTRL_AUTOSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ #define I2C_CTRL_AUTOSE_DEFAULT (_I2C_CTRL_AUTOSE_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_CTRL */ #define I2C_CTRL_AUTOSN (0x1UL << 4) /**< Automatic STOP on NACK */ #define _I2C_CTRL_AUTOSN_SHIFT 4 /**< Shift value for I2C_AUTOSN */ #define _I2C_CTRL_AUTOSN_MASK 0x10UL /**< Bit mask for I2C_AUTOSN */ #define _I2C_CTRL_AUTOSN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ #define I2C_CTRL_AUTOSN_DEFAULT (_I2C_CTRL_AUTOSN_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_CTRL */ #define I2C_CTRL_ARBDIS (0x1UL << 5) /**< Arbitration Disable */ #define _I2C_CTRL_ARBDIS_SHIFT 5 /**< Shift value for I2C_ARBDIS */ #define _I2C_CTRL_ARBDIS_MASK 0x20UL /**< Bit mask for I2C_ARBDIS */ #define _I2C_CTRL_ARBDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ #define I2C_CTRL_ARBDIS_DEFAULT (_I2C_CTRL_ARBDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_CTRL */ #define I2C_CTRL_GCAMEN (0x1UL << 6) /**< General Call Address Match Enable */ #define _I2C_CTRL_GCAMEN_SHIFT 6 /**< Shift value for I2C_GCAMEN */ #define _I2C_CTRL_GCAMEN_MASK 0x40UL /**< Bit mask for I2C_GCAMEN */ #define _I2C_CTRL_GCAMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ #define I2C_CTRL_GCAMEN_DEFAULT (_I2C_CTRL_GCAMEN_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_CTRL */ #define I2C_CTRL_TXBIL (0x1UL << 7) /**< TX Buffer Interrupt Level */ #define _I2C_CTRL_TXBIL_SHIFT 7 /**< Shift value for I2C_TXBIL */ #define _I2C_CTRL_TXBIL_MASK 0x80UL /**< Bit mask for I2C_TXBIL */ #define _I2C_CTRL_TXBIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ #define _I2C_CTRL_TXBIL_EMPTY 0x00000000UL /**< Mode EMPTY for I2C_CTRL */ #define _I2C_CTRL_TXBIL_HALFFULL 0x00000001UL /**< Mode HALFFULL for I2C_CTRL */ #define I2C_CTRL_TXBIL_DEFAULT (_I2C_CTRL_TXBIL_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_CTRL */ #define I2C_CTRL_TXBIL_EMPTY (_I2C_CTRL_TXBIL_EMPTY << 7) /**< Shifted mode EMPTY for I2C_CTRL */ #define I2C_CTRL_TXBIL_HALFFULL (_I2C_CTRL_TXBIL_HALFFULL << 7) /**< Shifted mode HALFFULL for I2C_CTRL */ #define _I2C_CTRL_CLHR_SHIFT 8 /**< Shift value for I2C_CLHR */ #define _I2C_CTRL_CLHR_MASK 0x300UL /**< Bit mask for I2C_CLHR */ #define _I2C_CTRL_CLHR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ #define _I2C_CTRL_CLHR_STANDARD 0x00000000UL /**< Mode STANDARD for I2C_CTRL */ #define _I2C_CTRL_CLHR_ASYMMETRIC 0x00000001UL /**< Mode ASYMMETRIC for I2C_CTRL */ #define _I2C_CTRL_CLHR_FAST 0x00000002UL /**< Mode FAST for I2C_CTRL */ #define I2C_CTRL_CLHR_DEFAULT (_I2C_CTRL_CLHR_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_CTRL */ #define I2C_CTRL_CLHR_STANDARD (_I2C_CTRL_CLHR_STANDARD << 8) /**< Shifted mode STANDARD for I2C_CTRL */ #define I2C_CTRL_CLHR_ASYMMETRIC (_I2C_CTRL_CLHR_ASYMMETRIC << 8) /**< Shifted mode ASYMMETRIC for I2C_CTRL */ #define I2C_CTRL_CLHR_FAST (_I2C_CTRL_CLHR_FAST << 8) /**< Shifted mode FAST for I2C_CTRL */ #define _I2C_CTRL_BITO_SHIFT 12 /**< Shift value for I2C_BITO */ #define _I2C_CTRL_BITO_MASK 0x3000UL /**< Bit mask for I2C_BITO */ #define _I2C_CTRL_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ #define _I2C_CTRL_BITO_OFF 0x00000000UL /**< Mode OFF for I2C_CTRL */ #define _I2C_CTRL_BITO_40PCC 0x00000001UL /**< Mode 40PCC for I2C_CTRL */ #define _I2C_CTRL_BITO_80PCC 0x00000002UL /**< Mode 80PCC for I2C_CTRL */ #define _I2C_CTRL_BITO_160PCC 0x00000003UL /**< Mode 160PCC for I2C_CTRL */ #define I2C_CTRL_BITO_DEFAULT (_I2C_CTRL_BITO_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_CTRL */ #define I2C_CTRL_BITO_OFF (_I2C_CTRL_BITO_OFF << 12) /**< Shifted mode OFF for I2C_CTRL */ #define I2C_CTRL_BITO_40PCC (_I2C_CTRL_BITO_40PCC << 12) /**< Shifted mode 40PCC for I2C_CTRL */ #define I2C_CTRL_BITO_80PCC (_I2C_CTRL_BITO_80PCC << 12) /**< Shifted mode 80PCC for I2C_CTRL */ #define I2C_CTRL_BITO_160PCC (_I2C_CTRL_BITO_160PCC << 12) /**< Shifted mode 160PCC for I2C_CTRL */ #define I2C_CTRL_GIBITO (0x1UL << 15) /**< Go Idle on Bus Idle Timeout */ #define _I2C_CTRL_GIBITO_SHIFT 15 /**< Shift value for I2C_GIBITO */ #define _I2C_CTRL_GIBITO_MASK 0x8000UL /**< Bit mask for I2C_GIBITO */ #define _I2C_CTRL_GIBITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ #define I2C_CTRL_GIBITO_DEFAULT (_I2C_CTRL_GIBITO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_CTRL */ #define _I2C_CTRL_CLTO_SHIFT 16 /**< Shift value for I2C_CLTO */ #define _I2C_CTRL_CLTO_MASK 0x70000UL /**< Bit mask for I2C_CLTO */ #define _I2C_CTRL_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ #define _I2C_CTRL_CLTO_OFF 0x00000000UL /**< Mode OFF for I2C_CTRL */ #define _I2C_CTRL_CLTO_40PCC 0x00000001UL /**< Mode 40PCC for I2C_CTRL */ #define _I2C_CTRL_CLTO_80PCC 0x00000002UL /**< Mode 80PCC for I2C_CTRL */ #define _I2C_CTRL_CLTO_160PCC 0x00000003UL /**< Mode 160PCC for I2C_CTRL */ #define _I2C_CTRL_CLTO_320PCC 0x00000004UL /**< Mode 320PCC for I2C_CTRL */ #define _I2C_CTRL_CLTO_1024PCC 0x00000005UL /**< Mode 1024PCC for I2C_CTRL */ #define I2C_CTRL_CLTO_DEFAULT (_I2C_CTRL_CLTO_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_CTRL */ #define I2C_CTRL_CLTO_OFF (_I2C_CTRL_CLTO_OFF << 16) /**< Shifted mode OFF for I2C_CTRL */ #define I2C_CTRL_CLTO_40PCC (_I2C_CTRL_CLTO_40PCC << 16) /**< Shifted mode 40PCC for I2C_CTRL */ #define I2C_CTRL_CLTO_80PCC (_I2C_CTRL_CLTO_80PCC << 16) /**< Shifted mode 80PCC for I2C_CTRL */ #define I2C_CTRL_CLTO_160PCC (_I2C_CTRL_CLTO_160PCC << 16) /**< Shifted mode 160PCC for I2C_CTRL */ #define I2C_CTRL_CLTO_320PCC (_I2C_CTRL_CLTO_320PCC << 16) /**< Shifted mode 320PCC for I2C_CTRL */ #define I2C_CTRL_CLTO_1024PCC (_I2C_CTRL_CLTO_1024PCC << 16) /**< Shifted mode 1024PCC for I2C_CTRL */ /* Bit fields for I2C CMD */ #define _I2C_CMD_RESETVALUE 0x00000000UL /**< Default value for I2C_CMD */ #define _I2C_CMD_MASK 0x000000FFUL /**< Mask for I2C_CMD */ #define I2C_CMD_START (0x1UL << 0) /**< Send Start Condition */ #define _I2C_CMD_START_SHIFT 0 /**< Shift value for I2C_START */ #define _I2C_CMD_START_MASK 0x1UL /**< Bit mask for I2C_START */ #define _I2C_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ #define I2C_CMD_START_DEFAULT (_I2C_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CMD */ #define I2C_CMD_STOP (0x1UL << 1) /**< Send Stop Condition */ #define _I2C_CMD_STOP_SHIFT 1 /**< Shift value for I2C_STOP */ #define _I2C_CMD_STOP_MASK 0x2UL /**< Bit mask for I2C_STOP */ #define _I2C_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ #define I2C_CMD_STOP_DEFAULT (_I2C_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_CMD */ #define I2C_CMD_ACK (0x1UL << 2) /**< Send ACK */ #define _I2C_CMD_ACK_SHIFT 2 /**< Shift value for I2C_ACK */ #define _I2C_CMD_ACK_MASK 0x4UL /**< Bit mask for I2C_ACK */ #define _I2C_CMD_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ #define I2C_CMD_ACK_DEFAULT (_I2C_CMD_ACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_CMD */ #define I2C_CMD_NACK (0x1UL << 3) /**< Send NACK */ #define _I2C_CMD_NACK_SHIFT 3 /**< Shift value for I2C_NACK */ #define _I2C_CMD_NACK_MASK 0x8UL /**< Bit mask for I2C_NACK */ #define _I2C_CMD_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ #define I2C_CMD_NACK_DEFAULT (_I2C_CMD_NACK_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_CMD */ #define I2C_CMD_CONT (0x1UL << 4) /**< Continue Transmission */ #define _I2C_CMD_CONT_SHIFT 4 /**< Shift value for I2C_CONT */ #define _I2C_CMD_CONT_MASK 0x10UL /**< Bit mask for I2C_CONT */ #define _I2C_CMD_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ #define I2C_CMD_CONT_DEFAULT (_I2C_CMD_CONT_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_CMD */ #define I2C_CMD_ABORT (0x1UL << 5) /**< Abort Transmission */ #define _I2C_CMD_ABORT_SHIFT 5 /**< Shift value for I2C_ABORT */ #define _I2C_CMD_ABORT_MASK 0x20UL /**< Bit mask for I2C_ABORT */ #define _I2C_CMD_ABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ #define I2C_CMD_ABORT_DEFAULT (_I2C_CMD_ABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_CMD */ #define I2C_CMD_CLEARTX (0x1UL << 6) /**< Clear TX */ #define _I2C_CMD_CLEARTX_SHIFT 6 /**< Shift value for I2C_CLEARTX */ #define _I2C_CMD_CLEARTX_MASK 0x40UL /**< Bit mask for I2C_CLEARTX */ #define _I2C_CMD_CLEARTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ #define I2C_CMD_CLEARTX_DEFAULT (_I2C_CMD_CLEARTX_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_CMD */ #define I2C_CMD_CLEARPC (0x1UL << 7) /**< Clear Pending Commands */ #define _I2C_CMD_CLEARPC_SHIFT 7 /**< Shift value for I2C_CLEARPC */ #define _I2C_CMD_CLEARPC_MASK 0x80UL /**< Bit mask for I2C_CLEARPC */ #define _I2C_CMD_CLEARPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ #define I2C_CMD_CLEARPC_DEFAULT (_I2C_CMD_CLEARPC_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_CMD */ /* Bit fields for I2C STATE */ #define _I2C_STATE_RESETVALUE 0x00000001UL /**< Default value for I2C_STATE */ #define _I2C_STATE_MASK 0x000000FFUL /**< Mask for I2C_STATE */ #define I2C_STATE_BUSY (0x1UL << 0) /**< Bus Busy */ #define _I2C_STATE_BUSY_SHIFT 0 /**< Shift value for I2C_BUSY */ #define _I2C_STATE_BUSY_MASK 0x1UL /**< Bit mask for I2C_BUSY */ #define _I2C_STATE_BUSY_DEFAULT 0x00000001UL /**< Mode DEFAULT for I2C_STATE */ #define I2C_STATE_BUSY_DEFAULT (_I2C_STATE_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_STATE */ #define I2C_STATE_MASTER (0x1UL << 1) /**< Master */ #define _I2C_STATE_MASTER_SHIFT 1 /**< Shift value for I2C_MASTER */ #define _I2C_STATE_MASTER_MASK 0x2UL /**< Bit mask for I2C_MASTER */ #define _I2C_STATE_MASTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ #define I2C_STATE_MASTER_DEFAULT (_I2C_STATE_MASTER_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_STATE */ #define I2C_STATE_TRANSMITTER (0x1UL << 2) /**< Transmitter */ #define _I2C_STATE_TRANSMITTER_SHIFT 2 /**< Shift value for I2C_TRANSMITTER */ #define _I2C_STATE_TRANSMITTER_MASK 0x4UL /**< Bit mask for I2C_TRANSMITTER */ #define _I2C_STATE_TRANSMITTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ #define I2C_STATE_TRANSMITTER_DEFAULT (_I2C_STATE_TRANSMITTER_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_STATE */ #define I2C_STATE_NACKED (0x1UL << 3) /**< Nack Received */ #define _I2C_STATE_NACKED_SHIFT 3 /**< Shift value for I2C_NACKED */ #define _I2C_STATE_NACKED_MASK 0x8UL /**< Bit mask for I2C_NACKED */ #define _I2C_STATE_NACKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ #define I2C_STATE_NACKED_DEFAULT (_I2C_STATE_NACKED_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_STATE */ #define I2C_STATE_BUSHOLD (0x1UL << 4) /**< Bus Held */ #define _I2C_STATE_BUSHOLD_SHIFT 4 /**< Shift value for I2C_BUSHOLD */ #define _I2C_STATE_BUSHOLD_MASK 0x10UL /**< Bit mask for I2C_BUSHOLD */ #define _I2C_STATE_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ #define I2C_STATE_BUSHOLD_DEFAULT (_I2C_STATE_BUSHOLD_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_STATE */ #define _I2C_STATE_STATE_SHIFT 5 /**< Shift value for I2C_STATE */ #define _I2C_STATE_STATE_MASK 0xE0UL /**< Bit mask for I2C_STATE */ #define _I2C_STATE_STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ #define _I2C_STATE_STATE_IDLE 0x00000000UL /**< Mode IDLE for I2C_STATE */ #define _I2C_STATE_STATE_WAIT 0x00000001UL /**< Mode WAIT for I2C_STATE */ #define _I2C_STATE_STATE_START 0x00000002UL /**< Mode START for I2C_STATE */ #define _I2C_STATE_STATE_ADDR 0x00000003UL /**< Mode ADDR for I2C_STATE */ #define _I2C_STATE_STATE_ADDRACK 0x00000004UL /**< Mode ADDRACK for I2C_STATE */ #define _I2C_STATE_STATE_DATA 0x00000005UL /**< Mode DATA for I2C_STATE */ #define _I2C_STATE_STATE_DATAACK 0x00000006UL /**< Mode DATAACK for I2C_STATE */ #define I2C_STATE_STATE_DEFAULT (_I2C_STATE_STATE_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_STATE */ #define I2C_STATE_STATE_IDLE (_I2C_STATE_STATE_IDLE << 5) /**< Shifted mode IDLE for I2C_STATE */ #define I2C_STATE_STATE_WAIT (_I2C_STATE_STATE_WAIT << 5) /**< Shifted mode WAIT for I2C_STATE */ #define I2C_STATE_STATE_START (_I2C_STATE_STATE_START << 5) /**< Shifted mode START for I2C_STATE */ #define I2C_STATE_STATE_ADDR (_I2C_STATE_STATE_ADDR << 5) /**< Shifted mode ADDR for I2C_STATE */ #define I2C_STATE_STATE_ADDRACK (_I2C_STATE_STATE_ADDRACK << 5) /**< Shifted mode ADDRACK for I2C_STATE */ #define I2C_STATE_STATE_DATA (_I2C_STATE_STATE_DATA << 5) /**< Shifted mode DATA for I2C_STATE */ #define I2C_STATE_STATE_DATAACK (_I2C_STATE_STATE_DATAACK << 5) /**< Shifted mode DATAACK for I2C_STATE */ /* Bit fields for I2C STATUS */ #define _I2C_STATUS_RESETVALUE 0x00000080UL /**< Default value for I2C_STATUS */ #define _I2C_STATUS_MASK 0x000003FFUL /**< Mask for I2C_STATUS */ #define I2C_STATUS_PSTART (0x1UL << 0) /**< Pending START */ #define _I2C_STATUS_PSTART_SHIFT 0 /**< Shift value for I2C_PSTART */ #define _I2C_STATUS_PSTART_MASK 0x1UL /**< Bit mask for I2C_PSTART */ #define _I2C_STATUS_PSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ #define I2C_STATUS_PSTART_DEFAULT (_I2C_STATUS_PSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_STATUS */ #define I2C_STATUS_PSTOP (0x1UL << 1) /**< Pending STOP */ #define _I2C_STATUS_PSTOP_SHIFT 1 /**< Shift value for I2C_PSTOP */ #define _I2C_STATUS_PSTOP_MASK 0x2UL /**< Bit mask for I2C_PSTOP */ #define _I2C_STATUS_PSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ #define I2C_STATUS_PSTOP_DEFAULT (_I2C_STATUS_PSTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_STATUS */ #define I2C_STATUS_PACK (0x1UL << 2) /**< Pending ACK */ #define _I2C_STATUS_PACK_SHIFT 2 /**< Shift value for I2C_PACK */ #define _I2C_STATUS_PACK_MASK 0x4UL /**< Bit mask for I2C_PACK */ #define _I2C_STATUS_PACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ #define I2C_STATUS_PACK_DEFAULT (_I2C_STATUS_PACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_STATUS */ #define I2C_STATUS_PNACK (0x1UL << 3) /**< Pending NACK */ #define _I2C_STATUS_PNACK_SHIFT 3 /**< Shift value for I2C_PNACK */ #define _I2C_STATUS_PNACK_MASK 0x8UL /**< Bit mask for I2C_PNACK */ #define _I2C_STATUS_PNACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ #define I2C_STATUS_PNACK_DEFAULT (_I2C_STATUS_PNACK_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_STATUS */ #define I2C_STATUS_PCONT (0x1UL << 4) /**< Pending Continue */ #define _I2C_STATUS_PCONT_SHIFT 4 /**< Shift value for I2C_PCONT */ #define _I2C_STATUS_PCONT_MASK 0x10UL /**< Bit mask for I2C_PCONT */ #define _I2C_STATUS_PCONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ #define I2C_STATUS_PCONT_DEFAULT (_I2C_STATUS_PCONT_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_STATUS */ #define I2C_STATUS_PABORT (0x1UL << 5) /**< Pending Abort */ #define _I2C_STATUS_PABORT_SHIFT 5 /**< Shift value for I2C_PABORT */ #define _I2C_STATUS_PABORT_MASK 0x20UL /**< Bit mask for I2C_PABORT */ #define _I2C_STATUS_PABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ #define I2C_STATUS_PABORT_DEFAULT (_I2C_STATUS_PABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_STATUS */ #define I2C_STATUS_TXC (0x1UL << 6) /**< TX Complete */ #define _I2C_STATUS_TXC_SHIFT 6 /**< Shift value for I2C_TXC */ #define _I2C_STATUS_TXC_MASK 0x40UL /**< Bit mask for I2C_TXC */ #define _I2C_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ #define I2C_STATUS_TXC_DEFAULT (_I2C_STATUS_TXC_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_STATUS */ #define I2C_STATUS_TXBL (0x1UL << 7) /**< TX Buffer Level */ #define _I2C_STATUS_TXBL_SHIFT 7 /**< Shift value for I2C_TXBL */ #define _I2C_STATUS_TXBL_MASK 0x80UL /**< Bit mask for I2C_TXBL */ #define _I2C_STATUS_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for I2C_STATUS */ #define I2C_STATUS_TXBL_DEFAULT (_I2C_STATUS_TXBL_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_STATUS */ #define I2C_STATUS_RXDATAV (0x1UL << 8) /**< RX Data Valid */ #define _I2C_STATUS_RXDATAV_SHIFT 8 /**< Shift value for I2C_RXDATAV */ #define _I2C_STATUS_RXDATAV_MASK 0x100UL /**< Bit mask for I2C_RXDATAV */ #define _I2C_STATUS_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ #define I2C_STATUS_RXDATAV_DEFAULT (_I2C_STATUS_RXDATAV_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_STATUS */ #define I2C_STATUS_RXFULL (0x1UL << 9) /**< RX FIFO Full */ #define _I2C_STATUS_RXFULL_SHIFT 9 /**< Shift value for I2C_RXFULL */ #define _I2C_STATUS_RXFULL_MASK 0x200UL /**< Bit mask for I2C_RXFULL */ #define _I2C_STATUS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ #define I2C_STATUS_RXFULL_DEFAULT (_I2C_STATUS_RXFULL_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_STATUS */ /* Bit fields for I2C CLKDIV */ #define _I2C_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for I2C_CLKDIV */ #define _I2C_CLKDIV_MASK 0x000001FFUL /**< Mask for I2C_CLKDIV */ #define _I2C_CLKDIV_DIV_SHIFT 0 /**< Shift value for I2C_DIV */ #define _I2C_CLKDIV_DIV_MASK 0x1FFUL /**< Bit mask for I2C_DIV */ #define _I2C_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CLKDIV */ #define I2C_CLKDIV_DIV_DEFAULT (_I2C_CLKDIV_DIV_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CLKDIV */ /* Bit fields for I2C SADDR */ #define _I2C_SADDR_RESETVALUE 0x00000000UL /**< Default value for I2C_SADDR */ #define _I2C_SADDR_MASK 0x000000FEUL /**< Mask for I2C_SADDR */ #define _I2C_SADDR_ADDR_SHIFT 1 /**< Shift value for I2C_ADDR */ #define _I2C_SADDR_ADDR_MASK 0xFEUL /**< Bit mask for I2C_ADDR */ #define _I2C_SADDR_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_SADDR */ #define I2C_SADDR_ADDR_DEFAULT (_I2C_SADDR_ADDR_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_SADDR */ /* Bit fields for I2C SADDRMASK */ #define _I2C_SADDRMASK_RESETVALUE 0x00000000UL /**< Default value for I2C_SADDRMASK */ #define _I2C_SADDRMASK_MASK 0x000000FEUL /**< Mask for I2C_SADDRMASK */ #define _I2C_SADDRMASK_MASK_SHIFT 1 /**< Shift value for I2C_MASK */ #define _I2C_SADDRMASK_MASK_MASK 0xFEUL /**< Bit mask for I2C_MASK */ #define _I2C_SADDRMASK_MASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_SADDRMASK */ #define I2C_SADDRMASK_MASK_DEFAULT (_I2C_SADDRMASK_MASK_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_SADDRMASK */ /* Bit fields for I2C RXDATA */ #define _I2C_RXDATA_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDATA */ #define _I2C_RXDATA_MASK 0x000000FFUL /**< Mask for I2C_RXDATA */ #define _I2C_RXDATA_RXDATA_SHIFT 0 /**< Shift value for I2C_RXDATA */ #define _I2C_RXDATA_RXDATA_MASK 0xFFUL /**< Bit mask for I2C_RXDATA */ #define _I2C_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDATA */ #define I2C_RXDATA_RXDATA_DEFAULT (_I2C_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDATA */ /* Bit fields for I2C RXDOUBLE */ #define _I2C_RXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDOUBLE */ #define _I2C_RXDOUBLE_MASK 0x0000FFFFUL /**< Mask for I2C_RXDOUBLE */ #define _I2C_RXDOUBLE_RXDATA0_SHIFT 0 /**< Shift value for I2C_RXDATA0 */ #define _I2C_RXDOUBLE_RXDATA0_MASK 0xFFUL /**< Bit mask for I2C_RXDATA0 */ #define _I2C_RXDOUBLE_RXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLE */ #define I2C_RXDOUBLE_RXDATA0_DEFAULT (_I2C_RXDOUBLE_RXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDOUBLE */ #define _I2C_RXDOUBLE_RXDATA1_SHIFT 8 /**< Shift value for I2C_RXDATA1 */ #define _I2C_RXDOUBLE_RXDATA1_MASK 0xFF00UL /**< Bit mask for I2C_RXDATA1 */ #define _I2C_RXDOUBLE_RXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLE */ #define I2C_RXDOUBLE_RXDATA1_DEFAULT (_I2C_RXDOUBLE_RXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_RXDOUBLE */ /* Bit fields for I2C RXDATAP */ #define _I2C_RXDATAP_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDATAP */ #define _I2C_RXDATAP_MASK 0x000000FFUL /**< Mask for I2C_RXDATAP */ #define _I2C_RXDATAP_RXDATAP_SHIFT 0 /**< Shift value for I2C_RXDATAP */ #define _I2C_RXDATAP_RXDATAP_MASK 0xFFUL /**< Bit mask for I2C_RXDATAP */ #define _I2C_RXDATAP_RXDATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDATAP */ #define I2C_RXDATAP_RXDATAP_DEFAULT (_I2C_RXDATAP_RXDATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDATAP */ /* Bit fields for I2C RXDOUBLEP */ #define _I2C_RXDOUBLEP_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDOUBLEP */ #define _I2C_RXDOUBLEP_MASK 0x0000FFFFUL /**< Mask for I2C_RXDOUBLEP */ #define _I2C_RXDOUBLEP_RXDATAP0_SHIFT 0 /**< Shift value for I2C_RXDATAP0 */ #define _I2C_RXDOUBLEP_RXDATAP0_MASK 0xFFUL /**< Bit mask for I2C_RXDATAP0 */ #define _I2C_RXDOUBLEP_RXDATAP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLEP */ #define I2C_RXDOUBLEP_RXDATAP0_DEFAULT (_I2C_RXDOUBLEP_RXDATAP0_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDOUBLEP */ #define _I2C_RXDOUBLEP_RXDATAP1_SHIFT 8 /**< Shift value for I2C_RXDATAP1 */ #define _I2C_RXDOUBLEP_RXDATAP1_MASK 0xFF00UL /**< Bit mask for I2C_RXDATAP1 */ #define _I2C_RXDOUBLEP_RXDATAP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLEP */ #define I2C_RXDOUBLEP_RXDATAP1_DEFAULT (_I2C_RXDOUBLEP_RXDATAP1_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_RXDOUBLEP */ /* Bit fields for I2C TXDATA */ #define _I2C_TXDATA_RESETVALUE 0x00000000UL /**< Default value for I2C_TXDATA */ #define _I2C_TXDATA_MASK 0x000000FFUL /**< Mask for I2C_TXDATA */ #define _I2C_TXDATA_TXDATA_SHIFT 0 /**< Shift value for I2C_TXDATA */ #define _I2C_TXDATA_TXDATA_MASK 0xFFUL /**< Bit mask for I2C_TXDATA */ #define _I2C_TXDATA_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_TXDATA */ #define I2C_TXDATA_TXDATA_DEFAULT (_I2C_TXDATA_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_TXDATA */ /* Bit fields for I2C TXDOUBLE */ #define _I2C_TXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for I2C_TXDOUBLE */ #define _I2C_TXDOUBLE_MASK 0x0000FFFFUL /**< Mask for I2C_TXDOUBLE */ #define _I2C_TXDOUBLE_TXDATA0_SHIFT 0 /**< Shift value for I2C_TXDATA0 */ #define _I2C_TXDOUBLE_TXDATA0_MASK 0xFFUL /**< Bit mask for I2C_TXDATA0 */ #define _I2C_TXDOUBLE_TXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_TXDOUBLE */ #define I2C_TXDOUBLE_TXDATA0_DEFAULT (_I2C_TXDOUBLE_TXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_TXDOUBLE */ #define _I2C_TXDOUBLE_TXDATA1_SHIFT 8 /**< Shift value for I2C_TXDATA1 */ #define _I2C_TXDOUBLE_TXDATA1_MASK 0xFF00UL /**< Bit mask for I2C_TXDATA1 */ #define _I2C_TXDOUBLE_TXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_TXDOUBLE */ #define I2C_TXDOUBLE_TXDATA1_DEFAULT (_I2C_TXDOUBLE_TXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_TXDOUBLE */ /* Bit fields for I2C IF */ #define _I2C_IF_RESETVALUE 0x00000010UL /**< Default value for I2C_IF */ #define _I2C_IF_MASK 0x0007FFFFUL /**< Mask for I2C_IF */ #define I2C_IF_START (0x1UL << 0) /**< START Condition Interrupt Flag */ #define _I2C_IF_START_SHIFT 0 /**< Shift value for I2C_START */ #define _I2C_IF_START_MASK 0x1UL /**< Bit mask for I2C_START */ #define _I2C_IF_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ #define I2C_IF_START_DEFAULT (_I2C_IF_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IF */ #define I2C_IF_RSTART (0x1UL << 1) /**< Repeated START Condition Interrupt Flag */ #define _I2C_IF_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */ #define _I2C_IF_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */ #define _I2C_IF_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ #define I2C_IF_RSTART_DEFAULT (_I2C_IF_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IF */ #define I2C_IF_ADDR (0x1UL << 2) /**< Address Interrupt Flag */ #define _I2C_IF_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */ #define _I2C_IF_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */ #define _I2C_IF_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ #define I2C_IF_ADDR_DEFAULT (_I2C_IF_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IF */ #define I2C_IF_TXC (0x1UL << 3) /**< Transfer Completed Interrupt Flag */ #define _I2C_IF_TXC_SHIFT 3 /**< Shift value for I2C_TXC */ #define _I2C_IF_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */ #define _I2C_IF_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ #define I2C_IF_TXC_DEFAULT (_I2C_IF_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IF */ #define I2C_IF_TXBL (0x1UL << 4) /**< Transmit Buffer Level Interrupt Flag */ #define _I2C_IF_TXBL_SHIFT 4 /**< Shift value for I2C_TXBL */ #define _I2C_IF_TXBL_MASK 0x10UL /**< Bit mask for I2C_TXBL */ #define _I2C_IF_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for I2C_IF */ #define I2C_IF_TXBL_DEFAULT (_I2C_IF_TXBL_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_IF */ #define I2C_IF_RXDATAV (0x1UL << 5) /**< Receive Data Valid Interrupt Flag */ #define _I2C_IF_RXDATAV_SHIFT 5 /**< Shift value for I2C_RXDATAV */ #define _I2C_IF_RXDATAV_MASK 0x20UL /**< Bit mask for I2C_RXDATAV */ #define _I2C_IF_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ #define I2C_IF_RXDATAV_DEFAULT (_I2C_IF_RXDATAV_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_IF */ #define I2C_IF_ACK (0x1UL << 6) /**< Acknowledge Received Interrupt Flag */ #define _I2C_IF_ACK_SHIFT 6 /**< Shift value for I2C_ACK */ #define _I2C_IF_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */ #define _I2C_IF_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ #define I2C_IF_ACK_DEFAULT (_I2C_IF_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IF */ #define I2C_IF_NACK (0x1UL << 7) /**< Not Acknowledge Received Interrupt Flag */ #define _I2C_IF_NACK_SHIFT 7 /**< Shift value for I2C_NACK */ #define _I2C_IF_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */ #define _I2C_IF_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ #define I2C_IF_NACK_DEFAULT (_I2C_IF_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IF */ #define I2C_IF_MSTOP (0x1UL << 8) /**< Master STOP Condition Interrupt Flag */ #define _I2C_IF_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */ #define _I2C_IF_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */ #define _I2C_IF_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ #define I2C_IF_MSTOP_DEFAULT (_I2C_IF_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IF */ #define I2C_IF_ARBLOST (0x1UL << 9) /**< Arbitration Lost Interrupt Flag */ #define _I2C_IF_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */ #define _I2C_IF_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */ #define _I2C_IF_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ #define I2C_IF_ARBLOST_DEFAULT (_I2C_IF_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IF */ #define I2C_IF_BUSERR (0x1UL << 10) /**< Bus Error Interrupt Flag */ #define _I2C_IF_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */ #define _I2C_IF_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */ #define _I2C_IF_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ #define I2C_IF_BUSERR_DEFAULT (_I2C_IF_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IF */ #define I2C_IF_BUSHOLD (0x1UL << 11) /**< Bus Held Interrupt Flag */ #define _I2C_IF_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */ #define _I2C_IF_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */ #define _I2C_IF_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ #define I2C_IF_BUSHOLD_DEFAULT (_I2C_IF_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IF */ #define I2C_IF_TXOF (0x1UL << 12) /**< Transmit Buffer Overflow Interrupt Flag */ #define _I2C_IF_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */ #define _I2C_IF_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */ #define _I2C_IF_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ #define I2C_IF_TXOF_DEFAULT (_I2C_IF_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IF */ #define I2C_IF_RXUF (0x1UL << 13) /**< Receive Buffer Underflow Interrupt Flag */ #define _I2C_IF_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */ #define _I2C_IF_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */ #define _I2C_IF_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ #define I2C_IF_RXUF_DEFAULT (_I2C_IF_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IF */ #define I2C_IF_BITO (0x1UL << 14) /**< Bus Idle Timeout Interrupt Flag */ #define _I2C_IF_BITO_SHIFT 14 /**< Shift value for I2C_BITO */ #define _I2C_IF_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */ #define _I2C_IF_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ #define I2C_IF_BITO_DEFAULT (_I2C_IF_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IF */ #define I2C_IF_CLTO (0x1UL << 15) /**< Clock Low Timeout Interrupt Flag */ #define _I2C_IF_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */ #define _I2C_IF_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */ #define _I2C_IF_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ #define I2C_IF_CLTO_DEFAULT (_I2C_IF_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IF */ #define I2C_IF_SSTOP (0x1UL << 16) /**< Slave STOP Condition Interrupt Flag */ #define _I2C_IF_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */ #define _I2C_IF_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */ #define _I2C_IF_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ #define I2C_IF_SSTOP_DEFAULT (_I2C_IF_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IF */ #define I2C_IF_RXFULL (0x1UL << 17) /**< Receive Buffer Full Interrupt Flag */ #define _I2C_IF_RXFULL_SHIFT 17 /**< Shift value for I2C_RXFULL */ #define _I2C_IF_RXFULL_MASK 0x20000UL /**< Bit mask for I2C_RXFULL */ #define _I2C_IF_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ #define I2C_IF_RXFULL_DEFAULT (_I2C_IF_RXFULL_DEFAULT << 17) /**< Shifted mode DEFAULT for I2C_IF */ #define I2C_IF_CLERR (0x1UL << 18) /**< Clock Low Error Interrupt Flag */ #define _I2C_IF_CLERR_SHIFT 18 /**< Shift value for I2C_CLERR */ #define _I2C_IF_CLERR_MASK 0x40000UL /**< Bit mask for I2C_CLERR */ #define _I2C_IF_CLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ #define I2C_IF_CLERR_DEFAULT (_I2C_IF_CLERR_DEFAULT << 18) /**< Shifted mode DEFAULT for I2C_IF */ /* Bit fields for I2C IFS */ #define _I2C_IFS_RESETVALUE 0x00000000UL /**< Default value for I2C_IFS */ #define _I2C_IFS_MASK 0x0007FFCFUL /**< Mask for I2C_IFS */ #define I2C_IFS_START (0x1UL << 0) /**< Set START Interrupt Flag */ #define _I2C_IFS_START_SHIFT 0 /**< Shift value for I2C_START */ #define _I2C_IFS_START_MASK 0x1UL /**< Bit mask for I2C_START */ #define _I2C_IFS_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ #define I2C_IFS_START_DEFAULT (_I2C_IFS_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IFS */ #define I2C_IFS_RSTART (0x1UL << 1) /**< Set RSTART Interrupt Flag */ #define _I2C_IFS_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */ #define _I2C_IFS_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */ #define _I2C_IFS_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ #define I2C_IFS_RSTART_DEFAULT (_I2C_IFS_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IFS */ #define I2C_IFS_ADDR (0x1UL << 2) /**< Set ADDR Interrupt Flag */ #define _I2C_IFS_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */ #define _I2C_IFS_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */ #define _I2C_IFS_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ #define I2C_IFS_ADDR_DEFAULT (_I2C_IFS_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IFS */ #define I2C_IFS_TXC (0x1UL << 3) /**< Set TXC Interrupt Flag */ #define _I2C_IFS_TXC_SHIFT 3 /**< Shift value for I2C_TXC */ #define _I2C_IFS_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */ #define _I2C_IFS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ #define I2C_IFS_TXC_DEFAULT (_I2C_IFS_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IFS */ #define I2C_IFS_ACK (0x1UL << 6) /**< Set ACK Interrupt Flag */ #define _I2C_IFS_ACK_SHIFT 6 /**< Shift value for I2C_ACK */ #define _I2C_IFS_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */ #define _I2C_IFS_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ #define I2C_IFS_ACK_DEFAULT (_I2C_IFS_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IFS */ #define I2C_IFS_NACK (0x1UL << 7) /**< Set NACK Interrupt Flag */ #define _I2C_IFS_NACK_SHIFT 7 /**< Shift value for I2C_NACK */ #define _I2C_IFS_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */ #define _I2C_IFS_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ #define I2C_IFS_NACK_DEFAULT (_I2C_IFS_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IFS */ #define I2C_IFS_MSTOP (0x1UL << 8) /**< Set MSTOP Interrupt Flag */ #define _I2C_IFS_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */ #define _I2C_IFS_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */ #define _I2C_IFS_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ #define I2C_IFS_MSTOP_DEFAULT (_I2C_IFS_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IFS */ #define I2C_IFS_ARBLOST (0x1UL << 9) /**< Set ARBLOST Interrupt Flag */ #define _I2C_IFS_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */ #define _I2C_IFS_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */ #define _I2C_IFS_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ #define I2C_IFS_ARBLOST_DEFAULT (_I2C_IFS_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IFS */ #define I2C_IFS_BUSERR (0x1UL << 10) /**< Set BUSERR Interrupt Flag */ #define _I2C_IFS_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */ #define _I2C_IFS_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */ #define _I2C_IFS_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ #define I2C_IFS_BUSERR_DEFAULT (_I2C_IFS_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IFS */ #define I2C_IFS_BUSHOLD (0x1UL << 11) /**< Set BUSHOLD Interrupt Flag */ #define _I2C_IFS_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */ #define _I2C_IFS_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */ #define _I2C_IFS_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ #define I2C_IFS_BUSHOLD_DEFAULT (_I2C_IFS_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IFS */ #define I2C_IFS_TXOF (0x1UL << 12) /**< Set TXOF Interrupt Flag */ #define _I2C_IFS_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */ #define _I2C_IFS_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */ #define _I2C_IFS_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ #define I2C_IFS_TXOF_DEFAULT (_I2C_IFS_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IFS */ #define I2C_IFS_RXUF (0x1UL << 13) /**< Set RXUF Interrupt Flag */ #define _I2C_IFS_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */ #define _I2C_IFS_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */ #define _I2C_IFS_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ #define I2C_IFS_RXUF_DEFAULT (_I2C_IFS_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IFS */ #define I2C_IFS_BITO (0x1UL << 14) /**< Set BITO Interrupt Flag */ #define _I2C_IFS_BITO_SHIFT 14 /**< Shift value for I2C_BITO */ #define _I2C_IFS_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */ #define _I2C_IFS_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ #define I2C_IFS_BITO_DEFAULT (_I2C_IFS_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IFS */ #define I2C_IFS_CLTO (0x1UL << 15) /**< Set CLTO Interrupt Flag */ #define _I2C_IFS_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */ #define _I2C_IFS_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */ #define _I2C_IFS_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ #define I2C_IFS_CLTO_DEFAULT (_I2C_IFS_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IFS */ #define I2C_IFS_SSTOP (0x1UL << 16) /**< Set SSTOP Interrupt Flag */ #define _I2C_IFS_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */ #define _I2C_IFS_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */ #define _I2C_IFS_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ #define I2C_IFS_SSTOP_DEFAULT (_I2C_IFS_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IFS */ #define I2C_IFS_RXFULL (0x1UL << 17) /**< Set RXFULL Interrupt Flag */ #define _I2C_IFS_RXFULL_SHIFT 17 /**< Shift value for I2C_RXFULL */ #define _I2C_IFS_RXFULL_MASK 0x20000UL /**< Bit mask for I2C_RXFULL */ #define _I2C_IFS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ #define I2C_IFS_RXFULL_DEFAULT (_I2C_IFS_RXFULL_DEFAULT << 17) /**< Shifted mode DEFAULT for I2C_IFS */ #define I2C_IFS_CLERR (0x1UL << 18) /**< Set CLERR Interrupt Flag */ #define _I2C_IFS_CLERR_SHIFT 18 /**< Shift value for I2C_CLERR */ #define _I2C_IFS_CLERR_MASK 0x40000UL /**< Bit mask for I2C_CLERR */ #define _I2C_IFS_CLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ #define I2C_IFS_CLERR_DEFAULT (_I2C_IFS_CLERR_DEFAULT << 18) /**< Shifted mode DEFAULT for I2C_IFS */ /* Bit fields for I2C IFC */ #define _I2C_IFC_RESETVALUE 0x00000000UL /**< Default value for I2C_IFC */ #define _I2C_IFC_MASK 0x0007FFCFUL /**< Mask for I2C_IFC */ #define I2C_IFC_START (0x1UL << 0) /**< Clear START Interrupt Flag */ #define _I2C_IFC_START_SHIFT 0 /**< Shift value for I2C_START */ #define _I2C_IFC_START_MASK 0x1UL /**< Bit mask for I2C_START */ #define _I2C_IFC_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ #define I2C_IFC_START_DEFAULT (_I2C_IFC_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IFC */ #define I2C_IFC_RSTART (0x1UL << 1) /**< Clear RSTART Interrupt Flag */ #define _I2C_IFC_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */ #define _I2C_IFC_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */ #define _I2C_IFC_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ #define I2C_IFC_RSTART_DEFAULT (_I2C_IFC_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IFC */ #define I2C_IFC_ADDR (0x1UL << 2) /**< Clear ADDR Interrupt Flag */ #define _I2C_IFC_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */ #define _I2C_IFC_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */ #define _I2C_IFC_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ #define I2C_IFC_ADDR_DEFAULT (_I2C_IFC_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IFC */ #define I2C_IFC_TXC (0x1UL << 3) /**< Clear TXC Interrupt Flag */ #define _I2C_IFC_TXC_SHIFT 3 /**< Shift value for I2C_TXC */ #define _I2C_IFC_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */ #define _I2C_IFC_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ #define I2C_IFC_TXC_DEFAULT (_I2C_IFC_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IFC */ #define I2C_IFC_ACK (0x1UL << 6) /**< Clear ACK Interrupt Flag */ #define _I2C_IFC_ACK_SHIFT 6 /**< Shift value for I2C_ACK */ #define _I2C_IFC_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */ #define _I2C_IFC_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ #define I2C_IFC_ACK_DEFAULT (_I2C_IFC_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IFC */ #define I2C_IFC_NACK (0x1UL << 7) /**< Clear NACK Interrupt Flag */ #define _I2C_IFC_NACK_SHIFT 7 /**< Shift value for I2C_NACK */ #define _I2C_IFC_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */ #define _I2C_IFC_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ #define I2C_IFC_NACK_DEFAULT (_I2C_IFC_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IFC */ #define I2C_IFC_MSTOP (0x1UL << 8) /**< Clear MSTOP Interrupt Flag */ #define _I2C_IFC_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */ #define _I2C_IFC_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */ #define _I2C_IFC_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ #define I2C_IFC_MSTOP_DEFAULT (_I2C_IFC_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IFC */ #define I2C_IFC_ARBLOST (0x1UL << 9) /**< Clear ARBLOST Interrupt Flag */ #define _I2C_IFC_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */ #define _I2C_IFC_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */ #define _I2C_IFC_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ #define I2C_IFC_ARBLOST_DEFAULT (_I2C_IFC_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IFC */ #define I2C_IFC_BUSERR (0x1UL << 10) /**< Clear BUSERR Interrupt Flag */ #define _I2C_IFC_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */ #define _I2C_IFC_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */ #define _I2C_IFC_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ #define I2C_IFC_BUSERR_DEFAULT (_I2C_IFC_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IFC */ #define I2C_IFC_BUSHOLD (0x1UL << 11) /**< Clear BUSHOLD Interrupt Flag */ #define _I2C_IFC_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */ #define _I2C_IFC_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */ #define _I2C_IFC_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ #define I2C_IFC_BUSHOLD_DEFAULT (_I2C_IFC_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IFC */ #define I2C_IFC_TXOF (0x1UL << 12) /**< Clear TXOF Interrupt Flag */ #define _I2C_IFC_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */ #define _I2C_IFC_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */ #define _I2C_IFC_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ #define I2C_IFC_TXOF_DEFAULT (_I2C_IFC_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IFC */ #define I2C_IFC_RXUF (0x1UL << 13) /**< Clear RXUF Interrupt Flag */ #define _I2C_IFC_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */ #define _I2C_IFC_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */ #define _I2C_IFC_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ #define I2C_IFC_RXUF_DEFAULT (_I2C_IFC_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IFC */ #define I2C_IFC_BITO (0x1UL << 14) /**< Clear BITO Interrupt Flag */ #define _I2C_IFC_BITO_SHIFT 14 /**< Shift value for I2C_BITO */ #define _I2C_IFC_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */ #define _I2C_IFC_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ #define I2C_IFC_BITO_DEFAULT (_I2C_IFC_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IFC */ #define I2C_IFC_CLTO (0x1UL << 15) /**< Clear CLTO Interrupt Flag */ #define _I2C_IFC_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */ #define _I2C_IFC_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */ #define _I2C_IFC_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ #define I2C_IFC_CLTO_DEFAULT (_I2C_IFC_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IFC */ #define I2C_IFC_SSTOP (0x1UL << 16) /**< Clear SSTOP Interrupt Flag */ #define _I2C_IFC_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */ #define _I2C_IFC_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */ #define _I2C_IFC_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ #define I2C_IFC_SSTOP_DEFAULT (_I2C_IFC_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IFC */ #define I2C_IFC_RXFULL (0x1UL << 17) /**< Clear RXFULL Interrupt Flag */ #define _I2C_IFC_RXFULL_SHIFT 17 /**< Shift value for I2C_RXFULL */ #define _I2C_IFC_RXFULL_MASK 0x20000UL /**< Bit mask for I2C_RXFULL */ #define _I2C_IFC_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ #define I2C_IFC_RXFULL_DEFAULT (_I2C_IFC_RXFULL_DEFAULT << 17) /**< Shifted mode DEFAULT for I2C_IFC */ #define I2C_IFC_CLERR (0x1UL << 18) /**< Clear CLERR Interrupt Flag */ #define _I2C_IFC_CLERR_SHIFT 18 /**< Shift value for I2C_CLERR */ #define _I2C_IFC_CLERR_MASK 0x40000UL /**< Bit mask for I2C_CLERR */ #define _I2C_IFC_CLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ #define I2C_IFC_CLERR_DEFAULT (_I2C_IFC_CLERR_DEFAULT << 18) /**< Shifted mode DEFAULT for I2C_IFC */ /* Bit fields for I2C IEN */ #define _I2C_IEN_RESETVALUE 0x00000000UL /**< Default value for I2C_IEN */ #define _I2C_IEN_MASK 0x0007FFFFUL /**< Mask for I2C_IEN */ #define I2C_IEN_START (0x1UL << 0) /**< START Interrupt Enable */ #define _I2C_IEN_START_SHIFT 0 /**< Shift value for I2C_START */ #define _I2C_IEN_START_MASK 0x1UL /**< Bit mask for I2C_START */ #define _I2C_IEN_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ #define I2C_IEN_START_DEFAULT (_I2C_IEN_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IEN */ #define I2C_IEN_RSTART (0x1UL << 1) /**< RSTART Interrupt Enable */ #define _I2C_IEN_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */ #define _I2C_IEN_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */ #define _I2C_IEN_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ #define I2C_IEN_RSTART_DEFAULT (_I2C_IEN_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IEN */ #define I2C_IEN_ADDR (0x1UL << 2) /**< ADDR Interrupt Enable */ #define _I2C_IEN_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */ #define _I2C_IEN_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */ #define _I2C_IEN_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ #define I2C_IEN_ADDR_DEFAULT (_I2C_IEN_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IEN */ #define I2C_IEN_TXC (0x1UL << 3) /**< TXC Interrupt Enable */ #define _I2C_IEN_TXC_SHIFT 3 /**< Shift value for I2C_TXC */ #define _I2C_IEN_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */ #define _I2C_IEN_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ #define I2C_IEN_TXC_DEFAULT (_I2C_IEN_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IEN */ #define I2C_IEN_TXBL (0x1UL << 4) /**< TXBL Interrupt Enable */ #define _I2C_IEN_TXBL_SHIFT 4 /**< Shift value for I2C_TXBL */ #define _I2C_IEN_TXBL_MASK 0x10UL /**< Bit mask for I2C_TXBL */ #define _I2C_IEN_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ #define I2C_IEN_TXBL_DEFAULT (_I2C_IEN_TXBL_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_IEN */ #define I2C_IEN_RXDATAV (0x1UL << 5) /**< RXDATAV Interrupt Enable */ #define _I2C_IEN_RXDATAV_SHIFT 5 /**< Shift value for I2C_RXDATAV */ #define _I2C_IEN_RXDATAV_MASK 0x20UL /**< Bit mask for I2C_RXDATAV */ #define _I2C_IEN_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ #define I2C_IEN_RXDATAV_DEFAULT (_I2C_IEN_RXDATAV_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_IEN */ #define I2C_IEN_ACK (0x1UL << 6) /**< ACK Interrupt Enable */ #define _I2C_IEN_ACK_SHIFT 6 /**< Shift value for I2C_ACK */ #define _I2C_IEN_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */ #define _I2C_IEN_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ #define I2C_IEN_ACK_DEFAULT (_I2C_IEN_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IEN */ #define I2C_IEN_NACK (0x1UL << 7) /**< NACK Interrupt Enable */ #define _I2C_IEN_NACK_SHIFT 7 /**< Shift value for I2C_NACK */ #define _I2C_IEN_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */ #define _I2C_IEN_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ #define I2C_IEN_NACK_DEFAULT (_I2C_IEN_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IEN */ #define I2C_IEN_MSTOP (0x1UL << 8) /**< MSTOP Interrupt Enable */ #define _I2C_IEN_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */ #define _I2C_IEN_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */ #define _I2C_IEN_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ #define I2C_IEN_MSTOP_DEFAULT (_I2C_IEN_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IEN */ #define I2C_IEN_ARBLOST (0x1UL << 9) /**< ARBLOST Interrupt Enable */ #define _I2C_IEN_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */ #define _I2C_IEN_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */ #define _I2C_IEN_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ #define I2C_IEN_ARBLOST_DEFAULT (_I2C_IEN_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IEN */ #define I2C_IEN_BUSERR (0x1UL << 10) /**< BUSERR Interrupt Enable */ #define _I2C_IEN_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */ #define _I2C_IEN_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */ #define _I2C_IEN_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ #define I2C_IEN_BUSERR_DEFAULT (_I2C_IEN_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IEN */ #define I2C_IEN_BUSHOLD (0x1UL << 11) /**< BUSHOLD Interrupt Enable */ #define _I2C_IEN_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */ #define _I2C_IEN_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */ #define _I2C_IEN_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ #define I2C_IEN_BUSHOLD_DEFAULT (_I2C_IEN_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IEN */ #define I2C_IEN_TXOF (0x1UL << 12) /**< TXOF Interrupt Enable */ #define _I2C_IEN_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */ #define _I2C_IEN_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */ #define _I2C_IEN_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ #define I2C_IEN_TXOF_DEFAULT (_I2C_IEN_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IEN */ #define I2C_IEN_RXUF (0x1UL << 13) /**< RXUF Interrupt Enable */ #define _I2C_IEN_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */ #define _I2C_IEN_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */ #define _I2C_IEN_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ #define I2C_IEN_RXUF_DEFAULT (_I2C_IEN_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IEN */ #define I2C_IEN_BITO (0x1UL << 14) /**< BITO Interrupt Enable */ #define _I2C_IEN_BITO_SHIFT 14 /**< Shift value for I2C_BITO */ #define _I2C_IEN_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */ #define _I2C_IEN_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ #define I2C_IEN_BITO_DEFAULT (_I2C_IEN_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IEN */ #define I2C_IEN_CLTO (0x1UL << 15) /**< CLTO Interrupt Enable */ #define _I2C_IEN_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */ #define _I2C_IEN_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */ #define _I2C_IEN_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ #define I2C_IEN_CLTO_DEFAULT (_I2C_IEN_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IEN */ #define I2C_IEN_SSTOP (0x1UL << 16) /**< SSTOP Interrupt Enable */ #define _I2C_IEN_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */ #define _I2C_IEN_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */ #define _I2C_IEN_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ #define I2C_IEN_SSTOP_DEFAULT (_I2C_IEN_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IEN */ #define I2C_IEN_RXFULL (0x1UL << 17) /**< RXFULL Interrupt Enable */ #define _I2C_IEN_RXFULL_SHIFT 17 /**< Shift value for I2C_RXFULL */ #define _I2C_IEN_RXFULL_MASK 0x20000UL /**< Bit mask for I2C_RXFULL */ #define _I2C_IEN_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ #define I2C_IEN_RXFULL_DEFAULT (_I2C_IEN_RXFULL_DEFAULT << 17) /**< Shifted mode DEFAULT for I2C_IEN */ #define I2C_IEN_CLERR (0x1UL << 18) /**< CLERR Interrupt Enable */ #define _I2C_IEN_CLERR_SHIFT 18 /**< Shift value for I2C_CLERR */ #define _I2C_IEN_CLERR_MASK 0x40000UL /**< Bit mask for I2C_CLERR */ #define _I2C_IEN_CLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ #define I2C_IEN_CLERR_DEFAULT (_I2C_IEN_CLERR_DEFAULT << 18) /**< Shifted mode DEFAULT for I2C_IEN */ /* Bit fields for I2C ROUTEPEN */ #define _I2C_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for I2C_ROUTEPEN */ #define _I2C_ROUTEPEN_MASK 0x00000003UL /**< Mask for I2C_ROUTEPEN */ #define I2C_ROUTEPEN_SDAPEN (0x1UL << 0) /**< SDA Pin Enable */ #define _I2C_ROUTEPEN_SDAPEN_SHIFT 0 /**< Shift value for I2C_SDAPEN */ #define _I2C_ROUTEPEN_SDAPEN_MASK 0x1UL /**< Bit mask for I2C_SDAPEN */ #define _I2C_ROUTEPEN_SDAPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_ROUTEPEN */ #define I2C_ROUTEPEN_SDAPEN_DEFAULT (_I2C_ROUTEPEN_SDAPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_ROUTEPEN */ #define I2C_ROUTEPEN_SCLPEN (0x1UL << 1) /**< SCL Pin Enable */ #define _I2C_ROUTEPEN_SCLPEN_SHIFT 1 /**< Shift value for I2C_SCLPEN */ #define _I2C_ROUTEPEN_SCLPEN_MASK 0x2UL /**< Bit mask for I2C_SCLPEN */ #define _I2C_ROUTEPEN_SCLPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_ROUTEPEN */ #define I2C_ROUTEPEN_SCLPEN_DEFAULT (_I2C_ROUTEPEN_SCLPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_ROUTEPEN */ /* Bit fields for I2C ROUTELOC0 */ #define _I2C_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for I2C_ROUTELOC0 */ #define _I2C_ROUTELOC0_MASK 0x00001F1FUL /**< Mask for I2C_ROUTELOC0 */ #define _I2C_ROUTELOC0_SDALOC_SHIFT 0 /**< Shift value for I2C_SDALOC */ #define _I2C_ROUTELOC0_SDALOC_MASK 0x1FUL /**< Bit mask for I2C_SDALOC */ #define _I2C_ROUTELOC0_SDALOC_LOC0 0x00000000UL /**< Mode LOC0 for I2C_ROUTELOC0 */ #define _I2C_ROUTELOC0_SDALOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_ROUTELOC0 */ #define _I2C_ROUTELOC0_SDALOC_LOC1 0x00000001UL /**< Mode LOC1 for I2C_ROUTELOC0 */ #define _I2C_ROUTELOC0_SDALOC_LOC2 0x00000002UL /**< Mode LOC2 for I2C_ROUTELOC0 */ #define _I2C_ROUTELOC0_SDALOC_LOC3 0x00000003UL /**< Mode LOC3 for I2C_ROUTELOC0 */ #define _I2C_ROUTELOC0_SDALOC_LOC4 0x00000004UL /**< Mode LOC4 for I2C_ROUTELOC0 */ #define _I2C_ROUTELOC0_SDALOC_LOC5 0x00000005UL /**< Mode LOC5 for I2C_ROUTELOC0 */ #define _I2C_ROUTELOC0_SDALOC_LOC6 0x00000006UL /**< Mode LOC6 for I2C_ROUTELOC0 */ #define _I2C_ROUTELOC0_SDALOC_LOC7 0x00000007UL /**< Mode LOC7 for I2C_ROUTELOC0 */ #define _I2C_ROUTELOC0_SDALOC_LOC8 0x00000008UL /**< Mode LOC8 for I2C_ROUTELOC0 */ #define _I2C_ROUTELOC0_SDALOC_LOC9 0x00000009UL /**< Mode LOC9 for I2C_ROUTELOC0 */ #define _I2C_ROUTELOC0_SDALOC_LOC10 0x0000000AUL /**< Mode LOC10 for I2C_ROUTELOC0 */ #define _I2C_ROUTELOC0_SDALOC_LOC11 0x0000000BUL /**< Mode LOC11 for I2C_ROUTELOC0 */ #define _I2C_ROUTELOC0_SDALOC_LOC12 0x0000000CUL /**< Mode LOC12 for I2C_ROUTELOC0 */ #define _I2C_ROUTELOC0_SDALOC_LOC13 0x0000000DUL /**< Mode LOC13 for I2C_ROUTELOC0 */ #define _I2C_ROUTELOC0_SDALOC_LOC14 0x0000000EUL /**< Mode LOC14 for I2C_ROUTELOC0 */ #define _I2C_ROUTELOC0_SDALOC_LOC15 0x0000000FUL /**< Mode LOC15 for I2C_ROUTELOC0 */ #define _I2C_ROUTELOC0_SDALOC_LOC16 0x00000010UL /**< Mode LOC16 for I2C_ROUTELOC0 */ #define _I2C_ROUTELOC0_SDALOC_LOC17 0x00000011UL /**< Mode LOC17 for I2C_ROUTELOC0 */ #define _I2C_ROUTELOC0_SDALOC_LOC18 0x00000012UL /**< Mode LOC18 for I2C_ROUTELOC0 */ #define _I2C_ROUTELOC0_SDALOC_LOC19 0x00000013UL /**< Mode LOC19 for I2C_ROUTELOC0 */ #define _I2C_ROUTELOC0_SDALOC_LOC20 0x00000014UL /**< Mode LOC20 for I2C_ROUTELOC0 */ #define _I2C_ROUTELOC0_SDALOC_LOC21 0x00000015UL /**< Mode LOC21 for I2C_ROUTELOC0 */ #define _I2C_ROUTELOC0_SDALOC_LOC22 0x00000016UL /**< Mode LOC22 for I2C_ROUTELOC0 */ #define _I2C_ROUTELOC0_SDALOC_LOC23 0x00000017UL /**< Mode LOC23 for I2C_ROUTELOC0 */ #define _I2C_ROUTELOC0_SDALOC_LOC24 0x00000018UL /**< Mode LOC24 for I2C_ROUTELOC0 */ #define _I2C_ROUTELOC0_SDALOC_LOC25 0x00000019UL /**< Mode LOC25 for I2C_ROUTELOC0 */ #define _I2C_ROUTELOC0_SDALOC_LOC26 0x0000001AUL /**< Mode LOC26 for I2C_ROUTELOC0 */ #define _I2C_ROUTELOC0_SDALOC_LOC27 0x0000001BUL /**< Mode LOC27 for I2C_ROUTELOC0 */ #define _I2C_ROUTELOC0_SDALOC_LOC28 0x0000001CUL /**< Mode LOC28 for I2C_ROUTELOC0 */ #define _I2C_ROUTELOC0_SDALOC_LOC29 0x0000001DUL /**< Mode LOC29 for I2C_ROUTELOC0 */ #define _I2C_ROUTELOC0_SDALOC_LOC30 0x0000001EUL /**< Mode LOC30 for I2C_ROUTELOC0 */ #define _I2C_ROUTELOC0_SDALOC_LOC31 0x0000001FUL /**< Mode LOC31 for I2C_ROUTELOC0 */ #define I2C_ROUTELOC0_SDALOC_LOC0 (_I2C_ROUTELOC0_SDALOC_LOC0 << 0) /**< Shifted mode LOC0 for I2C_ROUTELOC0 */ #define I2C_ROUTELOC0_SDALOC_DEFAULT (_I2C_ROUTELOC0_SDALOC_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_ROUTELOC0 */ #define I2C_ROUTELOC0_SDALOC_LOC1 (_I2C_ROUTELOC0_SDALOC_LOC1 << 0) /**< Shifted mode LOC1 for I2C_ROUTELOC0 */ #define I2C_ROUTELOC0_SDALOC_LOC2 (_I2C_ROUTELOC0_SDALOC_LOC2 << 0) /**< Shifted mode LOC2 for I2C_ROUTELOC0 */ #define I2C_ROUTELOC0_SDALOC_LOC3 (_I2C_ROUTELOC0_SDALOC_LOC3 << 0) /**< Shifted mode LOC3 for I2C_ROUTELOC0 */ #define I2C_ROUTELOC0_SDALOC_LOC4 (_I2C_ROUTELOC0_SDALOC_LOC4 << 0) /**< Shifted mode LOC4 for I2C_ROUTELOC0 */ #define I2C_ROUTELOC0_SDALOC_LOC5 (_I2C_ROUTELOC0_SDALOC_LOC5 << 0) /**< Shifted mode LOC5 for I2C_ROUTELOC0 */ #define I2C_ROUTELOC0_SDALOC_LOC6 (_I2C_ROUTELOC0_SDALOC_LOC6 << 0) /**< Shifted mode LOC6 for I2C_ROUTELOC0 */ #define I2C_ROUTELOC0_SDALOC_LOC7 (_I2C_ROUTELOC0_SDALOC_LOC7 << 0) /**< Shifted mode LOC7 for I2C_ROUTELOC0 */ #define I2C_ROUTELOC0_SDALOC_LOC8 (_I2C_ROUTELOC0_SDALOC_LOC8 << 0) /**< Shifted mode LOC8 for I2C_ROUTELOC0 */ #define I2C_ROUTELOC0_SDALOC_LOC9 (_I2C_ROUTELOC0_SDALOC_LOC9 << 0) /**< Shifted mode LOC9 for I2C_ROUTELOC0 */ #define I2C_ROUTELOC0_SDALOC_LOC10 (_I2C_ROUTELOC0_SDALOC_LOC10 << 0) /**< Shifted mode LOC10 for I2C_ROUTELOC0 */ #define I2C_ROUTELOC0_SDALOC_LOC11 (_I2C_ROUTELOC0_SDALOC_LOC11 << 0) /**< Shifted mode LOC11 for I2C_ROUTELOC0 */ #define I2C_ROUTELOC0_SDALOC_LOC12 (_I2C_ROUTELOC0_SDALOC_LOC12 << 0) /**< Shifted mode LOC12 for I2C_ROUTELOC0 */ #define I2C_ROUTELOC0_SDALOC_LOC13 (_I2C_ROUTELOC0_SDALOC_LOC13 << 0) /**< Shifted mode LOC13 for I2C_ROUTELOC0 */ #define I2C_ROUTELOC0_SDALOC_LOC14 (_I2C_ROUTELOC0_SDALOC_LOC14 << 0) /**< Shifted mode LOC14 for I2C_ROUTELOC0 */ #define I2C_ROUTELOC0_SDALOC_LOC15 (_I2C_ROUTELOC0_SDALOC_LOC15 << 0) /**< Shifted mode LOC15 for I2C_ROUTELOC0 */ #define I2C_ROUTELOC0_SDALOC_LOC16 (_I2C_ROUTELOC0_SDALOC_LOC16 << 0) /**< Shifted mode LOC16 for I2C_ROUTELOC0 */ #define I2C_ROUTELOC0_SDALOC_LOC17 (_I2C_ROUTELOC0_SDALOC_LOC17 << 0) /**< Shifted mode LOC17 for I2C_ROUTELOC0 */ #define I2C_ROUTELOC0_SDALOC_LOC18 (_I2C_ROUTELOC0_SDALOC_LOC18 << 0) /**< Shifted mode LOC18 for I2C_ROUTELOC0 */ #define I2C_ROUTELOC0_SDALOC_LOC19 (_I2C_ROUTELOC0_SDALOC_LOC19 << 0) /**< Shifted mode LOC19 for I2C_ROUTELOC0 */ #define I2C_ROUTELOC0_SDALOC_LOC20 (_I2C_ROUTELOC0_SDALOC_LOC20 << 0) /**< Shifted mode LOC20 for I2C_ROUTELOC0 */ #define I2C_ROUTELOC0_SDALOC_LOC21 (_I2C_ROUTELOC0_SDALOC_LOC21 << 0) /**< Shifted mode LOC21 for I2C_ROUTELOC0 */ #define I2C_ROUTELOC0_SDALOC_LOC22 (_I2C_ROUTELOC0_SDALOC_LOC22 << 0) /**< Shifted mode LOC22 for I2C_ROUTELOC0 */ #define I2C_ROUTELOC0_SDALOC_LOC23 (_I2C_ROUTELOC0_SDALOC_LOC23 << 0) /**< Shifted mode LOC23 for I2C_ROUTELOC0 */ #define I2C_ROUTELOC0_SDALOC_LOC24 (_I2C_ROUTELOC0_SDALOC_LOC24 << 0) /**< Shifted mode LOC24 for I2C_ROUTELOC0 */ #define I2C_ROUTELOC0_SDALOC_LOC25 (_I2C_ROUTELOC0_SDALOC_LOC25 << 0) /**< Shifted mode LOC25 for I2C_ROUTELOC0 */ #define I2C_ROUTELOC0_SDALOC_LOC26 (_I2C_ROUTELOC0_SDALOC_LOC26 << 0) /**< Shifted mode LOC26 for I2C_ROUTELOC0 */ #define I2C_ROUTELOC0_SDALOC_LOC27 (_I2C_ROUTELOC0_SDALOC_LOC27 << 0) /**< Shifted mode LOC27 for I2C_ROUTELOC0 */ #define I2C_ROUTELOC0_SDALOC_LOC28 (_I2C_ROUTELOC0_SDALOC_LOC28 << 0) /**< Shifted mode LOC28 for I2C_ROUTELOC0 */ #define I2C_ROUTELOC0_SDALOC_LOC29 (_I2C_ROUTELOC0_SDALOC_LOC29 << 0) /**< Shifted mode LOC29 for I2C_ROUTELOC0 */ #define I2C_ROUTELOC0_SDALOC_LOC30 (_I2C_ROUTELOC0_SDALOC_LOC30 << 0) /**< Shifted mode LOC30 for I2C_ROUTELOC0 */ #define I2C_ROUTELOC0_SDALOC_LOC31 (_I2C_ROUTELOC0_SDALOC_LOC31 << 0) /**< Shifted mode LOC31 for I2C_ROUTELOC0 */ #define _I2C_ROUTELOC0_SCLLOC_SHIFT 8 /**< Shift value for I2C_SCLLOC */ #define _I2C_ROUTELOC0_SCLLOC_MASK 0x1F00UL /**< Bit mask for I2C_SCLLOC */ #define _I2C_ROUTELOC0_SCLLOC_LOC0 0x00000000UL /**< Mode LOC0 for I2C_ROUTELOC0 */ #define _I2C_ROUTELOC0_SCLLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_ROUTELOC0 */ #define _I2C_ROUTELOC0_SCLLOC_LOC1 0x00000001UL /**< Mode LOC1 for I2C_ROUTELOC0 */ #define _I2C_ROUTELOC0_SCLLOC_LOC2 0x00000002UL /**< Mode LOC2 for I2C_ROUTELOC0 */ #define _I2C_ROUTELOC0_SCLLOC_LOC3 0x00000003UL /**< Mode LOC3 for I2C_ROUTELOC0 */ #define _I2C_ROUTELOC0_SCLLOC_LOC4 0x00000004UL /**< Mode LOC4 for I2C_ROUTELOC0 */ #define _I2C_ROUTELOC0_SCLLOC_LOC5 0x00000005UL /**< Mode LOC5 for I2C_ROUTELOC0 */ #define _I2C_ROUTELOC0_SCLLOC_LOC6 0x00000006UL /**< Mode LOC6 for I2C_ROUTELOC0 */ #define _I2C_ROUTELOC0_SCLLOC_LOC7 0x00000007UL /**< Mode LOC7 for I2C_ROUTELOC0 */ #define _I2C_ROUTELOC0_SCLLOC_LOC8 0x00000008UL /**< Mode LOC8 for I2C_ROUTELOC0 */ #define _I2C_ROUTELOC0_SCLLOC_LOC9 0x00000009UL /**< Mode LOC9 for I2C_ROUTELOC0 */ #define _I2C_ROUTELOC0_SCLLOC_LOC10 0x0000000AUL /**< Mode LOC10 for I2C_ROUTELOC0 */ #define _I2C_ROUTELOC0_SCLLOC_LOC11 0x0000000BUL /**< Mode LOC11 for I2C_ROUTELOC0 */ #define _I2C_ROUTELOC0_SCLLOC_LOC12 0x0000000CUL /**< Mode LOC12 for I2C_ROUTELOC0 */ #define _I2C_ROUTELOC0_SCLLOC_LOC13 0x0000000DUL /**< Mode LOC13 for I2C_ROUTELOC0 */ #define _I2C_ROUTELOC0_SCLLOC_LOC14 0x0000000EUL /**< Mode LOC14 for I2C_ROUTELOC0 */ #define _I2C_ROUTELOC0_SCLLOC_LOC15 0x0000000FUL /**< Mode LOC15 for I2C_ROUTELOC0 */ #define _I2C_ROUTELOC0_SCLLOC_LOC16 0x00000010UL /**< Mode LOC16 for I2C_ROUTELOC0 */ #define _I2C_ROUTELOC0_SCLLOC_LOC17 0x00000011UL /**< Mode LOC17 for I2C_ROUTELOC0 */ #define _I2C_ROUTELOC0_SCLLOC_LOC18 0x00000012UL /**< Mode LOC18 for I2C_ROUTELOC0 */ #define _I2C_ROUTELOC0_SCLLOC_LOC19 0x00000013UL /**< Mode LOC19 for I2C_ROUTELOC0 */ #define _I2C_ROUTELOC0_SCLLOC_LOC20 0x00000014UL /**< Mode LOC20 for I2C_ROUTELOC0 */ #define _I2C_ROUTELOC0_SCLLOC_LOC21 0x00000015UL /**< Mode LOC21 for I2C_ROUTELOC0 */ #define _I2C_ROUTELOC0_SCLLOC_LOC22 0x00000016UL /**< Mode LOC22 for I2C_ROUTELOC0 */ #define _I2C_ROUTELOC0_SCLLOC_LOC23 0x00000017UL /**< Mode LOC23 for I2C_ROUTELOC0 */ #define _I2C_ROUTELOC0_SCLLOC_LOC24 0x00000018UL /**< Mode LOC24 for I2C_ROUTELOC0 */ #define _I2C_ROUTELOC0_SCLLOC_LOC25 0x00000019UL /**< Mode LOC25 for I2C_ROUTELOC0 */ #define _I2C_ROUTELOC0_SCLLOC_LOC26 0x0000001AUL /**< Mode LOC26 for I2C_ROUTELOC0 */ #define _I2C_ROUTELOC0_SCLLOC_LOC27 0x0000001BUL /**< Mode LOC27 for I2C_ROUTELOC0 */ #define _I2C_ROUTELOC0_SCLLOC_LOC28 0x0000001CUL /**< Mode LOC28 for I2C_ROUTELOC0 */ #define _I2C_ROUTELOC0_SCLLOC_LOC29 0x0000001DUL /**< Mode LOC29 for I2C_ROUTELOC0 */ #define _I2C_ROUTELOC0_SCLLOC_LOC30 0x0000001EUL /**< Mode LOC30 for I2C_ROUTELOC0 */ #define _I2C_ROUTELOC0_SCLLOC_LOC31 0x0000001FUL /**< Mode LOC31 for I2C_ROUTELOC0 */ #define I2C_ROUTELOC0_SCLLOC_LOC0 (_I2C_ROUTELOC0_SCLLOC_LOC0 << 8) /**< Shifted mode LOC0 for I2C_ROUTELOC0 */ #define I2C_ROUTELOC0_SCLLOC_DEFAULT (_I2C_ROUTELOC0_SCLLOC_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_ROUTELOC0 */ #define I2C_ROUTELOC0_SCLLOC_LOC1 (_I2C_ROUTELOC0_SCLLOC_LOC1 << 8) /**< Shifted mode LOC1 for I2C_ROUTELOC0 */ #define I2C_ROUTELOC0_SCLLOC_LOC2 (_I2C_ROUTELOC0_SCLLOC_LOC2 << 8) /**< Shifted mode LOC2 for I2C_ROUTELOC0 */ #define I2C_ROUTELOC0_SCLLOC_LOC3 (_I2C_ROUTELOC0_SCLLOC_LOC3 << 8) /**< Shifted mode LOC3 for I2C_ROUTELOC0 */ #define I2C_ROUTELOC0_SCLLOC_LOC4 (_I2C_ROUTELOC0_SCLLOC_LOC4 << 8) /**< Shifted mode LOC4 for I2C_ROUTELOC0 */ #define I2C_ROUTELOC0_SCLLOC_LOC5 (_I2C_ROUTELOC0_SCLLOC_LOC5 << 8) /**< Shifted mode LOC5 for I2C_ROUTELOC0 */ #define I2C_ROUTELOC0_SCLLOC_LOC6 (_I2C_ROUTELOC0_SCLLOC_LOC6 << 8) /**< Shifted mode LOC6 for I2C_ROUTELOC0 */ #define I2C_ROUTELOC0_SCLLOC_LOC7 (_I2C_ROUTELOC0_SCLLOC_LOC7 << 8) /**< Shifted mode LOC7 for I2C_ROUTELOC0 */ #define I2C_ROUTELOC0_SCLLOC_LOC8 (_I2C_ROUTELOC0_SCLLOC_LOC8 << 8) /**< Shifted mode LOC8 for I2C_ROUTELOC0 */ #define I2C_ROUTELOC0_SCLLOC_LOC9 (_I2C_ROUTELOC0_SCLLOC_LOC9 << 8) /**< Shifted mode LOC9 for I2C_ROUTELOC0 */ #define I2C_ROUTELOC0_SCLLOC_LOC10 (_I2C_ROUTELOC0_SCLLOC_LOC10 << 8) /**< Shifted mode LOC10 for I2C_ROUTELOC0 */ #define I2C_ROUTELOC0_SCLLOC_LOC11 (_I2C_ROUTELOC0_SCLLOC_LOC11 << 8) /**< Shifted mode LOC11 for I2C_ROUTELOC0 */ #define I2C_ROUTELOC0_SCLLOC_LOC12 (_I2C_ROUTELOC0_SCLLOC_LOC12 << 8) /**< Shifted mode LOC12 for I2C_ROUTELOC0 */ #define I2C_ROUTELOC0_SCLLOC_LOC13 (_I2C_ROUTELOC0_SCLLOC_LOC13 << 8) /**< Shifted mode LOC13 for I2C_ROUTELOC0 */ #define I2C_ROUTELOC0_SCLLOC_LOC14 (_I2C_ROUTELOC0_SCLLOC_LOC14 << 8) /**< Shifted mode LOC14 for I2C_ROUTELOC0 */ #define I2C_ROUTELOC0_SCLLOC_LOC15 (_I2C_ROUTELOC0_SCLLOC_LOC15 << 8) /**< Shifted mode LOC15 for I2C_ROUTELOC0 */ #define I2C_ROUTELOC0_SCLLOC_LOC16 (_I2C_ROUTELOC0_SCLLOC_LOC16 << 8) /**< Shifted mode LOC16 for I2C_ROUTELOC0 */ #define I2C_ROUTELOC0_SCLLOC_LOC17 (_I2C_ROUTELOC0_SCLLOC_LOC17 << 8) /**< Shifted mode LOC17 for I2C_ROUTELOC0 */ #define I2C_ROUTELOC0_SCLLOC_LOC18 (_I2C_ROUTELOC0_SCLLOC_LOC18 << 8) /**< Shifted mode LOC18 for I2C_ROUTELOC0 */ #define I2C_ROUTELOC0_SCLLOC_LOC19 (_I2C_ROUTELOC0_SCLLOC_LOC19 << 8) /**< Shifted mode LOC19 for I2C_ROUTELOC0 */ #define I2C_ROUTELOC0_SCLLOC_LOC20 (_I2C_ROUTELOC0_SCLLOC_LOC20 << 8) /**< Shifted mode LOC20 for I2C_ROUTELOC0 */ #define I2C_ROUTELOC0_SCLLOC_LOC21 (_I2C_ROUTELOC0_SCLLOC_LOC21 << 8) /**< Shifted mode LOC21 for I2C_ROUTELOC0 */ #define I2C_ROUTELOC0_SCLLOC_LOC22 (_I2C_ROUTELOC0_SCLLOC_LOC22 << 8) /**< Shifted mode LOC22 for I2C_ROUTELOC0 */ #define I2C_ROUTELOC0_SCLLOC_LOC23 (_I2C_ROUTELOC0_SCLLOC_LOC23 << 8) /**< Shifted mode LOC23 for I2C_ROUTELOC0 */ #define I2C_ROUTELOC0_SCLLOC_LOC24 (_I2C_ROUTELOC0_SCLLOC_LOC24 << 8) /**< Shifted mode LOC24 for I2C_ROUTELOC0 */ #define I2C_ROUTELOC0_SCLLOC_LOC25 (_I2C_ROUTELOC0_SCLLOC_LOC25 << 8) /**< Shifted mode LOC25 for I2C_ROUTELOC0 */ #define I2C_ROUTELOC0_SCLLOC_LOC26 (_I2C_ROUTELOC0_SCLLOC_LOC26 << 8) /**< Shifted mode LOC26 for I2C_ROUTELOC0 */ #define I2C_ROUTELOC0_SCLLOC_LOC27 (_I2C_ROUTELOC0_SCLLOC_LOC27 << 8) /**< Shifted mode LOC27 for I2C_ROUTELOC0 */ #define I2C_ROUTELOC0_SCLLOC_LOC28 (_I2C_ROUTELOC0_SCLLOC_LOC28 << 8) /**< Shifted mode LOC28 for I2C_ROUTELOC0 */ #define I2C_ROUTELOC0_SCLLOC_LOC29 (_I2C_ROUTELOC0_SCLLOC_LOC29 << 8) /**< Shifted mode LOC29 for I2C_ROUTELOC0 */ #define I2C_ROUTELOC0_SCLLOC_LOC30 (_I2C_ROUTELOC0_SCLLOC_LOC30 << 8) /**< Shifted mode LOC30 for I2C_ROUTELOC0 */ #define I2C_ROUTELOC0_SCLLOC_LOC31 (_I2C_ROUTELOC0_SCLLOC_LOC31 << 8) /**< Shifted mode LOC31 for I2C_ROUTELOC0 */ /** @} */ /** @} End of group EFR32MG12P_I2C */ /** @} End of group Parts */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_idac.h.
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/***************************************************************************//** * @file * @brief EFR32MG12P_IDAC register and bit field definitions * @version 5.7.0 ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * SPDX-License-Identifier: Zlib * * The licensor of this software is Silicon Laboratories Inc. * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be * appreciated but is not required. * 2. Altered source versions must be plainly marked as such, and must not be * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * ******************************************************************************/ #if defined(__ICCARM__) #pragma system_include /* Treat file as system include file. */ #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang system_header /* Treat file as system include file. */ #endif /***************************************************************************//** * @addtogroup Parts * @{ ******************************************************************************/ /***************************************************************************//** * @defgroup EFR32MG12P_IDAC IDAC * @{ * @brief EFR32MG12P_IDAC Register Declaration ******************************************************************************/ /** IDAC Register Declaration */ typedef struct { __IOM uint32_t CTRL; /**< Control Register */ __IOM uint32_t CURPROG; /**< Current Programming Register */ uint32_t RESERVED0[1U]; /**< Reserved for future use **/ __IOM uint32_t DUTYCONFIG; /**< Duty Cycle Configuration Register */ uint32_t RESERVED1[2U]; /**< Reserved for future use **/ __IM uint32_t STATUS; /**< Status Register */ uint32_t RESERVED2[1U]; /**< Reserved for future use **/ __IM uint32_t IF; /**< Interrupt Flag Register */ __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ __IOM uint32_t IEN; /**< Interrupt Enable Register */ uint32_t RESERVED3[1U]; /**< Reserved for future use **/ __IM uint32_t APORTREQ; /**< APORT Request Status Register */ __IM uint32_t APORTCONFLICT; /**< APORT Request Status Register */ } IDAC_TypeDef; /** @} */ /***************************************************************************//** * @addtogroup EFR32MG12P_IDAC * @{ * @defgroup EFR32MG12P_IDAC_BitFields IDAC Bit Fields * @{ ******************************************************************************/ /* Bit fields for IDAC CTRL */ #define _IDAC_CTRL_RESETVALUE 0x00000000UL /**< Default value for IDAC_CTRL */ #define _IDAC_CTRL_MASK 0x00FD7FFFUL /**< Mask for IDAC_CTRL */ #define IDAC_CTRL_EN (0x1UL << 0) /**< Current DAC Enable */ #define _IDAC_CTRL_EN_SHIFT 0 /**< Shift value for IDAC_EN */ #define _IDAC_CTRL_EN_MASK 0x1UL /**< Bit mask for IDAC_EN */ #define _IDAC_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */ #define IDAC_CTRL_EN_DEFAULT (_IDAC_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for IDAC_CTRL */ #define IDAC_CTRL_CURSINK (0x1UL << 1) /**< Current Sink Enable */ #define _IDAC_CTRL_CURSINK_SHIFT 1 /**< Shift value for IDAC_CURSINK */ #define _IDAC_CTRL_CURSINK_MASK 0x2UL /**< Bit mask for IDAC_CURSINK */ #define _IDAC_CTRL_CURSINK_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */ #define IDAC_CTRL_CURSINK_DEFAULT (_IDAC_CTRL_CURSINK_DEFAULT << 1) /**< Shifted mode DEFAULT for IDAC_CTRL */ #define IDAC_CTRL_MINOUTTRANS (0x1UL << 2) /**< Minimum Output Transition Enable */ #define _IDAC_CTRL_MINOUTTRANS_SHIFT 2 /**< Shift value for IDAC_MINOUTTRANS */ #define _IDAC_CTRL_MINOUTTRANS_MASK 0x4UL /**< Bit mask for IDAC_MINOUTTRANS */ #define _IDAC_CTRL_MINOUTTRANS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */ #define IDAC_CTRL_MINOUTTRANS_DEFAULT (_IDAC_CTRL_MINOUTTRANS_DEFAULT << 2) /**< Shifted mode DEFAULT for IDAC_CTRL */ #define IDAC_CTRL_APORTOUTEN (0x1UL << 3) /**< APORT Output Enable */ #define _IDAC_CTRL_APORTOUTEN_SHIFT 3 /**< Shift value for IDAC_APORTOUTEN */ #define _IDAC_CTRL_APORTOUTEN_MASK 0x8UL /**< Bit mask for IDAC_APORTOUTEN */ #define _IDAC_CTRL_APORTOUTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */ #define IDAC_CTRL_APORTOUTEN_DEFAULT (_IDAC_CTRL_APORTOUTEN_DEFAULT << 3) /**< Shifted mode DEFAULT for IDAC_CTRL */ #define _IDAC_CTRL_APORTOUTSEL_SHIFT 4 /**< Shift value for IDAC_APORTOUTSEL */ #define _IDAC_CTRL_APORTOUTSEL_MASK 0xFF0UL /**< Bit mask for IDAC_APORTOUTSEL */ #define _IDAC_CTRL_APORTOUTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */ #define _IDAC_CTRL_APORTOUTSEL_APORT1XCH0 0x00000020UL /**< Mode APORT1XCH0 for IDAC_CTRL */ #define _IDAC_CTRL_APORTOUTSEL_APORT1YCH1 0x00000021UL /**< Mode APORT1YCH1 for IDAC_CTRL */ #define _IDAC_CTRL_APORTOUTSEL_APORT1XCH2 0x00000022UL /**< Mode APORT1XCH2 for IDAC_CTRL */ #define _IDAC_CTRL_APORTOUTSEL_APORT1YCH3 0x00000023UL /**< Mode APORT1YCH3 for IDAC_CTRL */ #define _IDAC_CTRL_APORTOUTSEL_APORT1XCH4 0x00000024UL /**< Mode APORT1XCH4 for IDAC_CTRL */ #define _IDAC_CTRL_APORTOUTSEL_APORT1YCH5 0x00000025UL /**< Mode APORT1YCH5 for IDAC_CTRL */ #define _IDAC_CTRL_APORTOUTSEL_APORT1XCH6 0x00000026UL /**< Mode APORT1XCH6 for IDAC_CTRL */ #define _IDAC_CTRL_APORTOUTSEL_APORT1YCH7 0x00000027UL /**< Mode APORT1YCH7 for IDAC_CTRL */ #define _IDAC_CTRL_APORTOUTSEL_APORT1XCH8 0x00000028UL /**< Mode APORT1XCH8 for IDAC_CTRL */ #define _IDAC_CTRL_APORTOUTSEL_APORT1YCH9 0x00000029UL /**< Mode APORT1YCH9 for IDAC_CTRL */ #define _IDAC_CTRL_APORTOUTSEL_APORT1XCH10 0x0000002AUL /**< Mode APORT1XCH10 for IDAC_CTRL */ #define _IDAC_CTRL_APORTOUTSEL_APORT1YCH11 0x0000002BUL /**< Mode APORT1YCH11 for IDAC_CTRL */ #define _IDAC_CTRL_APORTOUTSEL_APORT1XCH12 0x0000002CUL /**< Mode APORT1XCH12 for IDAC_CTRL */ #define _IDAC_CTRL_APORTOUTSEL_APORT1YCH13 0x0000002DUL /**< Mode APORT1YCH13 for IDAC_CTRL */ #define _IDAC_CTRL_APORTOUTSEL_APORT1XCH14 0x0000002EUL /**< Mode APORT1XCH14 for IDAC_CTRL */ #define _IDAC_CTRL_APORTOUTSEL_APORT1YCH15 0x0000002FUL /**< Mode APORT1YCH15 for IDAC_CTRL */ #define _IDAC_CTRL_APORTOUTSEL_APORT1XCH16 0x00000030UL /**< Mode APORT1XCH16 for IDAC_CTRL */ #define _IDAC_CTRL_APORTOUTSEL_APORT1YCH17 0x00000031UL /**< Mode APORT1YCH17 for IDAC_CTRL */ #define _IDAC_CTRL_APORTOUTSEL_APORT1XCH18 0x00000032UL /**< Mode APORT1XCH18 for IDAC_CTRL */ #define _IDAC_CTRL_APORTOUTSEL_APORT1YCH19 0x00000033UL /**< Mode APORT1YCH19 for IDAC_CTRL */ #define _IDAC_CTRL_APORTOUTSEL_APORT1XCH20 0x00000034UL /**< Mode APORT1XCH20 for IDAC_CTRL */ #define _IDAC_CTRL_APORTOUTSEL_APORT1YCH21 0x00000035UL /**< Mode APORT1YCH21 for IDAC_CTRL */ #define _IDAC_CTRL_APORTOUTSEL_APORT1XCH22 0x00000036UL /**< Mode APORT1XCH22 for IDAC_CTRL */ #define _IDAC_CTRL_APORTOUTSEL_APORT1YCH23 0x00000037UL /**< Mode APORT1YCH23 for IDAC_CTRL */ #define _IDAC_CTRL_APORTOUTSEL_APORT1XCH24 0x00000038UL /**< Mode APORT1XCH24 for IDAC_CTRL */ #define _IDAC_CTRL_APORTOUTSEL_APORT1YCH25 0x00000039UL /**< Mode APORT1YCH25 for IDAC_CTRL */ #define _IDAC_CTRL_APORTOUTSEL_APORT1XCH26 0x0000003AUL /**< Mode APORT1XCH26 for IDAC_CTRL */ #define _IDAC_CTRL_APORTOUTSEL_APORT1YCH27 0x0000003BUL /**< Mode APORT1YCH27 for IDAC_CTRL */ #define _IDAC_CTRL_APORTOUTSEL_APORT1XCH28 0x0000003CUL /**< Mode APORT1XCH28 for IDAC_CTRL */ #define _IDAC_CTRL_APORTOUTSEL_APORT1YCH29 0x0000003DUL /**< Mode APORT1YCH29 for IDAC_CTRL */ #define _IDAC_CTRL_APORTOUTSEL_APORT1XCH30 0x0000003EUL /**< Mode APORT1XCH30 for IDAC_CTRL */ #define _IDAC_CTRL_APORTOUTSEL_APORT1YCH31 0x0000003FUL /**< Mode APORT1YCH31 for IDAC_CTRL */ #define IDAC_CTRL_APORTOUTSEL_DEFAULT (_IDAC_CTRL_APORTOUTSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for IDAC_CTRL */ #define IDAC_CTRL_APORTOUTSEL_APORT1XCH0 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH0 << 4) /**< Shifted mode APORT1XCH0 for IDAC_CTRL */ #define IDAC_CTRL_APORTOUTSEL_APORT1YCH1 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH1 << 4) /**< Shifted mode APORT1YCH1 for IDAC_CTRL */ #define IDAC_CTRL_APORTOUTSEL_APORT1XCH2 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH2 << 4) /**< Shifted mode APORT1XCH2 for IDAC_CTRL */ #define IDAC_CTRL_APORTOUTSEL_APORT1YCH3 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH3 << 4) /**< Shifted mode APORT1YCH3 for IDAC_CTRL */ #define IDAC_CTRL_APORTOUTSEL_APORT1XCH4 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH4 << 4) /**< Shifted mode APORT1XCH4 for IDAC_CTRL */ #define IDAC_CTRL_APORTOUTSEL_APORT1YCH5 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH5 << 4) /**< Shifted mode APORT1YCH5 for IDAC_CTRL */ #define IDAC_CTRL_APORTOUTSEL_APORT1XCH6 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH6 << 4) /**< Shifted mode APORT1XCH6 for IDAC_CTRL */ #define IDAC_CTRL_APORTOUTSEL_APORT1YCH7 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH7 << 4) /**< Shifted mode APORT1YCH7 for IDAC_CTRL */ #define IDAC_CTRL_APORTOUTSEL_APORT1XCH8 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH8 << 4) /**< Shifted mode APORT1XCH8 for IDAC_CTRL */ #define IDAC_CTRL_APORTOUTSEL_APORT1YCH9 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH9 << 4) /**< Shifted mode APORT1YCH9 for IDAC_CTRL */ #define IDAC_CTRL_APORTOUTSEL_APORT1XCH10 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH10 << 4) /**< Shifted mode APORT1XCH10 for IDAC_CTRL */ #define IDAC_CTRL_APORTOUTSEL_APORT1YCH11 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH11 << 4) /**< Shifted mode APORT1YCH11 for IDAC_CTRL */ #define IDAC_CTRL_APORTOUTSEL_APORT1XCH12 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH12 << 4) /**< Shifted mode APORT1XCH12 for IDAC_CTRL */ #define IDAC_CTRL_APORTOUTSEL_APORT1YCH13 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH13 << 4) /**< Shifted mode APORT1YCH13 for IDAC_CTRL */ #define IDAC_CTRL_APORTOUTSEL_APORT1XCH14 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH14 << 4) /**< Shifted mode APORT1XCH14 for IDAC_CTRL */ #define IDAC_CTRL_APORTOUTSEL_APORT1YCH15 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH15 << 4) /**< Shifted mode APORT1YCH15 for IDAC_CTRL */ #define IDAC_CTRL_APORTOUTSEL_APORT1XCH16 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH16 << 4) /**< Shifted mode APORT1XCH16 for IDAC_CTRL */ #define IDAC_CTRL_APORTOUTSEL_APORT1YCH17 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH17 << 4) /**< Shifted mode APORT1YCH17 for IDAC_CTRL */ #define IDAC_CTRL_APORTOUTSEL_APORT1XCH18 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH18 << 4) /**< Shifted mode APORT1XCH18 for IDAC_CTRL */ #define IDAC_CTRL_APORTOUTSEL_APORT1YCH19 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH19 << 4) /**< Shifted mode APORT1YCH19 for IDAC_CTRL */ #define IDAC_CTRL_APORTOUTSEL_APORT1XCH20 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH20 << 4) /**< Shifted mode APORT1XCH20 for IDAC_CTRL */ #define IDAC_CTRL_APORTOUTSEL_APORT1YCH21 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH21 << 4) /**< Shifted mode APORT1YCH21 for IDAC_CTRL */ #define IDAC_CTRL_APORTOUTSEL_APORT1XCH22 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH22 << 4) /**< Shifted mode APORT1XCH22 for IDAC_CTRL */ #define IDAC_CTRL_APORTOUTSEL_APORT1YCH23 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH23 << 4) /**< Shifted mode APORT1YCH23 for IDAC_CTRL */ #define IDAC_CTRL_APORTOUTSEL_APORT1XCH24 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH24 << 4) /**< Shifted mode APORT1XCH24 for IDAC_CTRL */ #define IDAC_CTRL_APORTOUTSEL_APORT1YCH25 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH25 << 4) /**< Shifted mode APORT1YCH25 for IDAC_CTRL */ #define IDAC_CTRL_APORTOUTSEL_APORT1XCH26 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH26 << 4) /**< Shifted mode APORT1XCH26 for IDAC_CTRL */ #define IDAC_CTRL_APORTOUTSEL_APORT1YCH27 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH27 << 4) /**< Shifted mode APORT1YCH27 for IDAC_CTRL */ #define IDAC_CTRL_APORTOUTSEL_APORT1XCH28 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH28 << 4) /**< Shifted mode APORT1XCH28 for IDAC_CTRL */ #define IDAC_CTRL_APORTOUTSEL_APORT1YCH29 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH29 << 4) /**< Shifted mode APORT1YCH29 for IDAC_CTRL */ #define IDAC_CTRL_APORTOUTSEL_APORT1XCH30 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH30 << 4) /**< Shifted mode APORT1XCH30 for IDAC_CTRL */ #define IDAC_CTRL_APORTOUTSEL_APORT1YCH31 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH31 << 4) /**< Shifted mode APORT1YCH31 for IDAC_CTRL */ #define IDAC_CTRL_PWRSEL (0x1UL << 12) /**< Power Select */ #define _IDAC_CTRL_PWRSEL_SHIFT 12 /**< Shift value for IDAC_PWRSEL */ #define _IDAC_CTRL_PWRSEL_MASK 0x1000UL /**< Bit mask for IDAC_PWRSEL */ #define _IDAC_CTRL_PWRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */ #define _IDAC_CTRL_PWRSEL_ANA 0x00000000UL /**< Mode ANA for IDAC_CTRL */ #define _IDAC_CTRL_PWRSEL_IO 0x00000001UL /**< Mode IO for IDAC_CTRL */ #define IDAC_CTRL_PWRSEL_DEFAULT (_IDAC_CTRL_PWRSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for IDAC_CTRL */ #define IDAC_CTRL_PWRSEL_ANA (_IDAC_CTRL_PWRSEL_ANA << 12) /**< Shifted mode ANA for IDAC_CTRL */ #define IDAC_CTRL_PWRSEL_IO (_IDAC_CTRL_PWRSEL_IO << 12) /**< Shifted mode IO for IDAC_CTRL */ #define IDAC_CTRL_EM2DELAY (0x1UL << 13) /**< EM2 Delay */ #define _IDAC_CTRL_EM2DELAY_SHIFT 13 /**< Shift value for IDAC_EM2DELAY */ #define _IDAC_CTRL_EM2DELAY_MASK 0x2000UL /**< Bit mask for IDAC_EM2DELAY */ #define _IDAC_CTRL_EM2DELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */ #define IDAC_CTRL_EM2DELAY_DEFAULT (_IDAC_CTRL_EM2DELAY_DEFAULT << 13) /**< Shifted mode DEFAULT for IDAC_CTRL */ #define IDAC_CTRL_APORTMASTERDIS (0x1UL << 14) /**< APORT Bus Master Disable */ #define _IDAC_CTRL_APORTMASTERDIS_SHIFT 14 /**< Shift value for IDAC_APORTMASTERDIS */ #define _IDAC_CTRL_APORTMASTERDIS_MASK 0x4000UL /**< Bit mask for IDAC_APORTMASTERDIS */ #define _IDAC_CTRL_APORTMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */ #define IDAC_CTRL_APORTMASTERDIS_DEFAULT (_IDAC_CTRL_APORTMASTERDIS_DEFAULT << 14) /**< Shifted mode DEFAULT for IDAC_CTRL */ #define IDAC_CTRL_APORTOUTENPRS (0x1UL << 16) /**< PRS Controlled APORT Output Enable */ #define _IDAC_CTRL_APORTOUTENPRS_SHIFT 16 /**< Shift value for IDAC_APORTOUTENPRS */ #define _IDAC_CTRL_APORTOUTENPRS_MASK 0x10000UL /**< Bit mask for IDAC_APORTOUTENPRS */ #define _IDAC_CTRL_APORTOUTENPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */ #define IDAC_CTRL_APORTOUTENPRS_DEFAULT (_IDAC_CTRL_APORTOUTENPRS_DEFAULT << 16) /**< Shifted mode DEFAULT for IDAC_CTRL */ #define IDAC_CTRL_MAINOUTEN (0x1UL << 18) /**< Output Enable */ #define _IDAC_CTRL_MAINOUTEN_SHIFT 18 /**< Shift value for IDAC_MAINOUTEN */ #define _IDAC_CTRL_MAINOUTEN_MASK 0x40000UL /**< Bit mask for IDAC_MAINOUTEN */ #define _IDAC_CTRL_MAINOUTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */ #define IDAC_CTRL_MAINOUTEN_DEFAULT (_IDAC_CTRL_MAINOUTEN_DEFAULT << 18) /**< Shifted mode DEFAULT for IDAC_CTRL */ #define IDAC_CTRL_MAINOUTENPRS (0x1UL << 19) /**< PRS Controlled Main Pad Output Enable */ #define _IDAC_CTRL_MAINOUTENPRS_SHIFT 19 /**< Shift value for IDAC_MAINOUTENPRS */ #define _IDAC_CTRL_MAINOUTENPRS_MASK 0x80000UL /**< Bit mask for IDAC_MAINOUTENPRS */ #define _IDAC_CTRL_MAINOUTENPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */ #define IDAC_CTRL_MAINOUTENPRS_DEFAULT (_IDAC_CTRL_MAINOUTENPRS_DEFAULT << 19) /**< Shifted mode DEFAULT for IDAC_CTRL */ #define _IDAC_CTRL_PRSSEL_SHIFT 20 /**< Shift value for IDAC_PRSSEL */ #define _IDAC_CTRL_PRSSEL_MASK 0xF00000UL /**< Bit mask for IDAC_PRSSEL */ #define _IDAC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */ #define _IDAC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for IDAC_CTRL */ #define _IDAC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for IDAC_CTRL */ #define _IDAC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for IDAC_CTRL */ #define _IDAC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for IDAC_CTRL */ #define _IDAC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for IDAC_CTRL */ #define _IDAC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for IDAC_CTRL */ #define _IDAC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for IDAC_CTRL */ #define _IDAC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for IDAC_CTRL */ #define _IDAC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for IDAC_CTRL */ #define _IDAC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for IDAC_CTRL */ #define _IDAC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for IDAC_CTRL */ #define _IDAC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for IDAC_CTRL */ #define IDAC_CTRL_PRSSEL_DEFAULT (_IDAC_CTRL_PRSSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for IDAC_CTRL */ #define IDAC_CTRL_PRSSEL_PRSCH0 (_IDAC_CTRL_PRSSEL_PRSCH0 << 20) /**< Shifted mode PRSCH0 for IDAC_CTRL */ #define IDAC_CTRL_PRSSEL_PRSCH1 (_IDAC_CTRL_PRSSEL_PRSCH1 << 20) /**< Shifted mode PRSCH1 for IDAC_CTRL */ #define IDAC_CTRL_PRSSEL_PRSCH2 (_IDAC_CTRL_PRSSEL_PRSCH2 << 20) /**< Shifted mode PRSCH2 for IDAC_CTRL */ #define IDAC_CTRL_PRSSEL_PRSCH3 (_IDAC_CTRL_PRSSEL_PRSCH3 << 20) /**< Shifted mode PRSCH3 for IDAC_CTRL */ #define IDAC_CTRL_PRSSEL_PRSCH4 (_IDAC_CTRL_PRSSEL_PRSCH4 << 20) /**< Shifted mode PRSCH4 for IDAC_CTRL */ #define IDAC_CTRL_PRSSEL_PRSCH5 (_IDAC_CTRL_PRSSEL_PRSCH5 << 20) /**< Shifted mode PRSCH5 for IDAC_CTRL */ #define IDAC_CTRL_PRSSEL_PRSCH6 (_IDAC_CTRL_PRSSEL_PRSCH6 << 20) /**< Shifted mode PRSCH6 for IDAC_CTRL */ #define IDAC_CTRL_PRSSEL_PRSCH7 (_IDAC_CTRL_PRSSEL_PRSCH7 << 20) /**< Shifted mode PRSCH7 for IDAC_CTRL */ #define IDAC_CTRL_PRSSEL_PRSCH8 (_IDAC_CTRL_PRSSEL_PRSCH8 << 20) /**< Shifted mode PRSCH8 for IDAC_CTRL */ #define IDAC_CTRL_PRSSEL_PRSCH9 (_IDAC_CTRL_PRSSEL_PRSCH9 << 20) /**< Shifted mode PRSCH9 for IDAC_CTRL */ #define IDAC_CTRL_PRSSEL_PRSCH10 (_IDAC_CTRL_PRSSEL_PRSCH10 << 20) /**< Shifted mode PRSCH10 for IDAC_CTRL */ #define IDAC_CTRL_PRSSEL_PRSCH11 (_IDAC_CTRL_PRSSEL_PRSCH11 << 20) /**< Shifted mode PRSCH11 for IDAC_CTRL */ /* Bit fields for IDAC CURPROG */ #define _IDAC_CURPROG_RESETVALUE 0x009B0000UL /**< Default value for IDAC_CURPROG */ #define _IDAC_CURPROG_MASK 0x00FF1F03UL /**< Mask for IDAC_CURPROG */ #define _IDAC_CURPROG_RANGESEL_SHIFT 0 /**< Shift value for IDAC_RANGESEL */ #define _IDAC_CURPROG_RANGESEL_MASK 0x3UL /**< Bit mask for IDAC_RANGESEL */ #define _IDAC_CURPROG_RANGESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CURPROG */ #define _IDAC_CURPROG_RANGESEL_RANGE0 0x00000000UL /**< Mode RANGE0 for IDAC_CURPROG */ #define _IDAC_CURPROG_RANGESEL_RANGE1 0x00000001UL /**< Mode RANGE1 for IDAC_CURPROG */ #define _IDAC_CURPROG_RANGESEL_RANGE2 0x00000002UL /**< Mode RANGE2 for IDAC_CURPROG */ #define _IDAC_CURPROG_RANGESEL_RANGE3 0x00000003UL /**< Mode RANGE3 for IDAC_CURPROG */ #define IDAC_CURPROG_RANGESEL_DEFAULT (_IDAC_CURPROG_RANGESEL_DEFAULT << 0) /**< Shifted mode DEFAULT for IDAC_CURPROG */ #define IDAC_CURPROG_RANGESEL_RANGE0 (_IDAC_CURPROG_RANGESEL_RANGE0 << 0) /**< Shifted mode RANGE0 for IDAC_CURPROG */ #define IDAC_CURPROG_RANGESEL_RANGE1 (_IDAC_CURPROG_RANGESEL_RANGE1 << 0) /**< Shifted mode RANGE1 for IDAC_CURPROG */ #define IDAC_CURPROG_RANGESEL_RANGE2 (_IDAC_CURPROG_RANGESEL_RANGE2 << 0) /**< Shifted mode RANGE2 for IDAC_CURPROG */ #define IDAC_CURPROG_RANGESEL_RANGE3 (_IDAC_CURPROG_RANGESEL_RANGE3 << 0) /**< Shifted mode RANGE3 for IDAC_CURPROG */ #define _IDAC_CURPROG_STEPSEL_SHIFT 8 /**< Shift value for IDAC_STEPSEL */ #define _IDAC_CURPROG_STEPSEL_MASK 0x1F00UL /**< Bit mask for IDAC_STEPSEL */ #define _IDAC_CURPROG_STEPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CURPROG */ #define IDAC_CURPROG_STEPSEL_DEFAULT (_IDAC_CURPROG_STEPSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for IDAC_CURPROG */ #define _IDAC_CURPROG_TUNING_SHIFT 16 /**< Shift value for IDAC_TUNING */ #define _IDAC_CURPROG_TUNING_MASK 0xFF0000UL /**< Bit mask for IDAC_TUNING */ #define _IDAC_CURPROG_TUNING_DEFAULT 0x0000009BUL /**< Mode DEFAULT for IDAC_CURPROG */ #define IDAC_CURPROG_TUNING_DEFAULT (_IDAC_CURPROG_TUNING_DEFAULT << 16) /**< Shifted mode DEFAULT for IDAC_CURPROG */ /* Bit fields for IDAC DUTYCONFIG */ #define _IDAC_DUTYCONFIG_RESETVALUE 0x00000000UL /**< Default value for IDAC_DUTYCONFIG */ #define _IDAC_DUTYCONFIG_MASK 0x00000002UL /**< Mask for IDAC_DUTYCONFIG */ #define IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS (0x1UL << 1) /**< Duty Cycle Enable */ #define _IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS_SHIFT 1 /**< Shift value for IDAC_EM2DUTYCYCLEDIS */ #define _IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS_MASK 0x2UL /**< Bit mask for IDAC_EM2DUTYCYCLEDIS */ #define _IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_DUTYCONFIG */ #define IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS_DEFAULT (_IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for IDAC_DUTYCONFIG */ /* Bit fields for IDAC STATUS */ #define _IDAC_STATUS_RESETVALUE 0x00000000UL /**< Default value for IDAC_STATUS */ #define _IDAC_STATUS_MASK 0x00000003UL /**< Mask for IDAC_STATUS */ #define IDAC_STATUS_CURSTABLE (0x1UL << 0) /**< IDAC Output Current Stable */ #define _IDAC_STATUS_CURSTABLE_SHIFT 0 /**< Shift value for IDAC_CURSTABLE */ #define _IDAC_STATUS_CURSTABLE_MASK 0x1UL /**< Bit mask for IDAC_CURSTABLE */ #define _IDAC_STATUS_CURSTABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_STATUS */ #define IDAC_STATUS_CURSTABLE_DEFAULT (_IDAC_STATUS_CURSTABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for IDAC_STATUS */ #define IDAC_STATUS_APORTCONFLICT (0x1UL << 1) /**< APORT Conflict Output */ #define _IDAC_STATUS_APORTCONFLICT_SHIFT 1 /**< Shift value for IDAC_APORTCONFLICT */ #define _IDAC_STATUS_APORTCONFLICT_MASK 0x2UL /**< Bit mask for IDAC_APORTCONFLICT */ #define _IDAC_STATUS_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_STATUS */ #define IDAC_STATUS_APORTCONFLICT_DEFAULT (_IDAC_STATUS_APORTCONFLICT_DEFAULT << 1) /**< Shifted mode DEFAULT for IDAC_STATUS */ /* Bit fields for IDAC IF */ #define _IDAC_IF_RESETVALUE 0x00000000UL /**< Default value for IDAC_IF */ #define _IDAC_IF_MASK 0x00000003UL /**< Mask for IDAC_IF */ #define IDAC_IF_CURSTABLE (0x1UL << 0) /**< Edge Triggered Interrupt Flag */ #define _IDAC_IF_CURSTABLE_SHIFT 0 /**< Shift value for IDAC_CURSTABLE */ #define _IDAC_IF_CURSTABLE_MASK 0x1UL /**< Bit mask for IDAC_CURSTABLE */ #define _IDAC_IF_CURSTABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_IF */ #define IDAC_IF_CURSTABLE_DEFAULT (_IDAC_IF_CURSTABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for IDAC_IF */ #define IDAC_IF_APORTCONFLICT (0x1UL << 1) /**< APORT Conflict Interrupt Flag */ #define _IDAC_IF_APORTCONFLICT_SHIFT 1 /**< Shift value for IDAC_APORTCONFLICT */ #define _IDAC_IF_APORTCONFLICT_MASK 0x2UL /**< Bit mask for IDAC_APORTCONFLICT */ #define _IDAC_IF_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_IF */ #define IDAC_IF_APORTCONFLICT_DEFAULT (_IDAC_IF_APORTCONFLICT_DEFAULT << 1) /**< Shifted mode DEFAULT for IDAC_IF */ /* Bit fields for IDAC IFS */ #define _IDAC_IFS_RESETVALUE 0x00000000UL /**< Default value for IDAC_IFS */ #define _IDAC_IFS_MASK 0x00000003UL /**< Mask for IDAC_IFS */ #define IDAC_IFS_CURSTABLE (0x1UL << 0) /**< Set CURSTABLE Interrupt Flag */ #define _IDAC_IFS_CURSTABLE_SHIFT 0 /**< Shift value for IDAC_CURSTABLE */ #define _IDAC_IFS_CURSTABLE_MASK 0x1UL /**< Bit mask for IDAC_CURSTABLE */ #define _IDAC_IFS_CURSTABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_IFS */ #define IDAC_IFS_CURSTABLE_DEFAULT (_IDAC_IFS_CURSTABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for IDAC_IFS */ #define IDAC_IFS_APORTCONFLICT (0x1UL << 1) /**< Set APORTCONFLICT Interrupt Flag */ #define _IDAC_IFS_APORTCONFLICT_SHIFT 1 /**< Shift value for IDAC_APORTCONFLICT */ #define _IDAC_IFS_APORTCONFLICT_MASK 0x2UL /**< Bit mask for IDAC_APORTCONFLICT */ #define _IDAC_IFS_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_IFS */ #define IDAC_IFS_APORTCONFLICT_DEFAULT (_IDAC_IFS_APORTCONFLICT_DEFAULT << 1) /**< Shifted mode DEFAULT for IDAC_IFS */ /* Bit fields for IDAC IFC */ #define _IDAC_IFC_RESETVALUE 0x00000000UL /**< Default value for IDAC_IFC */ #define _IDAC_IFC_MASK 0x00000003UL /**< Mask for IDAC_IFC */ #define IDAC_IFC_CURSTABLE (0x1UL << 0) /**< Clear CURSTABLE Interrupt Flag */ #define _IDAC_IFC_CURSTABLE_SHIFT 0 /**< Shift value for IDAC_CURSTABLE */ #define _IDAC_IFC_CURSTABLE_MASK 0x1UL /**< Bit mask for IDAC_CURSTABLE */ #define _IDAC_IFC_CURSTABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_IFC */ #define IDAC_IFC_CURSTABLE_DEFAULT (_IDAC_IFC_CURSTABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for IDAC_IFC */ #define IDAC_IFC_APORTCONFLICT (0x1UL << 1) /**< Clear APORTCONFLICT Interrupt Flag */ #define _IDAC_IFC_APORTCONFLICT_SHIFT 1 /**< Shift value for IDAC_APORTCONFLICT */ #define _IDAC_IFC_APORTCONFLICT_MASK 0x2UL /**< Bit mask for IDAC_APORTCONFLICT */ #define _IDAC_IFC_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_IFC */ #define IDAC_IFC_APORTCONFLICT_DEFAULT (_IDAC_IFC_APORTCONFLICT_DEFAULT << 1) /**< Shifted mode DEFAULT for IDAC_IFC */ /* Bit fields for IDAC IEN */ #define _IDAC_IEN_RESETVALUE 0x00000000UL /**< Default value for IDAC_IEN */ #define _IDAC_IEN_MASK 0x00000003UL /**< Mask for IDAC_IEN */ #define IDAC_IEN_CURSTABLE (0x1UL << 0) /**< CURSTABLE Interrupt Enable */ #define _IDAC_IEN_CURSTABLE_SHIFT 0 /**< Shift value for IDAC_CURSTABLE */ #define _IDAC_IEN_CURSTABLE_MASK 0x1UL /**< Bit mask for IDAC_CURSTABLE */ #define _IDAC_IEN_CURSTABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_IEN */ #define IDAC_IEN_CURSTABLE_DEFAULT (_IDAC_IEN_CURSTABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for IDAC_IEN */ #define IDAC_IEN_APORTCONFLICT (0x1UL << 1) /**< APORTCONFLICT Interrupt Enable */ #define _IDAC_IEN_APORTCONFLICT_SHIFT 1 /**< Shift value for IDAC_APORTCONFLICT */ #define _IDAC_IEN_APORTCONFLICT_MASK 0x2UL /**< Bit mask for IDAC_APORTCONFLICT */ #define _IDAC_IEN_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_IEN */ #define IDAC_IEN_APORTCONFLICT_DEFAULT (_IDAC_IEN_APORTCONFLICT_DEFAULT << 1) /**< Shifted mode DEFAULT for IDAC_IEN */ /* Bit fields for IDAC APORTREQ */ #define _IDAC_APORTREQ_RESETVALUE 0x00000000UL /**< Default value for IDAC_APORTREQ */ #define _IDAC_APORTREQ_MASK 0x0000000CUL /**< Mask for IDAC_APORTREQ */ #define IDAC_APORTREQ_APORT1XREQ (0x1UL << 2) /**< 1 If the APORT Bus Connected to APORT1X is Requested */ #define _IDAC_APORTREQ_APORT1XREQ_SHIFT 2 /**< Shift value for IDAC_APORT1XREQ */ #define _IDAC_APORTREQ_APORT1XREQ_MASK 0x4UL /**< Bit mask for IDAC_APORT1XREQ */ #define _IDAC_APORTREQ_APORT1XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_APORTREQ */ #define IDAC_APORTREQ_APORT1XREQ_DEFAULT (_IDAC_APORTREQ_APORT1XREQ_DEFAULT << 2) /**< Shifted mode DEFAULT for IDAC_APORTREQ */ #define IDAC_APORTREQ_APORT1YREQ (0x1UL << 3) /**< 1 If the Bus Connected to APORT1Y is Requested */ #define _IDAC_APORTREQ_APORT1YREQ_SHIFT 3 /**< Shift value for IDAC_APORT1YREQ */ #define _IDAC_APORTREQ_APORT1YREQ_MASK 0x8UL /**< Bit mask for IDAC_APORT1YREQ */ #define _IDAC_APORTREQ_APORT1YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_APORTREQ */ #define IDAC_APORTREQ_APORT1YREQ_DEFAULT (_IDAC_APORTREQ_APORT1YREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for IDAC_APORTREQ */ /* Bit fields for IDAC APORTCONFLICT */ #define _IDAC_APORTCONFLICT_RESETVALUE 0x00000000UL /**< Default value for IDAC_APORTCONFLICT */ #define _IDAC_APORTCONFLICT_MASK 0x0000000CUL /**< Mask for IDAC_APORTCONFLICT */ #define IDAC_APORTCONFLICT_APORT1XCONFLICT (0x1UL << 2) /**< 1 If the Bus Connected to APORT1X is in Conflict With Another Peripheral */ #define _IDAC_APORTCONFLICT_APORT1XCONFLICT_SHIFT 2 /**< Shift value for IDAC_APORT1XCONFLICT */ #define _IDAC_APORTCONFLICT_APORT1XCONFLICT_MASK 0x4UL /**< Bit mask for IDAC_APORT1XCONFLICT */ #define _IDAC_APORTCONFLICT_APORT1XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_APORTCONFLICT */ #define IDAC_APORTCONFLICT_APORT1XCONFLICT_DEFAULT (_IDAC_APORTCONFLICT_APORT1XCONFLICT_DEFAULT << 2) /**< Shifted mode DEFAULT for IDAC_APORTCONFLICT */ #define IDAC_APORTCONFLICT_APORT1YCONFLICT (0x1UL << 3) /**< 1 If the Bus Connected to APORT1Y is in Conflict With Another Peripheral */ #define _IDAC_APORTCONFLICT_APORT1YCONFLICT_SHIFT 3 /**< Shift value for IDAC_APORT1YCONFLICT */ #define _IDAC_APORTCONFLICT_APORT1YCONFLICT_MASK 0x8UL /**< Bit mask for IDAC_APORT1YCONFLICT */ #define _IDAC_APORTCONFLICT_APORT1YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_APORTCONFLICT */ #define IDAC_APORTCONFLICT_APORT1YCONFLICT_DEFAULT (_IDAC_APORTCONFLICT_APORT1YCONFLICT_DEFAULT << 3) /**< Shifted mode DEFAULT for IDAC_APORTCONFLICT */ /** @} */ /** @} End of group EFR32MG12P_IDAC */ /** @} End of group Parts */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_ldma.h.
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/***************************************************************************//** * @file * @brief EFR32MG12P_LDMA register and bit field definitions * @version 5.7.0 ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * SPDX-License-Identifier: Zlib * * The licensor of this software is Silicon Laboratories Inc. * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be * appreciated but is not required. * 2. Altered source versions must be plainly marked as such, and must not be * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * ******************************************************************************/ #if defined(__ICCARM__) #pragma system_include /* Treat file as system include file. */ #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang system_header /* Treat file as system include file. */ #endif /***************************************************************************//** * @addtogroup Parts * @{ ******************************************************************************/ /***************************************************************************//** * @defgroup EFR32MG12P_LDMA LDMA * @{ * @brief EFR32MG12P_LDMA Register Declaration ******************************************************************************/ /** LDMA Register Declaration */ typedef struct { __IOM uint32_t CTRL; /**< DMA Control Register */ __IM uint32_t STATUS; /**< DMA Status Register */ __IOM uint32_t SYNC; /**< DMA Synchronization Trigger Register (Single-Cycle RMW) */ uint32_t RESERVED0[5U]; /**< Reserved for future use **/ __IOM uint32_t CHEN; /**< DMA Channel Enable Register (Single-Cycle RMW) */ __IM uint32_t CHBUSY; /**< DMA Channel Busy Register */ __IOM uint32_t CHDONE; /**< DMA Channel Linking Done Register (Single-Cycle RMW) */ __IOM uint32_t DBGHALT; /**< DMA Channel Debug Halt Register */ __IOM uint32_t SWREQ; /**< DMA Channel Software Transfer Request Register */ __IOM uint32_t REQDIS; /**< DMA Channel Request Disable Register */ __IM uint32_t REQPEND; /**< DMA Channel Requests Pending Register */ __IOM uint32_t LINKLOAD; /**< DMA Channel Link Load Register */ __IOM uint32_t REQCLEAR; /**< DMA Channel Request Clear Register */ uint32_t RESERVED1[7U]; /**< Reserved for future use **/ __IM uint32_t IF; /**< Interrupt Flag Register */ __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ __IOM uint32_t IEN; /**< Interrupt Enable Register */ uint32_t RESERVED2[4U]; /**< Reserved registers */ LDMA_CH_TypeDef CH[8U]; /**< DMA Channel Registers */ } LDMA_TypeDef; /** @} */ /***************************************************************************//** * @addtogroup EFR32MG12P_LDMA * @{ * @defgroup EFR32MG12P_LDMA_BitFields LDMA Bit Fields * @{ ******************************************************************************/ /* Bit fields for LDMA CTRL */ #define _LDMA_CTRL_RESETVALUE 0x07000000UL /**< Default value for LDMA_CTRL */ #define _LDMA_CTRL_MASK 0x0700FFFFUL /**< Mask for LDMA_CTRL */ #define _LDMA_CTRL_SYNCPRSSETEN_SHIFT 0 /**< Shift value for LDMA_SYNCPRSSETEN */ #define _LDMA_CTRL_SYNCPRSSETEN_MASK 0xFFUL /**< Bit mask for LDMA_SYNCPRSSETEN */ #define _LDMA_CTRL_SYNCPRSSETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CTRL */ #define LDMA_CTRL_SYNCPRSSETEN_DEFAULT (_LDMA_CTRL_SYNCPRSSETEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CTRL */ #define _LDMA_CTRL_SYNCPRSCLREN_SHIFT 8 /**< Shift value for LDMA_SYNCPRSCLREN */ #define _LDMA_CTRL_SYNCPRSCLREN_MASK 0xFF00UL /**< Bit mask for LDMA_SYNCPRSCLREN */ #define _LDMA_CTRL_SYNCPRSCLREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CTRL */ #define LDMA_CTRL_SYNCPRSCLREN_DEFAULT (_LDMA_CTRL_SYNCPRSCLREN_DEFAULT << 8) /**< Shifted mode DEFAULT for LDMA_CTRL */ #define _LDMA_CTRL_NUMFIXED_SHIFT 24 /**< Shift value for LDMA_NUMFIXED */ #define _LDMA_CTRL_NUMFIXED_MASK 0x7000000UL /**< Bit mask for LDMA_NUMFIXED */ #define _LDMA_CTRL_NUMFIXED_DEFAULT 0x00000007UL /**< Mode DEFAULT for LDMA_CTRL */ #define LDMA_CTRL_NUMFIXED_DEFAULT (_LDMA_CTRL_NUMFIXED_DEFAULT << 24) /**< Shifted mode DEFAULT for LDMA_CTRL */ /* Bit fields for LDMA STATUS */ #define _LDMA_STATUS_RESETVALUE 0x08100000UL /**< Default value for LDMA_STATUS */ #define _LDMA_STATUS_MASK 0x1F1F073BUL /**< Mask for LDMA_STATUS */ #define LDMA_STATUS_ANYBUSY (0x1UL << 0) /**< Any DMA Channel Busy */ #define _LDMA_STATUS_ANYBUSY_SHIFT 0 /**< Shift value for LDMA_ANYBUSY */ #define _LDMA_STATUS_ANYBUSY_MASK 0x1UL /**< Bit mask for LDMA_ANYBUSY */ #define _LDMA_STATUS_ANYBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_STATUS */ #define LDMA_STATUS_ANYBUSY_DEFAULT (_LDMA_STATUS_ANYBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_STATUS */ #define LDMA_STATUS_ANYREQ (0x1UL << 1) /**< Any DMA Channel Request Pending */ #define _LDMA_STATUS_ANYREQ_SHIFT 1 /**< Shift value for LDMA_ANYREQ */ #define _LDMA_STATUS_ANYREQ_MASK 0x2UL /**< Bit mask for LDMA_ANYREQ */ #define _LDMA_STATUS_ANYREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_STATUS */ #define LDMA_STATUS_ANYREQ_DEFAULT (_LDMA_STATUS_ANYREQ_DEFAULT << 1) /**< Shifted mode DEFAULT for LDMA_STATUS */ #define _LDMA_STATUS_CHGRANT_SHIFT 3 /**< Shift value for LDMA_CHGRANT */ #define _LDMA_STATUS_CHGRANT_MASK 0x38UL /**< Bit mask for LDMA_CHGRANT */ #define _LDMA_STATUS_CHGRANT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_STATUS */ #define LDMA_STATUS_CHGRANT_DEFAULT (_LDMA_STATUS_CHGRANT_DEFAULT << 3) /**< Shifted mode DEFAULT for LDMA_STATUS */ #define _LDMA_STATUS_CHERROR_SHIFT 8 /**< Shift value for LDMA_CHERROR */ #define _LDMA_STATUS_CHERROR_MASK 0x700UL /**< Bit mask for LDMA_CHERROR */ #define _LDMA_STATUS_CHERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_STATUS */ #define LDMA_STATUS_CHERROR_DEFAULT (_LDMA_STATUS_CHERROR_DEFAULT << 8) /**< Shifted mode DEFAULT for LDMA_STATUS */ #define _LDMA_STATUS_FIFOLEVEL_SHIFT 16 /**< Shift value for LDMA_FIFOLEVEL */ #define _LDMA_STATUS_FIFOLEVEL_MASK 0x1F0000UL /**< Bit mask for LDMA_FIFOLEVEL */ #define _LDMA_STATUS_FIFOLEVEL_DEFAULT 0x00000010UL /**< Mode DEFAULT for LDMA_STATUS */ #define LDMA_STATUS_FIFOLEVEL_DEFAULT (_LDMA_STATUS_FIFOLEVEL_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_STATUS */ #define _LDMA_STATUS_CHNUM_SHIFT 24 /**< Shift value for LDMA_CHNUM */ #define _LDMA_STATUS_CHNUM_MASK 0x1F000000UL /**< Bit mask for LDMA_CHNUM */ #define _LDMA_STATUS_CHNUM_DEFAULT 0x00000008UL /**< Mode DEFAULT for LDMA_STATUS */ #define LDMA_STATUS_CHNUM_DEFAULT (_LDMA_STATUS_CHNUM_DEFAULT << 24) /**< Shifted mode DEFAULT for LDMA_STATUS */ /* Bit fields for LDMA SYNC */ #define _LDMA_SYNC_RESETVALUE 0x00000000UL /**< Default value for LDMA_SYNC */ #define _LDMA_SYNC_MASK 0x000000FFUL /**< Mask for LDMA_SYNC */ #define _LDMA_SYNC_SYNCTRIG_SHIFT 0 /**< Shift value for LDMA_SYNCTRIG */ #define _LDMA_SYNC_SYNCTRIG_MASK 0xFFUL /**< Bit mask for LDMA_SYNCTRIG */ #define _LDMA_SYNC_SYNCTRIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNC */ #define LDMA_SYNC_SYNCTRIG_DEFAULT (_LDMA_SYNC_SYNCTRIG_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SYNC */ /* Bit fields for LDMA CHEN */ #define _LDMA_CHEN_RESETVALUE 0x00000000UL /**< Default value for LDMA_CHEN */ #define _LDMA_CHEN_MASK 0x000000FFUL /**< Mask for LDMA_CHEN */ #define _LDMA_CHEN_CHEN_SHIFT 0 /**< Shift value for LDMA_CHEN */ #define _LDMA_CHEN_CHEN_MASK 0xFFUL /**< Bit mask for LDMA_CHEN */ #define _LDMA_CHEN_CHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHEN */ #define LDMA_CHEN_CHEN_DEFAULT (_LDMA_CHEN_CHEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CHEN */ /* Bit fields for LDMA CHBUSY */ #define _LDMA_CHBUSY_RESETVALUE 0x00000000UL /**< Default value for LDMA_CHBUSY */ #define _LDMA_CHBUSY_MASK 0x000000FFUL /**< Mask for LDMA_CHBUSY */ #define _LDMA_CHBUSY_BUSY_SHIFT 0 /**< Shift value for LDMA_BUSY */ #define _LDMA_CHBUSY_BUSY_MASK 0xFFUL /**< Bit mask for LDMA_BUSY */ #define _LDMA_CHBUSY_BUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHBUSY */ #define LDMA_CHBUSY_BUSY_DEFAULT (_LDMA_CHBUSY_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CHBUSY */ /* Bit fields for LDMA CHDONE */ #define _LDMA_CHDONE_RESETVALUE 0x00000000UL /**< Default value for LDMA_CHDONE */ #define _LDMA_CHDONE_MASK 0x000000FFUL /**< Mask for LDMA_CHDONE */ #define _LDMA_CHDONE_CHDONE_SHIFT 0 /**< Shift value for LDMA_CHDONE */ #define _LDMA_CHDONE_CHDONE_MASK 0xFFUL /**< Bit mask for LDMA_CHDONE */ #define _LDMA_CHDONE_CHDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDONE */ #define LDMA_CHDONE_CHDONE_DEFAULT (_LDMA_CHDONE_CHDONE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CHDONE */ /* Bit fields for LDMA DBGHALT */ #define _LDMA_DBGHALT_RESETVALUE 0x00000000UL /**< Default value for LDMA_DBGHALT */ #define _LDMA_DBGHALT_MASK 0x000000FFUL /**< Mask for LDMA_DBGHALT */ #define _LDMA_DBGHALT_DBGHALT_SHIFT 0 /**< Shift value for LDMA_DBGHALT */ #define _LDMA_DBGHALT_DBGHALT_MASK 0xFFUL /**< Bit mask for LDMA_DBGHALT */ #define _LDMA_DBGHALT_DBGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_DBGHALT */ #define LDMA_DBGHALT_DBGHALT_DEFAULT (_LDMA_DBGHALT_DBGHALT_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_DBGHALT */ /* Bit fields for LDMA SWREQ */ #define _LDMA_SWREQ_RESETVALUE 0x00000000UL /**< Default value for LDMA_SWREQ */ #define _LDMA_SWREQ_MASK 0x000000FFUL /**< Mask for LDMA_SWREQ */ #define _LDMA_SWREQ_SWREQ_SHIFT 0 /**< Shift value for LDMA_SWREQ */ #define _LDMA_SWREQ_SWREQ_MASK 0xFFUL /**< Bit mask for LDMA_SWREQ */ #define _LDMA_SWREQ_SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SWREQ */ #define LDMA_SWREQ_SWREQ_DEFAULT (_LDMA_SWREQ_SWREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SWREQ */ /* Bit fields for LDMA REQDIS */ #define _LDMA_REQDIS_RESETVALUE 0x00000000UL /**< Default value for LDMA_REQDIS */ #define _LDMA_REQDIS_MASK 0x000000FFUL /**< Mask for LDMA_REQDIS */ #define _LDMA_REQDIS_REQDIS_SHIFT 0 /**< Shift value for LDMA_REQDIS */ #define _LDMA_REQDIS_REQDIS_MASK 0xFFUL /**< Bit mask for LDMA_REQDIS */ #define _LDMA_REQDIS_REQDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_REQDIS */ #define LDMA_REQDIS_REQDIS_DEFAULT (_LDMA_REQDIS_REQDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_REQDIS */ /* Bit fields for LDMA REQPEND */ #define _LDMA_REQPEND_RESETVALUE 0x00000000UL /**< Default value for LDMA_REQPEND */ #define _LDMA_REQPEND_MASK 0x000000FFUL /**< Mask for LDMA_REQPEND */ #define _LDMA_REQPEND_REQPEND_SHIFT 0 /**< Shift value for LDMA_REQPEND */ #define _LDMA_REQPEND_REQPEND_MASK 0xFFUL /**< Bit mask for LDMA_REQPEND */ #define _LDMA_REQPEND_REQPEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_REQPEND */ #define LDMA_REQPEND_REQPEND_DEFAULT (_LDMA_REQPEND_REQPEND_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_REQPEND */ /* Bit fields for LDMA LINKLOAD */ #define _LDMA_LINKLOAD_RESETVALUE 0x00000000UL /**< Default value for LDMA_LINKLOAD */ #define _LDMA_LINKLOAD_MASK 0x000000FFUL /**< Mask for LDMA_LINKLOAD */ #define _LDMA_LINKLOAD_LINKLOAD_SHIFT 0 /**< Shift value for LDMA_LINKLOAD */ #define _LDMA_LINKLOAD_LINKLOAD_MASK 0xFFUL /**< Bit mask for LDMA_LINKLOAD */ #define _LDMA_LINKLOAD_LINKLOAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_LINKLOAD */ #define LDMA_LINKLOAD_LINKLOAD_DEFAULT (_LDMA_LINKLOAD_LINKLOAD_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_LINKLOAD */ /* Bit fields for LDMA REQCLEAR */ #define _LDMA_REQCLEAR_RESETVALUE 0x00000000UL /**< Default value for LDMA_REQCLEAR */ #define _LDMA_REQCLEAR_MASK 0x000000FFUL /**< Mask for LDMA_REQCLEAR */ #define _LDMA_REQCLEAR_REQCLEAR_SHIFT 0 /**< Shift value for LDMA_REQCLEAR */ #define _LDMA_REQCLEAR_REQCLEAR_MASK 0xFFUL /**< Bit mask for LDMA_REQCLEAR */ #define _LDMA_REQCLEAR_REQCLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_REQCLEAR */ #define LDMA_REQCLEAR_REQCLEAR_DEFAULT (_LDMA_REQCLEAR_REQCLEAR_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_REQCLEAR */ /* Bit fields for LDMA IF */ #define _LDMA_IF_RESETVALUE 0x00000000UL /**< Default value for LDMA_IF */ #define _LDMA_IF_MASK 0x800000FFUL /**< Mask for LDMA_IF */ #define _LDMA_IF_DONE_SHIFT 0 /**< Shift value for LDMA_DONE */ #define _LDMA_IF_DONE_MASK 0xFFUL /**< Bit mask for LDMA_DONE */ #define _LDMA_IF_DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */ #define LDMA_IF_DONE_DEFAULT (_LDMA_IF_DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_IF */ #define LDMA_IF_ERROR (0x1UL << 31) /**< Transfer Error Interrupt Flag */ #define _LDMA_IF_ERROR_SHIFT 31 /**< Shift value for LDMA_ERROR */ #define _LDMA_IF_ERROR_MASK 0x80000000UL /**< Bit mask for LDMA_ERROR */ #define _LDMA_IF_ERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */ #define LDMA_IF_ERROR_DEFAULT (_LDMA_IF_ERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_IF */ /* Bit fields for LDMA IFS */ #define _LDMA_IFS_RESETVALUE 0x00000000UL /**< Default value for LDMA_IFS */ #define _LDMA_IFS_MASK 0x800000FFUL /**< Mask for LDMA_IFS */ #define _LDMA_IFS_DONE_SHIFT 0 /**< Shift value for LDMA_DONE */ #define _LDMA_IFS_DONE_MASK 0xFFUL /**< Bit mask for LDMA_DONE */ #define _LDMA_IFS_DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IFS */ #define LDMA_IFS_DONE_DEFAULT (_LDMA_IFS_DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_IFS */ #define LDMA_IFS_ERROR (0x1UL << 31) /**< Set ERROR Interrupt Flag */ #define _LDMA_IFS_ERROR_SHIFT 31 /**< Shift value for LDMA_ERROR */ #define _LDMA_IFS_ERROR_MASK 0x80000000UL /**< Bit mask for LDMA_ERROR */ #define _LDMA_IFS_ERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IFS */ #define LDMA_IFS_ERROR_DEFAULT (_LDMA_IFS_ERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_IFS */ /* Bit fields for LDMA IFC */ #define _LDMA_IFC_RESETVALUE 0x00000000UL /**< Default value for LDMA_IFC */ #define _LDMA_IFC_MASK 0x800000FFUL /**< Mask for LDMA_IFC */ #define _LDMA_IFC_DONE_SHIFT 0 /**< Shift value for LDMA_DONE */ #define _LDMA_IFC_DONE_MASK 0xFFUL /**< Bit mask for LDMA_DONE */ #define _LDMA_IFC_DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IFC */ #define LDMA_IFC_DONE_DEFAULT (_LDMA_IFC_DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_IFC */ #define LDMA_IFC_ERROR (0x1UL << 31) /**< Clear ERROR Interrupt Flag */ #define _LDMA_IFC_ERROR_SHIFT 31 /**< Shift value for LDMA_ERROR */ #define _LDMA_IFC_ERROR_MASK 0x80000000UL /**< Bit mask for LDMA_ERROR */ #define _LDMA_IFC_ERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IFC */ #define LDMA_IFC_ERROR_DEFAULT (_LDMA_IFC_ERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_IFC */ /* Bit fields for LDMA IEN */ #define _LDMA_IEN_RESETVALUE 0x00000000UL /**< Default value for LDMA_IEN */ #define _LDMA_IEN_MASK 0x800000FFUL /**< Mask for LDMA_IEN */ #define _LDMA_IEN_DONE_SHIFT 0 /**< Shift value for LDMA_DONE */ #define _LDMA_IEN_DONE_MASK 0xFFUL /**< Bit mask for LDMA_DONE */ #define _LDMA_IEN_DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IEN */ #define LDMA_IEN_DONE_DEFAULT (_LDMA_IEN_DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_IEN */ #define LDMA_IEN_ERROR (0x1UL << 31) /**< ERROR Interrupt Enable */ #define _LDMA_IEN_ERROR_SHIFT 31 /**< Shift value for LDMA_ERROR */ #define _LDMA_IEN_ERROR_MASK 0x80000000UL /**< Bit mask for LDMA_ERROR */ #define _LDMA_IEN_ERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IEN */ #define LDMA_IEN_ERROR_DEFAULT (_LDMA_IEN_ERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_IEN */ /* Bit fields for LDMA CH_REQSEL */ #define _LDMA_CH_REQSEL_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_REQSEL */ #define _LDMA_CH_REQSEL_MASK 0x003F000FUL /**< Mask for LDMA_CH_REQSEL */ #define _LDMA_CH_REQSEL_SIGSEL_SHIFT 0 /**< Shift value for LDMA_SIGSEL */ #define _LDMA_CH_REQSEL_SIGSEL_MASK 0xFUL /**< Bit mask for LDMA_SIGSEL */ #define _LDMA_CH_REQSEL_SIGSEL_PRSREQ0 0x00000000UL /**< Mode PRSREQ0 for LDMA_CH_REQSEL */ #define _LDMA_CH_REQSEL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for LDMA_CH_REQSEL */ #define _LDMA_CH_REQSEL_SIGSEL_VDAC0CH0 0x00000000UL /**< Mode VDAC0CH0 for LDMA_CH_REQSEL */ #define _LDMA_CH_REQSEL_SIGSEL_USART0RXDATAV 0x00000000UL /**< Mode USART0RXDATAV for LDMA_CH_REQSEL */ #define _LDMA_CH_REQSEL_SIGSEL_USART1RXDATAV 0x00000000UL /**< Mode USART1RXDATAV for LDMA_CH_REQSEL */ #define _LDMA_CH_REQSEL_SIGSEL_USART2RXDATAV 0x00000000UL /**< Mode USART2RXDATAV for LDMA_CH_REQSEL */ #define _LDMA_CH_REQSEL_SIGSEL_USART3RXDATAV 0x00000000UL /**< Mode USART3RXDATAV for LDMA_CH_REQSEL */ #define _LDMA_CH_REQSEL_SIGSEL_LEUART0RXDATAV 0x00000000UL /**< Mode LEUART0RXDATAV for LDMA_CH_REQSEL */ #define _LDMA_CH_REQSEL_SIGSEL_I2C0RXDATAV 0x00000000UL /**< Mode I2C0RXDATAV for LDMA_CH_REQSEL */ #define _LDMA_CH_REQSEL_SIGSEL_I2C1RXDATAV 0x00000000UL /**< Mode I2C1RXDATAV for LDMA_CH_REQSEL */ #define _LDMA_CH_REQSEL_SIGSEL_TIMER0UFOF 0x00000000UL /**< Mode TIMER0UFOF for LDMA_CH_REQSEL */ #define _LDMA_CH_REQSEL_SIGSEL_TIMER1UFOF 0x00000000UL /**< Mode TIMER1UFOF for LDMA_CH_REQSEL */ #define _LDMA_CH_REQSEL_SIGSEL_WTIMER0UFOF 0x00000000UL /**< Mode WTIMER0UFOF for LDMA_CH_REQSEL */ #define _LDMA_CH_REQSEL_SIGSEL_WTIMER1UFOF 0x00000000UL /**< Mode WTIMER1UFOF for LDMA_CH_REQSEL */ #define _LDMA_CH_REQSEL_SIGSEL_MSCWDATA 0x00000000UL /**< Mode MSCWDATA for LDMA_CH_REQSEL */ #define _LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0WR 0x00000000UL /**< Mode CRYPTO0DATA0WR for LDMA_CH_REQSEL */ #define _LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0WR _LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0WR /**< Alias for mode CRYPTO0DATA0WR */ #define _LDMA_CH_REQSEL_SIGSEL_CSENDATA 0x00000000UL /**< Mode CSENDATA for LDMA_CH_REQSEL */ #define _LDMA_CH_REQSEL_SIGSEL_LESENSEBUFDATAV 0x00000000UL /**< Mode LESENSEBUFDATAV for LDMA_CH_REQSEL */ #define _LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0WR 0x00000000UL /**< Mode CRYPTO1DATA0WR for LDMA_CH_REQSEL */ #define _LDMA_CH_REQSEL_SIGSEL_PRSREQ1 0x00000001UL /**< Mode PRSREQ1 for LDMA_CH_REQSEL */ #define _LDMA_CH_REQSEL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for LDMA_CH_REQSEL */ #define _LDMA_CH_REQSEL_SIGSEL_VDAC0CH1 0x00000001UL /**< Mode VDAC0CH1 for LDMA_CH_REQSEL */ #define _LDMA_CH_REQSEL_SIGSEL_USART0TXBL 0x00000001UL /**< Mode USART0TXBL for LDMA_CH_REQSEL */ #define _LDMA_CH_REQSEL_SIGSEL_USART1TXBL 0x00000001UL /**< Mode USART1TXBL for LDMA_CH_REQSEL */ #define _LDMA_CH_REQSEL_SIGSEL_USART2TXBL 0x00000001UL /**< Mode USART2TXBL for LDMA_CH_REQSEL */ #define _LDMA_CH_REQSEL_SIGSEL_USART3TXBL 0x00000001UL /**< Mode USART3TXBL for LDMA_CH_REQSEL */ #define _LDMA_CH_REQSEL_SIGSEL_LEUART0TXBL 0x00000001UL /**< Mode LEUART0TXBL for LDMA_CH_REQSEL */ #define _LDMA_CH_REQSEL_SIGSEL_I2C0TXBL 0x00000001UL /**< Mode I2C0TXBL for LDMA_CH_REQSEL */ #define _LDMA_CH_REQSEL_SIGSEL_I2C1TXBL 0x00000001UL /**< Mode I2C1TXBL for LDMA_CH_REQSEL */ #define _LDMA_CH_REQSEL_SIGSEL_TIMER0CC0 0x00000001UL /**< Mode TIMER0CC0 for LDMA_CH_REQSEL */ #define _LDMA_CH_REQSEL_SIGSEL_TIMER1CC0 0x00000001UL /**< Mode TIMER1CC0 for LDMA_CH_REQSEL */ #define _LDMA_CH_REQSEL_SIGSEL_WTIMER0CC0 0x00000001UL /**< Mode WTIMER0CC0 for LDMA_CH_REQSEL */ #define _LDMA_CH_REQSEL_SIGSEL_WTIMER1CC0 0x00000001UL /**< Mode WTIMER1CC0 for LDMA_CH_REQSEL */ #define _LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0XWR 0x00000001UL /**< Mode CRYPTO0DATA0XWR for LDMA_CH_REQSEL */ #define _LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0XWR _LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0XWR /**< Alias for mode CRYPTO0DATA0XWR */ #define _LDMA_CH_REQSEL_SIGSEL_CSENBSLN 0x00000001UL /**< Mode CSENBSLN for LDMA_CH_REQSEL */ #define _LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0XWR 0x00000001UL /**< Mode CRYPTO1DATA0XWR for LDMA_CH_REQSEL */ #define _LDMA_CH_REQSEL_SIGSEL_USART0TXEMPTY 0x00000002UL /**< Mode USART0TXEMPTY for LDMA_CH_REQSEL */ #define _LDMA_CH_REQSEL_SIGSEL_USART1TXEMPTY 0x00000002UL /**< Mode USART1TXEMPTY for LDMA_CH_REQSEL */ #define _LDMA_CH_REQSEL_SIGSEL_USART2TXEMPTY 0x00000002UL /**< Mode USART2TXEMPTY for LDMA_CH_REQSEL */ #define _LDMA_CH_REQSEL_SIGSEL_USART3TXEMPTY 0x00000002UL /**< Mode USART3TXEMPTY for LDMA_CH_REQSEL */ #define _LDMA_CH_REQSEL_SIGSEL_LEUART0TXEMPTY 0x00000002UL /**< Mode LEUART0TXEMPTY for LDMA_CH_REQSEL */ #define _LDMA_CH_REQSEL_SIGSEL_TIMER0CC1 0x00000002UL /**< Mode TIMER0CC1 for LDMA_CH_REQSEL */ #define _LDMA_CH_REQSEL_SIGSEL_TIMER1CC1 0x00000002UL /**< Mode TIMER1CC1 for LDMA_CH_REQSEL */ #define _LDMA_CH_REQSEL_SIGSEL_WTIMER0CC1 0x00000002UL /**< Mode WTIMER0CC1 for LDMA_CH_REQSEL */ #define _LDMA_CH_REQSEL_SIGSEL_WTIMER1CC1 0x00000002UL /**< Mode WTIMER1CC1 for LDMA_CH_REQSEL */ #define _LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0RD 0x00000002UL /**< Mode CRYPTO0DATA0RD for LDMA_CH_REQSEL */ #define _LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0RD _LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0RD /**< Alias for mode CRYPTO0DATA0RD */ #define _LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0RD 0x00000002UL /**< Mode CRYPTO1DATA0RD for LDMA_CH_REQSEL */ #define _LDMA_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT 0x00000003UL /**< Mode USART1RXDATAVRIGHT for LDMA_CH_REQSEL */ #define _LDMA_CH_REQSEL_SIGSEL_USART3RXDATAVRIGHT 0x00000003UL /**< Mode USART3RXDATAVRIGHT for LDMA_CH_REQSEL */ #define _LDMA_CH_REQSEL_SIGSEL_TIMER0CC2 0x00000003UL /**< Mode TIMER0CC2 for LDMA_CH_REQSEL */ #define _LDMA_CH_REQSEL_SIGSEL_TIMER1CC2 0x00000003UL /**< Mode TIMER1CC2 for LDMA_CH_REQSEL */ #define _LDMA_CH_REQSEL_SIGSEL_WTIMER0CC2 0x00000003UL /**< Mode WTIMER0CC2 for LDMA_CH_REQSEL */ #define _LDMA_CH_REQSEL_SIGSEL_WTIMER1CC2 0x00000003UL /**< Mode WTIMER1CC2 for LDMA_CH_REQSEL */ #define _LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1WR 0x00000003UL /**< Mode CRYPTO0DATA1WR for LDMA_CH_REQSEL */ #define _LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1WR _LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1WR /**< Alias for mode CRYPTO0DATA1WR */ #define _LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA1WR 0x00000003UL /**< Mode CRYPTO1DATA1WR for LDMA_CH_REQSEL */ #define _LDMA_CH_REQSEL_SIGSEL_USART1TXBLRIGHT 0x00000004UL /**< Mode USART1TXBLRIGHT for LDMA_CH_REQSEL */ #define _LDMA_CH_REQSEL_SIGSEL_USART3TXBLRIGHT 0x00000004UL /**< Mode USART3TXBLRIGHT for LDMA_CH_REQSEL */ #define _LDMA_CH_REQSEL_SIGSEL_TIMER1CC3 0x00000004UL /**< Mode TIMER1CC3 for LDMA_CH_REQSEL */ #define _LDMA_CH_REQSEL_SIGSEL_WTIMER1CC3 0x00000004UL /**< Mode WTIMER1CC3 for LDMA_CH_REQSEL */ #define _LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1RD 0x00000004UL /**< Mode CRYPTO0DATA1RD for LDMA_CH_REQSEL */ #define _LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1RD _LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1RD /**< Alias for mode CRYPTO0DATA1RD */ #define _LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA1RD 0x00000004UL /**< Mode CRYPTO1DATA1RD for LDMA_CH_REQSEL */ #define LDMA_CH_REQSEL_SIGSEL_PRSREQ0 (_LDMA_CH_REQSEL_SIGSEL_PRSREQ0 << 0) /**< Shifted mode PRSREQ0 for LDMA_CH_REQSEL */ #define LDMA_CH_REQSEL_SIGSEL_ADC0SINGLE (_LDMA_CH_REQSEL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for LDMA_CH_REQSEL */ #define LDMA_CH_REQSEL_SIGSEL_VDAC0CH0 (_LDMA_CH_REQSEL_SIGSEL_VDAC0CH0 << 0) /**< Shifted mode VDAC0CH0 for LDMA_CH_REQSEL */ #define LDMA_CH_REQSEL_SIGSEL_USART0RXDATAV (_LDMA_CH_REQSEL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for LDMA_CH_REQSEL */ #define LDMA_CH_REQSEL_SIGSEL_USART1RXDATAV (_LDMA_CH_REQSEL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for LDMA_CH_REQSEL */ #define LDMA_CH_REQSEL_SIGSEL_USART2RXDATAV (_LDMA_CH_REQSEL_SIGSEL_USART2RXDATAV << 0) /**< Shifted mode USART2RXDATAV for LDMA_CH_REQSEL */ #define LDMA_CH_REQSEL_SIGSEL_USART3RXDATAV (_LDMA_CH_REQSEL_SIGSEL_USART3RXDATAV << 0) /**< Shifted mode USART3RXDATAV for LDMA_CH_REQSEL */ #define LDMA_CH_REQSEL_SIGSEL_LEUART0RXDATAV (_LDMA_CH_REQSEL_SIGSEL_LEUART0RXDATAV << 0) /**< Shifted mode LEUART0RXDATAV for LDMA_CH_REQSEL */ #define LDMA_CH_REQSEL_SIGSEL_I2C0RXDATAV (_LDMA_CH_REQSEL_SIGSEL_I2C0RXDATAV << 0) /**< Shifted mode I2C0RXDATAV for LDMA_CH_REQSEL */ #define LDMA_CH_REQSEL_SIGSEL_I2C1RXDATAV (_LDMA_CH_REQSEL_SIGSEL_I2C1RXDATAV << 0) /**< Shifted mode I2C1RXDATAV for LDMA_CH_REQSEL */ #define LDMA_CH_REQSEL_SIGSEL_TIMER0UFOF (_LDMA_CH_REQSEL_SIGSEL_TIMER0UFOF << 0) /**< Shifted mode TIMER0UFOF for LDMA_CH_REQSEL */ #define LDMA_CH_REQSEL_SIGSEL_TIMER1UFOF (_LDMA_CH_REQSEL_SIGSEL_TIMER1UFOF << 0) /**< Shifted mode TIMER1UFOF for LDMA_CH_REQSEL */ #define LDMA_CH_REQSEL_SIGSEL_WTIMER0UFOF (_LDMA_CH_REQSEL_SIGSEL_WTIMER0UFOF << 0) /**< Shifted mode WTIMER0UFOF for LDMA_CH_REQSEL */ #define LDMA_CH_REQSEL_SIGSEL_WTIMER1UFOF (_LDMA_CH_REQSEL_SIGSEL_WTIMER1UFOF << 0) /**< Shifted mode WTIMER1UFOF for LDMA_CH_REQSEL */ #define LDMA_CH_REQSEL_SIGSEL_MSCWDATA (_LDMA_CH_REQSEL_SIGSEL_MSCWDATA << 0) /**< Shifted mode MSCWDATA for LDMA_CH_REQSEL */ #define LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0WR (_LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0WR << 0) /**< Shifted mode CRYPTO0DATA0WR for LDMA_CH_REQSEL */ #define LDMA_CH_REQSEL_SIGSEL_CSENDATA (_LDMA_CH_REQSEL_SIGSEL_CSENDATA << 0) /**< Shifted mode CSENDATA for LDMA_CH_REQSEL */ #define LDMA_CH_REQSEL_SIGSEL_LESENSEBUFDATAV (_LDMA_CH_REQSEL_SIGSEL_LESENSEBUFDATAV << 0) /**< Shifted mode LESENSEBUFDATAV for LDMA_CH_REQSEL */ #define LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0WR (_LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0WR << 0) /**< Shifted mode CRYPTO1DATA0WR for LDMA_CH_REQSEL */ #define LDMA_CH_REQSEL_SIGSEL_PRSREQ1 (_LDMA_CH_REQSEL_SIGSEL_PRSREQ1 << 0) /**< Shifted mode PRSREQ1 for LDMA_CH_REQSEL */ #define LDMA_CH_REQSEL_SIGSEL_ADC0SCAN (_LDMA_CH_REQSEL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for LDMA_CH_REQSEL */ #define LDMA_CH_REQSEL_SIGSEL_VDAC0CH1 (_LDMA_CH_REQSEL_SIGSEL_VDAC0CH1 << 0) /**< Shifted mode VDAC0CH1 for LDMA_CH_REQSEL */ #define LDMA_CH_REQSEL_SIGSEL_USART0TXBL (_LDMA_CH_REQSEL_SIGSEL_USART0TXBL << 0) /**< Shifted mode USART0TXBL for LDMA_CH_REQSEL */ #define LDMA_CH_REQSEL_SIGSEL_USART1TXBL (_LDMA_CH_REQSEL_SIGSEL_USART1TXBL << 0) /**< Shifted mode USART1TXBL for LDMA_CH_REQSEL */ #define LDMA_CH_REQSEL_SIGSEL_USART2TXBL (_LDMA_CH_REQSEL_SIGSEL_USART2TXBL << 0) /**< Shifted mode USART2TXBL for LDMA_CH_REQSEL */ #define LDMA_CH_REQSEL_SIGSEL_USART3TXBL (_LDMA_CH_REQSEL_SIGSEL_USART3TXBL << 0) /**< Shifted mode USART3TXBL for LDMA_CH_REQSEL */ #define LDMA_CH_REQSEL_SIGSEL_LEUART0TXBL (_LDMA_CH_REQSEL_SIGSEL_LEUART0TXBL << 0) /**< Shifted mode LEUART0TXBL for LDMA_CH_REQSEL */ #define LDMA_CH_REQSEL_SIGSEL_I2C0TXBL (_LDMA_CH_REQSEL_SIGSEL_I2C0TXBL << 0) /**< Shifted mode I2C0TXBL for LDMA_CH_REQSEL */ #define LDMA_CH_REQSEL_SIGSEL_I2C1TXBL (_LDMA_CH_REQSEL_SIGSEL_I2C1TXBL << 0) /**< Shifted mode I2C1TXBL for LDMA_CH_REQSEL */ #define LDMA_CH_REQSEL_SIGSEL_TIMER0CC0 (_LDMA_CH_REQSEL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for LDMA_CH_REQSEL */ #define LDMA_CH_REQSEL_SIGSEL_TIMER1CC0 (_LDMA_CH_REQSEL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for LDMA_CH_REQSEL */ #define LDMA_CH_REQSEL_SIGSEL_WTIMER0CC0 (_LDMA_CH_REQSEL_SIGSEL_WTIMER0CC0 << 0) /**< Shifted mode WTIMER0CC0 for LDMA_CH_REQSEL */ #define LDMA_CH_REQSEL_SIGSEL_WTIMER1CC0 (_LDMA_CH_REQSEL_SIGSEL_WTIMER1CC0 << 0) /**< Shifted mode WTIMER1CC0 for LDMA_CH_REQSEL */ #define LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0XWR (_LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0XWR << 0) /**< Shifted mode CRYPTO0DATA0XWR for LDMA_CH_REQSEL */ #define LDMA_CH_REQSEL_SIGSEL_CSENBSLN (_LDMA_CH_REQSEL_SIGSEL_CSENBSLN << 0) /**< Shifted mode CSENBSLN for LDMA_CH_REQSEL */ #define LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0XWR (_LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0XWR << 0) /**< Shifted mode CRYPTO1DATA0XWR for LDMA_CH_REQSEL */ #define LDMA_CH_REQSEL_SIGSEL_USART0TXEMPTY (_LDMA_CH_REQSEL_SIGSEL_USART0TXEMPTY << 0) /**< Shifted mode USART0TXEMPTY for LDMA_CH_REQSEL */ #define LDMA_CH_REQSEL_SIGSEL_USART1TXEMPTY (_LDMA_CH_REQSEL_SIGSEL_USART1TXEMPTY << 0) /**< Shifted mode USART1TXEMPTY for LDMA_CH_REQSEL */ #define LDMA_CH_REQSEL_SIGSEL_USART2TXEMPTY (_LDMA_CH_REQSEL_SIGSEL_USART2TXEMPTY << 0) /**< Shifted mode USART2TXEMPTY for LDMA_CH_REQSEL */ #define LDMA_CH_REQSEL_SIGSEL_USART3TXEMPTY (_LDMA_CH_REQSEL_SIGSEL_USART3TXEMPTY << 0) /**< Shifted mode USART3TXEMPTY for LDMA_CH_REQSEL */ #define LDMA_CH_REQSEL_SIGSEL_LEUART0TXEMPTY (_LDMA_CH_REQSEL_SIGSEL_LEUART0TXEMPTY << 0) /**< Shifted mode LEUART0TXEMPTY for LDMA_CH_REQSEL */ #define LDMA_CH_REQSEL_SIGSEL_TIMER0CC1 (_LDMA_CH_REQSEL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for LDMA_CH_REQSEL */ #define LDMA_CH_REQSEL_SIGSEL_TIMER1CC1 (_LDMA_CH_REQSEL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for LDMA_CH_REQSEL */ #define LDMA_CH_REQSEL_SIGSEL_WTIMER0CC1 (_LDMA_CH_REQSEL_SIGSEL_WTIMER0CC1 << 0) /**< Shifted mode WTIMER0CC1 for LDMA_CH_REQSEL */ #define LDMA_CH_REQSEL_SIGSEL_WTIMER1CC1 (_LDMA_CH_REQSEL_SIGSEL_WTIMER1CC1 << 0) /**< Shifted mode WTIMER1CC1 for LDMA_CH_REQSEL */ #define LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0RD (_LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0RD << 0) /**< Shifted mode CRYPTO0DATA0RD for LDMA_CH_REQSEL */ #define LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0RD (_LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0RD << 0) /**< Shifted mode CRYPTO1DATA0RD for LDMA_CH_REQSEL */ #define LDMA_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT (_LDMA_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT << 0) /**< Shifted mode USART1RXDATAVRIGHT for LDMA_CH_REQSEL */ #define LDMA_CH_REQSEL_SIGSEL_USART3RXDATAVRIGHT (_LDMA_CH_REQSEL_SIGSEL_USART3RXDATAVRIGHT << 0) /**< Shifted mode USART3RXDATAVRIGHT for LDMA_CH_REQSEL */ #define LDMA_CH_REQSEL_SIGSEL_TIMER0CC2 (_LDMA_CH_REQSEL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for LDMA_CH_REQSEL */ #define LDMA_CH_REQSEL_SIGSEL_TIMER1CC2 (_LDMA_CH_REQSEL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for LDMA_CH_REQSEL */ #define LDMA_CH_REQSEL_SIGSEL_WTIMER0CC2 (_LDMA_CH_REQSEL_SIGSEL_WTIMER0CC2 << 0) /**< Shifted mode WTIMER0CC2 for LDMA_CH_REQSEL */ #define LDMA_CH_REQSEL_SIGSEL_WTIMER1CC2 (_LDMA_CH_REQSEL_SIGSEL_WTIMER1CC2 << 0) /**< Shifted mode WTIMER1CC2 for LDMA_CH_REQSEL */ #define LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1WR (_LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1WR << 0) /**< Shifted mode CRYPTO0DATA1WR for LDMA_CH_REQSEL */ #define LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA1WR (_LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA1WR << 0) /**< Shifted mode CRYPTO1DATA1WR for LDMA_CH_REQSEL */ #define LDMA_CH_REQSEL_SIGSEL_USART1TXBLRIGHT (_LDMA_CH_REQSEL_SIGSEL_USART1TXBLRIGHT << 0) /**< Shifted mode USART1TXBLRIGHT for LDMA_CH_REQSEL */ #define LDMA_CH_REQSEL_SIGSEL_USART3TXBLRIGHT (_LDMA_CH_REQSEL_SIGSEL_USART3TXBLRIGHT << 0) /**< Shifted mode USART3TXBLRIGHT for LDMA_CH_REQSEL */ #define LDMA_CH_REQSEL_SIGSEL_TIMER1CC3 (_LDMA_CH_REQSEL_SIGSEL_TIMER1CC3 << 0) /**< Shifted mode TIMER1CC3 for LDMA_CH_REQSEL */ #define LDMA_CH_REQSEL_SIGSEL_WTIMER1CC3 (_LDMA_CH_REQSEL_SIGSEL_WTIMER1CC3 << 0) /**< Shifted mode WTIMER1CC3 for LDMA_CH_REQSEL */ #define LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1RD (_LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1RD << 0) /**< Shifted mode CRYPTO0DATA1RD for LDMA_CH_REQSEL */ #define LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA1RD (_LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA1RD << 0) /**< Shifted mode CRYPTO1DATA1RD for LDMA_CH_REQSEL */ #define _LDMA_CH_REQSEL_SOURCESEL_SHIFT 16 /**< Shift value for LDMA_SOURCESEL */ #define _LDMA_CH_REQSEL_SOURCESEL_MASK 0x3F0000UL /**< Bit mask for LDMA_SOURCESEL */ #define _LDMA_CH_REQSEL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for LDMA_CH_REQSEL */ #define _LDMA_CH_REQSEL_SOURCESEL_PRS 0x00000001UL /**< Mode PRS for LDMA_CH_REQSEL */ #define _LDMA_CH_REQSEL_SOURCESEL_ADC0 0x00000008UL /**< Mode ADC0 for LDMA_CH_REQSEL */ #define _LDMA_CH_REQSEL_SOURCESEL_VDAC0 0x0000000AUL /**< Mode VDAC0 for LDMA_CH_REQSEL */ #define _LDMA_CH_REQSEL_SOURCESEL_USART0 0x0000000CUL /**< Mode USART0 for LDMA_CH_REQSEL */ #define _LDMA_CH_REQSEL_SOURCESEL_USART1 0x0000000DUL /**< Mode USART1 for LDMA_CH_REQSEL */ #define _LDMA_CH_REQSEL_SOURCESEL_USART2 0x0000000EUL /**< Mode USART2 for LDMA_CH_REQSEL */ #define _LDMA_CH_REQSEL_SOURCESEL_USART3 0x0000000FUL /**< Mode USART3 for LDMA_CH_REQSEL */ #define _LDMA_CH_REQSEL_SOURCESEL_LEUART0 0x00000010UL /**< Mode LEUART0 for LDMA_CH_REQSEL */ #define _LDMA_CH_REQSEL_SOURCESEL_I2C0 0x00000014UL /**< Mode I2C0 for LDMA_CH_REQSEL */ #define _LDMA_CH_REQSEL_SOURCESEL_I2C1 0x00000015UL /**< Mode I2C1 for LDMA_CH_REQSEL */ #define _LDMA_CH_REQSEL_SOURCESEL_TIMER0 0x00000018UL /**< Mode TIMER0 for LDMA_CH_REQSEL */ #define _LDMA_CH_REQSEL_SOURCESEL_TIMER1 0x00000019UL /**< Mode TIMER1 for LDMA_CH_REQSEL */ #define _LDMA_CH_REQSEL_SOURCESEL_WTIMER0 0x0000001AUL /**< Mode WTIMER0 for LDMA_CH_REQSEL */ #define _LDMA_CH_REQSEL_SOURCESEL_WTIMER1 0x0000001BUL /**< Mode WTIMER1 for LDMA_CH_REQSEL */ #define _LDMA_CH_REQSEL_SOURCESEL_MSC 0x00000030UL /**< Mode MSC for LDMA_CH_REQSEL */ #define _LDMA_CH_REQSEL_SOURCESEL_CRYPTO0 0x00000031UL /**< Mode CRYPTO0 for LDMA_CH_REQSEL */ #define _LDMA_CH_REQSEL_SOURCESEL_CRYPTO _LDMA_CH_REQSEL_SOURCESEL_CRYPTO0 /**< Alias for mode CRYPTO0 */ #define _LDMA_CH_REQSEL_SOURCESEL_CSEN 0x00000032UL /**< Mode CSEN for LDMA_CH_REQSEL */ #define _LDMA_CH_REQSEL_SOURCESEL_LESENSE 0x00000033UL /**< Mode LESENSE for LDMA_CH_REQSEL */ #define _LDMA_CH_REQSEL_SOURCESEL_CRYPTO1 0x00000034UL /**< Mode CRYPTO1 for LDMA_CH_REQSEL */ #define LDMA_CH_REQSEL_SOURCESEL_NONE (_LDMA_CH_REQSEL_SOURCESEL_NONE << 16) /**< Shifted mode NONE for LDMA_CH_REQSEL */ #define LDMA_CH_REQSEL_SOURCESEL_PRS (_LDMA_CH_REQSEL_SOURCESEL_PRS << 16) /**< Shifted mode PRS for LDMA_CH_REQSEL */ #define LDMA_CH_REQSEL_SOURCESEL_ADC0 (_LDMA_CH_REQSEL_SOURCESEL_ADC0 << 16) /**< Shifted mode ADC0 for LDMA_CH_REQSEL */ #define LDMA_CH_REQSEL_SOURCESEL_VDAC0 (_LDMA_CH_REQSEL_SOURCESEL_VDAC0 << 16) /**< Shifted mode VDAC0 for LDMA_CH_REQSEL */ #define LDMA_CH_REQSEL_SOURCESEL_USART0 (_LDMA_CH_REQSEL_SOURCESEL_USART0 << 16) /**< Shifted mode USART0 for LDMA_CH_REQSEL */ #define LDMA_CH_REQSEL_SOURCESEL_USART1 (_LDMA_CH_REQSEL_SOURCESEL_USART1 << 16) /**< Shifted mode USART1 for LDMA_CH_REQSEL */ #define LDMA_CH_REQSEL_SOURCESEL_USART2 (_LDMA_CH_REQSEL_SOURCESEL_USART2 << 16) /**< Shifted mode USART2 for LDMA_CH_REQSEL */ #define LDMA_CH_REQSEL_SOURCESEL_USART3 (_LDMA_CH_REQSEL_SOURCESEL_USART3 << 16) /**< Shifted mode USART3 for LDMA_CH_REQSEL */ #define LDMA_CH_REQSEL_SOURCESEL_LEUART0 (_LDMA_CH_REQSEL_SOURCESEL_LEUART0 << 16) /**< Shifted mode LEUART0 for LDMA_CH_REQSEL */ #define LDMA_CH_REQSEL_SOURCESEL_I2C0 (_LDMA_CH_REQSEL_SOURCESEL_I2C0 << 16) /**< Shifted mode I2C0 for LDMA_CH_REQSEL */ #define LDMA_CH_REQSEL_SOURCESEL_I2C1 (_LDMA_CH_REQSEL_SOURCESEL_I2C1 << 16) /**< Shifted mode I2C1 for LDMA_CH_REQSEL */ #define LDMA_CH_REQSEL_SOURCESEL_TIMER0 (_LDMA_CH_REQSEL_SOURCESEL_TIMER0 << 16) /**< Shifted mode TIMER0 for LDMA_CH_REQSEL */ #define LDMA_CH_REQSEL_SOURCESEL_TIMER1 (_LDMA_CH_REQSEL_SOURCESEL_TIMER1 << 16) /**< Shifted mode TIMER1 for LDMA_CH_REQSEL */ #define LDMA_CH_REQSEL_SOURCESEL_WTIMER0 (_LDMA_CH_REQSEL_SOURCESEL_WTIMER0 << 16) /**< Shifted mode WTIMER0 for LDMA_CH_REQSEL */ #define LDMA_CH_REQSEL_SOURCESEL_WTIMER1 (_LDMA_CH_REQSEL_SOURCESEL_WTIMER1 << 16) /**< Shifted mode WTIMER1 for LDMA_CH_REQSEL */ #define LDMA_CH_REQSEL_SOURCESEL_MSC (_LDMA_CH_REQSEL_SOURCESEL_MSC << 16) /**< Shifted mode MSC for LDMA_CH_REQSEL */ #define LDMA_CH_REQSEL_SOURCESEL_CRYPTO0 (_LDMA_CH_REQSEL_SOURCESEL_CRYPTO0 << 16) /**< Shifted mode CRYPTO0 for LDMA_CH_REQSEL */ #define LDMA_CH_REQSEL_SOURCESEL_CSEN (_LDMA_CH_REQSEL_SOURCESEL_CSEN << 16) /**< Shifted mode CSEN for LDMA_CH_REQSEL */ #define LDMA_CH_REQSEL_SOURCESEL_LESENSE (_LDMA_CH_REQSEL_SOURCESEL_LESENSE << 16) /**< Shifted mode LESENSE for LDMA_CH_REQSEL */ #define LDMA_CH_REQSEL_SOURCESEL_CRYPTO1 (_LDMA_CH_REQSEL_SOURCESEL_CRYPTO1 << 16) /**< Shifted mode CRYPTO1 for LDMA_CH_REQSEL */ /* Bit fields for LDMA CH_CFG */ #define _LDMA_CH_CFG_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_CFG */ #define _LDMA_CH_CFG_MASK 0x00330000UL /**< Mask for LDMA_CH_CFG */ #define _LDMA_CH_CFG_ARBSLOTS_SHIFT 16 /**< Shift value for LDMA_ARBSLOTS */ #define _LDMA_CH_CFG_ARBSLOTS_MASK 0x30000UL /**< Bit mask for LDMA_ARBSLOTS */ #define _LDMA_CH_CFG_ARBSLOTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CFG */ #define _LDMA_CH_CFG_ARBSLOTS_ONE 0x00000000UL /**< Mode ONE for LDMA_CH_CFG */ #define _LDMA_CH_CFG_ARBSLOTS_TWO 0x00000001UL /**< Mode TWO for LDMA_CH_CFG */ #define _LDMA_CH_CFG_ARBSLOTS_FOUR 0x00000002UL /**< Mode FOUR for LDMA_CH_CFG */ #define _LDMA_CH_CFG_ARBSLOTS_EIGHT 0x00000003UL /**< Mode EIGHT for LDMA_CH_CFG */ #define LDMA_CH_CFG_ARBSLOTS_DEFAULT (_LDMA_CH_CFG_ARBSLOTS_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_CH_CFG */ #define LDMA_CH_CFG_ARBSLOTS_ONE (_LDMA_CH_CFG_ARBSLOTS_ONE << 16) /**< Shifted mode ONE for LDMA_CH_CFG */ #define LDMA_CH_CFG_ARBSLOTS_TWO (_LDMA_CH_CFG_ARBSLOTS_TWO << 16) /**< Shifted mode TWO for LDMA_CH_CFG */ #define LDMA_CH_CFG_ARBSLOTS_FOUR (_LDMA_CH_CFG_ARBSLOTS_FOUR << 16) /**< Shifted mode FOUR for LDMA_CH_CFG */ #define LDMA_CH_CFG_ARBSLOTS_EIGHT (_LDMA_CH_CFG_ARBSLOTS_EIGHT << 16) /**< Shifted mode EIGHT for LDMA_CH_CFG */ #define LDMA_CH_CFG_SRCINCSIGN (0x1UL << 20) /**< Source Address Increment Sign */ #define _LDMA_CH_CFG_SRCINCSIGN_SHIFT 20 /**< Shift value for LDMA_SRCINCSIGN */ #define _LDMA_CH_CFG_SRCINCSIGN_MASK 0x100000UL /**< Bit mask for LDMA_SRCINCSIGN */ #define _LDMA_CH_CFG_SRCINCSIGN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CFG */ #define _LDMA_CH_CFG_SRCINCSIGN_POSITIVE 0x00000000UL /**< Mode POSITIVE for LDMA_CH_CFG */ #define _LDMA_CH_CFG_SRCINCSIGN_NEGATIVE 0x00000001UL /**< Mode NEGATIVE for LDMA_CH_CFG */ #define LDMA_CH_CFG_SRCINCSIGN_DEFAULT (_LDMA_CH_CFG_SRCINCSIGN_DEFAULT << 20) /**< Shifted mode DEFAULT for LDMA_CH_CFG */ #define LDMA_CH_CFG_SRCINCSIGN_POSITIVE (_LDMA_CH_CFG_SRCINCSIGN_POSITIVE << 20) /**< Shifted mode POSITIVE for LDMA_CH_CFG */ #define LDMA_CH_CFG_SRCINCSIGN_NEGATIVE (_LDMA_CH_CFG_SRCINCSIGN_NEGATIVE << 20) /**< Shifted mode NEGATIVE for LDMA_CH_CFG */ #define LDMA_CH_CFG_DSTINCSIGN (0x1UL << 21) /**< Destination Address Increment Sign */ #define _LDMA_CH_CFG_DSTINCSIGN_SHIFT 21 /**< Shift value for LDMA_DSTINCSIGN */ #define _LDMA_CH_CFG_DSTINCSIGN_MASK 0x200000UL /**< Bit mask for LDMA_DSTINCSIGN */ #define _LDMA_CH_CFG_DSTINCSIGN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CFG */ #define _LDMA_CH_CFG_DSTINCSIGN_POSITIVE 0x00000000UL /**< Mode POSITIVE for LDMA_CH_CFG */ #define _LDMA_CH_CFG_DSTINCSIGN_NEGATIVE 0x00000001UL /**< Mode NEGATIVE for LDMA_CH_CFG */ #define LDMA_CH_CFG_DSTINCSIGN_DEFAULT (_LDMA_CH_CFG_DSTINCSIGN_DEFAULT << 21) /**< Shifted mode DEFAULT for LDMA_CH_CFG */ #define LDMA_CH_CFG_DSTINCSIGN_POSITIVE (_LDMA_CH_CFG_DSTINCSIGN_POSITIVE << 21) /**< Shifted mode POSITIVE for LDMA_CH_CFG */ #define LDMA_CH_CFG_DSTINCSIGN_NEGATIVE (_LDMA_CH_CFG_DSTINCSIGN_NEGATIVE << 21) /**< Shifted mode NEGATIVE for LDMA_CH_CFG */ /* Bit fields for LDMA CH_LOOP */ #define _LDMA_CH_LOOP_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_LOOP */ #define _LDMA_CH_LOOP_MASK 0x000000FFUL /**< Mask for LDMA_CH_LOOP */ #define _LDMA_CH_LOOP_LOOPCNT_SHIFT 0 /**< Shift value for LDMA_LOOPCNT */ #define _LDMA_CH_LOOP_LOOPCNT_MASK 0xFFUL /**< Bit mask for LDMA_LOOPCNT */ #define _LDMA_CH_LOOP_LOOPCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_LOOP */ #define LDMA_CH_LOOP_LOOPCNT_DEFAULT (_LDMA_CH_LOOP_LOOPCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_LOOP */ /* Bit fields for LDMA CH_CTRL */ #define _LDMA_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_CTRL */ #define _LDMA_CH_CTRL_MASK 0xFFFFFFFBUL /**< Mask for LDMA_CH_CTRL */ #define _LDMA_CH_CTRL_STRUCTTYPE_SHIFT 0 /**< Shift value for LDMA_STRUCTTYPE */ #define _LDMA_CH_CTRL_STRUCTTYPE_MASK 0x3UL /**< Bit mask for LDMA_STRUCTTYPE */ #define _LDMA_CH_CTRL_STRUCTTYPE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ #define _LDMA_CH_CTRL_STRUCTTYPE_TRANSFER 0x00000000UL /**< Mode TRANSFER for LDMA_CH_CTRL */ #define _LDMA_CH_CTRL_STRUCTTYPE_SYNCHRONIZE 0x00000001UL /**< Mode SYNCHRONIZE for LDMA_CH_CTRL */ #define _LDMA_CH_CTRL_STRUCTTYPE_WRITE 0x00000002UL /**< Mode WRITE for LDMA_CH_CTRL */ #define LDMA_CH_CTRL_STRUCTTYPE_DEFAULT (_LDMA_CH_CTRL_STRUCTTYPE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ #define LDMA_CH_CTRL_STRUCTTYPE_TRANSFER (_LDMA_CH_CTRL_STRUCTTYPE_TRANSFER << 0) /**< Shifted mode TRANSFER for LDMA_CH_CTRL */ #define LDMA_CH_CTRL_STRUCTTYPE_SYNCHRONIZE (_LDMA_CH_CTRL_STRUCTTYPE_SYNCHRONIZE << 0) /**< Shifted mode SYNCHRONIZE for LDMA_CH_CTRL */ #define LDMA_CH_CTRL_STRUCTTYPE_WRITE (_LDMA_CH_CTRL_STRUCTTYPE_WRITE << 0) /**< Shifted mode WRITE for LDMA_CH_CTRL */ #define LDMA_CH_CTRL_STRUCTREQ (0x1UL << 3) /**< Structure DMA Transfer Request */ #define _LDMA_CH_CTRL_STRUCTREQ_SHIFT 3 /**< Shift value for LDMA_STRUCTREQ */ #define _LDMA_CH_CTRL_STRUCTREQ_MASK 0x8UL /**< Bit mask for LDMA_STRUCTREQ */ #define _LDMA_CH_CTRL_STRUCTREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ #define LDMA_CH_CTRL_STRUCTREQ_DEFAULT (_LDMA_CH_CTRL_STRUCTREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ #define _LDMA_CH_CTRL_XFERCNT_SHIFT 4 /**< Shift value for LDMA_XFERCNT */ #define _LDMA_CH_CTRL_XFERCNT_MASK 0x7FF0UL /**< Bit mask for LDMA_XFERCNT */ #define _LDMA_CH_CTRL_XFERCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ #define LDMA_CH_CTRL_XFERCNT_DEFAULT (_LDMA_CH_CTRL_XFERCNT_DEFAULT << 4) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ #define LDMA_CH_CTRL_BYTESWAP (0x1UL << 15) /**< Endian Byte Swap */ #define _LDMA_CH_CTRL_BYTESWAP_SHIFT 15 /**< Shift value for LDMA_BYTESWAP */ #define _LDMA_CH_CTRL_BYTESWAP_MASK 0x8000UL /**< Bit mask for LDMA_BYTESWAP */ #define _LDMA_CH_CTRL_BYTESWAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ #define LDMA_CH_CTRL_BYTESWAP_DEFAULT (_LDMA_CH_CTRL_BYTESWAP_DEFAULT << 15) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ #define _LDMA_CH_CTRL_BLOCKSIZE_SHIFT 16 /**< Shift value for LDMA_BLOCKSIZE */ #define _LDMA_CH_CTRL_BLOCKSIZE_MASK 0xF0000UL /**< Bit mask for LDMA_BLOCKSIZE */ #define _LDMA_CH_CTRL_BLOCKSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ #define _LDMA_CH_CTRL_BLOCKSIZE_UNIT1 0x00000000UL /**< Mode UNIT1 for LDMA_CH_CTRL */ #define _LDMA_CH_CTRL_BLOCKSIZE_UNIT2 0x00000001UL /**< Mode UNIT2 for LDMA_CH_CTRL */ #define _LDMA_CH_CTRL_BLOCKSIZE_UNIT3 0x00000002UL /**< Mode UNIT3 for LDMA_CH_CTRL */ #define _LDMA_CH_CTRL_BLOCKSIZE_UNIT4 0x00000003UL /**< Mode UNIT4 for LDMA_CH_CTRL */ #define _LDMA_CH_CTRL_BLOCKSIZE_UNIT6 0x00000004UL /**< Mode UNIT6 for LDMA_CH_CTRL */ #define _LDMA_CH_CTRL_BLOCKSIZE_UNIT8 0x00000005UL /**< Mode UNIT8 for LDMA_CH_CTRL */ #define _LDMA_CH_CTRL_BLOCKSIZE_UNIT16 0x00000007UL /**< Mode UNIT16 for LDMA_CH_CTRL */ #define _LDMA_CH_CTRL_BLOCKSIZE_UNIT32 0x00000009UL /**< Mode UNIT32 for LDMA_CH_CTRL */ #define _LDMA_CH_CTRL_BLOCKSIZE_UNIT64 0x0000000AUL /**< Mode UNIT64 for LDMA_CH_CTRL */ #define _LDMA_CH_CTRL_BLOCKSIZE_UNIT128 0x0000000BUL /**< Mode UNIT128 for LDMA_CH_CTRL */ #define _LDMA_CH_CTRL_BLOCKSIZE_UNIT256 0x0000000CUL /**< Mode UNIT256 for LDMA_CH_CTRL */ #define _LDMA_CH_CTRL_BLOCKSIZE_UNIT512 0x0000000DUL /**< Mode UNIT512 for LDMA_CH_CTRL */ #define _LDMA_CH_CTRL_BLOCKSIZE_UNIT1024 0x0000000EUL /**< Mode UNIT1024 for LDMA_CH_CTRL */ #define _LDMA_CH_CTRL_BLOCKSIZE_ALL 0x0000000FUL /**< Mode ALL for LDMA_CH_CTRL */ #define LDMA_CH_CTRL_BLOCKSIZE_DEFAULT (_LDMA_CH_CTRL_BLOCKSIZE_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ #define LDMA_CH_CTRL_BLOCKSIZE_UNIT1 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT1 << 16) /**< Shifted mode UNIT1 for LDMA_CH_CTRL */ #define LDMA_CH_CTRL_BLOCKSIZE_UNIT2 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT2 << 16) /**< Shifted mode UNIT2 for LDMA_CH_CTRL */ #define LDMA_CH_CTRL_BLOCKSIZE_UNIT3 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT3 << 16) /**< Shifted mode UNIT3 for LDMA_CH_CTRL */ #define LDMA_CH_CTRL_BLOCKSIZE_UNIT4 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT4 << 16) /**< Shifted mode UNIT4 for LDMA_CH_CTRL */ #define LDMA_CH_CTRL_BLOCKSIZE_UNIT6 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT6 << 16) /**< Shifted mode UNIT6 for LDMA_CH_CTRL */ #define LDMA_CH_CTRL_BLOCKSIZE_UNIT8 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT8 << 16) /**< Shifted mode UNIT8 for LDMA_CH_CTRL */ #define LDMA_CH_CTRL_BLOCKSIZE_UNIT16 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT16 << 16) /**< Shifted mode UNIT16 for LDMA_CH_CTRL */ #define LDMA_CH_CTRL_BLOCKSIZE_UNIT32 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT32 << 16) /**< Shifted mode UNIT32 for LDMA_CH_CTRL */ #define LDMA_CH_CTRL_BLOCKSIZE_UNIT64 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT64 << 16) /**< Shifted mode UNIT64 for LDMA_CH_CTRL */ #define LDMA_CH_CTRL_BLOCKSIZE_UNIT128 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT128 << 16) /**< Shifted mode UNIT128 for LDMA_CH_CTRL */ #define LDMA_CH_CTRL_BLOCKSIZE_UNIT256 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT256 << 16) /**< Shifted mode UNIT256 for LDMA_CH_CTRL */ #define LDMA_CH_CTRL_BLOCKSIZE_UNIT512 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT512 << 16) /**< Shifted mode UNIT512 for LDMA_CH_CTRL */ #define LDMA_CH_CTRL_BLOCKSIZE_UNIT1024 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT1024 << 16) /**< Shifted mode UNIT1024 for LDMA_CH_CTRL */ #define LDMA_CH_CTRL_BLOCKSIZE_ALL (_LDMA_CH_CTRL_BLOCKSIZE_ALL << 16) /**< Shifted mode ALL for LDMA_CH_CTRL */ #define LDMA_CH_CTRL_DONEIFSEN (0x1UL << 20) /**< DMA Operation Done Interrupt Flag Set Enable */ #define _LDMA_CH_CTRL_DONEIFSEN_SHIFT 20 /**< Shift value for LDMA_DONEIFSEN */ #define _LDMA_CH_CTRL_DONEIFSEN_MASK 0x100000UL /**< Bit mask for LDMA_DONEIFSEN */ #define _LDMA_CH_CTRL_DONEIFSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ #define LDMA_CH_CTRL_DONEIFSEN_DEFAULT (_LDMA_CH_CTRL_DONEIFSEN_DEFAULT << 20) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ #define LDMA_CH_CTRL_REQMODE (0x1UL << 21) /**< DMA Request Transfer Mode Select */ #define _LDMA_CH_CTRL_REQMODE_SHIFT 21 /**< Shift value for LDMA_REQMODE */ #define _LDMA_CH_CTRL_REQMODE_MASK 0x200000UL /**< Bit mask for LDMA_REQMODE */ #define _LDMA_CH_CTRL_REQMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ #define _LDMA_CH_CTRL_REQMODE_BLOCK 0x00000000UL /**< Mode BLOCK for LDMA_CH_CTRL */ #define _LDMA_CH_CTRL_REQMODE_ALL 0x00000001UL /**< Mode ALL for LDMA_CH_CTRL */ #define LDMA_CH_CTRL_REQMODE_DEFAULT (_LDMA_CH_CTRL_REQMODE_DEFAULT << 21) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ #define LDMA_CH_CTRL_REQMODE_BLOCK (_LDMA_CH_CTRL_REQMODE_BLOCK << 21) /**< Shifted mode BLOCK for LDMA_CH_CTRL */ #define LDMA_CH_CTRL_REQMODE_ALL (_LDMA_CH_CTRL_REQMODE_ALL << 21) /**< Shifted mode ALL for LDMA_CH_CTRL */ #define LDMA_CH_CTRL_DECLOOPCNT (0x1UL << 22) /**< Decrement Loop Count */ #define _LDMA_CH_CTRL_DECLOOPCNT_SHIFT 22 /**< Shift value for LDMA_DECLOOPCNT */ #define _LDMA_CH_CTRL_DECLOOPCNT_MASK 0x400000UL /**< Bit mask for LDMA_DECLOOPCNT */ #define _LDMA_CH_CTRL_DECLOOPCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ #define LDMA_CH_CTRL_DECLOOPCNT_DEFAULT (_LDMA_CH_CTRL_DECLOOPCNT_DEFAULT << 22) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ #define LDMA_CH_CTRL_IGNORESREQ (0x1UL << 23) /**< Ignore Sreq */ #define _LDMA_CH_CTRL_IGNORESREQ_SHIFT 23 /**< Shift value for LDMA_IGNORESREQ */ #define _LDMA_CH_CTRL_IGNORESREQ_MASK 0x800000UL /**< Bit mask for LDMA_IGNORESREQ */ #define _LDMA_CH_CTRL_IGNORESREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ #define LDMA_CH_CTRL_IGNORESREQ_DEFAULT (_LDMA_CH_CTRL_IGNORESREQ_DEFAULT << 23) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ #define _LDMA_CH_CTRL_SRCINC_SHIFT 24 /**< Shift value for LDMA_SRCINC */ #define _LDMA_CH_CTRL_SRCINC_MASK 0x3000000UL /**< Bit mask for LDMA_SRCINC */ #define _LDMA_CH_CTRL_SRCINC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ #define _LDMA_CH_CTRL_SRCINC_ONE 0x00000000UL /**< Mode ONE for LDMA_CH_CTRL */ #define _LDMA_CH_CTRL_SRCINC_TWO 0x00000001UL /**< Mode TWO for LDMA_CH_CTRL */ #define _LDMA_CH_CTRL_SRCINC_FOUR 0x00000002UL /**< Mode FOUR for LDMA_CH_CTRL */ #define _LDMA_CH_CTRL_SRCINC_NONE 0x00000003UL /**< Mode NONE for LDMA_CH_CTRL */ #define LDMA_CH_CTRL_SRCINC_DEFAULT (_LDMA_CH_CTRL_SRCINC_DEFAULT << 24) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ #define LDMA_CH_CTRL_SRCINC_ONE (_LDMA_CH_CTRL_SRCINC_ONE << 24) /**< Shifted mode ONE for LDMA_CH_CTRL */ #define LDMA_CH_CTRL_SRCINC_TWO (_LDMA_CH_CTRL_SRCINC_TWO << 24) /**< Shifted mode TWO for LDMA_CH_CTRL */ #define LDMA_CH_CTRL_SRCINC_FOUR (_LDMA_CH_CTRL_SRCINC_FOUR << 24) /**< Shifted mode FOUR for LDMA_CH_CTRL */ #define LDMA_CH_CTRL_SRCINC_NONE (_LDMA_CH_CTRL_SRCINC_NONE << 24) /**< Shifted mode NONE for LDMA_CH_CTRL */ #define _LDMA_CH_CTRL_SIZE_SHIFT 26 /**< Shift value for LDMA_SIZE */ #define _LDMA_CH_CTRL_SIZE_MASK 0xC000000UL /**< Bit mask for LDMA_SIZE */ #define _LDMA_CH_CTRL_SIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ #define _LDMA_CH_CTRL_SIZE_BYTE 0x00000000UL /**< Mode BYTE for LDMA_CH_CTRL */ #define _LDMA_CH_CTRL_SIZE_HALFWORD 0x00000001UL /**< Mode HALFWORD for LDMA_CH_CTRL */ #define _LDMA_CH_CTRL_SIZE_WORD 0x00000002UL /**< Mode WORD for LDMA_CH_CTRL */ #define LDMA_CH_CTRL_SIZE_DEFAULT (_LDMA_CH_CTRL_SIZE_DEFAULT << 26) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ #define LDMA_CH_CTRL_SIZE_BYTE (_LDMA_CH_CTRL_SIZE_BYTE << 26) /**< Shifted mode BYTE for LDMA_CH_CTRL */ #define LDMA_CH_CTRL_SIZE_HALFWORD (_LDMA_CH_CTRL_SIZE_HALFWORD << 26) /**< Shifted mode HALFWORD for LDMA_CH_CTRL */ #define LDMA_CH_CTRL_SIZE_WORD (_LDMA_CH_CTRL_SIZE_WORD << 26) /**< Shifted mode WORD for LDMA_CH_CTRL */ #define _LDMA_CH_CTRL_DSTINC_SHIFT 28 /**< Shift value for LDMA_DSTINC */ #define _LDMA_CH_CTRL_DSTINC_MASK 0x30000000UL /**< Bit mask for LDMA_DSTINC */ #define _LDMA_CH_CTRL_DSTINC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ #define _LDMA_CH_CTRL_DSTINC_ONE 0x00000000UL /**< Mode ONE for LDMA_CH_CTRL */ #define _LDMA_CH_CTRL_DSTINC_TWO 0x00000001UL /**< Mode TWO for LDMA_CH_CTRL */ #define _LDMA_CH_CTRL_DSTINC_FOUR 0x00000002UL /**< Mode FOUR for LDMA_CH_CTRL */ #define _LDMA_CH_CTRL_DSTINC_NONE 0x00000003UL /**< Mode NONE for LDMA_CH_CTRL */ #define LDMA_CH_CTRL_DSTINC_DEFAULT (_LDMA_CH_CTRL_DSTINC_DEFAULT << 28) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ #define LDMA_CH_CTRL_DSTINC_ONE (_LDMA_CH_CTRL_DSTINC_ONE << 28) /**< Shifted mode ONE for LDMA_CH_CTRL */ #define LDMA_CH_CTRL_DSTINC_TWO (_LDMA_CH_CTRL_DSTINC_TWO << 28) /**< Shifted mode TWO for LDMA_CH_CTRL */ #define LDMA_CH_CTRL_DSTINC_FOUR (_LDMA_CH_CTRL_DSTINC_FOUR << 28) /**< Shifted mode FOUR for LDMA_CH_CTRL */ #define LDMA_CH_CTRL_DSTINC_NONE (_LDMA_CH_CTRL_DSTINC_NONE << 28) /**< Shifted mode NONE for LDMA_CH_CTRL */ #define LDMA_CH_CTRL_SRCMODE (0x1UL << 30) /**< Source Addressing Mode */ #define _LDMA_CH_CTRL_SRCMODE_SHIFT 30 /**< Shift value for LDMA_SRCMODE */ #define _LDMA_CH_CTRL_SRCMODE_MASK 0x40000000UL /**< Bit mask for LDMA_SRCMODE */ #define _LDMA_CH_CTRL_SRCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ #define _LDMA_CH_CTRL_SRCMODE_ABSOLUTE 0x00000000UL /**< Mode ABSOLUTE for LDMA_CH_CTRL */ #define _LDMA_CH_CTRL_SRCMODE_RELATIVE 0x00000001UL /**< Mode RELATIVE for LDMA_CH_CTRL */ #define LDMA_CH_CTRL_SRCMODE_DEFAULT (_LDMA_CH_CTRL_SRCMODE_DEFAULT << 30) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ #define LDMA_CH_CTRL_SRCMODE_ABSOLUTE (_LDMA_CH_CTRL_SRCMODE_ABSOLUTE << 30) /**< Shifted mode ABSOLUTE for LDMA_CH_CTRL */ #define LDMA_CH_CTRL_SRCMODE_RELATIVE (_LDMA_CH_CTRL_SRCMODE_RELATIVE << 30) /**< Shifted mode RELATIVE for LDMA_CH_CTRL */ #define LDMA_CH_CTRL_DSTMODE (0x1UL << 31) /**< Destination Addressing Mode */ #define _LDMA_CH_CTRL_DSTMODE_SHIFT 31 /**< Shift value for LDMA_DSTMODE */ #define _LDMA_CH_CTRL_DSTMODE_MASK 0x80000000UL /**< Bit mask for LDMA_DSTMODE */ #define _LDMA_CH_CTRL_DSTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ #define _LDMA_CH_CTRL_DSTMODE_ABSOLUTE 0x00000000UL /**< Mode ABSOLUTE for LDMA_CH_CTRL */ #define _LDMA_CH_CTRL_DSTMODE_RELATIVE 0x00000001UL /**< Mode RELATIVE for LDMA_CH_CTRL */ #define LDMA_CH_CTRL_DSTMODE_DEFAULT (_LDMA_CH_CTRL_DSTMODE_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ #define LDMA_CH_CTRL_DSTMODE_ABSOLUTE (_LDMA_CH_CTRL_DSTMODE_ABSOLUTE << 31) /**< Shifted mode ABSOLUTE for LDMA_CH_CTRL */ #define LDMA_CH_CTRL_DSTMODE_RELATIVE (_LDMA_CH_CTRL_DSTMODE_RELATIVE << 31) /**< Shifted mode RELATIVE for LDMA_CH_CTRL */ /* Bit fields for LDMA CH_SRC */ #define _LDMA_CH_SRC_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_SRC */ #define _LDMA_CH_SRC_MASK 0xFFFFFFFFUL /**< Mask for LDMA_CH_SRC */ #define _LDMA_CH_SRC_SRCADDR_SHIFT 0 /**< Shift value for LDMA_SRCADDR */ #define _LDMA_CH_SRC_SRCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for LDMA_SRCADDR */ #define _LDMA_CH_SRC_SRCADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_SRC */ #define LDMA_CH_SRC_SRCADDR_DEFAULT (_LDMA_CH_SRC_SRCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_SRC */ /* Bit fields for LDMA CH_DST */ #define _LDMA_CH_DST_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_DST */ #define _LDMA_CH_DST_MASK 0xFFFFFFFFUL /**< Mask for LDMA_CH_DST */ #define _LDMA_CH_DST_DSTADDR_SHIFT 0 /**< Shift value for LDMA_DSTADDR */ #define _LDMA_CH_DST_DSTADDR_MASK 0xFFFFFFFFUL /**< Bit mask for LDMA_DSTADDR */ #define _LDMA_CH_DST_DSTADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_DST */ #define LDMA_CH_DST_DSTADDR_DEFAULT (_LDMA_CH_DST_DSTADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_DST */ /* Bit fields for LDMA CH_LINK */ #define _LDMA_CH_LINK_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_LINK */ #define _LDMA_CH_LINK_MASK 0xFFFFFFFFUL /**< Mask for LDMA_CH_LINK */ #define LDMA_CH_LINK_LINKMODE (0x1UL << 0) /**< Link Structure Addressing Mode */ #define _LDMA_CH_LINK_LINKMODE_SHIFT 0 /**< Shift value for LDMA_LINKMODE */ #define _LDMA_CH_LINK_LINKMODE_MASK 0x1UL /**< Bit mask for LDMA_LINKMODE */ #define _LDMA_CH_LINK_LINKMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_LINK */ #define _LDMA_CH_LINK_LINKMODE_ABSOLUTE 0x00000000UL /**< Mode ABSOLUTE for LDMA_CH_LINK */ #define _LDMA_CH_LINK_LINKMODE_RELATIVE 0x00000001UL /**< Mode RELATIVE for LDMA_CH_LINK */ #define LDMA_CH_LINK_LINKMODE_DEFAULT (_LDMA_CH_LINK_LINKMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_LINK */ #define LDMA_CH_LINK_LINKMODE_ABSOLUTE (_LDMA_CH_LINK_LINKMODE_ABSOLUTE << 0) /**< Shifted mode ABSOLUTE for LDMA_CH_LINK */ #define LDMA_CH_LINK_LINKMODE_RELATIVE (_LDMA_CH_LINK_LINKMODE_RELATIVE << 0) /**< Shifted mode RELATIVE for LDMA_CH_LINK */ #define LDMA_CH_LINK_LINK (0x1UL << 1) /**< Link Next Structure */ #define _LDMA_CH_LINK_LINK_SHIFT 1 /**< Shift value for LDMA_LINK */ #define _LDMA_CH_LINK_LINK_MASK 0x2UL /**< Bit mask for LDMA_LINK */ #define _LDMA_CH_LINK_LINK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_LINK */ #define LDMA_CH_LINK_LINK_DEFAULT (_LDMA_CH_LINK_LINK_DEFAULT << 1) /**< Shifted mode DEFAULT for LDMA_CH_LINK */ #define _LDMA_CH_LINK_LINKADDR_SHIFT 2 /**< Shift value for LDMA_LINKADDR */ #define _LDMA_CH_LINK_LINKADDR_MASK 0xFFFFFFFCUL /**< Bit mask for LDMA_LINKADDR */ #define _LDMA_CH_LINK_LINKADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_LINK */ #define LDMA_CH_LINK_LINKADDR_DEFAULT (_LDMA_CH_LINK_LINKADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for LDMA_CH_LINK */ /** @} */ /** @} End of group EFR32MG12P_LDMA */ /** @} End of group Parts */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_ldma_ch.h.
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/***************************************************************************//** * @file * @brief EFR32MG12P_LDMA_CH register and bit field definitions * @version 5.7.0 ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * SPDX-License-Identifier: Zlib * * The licensor of this software is Silicon Laboratories Inc. * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be * appreciated but is not required. * 2. Altered source versions must be plainly marked as such, and must not be * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * ******************************************************************************/ #if defined(__ICCARM__) #pragma system_include /* Treat file as system include file. */ #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang system_header /* Treat file as system include file. */ #endif /***************************************************************************//** * @addtogroup Parts * @{ ******************************************************************************/ /***************************************************************************//** * @brief LDMA_CH LDMA CH Register * @ingroup EFR32MG12P_LDMA ******************************************************************************/ typedef struct { __IOM uint32_t REQSEL; /**< Channel Peripheral Request Select Register */ __IOM uint32_t CFG; /**< Channel Configuration Register */ __IOM uint32_t LOOP; /**< Channel Loop Counter Register */ __IOM uint32_t CTRL; /**< Channel Descriptor Control Word Register */ __IOM uint32_t SRC; /**< Channel Descriptor Source Data Address Register */ __IOM uint32_t DST; /**< Channel Descriptor Destination Data Address Register */ __IOM uint32_t LINK; /**< Channel Descriptor Link Structure Address Register */ uint32_t RESERVED0[5U]; /**< Reserved future */ } LDMA_CH_TypeDef; /** @} End of group Parts */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_lesense.h.
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/***************************************************************************//** * @file * @brief EFR32MG12P_LESENSE register and bit field definitions * @version 5.7.0 ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * SPDX-License-Identifier: Zlib * * The licensor of this software is Silicon Laboratories Inc. * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be * appreciated but is not required. * 2. Altered source versions must be plainly marked as such, and must not be * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * ******************************************************************************/ #if defined(__ICCARM__) #pragma system_include /* Treat file as system include file. */ #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang system_header /* Treat file as system include file. */ #endif /***************************************************************************//** * @addtogroup Parts * @{ ******************************************************************************/ /***************************************************************************//** * @defgroup EFR32MG12P_LESENSE LESENSE * @{ * @brief EFR32MG12P_LESENSE Register Declaration ******************************************************************************/ /** LESENSE Register Declaration */ typedef struct { __IOM uint32_t CTRL; /**< Control Register */ __IOM uint32_t TIMCTRL; /**< Timing Control Register */ __IOM uint32_t PERCTRL; /**< Peripheral Control Register */ __IOM uint32_t DECCTRL; /**< Decoder Control Register */ __IOM uint32_t BIASCTRL; /**< Bias Control Register */ __IOM uint32_t EVALCTRL; /**< LESENSE Evaluation Control */ __IOM uint32_t PRSCTRL; /**< PRS Control Register */ __IOM uint32_t CMD; /**< Command Register */ __IOM uint32_t CHEN; /**< Channel Enable Register */ __IOM uint32_t SCANRES; /**< Scan Result Register */ __IM uint32_t STATUS; /**< Status Register */ __IM uint32_t PTR; /**< Result Buffer Pointers */ __IM uint32_t BUFDATA; /**< Result Buffer Data Register */ __IM uint32_t CURCH; /**< Current Channel Index */ __IOM uint32_t DECSTATE; /**< Current Decoder State */ __IOM uint32_t SENSORSTATE; /**< Decoder Input Register */ __IOM uint32_t IDLECONF; /**< GPIO Idle Phase Configuration */ __IOM uint32_t ALTEXCONF; /**< Alternative Excite Pin Configuration */ uint32_t RESERVED0[2U]; /**< Reserved for future use **/ __IM uint32_t IF; /**< Interrupt Flag Register */ __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ __IOM uint32_t IEN; /**< Interrupt Enable Register */ __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ __IOM uint32_t ROUTEPEN; /**< I/O Routing Register */ uint32_t RESERVED1[38U]; /**< Reserved registers */ LESENSE_ST_TypeDef ST[32U]; /**< Decoding states */ LESENSE_BUF_TypeDef BUF[16U]; /**< Scanresult */ LESENSE_CH_TypeDef CH[16U]; /**< Scanconfig */ } LESENSE_TypeDef; /** @} */ /***************************************************************************//** * @addtogroup EFR32MG12P_LESENSE * @{ * @defgroup EFR32MG12P_LESENSE_BitFields LESENSE Bit Fields * @{ ******************************************************************************/ /* Bit fields for LESENSE CTRL */ #define _LESENSE_CTRL_RESETVALUE 0x00000000UL /**< Default value for LESENSE_CTRL */ #define _LESENSE_CTRL_MASK 0x007B29BFUL /**< Mask for LESENSE_CTRL */ #define _LESENSE_CTRL_SCANMODE_SHIFT 0 /**< Shift value for LESENSE_SCANMODE */ #define _LESENSE_CTRL_SCANMODE_MASK 0x3UL /**< Bit mask for LESENSE_SCANMODE */ #define _LESENSE_CTRL_SCANMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CTRL */ #define _LESENSE_CTRL_SCANMODE_PERIODIC 0x00000000UL /**< Mode PERIODIC for LESENSE_CTRL */ #define _LESENSE_CTRL_SCANMODE_ONESHOT 0x00000001UL /**< Mode ONESHOT for LESENSE_CTRL */ #define _LESENSE_CTRL_SCANMODE_PRS 0x00000002UL /**< Mode PRS for LESENSE_CTRL */ #define LESENSE_CTRL_SCANMODE_DEFAULT (_LESENSE_CTRL_SCANMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_CTRL */ #define LESENSE_CTRL_SCANMODE_PERIODIC (_LESENSE_CTRL_SCANMODE_PERIODIC << 0) /**< Shifted mode PERIODIC for LESENSE_CTRL */ #define LESENSE_CTRL_SCANMODE_ONESHOT (_LESENSE_CTRL_SCANMODE_ONESHOT << 0) /**< Shifted mode ONESHOT for LESENSE_CTRL */ #define LESENSE_CTRL_SCANMODE_PRS (_LESENSE_CTRL_SCANMODE_PRS << 0) /**< Shifted mode PRS for LESENSE_CTRL */ #define _LESENSE_CTRL_PRSSEL_SHIFT 2 /**< Shift value for LESENSE_PRSSEL */ #define _LESENSE_CTRL_PRSSEL_MASK 0x3CUL /**< Bit mask for LESENSE_PRSSEL */ #define _LESENSE_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CTRL */ #define _LESENSE_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for LESENSE_CTRL */ #define _LESENSE_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for LESENSE_CTRL */ #define _LESENSE_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for LESENSE_CTRL */ #define _LESENSE_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for LESENSE_CTRL */ #define _LESENSE_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for LESENSE_CTRL */ #define _LESENSE_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for LESENSE_CTRL */ #define _LESENSE_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for LESENSE_CTRL */ #define _LESENSE_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for LESENSE_CTRL */ #define _LESENSE_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for LESENSE_CTRL */ #define _LESENSE_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for LESENSE_CTRL */ #define _LESENSE_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for LESENSE_CTRL */ #define _LESENSE_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for LESENSE_CTRL */ #define LESENSE_CTRL_PRSSEL_DEFAULT (_LESENSE_CTRL_PRSSEL_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_CTRL */ #define LESENSE_CTRL_PRSSEL_PRSCH0 (_LESENSE_CTRL_PRSSEL_PRSCH0 << 2) /**< Shifted mode PRSCH0 for LESENSE_CTRL */ #define LESENSE_CTRL_PRSSEL_PRSCH1 (_LESENSE_CTRL_PRSSEL_PRSCH1 << 2) /**< Shifted mode PRSCH1 for LESENSE_CTRL */ #define LESENSE_CTRL_PRSSEL_PRSCH2 (_LESENSE_CTRL_PRSSEL_PRSCH2 << 2) /**< Shifted mode PRSCH2 for LESENSE_CTRL */ #define LESENSE_CTRL_PRSSEL_PRSCH3 (_LESENSE_CTRL_PRSSEL_PRSCH3 << 2) /**< Shifted mode PRSCH3 for LESENSE_CTRL */ #define LESENSE_CTRL_PRSSEL_PRSCH4 (_LESENSE_CTRL_PRSSEL_PRSCH4 << 2) /**< Shifted mode PRSCH4 for LESENSE_CTRL */ #define LESENSE_CTRL_PRSSEL_PRSCH5 (_LESENSE_CTRL_PRSSEL_PRSCH5 << 2) /**< Shifted mode PRSCH5 for LESENSE_CTRL */ #define LESENSE_CTRL_PRSSEL_PRSCH6 (_LESENSE_CTRL_PRSSEL_PRSCH6 << 2) /**< Shifted mode PRSCH6 for LESENSE_CTRL */ #define LESENSE_CTRL_PRSSEL_PRSCH7 (_LESENSE_CTRL_PRSSEL_PRSCH7 << 2) /**< Shifted mode PRSCH7 for LESENSE_CTRL */ #define LESENSE_CTRL_PRSSEL_PRSCH8 (_LESENSE_CTRL_PRSSEL_PRSCH8 << 2) /**< Shifted mode PRSCH8 for LESENSE_CTRL */ #define LESENSE_CTRL_PRSSEL_PRSCH9 (_LESENSE_CTRL_PRSSEL_PRSCH9 << 2) /**< Shifted mode PRSCH9 for LESENSE_CTRL */ #define LESENSE_CTRL_PRSSEL_PRSCH10 (_LESENSE_CTRL_PRSSEL_PRSCH10 << 2) /**< Shifted mode PRSCH10 for LESENSE_CTRL */ #define LESENSE_CTRL_PRSSEL_PRSCH11 (_LESENSE_CTRL_PRSSEL_PRSCH11 << 2) /**< Shifted mode PRSCH11 for LESENSE_CTRL */ #define _LESENSE_CTRL_SCANCONF_SHIFT 7 /**< Shift value for LESENSE_SCANCONF */ #define _LESENSE_CTRL_SCANCONF_MASK 0x180UL /**< Bit mask for LESENSE_SCANCONF */ #define _LESENSE_CTRL_SCANCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CTRL */ #define _LESENSE_CTRL_SCANCONF_DIRMAP 0x00000000UL /**< Mode DIRMAP for LESENSE_CTRL */ #define _LESENSE_CTRL_SCANCONF_INVMAP 0x00000001UL /**< Mode INVMAP for LESENSE_CTRL */ #define _LESENSE_CTRL_SCANCONF_TOGGLE 0x00000002UL /**< Mode TOGGLE for LESENSE_CTRL */ #define _LESENSE_CTRL_SCANCONF_DECDEF 0x00000003UL /**< Mode DECDEF for LESENSE_CTRL */ #define LESENSE_CTRL_SCANCONF_DEFAULT (_LESENSE_CTRL_SCANCONF_DEFAULT << 7) /**< Shifted mode DEFAULT for LESENSE_CTRL */ #define LESENSE_CTRL_SCANCONF_DIRMAP (_LESENSE_CTRL_SCANCONF_DIRMAP << 7) /**< Shifted mode DIRMAP for LESENSE_CTRL */ #define LESENSE_CTRL_SCANCONF_INVMAP (_LESENSE_CTRL_SCANCONF_INVMAP << 7) /**< Shifted mode INVMAP for LESENSE_CTRL */ #define LESENSE_CTRL_SCANCONF_TOGGLE (_LESENSE_CTRL_SCANCONF_TOGGLE << 7) /**< Shifted mode TOGGLE for LESENSE_CTRL */ #define LESENSE_CTRL_SCANCONF_DECDEF (_LESENSE_CTRL_SCANCONF_DECDEF << 7) /**< Shifted mode DECDEF for LESENSE_CTRL */ #define LESENSE_CTRL_ALTEXMAP (0x1UL << 11) /**< Alternative Excitation Map */ #define _LESENSE_CTRL_ALTEXMAP_SHIFT 11 /**< Shift value for LESENSE_ALTEXMAP */ #define _LESENSE_CTRL_ALTEXMAP_MASK 0x800UL /**< Bit mask for LESENSE_ALTEXMAP */ #define _LESENSE_CTRL_ALTEXMAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CTRL */ #define _LESENSE_CTRL_ALTEXMAP_ALTEX 0x00000000UL /**< Mode ALTEX for LESENSE_CTRL */ #define _LESENSE_CTRL_ALTEXMAP_CH 0x00000001UL /**< Mode CH for LESENSE_CTRL */ #define LESENSE_CTRL_ALTEXMAP_DEFAULT (_LESENSE_CTRL_ALTEXMAP_DEFAULT << 11) /**< Shifted mode DEFAULT for LESENSE_CTRL */ #define LESENSE_CTRL_ALTEXMAP_ALTEX (_LESENSE_CTRL_ALTEXMAP_ALTEX << 11) /**< Shifted mode ALTEX for LESENSE_CTRL */ #define LESENSE_CTRL_ALTEXMAP_CH (_LESENSE_CTRL_ALTEXMAP_CH << 11) /**< Shifted mode CH for LESENSE_CTRL */ #define LESENSE_CTRL_DUALSAMPLE (0x1UL << 13) /**< Enable Dual Sample Mode */ #define _LESENSE_CTRL_DUALSAMPLE_SHIFT 13 /**< Shift value for LESENSE_DUALSAMPLE */ #define _LESENSE_CTRL_DUALSAMPLE_MASK 0x2000UL /**< Bit mask for LESENSE_DUALSAMPLE */ #define _LESENSE_CTRL_DUALSAMPLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CTRL */ #define LESENSE_CTRL_DUALSAMPLE_DEFAULT (_LESENSE_CTRL_DUALSAMPLE_DEFAULT << 13) /**< Shifted mode DEFAULT for LESENSE_CTRL */ #define LESENSE_CTRL_BUFOW (0x1UL << 16) /**< Result Buffer Overwrite */ #define _LESENSE_CTRL_BUFOW_SHIFT 16 /**< Shift value for LESENSE_BUFOW */ #define _LESENSE_CTRL_BUFOW_MASK 0x10000UL /**< Bit mask for LESENSE_BUFOW */ #define _LESENSE_CTRL_BUFOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CTRL */ #define LESENSE_CTRL_BUFOW_DEFAULT (_LESENSE_CTRL_BUFOW_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_CTRL */ #define LESENSE_CTRL_STRSCANRES (0x1UL << 17) /**< Enable Storing of SCANRES */ #define _LESENSE_CTRL_STRSCANRES_SHIFT 17 /**< Shift value for LESENSE_STRSCANRES */ #define _LESENSE_CTRL_STRSCANRES_MASK 0x20000UL /**< Bit mask for LESENSE_STRSCANRES */ #define _LESENSE_CTRL_STRSCANRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CTRL */ #define LESENSE_CTRL_STRSCANRES_DEFAULT (_LESENSE_CTRL_STRSCANRES_DEFAULT << 17) /**< Shifted mode DEFAULT for LESENSE_CTRL */ #define LESENSE_CTRL_BUFIDL (0x1UL << 19) /**< Result Buffer Interrupt and DMA Trigger Level */ #define _LESENSE_CTRL_BUFIDL_SHIFT 19 /**< Shift value for LESENSE_BUFIDL */ #define _LESENSE_CTRL_BUFIDL_MASK 0x80000UL /**< Bit mask for LESENSE_BUFIDL */ #define _LESENSE_CTRL_BUFIDL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CTRL */ #define _LESENSE_CTRL_BUFIDL_HALFFULL 0x00000000UL /**< Mode HALFFULL for LESENSE_CTRL */ #define _LESENSE_CTRL_BUFIDL_FULL 0x00000001UL /**< Mode FULL for LESENSE_CTRL */ #define LESENSE_CTRL_BUFIDL_DEFAULT (_LESENSE_CTRL_BUFIDL_DEFAULT << 19) /**< Shifted mode DEFAULT for LESENSE_CTRL */ #define LESENSE_CTRL_BUFIDL_HALFFULL (_LESENSE_CTRL_BUFIDL_HALFFULL << 19) /**< Shifted mode HALFFULL for LESENSE_CTRL */ #define LESENSE_CTRL_BUFIDL_FULL (_LESENSE_CTRL_BUFIDL_FULL << 19) /**< Shifted mode FULL for LESENSE_CTRL */ #define _LESENSE_CTRL_DMAWU_SHIFT 20 /**< Shift value for LESENSE_DMAWU */ #define _LESENSE_CTRL_DMAWU_MASK 0x300000UL /**< Bit mask for LESENSE_DMAWU */ #define _LESENSE_CTRL_DMAWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CTRL */ #define _LESENSE_CTRL_DMAWU_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_CTRL */ #define _LESENSE_CTRL_DMAWU_BUFDATAV 0x00000001UL /**< Mode BUFDATAV for LESENSE_CTRL */ #define _LESENSE_CTRL_DMAWU_BUFLEVEL 0x00000002UL /**< Mode BUFLEVEL for LESENSE_CTRL */ #define LESENSE_CTRL_DMAWU_DEFAULT (_LESENSE_CTRL_DMAWU_DEFAULT << 20) /**< Shifted mode DEFAULT for LESENSE_CTRL */ #define LESENSE_CTRL_DMAWU_DISABLE (_LESENSE_CTRL_DMAWU_DISABLE << 20) /**< Shifted mode DISABLE for LESENSE_CTRL */ #define LESENSE_CTRL_DMAWU_BUFDATAV (_LESENSE_CTRL_DMAWU_BUFDATAV << 20) /**< Shifted mode BUFDATAV for LESENSE_CTRL */ #define LESENSE_CTRL_DMAWU_BUFLEVEL (_LESENSE_CTRL_DMAWU_BUFLEVEL << 20) /**< Shifted mode BUFLEVEL for LESENSE_CTRL */ #define LESENSE_CTRL_DEBUGRUN (0x1UL << 22) /**< Debug Mode Run Enable */ #define _LESENSE_CTRL_DEBUGRUN_SHIFT 22 /**< Shift value for LESENSE_DEBUGRUN */ #define _LESENSE_CTRL_DEBUGRUN_MASK 0x400000UL /**< Bit mask for LESENSE_DEBUGRUN */ #define _LESENSE_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CTRL */ #define LESENSE_CTRL_DEBUGRUN_DEFAULT (_LESENSE_CTRL_DEBUGRUN_DEFAULT << 22) /**< Shifted mode DEFAULT for LESENSE_CTRL */ /* Bit fields for LESENSE TIMCTRL */ #define _LESENSE_TIMCTRL_RESETVALUE 0x00000000UL /**< Default value for LESENSE_TIMCTRL */ #define _LESENSE_TIMCTRL_MASK 0x10CFF773UL /**< Mask for LESENSE_TIMCTRL */ #define _LESENSE_TIMCTRL_AUXPRESC_SHIFT 0 /**< Shift value for LESENSE_AUXPRESC */ #define _LESENSE_TIMCTRL_AUXPRESC_MASK 0x3UL /**< Bit mask for LESENSE_AUXPRESC */ #define _LESENSE_TIMCTRL_AUXPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_TIMCTRL */ #define _LESENSE_TIMCTRL_AUXPRESC_DIV1 0x00000000UL /**< Mode DIV1 for LESENSE_TIMCTRL */ #define _LESENSE_TIMCTRL_AUXPRESC_DIV2 0x00000001UL /**< Mode DIV2 for LESENSE_TIMCTRL */ #define _LESENSE_TIMCTRL_AUXPRESC_DIV4 0x00000002UL /**< Mode DIV4 for LESENSE_TIMCTRL */ #define _LESENSE_TIMCTRL_AUXPRESC_DIV8 0x00000003UL /**< Mode DIV8 for LESENSE_TIMCTRL */ #define LESENSE_TIMCTRL_AUXPRESC_DEFAULT (_LESENSE_TIMCTRL_AUXPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_TIMCTRL */ #define LESENSE_TIMCTRL_AUXPRESC_DIV1 (_LESENSE_TIMCTRL_AUXPRESC_DIV1 << 0) /**< Shifted mode DIV1 for LESENSE_TIMCTRL */ #define LESENSE_TIMCTRL_AUXPRESC_DIV2 (_LESENSE_TIMCTRL_AUXPRESC_DIV2 << 0) /**< Shifted mode DIV2 for LESENSE_TIMCTRL */ #define LESENSE_TIMCTRL_AUXPRESC_DIV4 (_LESENSE_TIMCTRL_AUXPRESC_DIV4 << 0) /**< Shifted mode DIV4 for LESENSE_TIMCTRL */ #define LESENSE_TIMCTRL_AUXPRESC_DIV8 (_LESENSE_TIMCTRL_AUXPRESC_DIV8 << 0) /**< Shifted mode DIV8 for LESENSE_TIMCTRL */ #define _LESENSE_TIMCTRL_LFPRESC_SHIFT 4 /**< Shift value for LESENSE_LFPRESC */ #define _LESENSE_TIMCTRL_LFPRESC_MASK 0x70UL /**< Bit mask for LESENSE_LFPRESC */ #define _LESENSE_TIMCTRL_LFPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_TIMCTRL */ #define _LESENSE_TIMCTRL_LFPRESC_DIV1 0x00000000UL /**< Mode DIV1 for LESENSE_TIMCTRL */ #define _LESENSE_TIMCTRL_LFPRESC_DIV2 0x00000001UL /**< Mode DIV2 for LESENSE_TIMCTRL */ #define _LESENSE_TIMCTRL_LFPRESC_DIV4 0x00000002UL /**< Mode DIV4 for LESENSE_TIMCTRL */ #define _LESENSE_TIMCTRL_LFPRESC_DIV8 0x00000003UL /**< Mode DIV8 for LESENSE_TIMCTRL */ #define _LESENSE_TIMCTRL_LFPRESC_DIV16 0x00000004UL /**< Mode DIV16 for LESENSE_TIMCTRL */ #define _LESENSE_TIMCTRL_LFPRESC_DIV32 0x00000005UL /**< Mode DIV32 for LESENSE_TIMCTRL */ #define _LESENSE_TIMCTRL_LFPRESC_DIV64 0x00000006UL /**< Mode DIV64 for LESENSE_TIMCTRL */ #define _LESENSE_TIMCTRL_LFPRESC_DIV128 0x00000007UL /**< Mode DIV128 for LESENSE_TIMCTRL */ #define LESENSE_TIMCTRL_LFPRESC_DEFAULT (_LESENSE_TIMCTRL_LFPRESC_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_TIMCTRL */ #define LESENSE_TIMCTRL_LFPRESC_DIV1 (_LESENSE_TIMCTRL_LFPRESC_DIV1 << 4) /**< Shifted mode DIV1 for LESENSE_TIMCTRL */ #define LESENSE_TIMCTRL_LFPRESC_DIV2 (_LESENSE_TIMCTRL_LFPRESC_DIV2 << 4) /**< Shifted mode DIV2 for LESENSE_TIMCTRL */ #define LESENSE_TIMCTRL_LFPRESC_DIV4 (_LESENSE_TIMCTRL_LFPRESC_DIV4 << 4) /**< Shifted mode DIV4 for LESENSE_TIMCTRL */ #define LESENSE_TIMCTRL_LFPRESC_DIV8 (_LESENSE_TIMCTRL_LFPRESC_DIV8 << 4) /**< Shifted mode DIV8 for LESENSE_TIMCTRL */ #define LESENSE_TIMCTRL_LFPRESC_DIV16 (_LESENSE_TIMCTRL_LFPRESC_DIV16 << 4) /**< Shifted mode DIV16 for LESENSE_TIMCTRL */ #define LESENSE_TIMCTRL_LFPRESC_DIV32 (_LESENSE_TIMCTRL_LFPRESC_DIV32 << 4) /**< Shifted mode DIV32 for LESENSE_TIMCTRL */ #define LESENSE_TIMCTRL_LFPRESC_DIV64 (_LESENSE_TIMCTRL_LFPRESC_DIV64 << 4) /**< Shifted mode DIV64 for LESENSE_TIMCTRL */ #define LESENSE_TIMCTRL_LFPRESC_DIV128 (_LESENSE_TIMCTRL_LFPRESC_DIV128 << 4) /**< Shifted mode DIV128 for LESENSE_TIMCTRL */ #define _LESENSE_TIMCTRL_PCPRESC_SHIFT 8 /**< Shift value for LESENSE_PCPRESC */ #define _LESENSE_TIMCTRL_PCPRESC_MASK 0x700UL /**< Bit mask for LESENSE_PCPRESC */ #define _LESENSE_TIMCTRL_PCPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_TIMCTRL */ #define _LESENSE_TIMCTRL_PCPRESC_DIV1 0x00000000UL /**< Mode DIV1 for LESENSE_TIMCTRL */ #define _LESENSE_TIMCTRL_PCPRESC_DIV2 0x00000001UL /**< Mode DIV2 for LESENSE_TIMCTRL */ #define _LESENSE_TIMCTRL_PCPRESC_DIV4 0x00000002UL /**< Mode DIV4 for LESENSE_TIMCTRL */ #define _LESENSE_TIMCTRL_PCPRESC_DIV8 0x00000003UL /**< Mode DIV8 for LESENSE_TIMCTRL */ #define _LESENSE_TIMCTRL_PCPRESC_DIV16 0x00000004UL /**< Mode DIV16 for LESENSE_TIMCTRL */ #define _LESENSE_TIMCTRL_PCPRESC_DIV32 0x00000005UL /**< Mode DIV32 for LESENSE_TIMCTRL */ #define _LESENSE_TIMCTRL_PCPRESC_DIV64 0x00000006UL /**< Mode DIV64 for LESENSE_TIMCTRL */ #define _LESENSE_TIMCTRL_PCPRESC_DIV128 0x00000007UL /**< Mode DIV128 for LESENSE_TIMCTRL */ #define LESENSE_TIMCTRL_PCPRESC_DEFAULT (_LESENSE_TIMCTRL_PCPRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_TIMCTRL */ #define LESENSE_TIMCTRL_PCPRESC_DIV1 (_LESENSE_TIMCTRL_PCPRESC_DIV1 << 8) /**< Shifted mode DIV1 for LESENSE_TIMCTRL */ #define LESENSE_TIMCTRL_PCPRESC_DIV2 (_LESENSE_TIMCTRL_PCPRESC_DIV2 << 8) /**< Shifted mode DIV2 for LESENSE_TIMCTRL */ #define LESENSE_TIMCTRL_PCPRESC_DIV4 (_LESENSE_TIMCTRL_PCPRESC_DIV4 << 8) /**< Shifted mode DIV4 for LESENSE_TIMCTRL */ #define LESENSE_TIMCTRL_PCPRESC_DIV8 (_LESENSE_TIMCTRL_PCPRESC_DIV8 << 8) /**< Shifted mode DIV8 for LESENSE_TIMCTRL */ #define LESENSE_TIMCTRL_PCPRESC_DIV16 (_LESENSE_TIMCTRL_PCPRESC_DIV16 << 8) /**< Shifted mode DIV16 for LESENSE_TIMCTRL */ #define LESENSE_TIMCTRL_PCPRESC_DIV32 (_LESENSE_TIMCTRL_PCPRESC_DIV32 << 8) /**< Shifted mode DIV32 for LESENSE_TIMCTRL */ #define LESENSE_TIMCTRL_PCPRESC_DIV64 (_LESENSE_TIMCTRL_PCPRESC_DIV64 << 8) /**< Shifted mode DIV64 for LESENSE_TIMCTRL */ #define LESENSE_TIMCTRL_PCPRESC_DIV128 (_LESENSE_TIMCTRL_PCPRESC_DIV128 << 8) /**< Shifted mode DIV128 for LESENSE_TIMCTRL */ #define _LESENSE_TIMCTRL_PCTOP_SHIFT 12 /**< Shift value for LESENSE_PCTOP */ #define _LESENSE_TIMCTRL_PCTOP_MASK 0xFF000UL /**< Bit mask for LESENSE_PCTOP */ #define _LESENSE_TIMCTRL_PCTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_TIMCTRL */ #define LESENSE_TIMCTRL_PCTOP_DEFAULT (_LESENSE_TIMCTRL_PCTOP_DEFAULT << 12) /**< Shifted mode DEFAULT for LESENSE_TIMCTRL */ #define _LESENSE_TIMCTRL_STARTDLY_SHIFT 22 /**< Shift value for LESENSE_STARTDLY */ #define _LESENSE_TIMCTRL_STARTDLY_MASK 0xC00000UL /**< Bit mask for LESENSE_STARTDLY */ #define _LESENSE_TIMCTRL_STARTDLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_TIMCTRL */ #define LESENSE_TIMCTRL_STARTDLY_DEFAULT (_LESENSE_TIMCTRL_STARTDLY_DEFAULT << 22) /**< Shifted mode DEFAULT for LESENSE_TIMCTRL */ #define LESENSE_TIMCTRL_AUXSTARTUP (0x1UL << 28) /**< AUXHFRCO Startup Configuration */ #define _LESENSE_TIMCTRL_AUXSTARTUP_SHIFT 28 /**< Shift value for LESENSE_AUXSTARTUP */ #define _LESENSE_TIMCTRL_AUXSTARTUP_MASK 0x10000000UL /**< Bit mask for LESENSE_AUXSTARTUP */ #define _LESENSE_TIMCTRL_AUXSTARTUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_TIMCTRL */ #define _LESENSE_TIMCTRL_AUXSTARTUP_PREDEMAND 0x00000000UL /**< Mode PREDEMAND for LESENSE_TIMCTRL */ #define _LESENSE_TIMCTRL_AUXSTARTUP_ONDEMAND 0x00000001UL /**< Mode ONDEMAND for LESENSE_TIMCTRL */ #define LESENSE_TIMCTRL_AUXSTARTUP_DEFAULT (_LESENSE_TIMCTRL_AUXSTARTUP_DEFAULT << 28) /**< Shifted mode DEFAULT for LESENSE_TIMCTRL */ #define LESENSE_TIMCTRL_AUXSTARTUP_PREDEMAND (_LESENSE_TIMCTRL_AUXSTARTUP_PREDEMAND << 28) /**< Shifted mode PREDEMAND for LESENSE_TIMCTRL */ #define LESENSE_TIMCTRL_AUXSTARTUP_ONDEMAND (_LESENSE_TIMCTRL_AUXSTARTUP_ONDEMAND << 28) /**< Shifted mode ONDEMAND for LESENSE_TIMCTRL */ /* Bit fields for LESENSE PERCTRL */ #define _LESENSE_PERCTRL_RESETVALUE 0x00000000UL /**< Default value for LESENSE_PERCTRL */ #define _LESENSE_PERCTRL_MASK 0x3FF0014FUL /**< Mask for LESENSE_PERCTRL */ #define LESENSE_PERCTRL_DACCH0EN (0x1UL << 0) /**< VDAC CH0 Enable */ #define _LESENSE_PERCTRL_DACCH0EN_SHIFT 0 /**< Shift value for LESENSE_DACCH0EN */ #define _LESENSE_PERCTRL_DACCH0EN_MASK 0x1UL /**< Bit mask for LESENSE_DACCH0EN */ #define _LESENSE_PERCTRL_DACCH0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */ #define LESENSE_PERCTRL_DACCH0EN_DEFAULT (_LESENSE_PERCTRL_DACCH0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */ #define LESENSE_PERCTRL_DACCH1EN (0x1UL << 1) /**< VDAC CH1 Enable */ #define _LESENSE_PERCTRL_DACCH1EN_SHIFT 1 /**< Shift value for LESENSE_DACCH1EN */ #define _LESENSE_PERCTRL_DACCH1EN_MASK 0x2UL /**< Bit mask for LESENSE_DACCH1EN */ #define _LESENSE_PERCTRL_DACCH1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */ #define LESENSE_PERCTRL_DACCH1EN_DEFAULT (_LESENSE_PERCTRL_DACCH1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */ #define LESENSE_PERCTRL_DACCH0DATA (0x1UL << 2) /**< VDAC CH0 Data Selection */ #define _LESENSE_PERCTRL_DACCH0DATA_SHIFT 2 /**< Shift value for LESENSE_DACCH0DATA */ #define _LESENSE_PERCTRL_DACCH0DATA_MASK 0x4UL /**< Bit mask for LESENSE_DACCH0DATA */ #define _LESENSE_PERCTRL_DACCH0DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */ #define _LESENSE_PERCTRL_DACCH0DATA_DACDATA 0x00000000UL /**< Mode DACDATA for LESENSE_PERCTRL */ #define _LESENSE_PERCTRL_DACCH0DATA_THRES 0x00000001UL /**< Mode THRES for LESENSE_PERCTRL */ #define LESENSE_PERCTRL_DACCH0DATA_DEFAULT (_LESENSE_PERCTRL_DACCH0DATA_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */ #define LESENSE_PERCTRL_DACCH0DATA_DACDATA (_LESENSE_PERCTRL_DACCH0DATA_DACDATA << 2) /**< Shifted mode DACDATA for LESENSE_PERCTRL */ #define LESENSE_PERCTRL_DACCH0DATA_THRES (_LESENSE_PERCTRL_DACCH0DATA_THRES << 2) /**< Shifted mode THRES for LESENSE_PERCTRL */ #define LESENSE_PERCTRL_DACCH1DATA (0x1UL << 3) /**< VDAC CH1 Data Selection */ #define _LESENSE_PERCTRL_DACCH1DATA_SHIFT 3 /**< Shift value for LESENSE_DACCH1DATA */ #define _LESENSE_PERCTRL_DACCH1DATA_MASK 0x8UL /**< Bit mask for LESENSE_DACCH1DATA */ #define _LESENSE_PERCTRL_DACCH1DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */ #define _LESENSE_PERCTRL_DACCH1DATA_DACDATA 0x00000000UL /**< Mode DACDATA for LESENSE_PERCTRL */ #define _LESENSE_PERCTRL_DACCH1DATA_THRES 0x00000001UL /**< Mode THRES for LESENSE_PERCTRL */ #define LESENSE_PERCTRL_DACCH1DATA_DEFAULT (_LESENSE_PERCTRL_DACCH1DATA_DEFAULT << 3) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */ #define LESENSE_PERCTRL_DACCH1DATA_DACDATA (_LESENSE_PERCTRL_DACCH1DATA_DACDATA << 3) /**< Shifted mode DACDATA for LESENSE_PERCTRL */ #define LESENSE_PERCTRL_DACCH1DATA_THRES (_LESENSE_PERCTRL_DACCH1DATA_THRES << 3) /**< Shifted mode THRES for LESENSE_PERCTRL */ #define LESENSE_PERCTRL_DACSTARTUP (0x1UL << 6) /**< VDAC Startup Configuration */ #define _LESENSE_PERCTRL_DACSTARTUP_SHIFT 6 /**< Shift value for LESENSE_DACSTARTUP */ #define _LESENSE_PERCTRL_DACSTARTUP_MASK 0x40UL /**< Bit mask for LESENSE_DACSTARTUP */ #define _LESENSE_PERCTRL_DACSTARTUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */ #define _LESENSE_PERCTRL_DACSTARTUP_FULLCYCLE 0x00000000UL /**< Mode FULLCYCLE for LESENSE_PERCTRL */ #define _LESENSE_PERCTRL_DACSTARTUP_HALFCYCLE 0x00000001UL /**< Mode HALFCYCLE for LESENSE_PERCTRL */ #define LESENSE_PERCTRL_DACSTARTUP_DEFAULT (_LESENSE_PERCTRL_DACSTARTUP_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */ #define LESENSE_PERCTRL_DACSTARTUP_FULLCYCLE (_LESENSE_PERCTRL_DACSTARTUP_FULLCYCLE << 6) /**< Shifted mode FULLCYCLE for LESENSE_PERCTRL */ #define LESENSE_PERCTRL_DACSTARTUP_HALFCYCLE (_LESENSE_PERCTRL_DACSTARTUP_HALFCYCLE << 6) /**< Shifted mode HALFCYCLE for LESENSE_PERCTRL */ #define LESENSE_PERCTRL_DACCONVTRIG (0x1UL << 8) /**< VDAC Conversion Trigger Configuration */ #define _LESENSE_PERCTRL_DACCONVTRIG_SHIFT 8 /**< Shift value for LESENSE_DACCONVTRIG */ #define _LESENSE_PERCTRL_DACCONVTRIG_MASK 0x100UL /**< Bit mask for LESENSE_DACCONVTRIG */ #define _LESENSE_PERCTRL_DACCONVTRIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */ #define _LESENSE_PERCTRL_DACCONVTRIG_CHANNELSTART 0x00000000UL /**< Mode CHANNELSTART for LESENSE_PERCTRL */ #define _LESENSE_PERCTRL_DACCONVTRIG_SCANSTART 0x00000001UL /**< Mode SCANSTART for LESENSE_PERCTRL */ #define LESENSE_PERCTRL_DACCONVTRIG_DEFAULT (_LESENSE_PERCTRL_DACCONVTRIG_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */ #define LESENSE_PERCTRL_DACCONVTRIG_CHANNELSTART (_LESENSE_PERCTRL_DACCONVTRIG_CHANNELSTART << 8) /**< Shifted mode CHANNELSTART for LESENSE_PERCTRL */ #define LESENSE_PERCTRL_DACCONVTRIG_SCANSTART (_LESENSE_PERCTRL_DACCONVTRIG_SCANSTART << 8) /**< Shifted mode SCANSTART for LESENSE_PERCTRL */ #define _LESENSE_PERCTRL_ACMP0MODE_SHIFT 20 /**< Shift value for LESENSE_ACMP0MODE */ #define _LESENSE_PERCTRL_ACMP0MODE_MASK 0x300000UL /**< Bit mask for LESENSE_ACMP0MODE */ #define _LESENSE_PERCTRL_ACMP0MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */ #define _LESENSE_PERCTRL_ACMP0MODE_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_PERCTRL */ #define _LESENSE_PERCTRL_ACMP0MODE_MUX 0x00000001UL /**< Mode MUX for LESENSE_PERCTRL */ #define _LESENSE_PERCTRL_ACMP0MODE_MUXTHRES 0x00000002UL /**< Mode MUXTHRES for LESENSE_PERCTRL */ #define LESENSE_PERCTRL_ACMP0MODE_DEFAULT (_LESENSE_PERCTRL_ACMP0MODE_DEFAULT << 20) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */ #define LESENSE_PERCTRL_ACMP0MODE_DISABLE (_LESENSE_PERCTRL_ACMP0MODE_DISABLE << 20) /**< Shifted mode DISABLE for LESENSE_PERCTRL */ #define LESENSE_PERCTRL_ACMP0MODE_MUX (_LESENSE_PERCTRL_ACMP0MODE_MUX << 20) /**< Shifted mode MUX for LESENSE_PERCTRL */ #define LESENSE_PERCTRL_ACMP0MODE_MUXTHRES (_LESENSE_PERCTRL_ACMP0MODE_MUXTHRES << 20) /**< Shifted mode MUXTHRES for LESENSE_PERCTRL */ #define _LESENSE_PERCTRL_ACMP1MODE_SHIFT 22 /**< Shift value for LESENSE_ACMP1MODE */ #define _LESENSE_PERCTRL_ACMP1MODE_MASK 0xC00000UL /**< Bit mask for LESENSE_ACMP1MODE */ #define _LESENSE_PERCTRL_ACMP1MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */ #define _LESENSE_PERCTRL_ACMP1MODE_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_PERCTRL */ #define _LESENSE_PERCTRL_ACMP1MODE_MUX 0x00000001UL /**< Mode MUX for LESENSE_PERCTRL */ #define _LESENSE_PERCTRL_ACMP1MODE_MUXTHRES 0x00000002UL /**< Mode MUXTHRES for LESENSE_PERCTRL */ #define LESENSE_PERCTRL_ACMP1MODE_DEFAULT (_LESENSE_PERCTRL_ACMP1MODE_DEFAULT << 22) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */ #define LESENSE_PERCTRL_ACMP1MODE_DISABLE (_LESENSE_PERCTRL_ACMP1MODE_DISABLE << 22) /**< Shifted mode DISABLE for LESENSE_PERCTRL */ #define LESENSE_PERCTRL_ACMP1MODE_MUX (_LESENSE_PERCTRL_ACMP1MODE_MUX << 22) /**< Shifted mode MUX for LESENSE_PERCTRL */ #define LESENSE_PERCTRL_ACMP1MODE_MUXTHRES (_LESENSE_PERCTRL_ACMP1MODE_MUXTHRES << 22) /**< Shifted mode MUXTHRES for LESENSE_PERCTRL */ #define LESENSE_PERCTRL_ACMP0INV (0x1UL << 24) /**< Invert Analog Comparator 0 Output */ #define _LESENSE_PERCTRL_ACMP0INV_SHIFT 24 /**< Shift value for LESENSE_ACMP0INV */ #define _LESENSE_PERCTRL_ACMP0INV_MASK 0x1000000UL /**< Bit mask for LESENSE_ACMP0INV */ #define _LESENSE_PERCTRL_ACMP0INV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */ #define LESENSE_PERCTRL_ACMP0INV_DEFAULT (_LESENSE_PERCTRL_ACMP0INV_DEFAULT << 24) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */ #define LESENSE_PERCTRL_ACMP1INV (0x1UL << 25) /**< Invert Analog Comparator 1 Output */ #define _LESENSE_PERCTRL_ACMP1INV_SHIFT 25 /**< Shift value for LESENSE_ACMP1INV */ #define _LESENSE_PERCTRL_ACMP1INV_MASK 0x2000000UL /**< Bit mask for LESENSE_ACMP1INV */ #define _LESENSE_PERCTRL_ACMP1INV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */ #define LESENSE_PERCTRL_ACMP1INV_DEFAULT (_LESENSE_PERCTRL_ACMP1INV_DEFAULT << 25) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */ #define LESENSE_PERCTRL_ACMP0HYSTEN (0x1UL << 26) /**< ACMP0 Hysteresis Enable */ #define _LESENSE_PERCTRL_ACMP0HYSTEN_SHIFT 26 /**< Shift value for LESENSE_ACMP0HYSTEN */ #define _LESENSE_PERCTRL_ACMP0HYSTEN_MASK 0x4000000UL /**< Bit mask for LESENSE_ACMP0HYSTEN */ #define _LESENSE_PERCTRL_ACMP0HYSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */ #define LESENSE_PERCTRL_ACMP0HYSTEN_DEFAULT (_LESENSE_PERCTRL_ACMP0HYSTEN_DEFAULT << 26) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */ #define LESENSE_PERCTRL_ACMP1HYSTEN (0x1UL << 27) /**< ACMP1 Hysteresis Enable */ #define _LESENSE_PERCTRL_ACMP1HYSTEN_SHIFT 27 /**< Shift value for LESENSE_ACMP1HYSTEN */ #define _LESENSE_PERCTRL_ACMP1HYSTEN_MASK 0x8000000UL /**< Bit mask for LESENSE_ACMP1HYSTEN */ #define _LESENSE_PERCTRL_ACMP1HYSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */ #define LESENSE_PERCTRL_ACMP1HYSTEN_DEFAULT (_LESENSE_PERCTRL_ACMP1HYSTEN_DEFAULT << 27) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */ #define _LESENSE_PERCTRL_WARMUPMODE_SHIFT 28 /**< Shift value for LESENSE_WARMUPMODE */ #define _LESENSE_PERCTRL_WARMUPMODE_MASK 0x30000000UL /**< Bit mask for LESENSE_WARMUPMODE */ #define _LESENSE_PERCTRL_WARMUPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */ #define _LESENSE_PERCTRL_WARMUPMODE_NORMAL 0x00000000UL /**< Mode NORMAL for LESENSE_PERCTRL */ #define _LESENSE_PERCTRL_WARMUPMODE_KEEPACMPWARM 0x00000001UL /**< Mode KEEPACMPWARM for LESENSE_PERCTRL */ #define _LESENSE_PERCTRL_WARMUPMODE_KEEPDACWARM 0x00000002UL /**< Mode KEEPDACWARM for LESENSE_PERCTRL */ #define _LESENSE_PERCTRL_WARMUPMODE_KEEPACMPDACWARM 0x00000003UL /**< Mode KEEPACMPDACWARM for LESENSE_PERCTRL */ #define LESENSE_PERCTRL_WARMUPMODE_DEFAULT (_LESENSE_PERCTRL_WARMUPMODE_DEFAULT << 28) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */ #define LESENSE_PERCTRL_WARMUPMODE_NORMAL (_LESENSE_PERCTRL_WARMUPMODE_NORMAL << 28) /**< Shifted mode NORMAL for LESENSE_PERCTRL */ #define LESENSE_PERCTRL_WARMUPMODE_KEEPACMPWARM (_LESENSE_PERCTRL_WARMUPMODE_KEEPACMPWARM << 28) /**< Shifted mode KEEPACMPWARM for LESENSE_PERCTRL */ #define LESENSE_PERCTRL_WARMUPMODE_KEEPDACWARM (_LESENSE_PERCTRL_WARMUPMODE_KEEPDACWARM << 28) /**< Shifted mode KEEPDACWARM for LESENSE_PERCTRL */ #define LESENSE_PERCTRL_WARMUPMODE_KEEPACMPDACWARM (_LESENSE_PERCTRL_WARMUPMODE_KEEPACMPDACWARM << 28) /**< Shifted mode KEEPACMPDACWARM for LESENSE_PERCTRL */ /* Bit fields for LESENSE DECCTRL */ #define _LESENSE_DECCTRL_RESETVALUE 0x00000000UL /**< Default value for LESENSE_DECCTRL */ #define _LESENSE_DECCTRL_MASK 0x1EF7BDFFUL /**< Mask for LESENSE_DECCTRL */ #define LESENSE_DECCTRL_DISABLE (0x1UL << 0) /**< Disable the Decoder */ #define _LESENSE_DECCTRL_DISABLE_SHIFT 0 /**< Shift value for LESENSE_DISABLE */ #define _LESENSE_DECCTRL_DISABLE_MASK 0x1UL /**< Bit mask for LESENSE_DISABLE */ #define _LESENSE_DECCTRL_DISABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */ #define LESENSE_DECCTRL_DISABLE_DEFAULT (_LESENSE_DECCTRL_DISABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */ #define LESENSE_DECCTRL_ERRCHK (0x1UL << 1) /**< Enable Check of Current State */ #define _LESENSE_DECCTRL_ERRCHK_SHIFT 1 /**< Shift value for LESENSE_ERRCHK */ #define _LESENSE_DECCTRL_ERRCHK_MASK 0x2UL /**< Bit mask for LESENSE_ERRCHK */ #define _LESENSE_DECCTRL_ERRCHK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */ #define LESENSE_DECCTRL_ERRCHK_DEFAULT (_LESENSE_DECCTRL_ERRCHK_DEFAULT << 1) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */ #define LESENSE_DECCTRL_INTMAP (0x1UL << 2) /**< Enable Decoder to Channel Interrupt Mapping */ #define _LESENSE_DECCTRL_INTMAP_SHIFT 2 /**< Shift value for LESENSE_INTMAP */ #define _LESENSE_DECCTRL_INTMAP_MASK 0x4UL /**< Bit mask for LESENSE_INTMAP */ #define _LESENSE_DECCTRL_INTMAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */ #define LESENSE_DECCTRL_INTMAP_DEFAULT (_LESENSE_DECCTRL_INTMAP_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */ #define LESENSE_DECCTRL_HYSTPRS0 (0x1UL << 3) /**< Enable Decoder Hysteresis on PRS0 Output */ #define _LESENSE_DECCTRL_HYSTPRS0_SHIFT 3 /**< Shift value for LESENSE_HYSTPRS0 */ #define _LESENSE_DECCTRL_HYSTPRS0_MASK 0x8UL /**< Bit mask for LESENSE_HYSTPRS0 */ #define _LESENSE_DECCTRL_HYSTPRS0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */ #define LESENSE_DECCTRL_HYSTPRS0_DEFAULT (_LESENSE_DECCTRL_HYSTPRS0_DEFAULT << 3) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */ #define LESENSE_DECCTRL_HYSTPRS1 (0x1UL << 4) /**< Enable Decoder Hysteresis on PRS1 Output */ #define _LESENSE_DECCTRL_HYSTPRS1_SHIFT 4 /**< Shift value for LESENSE_HYSTPRS1 */ #define _LESENSE_DECCTRL_HYSTPRS1_MASK 0x10UL /**< Bit mask for LESENSE_HYSTPRS1 */ #define _LESENSE_DECCTRL_HYSTPRS1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */ #define LESENSE_DECCTRL_HYSTPRS1_DEFAULT (_LESENSE_DECCTRL_HYSTPRS1_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */ #define LESENSE_DECCTRL_HYSTPRS2 (0x1UL << 5) /**< Enable Decoder Hysteresis on PRS2 Output */ #define _LESENSE_DECCTRL_HYSTPRS2_SHIFT 5 /**< Shift value for LESENSE_HYSTPRS2 */ #define _LESENSE_DECCTRL_HYSTPRS2_MASK 0x20UL /**< Bit mask for LESENSE_HYSTPRS2 */ #define _LESENSE_DECCTRL_HYSTPRS2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */ #define LESENSE_DECCTRL_HYSTPRS2_DEFAULT (_LESENSE_DECCTRL_HYSTPRS2_DEFAULT << 5) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */ #define LESENSE_DECCTRL_HYSTIRQ (0x1UL << 6) /**< Enable Decoder Hysteresis on Interrupt Requests */ #define _LESENSE_DECCTRL_HYSTIRQ_SHIFT 6 /**< Shift value for LESENSE_HYSTIRQ */ #define _LESENSE_DECCTRL_HYSTIRQ_MASK 0x40UL /**< Bit mask for LESENSE_HYSTIRQ */ #define _LESENSE_DECCTRL_HYSTIRQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */ #define LESENSE_DECCTRL_HYSTIRQ_DEFAULT (_LESENSE_DECCTRL_HYSTIRQ_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */ #define LESENSE_DECCTRL_PRSCNT (0x1UL << 7) /**< Enable Count Mode on Decoder PRS Channels 0 and 1 */ #define _LESENSE_DECCTRL_PRSCNT_SHIFT 7 /**< Shift value for LESENSE_PRSCNT */ #define _LESENSE_DECCTRL_PRSCNT_MASK 0x80UL /**< Bit mask for LESENSE_PRSCNT */ #define _LESENSE_DECCTRL_PRSCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */ #define LESENSE_DECCTRL_PRSCNT_DEFAULT (_LESENSE_DECCTRL_PRSCNT_DEFAULT << 7) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */ #define LESENSE_DECCTRL_INPUT (0x1UL << 8) /**< LESENSE Decoder Input Configuration */ #define _LESENSE_DECCTRL_INPUT_SHIFT 8 /**< Shift value for LESENSE_INPUT */ #define _LESENSE_DECCTRL_INPUT_MASK 0x100UL /**< Bit mask for LESENSE_INPUT */ #define _LESENSE_DECCTRL_INPUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */ #define _LESENSE_DECCTRL_INPUT_SENSORSTATE 0x00000000UL /**< Mode SENSORSTATE for LESENSE_DECCTRL */ #define _LESENSE_DECCTRL_INPUT_PRS 0x00000001UL /**< Mode PRS for LESENSE_DECCTRL */ #define LESENSE_DECCTRL_INPUT_DEFAULT (_LESENSE_DECCTRL_INPUT_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */ #define LESENSE_DECCTRL_INPUT_SENSORSTATE (_LESENSE_DECCTRL_INPUT_SENSORSTATE << 8) /**< Shifted mode SENSORSTATE for LESENSE_DECCTRL */ #define LESENSE_DECCTRL_INPUT_PRS (_LESENSE_DECCTRL_INPUT_PRS << 8) /**< Shifted mode PRS for LESENSE_DECCTRL */ #define _LESENSE_DECCTRL_PRSSEL0_SHIFT 10 /**< Shift value for LESENSE_PRSSEL0 */ #define _LESENSE_DECCTRL_PRSSEL0_MASK 0x3C00UL /**< Bit mask for LESENSE_PRSSEL0 */ #define _LESENSE_DECCTRL_PRSSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */ #define _LESENSE_DECCTRL_PRSSEL0_PRSCH0 0x00000000UL /**< Mode PRSCH0 for LESENSE_DECCTRL */ #define _LESENSE_DECCTRL_PRSSEL0_PRSCH1 0x00000001UL /**< Mode PRSCH1 for LESENSE_DECCTRL */ #define _LESENSE_DECCTRL_PRSSEL0_PRSCH2 0x00000002UL /**< Mode PRSCH2 for LESENSE_DECCTRL */ #define _LESENSE_DECCTRL_PRSSEL0_PRSCH3 0x00000003UL /**< Mode PRSCH3 for LESENSE_DECCTRL */ #define _LESENSE_DECCTRL_PRSSEL0_PRSCH4 0x00000004UL /**< Mode PRSCH4 for LESENSE_DECCTRL */ #define _LESENSE_DECCTRL_PRSSEL0_PRSCH5 0x00000005UL /**< Mode PRSCH5 for LESENSE_DECCTRL */ #define _LESENSE_DECCTRL_PRSSEL0_PRSCH6 0x00000006UL /**< Mode PRSCH6 for LESENSE_DECCTRL */ #define _LESENSE_DECCTRL_PRSSEL0_PRSCH7 0x00000007UL /**< Mode PRSCH7 for LESENSE_DECCTRL */ #define _LESENSE_DECCTRL_PRSSEL0_PRSCH8 0x00000008UL /**< Mode PRSCH8 for LESENSE_DECCTRL */ #define _LESENSE_DECCTRL_PRSSEL0_PRSCH9 0x00000009UL /**< Mode PRSCH9 for LESENSE_DECCTRL */ #define _LESENSE_DECCTRL_PRSSEL0_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for LESENSE_DECCTRL */ #define _LESENSE_DECCTRL_PRSSEL0_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for LESENSE_DECCTRL */ #define LESENSE_DECCTRL_PRSSEL0_DEFAULT (_LESENSE_DECCTRL_PRSSEL0_DEFAULT << 10) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */ #define LESENSE_DECCTRL_PRSSEL0_PRSCH0 (_LESENSE_DECCTRL_PRSSEL0_PRSCH0 << 10) /**< Shifted mode PRSCH0 for LESENSE_DECCTRL */ #define LESENSE_DECCTRL_PRSSEL0_PRSCH1 (_LESENSE_DECCTRL_PRSSEL0_PRSCH1 << 10) /**< Shifted mode PRSCH1 for LESENSE_DECCTRL */ #define LESENSE_DECCTRL_PRSSEL0_PRSCH2 (_LESENSE_DECCTRL_PRSSEL0_PRSCH2 << 10) /**< Shifted mode PRSCH2 for LESENSE_DECCTRL */ #define LESENSE_DECCTRL_PRSSEL0_PRSCH3 (_LESENSE_DECCTRL_PRSSEL0_PRSCH3 << 10) /**< Shifted mode PRSCH3 for LESENSE_DECCTRL */ #define LESENSE_DECCTRL_PRSSEL0_PRSCH4 (_LESENSE_DECCTRL_PRSSEL0_PRSCH4 << 10) /**< Shifted mode PRSCH4 for LESENSE_DECCTRL */ #define LESENSE_DECCTRL_PRSSEL0_PRSCH5 (_LESENSE_DECCTRL_PRSSEL0_PRSCH5 << 10) /**< Shifted mode PRSCH5 for LESENSE_DECCTRL */ #define LESENSE_DECCTRL_PRSSEL0_PRSCH6 (_LESENSE_DECCTRL_PRSSEL0_PRSCH6 << 10) /**< Shifted mode PRSCH6 for LESENSE_DECCTRL */ #define LESENSE_DECCTRL_PRSSEL0_PRSCH7 (_LESENSE_DECCTRL_PRSSEL0_PRSCH7 << 10) /**< Shifted mode PRSCH7 for LESENSE_DECCTRL */ #define LESENSE_DECCTRL_PRSSEL0_PRSCH8 (_LESENSE_DECCTRL_PRSSEL0_PRSCH8 << 10) /**< Shifted mode PRSCH8 for LESENSE_DECCTRL */ #define LESENSE_DECCTRL_PRSSEL0_PRSCH9 (_LESENSE_DECCTRL_PRSSEL0_PRSCH9 << 10) /**< Shifted mode PRSCH9 for LESENSE_DECCTRL */ #define LESENSE_DECCTRL_PRSSEL0_PRSCH10 (_LESENSE_DECCTRL_PRSSEL0_PRSCH10 << 10) /**< Shifted mode PRSCH10 for LESENSE_DECCTRL */ #define LESENSE_DECCTRL_PRSSEL0_PRSCH11 (_LESENSE_DECCTRL_PRSSEL0_PRSCH11 << 10) /**< Shifted mode PRSCH11 for LESENSE_DECCTRL */ #define _LESENSE_DECCTRL_PRSSEL1_SHIFT 15 /**< Shift value for LESENSE_PRSSEL1 */ #define _LESENSE_DECCTRL_PRSSEL1_MASK 0x78000UL /**< Bit mask for LESENSE_PRSSEL1 */ #define _LESENSE_DECCTRL_PRSSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */ #define _LESENSE_DECCTRL_PRSSEL1_PRSCH0 0x00000000UL /**< Mode PRSCH0 for LESENSE_DECCTRL */ #define _LESENSE_DECCTRL_PRSSEL1_PRSCH1 0x00000001UL /**< Mode PRSCH1 for LESENSE_DECCTRL */ #define _LESENSE_DECCTRL_PRSSEL1_PRSCH2 0x00000002UL /**< Mode PRSCH2 for LESENSE_DECCTRL */ #define _LESENSE_DECCTRL_PRSSEL1_PRSCH3 0x00000003UL /**< Mode PRSCH3 for LESENSE_DECCTRL */ #define _LESENSE_DECCTRL_PRSSEL1_PRSCH4 0x00000004UL /**< Mode PRSCH4 for LESENSE_DECCTRL */ #define _LESENSE_DECCTRL_PRSSEL1_PRSCH5 0x00000005UL /**< Mode PRSCH5 for LESENSE_DECCTRL */ #define _LESENSE_DECCTRL_PRSSEL1_PRSCH6 0x00000006UL /**< Mode PRSCH6 for LESENSE_DECCTRL */ #define _LESENSE_DECCTRL_PRSSEL1_PRSCH7 0x00000007UL /**< Mode PRSCH7 for LESENSE_DECCTRL */ #define _LESENSE_DECCTRL_PRSSEL1_PRSCH8 0x00000008UL /**< Mode PRSCH8 for LESENSE_DECCTRL */ #define _LESENSE_DECCTRL_PRSSEL1_PRSCH9 0x00000009UL /**< Mode PRSCH9 for LESENSE_DECCTRL */ #define _LESENSE_DECCTRL_PRSSEL1_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for LESENSE_DECCTRL */ #define _LESENSE_DECCTRL_PRSSEL1_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for LESENSE_DECCTRL */ #define LESENSE_DECCTRL_PRSSEL1_DEFAULT (_LESENSE_DECCTRL_PRSSEL1_DEFAULT << 15) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */ #define LESENSE_DECCTRL_PRSSEL1_PRSCH0 (_LESENSE_DECCTRL_PRSSEL1_PRSCH0 << 15) /**< Shifted mode PRSCH0 for LESENSE_DECCTRL */ #define LESENSE_DECCTRL_PRSSEL1_PRSCH1 (_LESENSE_DECCTRL_PRSSEL1_PRSCH1 << 15) /**< Shifted mode PRSCH1 for LESENSE_DECCTRL */ #define LESENSE_DECCTRL_PRSSEL1_PRSCH2 (_LESENSE_DECCTRL_PRSSEL1_PRSCH2 << 15) /**< Shifted mode PRSCH2 for LESENSE_DECCTRL */ #define LESENSE_DECCTRL_PRSSEL1_PRSCH3 (_LESENSE_DECCTRL_PRSSEL1_PRSCH3 << 15) /**< Shifted mode PRSCH3 for LESENSE_DECCTRL */ #define LESENSE_DECCTRL_PRSSEL1_PRSCH4 (_LESENSE_DECCTRL_PRSSEL1_PRSCH4 << 15) /**< Shifted mode PRSCH4 for LESENSE_DECCTRL */ #define LESENSE_DECCTRL_PRSSEL1_PRSCH5 (_LESENSE_DECCTRL_PRSSEL1_PRSCH5 << 15) /**< Shifted mode PRSCH5 for LESENSE_DECCTRL */ #define LESENSE_DECCTRL_PRSSEL1_PRSCH6 (_LESENSE_DECCTRL_PRSSEL1_PRSCH6 << 15) /**< Shifted mode PRSCH6 for LESENSE_DECCTRL */ #define LESENSE_DECCTRL_PRSSEL1_PRSCH7 (_LESENSE_DECCTRL_PRSSEL1_PRSCH7 << 15) /**< Shifted mode PRSCH7 for LESENSE_DECCTRL */ #define LESENSE_DECCTRL_PRSSEL1_PRSCH8 (_LESENSE_DECCTRL_PRSSEL1_PRSCH8 << 15) /**< Shifted mode PRSCH8 for LESENSE_DECCTRL */ #define LESENSE_DECCTRL_PRSSEL1_PRSCH9 (_LESENSE_DECCTRL_PRSSEL1_PRSCH9 << 15) /**< Shifted mode PRSCH9 for LESENSE_DECCTRL */ #define LESENSE_DECCTRL_PRSSEL1_PRSCH10 (_LESENSE_DECCTRL_PRSSEL1_PRSCH10 << 15) /**< Shifted mode PRSCH10 for LESENSE_DECCTRL */ #define LESENSE_DECCTRL_PRSSEL1_PRSCH11 (_LESENSE_DECCTRL_PRSSEL1_PRSCH11 << 15) /**< Shifted mode PRSCH11 for LESENSE_DECCTRL */ #define _LESENSE_DECCTRL_PRSSEL2_SHIFT 20 /**< Shift value for LESENSE_PRSSEL2 */ #define _LESENSE_DECCTRL_PRSSEL2_MASK 0xF00000UL /**< Bit mask for LESENSE_PRSSEL2 */ #define _LESENSE_DECCTRL_PRSSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */ #define _LESENSE_DECCTRL_PRSSEL2_PRSCH0 0x00000000UL /**< Mode PRSCH0 for LESENSE_DECCTRL */ #define _LESENSE_DECCTRL_PRSSEL2_PRSCH1 0x00000001UL /**< Mode PRSCH1 for LESENSE_DECCTRL */ #define _LESENSE_DECCTRL_PRSSEL2_PRSCH2 0x00000002UL /**< Mode PRSCH2 for LESENSE_DECCTRL */ #define _LESENSE_DECCTRL_PRSSEL2_PRSCH3 0x00000003UL /**< Mode PRSCH3 for LESENSE_DECCTRL */ #define _LESENSE_DECCTRL_PRSSEL2_PRSCH4 0x00000004UL /**< Mode PRSCH4 for LESENSE_DECCTRL */ #define _LESENSE_DECCTRL_PRSSEL2_PRSCH5 0x00000005UL /**< Mode PRSCH5 for LESENSE_DECCTRL */ #define _LESENSE_DECCTRL_PRSSEL2_PRSCH6 0x00000006UL /**< Mode PRSCH6 for LESENSE_DECCTRL */ #define _LESENSE_DECCTRL_PRSSEL2_PRSCH7 0x00000007UL /**< Mode PRSCH7 for LESENSE_DECCTRL */ #define _LESENSE_DECCTRL_PRSSEL2_PRSCH8 0x00000008UL /**< Mode PRSCH8 for LESENSE_DECCTRL */ #define _LESENSE_DECCTRL_PRSSEL2_PRSCH9 0x00000009UL /**< Mode PRSCH9 for LESENSE_DECCTRL */ #define _LESENSE_DECCTRL_PRSSEL2_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for LESENSE_DECCTRL */ #define _LESENSE_DECCTRL_PRSSEL2_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for LESENSE_DECCTRL */ #define LESENSE_DECCTRL_PRSSEL2_DEFAULT (_LESENSE_DECCTRL_PRSSEL2_DEFAULT << 20) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */ #define LESENSE_DECCTRL_PRSSEL2_PRSCH0 (_LESENSE_DECCTRL_PRSSEL2_PRSCH0 << 20) /**< Shifted mode PRSCH0 for LESENSE_DECCTRL */ #define LESENSE_DECCTRL_PRSSEL2_PRSCH1 (_LESENSE_DECCTRL_PRSSEL2_PRSCH1 << 20) /**< Shifted mode PRSCH1 for LESENSE_DECCTRL */ #define LESENSE_DECCTRL_PRSSEL2_PRSCH2 (_LESENSE_DECCTRL_PRSSEL2_PRSCH2 << 20) /**< Shifted mode PRSCH2 for LESENSE_DECCTRL */ #define LESENSE_DECCTRL_PRSSEL2_PRSCH3 (_LESENSE_DECCTRL_PRSSEL2_PRSCH3 << 20) /**< Shifted mode PRSCH3 for LESENSE_DECCTRL */ #define LESENSE_DECCTRL_PRSSEL2_PRSCH4 (_LESENSE_DECCTRL_PRSSEL2_PRSCH4 << 20) /**< Shifted mode PRSCH4 for LESENSE_DECCTRL */ #define LESENSE_DECCTRL_PRSSEL2_PRSCH5 (_LESENSE_DECCTRL_PRSSEL2_PRSCH5 << 20) /**< Shifted mode PRSCH5 for LESENSE_DECCTRL */ #define LESENSE_DECCTRL_PRSSEL2_PRSCH6 (_LESENSE_DECCTRL_PRSSEL2_PRSCH6 << 20) /**< Shifted mode PRSCH6 for LESENSE_DECCTRL */ #define LESENSE_DECCTRL_PRSSEL2_PRSCH7 (_LESENSE_DECCTRL_PRSSEL2_PRSCH7 << 20) /**< Shifted mode PRSCH7 for LESENSE_DECCTRL */ #define LESENSE_DECCTRL_PRSSEL2_PRSCH8 (_LESENSE_DECCTRL_PRSSEL2_PRSCH8 << 20) /**< Shifted mode PRSCH8 for LESENSE_DECCTRL */ #define LESENSE_DECCTRL_PRSSEL2_PRSCH9 (_LESENSE_DECCTRL_PRSSEL2_PRSCH9 << 20) /**< Shifted mode PRSCH9 for LESENSE_DECCTRL */ #define LESENSE_DECCTRL_PRSSEL2_PRSCH10 (_LESENSE_DECCTRL_PRSSEL2_PRSCH10 << 20) /**< Shifted mode PRSCH10 for LESENSE_DECCTRL */ #define LESENSE_DECCTRL_PRSSEL2_PRSCH11 (_LESENSE_DECCTRL_PRSSEL2_PRSCH11 << 20) /**< Shifted mode PRSCH11 for LESENSE_DECCTRL */ #define _LESENSE_DECCTRL_PRSSEL3_SHIFT 25 /**< Shift value for LESENSE_PRSSEL3 */ #define _LESENSE_DECCTRL_PRSSEL3_MASK 0x1E000000UL /**< Bit mask for LESENSE_PRSSEL3 */ #define _LESENSE_DECCTRL_PRSSEL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */ #define _LESENSE_DECCTRL_PRSSEL3_PRSCH0 0x00000000UL /**< Mode PRSCH0 for LESENSE_DECCTRL */ #define _LESENSE_DECCTRL_PRSSEL3_PRSCH1 0x00000001UL /**< Mode PRSCH1 for LESENSE_DECCTRL */ #define _LESENSE_DECCTRL_PRSSEL3_PRSCH2 0x00000002UL /**< Mode PRSCH2 for LESENSE_DECCTRL */ #define _LESENSE_DECCTRL_PRSSEL3_PRSCH3 0x00000003UL /**< Mode PRSCH3 for LESENSE_DECCTRL */ #define _LESENSE_DECCTRL_PRSSEL3_PRSCH4 0x00000004UL /**< Mode PRSCH4 for LESENSE_DECCTRL */ #define _LESENSE_DECCTRL_PRSSEL3_PRSCH5 0x00000005UL /**< Mode PRSCH5 for LESENSE_DECCTRL */ #define _LESENSE_DECCTRL_PRSSEL3_PRSCH6 0x00000006UL /**< Mode PRSCH6 for LESENSE_DECCTRL */ #define _LESENSE_DECCTRL_PRSSEL3_PRSCH7 0x00000007UL /**< Mode PRSCH7 for LESENSE_DECCTRL */ #define _LESENSE_DECCTRL_PRSSEL3_PRSCH8 0x00000008UL /**< Mode PRSCH8 for LESENSE_DECCTRL */ #define _LESENSE_DECCTRL_PRSSEL3_PRSCH9 0x00000009UL /**< Mode PRSCH9 for LESENSE_DECCTRL */ #define _LESENSE_DECCTRL_PRSSEL3_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for LESENSE_DECCTRL */ #define _LESENSE_DECCTRL_PRSSEL3_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for LESENSE_DECCTRL */ #define LESENSE_DECCTRL_PRSSEL3_DEFAULT (_LESENSE_DECCTRL_PRSSEL3_DEFAULT << 25) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */ #define LESENSE_DECCTRL_PRSSEL3_PRSCH0 (_LESENSE_DECCTRL_PRSSEL3_PRSCH0 << 25) /**< Shifted mode PRSCH0 for LESENSE_DECCTRL */ #define LESENSE_DECCTRL_PRSSEL3_PRSCH1 (_LESENSE_DECCTRL_PRSSEL3_PRSCH1 << 25) /**< Shifted mode PRSCH1 for LESENSE_DECCTRL */ #define LESENSE_DECCTRL_PRSSEL3_PRSCH2 (_LESENSE_DECCTRL_PRSSEL3_PRSCH2 << 25) /**< Shifted mode PRSCH2 for LESENSE_DECCTRL */ #define LESENSE_DECCTRL_PRSSEL3_PRSCH3 (_LESENSE_DECCTRL_PRSSEL3_PRSCH3 << 25) /**< Shifted mode PRSCH3 for LESENSE_DECCTRL */ #define LESENSE_DECCTRL_PRSSEL3_PRSCH4 (_LESENSE_DECCTRL_PRSSEL3_PRSCH4 << 25) /**< Shifted mode PRSCH4 for LESENSE_DECCTRL */ #define LESENSE_DECCTRL_PRSSEL3_PRSCH5 (_LESENSE_DECCTRL_PRSSEL3_PRSCH5 << 25) /**< Shifted mode PRSCH5 for LESENSE_DECCTRL */ #define LESENSE_DECCTRL_PRSSEL3_PRSCH6 (_LESENSE_DECCTRL_PRSSEL3_PRSCH6 << 25) /**< Shifted mode PRSCH6 for LESENSE_DECCTRL */ #define LESENSE_DECCTRL_PRSSEL3_PRSCH7 (_LESENSE_DECCTRL_PRSSEL3_PRSCH7 << 25) /**< Shifted mode PRSCH7 for LESENSE_DECCTRL */ #define LESENSE_DECCTRL_PRSSEL3_PRSCH8 (_LESENSE_DECCTRL_PRSSEL3_PRSCH8 << 25) /**< Shifted mode PRSCH8 for LESENSE_DECCTRL */ #define LESENSE_DECCTRL_PRSSEL3_PRSCH9 (_LESENSE_DECCTRL_PRSSEL3_PRSCH9 << 25) /**< Shifted mode PRSCH9 for LESENSE_DECCTRL */ #define LESENSE_DECCTRL_PRSSEL3_PRSCH10 (_LESENSE_DECCTRL_PRSSEL3_PRSCH10 << 25) /**< Shifted mode PRSCH10 for LESENSE_DECCTRL */ #define LESENSE_DECCTRL_PRSSEL3_PRSCH11 (_LESENSE_DECCTRL_PRSSEL3_PRSCH11 << 25) /**< Shifted mode PRSCH11 for LESENSE_DECCTRL */ /* Bit fields for LESENSE BIASCTRL */ #define _LESENSE_BIASCTRL_RESETVALUE 0x00000000UL /**< Default value for LESENSE_BIASCTRL */ #define _LESENSE_BIASCTRL_MASK 0x00000003UL /**< Mask for LESENSE_BIASCTRL */ #define _LESENSE_BIASCTRL_BIASMODE_SHIFT 0 /**< Shift value for LESENSE_BIASMODE */ #define _LESENSE_BIASCTRL_BIASMODE_MASK 0x3UL /**< Bit mask for LESENSE_BIASMODE */ #define _LESENSE_BIASCTRL_BIASMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_BIASCTRL */ #define _LESENSE_BIASCTRL_BIASMODE_DONTTOUCH 0x00000000UL /**< Mode DONTTOUCH for LESENSE_BIASCTRL */ #define _LESENSE_BIASCTRL_BIASMODE_DUTYCYCLE 0x00000001UL /**< Mode DUTYCYCLE for LESENSE_BIASCTRL */ #define _LESENSE_BIASCTRL_BIASMODE_HIGHACC 0x00000002UL /**< Mode HIGHACC for LESENSE_BIASCTRL */ #define LESENSE_BIASCTRL_BIASMODE_DEFAULT (_LESENSE_BIASCTRL_BIASMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_BIASCTRL */ #define LESENSE_BIASCTRL_BIASMODE_DONTTOUCH (_LESENSE_BIASCTRL_BIASMODE_DONTTOUCH << 0) /**< Shifted mode DONTTOUCH for LESENSE_BIASCTRL */ #define LESENSE_BIASCTRL_BIASMODE_DUTYCYCLE (_LESENSE_BIASCTRL_BIASMODE_DUTYCYCLE << 0) /**< Shifted mode DUTYCYCLE for LESENSE_BIASCTRL */ #define LESENSE_BIASCTRL_BIASMODE_HIGHACC (_LESENSE_BIASCTRL_BIASMODE_HIGHACC << 0) /**< Shifted mode HIGHACC for LESENSE_BIASCTRL */ /* Bit fields for LESENSE EVALCTRL */ #define _LESENSE_EVALCTRL_RESETVALUE 0x00000000UL /**< Default value for LESENSE_EVALCTRL */ #define _LESENSE_EVALCTRL_MASK 0x0000FFFFUL /**< Mask for LESENSE_EVALCTRL */ #define _LESENSE_EVALCTRL_WINSIZE_SHIFT 0 /**< Shift value for LESENSE_WINSIZE */ #define _LESENSE_EVALCTRL_WINSIZE_MASK 0xFFFFUL /**< Bit mask for LESENSE_WINSIZE */ #define _LESENSE_EVALCTRL_WINSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_EVALCTRL */ #define LESENSE_EVALCTRL_WINSIZE_DEFAULT (_LESENSE_EVALCTRL_WINSIZE_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_EVALCTRL */ /* Bit fields for LESENSE PRSCTRL */ #define _LESENSE_PRSCTRL_RESETVALUE 0x00000000UL /**< Default value for LESENSE_PRSCTRL */ #define _LESENSE_PRSCTRL_MASK 0x00011F1FUL /**< Mask for LESENSE_PRSCTRL */ #define _LESENSE_PRSCTRL_DECCMPVAL_SHIFT 0 /**< Shift value for LESENSE_DECCMPVAL */ #define _LESENSE_PRSCTRL_DECCMPVAL_MASK 0x1FUL /**< Bit mask for LESENSE_DECCMPVAL */ #define _LESENSE_PRSCTRL_DECCMPVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PRSCTRL */ #define LESENSE_PRSCTRL_DECCMPVAL_DEFAULT (_LESENSE_PRSCTRL_DECCMPVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_PRSCTRL */ #define _LESENSE_PRSCTRL_DECCMPMASK_SHIFT 8 /**< Shift value for LESENSE_DECCMPMASK */ #define _LESENSE_PRSCTRL_DECCMPMASK_MASK 0x1F00UL /**< Bit mask for LESENSE_DECCMPMASK */ #define _LESENSE_PRSCTRL_DECCMPMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PRSCTRL */ #define LESENSE_PRSCTRL_DECCMPMASK_DEFAULT (_LESENSE_PRSCTRL_DECCMPMASK_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_PRSCTRL */ #define LESENSE_PRSCTRL_DECCMPEN (0x1UL << 16) /**< Enable PRS Output DECCMP */ #define _LESENSE_PRSCTRL_DECCMPEN_SHIFT 16 /**< Shift value for LESENSE_DECCMPEN */ #define _LESENSE_PRSCTRL_DECCMPEN_MASK 0x10000UL /**< Bit mask for LESENSE_DECCMPEN */ #define _LESENSE_PRSCTRL_DECCMPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PRSCTRL */ #define LESENSE_PRSCTRL_DECCMPEN_DEFAULT (_LESENSE_PRSCTRL_DECCMPEN_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_PRSCTRL */ /* Bit fields for LESENSE CMD */ #define _LESENSE_CMD_RESETVALUE 0x00000000UL /**< Default value for LESENSE_CMD */ #define _LESENSE_CMD_MASK 0x0000000FUL /**< Mask for LESENSE_CMD */ #define LESENSE_CMD_START (0x1UL << 0) /**< Start Scanning of Sensors */ #define _LESENSE_CMD_START_SHIFT 0 /**< Shift value for LESENSE_START */ #define _LESENSE_CMD_START_MASK 0x1UL /**< Bit mask for LESENSE_START */ #define _LESENSE_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CMD */ #define LESENSE_CMD_START_DEFAULT (_LESENSE_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_CMD */ #define LESENSE_CMD_STOP (0x1UL << 1) /**< Stop Scanning of Sensors */ #define _LESENSE_CMD_STOP_SHIFT 1 /**< Shift value for LESENSE_STOP */ #define _LESENSE_CMD_STOP_MASK 0x2UL /**< Bit mask for LESENSE_STOP */ #define _LESENSE_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CMD */ #define LESENSE_CMD_STOP_DEFAULT (_LESENSE_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for LESENSE_CMD */ #define LESENSE_CMD_DECODE (0x1UL << 2) /**< Start Decoder */ #define _LESENSE_CMD_DECODE_SHIFT 2 /**< Shift value for LESENSE_DECODE */ #define _LESENSE_CMD_DECODE_MASK 0x4UL /**< Bit mask for LESENSE_DECODE */ #define _LESENSE_CMD_DECODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CMD */ #define LESENSE_CMD_DECODE_DEFAULT (_LESENSE_CMD_DECODE_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_CMD */ #define LESENSE_CMD_CLEARBUF (0x1UL << 3) /**< Clear Result Buffer */ #define _LESENSE_CMD_CLEARBUF_SHIFT 3 /**< Shift value for LESENSE_CLEARBUF */ #define _LESENSE_CMD_CLEARBUF_MASK 0x8UL /**< Bit mask for LESENSE_CLEARBUF */ #define _LESENSE_CMD_CLEARBUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CMD */ #define LESENSE_CMD_CLEARBUF_DEFAULT (_LESENSE_CMD_CLEARBUF_DEFAULT << 3) /**< Shifted mode DEFAULT for LESENSE_CMD */ /* Bit fields for LESENSE CHEN */ #define _LESENSE_CHEN_RESETVALUE 0x00000000UL /**< Default value for LESENSE_CHEN */ #define _LESENSE_CHEN_MASK 0x0000FFFFUL /**< Mask for LESENSE_CHEN */ #define _LESENSE_CHEN_CHEN_SHIFT 0 /**< Shift value for LESENSE_CHEN */ #define _LESENSE_CHEN_CHEN_MASK 0xFFFFUL /**< Bit mask for LESENSE_CHEN */ #define _LESENSE_CHEN_CHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CHEN */ #define LESENSE_CHEN_CHEN_DEFAULT (_LESENSE_CHEN_CHEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_CHEN */ /* Bit fields for LESENSE SCANRES */ #define _LESENSE_SCANRES_RESETVALUE 0x00000000UL /**< Default value for LESENSE_SCANRES */ #define _LESENSE_SCANRES_MASK 0xFFFFFFFFUL /**< Mask for LESENSE_SCANRES */ #define _LESENSE_SCANRES_SCANRES_SHIFT 0 /**< Shift value for LESENSE_SCANRES */ #define _LESENSE_SCANRES_SCANRES_MASK 0xFFFFUL /**< Bit mask for LESENSE_SCANRES */ #define _LESENSE_SCANRES_SCANRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_SCANRES */ #define LESENSE_SCANRES_SCANRES_DEFAULT (_LESENSE_SCANRES_SCANRES_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_SCANRES */ #define _LESENSE_SCANRES_STEPDIR_SHIFT 16 /**< Shift value for LESENSE_STEPDIR */ #define _LESENSE_SCANRES_STEPDIR_MASK 0xFFFF0000UL /**< Bit mask for LESENSE_STEPDIR */ #define _LESENSE_SCANRES_STEPDIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_SCANRES */ #define LESENSE_SCANRES_STEPDIR_DEFAULT (_LESENSE_SCANRES_STEPDIR_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_SCANRES */ /* Bit fields for LESENSE STATUS */ #define _LESENSE_STATUS_RESETVALUE 0x00000000UL /**< Default value for LESENSE_STATUS */ #define _LESENSE_STATUS_MASK 0x0000003FUL /**< Mask for LESENSE_STATUS */ #define LESENSE_STATUS_BUFDATAV (0x1UL << 0) /**< Result Data Valid */ #define _LESENSE_STATUS_BUFDATAV_SHIFT 0 /**< Shift value for LESENSE_BUFDATAV */ #define _LESENSE_STATUS_BUFDATAV_MASK 0x1UL /**< Bit mask for LESENSE_BUFDATAV */ #define _LESENSE_STATUS_BUFDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_STATUS */ #define LESENSE_STATUS_BUFDATAV_DEFAULT (_LESENSE_STATUS_BUFDATAV_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_STATUS */ #define LESENSE_STATUS_BUFHALFFULL (0x1UL << 1) /**< Result Buffer Half Full */ #define _LESENSE_STATUS_BUFHALFFULL_SHIFT 1 /**< Shift value for LESENSE_BUFHALFFULL */ #define _LESENSE_STATUS_BUFHALFFULL_MASK 0x2UL /**< Bit mask for LESENSE_BUFHALFFULL */ #define _LESENSE_STATUS_BUFHALFFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_STATUS */ #define LESENSE_STATUS_BUFHALFFULL_DEFAULT (_LESENSE_STATUS_BUFHALFFULL_DEFAULT << 1) /**< Shifted mode DEFAULT for LESENSE_STATUS */ #define LESENSE_STATUS_BUFFULL (0x1UL << 2) /**< Result Buffer Full */ #define _LESENSE_STATUS_BUFFULL_SHIFT 2 /**< Shift value for LESENSE_BUFFULL */ #define _LESENSE_STATUS_BUFFULL_MASK 0x4UL /**< Bit mask for LESENSE_BUFFULL */ #define _LESENSE_STATUS_BUFFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_STATUS */ #define LESENSE_STATUS_BUFFULL_DEFAULT (_LESENSE_STATUS_BUFFULL_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_STATUS */ #define LESENSE_STATUS_RUNNING (0x1UL << 3) /**< LESENSE Periodic Counter Running */ #define _LESENSE_STATUS_RUNNING_SHIFT 3 /**< Shift value for LESENSE_RUNNING */ #define _LESENSE_STATUS_RUNNING_MASK 0x8UL /**< Bit mask for LESENSE_RUNNING */ #define _LESENSE_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_STATUS */ #define LESENSE_STATUS_RUNNING_DEFAULT (_LESENSE_STATUS_RUNNING_DEFAULT << 3) /**< Shifted mode DEFAULT for LESENSE_STATUS */ #define LESENSE_STATUS_SCANACTIVE (0x1UL << 4) /**< LESENSE Scan Active */ #define _LESENSE_STATUS_SCANACTIVE_SHIFT 4 /**< Shift value for LESENSE_SCANACTIVE */ #define _LESENSE_STATUS_SCANACTIVE_MASK 0x10UL /**< Bit mask for LESENSE_SCANACTIVE */ #define _LESENSE_STATUS_SCANACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_STATUS */ #define LESENSE_STATUS_SCANACTIVE_DEFAULT (_LESENSE_STATUS_SCANACTIVE_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_STATUS */ #define LESENSE_STATUS_DACACTIVE (0x1UL << 5) /**< LESENSE VDAC Interface is Active */ #define _LESENSE_STATUS_DACACTIVE_SHIFT 5 /**< Shift value for LESENSE_DACACTIVE */ #define _LESENSE_STATUS_DACACTIVE_MASK 0x20UL /**< Bit mask for LESENSE_DACACTIVE */ #define _LESENSE_STATUS_DACACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_STATUS */ #define LESENSE_STATUS_DACACTIVE_DEFAULT (_LESENSE_STATUS_DACACTIVE_DEFAULT << 5) /**< Shifted mode DEFAULT for LESENSE_STATUS */ /* Bit fields for LESENSE PTR */ #define _LESENSE_PTR_RESETVALUE 0x00000000UL /**< Default value for LESENSE_PTR */ #define _LESENSE_PTR_MASK 0x000000FFUL /**< Mask for LESENSE_PTR */ #define _LESENSE_PTR_RD_SHIFT 0 /**< Shift value for LESENSE_RD */ #define _LESENSE_PTR_RD_MASK 0xFUL /**< Bit mask for LESENSE_RD */ #define _LESENSE_PTR_RD_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PTR */ #define LESENSE_PTR_RD_DEFAULT (_LESENSE_PTR_RD_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_PTR */ #define _LESENSE_PTR_WR_SHIFT 4 /**< Shift value for LESENSE_WR */ #define _LESENSE_PTR_WR_MASK 0xF0UL /**< Bit mask for LESENSE_WR */ #define _LESENSE_PTR_WR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PTR */ #define LESENSE_PTR_WR_DEFAULT (_LESENSE_PTR_WR_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_PTR */ /* Bit fields for LESENSE BUFDATA */ #define _LESENSE_BUFDATA_RESETVALUE 0x00000000UL /**< Default value for LESENSE_BUFDATA */ #define _LESENSE_BUFDATA_MASK 0x000FFFFFUL /**< Mask for LESENSE_BUFDATA */ #define _LESENSE_BUFDATA_BUFDATA_SHIFT 0 /**< Shift value for LESENSE_BUFDATA */ #define _LESENSE_BUFDATA_BUFDATA_MASK 0xFFFFUL /**< Bit mask for LESENSE_BUFDATA */ #define _LESENSE_BUFDATA_BUFDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_BUFDATA */ #define LESENSE_BUFDATA_BUFDATA_DEFAULT (_LESENSE_BUFDATA_BUFDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_BUFDATA */ #define _LESENSE_BUFDATA_BUFDATASRC_SHIFT 16 /**< Shift value for LESENSE_BUFDATASRC */ #define _LESENSE_BUFDATA_BUFDATASRC_MASK 0xF0000UL /**< Bit mask for LESENSE_BUFDATASRC */ #define _LESENSE_BUFDATA_BUFDATASRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_BUFDATA */ #define LESENSE_BUFDATA_BUFDATASRC_DEFAULT (_LESENSE_BUFDATA_BUFDATASRC_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_BUFDATA */ /* Bit fields for LESENSE CURCH */ #define _LESENSE_CURCH_RESETVALUE 0x00000000UL /**< Default value for LESENSE_CURCH */ #define _LESENSE_CURCH_MASK 0x0000000FUL /**< Mask for LESENSE_CURCH */ #define _LESENSE_CURCH_CURCH_SHIFT 0 /**< Shift value for LESENSE_CURCH */ #define _LESENSE_CURCH_CURCH_MASK 0xFUL /**< Bit mask for LESENSE_CURCH */ #define _LESENSE_CURCH_CURCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CURCH */ #define LESENSE_CURCH_CURCH_DEFAULT (_LESENSE_CURCH_CURCH_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_CURCH */ /* Bit fields for LESENSE DECSTATE */ #define _LESENSE_DECSTATE_RESETVALUE 0x00000000UL /**< Default value for LESENSE_DECSTATE */ #define _LESENSE_DECSTATE_MASK 0x0000001FUL /**< Mask for LESENSE_DECSTATE */ #define _LESENSE_DECSTATE_DECSTATE_SHIFT 0 /**< Shift value for LESENSE_DECSTATE */ #define _LESENSE_DECSTATE_DECSTATE_MASK 0x1FUL /**< Bit mask for LESENSE_DECSTATE */ #define _LESENSE_DECSTATE_DECSTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECSTATE */ #define LESENSE_DECSTATE_DECSTATE_DEFAULT (_LESENSE_DECSTATE_DECSTATE_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_DECSTATE */ /* Bit fields for LESENSE SENSORSTATE */ #define _LESENSE_SENSORSTATE_RESETVALUE 0x00000000UL /**< Default value for LESENSE_SENSORSTATE */ #define _LESENSE_SENSORSTATE_MASK 0x0000000FUL /**< Mask for LESENSE_SENSORSTATE */ #define _LESENSE_SENSORSTATE_SENSORSTATE_SHIFT 0 /**< Shift value for LESENSE_SENSORSTATE */ #define _LESENSE_SENSORSTATE_SENSORSTATE_MASK 0xFUL /**< Bit mask for LESENSE_SENSORSTATE */ #define _LESENSE_SENSORSTATE_SENSORSTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_SENSORSTATE */ #define LESENSE_SENSORSTATE_SENSORSTATE_DEFAULT (_LESENSE_SENSORSTATE_SENSORSTATE_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_SENSORSTATE */ /* Bit fields for LESENSE IDLECONF */ #define _LESENSE_IDLECONF_RESETVALUE 0x00000000UL /**< Default value for LESENSE_IDLECONF */ #define _LESENSE_IDLECONF_MASK 0xFFFFFFFFUL /**< Mask for LESENSE_IDLECONF */ #define _LESENSE_IDLECONF_CH0_SHIFT 0 /**< Shift value for LESENSE_CH0 */ #define _LESENSE_IDLECONF_CH0_MASK 0x3UL /**< Bit mask for LESENSE_CH0 */ #define _LESENSE_IDLECONF_CH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ #define _LESENSE_IDLECONF_CH0_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ #define _LESENSE_IDLECONF_CH0_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ #define _LESENSE_IDLECONF_CH0_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ #define _LESENSE_IDLECONF_CH0_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ #define LESENSE_IDLECONF_CH0_DEFAULT (_LESENSE_IDLECONF_CH0_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ #define LESENSE_IDLECONF_CH0_DISABLE (_LESENSE_IDLECONF_CH0_DISABLE << 0) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ #define LESENSE_IDLECONF_CH0_HIGH (_LESENSE_IDLECONF_CH0_HIGH << 0) /**< Shifted mode HIGH for LESENSE_IDLECONF */ #define LESENSE_IDLECONF_CH0_LOW (_LESENSE_IDLECONF_CH0_LOW << 0) /**< Shifted mode LOW for LESENSE_IDLECONF */ #define LESENSE_IDLECONF_CH0_DAC (_LESENSE_IDLECONF_CH0_DAC << 0) /**< Shifted mode DAC for LESENSE_IDLECONF */ #define _LESENSE_IDLECONF_CH1_SHIFT 2 /**< Shift value for LESENSE_CH1 */ #define _LESENSE_IDLECONF_CH1_MASK 0xCUL /**< Bit mask for LESENSE_CH1 */ #define _LESENSE_IDLECONF_CH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ #define _LESENSE_IDLECONF_CH1_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ #define _LESENSE_IDLECONF_CH1_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ #define _LESENSE_IDLECONF_CH1_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ #define _LESENSE_IDLECONF_CH1_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ #define LESENSE_IDLECONF_CH1_DEFAULT (_LESENSE_IDLECONF_CH1_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ #define LESENSE_IDLECONF_CH1_DISABLE (_LESENSE_IDLECONF_CH1_DISABLE << 2) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ #define LESENSE_IDLECONF_CH1_HIGH (_LESENSE_IDLECONF_CH1_HIGH << 2) /**< Shifted mode HIGH for LESENSE_IDLECONF */ #define LESENSE_IDLECONF_CH1_LOW (_LESENSE_IDLECONF_CH1_LOW << 2) /**< Shifted mode LOW for LESENSE_IDLECONF */ #define LESENSE_IDLECONF_CH1_DAC (_LESENSE_IDLECONF_CH1_DAC << 2) /**< Shifted mode DAC for LESENSE_IDLECONF */ #define _LESENSE_IDLECONF_CH2_SHIFT 4 /**< Shift value for LESENSE_CH2 */ #define _LESENSE_IDLECONF_CH2_MASK 0x30UL /**< Bit mask for LESENSE_CH2 */ #define _LESENSE_IDLECONF_CH2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ #define _LESENSE_IDLECONF_CH2_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ #define _LESENSE_IDLECONF_CH2_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ #define _LESENSE_IDLECONF_CH2_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ #define _LESENSE_IDLECONF_CH2_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ #define LESENSE_IDLECONF_CH2_DEFAULT (_LESENSE_IDLECONF_CH2_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ #define LESENSE_IDLECONF_CH2_DISABLE (_LESENSE_IDLECONF_CH2_DISABLE << 4) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ #define LESENSE_IDLECONF_CH2_HIGH (_LESENSE_IDLECONF_CH2_HIGH << 4) /**< Shifted mode HIGH for LESENSE_IDLECONF */ #define LESENSE_IDLECONF_CH2_LOW (_LESENSE_IDLECONF_CH2_LOW << 4) /**< Shifted mode LOW for LESENSE_IDLECONF */ #define LESENSE_IDLECONF_CH2_DAC (_LESENSE_IDLECONF_CH2_DAC << 4) /**< Shifted mode DAC for LESENSE_IDLECONF */ #define _LESENSE_IDLECONF_CH3_SHIFT 6 /**< Shift value for LESENSE_CH3 */ #define _LESENSE_IDLECONF_CH3_MASK 0xC0UL /**< Bit mask for LESENSE_CH3 */ #define _LESENSE_IDLECONF_CH3_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ #define _LESENSE_IDLECONF_CH3_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ #define _LESENSE_IDLECONF_CH3_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ #define _LESENSE_IDLECONF_CH3_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ #define _LESENSE_IDLECONF_CH3_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ #define LESENSE_IDLECONF_CH3_DEFAULT (_LESENSE_IDLECONF_CH3_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ #define LESENSE_IDLECONF_CH3_DISABLE (_LESENSE_IDLECONF_CH3_DISABLE << 6) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ #define LESENSE_IDLECONF_CH3_HIGH (_LESENSE_IDLECONF_CH3_HIGH << 6) /**< Shifted mode HIGH for LESENSE_IDLECONF */ #define LESENSE_IDLECONF_CH3_LOW (_LESENSE_IDLECONF_CH3_LOW << 6) /**< Shifted mode LOW for LESENSE_IDLECONF */ #define LESENSE_IDLECONF_CH3_DAC (_LESENSE_IDLECONF_CH3_DAC << 6) /**< Shifted mode DAC for LESENSE_IDLECONF */ #define _LESENSE_IDLECONF_CH4_SHIFT 8 /**< Shift value for LESENSE_CH4 */ #define _LESENSE_IDLECONF_CH4_MASK 0x300UL /**< Bit mask for LESENSE_CH4 */ #define _LESENSE_IDLECONF_CH4_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ #define _LESENSE_IDLECONF_CH4_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ #define _LESENSE_IDLECONF_CH4_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ #define _LESENSE_IDLECONF_CH4_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ #define _LESENSE_IDLECONF_CH4_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ #define LESENSE_IDLECONF_CH4_DEFAULT (_LESENSE_IDLECONF_CH4_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ #define LESENSE_IDLECONF_CH4_DISABLE (_LESENSE_IDLECONF_CH4_DISABLE << 8) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ #define LESENSE_IDLECONF_CH4_HIGH (_LESENSE_IDLECONF_CH4_HIGH << 8) /**< Shifted mode HIGH for LESENSE_IDLECONF */ #define LESENSE_IDLECONF_CH4_LOW (_LESENSE_IDLECONF_CH4_LOW << 8) /**< Shifted mode LOW for LESENSE_IDLECONF */ #define LESENSE_IDLECONF_CH4_DAC (_LESENSE_IDLECONF_CH4_DAC << 8) /**< Shifted mode DAC for LESENSE_IDLECONF */ #define _LESENSE_IDLECONF_CH5_SHIFT 10 /**< Shift value for LESENSE_CH5 */ #define _LESENSE_IDLECONF_CH5_MASK 0xC00UL /**< Bit mask for LESENSE_CH5 */ #define _LESENSE_IDLECONF_CH5_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ #define _LESENSE_IDLECONF_CH5_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ #define _LESENSE_IDLECONF_CH5_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ #define _LESENSE_IDLECONF_CH5_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ #define _LESENSE_IDLECONF_CH5_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ #define LESENSE_IDLECONF_CH5_DEFAULT (_LESENSE_IDLECONF_CH5_DEFAULT << 10) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ #define LESENSE_IDLECONF_CH5_DISABLE (_LESENSE_IDLECONF_CH5_DISABLE << 10) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ #define LESENSE_IDLECONF_CH5_HIGH (_LESENSE_IDLECONF_CH5_HIGH << 10) /**< Shifted mode HIGH for LESENSE_IDLECONF */ #define LESENSE_IDLECONF_CH5_LOW (_LESENSE_IDLECONF_CH5_LOW << 10) /**< Shifted mode LOW for LESENSE_IDLECONF */ #define LESENSE_IDLECONF_CH5_DAC (_LESENSE_IDLECONF_CH5_DAC << 10) /**< Shifted mode DAC for LESENSE_IDLECONF */ #define _LESENSE_IDLECONF_CH6_SHIFT 12 /**< Shift value for LESENSE_CH6 */ #define _LESENSE_IDLECONF_CH6_MASK 0x3000UL /**< Bit mask for LESENSE_CH6 */ #define _LESENSE_IDLECONF_CH6_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ #define _LESENSE_IDLECONF_CH6_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ #define _LESENSE_IDLECONF_CH6_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ #define _LESENSE_IDLECONF_CH6_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ #define _LESENSE_IDLECONF_CH6_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ #define LESENSE_IDLECONF_CH6_DEFAULT (_LESENSE_IDLECONF_CH6_DEFAULT << 12) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ #define LESENSE_IDLECONF_CH6_DISABLE (_LESENSE_IDLECONF_CH6_DISABLE << 12) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ #define LESENSE_IDLECONF_CH6_HIGH (_LESENSE_IDLECONF_CH6_HIGH << 12) /**< Shifted mode HIGH for LESENSE_IDLECONF */ #define LESENSE_IDLECONF_CH6_LOW (_LESENSE_IDLECONF_CH6_LOW << 12) /**< Shifted mode LOW for LESENSE_IDLECONF */ #define LESENSE_IDLECONF_CH6_DAC (_LESENSE_IDLECONF_CH6_DAC << 12) /**< Shifted mode DAC for LESENSE_IDLECONF */ #define _LESENSE_IDLECONF_CH7_SHIFT 14 /**< Shift value for LESENSE_CH7 */ #define _LESENSE_IDLECONF_CH7_MASK 0xC000UL /**< Bit mask for LESENSE_CH7 */ #define _LESENSE_IDLECONF_CH7_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ #define _LESENSE_IDLECONF_CH7_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ #define _LESENSE_IDLECONF_CH7_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ #define _LESENSE_IDLECONF_CH7_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ #define _LESENSE_IDLECONF_CH7_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ #define LESENSE_IDLECONF_CH7_DEFAULT (_LESENSE_IDLECONF_CH7_DEFAULT << 14) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ #define LESENSE_IDLECONF_CH7_DISABLE (_LESENSE_IDLECONF_CH7_DISABLE << 14) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ #define LESENSE_IDLECONF_CH7_HIGH (_LESENSE_IDLECONF_CH7_HIGH << 14) /**< Shifted mode HIGH for LESENSE_IDLECONF */ #define LESENSE_IDLECONF_CH7_LOW (_LESENSE_IDLECONF_CH7_LOW << 14) /**< Shifted mode LOW for LESENSE_IDLECONF */ #define LESENSE_IDLECONF_CH7_DAC (_LESENSE_IDLECONF_CH7_DAC << 14) /**< Shifted mode DAC for LESENSE_IDLECONF */ #define _LESENSE_IDLECONF_CH8_SHIFT 16 /**< Shift value for LESENSE_CH8 */ #define _LESENSE_IDLECONF_CH8_MASK 0x30000UL /**< Bit mask for LESENSE_CH8 */ #define _LESENSE_IDLECONF_CH8_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ #define _LESENSE_IDLECONF_CH8_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ #define _LESENSE_IDLECONF_CH8_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ #define _LESENSE_IDLECONF_CH8_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ #define _LESENSE_IDLECONF_CH8_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ #define LESENSE_IDLECONF_CH8_DEFAULT (_LESENSE_IDLECONF_CH8_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ #define LESENSE_IDLECONF_CH8_DISABLE (_LESENSE_IDLECONF_CH8_DISABLE << 16) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ #define LESENSE_IDLECONF_CH8_HIGH (_LESENSE_IDLECONF_CH8_HIGH << 16) /**< Shifted mode HIGH for LESENSE_IDLECONF */ #define LESENSE_IDLECONF_CH8_LOW (_LESENSE_IDLECONF_CH8_LOW << 16) /**< Shifted mode LOW for LESENSE_IDLECONF */ #define LESENSE_IDLECONF_CH8_DAC (_LESENSE_IDLECONF_CH8_DAC << 16) /**< Shifted mode DAC for LESENSE_IDLECONF */ #define _LESENSE_IDLECONF_CH9_SHIFT 18 /**< Shift value for LESENSE_CH9 */ #define _LESENSE_IDLECONF_CH9_MASK 0xC0000UL /**< Bit mask for LESENSE_CH9 */ #define _LESENSE_IDLECONF_CH9_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ #define _LESENSE_IDLECONF_CH9_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ #define _LESENSE_IDLECONF_CH9_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ #define _LESENSE_IDLECONF_CH9_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ #define _LESENSE_IDLECONF_CH9_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ #define LESENSE_IDLECONF_CH9_DEFAULT (_LESENSE_IDLECONF_CH9_DEFAULT << 18) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ #define LESENSE_IDLECONF_CH9_DISABLE (_LESENSE_IDLECONF_CH9_DISABLE << 18) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ #define LESENSE_IDLECONF_CH9_HIGH (_LESENSE_IDLECONF_CH9_HIGH << 18) /**< Shifted mode HIGH for LESENSE_IDLECONF */ #define LESENSE_IDLECONF_CH9_LOW (_LESENSE_IDLECONF_CH9_LOW << 18) /**< Shifted mode LOW for LESENSE_IDLECONF */ #define LESENSE_IDLECONF_CH9_DAC (_LESENSE_IDLECONF_CH9_DAC << 18) /**< Shifted mode DAC for LESENSE_IDLECONF */ #define _LESENSE_IDLECONF_CH10_SHIFT 20 /**< Shift value for LESENSE_CH10 */ #define _LESENSE_IDLECONF_CH10_MASK 0x300000UL /**< Bit mask for LESENSE_CH10 */ #define _LESENSE_IDLECONF_CH10_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ #define _LESENSE_IDLECONF_CH10_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ #define _LESENSE_IDLECONF_CH10_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ #define _LESENSE_IDLECONF_CH10_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ #define _LESENSE_IDLECONF_CH10_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ #define LESENSE_IDLECONF_CH10_DEFAULT (_LESENSE_IDLECONF_CH10_DEFAULT << 20) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ #define LESENSE_IDLECONF_CH10_DISABLE (_LESENSE_IDLECONF_CH10_DISABLE << 20) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ #define LESENSE_IDLECONF_CH10_HIGH (_LESENSE_IDLECONF_CH10_HIGH << 20) /**< Shifted mode HIGH for LESENSE_IDLECONF */ #define LESENSE_IDLECONF_CH10_LOW (_LESENSE_IDLECONF_CH10_LOW << 20) /**< Shifted mode LOW for LESENSE_IDLECONF */ #define LESENSE_IDLECONF_CH10_DAC (_LESENSE_IDLECONF_CH10_DAC << 20) /**< Shifted mode DAC for LESENSE_IDLECONF */ #define _LESENSE_IDLECONF_CH11_SHIFT 22 /**< Shift value for LESENSE_CH11 */ #define _LESENSE_IDLECONF_CH11_MASK 0xC00000UL /**< Bit mask for LESENSE_CH11 */ #define _LESENSE_IDLECONF_CH11_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ #define _LESENSE_IDLECONF_CH11_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ #define _LESENSE_IDLECONF_CH11_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ #define _LESENSE_IDLECONF_CH11_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ #define _LESENSE_IDLECONF_CH11_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ #define LESENSE_IDLECONF_CH11_DEFAULT (_LESENSE_IDLECONF_CH11_DEFAULT << 22) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ #define LESENSE_IDLECONF_CH11_DISABLE (_LESENSE_IDLECONF_CH11_DISABLE << 22) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ #define LESENSE_IDLECONF_CH11_HIGH (_LESENSE_IDLECONF_CH11_HIGH << 22) /**< Shifted mode HIGH for LESENSE_IDLECONF */ #define LESENSE_IDLECONF_CH11_LOW (_LESENSE_IDLECONF_CH11_LOW << 22) /**< Shifted mode LOW for LESENSE_IDLECONF */ #define LESENSE_IDLECONF_CH11_DAC (_LESENSE_IDLECONF_CH11_DAC << 22) /**< Shifted mode DAC for LESENSE_IDLECONF */ #define _LESENSE_IDLECONF_CH12_SHIFT 24 /**< Shift value for LESENSE_CH12 */ #define _LESENSE_IDLECONF_CH12_MASK 0x3000000UL /**< Bit mask for LESENSE_CH12 */ #define _LESENSE_IDLECONF_CH12_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ #define _LESENSE_IDLECONF_CH12_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ #define _LESENSE_IDLECONF_CH12_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ #define _LESENSE_IDLECONF_CH12_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ #define _LESENSE_IDLECONF_CH12_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ #define LESENSE_IDLECONF_CH12_DEFAULT (_LESENSE_IDLECONF_CH12_DEFAULT << 24) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ #define LESENSE_IDLECONF_CH12_DISABLE (_LESENSE_IDLECONF_CH12_DISABLE << 24) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ #define LESENSE_IDLECONF_CH12_HIGH (_LESENSE_IDLECONF_CH12_HIGH << 24) /**< Shifted mode HIGH for LESENSE_IDLECONF */ #define LESENSE_IDLECONF_CH12_LOW (_LESENSE_IDLECONF_CH12_LOW << 24) /**< Shifted mode LOW for LESENSE_IDLECONF */ #define LESENSE_IDLECONF_CH12_DAC (_LESENSE_IDLECONF_CH12_DAC << 24) /**< Shifted mode DAC for LESENSE_IDLECONF */ #define _LESENSE_IDLECONF_CH13_SHIFT 26 /**< Shift value for LESENSE_CH13 */ #define _LESENSE_IDLECONF_CH13_MASK 0xC000000UL /**< Bit mask for LESENSE_CH13 */ #define _LESENSE_IDLECONF_CH13_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ #define _LESENSE_IDLECONF_CH13_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ #define _LESENSE_IDLECONF_CH13_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ #define _LESENSE_IDLECONF_CH13_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ #define _LESENSE_IDLECONF_CH13_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ #define LESENSE_IDLECONF_CH13_DEFAULT (_LESENSE_IDLECONF_CH13_DEFAULT << 26) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ #define LESENSE_IDLECONF_CH13_DISABLE (_LESENSE_IDLECONF_CH13_DISABLE << 26) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ #define LESENSE_IDLECONF_CH13_HIGH (_LESENSE_IDLECONF_CH13_HIGH << 26) /**< Shifted mode HIGH for LESENSE_IDLECONF */ #define LESENSE_IDLECONF_CH13_LOW (_LESENSE_IDLECONF_CH13_LOW << 26) /**< Shifted mode LOW for LESENSE_IDLECONF */ #define LESENSE_IDLECONF_CH13_DAC (_LESENSE_IDLECONF_CH13_DAC << 26) /**< Shifted mode DAC for LESENSE_IDLECONF */ #define _LESENSE_IDLECONF_CH14_SHIFT 28 /**< Shift value for LESENSE_CH14 */ #define _LESENSE_IDLECONF_CH14_MASK 0x30000000UL /**< Bit mask for LESENSE_CH14 */ #define _LESENSE_IDLECONF_CH14_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ #define _LESENSE_IDLECONF_CH14_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ #define _LESENSE_IDLECONF_CH14_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ #define _LESENSE_IDLECONF_CH14_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ #define _LESENSE_IDLECONF_CH14_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ #define LESENSE_IDLECONF_CH14_DEFAULT (_LESENSE_IDLECONF_CH14_DEFAULT << 28) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ #define LESENSE_IDLECONF_CH14_DISABLE (_LESENSE_IDLECONF_CH14_DISABLE << 28) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ #define LESENSE_IDLECONF_CH14_HIGH (_LESENSE_IDLECONF_CH14_HIGH << 28) /**< Shifted mode HIGH for LESENSE_IDLECONF */ #define LESENSE_IDLECONF_CH14_LOW (_LESENSE_IDLECONF_CH14_LOW << 28) /**< Shifted mode LOW for LESENSE_IDLECONF */ #define LESENSE_IDLECONF_CH14_DAC (_LESENSE_IDLECONF_CH14_DAC << 28) /**< Shifted mode DAC for LESENSE_IDLECONF */ #define _LESENSE_IDLECONF_CH15_SHIFT 30 /**< Shift value for LESENSE_CH15 */ #define _LESENSE_IDLECONF_CH15_MASK 0xC0000000UL /**< Bit mask for LESENSE_CH15 */ #define _LESENSE_IDLECONF_CH15_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ #define _LESENSE_IDLECONF_CH15_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ #define _LESENSE_IDLECONF_CH15_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ #define _LESENSE_IDLECONF_CH15_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ #define _LESENSE_IDLECONF_CH15_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ #define LESENSE_IDLECONF_CH15_DEFAULT (_LESENSE_IDLECONF_CH15_DEFAULT << 30) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ #define LESENSE_IDLECONF_CH15_DISABLE (_LESENSE_IDLECONF_CH15_DISABLE << 30) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ #define LESENSE_IDLECONF_CH15_HIGH (_LESENSE_IDLECONF_CH15_HIGH << 30) /**< Shifted mode HIGH for LESENSE_IDLECONF */ #define LESENSE_IDLECONF_CH15_LOW (_LESENSE_IDLECONF_CH15_LOW << 30) /**< Shifted mode LOW for LESENSE_IDLECONF */ #define LESENSE_IDLECONF_CH15_DAC (_LESENSE_IDLECONF_CH15_DAC << 30) /**< Shifted mode DAC for LESENSE_IDLECONF */ /* Bit fields for LESENSE ALTEXCONF */ #define _LESENSE_ALTEXCONF_RESETVALUE 0x00000000UL /**< Default value for LESENSE_ALTEXCONF */ #define _LESENSE_ALTEXCONF_MASK 0x00FFFFFFUL /**< Mask for LESENSE_ALTEXCONF */ #define _LESENSE_ALTEXCONF_IDLECONF0_SHIFT 0 /**< Shift value for LESENSE_IDLECONF0 */ #define _LESENSE_ALTEXCONF_IDLECONF0_MASK 0x3UL /**< Bit mask for LESENSE_IDLECONF0 */ #define _LESENSE_ALTEXCONF_IDLECONF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */ #define _LESENSE_ALTEXCONF_IDLECONF0_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_ALTEXCONF */ #define _LESENSE_ALTEXCONF_IDLECONF0_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_ALTEXCONF */ #define _LESENSE_ALTEXCONF_IDLECONF0_LOW 0x00000002UL /**< Mode LOW for LESENSE_ALTEXCONF */ #define LESENSE_ALTEXCONF_IDLECONF0_DEFAULT (_LESENSE_ALTEXCONF_IDLECONF0_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */ #define LESENSE_ALTEXCONF_IDLECONF0_DISABLE (_LESENSE_ALTEXCONF_IDLECONF0_DISABLE << 0) /**< Shifted mode DISABLE for LESENSE_ALTEXCONF */ #define LESENSE_ALTEXCONF_IDLECONF0_HIGH (_LESENSE_ALTEXCONF_IDLECONF0_HIGH << 0) /**< Shifted mode HIGH for LESENSE_ALTEXCONF */ #define LESENSE_ALTEXCONF_IDLECONF0_LOW (_LESENSE_ALTEXCONF_IDLECONF0_LOW << 0) /**< Shifted mode LOW for LESENSE_ALTEXCONF */ #define _LESENSE_ALTEXCONF_IDLECONF1_SHIFT 2 /**< Shift value for LESENSE_IDLECONF1 */ #define _LESENSE_ALTEXCONF_IDLECONF1_MASK 0xCUL /**< Bit mask for LESENSE_IDLECONF1 */ #define _LESENSE_ALTEXCONF_IDLECONF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */ #define _LESENSE_ALTEXCONF_IDLECONF1_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_ALTEXCONF */ #define _LESENSE_ALTEXCONF_IDLECONF1_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_ALTEXCONF */ #define _LESENSE_ALTEXCONF_IDLECONF1_LOW 0x00000002UL /**< Mode LOW for LESENSE_ALTEXCONF */ #define LESENSE_ALTEXCONF_IDLECONF1_DEFAULT (_LESENSE_ALTEXCONF_IDLECONF1_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */ #define LESENSE_ALTEXCONF_IDLECONF1_DISABLE (_LESENSE_ALTEXCONF_IDLECONF1_DISABLE << 2) /**< Shifted mode DISABLE for LESENSE_ALTEXCONF */ #define LESENSE_ALTEXCONF_IDLECONF1_HIGH (_LESENSE_ALTEXCONF_IDLECONF1_HIGH << 2) /**< Shifted mode HIGH for LESENSE_ALTEXCONF */ #define LESENSE_ALTEXCONF_IDLECONF1_LOW (_LESENSE_ALTEXCONF_IDLECONF1_LOW << 2) /**< Shifted mode LOW for LESENSE_ALTEXCONF */ #define _LESENSE_ALTEXCONF_IDLECONF2_SHIFT 4 /**< Shift value for LESENSE_IDLECONF2 */ #define _LESENSE_ALTEXCONF_IDLECONF2_MASK 0x30UL /**< Bit mask for LESENSE_IDLECONF2 */ #define _LESENSE_ALTEXCONF_IDLECONF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */ #define _LESENSE_ALTEXCONF_IDLECONF2_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_ALTEXCONF */ #define _LESENSE_ALTEXCONF_IDLECONF2_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_ALTEXCONF */ #define _LESENSE_ALTEXCONF_IDLECONF2_LOW 0x00000002UL /**< Mode LOW for LESENSE_ALTEXCONF */ #define LESENSE_ALTEXCONF_IDLECONF2_DEFAULT (_LESENSE_ALTEXCONF_IDLECONF2_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */ #define LESENSE_ALTEXCONF_IDLECONF2_DISABLE (_LESENSE_ALTEXCONF_IDLECONF2_DISABLE << 4) /**< Shifted mode DISABLE for LESENSE_ALTEXCONF */ #define LESENSE_ALTEXCONF_IDLECONF2_HIGH (_LESENSE_ALTEXCONF_IDLECONF2_HIGH << 4) /**< Shifted mode HIGH for LESENSE_ALTEXCONF */ #define LESENSE_ALTEXCONF_IDLECONF2_LOW (_LESENSE_ALTEXCONF_IDLECONF2_LOW << 4) /**< Shifted mode LOW for LESENSE_ALTEXCONF */ #define _LESENSE_ALTEXCONF_IDLECONF3_SHIFT 6 /**< Shift value for LESENSE_IDLECONF3 */ #define _LESENSE_ALTEXCONF_IDLECONF3_MASK 0xC0UL /**< Bit mask for LESENSE_IDLECONF3 */ #define _LESENSE_ALTEXCONF_IDLECONF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */ #define _LESENSE_ALTEXCONF_IDLECONF3_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_ALTEXCONF */ #define _LESENSE_ALTEXCONF_IDLECONF3_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_ALTEXCONF */ #define _LESENSE_ALTEXCONF_IDLECONF3_LOW 0x00000002UL /**< Mode LOW for LESENSE_ALTEXCONF */ #define LESENSE_ALTEXCONF_IDLECONF3_DEFAULT (_LESENSE_ALTEXCONF_IDLECONF3_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */ #define LESENSE_ALTEXCONF_IDLECONF3_DISABLE (_LESENSE_ALTEXCONF_IDLECONF3_DISABLE << 6) /**< Shifted mode DISABLE for LESENSE_ALTEXCONF */ #define LESENSE_ALTEXCONF_IDLECONF3_HIGH (_LESENSE_ALTEXCONF_IDLECONF3_HIGH << 6) /**< Shifted mode HIGH for LESENSE_ALTEXCONF */ #define LESENSE_ALTEXCONF_IDLECONF3_LOW (_LESENSE_ALTEXCONF_IDLECONF3_LOW << 6) /**< Shifted mode LOW for LESENSE_ALTEXCONF */ #define _LESENSE_ALTEXCONF_IDLECONF4_SHIFT 8 /**< Shift value for LESENSE_IDLECONF4 */ #define _LESENSE_ALTEXCONF_IDLECONF4_MASK 0x300UL /**< Bit mask for LESENSE_IDLECONF4 */ #define _LESENSE_ALTEXCONF_IDLECONF4_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */ #define _LESENSE_ALTEXCONF_IDLECONF4_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_ALTEXCONF */ #define _LESENSE_ALTEXCONF_IDLECONF4_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_ALTEXCONF */ #define _LESENSE_ALTEXCONF_IDLECONF4_LOW 0x00000002UL /**< Mode LOW for LESENSE_ALTEXCONF */ #define LESENSE_ALTEXCONF_IDLECONF4_DEFAULT (_LESENSE_ALTEXCONF_IDLECONF4_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */ #define LESENSE_ALTEXCONF_IDLECONF4_DISABLE (_LESENSE_ALTEXCONF_IDLECONF4_DISABLE << 8) /**< Shifted mode DISABLE for LESENSE_ALTEXCONF */ #define LESENSE_ALTEXCONF_IDLECONF4_HIGH (_LESENSE_ALTEXCONF_IDLECONF4_HIGH << 8) /**< Shifted mode HIGH for LESENSE_ALTEXCONF */ #define LESENSE_ALTEXCONF_IDLECONF4_LOW (_LESENSE_ALTEXCONF_IDLECONF4_LOW << 8) /**< Shifted mode LOW for LESENSE_ALTEXCONF */ #define _LESENSE_ALTEXCONF_IDLECONF5_SHIFT 10 /**< Shift value for LESENSE_IDLECONF5 */ #define _LESENSE_ALTEXCONF_IDLECONF5_MASK 0xC00UL /**< Bit mask for LESENSE_IDLECONF5 */ #define _LESENSE_ALTEXCONF_IDLECONF5_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */ #define _LESENSE_ALTEXCONF_IDLECONF5_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_ALTEXCONF */ #define _LESENSE_ALTEXCONF_IDLECONF5_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_ALTEXCONF */ #define _LESENSE_ALTEXCONF_IDLECONF5_LOW 0x00000002UL /**< Mode LOW for LESENSE_ALTEXCONF */ #define LESENSE_ALTEXCONF_IDLECONF5_DEFAULT (_LESENSE_ALTEXCONF_IDLECONF5_DEFAULT << 10) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */ #define LESENSE_ALTEXCONF_IDLECONF5_DISABLE (_LESENSE_ALTEXCONF_IDLECONF5_DISABLE << 10) /**< Shifted mode DISABLE for LESENSE_ALTEXCONF */ #define LESENSE_ALTEXCONF_IDLECONF5_HIGH (_LESENSE_ALTEXCONF_IDLECONF5_HIGH << 10) /**< Shifted mode HIGH for LESENSE_ALTEXCONF */ #define LESENSE_ALTEXCONF_IDLECONF5_LOW (_LESENSE_ALTEXCONF_IDLECONF5_LOW << 10) /**< Shifted mode LOW for LESENSE_ALTEXCONF */ #define _LESENSE_ALTEXCONF_IDLECONF6_SHIFT 12 /**< Shift value for LESENSE_IDLECONF6 */ #define _LESENSE_ALTEXCONF_IDLECONF6_MASK 0x3000UL /**< Bit mask for LESENSE_IDLECONF6 */ #define _LESENSE_ALTEXCONF_IDLECONF6_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */ #define _LESENSE_ALTEXCONF_IDLECONF6_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_ALTEXCONF */ #define _LESENSE_ALTEXCONF_IDLECONF6_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_ALTEXCONF */ #define _LESENSE_ALTEXCONF_IDLECONF6_LOW 0x00000002UL /**< Mode LOW for LESENSE_ALTEXCONF */ #define LESENSE_ALTEXCONF_IDLECONF6_DEFAULT (_LESENSE_ALTEXCONF_IDLECONF6_DEFAULT << 12) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */ #define LESENSE_ALTEXCONF_IDLECONF6_DISABLE (_LESENSE_ALTEXCONF_IDLECONF6_DISABLE << 12) /**< Shifted mode DISABLE for LESENSE_ALTEXCONF */ #define LESENSE_ALTEXCONF_IDLECONF6_HIGH (_LESENSE_ALTEXCONF_IDLECONF6_HIGH << 12) /**< Shifted mode HIGH for LESENSE_ALTEXCONF */ #define LESENSE_ALTEXCONF_IDLECONF6_LOW (_LESENSE_ALTEXCONF_IDLECONF6_LOW << 12) /**< Shifted mode LOW for LESENSE_ALTEXCONF */ #define _LESENSE_ALTEXCONF_IDLECONF7_SHIFT 14 /**< Shift value for LESENSE_IDLECONF7 */ #define _LESENSE_ALTEXCONF_IDLECONF7_MASK 0xC000UL /**< Bit mask for LESENSE_IDLECONF7 */ #define _LESENSE_ALTEXCONF_IDLECONF7_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */ #define _LESENSE_ALTEXCONF_IDLECONF7_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_ALTEXCONF */ #define _LESENSE_ALTEXCONF_IDLECONF7_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_ALTEXCONF */ #define _LESENSE_ALTEXCONF_IDLECONF7_LOW 0x00000002UL /**< Mode LOW for LESENSE_ALTEXCONF */ #define LESENSE_ALTEXCONF_IDLECONF7_DEFAULT (_LESENSE_ALTEXCONF_IDLECONF7_DEFAULT << 14) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */ #define LESENSE_ALTEXCONF_IDLECONF7_DISABLE (_LESENSE_ALTEXCONF_IDLECONF7_DISABLE << 14) /**< Shifted mode DISABLE for LESENSE_ALTEXCONF */ #define LESENSE_ALTEXCONF_IDLECONF7_HIGH (_LESENSE_ALTEXCONF_IDLECONF7_HIGH << 14) /**< Shifted mode HIGH for LESENSE_ALTEXCONF */ #define LESENSE_ALTEXCONF_IDLECONF7_LOW (_LESENSE_ALTEXCONF_IDLECONF7_LOW << 14) /**< Shifted mode LOW for LESENSE_ALTEXCONF */ #define LESENSE_ALTEXCONF_AEX0 (0x1UL << 16) /**< ALTEX0 Always Excite Enable */ #define _LESENSE_ALTEXCONF_AEX0_SHIFT 16 /**< Shift value for LESENSE_AEX0 */ #define _LESENSE_ALTEXCONF_AEX0_MASK 0x10000UL /**< Bit mask for LESENSE_AEX0 */ #define _LESENSE_ALTEXCONF_AEX0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */ #define LESENSE_ALTEXCONF_AEX0_DEFAULT (_LESENSE_ALTEXCONF_AEX0_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */ #define LESENSE_ALTEXCONF_AEX1 (0x1UL << 17) /**< ALTEX1 Always Excite Enable */ #define _LESENSE_ALTEXCONF_AEX1_SHIFT 17 /**< Shift value for LESENSE_AEX1 */ #define _LESENSE_ALTEXCONF_AEX1_MASK 0x20000UL /**< Bit mask for LESENSE_AEX1 */ #define _LESENSE_ALTEXCONF_AEX1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */ #define LESENSE_ALTEXCONF_AEX1_DEFAULT (_LESENSE_ALTEXCONF_AEX1_DEFAULT << 17) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */ #define LESENSE_ALTEXCONF_AEX2 (0x1UL << 18) /**< ALTEX2 Always Excite Enable */ #define _LESENSE_ALTEXCONF_AEX2_SHIFT 18 /**< Shift value for LESENSE_AEX2 */ #define _LESENSE_ALTEXCONF_AEX2_MASK 0x40000UL /**< Bit mask for LESENSE_AEX2 */ #define _LESENSE_ALTEXCONF_AEX2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */ #define LESENSE_ALTEXCONF_AEX2_DEFAULT (_LESENSE_ALTEXCONF_AEX2_DEFAULT << 18) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */ #define LESENSE_ALTEXCONF_AEX3 (0x1UL << 19) /**< ALTEX3 Always Excite Enable */ #define _LESENSE_ALTEXCONF_AEX3_SHIFT 19 /**< Shift value for LESENSE_AEX3 */ #define _LESENSE_ALTEXCONF_AEX3_MASK 0x80000UL /**< Bit mask for LESENSE_AEX3 */ #define _LESENSE_ALTEXCONF_AEX3_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */ #define LESENSE_ALTEXCONF_AEX3_DEFAULT (_LESENSE_ALTEXCONF_AEX3_DEFAULT << 19) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */ #define LESENSE_ALTEXCONF_AEX4 (0x1UL << 20) /**< ALTEX4 Always Excite Enable */ #define _LESENSE_ALTEXCONF_AEX4_SHIFT 20 /**< Shift value for LESENSE_AEX4 */ #define _LESENSE_ALTEXCONF_AEX4_MASK 0x100000UL /**< Bit mask for LESENSE_AEX4 */ #define _LESENSE_ALTEXCONF_AEX4_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */ #define LESENSE_ALTEXCONF_AEX4_DEFAULT (_LESENSE_ALTEXCONF_AEX4_DEFAULT << 20) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */ #define LESENSE_ALTEXCONF_AEX5 (0x1UL << 21) /**< ALTEX5 Always Excite Enable */ #define _LESENSE_ALTEXCONF_AEX5_SHIFT 21 /**< Shift value for LESENSE_AEX5 */ #define _LESENSE_ALTEXCONF_AEX5_MASK 0x200000UL /**< Bit mask for LESENSE_AEX5 */ #define _LESENSE_ALTEXCONF_AEX5_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */ #define LESENSE_ALTEXCONF_AEX5_DEFAULT (_LESENSE_ALTEXCONF_AEX5_DEFAULT << 21) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */ #define LESENSE_ALTEXCONF_AEX6 (0x1UL << 22) /**< ALTEX6 Always Excite Enable */ #define _LESENSE_ALTEXCONF_AEX6_SHIFT 22 /**< Shift value for LESENSE_AEX6 */ #define _LESENSE_ALTEXCONF_AEX6_MASK 0x400000UL /**< Bit mask for LESENSE_AEX6 */ #define _LESENSE_ALTEXCONF_AEX6_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */ #define LESENSE_ALTEXCONF_AEX6_DEFAULT (_LESENSE_ALTEXCONF_AEX6_DEFAULT << 22) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */ #define LESENSE_ALTEXCONF_AEX7 (0x1UL << 23) /**< ALTEX7 Always Excite Enable */ #define _LESENSE_ALTEXCONF_AEX7_SHIFT 23 /**< Shift value for LESENSE_AEX7 */ #define _LESENSE_ALTEXCONF_AEX7_MASK 0x800000UL /**< Bit mask for LESENSE_AEX7 */ #define _LESENSE_ALTEXCONF_AEX7_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */ #define LESENSE_ALTEXCONF_AEX7_DEFAULT (_LESENSE_ALTEXCONF_AEX7_DEFAULT << 23) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */ /* Bit fields for LESENSE IF */ #define _LESENSE_IF_RESETVALUE 0x00000000UL /**< Default value for LESENSE_IF */ #define _LESENSE_IF_MASK 0x007FFFFFUL /**< Mask for LESENSE_IF */ #define LESENSE_IF_CH0 (0x1UL << 0) /**< CH0 Interrupt Flag */ #define _LESENSE_IF_CH0_SHIFT 0 /**< Shift value for LESENSE_CH0 */ #define _LESENSE_IF_CH0_MASK 0x1UL /**< Bit mask for LESENSE_CH0 */ #define _LESENSE_IF_CH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ #define LESENSE_IF_CH0_DEFAULT (_LESENSE_IF_CH0_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_IF */ #define LESENSE_IF_CH1 (0x1UL << 1) /**< CH1 Interrupt Flag */ #define _LESENSE_IF_CH1_SHIFT 1 /**< Shift value for LESENSE_CH1 */ #define _LESENSE_IF_CH1_MASK 0x2UL /**< Bit mask for LESENSE_CH1 */ #define _LESENSE_IF_CH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ #define LESENSE_IF_CH1_DEFAULT (_LESENSE_IF_CH1_DEFAULT << 1) /**< Shifted mode DEFAULT for LESENSE_IF */ #define LESENSE_IF_CH2 (0x1UL << 2) /**< CH2 Interrupt Flag */ #define _LESENSE_IF_CH2_SHIFT 2 /**< Shift value for LESENSE_CH2 */ #define _LESENSE_IF_CH2_MASK 0x4UL /**< Bit mask for LESENSE_CH2 */ #define _LESENSE_IF_CH2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ #define LESENSE_IF_CH2_DEFAULT (_LESENSE_IF_CH2_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_IF */ #define LESENSE_IF_CH3 (0x1UL << 3) /**< CH3 Interrupt Flag */ #define _LESENSE_IF_CH3_SHIFT 3 /**< Shift value for LESENSE_CH3 */ #define _LESENSE_IF_CH3_MASK 0x8UL /**< Bit mask for LESENSE_CH3 */ #define _LESENSE_IF_CH3_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ #define LESENSE_IF_CH3_DEFAULT (_LESENSE_IF_CH3_DEFAULT << 3) /**< Shifted mode DEFAULT for LESENSE_IF */ #define LESENSE_IF_CH4 (0x1UL << 4) /**< CH4 Interrupt Flag */ #define _LESENSE_IF_CH4_SHIFT 4 /**< Shift value for LESENSE_CH4 */ #define _LESENSE_IF_CH4_MASK 0x10UL /**< Bit mask for LESENSE_CH4 */ #define _LESENSE_IF_CH4_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ #define LESENSE_IF_CH4_DEFAULT (_LESENSE_IF_CH4_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_IF */ #define LESENSE_IF_CH5 (0x1UL << 5) /**< CH5 Interrupt Flag */ #define _LESENSE_IF_CH5_SHIFT 5 /**< Shift value for LESENSE_CH5 */ #define _LESENSE_IF_CH5_MASK 0x20UL /**< Bit mask for LESENSE_CH5 */ #define _LESENSE_IF_CH5_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ #define LESENSE_IF_CH5_DEFAULT (_LESENSE_IF_CH5_DEFAULT << 5) /**< Shifted mode DEFAULT for LESENSE_IF */ #define LESENSE_IF_CH6 (0x1UL << 6) /**< CH6 Interrupt Flag */ #define _LESENSE_IF_CH6_SHIFT 6 /**< Shift value for LESENSE_CH6 */ #define _LESENSE_IF_CH6_MASK 0x40UL /**< Bit mask for LESENSE_CH6 */ #define _LESENSE_IF_CH6_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ #define LESENSE_IF_CH6_DEFAULT (_LESENSE_IF_CH6_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_IF */ #define LESENSE_IF_CH7 (0x1UL << 7) /**< CH7 Interrupt Flag */ #define _LESENSE_IF_CH7_SHIFT 7 /**< Shift value for LESENSE_CH7 */ #define _LESENSE_IF_CH7_MASK 0x80UL /**< Bit mask for LESENSE_CH7 */ #define _LESENSE_IF_CH7_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ #define LESENSE_IF_CH7_DEFAULT (_LESENSE_IF_CH7_DEFAULT << 7) /**< Shifted mode DEFAULT for LESENSE_IF */ #define LESENSE_IF_CH8 (0x1UL << 8) /**< CH8 Interrupt Flag */ #define _LESENSE_IF_CH8_SHIFT 8 /**< Shift value for LESENSE_CH8 */ #define _LESENSE_IF_CH8_MASK 0x100UL /**< Bit mask for LESENSE_CH8 */ #define _LESENSE_IF_CH8_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ #define LESENSE_IF_CH8_DEFAULT (_LESENSE_IF_CH8_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_IF */ #define LESENSE_IF_CH9 (0x1UL << 9) /**< CH9 Interrupt Flag */ #define _LESENSE_IF_CH9_SHIFT 9 /**< Shift value for LESENSE_CH9 */ #define _LESENSE_IF_CH9_MASK 0x200UL /**< Bit mask for LESENSE_CH9 */ #define _LESENSE_IF_CH9_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ #define LESENSE_IF_CH9_DEFAULT (_LESENSE_IF_CH9_DEFAULT << 9) /**< Shifted mode DEFAULT for LESENSE_IF */ #define LESENSE_IF_CH10 (0x1UL << 10) /**< CH10 Interrupt Flag */ #define _LESENSE_IF_CH10_SHIFT 10 /**< Shift value for LESENSE_CH10 */ #define _LESENSE_IF_CH10_MASK 0x400UL /**< Bit mask for LESENSE_CH10 */ #define _LESENSE_IF_CH10_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ #define LESENSE_IF_CH10_DEFAULT (_LESENSE_IF_CH10_DEFAULT << 10) /**< Shifted mode DEFAULT for LESENSE_IF */ #define LESENSE_IF_CH11 (0x1UL << 11) /**< CH11 Interrupt Flag */ #define _LESENSE_IF_CH11_SHIFT 11 /**< Shift value for LESENSE_CH11 */ #define _LESENSE_IF_CH11_MASK 0x800UL /**< Bit mask for LESENSE_CH11 */ #define _LESENSE_IF_CH11_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ #define LESENSE_IF_CH11_DEFAULT (_LESENSE_IF_CH11_DEFAULT << 11) /**< Shifted mode DEFAULT for LESENSE_IF */ #define LESENSE_IF_CH12 (0x1UL << 12) /**< CH12 Interrupt Flag */ #define _LESENSE_IF_CH12_SHIFT 12 /**< Shift value for LESENSE_CH12 */ #define _LESENSE_IF_CH12_MASK 0x1000UL /**< Bit mask for LESENSE_CH12 */ #define _LESENSE_IF_CH12_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ #define LESENSE_IF_CH12_DEFAULT (_LESENSE_IF_CH12_DEFAULT << 12) /**< Shifted mode DEFAULT for LESENSE_IF */ #define LESENSE_IF_CH13 (0x1UL << 13) /**< CH13 Interrupt Flag */ #define _LESENSE_IF_CH13_SHIFT 13 /**< Shift value for LESENSE_CH13 */ #define _LESENSE_IF_CH13_MASK 0x2000UL /**< Bit mask for LESENSE_CH13 */ #define _LESENSE_IF_CH13_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ #define LESENSE_IF_CH13_DEFAULT (_LESENSE_IF_CH13_DEFAULT << 13) /**< Shifted mode DEFAULT for LESENSE_IF */ #define LESENSE_IF_CH14 (0x1UL << 14) /**< CH14 Interrupt Flag */ #define _LESENSE_IF_CH14_SHIFT 14 /**< Shift value for LESENSE_CH14 */ #define _LESENSE_IF_CH14_MASK 0x4000UL /**< Bit mask for LESENSE_CH14 */ #define _LESENSE_IF_CH14_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ #define LESENSE_IF_CH14_DEFAULT (_LESENSE_IF_CH14_DEFAULT << 14) /**< Shifted mode DEFAULT for LESENSE_IF */ #define LESENSE_IF_CH15 (0x1UL << 15) /**< CH15 Interrupt Flag */ #define _LESENSE_IF_CH15_SHIFT 15 /**< Shift value for LESENSE_CH15 */ #define _LESENSE_IF_CH15_MASK 0x8000UL /**< Bit mask for LESENSE_CH15 */ #define _LESENSE_IF_CH15_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ #define LESENSE_IF_CH15_DEFAULT (_LESENSE_IF_CH15_DEFAULT << 15) /**< Shifted mode DEFAULT for LESENSE_IF */ #define LESENSE_IF_SCANCOMPLETE (0x1UL << 16) /**< SCANCOMPLETE Interrupt Flag */ #define _LESENSE_IF_SCANCOMPLETE_SHIFT 16 /**< Shift value for LESENSE_SCANCOMPLETE */ #define _LESENSE_IF_SCANCOMPLETE_MASK 0x10000UL /**< Bit mask for LESENSE_SCANCOMPLETE */ #define _LESENSE_IF_SCANCOMPLETE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ #define LESENSE_IF_SCANCOMPLETE_DEFAULT (_LESENSE_IF_SCANCOMPLETE_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_IF */ #define LESENSE_IF_DEC (0x1UL << 17) /**< DEC Interrupt Flag */ #define _LESENSE_IF_DEC_SHIFT 17 /**< Shift value for LESENSE_DEC */ #define _LESENSE_IF_DEC_MASK 0x20000UL /**< Bit mask for LESENSE_DEC */ #define _LESENSE_IF_DEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ #define LESENSE_IF_DEC_DEFAULT (_LESENSE_IF_DEC_DEFAULT << 17) /**< Shifted mode DEFAULT for LESENSE_IF */ #define LESENSE_IF_DECERR (0x1UL << 18) /**< DECERR Interrupt Flag */ #define _LESENSE_IF_DECERR_SHIFT 18 /**< Shift value for LESENSE_DECERR */ #define _LESENSE_IF_DECERR_MASK 0x40000UL /**< Bit mask for LESENSE_DECERR */ #define _LESENSE_IF_DECERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ #define LESENSE_IF_DECERR_DEFAULT (_LESENSE_IF_DECERR_DEFAULT << 18) /**< Shifted mode DEFAULT for LESENSE_IF */ #define LESENSE_IF_BUFDATAV (0x1UL << 19) /**< BUFDATAV Interrupt Flag */ #define _LESENSE_IF_BUFDATAV_SHIFT 19 /**< Shift value for LESENSE_BUFDATAV */ #define _LESENSE_IF_BUFDATAV_MASK 0x80000UL /**< Bit mask for LESENSE_BUFDATAV */ #define _LESENSE_IF_BUFDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ #define LESENSE_IF_BUFDATAV_DEFAULT (_LESENSE_IF_BUFDATAV_DEFAULT << 19) /**< Shifted mode DEFAULT for LESENSE_IF */ #define LESENSE_IF_BUFLEVEL (0x1UL << 20) /**< BUFLEVEL Interrupt Flag */ #define _LESENSE_IF_BUFLEVEL_SHIFT 20 /**< Shift value for LESENSE_BUFLEVEL */ #define _LESENSE_IF_BUFLEVEL_MASK 0x100000UL /**< Bit mask for LESENSE_BUFLEVEL */ #define _LESENSE_IF_BUFLEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ #define LESENSE_IF_BUFLEVEL_DEFAULT (_LESENSE_IF_BUFLEVEL_DEFAULT << 20) /**< Shifted mode DEFAULT for LESENSE_IF */ #define LESENSE_IF_BUFOF (0x1UL << 21) /**< BUFOF Interrupt Flag */ #define _LESENSE_IF_BUFOF_SHIFT 21 /**< Shift value for LESENSE_BUFOF */ #define _LESENSE_IF_BUFOF_MASK 0x200000UL /**< Bit mask for LESENSE_BUFOF */ #define _LESENSE_IF_BUFOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ #define LESENSE_IF_BUFOF_DEFAULT (_LESENSE_IF_BUFOF_DEFAULT << 21) /**< Shifted mode DEFAULT for LESENSE_IF */ #define LESENSE_IF_CNTOF (0x1UL << 22) /**< CNTOF Interrupt Flag */ #define _LESENSE_IF_CNTOF_SHIFT 22 /**< Shift value for LESENSE_CNTOF */ #define _LESENSE_IF_CNTOF_MASK 0x400000UL /**< Bit mask for LESENSE_CNTOF */ #define _LESENSE_IF_CNTOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ #define LESENSE_IF_CNTOF_DEFAULT (_LESENSE_IF_CNTOF_DEFAULT << 22) /**< Shifted mode DEFAULT for LESENSE_IF */ /* Bit fields for LESENSE IFS */ #define _LESENSE_IFS_RESETVALUE 0x00000000UL /**< Default value for LESENSE_IFS */ #define _LESENSE_IFS_MASK 0x007FFFFFUL /**< Mask for LESENSE_IFS */ #define LESENSE_IFS_CH0 (0x1UL << 0) /**< Set CH0 Interrupt Flag */ #define _LESENSE_IFS_CH0_SHIFT 0 /**< Shift value for LESENSE_CH0 */ #define _LESENSE_IFS_CH0_MASK 0x1UL /**< Bit mask for LESENSE_CH0 */ #define _LESENSE_IFS_CH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ #define LESENSE_IFS_CH0_DEFAULT (_LESENSE_IFS_CH0_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_IFS */ #define LESENSE_IFS_CH1 (0x1UL << 1) /**< Set CH1 Interrupt Flag */ #define _LESENSE_IFS_CH1_SHIFT 1 /**< Shift value for LESENSE_CH1 */ #define _LESENSE_IFS_CH1_MASK 0x2UL /**< Bit mask for LESENSE_CH1 */ #define _LESENSE_IFS_CH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ #define LESENSE_IFS_CH1_DEFAULT (_LESENSE_IFS_CH1_DEFAULT << 1) /**< Shifted mode DEFAULT for LESENSE_IFS */ #define LESENSE_IFS_CH2 (0x1UL << 2) /**< Set CH2 Interrupt Flag */ #define _LESENSE_IFS_CH2_SHIFT 2 /**< Shift value for LESENSE_CH2 */ #define _LESENSE_IFS_CH2_MASK 0x4UL /**< Bit mask for LESENSE_CH2 */ #define _LESENSE_IFS_CH2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ #define LESENSE_IFS_CH2_DEFAULT (_LESENSE_IFS_CH2_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_IFS */ #define LESENSE_IFS_CH3 (0x1UL << 3) /**< Set CH3 Interrupt Flag */ #define _LESENSE_IFS_CH3_SHIFT 3 /**< Shift value for LESENSE_CH3 */ #define _LESENSE_IFS_CH3_MASK 0x8UL /**< Bit mask for LESENSE_CH3 */ #define _LESENSE_IFS_CH3_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ #define LESENSE_IFS_CH3_DEFAULT (_LESENSE_IFS_CH3_DEFAULT << 3) /**< Shifted mode DEFAULT for LESENSE_IFS */ #define LESENSE_IFS_CH4 (0x1UL << 4) /**< Set CH4 Interrupt Flag */ #define _LESENSE_IFS_CH4_SHIFT 4 /**< Shift value for LESENSE_CH4 */ #define _LESENSE_IFS_CH4_MASK 0x10UL /**< Bit mask for LESENSE_CH4 */ #define _LESENSE_IFS_CH4_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ #define LESENSE_IFS_CH4_DEFAULT (_LESENSE_IFS_CH4_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_IFS */ #define LESENSE_IFS_CH5 (0x1UL << 5) /**< Set CH5 Interrupt Flag */ #define _LESENSE_IFS_CH5_SHIFT 5 /**< Shift value for LESENSE_CH5 */ #define _LESENSE_IFS_CH5_MASK 0x20UL /**< Bit mask for LESENSE_CH5 */ #define _LESENSE_IFS_CH5_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ #define LESENSE_IFS_CH5_DEFAULT (_LESENSE_IFS_CH5_DEFAULT << 5) /**< Shifted mode DEFAULT for LESENSE_IFS */ #define LESENSE_IFS_CH6 (0x1UL << 6) /**< Set CH6 Interrupt Flag */ #define _LESENSE_IFS_CH6_SHIFT 6 /**< Shift value for LESENSE_CH6 */ #define _LESENSE_IFS_CH6_MASK 0x40UL /**< Bit mask for LESENSE_CH6 */ #define _LESENSE_IFS_CH6_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ #define LESENSE_IFS_CH6_DEFAULT (_LESENSE_IFS_CH6_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_IFS */ #define LESENSE_IFS_CH7 (0x1UL << 7) /**< Set CH7 Interrupt Flag */ #define _LESENSE_IFS_CH7_SHIFT 7 /**< Shift value for LESENSE_CH7 */ #define _LESENSE_IFS_CH7_MASK 0x80UL /**< Bit mask for LESENSE_CH7 */ #define _LESENSE_IFS_CH7_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ #define LESENSE_IFS_CH7_DEFAULT (_LESENSE_IFS_CH7_DEFAULT << 7) /**< Shifted mode DEFAULT for LESENSE_IFS */ #define LESENSE_IFS_CH8 (0x1UL << 8) /**< Set CH8 Interrupt Flag */ #define _LESENSE_IFS_CH8_SHIFT 8 /**< Shift value for LESENSE_CH8 */ #define _LESENSE_IFS_CH8_MASK 0x100UL /**< Bit mask for LESENSE_CH8 */ #define _LESENSE_IFS_CH8_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ #define LESENSE_IFS_CH8_DEFAULT (_LESENSE_IFS_CH8_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_IFS */ #define LESENSE_IFS_CH9 (0x1UL << 9) /**< Set CH9 Interrupt Flag */ #define _LESENSE_IFS_CH9_SHIFT 9 /**< Shift value for LESENSE_CH9 */ #define _LESENSE_IFS_CH9_MASK 0x200UL /**< Bit mask for LESENSE_CH9 */ #define _LESENSE_IFS_CH9_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ #define LESENSE_IFS_CH9_DEFAULT (_LESENSE_IFS_CH9_DEFAULT << 9) /**< Shifted mode DEFAULT for LESENSE_IFS */ #define LESENSE_IFS_CH10 (0x1UL << 10) /**< Set CH10 Interrupt Flag */ #define _LESENSE_IFS_CH10_SHIFT 10 /**< Shift value for LESENSE_CH10 */ #define _LESENSE_IFS_CH10_MASK 0x400UL /**< Bit mask for LESENSE_CH10 */ #define _LESENSE_IFS_CH10_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ #define LESENSE_IFS_CH10_DEFAULT (_LESENSE_IFS_CH10_DEFAULT << 10) /**< Shifted mode DEFAULT for LESENSE_IFS */ #define LESENSE_IFS_CH11 (0x1UL << 11) /**< Set CH11 Interrupt Flag */ #define _LESENSE_IFS_CH11_SHIFT 11 /**< Shift value for LESENSE_CH11 */ #define _LESENSE_IFS_CH11_MASK 0x800UL /**< Bit mask for LESENSE_CH11 */ #define _LESENSE_IFS_CH11_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ #define LESENSE_IFS_CH11_DEFAULT (_LESENSE_IFS_CH11_DEFAULT << 11) /**< Shifted mode DEFAULT for LESENSE_IFS */ #define LESENSE_IFS_CH12 (0x1UL << 12) /**< Set CH12 Interrupt Flag */ #define _LESENSE_IFS_CH12_SHIFT 12 /**< Shift value for LESENSE_CH12 */ #define _LESENSE_IFS_CH12_MASK 0x1000UL /**< Bit mask for LESENSE_CH12 */ #define _LESENSE_IFS_CH12_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ #define LESENSE_IFS_CH12_DEFAULT (_LESENSE_IFS_CH12_DEFAULT << 12) /**< Shifted mode DEFAULT for LESENSE_IFS */ #define LESENSE_IFS_CH13 (0x1UL << 13) /**< Set CH13 Interrupt Flag */ #define _LESENSE_IFS_CH13_SHIFT 13 /**< Shift value for LESENSE_CH13 */ #define _LESENSE_IFS_CH13_MASK 0x2000UL /**< Bit mask for LESENSE_CH13 */ #define _LESENSE_IFS_CH13_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ #define LESENSE_IFS_CH13_DEFAULT (_LESENSE_IFS_CH13_DEFAULT << 13) /**< Shifted mode DEFAULT for LESENSE_IFS */ #define LESENSE_IFS_CH14 (0x1UL << 14) /**< Set CH14 Interrupt Flag */ #define _LESENSE_IFS_CH14_SHIFT 14 /**< Shift value for LESENSE_CH14 */ #define _LESENSE_IFS_CH14_MASK 0x4000UL /**< Bit mask for LESENSE_CH14 */ #define _LESENSE_IFS_CH14_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ #define LESENSE_IFS_CH14_DEFAULT (_LESENSE_IFS_CH14_DEFAULT << 14) /**< Shifted mode DEFAULT for LESENSE_IFS */ #define LESENSE_IFS_CH15 (0x1UL << 15) /**< Set CH15 Interrupt Flag */ #define _LESENSE_IFS_CH15_SHIFT 15 /**< Shift value for LESENSE_CH15 */ #define _LESENSE_IFS_CH15_MASK 0x8000UL /**< Bit mask for LESENSE_CH15 */ #define _LESENSE_IFS_CH15_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ #define LESENSE_IFS_CH15_DEFAULT (_LESENSE_IFS_CH15_DEFAULT << 15) /**< Shifted mode DEFAULT for LESENSE_IFS */ #define LESENSE_IFS_SCANCOMPLETE (0x1UL << 16) /**< Set SCANCOMPLETE Interrupt Flag */ #define _LESENSE_IFS_SCANCOMPLETE_SHIFT 16 /**< Shift value for LESENSE_SCANCOMPLETE */ #define _LESENSE_IFS_SCANCOMPLETE_MASK 0x10000UL /**< Bit mask for LESENSE_SCANCOMPLETE */ #define _LESENSE_IFS_SCANCOMPLETE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ #define LESENSE_IFS_SCANCOMPLETE_DEFAULT (_LESENSE_IFS_SCANCOMPLETE_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_IFS */ #define LESENSE_IFS_DEC (0x1UL << 17) /**< Set DEC Interrupt Flag */ #define _LESENSE_IFS_DEC_SHIFT 17 /**< Shift value for LESENSE_DEC */ #define _LESENSE_IFS_DEC_MASK 0x20000UL /**< Bit mask for LESENSE_DEC */ #define _LESENSE_IFS_DEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ #define LESENSE_IFS_DEC_DEFAULT (_LESENSE_IFS_DEC_DEFAULT << 17) /**< Shifted mode DEFAULT for LESENSE_IFS */ #define LESENSE_IFS_DECERR (0x1UL << 18) /**< Set DECERR Interrupt Flag */ #define _LESENSE_IFS_DECERR_SHIFT 18 /**< Shift value for LESENSE_DECERR */ #define _LESENSE_IFS_DECERR_MASK 0x40000UL /**< Bit mask for LESENSE_DECERR */ #define _LESENSE_IFS_DECERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ #define LESENSE_IFS_DECERR_DEFAULT (_LESENSE_IFS_DECERR_DEFAULT << 18) /**< Shifted mode DEFAULT for LESENSE_IFS */ #define LESENSE_IFS_BUFDATAV (0x1UL << 19) /**< Set BUFDATAV Interrupt Flag */ #define _LESENSE_IFS_BUFDATAV_SHIFT 19 /**< Shift value for LESENSE_BUFDATAV */ #define _LESENSE_IFS_BUFDATAV_MASK 0x80000UL /**< Bit mask for LESENSE_BUFDATAV */ #define _LESENSE_IFS_BUFDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ #define LESENSE_IFS_BUFDATAV_DEFAULT (_LESENSE_IFS_BUFDATAV_DEFAULT << 19) /**< Shifted mode DEFAULT for LESENSE_IFS */ #define LESENSE_IFS_BUFLEVEL (0x1UL << 20) /**< Set BUFLEVEL Interrupt Flag */ #define _LESENSE_IFS_BUFLEVEL_SHIFT 20 /**< Shift value for LESENSE_BUFLEVEL */ #define _LESENSE_IFS_BUFLEVEL_MASK 0x100000UL /**< Bit mask for LESENSE_BUFLEVEL */ #define _LESENSE_IFS_BUFLEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ #define LESENSE_IFS_BUFLEVEL_DEFAULT (_LESENSE_IFS_BUFLEVEL_DEFAULT << 20) /**< Shifted mode DEFAULT for LESENSE_IFS */ #define LESENSE_IFS_BUFOF (0x1UL << 21) /**< Set BUFOF Interrupt Flag */ #define _LESENSE_IFS_BUFOF_SHIFT 21 /**< Shift value for LESENSE_BUFOF */ #define _LESENSE_IFS_BUFOF_MASK 0x200000UL /**< Bit mask for LESENSE_BUFOF */ #define _LESENSE_IFS_BUFOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ #define LESENSE_IFS_BUFOF_DEFAULT (_LESENSE_IFS_BUFOF_DEFAULT << 21) /**< Shifted mode DEFAULT for LESENSE_IFS */ #define LESENSE_IFS_CNTOF (0x1UL << 22) /**< Set CNTOF Interrupt Flag */ #define _LESENSE_IFS_CNTOF_SHIFT 22 /**< Shift value for LESENSE_CNTOF */ #define _LESENSE_IFS_CNTOF_MASK 0x400000UL /**< Bit mask for LESENSE_CNTOF */ #define _LESENSE_IFS_CNTOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ #define LESENSE_IFS_CNTOF_DEFAULT (_LESENSE_IFS_CNTOF_DEFAULT << 22) /**< Shifted mode DEFAULT for LESENSE_IFS */ /* Bit fields for LESENSE IFC */ #define _LESENSE_IFC_RESETVALUE 0x00000000UL /**< Default value for LESENSE_IFC */ #define _LESENSE_IFC_MASK 0x007FFFFFUL /**< Mask for LESENSE_IFC */ #define LESENSE_IFC_CH0 (0x1UL << 0) /**< Clear CH0 Interrupt Flag */ #define _LESENSE_IFC_CH0_SHIFT 0 /**< Shift value for LESENSE_CH0 */ #define _LESENSE_IFC_CH0_MASK 0x1UL /**< Bit mask for LESENSE_CH0 */ #define _LESENSE_IFC_CH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ #define LESENSE_IFC_CH0_DEFAULT (_LESENSE_IFC_CH0_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_IFC */ #define LESENSE_IFC_CH1 (0x1UL << 1) /**< Clear CH1 Interrupt Flag */ #define _LESENSE_IFC_CH1_SHIFT 1 /**< Shift value for LESENSE_CH1 */ #define _LESENSE_IFC_CH1_MASK 0x2UL /**< Bit mask for LESENSE_CH1 */ #define _LESENSE_IFC_CH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ #define LESENSE_IFC_CH1_DEFAULT (_LESENSE_IFC_CH1_DEFAULT << 1) /**< Shifted mode DEFAULT for LESENSE_IFC */ #define LESENSE_IFC_CH2 (0x1UL << 2) /**< Clear CH2 Interrupt Flag */ #define _LESENSE_IFC_CH2_SHIFT 2 /**< Shift value for LESENSE_CH2 */ #define _LESENSE_IFC_CH2_MASK 0x4UL /**< Bit mask for LESENSE_CH2 */ #define _LESENSE_IFC_CH2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ #define LESENSE_IFC_CH2_DEFAULT (_LESENSE_IFC_CH2_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_IFC */ #define LESENSE_IFC_CH3 (0x1UL << 3) /**< Clear CH3 Interrupt Flag */ #define _LESENSE_IFC_CH3_SHIFT 3 /**< Shift value for LESENSE_CH3 */ #define _LESENSE_IFC_CH3_MASK 0x8UL /**< Bit mask for LESENSE_CH3 */ #define _LESENSE_IFC_CH3_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ #define LESENSE_IFC_CH3_DEFAULT (_LESENSE_IFC_CH3_DEFAULT << 3) /**< Shifted mode DEFAULT for LESENSE_IFC */ #define LESENSE_IFC_CH4 (0x1UL << 4) /**< Clear CH4 Interrupt Flag */ #define _LESENSE_IFC_CH4_SHIFT 4 /**< Shift value for LESENSE_CH4 */ #define _LESENSE_IFC_CH4_MASK 0x10UL /**< Bit mask for LESENSE_CH4 */ #define _LESENSE_IFC_CH4_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ #define LESENSE_IFC_CH4_DEFAULT (_LESENSE_IFC_CH4_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_IFC */ #define LESENSE_IFC_CH5 (0x1UL << 5) /**< Clear CH5 Interrupt Flag */ #define _LESENSE_IFC_CH5_SHIFT 5 /**< Shift value for LESENSE_CH5 */ #define _LESENSE_IFC_CH5_MASK 0x20UL /**< Bit mask for LESENSE_CH5 */ #define _LESENSE_IFC_CH5_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ #define LESENSE_IFC_CH5_DEFAULT (_LESENSE_IFC_CH5_DEFAULT << 5) /**< Shifted mode DEFAULT for LESENSE_IFC */ #define LESENSE_IFC_CH6 (0x1UL << 6) /**< Clear CH6 Interrupt Flag */ #define _LESENSE_IFC_CH6_SHIFT 6 /**< Shift value for LESENSE_CH6 */ #define _LESENSE_IFC_CH6_MASK 0x40UL /**< Bit mask for LESENSE_CH6 */ #define _LESENSE_IFC_CH6_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ #define LESENSE_IFC_CH6_DEFAULT (_LESENSE_IFC_CH6_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_IFC */ #define LESENSE_IFC_CH7 (0x1UL << 7) /**< Clear CH7 Interrupt Flag */ #define _LESENSE_IFC_CH7_SHIFT 7 /**< Shift value for LESENSE_CH7 */ #define _LESENSE_IFC_CH7_MASK 0x80UL /**< Bit mask for LESENSE_CH7 */ #define _LESENSE_IFC_CH7_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ #define LESENSE_IFC_CH7_DEFAULT (_LESENSE_IFC_CH7_DEFAULT << 7) /**< Shifted mode DEFAULT for LESENSE_IFC */ #define LESENSE_IFC_CH8 (0x1UL << 8) /**< Clear CH8 Interrupt Flag */ #define _LESENSE_IFC_CH8_SHIFT 8 /**< Shift value for LESENSE_CH8 */ #define _LESENSE_IFC_CH8_MASK 0x100UL /**< Bit mask for LESENSE_CH8 */ #define _LESENSE_IFC_CH8_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ #define LESENSE_IFC_CH8_DEFAULT (_LESENSE_IFC_CH8_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_IFC */ #define LESENSE_IFC_CH9 (0x1UL << 9) /**< Clear CH9 Interrupt Flag */ #define _LESENSE_IFC_CH9_SHIFT 9 /**< Shift value for LESENSE_CH9 */ #define _LESENSE_IFC_CH9_MASK 0x200UL /**< Bit mask for LESENSE_CH9 */ #define _LESENSE_IFC_CH9_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ #define LESENSE_IFC_CH9_DEFAULT (_LESENSE_IFC_CH9_DEFAULT << 9) /**< Shifted mode DEFAULT for LESENSE_IFC */ #define LESENSE_IFC_CH10 (0x1UL << 10) /**< Clear CH10 Interrupt Flag */ #define _LESENSE_IFC_CH10_SHIFT 10 /**< Shift value for LESENSE_CH10 */ #define _LESENSE_IFC_CH10_MASK 0x400UL /**< Bit mask for LESENSE_CH10 */ #define _LESENSE_IFC_CH10_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ #define LESENSE_IFC_CH10_DEFAULT (_LESENSE_IFC_CH10_DEFAULT << 10) /**< Shifted mode DEFAULT for LESENSE_IFC */ #define LESENSE_IFC_CH11 (0x1UL << 11) /**< Clear CH11 Interrupt Flag */ #define _LESENSE_IFC_CH11_SHIFT 11 /**< Shift value for LESENSE_CH11 */ #define _LESENSE_IFC_CH11_MASK 0x800UL /**< Bit mask for LESENSE_CH11 */ #define _LESENSE_IFC_CH11_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ #define LESENSE_IFC_CH11_DEFAULT (_LESENSE_IFC_CH11_DEFAULT << 11) /**< Shifted mode DEFAULT for LESENSE_IFC */ #define LESENSE_IFC_CH12 (0x1UL << 12) /**< Clear CH12 Interrupt Flag */ #define _LESENSE_IFC_CH12_SHIFT 12 /**< Shift value for LESENSE_CH12 */ #define _LESENSE_IFC_CH12_MASK 0x1000UL /**< Bit mask for LESENSE_CH12 */ #define _LESENSE_IFC_CH12_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ #define LESENSE_IFC_CH12_DEFAULT (_LESENSE_IFC_CH12_DEFAULT << 12) /**< Shifted mode DEFAULT for LESENSE_IFC */ #define LESENSE_IFC_CH13 (0x1UL << 13) /**< Clear CH13 Interrupt Flag */ #define _LESENSE_IFC_CH13_SHIFT 13 /**< Shift value for LESENSE_CH13 */ #define _LESENSE_IFC_CH13_MASK 0x2000UL /**< Bit mask for LESENSE_CH13 */ #define _LESENSE_IFC_CH13_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ #define LESENSE_IFC_CH13_DEFAULT (_LESENSE_IFC_CH13_DEFAULT << 13) /**< Shifted mode DEFAULT for LESENSE_IFC */ #define LESENSE_IFC_CH14 (0x1UL << 14) /**< Clear CH14 Interrupt Flag */ #define _LESENSE_IFC_CH14_SHIFT 14 /**< Shift value for LESENSE_CH14 */ #define _LESENSE_IFC_CH14_MASK 0x4000UL /**< Bit mask for LESENSE_CH14 */ #define _LESENSE_IFC_CH14_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ #define LESENSE_IFC_CH14_DEFAULT (_LESENSE_IFC_CH14_DEFAULT << 14) /**< Shifted mode DEFAULT for LESENSE_IFC */ #define LESENSE_IFC_CH15 (0x1UL << 15) /**< Clear CH15 Interrupt Flag */ #define _LESENSE_IFC_CH15_SHIFT 15 /**< Shift value for LESENSE_CH15 */ #define _LESENSE_IFC_CH15_MASK 0x8000UL /**< Bit mask for LESENSE_CH15 */ #define _LESENSE_IFC_CH15_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ #define LESENSE_IFC_CH15_DEFAULT (_LESENSE_IFC_CH15_DEFAULT << 15) /**< Shifted mode DEFAULT for LESENSE_IFC */ #define LESENSE_IFC_SCANCOMPLETE (0x1UL << 16) /**< Clear SCANCOMPLETE Interrupt Flag */ #define _LESENSE_IFC_SCANCOMPLETE_SHIFT 16 /**< Shift value for LESENSE_SCANCOMPLETE */ #define _LESENSE_IFC_SCANCOMPLETE_MASK 0x10000UL /**< Bit mask for LESENSE_SCANCOMPLETE */ #define _LESENSE_IFC_SCANCOMPLETE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ #define LESENSE_IFC_SCANCOMPLETE_DEFAULT (_LESENSE_IFC_SCANCOMPLETE_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_IFC */ #define LESENSE_IFC_DEC (0x1UL << 17) /**< Clear DEC Interrupt Flag */ #define _LESENSE_IFC_DEC_SHIFT 17 /**< Shift value for LESENSE_DEC */ #define _LESENSE_IFC_DEC_MASK 0x20000UL /**< Bit mask for LESENSE_DEC */ #define _LESENSE_IFC_DEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ #define LESENSE_IFC_DEC_DEFAULT (_LESENSE_IFC_DEC_DEFAULT << 17) /**< Shifted mode DEFAULT for LESENSE_IFC */ #define LESENSE_IFC_DECERR (0x1UL << 18) /**< Clear DECERR Interrupt Flag */ #define _LESENSE_IFC_DECERR_SHIFT 18 /**< Shift value for LESENSE_DECERR */ #define _LESENSE_IFC_DECERR_MASK 0x40000UL /**< Bit mask for LESENSE_DECERR */ #define _LESENSE_IFC_DECERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ #define LESENSE_IFC_DECERR_DEFAULT (_LESENSE_IFC_DECERR_DEFAULT << 18) /**< Shifted mode DEFAULT for LESENSE_IFC */ #define LESENSE_IFC_BUFDATAV (0x1UL << 19) /**< Clear BUFDATAV Interrupt Flag */ #define _LESENSE_IFC_BUFDATAV_SHIFT 19 /**< Shift value for LESENSE_BUFDATAV */ #define _LESENSE_IFC_BUFDATAV_MASK 0x80000UL /**< Bit mask for LESENSE_BUFDATAV */ #define _LESENSE_IFC_BUFDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ #define LESENSE_IFC_BUFDATAV_DEFAULT (_LESENSE_IFC_BUFDATAV_DEFAULT << 19) /**< Shifted mode DEFAULT for LESENSE_IFC */ #define LESENSE_IFC_BUFLEVEL (0x1UL << 20) /**< Clear BUFLEVEL Interrupt Flag */ #define _LESENSE_IFC_BUFLEVEL_SHIFT 20 /**< Shift value for LESENSE_BUFLEVEL */ #define _LESENSE_IFC_BUFLEVEL_MASK 0x100000UL /**< Bit mask for LESENSE_BUFLEVEL */ #define _LESENSE_IFC_BUFLEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ #define LESENSE_IFC_BUFLEVEL_DEFAULT (_LESENSE_IFC_BUFLEVEL_DEFAULT << 20) /**< Shifted mode DEFAULT for LESENSE_IFC */ #define LESENSE_IFC_BUFOF (0x1UL << 21) /**< Clear BUFOF Interrupt Flag */ #define _LESENSE_IFC_BUFOF_SHIFT 21 /**< Shift value for LESENSE_BUFOF */ #define _LESENSE_IFC_BUFOF_MASK 0x200000UL /**< Bit mask for LESENSE_BUFOF */ #define _LESENSE_IFC_BUFOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ #define LESENSE_IFC_BUFOF_DEFAULT (_LESENSE_IFC_BUFOF_DEFAULT << 21) /**< Shifted mode DEFAULT for LESENSE_IFC */ #define LESENSE_IFC_CNTOF (0x1UL << 22) /**< Clear CNTOF Interrupt Flag */ #define _LESENSE_IFC_CNTOF_SHIFT 22 /**< Shift value for LESENSE_CNTOF */ #define _LESENSE_IFC_CNTOF_MASK 0x400000UL /**< Bit mask for LESENSE_CNTOF */ #define _LESENSE_IFC_CNTOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ #define LESENSE_IFC_CNTOF_DEFAULT (_LESENSE_IFC_CNTOF_DEFAULT << 22) /**< Shifted mode DEFAULT for LESENSE_IFC */ /* Bit fields for LESENSE IEN */ #define _LESENSE_IEN_RESETVALUE 0x00000000UL /**< Default value for LESENSE_IEN */ #define _LESENSE_IEN_MASK 0x007FFFFFUL /**< Mask for LESENSE_IEN */ #define LESENSE_IEN_CH0 (0x1UL << 0) /**< CH0 Interrupt Enable */ #define _LESENSE_IEN_CH0_SHIFT 0 /**< Shift value for LESENSE_CH0 */ #define _LESENSE_IEN_CH0_MASK 0x1UL /**< Bit mask for LESENSE_CH0 */ #define _LESENSE_IEN_CH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ #define LESENSE_IEN_CH0_DEFAULT (_LESENSE_IEN_CH0_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_IEN */ #define LESENSE_IEN_CH1 (0x1UL << 1) /**< CH1 Interrupt Enable */ #define _LESENSE_IEN_CH1_SHIFT 1 /**< Shift value for LESENSE_CH1 */ #define _LESENSE_IEN_CH1_MASK 0x2UL /**< Bit mask for LESENSE_CH1 */ #define _LESENSE_IEN_CH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ #define LESENSE_IEN_CH1_DEFAULT (_LESENSE_IEN_CH1_DEFAULT << 1) /**< Shifted mode DEFAULT for LESENSE_IEN */ #define LESENSE_IEN_CH2 (0x1UL << 2) /**< CH2 Interrupt Enable */ #define _LESENSE_IEN_CH2_SHIFT 2 /**< Shift value for LESENSE_CH2 */ #define _LESENSE_IEN_CH2_MASK 0x4UL /**< Bit mask for LESENSE_CH2 */ #define _LESENSE_IEN_CH2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ #define LESENSE_IEN_CH2_DEFAULT (_LESENSE_IEN_CH2_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_IEN */ #define LESENSE_IEN_CH3 (0x1UL << 3) /**< CH3 Interrupt Enable */ #define _LESENSE_IEN_CH3_SHIFT 3 /**< Shift value for LESENSE_CH3 */ #define _LESENSE_IEN_CH3_MASK 0x8UL /**< Bit mask for LESENSE_CH3 */ #define _LESENSE_IEN_CH3_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ #define LESENSE_IEN_CH3_DEFAULT (_LESENSE_IEN_CH3_DEFAULT << 3) /**< Shifted mode DEFAULT for LESENSE_IEN */ #define LESENSE_IEN_CH4 (0x1UL << 4) /**< CH4 Interrupt Enable */ #define _LESENSE_IEN_CH4_SHIFT 4 /**< Shift value for LESENSE_CH4 */ #define _LESENSE_IEN_CH4_MASK 0x10UL /**< Bit mask for LESENSE_CH4 */ #define _LESENSE_IEN_CH4_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ #define LESENSE_IEN_CH4_DEFAULT (_LESENSE_IEN_CH4_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_IEN */ #define LESENSE_IEN_CH5 (0x1UL << 5) /**< CH5 Interrupt Enable */ #define _LESENSE_IEN_CH5_SHIFT 5 /**< Shift value for LESENSE_CH5 */ #define _LESENSE_IEN_CH5_MASK 0x20UL /**< Bit mask for LESENSE_CH5 */ #define _LESENSE_IEN_CH5_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ #define LESENSE_IEN_CH5_DEFAULT (_LESENSE_IEN_CH5_DEFAULT << 5) /**< Shifted mode DEFAULT for LESENSE_IEN */ #define LESENSE_IEN_CH6 (0x1UL << 6) /**< CH6 Interrupt Enable */ #define _LESENSE_IEN_CH6_SHIFT 6 /**< Shift value for LESENSE_CH6 */ #define _LESENSE_IEN_CH6_MASK 0x40UL /**< Bit mask for LESENSE_CH6 */ #define _LESENSE_IEN_CH6_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ #define LESENSE_IEN_CH6_DEFAULT (_LESENSE_IEN_CH6_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_IEN */ #define LESENSE_IEN_CH7 (0x1UL << 7) /**< CH7 Interrupt Enable */ #define _LESENSE_IEN_CH7_SHIFT 7 /**< Shift value for LESENSE_CH7 */ #define _LESENSE_IEN_CH7_MASK 0x80UL /**< Bit mask for LESENSE_CH7 */ #define _LESENSE_IEN_CH7_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ #define LESENSE_IEN_CH7_DEFAULT (_LESENSE_IEN_CH7_DEFAULT << 7) /**< Shifted mode DEFAULT for LESENSE_IEN */ #define LESENSE_IEN_CH8 (0x1UL << 8) /**< CH8 Interrupt Enable */ #define _LESENSE_IEN_CH8_SHIFT 8 /**< Shift value for LESENSE_CH8 */ #define _LESENSE_IEN_CH8_MASK 0x100UL /**< Bit mask for LESENSE_CH8 */ #define _LESENSE_IEN_CH8_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ #define LESENSE_IEN_CH8_DEFAULT (_LESENSE_IEN_CH8_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_IEN */ #define LESENSE_IEN_CH9 (0x1UL << 9) /**< CH9 Interrupt Enable */ #define _LESENSE_IEN_CH9_SHIFT 9 /**< Shift value for LESENSE_CH9 */ #define _LESENSE_IEN_CH9_MASK 0x200UL /**< Bit mask for LESENSE_CH9 */ #define _LESENSE_IEN_CH9_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ #define LESENSE_IEN_CH9_DEFAULT (_LESENSE_IEN_CH9_DEFAULT << 9) /**< Shifted mode DEFAULT for LESENSE_IEN */ #define LESENSE_IEN_CH10 (0x1UL << 10) /**< CH10 Interrupt Enable */ #define _LESENSE_IEN_CH10_SHIFT 10 /**< Shift value for LESENSE_CH10 */ #define _LESENSE_IEN_CH10_MASK 0x400UL /**< Bit mask for LESENSE_CH10 */ #define _LESENSE_IEN_CH10_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ #define LESENSE_IEN_CH10_DEFAULT (_LESENSE_IEN_CH10_DEFAULT << 10) /**< Shifted mode DEFAULT for LESENSE_IEN */ #define LESENSE_IEN_CH11 (0x1UL << 11) /**< CH11 Interrupt Enable */ #define _LESENSE_IEN_CH11_SHIFT 11 /**< Shift value for LESENSE_CH11 */ #define _LESENSE_IEN_CH11_MASK 0x800UL /**< Bit mask for LESENSE_CH11 */ #define _LESENSE_IEN_CH11_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ #define LESENSE_IEN_CH11_DEFAULT (_LESENSE_IEN_CH11_DEFAULT << 11) /**< Shifted mode DEFAULT for LESENSE_IEN */ #define LESENSE_IEN_CH12 (0x1UL << 12) /**< CH12 Interrupt Enable */ #define _LESENSE_IEN_CH12_SHIFT 12 /**< Shift value for LESENSE_CH12 */ #define _LESENSE_IEN_CH12_MASK 0x1000UL /**< Bit mask for LESENSE_CH12 */ #define _LESENSE_IEN_CH12_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ #define LESENSE_IEN_CH12_DEFAULT (_LESENSE_IEN_CH12_DEFAULT << 12) /**< Shifted mode DEFAULT for LESENSE_IEN */ #define LESENSE_IEN_CH13 (0x1UL << 13) /**< CH13 Interrupt Enable */ #define _LESENSE_IEN_CH13_SHIFT 13 /**< Shift value for LESENSE_CH13 */ #define _LESENSE_IEN_CH13_MASK 0x2000UL /**< Bit mask for LESENSE_CH13 */ #define _LESENSE_IEN_CH13_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ #define LESENSE_IEN_CH13_DEFAULT (_LESENSE_IEN_CH13_DEFAULT << 13) /**< Shifted mode DEFAULT for LESENSE_IEN */ #define LESENSE_IEN_CH14 (0x1UL << 14) /**< CH14 Interrupt Enable */ #define _LESENSE_IEN_CH14_SHIFT 14 /**< Shift value for LESENSE_CH14 */ #define _LESENSE_IEN_CH14_MASK 0x4000UL /**< Bit mask for LESENSE_CH14 */ #define _LESENSE_IEN_CH14_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ #define LESENSE_IEN_CH14_DEFAULT (_LESENSE_IEN_CH14_DEFAULT << 14) /**< Shifted mode DEFAULT for LESENSE_IEN */ #define LESENSE_IEN_CH15 (0x1UL << 15) /**< CH15 Interrupt Enable */ #define _LESENSE_IEN_CH15_SHIFT 15 /**< Shift value for LESENSE_CH15 */ #define _LESENSE_IEN_CH15_MASK 0x8000UL /**< Bit mask for LESENSE_CH15 */ #define _LESENSE_IEN_CH15_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ #define LESENSE_IEN_CH15_DEFAULT (_LESENSE_IEN_CH15_DEFAULT << 15) /**< Shifted mode DEFAULT for LESENSE_IEN */ #define LESENSE_IEN_SCANCOMPLETE (0x1UL << 16) /**< SCANCOMPLETE Interrupt Enable */ #define _LESENSE_IEN_SCANCOMPLETE_SHIFT 16 /**< Shift value for LESENSE_SCANCOMPLETE */ #define _LESENSE_IEN_SCANCOMPLETE_MASK 0x10000UL /**< Bit mask for LESENSE_SCANCOMPLETE */ #define _LESENSE_IEN_SCANCOMPLETE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ #define LESENSE_IEN_SCANCOMPLETE_DEFAULT (_LESENSE_IEN_SCANCOMPLETE_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_IEN */ #define LESENSE_IEN_DEC (0x1UL << 17) /**< DEC Interrupt Enable */ #define _LESENSE_IEN_DEC_SHIFT 17 /**< Shift value for LESENSE_DEC */ #define _LESENSE_IEN_DEC_MASK 0x20000UL /**< Bit mask for LESENSE_DEC */ #define _LESENSE_IEN_DEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ #define LESENSE_IEN_DEC_DEFAULT (_LESENSE_IEN_DEC_DEFAULT << 17) /**< Shifted mode DEFAULT for LESENSE_IEN */ #define LESENSE_IEN_DECERR (0x1UL << 18) /**< DECERR Interrupt Enable */ #define _LESENSE_IEN_DECERR_SHIFT 18 /**< Shift value for LESENSE_DECERR */ #define _LESENSE_IEN_DECERR_MASK 0x40000UL /**< Bit mask for LESENSE_DECERR */ #define _LESENSE_IEN_DECERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ #define LESENSE_IEN_DECERR_DEFAULT (_LESENSE_IEN_DECERR_DEFAULT << 18) /**< Shifted mode DEFAULT for LESENSE_IEN */ #define LESENSE_IEN_BUFDATAV (0x1UL << 19) /**< BUFDATAV Interrupt Enable */ #define _LESENSE_IEN_BUFDATAV_SHIFT 19 /**< Shift value for LESENSE_BUFDATAV */ #define _LESENSE_IEN_BUFDATAV_MASK 0x80000UL /**< Bit mask for LESENSE_BUFDATAV */ #define _LESENSE_IEN_BUFDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ #define LESENSE_IEN_BUFDATAV_DEFAULT (_LESENSE_IEN_BUFDATAV_DEFAULT << 19) /**< Shifted mode DEFAULT for LESENSE_IEN */ #define LESENSE_IEN_BUFLEVEL (0x1UL << 20) /**< BUFLEVEL Interrupt Enable */ #define _LESENSE_IEN_BUFLEVEL_SHIFT 20 /**< Shift value for LESENSE_BUFLEVEL */ #define _LESENSE_IEN_BUFLEVEL_MASK 0x100000UL /**< Bit mask for LESENSE_BUFLEVEL */ #define _LESENSE_IEN_BUFLEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ #define LESENSE_IEN_BUFLEVEL_DEFAULT (_LESENSE_IEN_BUFLEVEL_DEFAULT << 20) /**< Shifted mode DEFAULT for LESENSE_IEN */ #define LESENSE_IEN_BUFOF (0x1UL << 21) /**< BUFOF Interrupt Enable */ #define _LESENSE_IEN_BUFOF_SHIFT 21 /**< Shift value for LESENSE_BUFOF */ #define _LESENSE_IEN_BUFOF_MASK 0x200000UL /**< Bit mask for LESENSE_BUFOF */ #define _LESENSE_IEN_BUFOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ #define LESENSE_IEN_BUFOF_DEFAULT (_LESENSE_IEN_BUFOF_DEFAULT << 21) /**< Shifted mode DEFAULT for LESENSE_IEN */ #define LESENSE_IEN_CNTOF (0x1UL << 22) /**< CNTOF Interrupt Enable */ #define _LESENSE_IEN_CNTOF_SHIFT 22 /**< Shift value for LESENSE_CNTOF */ #define _LESENSE_IEN_CNTOF_MASK 0x400000UL /**< Bit mask for LESENSE_CNTOF */ #define _LESENSE_IEN_CNTOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ #define LESENSE_IEN_CNTOF_DEFAULT (_LESENSE_IEN_CNTOF_DEFAULT << 22) /**< Shifted mode DEFAULT for LESENSE_IEN */ /* Bit fields for LESENSE SYNCBUSY */ #define _LESENSE_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for LESENSE_SYNCBUSY */ #define _LESENSE_SYNCBUSY_MASK 0x00000080UL /**< Mask for LESENSE_SYNCBUSY */ #define LESENSE_SYNCBUSY_CMD (0x1UL << 7) /**< CMD Register Busy */ #define _LESENSE_SYNCBUSY_CMD_SHIFT 7 /**< Shift value for LESENSE_CMD */ #define _LESENSE_SYNCBUSY_CMD_MASK 0x80UL /**< Bit mask for LESENSE_CMD */ #define _LESENSE_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_SYNCBUSY */ #define LESENSE_SYNCBUSY_CMD_DEFAULT (_LESENSE_SYNCBUSY_CMD_DEFAULT << 7) /**< Shifted mode DEFAULT for LESENSE_SYNCBUSY */ /* Bit fields for LESENSE ROUTEPEN */ #define _LESENSE_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for LESENSE_ROUTEPEN */ #define _LESENSE_ROUTEPEN_MASK 0x00FFFFFFUL /**< Mask for LESENSE_ROUTEPEN */ #define LESENSE_ROUTEPEN_CH0PEN (0x1UL << 0) /**< CH0 Pin Enable */ #define _LESENSE_ROUTEPEN_CH0PEN_SHIFT 0 /**< Shift value for LESENSE_CH0PEN */ #define _LESENSE_ROUTEPEN_CH0PEN_MASK 0x1UL /**< Bit mask for LESENSE_CH0PEN */ #define _LESENSE_ROUTEPEN_CH0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ #define LESENSE_ROUTEPEN_CH0PEN_DEFAULT (_LESENSE_ROUTEPEN_CH0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ #define LESENSE_ROUTEPEN_CH1PEN (0x1UL << 1) /**< CH1 Pin Enable */ #define _LESENSE_ROUTEPEN_CH1PEN_SHIFT 1 /**< Shift value for LESENSE_CH1PEN */ #define _LESENSE_ROUTEPEN_CH1PEN_MASK 0x2UL /**< Bit mask for LESENSE_CH1PEN */ #define _LESENSE_ROUTEPEN_CH1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ #define LESENSE_ROUTEPEN_CH1PEN_DEFAULT (_LESENSE_ROUTEPEN_CH1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ #define LESENSE_ROUTEPEN_CH2PEN (0x1UL << 2) /**< CH2 Pin Enable */ #define _LESENSE_ROUTEPEN_CH2PEN_SHIFT 2 /**< Shift value for LESENSE_CH2PEN */ #define _LESENSE_ROUTEPEN_CH2PEN_MASK 0x4UL /**< Bit mask for LESENSE_CH2PEN */ #define _LESENSE_ROUTEPEN_CH2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ #define LESENSE_ROUTEPEN_CH2PEN_DEFAULT (_LESENSE_ROUTEPEN_CH2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ #define LESENSE_ROUTEPEN_CH3PEN (0x1UL << 3) /**< CH3 Pin Enable */ #define _LESENSE_ROUTEPEN_CH3PEN_SHIFT 3 /**< Shift value for LESENSE_CH3PEN */ #define _LESENSE_ROUTEPEN_CH3PEN_MASK 0x8UL /**< Bit mask for LESENSE_CH3PEN */ #define _LESENSE_ROUTEPEN_CH3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ #define LESENSE_ROUTEPEN_CH3PEN_DEFAULT (_LESENSE_ROUTEPEN_CH3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ #define LESENSE_ROUTEPEN_CH4PEN (0x1UL << 4) /**< CH4 Pin Enable */ #define _LESENSE_ROUTEPEN_CH4PEN_SHIFT 4 /**< Shift value for LESENSE_CH4PEN */ #define _LESENSE_ROUTEPEN_CH4PEN_MASK 0x10UL /**< Bit mask for LESENSE_CH4PEN */ #define _LESENSE_ROUTEPEN_CH4PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ #define LESENSE_ROUTEPEN_CH4PEN_DEFAULT (_LESENSE_ROUTEPEN_CH4PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ #define LESENSE_ROUTEPEN_CH5PEN (0x1UL << 5) /**< CH5 Pin Enable */ #define _LESENSE_ROUTEPEN_CH5PEN_SHIFT 5 /**< Shift value for LESENSE_CH5PEN */ #define _LESENSE_ROUTEPEN_CH5PEN_MASK 0x20UL /**< Bit mask for LESENSE_CH5PEN */ #define _LESENSE_ROUTEPEN_CH5PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ #define LESENSE_ROUTEPEN_CH5PEN_DEFAULT (_LESENSE_ROUTEPEN_CH5PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ #define LESENSE_ROUTEPEN_CH6PEN (0x1UL << 6) /**< CH6 Pin Enable */ #define _LESENSE_ROUTEPEN_CH6PEN_SHIFT 6 /**< Shift value for LESENSE_CH6PEN */ #define _LESENSE_ROUTEPEN_CH6PEN_MASK 0x40UL /**< Bit mask for LESENSE_CH6PEN */ #define _LESENSE_ROUTEPEN_CH6PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ #define LESENSE_ROUTEPEN_CH6PEN_DEFAULT (_LESENSE_ROUTEPEN_CH6PEN_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ #define LESENSE_ROUTEPEN_CH7PEN (0x1UL << 7) /**< CH7 Pin Enable */ #define _LESENSE_ROUTEPEN_CH7PEN_SHIFT 7 /**< Shift value for LESENSE_CH7PEN */ #define _LESENSE_ROUTEPEN_CH7PEN_MASK 0x80UL /**< Bit mask for LESENSE_CH7PEN */ #define _LESENSE_ROUTEPEN_CH7PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ #define LESENSE_ROUTEPEN_CH7PEN_DEFAULT (_LESENSE_ROUTEPEN_CH7PEN_DEFAULT << 7) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ #define LESENSE_ROUTEPEN_CH8PEN (0x1UL << 8) /**< CH8 Pin Enable */ #define _LESENSE_ROUTEPEN_CH8PEN_SHIFT 8 /**< Shift value for LESENSE_CH8PEN */ #define _LESENSE_ROUTEPEN_CH8PEN_MASK 0x100UL /**< Bit mask for LESENSE_CH8PEN */ #define _LESENSE_ROUTEPEN_CH8PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ #define LESENSE_ROUTEPEN_CH8PEN_DEFAULT (_LESENSE_ROUTEPEN_CH8PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ #define LESENSE_ROUTEPEN_CH9PEN (0x1UL << 9) /**< CH9 Pin Enable */ #define _LESENSE_ROUTEPEN_CH9PEN_SHIFT 9 /**< Shift value for LESENSE_CH9PEN */ #define _LESENSE_ROUTEPEN_CH9PEN_MASK 0x200UL /**< Bit mask for LESENSE_CH9PEN */ #define _LESENSE_ROUTEPEN_CH9PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ #define LESENSE_ROUTEPEN_CH9PEN_DEFAULT (_LESENSE_ROUTEPEN_CH9PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ #define LESENSE_ROUTEPEN_CH10PEN (0x1UL << 10) /**< CH10 Pin Enable */ #define _LESENSE_ROUTEPEN_CH10PEN_SHIFT 10 /**< Shift value for LESENSE_CH10PEN */ #define _LESENSE_ROUTEPEN_CH10PEN_MASK 0x400UL /**< Bit mask for LESENSE_CH10PEN */ #define _LESENSE_ROUTEPEN_CH10PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ #define LESENSE_ROUTEPEN_CH10PEN_DEFAULT (_LESENSE_ROUTEPEN_CH10PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ #define LESENSE_ROUTEPEN_CH11PEN (0x1UL << 11) /**< CH11 Pin Enable */ #define _LESENSE_ROUTEPEN_CH11PEN_SHIFT 11 /**< Shift value for LESENSE_CH11PEN */ #define _LESENSE_ROUTEPEN_CH11PEN_MASK 0x800UL /**< Bit mask for LESENSE_CH11PEN */ #define _LESENSE_ROUTEPEN_CH11PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ #define LESENSE_ROUTEPEN_CH11PEN_DEFAULT (_LESENSE_ROUTEPEN_CH11PEN_DEFAULT << 11) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ #define LESENSE_ROUTEPEN_CH12PEN (0x1UL << 12) /**< CH12 Pin Enable */ #define _LESENSE_ROUTEPEN_CH12PEN_SHIFT 12 /**< Shift value for LESENSE_CH12PEN */ #define _LESENSE_ROUTEPEN_CH12PEN_MASK 0x1000UL /**< Bit mask for LESENSE_CH12PEN */ #define _LESENSE_ROUTEPEN_CH12PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ #define LESENSE_ROUTEPEN_CH12PEN_DEFAULT (_LESENSE_ROUTEPEN_CH12PEN_DEFAULT << 12) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ #define LESENSE_ROUTEPEN_CH13PEN (0x1UL << 13) /**< CH13 Pin Enable */ #define _LESENSE_ROUTEPEN_CH13PEN_SHIFT 13 /**< Shift value for LESENSE_CH13PEN */ #define _LESENSE_ROUTEPEN_CH13PEN_MASK 0x2000UL /**< Bit mask for LESENSE_CH13PEN */ #define _LESENSE_ROUTEPEN_CH13PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ #define LESENSE_ROUTEPEN_CH13PEN_DEFAULT (_LESENSE_ROUTEPEN_CH13PEN_DEFAULT << 13) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ #define LESENSE_ROUTEPEN_CH14PEN (0x1UL << 14) /**< CH14 Pin Enable */ #define _LESENSE_ROUTEPEN_CH14PEN_SHIFT 14 /**< Shift value for LESENSE_CH14PEN */ #define _LESENSE_ROUTEPEN_CH14PEN_MASK 0x4000UL /**< Bit mask for LESENSE_CH14PEN */ #define _LESENSE_ROUTEPEN_CH14PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ #define LESENSE_ROUTEPEN_CH14PEN_DEFAULT (_LESENSE_ROUTEPEN_CH14PEN_DEFAULT << 14) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ #define LESENSE_ROUTEPEN_CH15PEN (0x1UL << 15) /**< CH15 Pin Enable */ #define _LESENSE_ROUTEPEN_CH15PEN_SHIFT 15 /**< Shift value for LESENSE_CH15PEN */ #define _LESENSE_ROUTEPEN_CH15PEN_MASK 0x8000UL /**< Bit mask for LESENSE_CH15PEN */ #define _LESENSE_ROUTEPEN_CH15PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ #define LESENSE_ROUTEPEN_CH15PEN_DEFAULT (_LESENSE_ROUTEPEN_CH15PEN_DEFAULT << 15) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ #define LESENSE_ROUTEPEN_ALTEX0PEN (0x1UL << 16) /**< ALTEX0 Pin Enable */ #define _LESENSE_ROUTEPEN_ALTEX0PEN_SHIFT 16 /**< Shift value for LESENSE_ALTEX0PEN */ #define _LESENSE_ROUTEPEN_ALTEX0PEN_MASK 0x10000UL /**< Bit mask for LESENSE_ALTEX0PEN */ #define _LESENSE_ROUTEPEN_ALTEX0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ #define LESENSE_ROUTEPEN_ALTEX0PEN_DEFAULT (_LESENSE_ROUTEPEN_ALTEX0PEN_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ #define LESENSE_ROUTEPEN_ALTEX1PEN (0x1UL << 17) /**< ALTEX1 Pin Enable */ #define _LESENSE_ROUTEPEN_ALTEX1PEN_SHIFT 17 /**< Shift value for LESENSE_ALTEX1PEN */ #define _LESENSE_ROUTEPEN_ALTEX1PEN_MASK 0x20000UL /**< Bit mask for LESENSE_ALTEX1PEN */ #define _LESENSE_ROUTEPEN_ALTEX1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ #define LESENSE_ROUTEPEN_ALTEX1PEN_DEFAULT (_LESENSE_ROUTEPEN_ALTEX1PEN_DEFAULT << 17) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ #define LESENSE_ROUTEPEN_ALTEX2PEN (0x1UL << 18) /**< ALTEX2 Pin Enable */ #define _LESENSE_ROUTEPEN_ALTEX2PEN_SHIFT 18 /**< Shift value for LESENSE_ALTEX2PEN */ #define _LESENSE_ROUTEPEN_ALTEX2PEN_MASK 0x40000UL /**< Bit mask for LESENSE_ALTEX2PEN */ #define _LESENSE_ROUTEPEN_ALTEX2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ #define LESENSE_ROUTEPEN_ALTEX2PEN_DEFAULT (_LESENSE_ROUTEPEN_ALTEX2PEN_DEFAULT << 18) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ #define LESENSE_ROUTEPEN_ALTEX3PEN (0x1UL << 19) /**< ALTEX3 Pin Enable */ #define _LESENSE_ROUTEPEN_ALTEX3PEN_SHIFT 19 /**< Shift value for LESENSE_ALTEX3PEN */ #define _LESENSE_ROUTEPEN_ALTEX3PEN_MASK 0x80000UL /**< Bit mask for LESENSE_ALTEX3PEN */ #define _LESENSE_ROUTEPEN_ALTEX3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ #define LESENSE_ROUTEPEN_ALTEX3PEN_DEFAULT (_LESENSE_ROUTEPEN_ALTEX3PEN_DEFAULT << 19) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ #define LESENSE_ROUTEPEN_ALTEX4PEN (0x1UL << 20) /**< ALTEX4 Pin Enable */ #define _LESENSE_ROUTEPEN_ALTEX4PEN_SHIFT 20 /**< Shift value for LESENSE_ALTEX4PEN */ #define _LESENSE_ROUTEPEN_ALTEX4PEN_MASK 0x100000UL /**< Bit mask for LESENSE_ALTEX4PEN */ #define _LESENSE_ROUTEPEN_ALTEX4PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ #define LESENSE_ROUTEPEN_ALTEX4PEN_DEFAULT (_LESENSE_ROUTEPEN_ALTEX4PEN_DEFAULT << 20) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ #define LESENSE_ROUTEPEN_ALTEX5PEN (0x1UL << 21) /**< ALTEX5 Pin Enable */ #define _LESENSE_ROUTEPEN_ALTEX5PEN_SHIFT 21 /**< Shift value for LESENSE_ALTEX5PEN */ #define _LESENSE_ROUTEPEN_ALTEX5PEN_MASK 0x200000UL /**< Bit mask for LESENSE_ALTEX5PEN */ #define _LESENSE_ROUTEPEN_ALTEX5PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ #define LESENSE_ROUTEPEN_ALTEX5PEN_DEFAULT (_LESENSE_ROUTEPEN_ALTEX5PEN_DEFAULT << 21) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ #define LESENSE_ROUTEPEN_ALTEX6PEN (0x1UL << 22) /**< ALTEX6 Pin Enable */ #define _LESENSE_ROUTEPEN_ALTEX6PEN_SHIFT 22 /**< Shift value for LESENSE_ALTEX6PEN */ #define _LESENSE_ROUTEPEN_ALTEX6PEN_MASK 0x400000UL /**< Bit mask for LESENSE_ALTEX6PEN */ #define _LESENSE_ROUTEPEN_ALTEX6PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ #define LESENSE_ROUTEPEN_ALTEX6PEN_DEFAULT (_LESENSE_ROUTEPEN_ALTEX6PEN_DEFAULT << 22) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ #define LESENSE_ROUTEPEN_ALTEX7PEN (0x1UL << 23) /**< ALTEX7 Pin Enable */ #define _LESENSE_ROUTEPEN_ALTEX7PEN_SHIFT 23 /**< Shift value for LESENSE_ALTEX7PEN */ #define _LESENSE_ROUTEPEN_ALTEX7PEN_MASK 0x800000UL /**< Bit mask for LESENSE_ALTEX7PEN */ #define _LESENSE_ROUTEPEN_ALTEX7PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ #define LESENSE_ROUTEPEN_ALTEX7PEN_DEFAULT (_LESENSE_ROUTEPEN_ALTEX7PEN_DEFAULT << 23) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ /* Bit fields for LESENSE ST_TCONFA */ #define _LESENSE_ST_TCONFA_RESETVALUE 0x00000000UL /**< Default value for LESENSE_ST_TCONFA */ #define _LESENSE_ST_TCONFA_MASK 0x0007DFFFUL /**< Mask for LESENSE_ST_TCONFA */ #define _LESENSE_ST_TCONFA_COMP_SHIFT 0 /**< Shift value for LESENSE_COMP */ #define _LESENSE_ST_TCONFA_COMP_MASK 0xFUL /**< Bit mask for LESENSE_COMP */ #define _LESENSE_ST_TCONFA_COMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_TCONFA */ #define LESENSE_ST_TCONFA_COMP_DEFAULT (_LESENSE_ST_TCONFA_COMP_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_ST_TCONFA */ #define _LESENSE_ST_TCONFA_MASK_SHIFT 4 /**< Shift value for LESENSE_MASK */ #define _LESENSE_ST_TCONFA_MASK_MASK 0xF0UL /**< Bit mask for LESENSE_MASK */ #define _LESENSE_ST_TCONFA_MASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_TCONFA */ #define LESENSE_ST_TCONFA_MASK_DEFAULT (_LESENSE_ST_TCONFA_MASK_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_ST_TCONFA */ #define _LESENSE_ST_TCONFA_NEXTSTATE_SHIFT 8 /**< Shift value for LESENSE_NEXTSTATE */ #define _LESENSE_ST_TCONFA_NEXTSTATE_MASK 0x1F00UL /**< Bit mask for LESENSE_NEXTSTATE */ #define _LESENSE_ST_TCONFA_NEXTSTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_TCONFA */ #define LESENSE_ST_TCONFA_NEXTSTATE_DEFAULT (_LESENSE_ST_TCONFA_NEXTSTATE_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_ST_TCONFA */ #define LESENSE_ST_TCONFA_CHAIN (0x1UL << 14) /**< Enable State Descriptor Chaining */ #define _LESENSE_ST_TCONFA_CHAIN_SHIFT 14 /**< Shift value for LESENSE_CHAIN */ #define _LESENSE_ST_TCONFA_CHAIN_MASK 0x4000UL /**< Bit mask for LESENSE_CHAIN */ #define _LESENSE_ST_TCONFA_CHAIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_TCONFA */ #define LESENSE_ST_TCONFA_CHAIN_DEFAULT (_LESENSE_ST_TCONFA_CHAIN_DEFAULT << 14) /**< Shifted mode DEFAULT for LESENSE_ST_TCONFA */ #define LESENSE_ST_TCONFA_SETIF (0x1UL << 15) /**< Set Interrupt Flag Enable */ #define _LESENSE_ST_TCONFA_SETIF_SHIFT 15 /**< Shift value for LESENSE_SETIF */ #define _LESENSE_ST_TCONFA_SETIF_MASK 0x8000UL /**< Bit mask for LESENSE_SETIF */ #define _LESENSE_ST_TCONFA_SETIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_TCONFA */ #define LESENSE_ST_TCONFA_SETIF_DEFAULT (_LESENSE_ST_TCONFA_SETIF_DEFAULT << 15) /**< Shifted mode DEFAULT for LESENSE_ST_TCONFA */ #define _LESENSE_ST_TCONFA_PRSACT_SHIFT 16 /**< Shift value for LESENSE_PRSACT */ #define _LESENSE_ST_TCONFA_PRSACT_MASK 0x70000UL /**< Bit mask for LESENSE_PRSACT */ #define _LESENSE_ST_TCONFA_PRSACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_TCONFA */ #define _LESENSE_ST_TCONFA_PRSACT_NONE 0x00000000UL /**< Mode NONE for LESENSE_ST_TCONFA */ #define _LESENSE_ST_TCONFA_PRSACT_UP 0x00000001UL /**< Mode UP for LESENSE_ST_TCONFA */ #define _LESENSE_ST_TCONFA_PRSACT_PRS0 0x00000001UL /**< Mode PRS0 for LESENSE_ST_TCONFA */ #define _LESENSE_ST_TCONFA_PRSACT_PRS1 0x00000002UL /**< Mode PRS1 for LESENSE_ST_TCONFA */ #define _LESENSE_ST_TCONFA_PRSACT_DOWN 0x00000002UL /**< Mode DOWN for LESENSE_ST_TCONFA */ #define _LESENSE_ST_TCONFA_PRSACT_PRS01 0x00000003UL /**< Mode PRS01 for LESENSE_ST_TCONFA */ #define _LESENSE_ST_TCONFA_PRSACT_PRS2 0x00000004UL /**< Mode PRS2 for LESENSE_ST_TCONFA */ #define _LESENSE_ST_TCONFA_PRSACT_PRS02 0x00000005UL /**< Mode PRS02 for LESENSE_ST_TCONFA */ #define _LESENSE_ST_TCONFA_PRSACT_UPANDPRS2 0x00000005UL /**< Mode UPANDPRS2 for LESENSE_ST_TCONFA */ #define _LESENSE_ST_TCONFA_PRSACT_PRS12 0x00000006UL /**< Mode PRS12 for LESENSE_ST_TCONFA */ #define _LESENSE_ST_TCONFA_PRSACT_DOWNANDPRS2 0x00000006UL /**< Mode DOWNANDPRS2 for LESENSE_ST_TCONFA */ #define _LESENSE_ST_TCONFA_PRSACT_PRS012 0x00000007UL /**< Mode PRS012 for LESENSE_ST_TCONFA */ #define LESENSE_ST_TCONFA_PRSACT_DEFAULT (_LESENSE_ST_TCONFA_PRSACT_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_ST_TCONFA */ #define LESENSE_ST_TCONFA_PRSACT_NONE (_LESENSE_ST_TCONFA_PRSACT_NONE << 16) /**< Shifted mode NONE for LESENSE_ST_TCONFA */ #define LESENSE_ST_TCONFA_PRSACT_UP (_LESENSE_ST_TCONFA_PRSACT_UP << 16) /**< Shifted mode UP for LESENSE_ST_TCONFA */ #define LESENSE_ST_TCONFA_PRSACT_PRS0 (_LESENSE_ST_TCONFA_PRSACT_PRS0 << 16) /**< Shifted mode PRS0 for LESENSE_ST_TCONFA */ #define LESENSE_ST_TCONFA_PRSACT_PRS1 (_LESENSE_ST_TCONFA_PRSACT_PRS1 << 16) /**< Shifted mode PRS1 for LESENSE_ST_TCONFA */ #define LESENSE_ST_TCONFA_PRSACT_DOWN (_LESENSE_ST_TCONFA_PRSACT_DOWN << 16) /**< Shifted mode DOWN for LESENSE_ST_TCONFA */ #define LESENSE_ST_TCONFA_PRSACT_PRS01 (_LESENSE_ST_TCONFA_PRSACT_PRS01 << 16) /**< Shifted mode PRS01 for LESENSE_ST_TCONFA */ #define LESENSE_ST_TCONFA_PRSACT_PRS2 (_LESENSE_ST_TCONFA_PRSACT_PRS2 << 16) /**< Shifted mode PRS2 for LESENSE_ST_TCONFA */ #define LESENSE_ST_TCONFA_PRSACT_PRS02 (_LESENSE_ST_TCONFA_PRSACT_PRS02 << 16) /**< Shifted mode PRS02 for LESENSE_ST_TCONFA */ #define LESENSE_ST_TCONFA_PRSACT_UPANDPRS2 (_LESENSE_ST_TCONFA_PRSACT_UPANDPRS2 << 16) /**< Shifted mode UPANDPRS2 for LESENSE_ST_TCONFA */ #define LESENSE_ST_TCONFA_PRSACT_PRS12 (_LESENSE_ST_TCONFA_PRSACT_PRS12 << 16) /**< Shifted mode PRS12 for LESENSE_ST_TCONFA */ #define LESENSE_ST_TCONFA_PRSACT_DOWNANDPRS2 (_LESENSE_ST_TCONFA_PRSACT_DOWNANDPRS2 << 16) /**< Shifted mode DOWNANDPRS2 for LESENSE_ST_TCONFA */ #define LESENSE_ST_TCONFA_PRSACT_PRS012 (_LESENSE_ST_TCONFA_PRSACT_PRS012 << 16) /**< Shifted mode PRS012 for LESENSE_ST_TCONFA */ /* Bit fields for LESENSE ST_TCONFB */ #define _LESENSE_ST_TCONFB_RESETVALUE 0x00000000UL /**< Default value for LESENSE_ST_TCONFB */ #define _LESENSE_ST_TCONFB_MASK 0x00079FFFUL /**< Mask for LESENSE_ST_TCONFB */ #define _LESENSE_ST_TCONFB_COMP_SHIFT 0 /**< Shift value for LESENSE_COMP */ #define _LESENSE_ST_TCONFB_COMP_MASK 0xFUL /**< Bit mask for LESENSE_COMP */ #define _LESENSE_ST_TCONFB_COMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_TCONFB */ #define LESENSE_ST_TCONFB_COMP_DEFAULT (_LESENSE_ST_TCONFB_COMP_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_ST_TCONFB */ #define _LESENSE_ST_TCONFB_MASK_SHIFT 4 /**< Shift value for LESENSE_MASK */ #define _LESENSE_ST_TCONFB_MASK_MASK 0xF0UL /**< Bit mask for LESENSE_MASK */ #define _LESENSE_ST_TCONFB_MASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_TCONFB */ #define LESENSE_ST_TCONFB_MASK_DEFAULT (_LESENSE_ST_TCONFB_MASK_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_ST_TCONFB */ #define _LESENSE_ST_TCONFB_NEXTSTATE_SHIFT 8 /**< Shift value for LESENSE_NEXTSTATE */ #define _LESENSE_ST_TCONFB_NEXTSTATE_MASK 0x1F00UL /**< Bit mask for LESENSE_NEXTSTATE */ #define _LESENSE_ST_TCONFB_NEXTSTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_TCONFB */ #define LESENSE_ST_TCONFB_NEXTSTATE_DEFAULT (_LESENSE_ST_TCONFB_NEXTSTATE_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_ST_TCONFB */ #define LESENSE_ST_TCONFB_SETIF (0x1UL << 15) /**< Set Interrupt Flag */ #define _LESENSE_ST_TCONFB_SETIF_SHIFT 15 /**< Shift value for LESENSE_SETIF */ #define _LESENSE_ST_TCONFB_SETIF_MASK 0x8000UL /**< Bit mask for LESENSE_SETIF */ #define _LESENSE_ST_TCONFB_SETIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_TCONFB */ #define LESENSE_ST_TCONFB_SETIF_DEFAULT (_LESENSE_ST_TCONFB_SETIF_DEFAULT << 15) /**< Shifted mode DEFAULT for LESENSE_ST_TCONFB */ #define _LESENSE_ST_TCONFB_PRSACT_SHIFT 16 /**< Shift value for LESENSE_PRSACT */ #define _LESENSE_ST_TCONFB_PRSACT_MASK 0x70000UL /**< Bit mask for LESENSE_PRSACT */ #define _LESENSE_ST_TCONFB_PRSACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_TCONFB */ #define _LESENSE_ST_TCONFB_PRSACT_NONE 0x00000000UL /**< Mode NONE for LESENSE_ST_TCONFB */ #define _LESENSE_ST_TCONFB_PRSACT_UP 0x00000001UL /**< Mode UP for LESENSE_ST_TCONFB */ #define _LESENSE_ST_TCONFB_PRSACT_PRS0 0x00000001UL /**< Mode PRS0 for LESENSE_ST_TCONFB */ #define _LESENSE_ST_TCONFB_PRSACT_PRS1 0x00000002UL /**< Mode PRS1 for LESENSE_ST_TCONFB */ #define _LESENSE_ST_TCONFB_PRSACT_DOWN 0x00000002UL /**< Mode DOWN for LESENSE_ST_TCONFB */ #define _LESENSE_ST_TCONFB_PRSACT_PRS01 0x00000003UL /**< Mode PRS01 for LESENSE_ST_TCONFB */ #define _LESENSE_ST_TCONFB_PRSACT_PRS2 0x00000004UL /**< Mode PRS2 for LESENSE_ST_TCONFB */ #define _LESENSE_ST_TCONFB_PRSACT_PRS02 0x00000005UL /**< Mode PRS02 for LESENSE_ST_TCONFB */ #define _LESENSE_ST_TCONFB_PRSACT_UPANDPRS2 0x00000005UL /**< Mode UPANDPRS2 for LESENSE_ST_TCONFB */ #define _LESENSE_ST_TCONFB_PRSACT_PRS12 0x00000006UL /**< Mode PRS12 for LESENSE_ST_TCONFB */ #define _LESENSE_ST_TCONFB_PRSACT_DOWNANDPRS2 0x00000006UL /**< Mode DOWNANDPRS2 for LESENSE_ST_TCONFB */ #define _LESENSE_ST_TCONFB_PRSACT_PRS012 0x00000007UL /**< Mode PRS012 for LESENSE_ST_TCONFB */ #define LESENSE_ST_TCONFB_PRSACT_DEFAULT (_LESENSE_ST_TCONFB_PRSACT_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_ST_TCONFB */ #define LESENSE_ST_TCONFB_PRSACT_NONE (_LESENSE_ST_TCONFB_PRSACT_NONE << 16) /**< Shifted mode NONE for LESENSE_ST_TCONFB */ #define LESENSE_ST_TCONFB_PRSACT_UP (_LESENSE_ST_TCONFB_PRSACT_UP << 16) /**< Shifted mode UP for LESENSE_ST_TCONFB */ #define LESENSE_ST_TCONFB_PRSACT_PRS0 (_LESENSE_ST_TCONFB_PRSACT_PRS0 << 16) /**< Shifted mode PRS0 for LESENSE_ST_TCONFB */ #define LESENSE_ST_TCONFB_PRSACT_PRS1 (_LESENSE_ST_TCONFB_PRSACT_PRS1 << 16) /**< Shifted mode PRS1 for LESENSE_ST_TCONFB */ #define LESENSE_ST_TCONFB_PRSACT_DOWN (_LESENSE_ST_TCONFB_PRSACT_DOWN << 16) /**< Shifted mode DOWN for LESENSE_ST_TCONFB */ #define LESENSE_ST_TCONFB_PRSACT_PRS01 (_LESENSE_ST_TCONFB_PRSACT_PRS01 << 16) /**< Shifted mode PRS01 for LESENSE_ST_TCONFB */ #define LESENSE_ST_TCONFB_PRSACT_PRS2 (_LESENSE_ST_TCONFB_PRSACT_PRS2 << 16) /**< Shifted mode PRS2 for LESENSE_ST_TCONFB */ #define LESENSE_ST_TCONFB_PRSACT_PRS02 (_LESENSE_ST_TCONFB_PRSACT_PRS02 << 16) /**< Shifted mode PRS02 for LESENSE_ST_TCONFB */ #define LESENSE_ST_TCONFB_PRSACT_UPANDPRS2 (_LESENSE_ST_TCONFB_PRSACT_UPANDPRS2 << 16) /**< Shifted mode UPANDPRS2 for LESENSE_ST_TCONFB */ #define LESENSE_ST_TCONFB_PRSACT_PRS12 (_LESENSE_ST_TCONFB_PRSACT_PRS12 << 16) /**< Shifted mode PRS12 for LESENSE_ST_TCONFB */ #define LESENSE_ST_TCONFB_PRSACT_DOWNANDPRS2 (_LESENSE_ST_TCONFB_PRSACT_DOWNANDPRS2 << 16) /**< Shifted mode DOWNANDPRS2 for LESENSE_ST_TCONFB */ #define LESENSE_ST_TCONFB_PRSACT_PRS012 (_LESENSE_ST_TCONFB_PRSACT_PRS012 << 16) /**< Shifted mode PRS012 for LESENSE_ST_TCONFB */ /* Bit fields for LESENSE BUF_DATA */ #define _LESENSE_BUF_DATA_RESETVALUE 0x00000000UL /**< Default value for LESENSE_BUF_DATA */ #define _LESENSE_BUF_DATA_MASK 0x000FFFFFUL /**< Mask for LESENSE_BUF_DATA */ #define _LESENSE_BUF_DATA_DATA_SHIFT 0 /**< Shift value for LESENSE_DATA */ #define _LESENSE_BUF_DATA_DATA_MASK 0xFFFFUL /**< Bit mask for LESENSE_DATA */ #define _LESENSE_BUF_DATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_BUF_DATA */ #define LESENSE_BUF_DATA_DATA_DEFAULT (_LESENSE_BUF_DATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_BUF_DATA */ #define _LESENSE_BUF_DATA_DATASRC_SHIFT 16 /**< Shift value for LESENSE_DATASRC */ #define _LESENSE_BUF_DATA_DATASRC_MASK 0xF0000UL /**< Bit mask for LESENSE_DATASRC */ #define _LESENSE_BUF_DATA_DATASRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_BUF_DATA */ #define LESENSE_BUF_DATA_DATASRC_DEFAULT (_LESENSE_BUF_DATA_DATASRC_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_BUF_DATA */ /* Bit fields for LESENSE CH_TIMING */ #define _LESENSE_CH_TIMING_RESETVALUE 0x00000000UL /**< Default value for LESENSE_CH_TIMING */ #define _LESENSE_CH_TIMING_MASK 0x00FFFFFFUL /**< Mask for LESENSE_CH_TIMING */ #define _LESENSE_CH_TIMING_EXTIME_SHIFT 0 /**< Shift value for LESENSE_EXTIME */ #define _LESENSE_CH_TIMING_EXTIME_MASK 0x3FUL /**< Bit mask for LESENSE_EXTIME */ #define _LESENSE_CH_TIMING_EXTIME_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_TIMING */ #define LESENSE_CH_TIMING_EXTIME_DEFAULT (_LESENSE_CH_TIMING_EXTIME_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_CH_TIMING */ #define _LESENSE_CH_TIMING_SAMPLEDLY_SHIFT 6 /**< Shift value for LESENSE_SAMPLEDLY */ #define _LESENSE_CH_TIMING_SAMPLEDLY_MASK 0x3FC0UL /**< Bit mask for LESENSE_SAMPLEDLY */ #define _LESENSE_CH_TIMING_SAMPLEDLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_TIMING */ #define LESENSE_CH_TIMING_SAMPLEDLY_DEFAULT (_LESENSE_CH_TIMING_SAMPLEDLY_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_CH_TIMING */ #define _LESENSE_CH_TIMING_MEASUREDLY_SHIFT 14 /**< Shift value for LESENSE_MEASUREDLY */ #define _LESENSE_CH_TIMING_MEASUREDLY_MASK 0xFFC000UL /**< Bit mask for LESENSE_MEASUREDLY */ #define _LESENSE_CH_TIMING_MEASUREDLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_TIMING */ #define LESENSE_CH_TIMING_MEASUREDLY_DEFAULT (_LESENSE_CH_TIMING_MEASUREDLY_DEFAULT << 14) /**< Shifted mode DEFAULT for LESENSE_CH_TIMING */ /* Bit fields for LESENSE CH_INTERACT */ #define _LESENSE_CH_INTERACT_RESETVALUE 0x00000000UL /**< Default value for LESENSE_CH_INTERACT */ #define _LESENSE_CH_INTERACT_MASK 0x003FFFFFUL /**< Mask for LESENSE_CH_INTERACT */ #define _LESENSE_CH_INTERACT_THRES_SHIFT 0 /**< Shift value for LESENSE_THRES */ #define _LESENSE_CH_INTERACT_THRES_MASK 0xFFFUL /**< Bit mask for LESENSE_THRES */ #define _LESENSE_CH_INTERACT_THRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_INTERACT */ #define LESENSE_CH_INTERACT_THRES_DEFAULT (_LESENSE_CH_INTERACT_THRES_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_CH_INTERACT */ #define _LESENSE_CH_INTERACT_SAMPLE_SHIFT 12 /**< Shift value for LESENSE_SAMPLE */ #define _LESENSE_CH_INTERACT_SAMPLE_MASK 0x3000UL /**< Bit mask for LESENSE_SAMPLE */ #define _LESENSE_CH_INTERACT_SAMPLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_INTERACT */ #define _LESENSE_CH_INTERACT_SAMPLE_ACMPCOUNT 0x00000000UL /**< Mode ACMPCOUNT for LESENSE_CH_INTERACT */ #define _LESENSE_CH_INTERACT_SAMPLE_ACMP 0x00000001UL /**< Mode ACMP for LESENSE_CH_INTERACT */ #define _LESENSE_CH_INTERACT_SAMPLE_ADC 0x00000002UL /**< Mode ADC for LESENSE_CH_INTERACT */ #define _LESENSE_CH_INTERACT_SAMPLE_ADCDIFF 0x00000003UL /**< Mode ADCDIFF for LESENSE_CH_INTERACT */ #define LESENSE_CH_INTERACT_SAMPLE_DEFAULT (_LESENSE_CH_INTERACT_SAMPLE_DEFAULT << 12) /**< Shifted mode DEFAULT for LESENSE_CH_INTERACT */ #define LESENSE_CH_INTERACT_SAMPLE_ACMPCOUNT (_LESENSE_CH_INTERACT_SAMPLE_ACMPCOUNT << 12) /**< Shifted mode ACMPCOUNT for LESENSE_CH_INTERACT */ #define LESENSE_CH_INTERACT_SAMPLE_ACMP (_LESENSE_CH_INTERACT_SAMPLE_ACMP << 12) /**< Shifted mode ACMP for LESENSE_CH_INTERACT */ #define LESENSE_CH_INTERACT_SAMPLE_ADC (_LESENSE_CH_INTERACT_SAMPLE_ADC << 12) /**< Shifted mode ADC for LESENSE_CH_INTERACT */ #define LESENSE_CH_INTERACT_SAMPLE_ADCDIFF (_LESENSE_CH_INTERACT_SAMPLE_ADCDIFF << 12) /**< Shifted mode ADCDIFF for LESENSE_CH_INTERACT */ #define _LESENSE_CH_INTERACT_SETIF_SHIFT 14 /**< Shift value for LESENSE_SETIF */ #define _LESENSE_CH_INTERACT_SETIF_MASK 0x1C000UL /**< Bit mask for LESENSE_SETIF */ #define _LESENSE_CH_INTERACT_SETIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_INTERACT */ #define _LESENSE_CH_INTERACT_SETIF_NONE 0x00000000UL /**< Mode NONE for LESENSE_CH_INTERACT */ #define _LESENSE_CH_INTERACT_SETIF_LEVEL 0x00000001UL /**< Mode LEVEL for LESENSE_CH_INTERACT */ #define _LESENSE_CH_INTERACT_SETIF_POSEDGE 0x00000002UL /**< Mode POSEDGE for LESENSE_CH_INTERACT */ #define _LESENSE_CH_INTERACT_SETIF_NEGEDGE 0x00000003UL /**< Mode NEGEDGE for LESENSE_CH_INTERACT */ #define _LESENSE_CH_INTERACT_SETIF_BOTHEDGES 0x00000004UL /**< Mode BOTHEDGES for LESENSE_CH_INTERACT */ #define LESENSE_CH_INTERACT_SETIF_DEFAULT (_LESENSE_CH_INTERACT_SETIF_DEFAULT << 14) /**< Shifted mode DEFAULT for LESENSE_CH_INTERACT */ #define LESENSE_CH_INTERACT_SETIF_NONE (_LESENSE_CH_INTERACT_SETIF_NONE << 14) /**< Shifted mode NONE for LESENSE_CH_INTERACT */ #define LESENSE_CH_INTERACT_SETIF_LEVEL (_LESENSE_CH_INTERACT_SETIF_LEVEL << 14) /**< Shifted mode LEVEL for LESENSE_CH_INTERACT */ #define LESENSE_CH_INTERACT_SETIF_POSEDGE (_LESENSE_CH_INTERACT_SETIF_POSEDGE << 14) /**< Shifted mode POSEDGE for LESENSE_CH_INTERACT */ #define LESENSE_CH_INTERACT_SETIF_NEGEDGE (_LESENSE_CH_INTERACT_SETIF_NEGEDGE << 14) /**< Shifted mode NEGEDGE for LESENSE_CH_INTERACT */ #define LESENSE_CH_INTERACT_SETIF_BOTHEDGES (_LESENSE_CH_INTERACT_SETIF_BOTHEDGES << 14) /**< Shifted mode BOTHEDGES for LESENSE_CH_INTERACT */ #define _LESENSE_CH_INTERACT_EXMODE_SHIFT 17 /**< Shift value for LESENSE_EXMODE */ #define _LESENSE_CH_INTERACT_EXMODE_MASK 0x60000UL /**< Bit mask for LESENSE_EXMODE */ #define _LESENSE_CH_INTERACT_EXMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_INTERACT */ #define _LESENSE_CH_INTERACT_EXMODE_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_CH_INTERACT */ #define _LESENSE_CH_INTERACT_EXMODE_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_CH_INTERACT */ #define _LESENSE_CH_INTERACT_EXMODE_LOW 0x00000002UL /**< Mode LOW for LESENSE_CH_INTERACT */ #define _LESENSE_CH_INTERACT_EXMODE_DACOUT 0x00000003UL /**< Mode DACOUT for LESENSE_CH_INTERACT */ #define LESENSE_CH_INTERACT_EXMODE_DEFAULT (_LESENSE_CH_INTERACT_EXMODE_DEFAULT << 17) /**< Shifted mode DEFAULT for LESENSE_CH_INTERACT */ #define LESENSE_CH_INTERACT_EXMODE_DISABLE (_LESENSE_CH_INTERACT_EXMODE_DISABLE << 17) /**< Shifted mode DISABLE for LESENSE_CH_INTERACT */ #define LESENSE_CH_INTERACT_EXMODE_HIGH (_LESENSE_CH_INTERACT_EXMODE_HIGH << 17) /**< Shifted mode HIGH for LESENSE_CH_INTERACT */ #define LESENSE_CH_INTERACT_EXMODE_LOW (_LESENSE_CH_INTERACT_EXMODE_LOW << 17) /**< Shifted mode LOW for LESENSE_CH_INTERACT */ #define LESENSE_CH_INTERACT_EXMODE_DACOUT (_LESENSE_CH_INTERACT_EXMODE_DACOUT << 17) /**< Shifted mode DACOUT for LESENSE_CH_INTERACT */ #define LESENSE_CH_INTERACT_EXCLK (0x1UL << 19) /**< Select Clock Used for Excitation Timing */ #define _LESENSE_CH_INTERACT_EXCLK_SHIFT 19 /**< Shift value for LESENSE_EXCLK */ #define _LESENSE_CH_INTERACT_EXCLK_MASK 0x80000UL /**< Bit mask for LESENSE_EXCLK */ #define _LESENSE_CH_INTERACT_EXCLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_INTERACT */ #define _LESENSE_CH_INTERACT_EXCLK_LFACLK 0x00000000UL /**< Mode LFACLK for LESENSE_CH_INTERACT */ #define _LESENSE_CH_INTERACT_EXCLK_AUXHFRCO 0x00000001UL /**< Mode AUXHFRCO for LESENSE_CH_INTERACT */ #define LESENSE_CH_INTERACT_EXCLK_DEFAULT (_LESENSE_CH_INTERACT_EXCLK_DEFAULT << 19) /**< Shifted mode DEFAULT for LESENSE_CH_INTERACT */ #define LESENSE_CH_INTERACT_EXCLK_LFACLK (_LESENSE_CH_INTERACT_EXCLK_LFACLK << 19) /**< Shifted mode LFACLK for LESENSE_CH_INTERACT */ #define LESENSE_CH_INTERACT_EXCLK_AUXHFRCO (_LESENSE_CH_INTERACT_EXCLK_AUXHFRCO << 19) /**< Shifted mode AUXHFRCO for LESENSE_CH_INTERACT */ #define LESENSE_CH_INTERACT_SAMPLECLK (0x1UL << 20) /**< Select Clock Used for Timing of Sample Delay */ #define _LESENSE_CH_INTERACT_SAMPLECLK_SHIFT 20 /**< Shift value for LESENSE_SAMPLECLK */ #define _LESENSE_CH_INTERACT_SAMPLECLK_MASK 0x100000UL /**< Bit mask for LESENSE_SAMPLECLK */ #define _LESENSE_CH_INTERACT_SAMPLECLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_INTERACT */ #define _LESENSE_CH_INTERACT_SAMPLECLK_LFACLK 0x00000000UL /**< Mode LFACLK for LESENSE_CH_INTERACT */ #define _LESENSE_CH_INTERACT_SAMPLECLK_AUXHFRCO 0x00000001UL /**< Mode AUXHFRCO for LESENSE_CH_INTERACT */ #define LESENSE_CH_INTERACT_SAMPLECLK_DEFAULT (_LESENSE_CH_INTERACT_SAMPLECLK_DEFAULT << 20) /**< Shifted mode DEFAULT for LESENSE_CH_INTERACT */ #define LESENSE_CH_INTERACT_SAMPLECLK_LFACLK (_LESENSE_CH_INTERACT_SAMPLECLK_LFACLK << 20) /**< Shifted mode LFACLK for LESENSE_CH_INTERACT */ #define LESENSE_CH_INTERACT_SAMPLECLK_AUXHFRCO (_LESENSE_CH_INTERACT_SAMPLECLK_AUXHFRCO << 20) /**< Shifted mode AUXHFRCO for LESENSE_CH_INTERACT */ #define LESENSE_CH_INTERACT_ALTEX (0x1UL << 21) /**< Use Alternative Excite Pin */ #define _LESENSE_CH_INTERACT_ALTEX_SHIFT 21 /**< Shift value for LESENSE_ALTEX */ #define _LESENSE_CH_INTERACT_ALTEX_MASK 0x200000UL /**< Bit mask for LESENSE_ALTEX */ #define _LESENSE_CH_INTERACT_ALTEX_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_INTERACT */ #define LESENSE_CH_INTERACT_ALTEX_DEFAULT (_LESENSE_CH_INTERACT_ALTEX_DEFAULT << 21) /**< Shifted mode DEFAULT for LESENSE_CH_INTERACT */ /* Bit fields for LESENSE CH_EVAL */ #define _LESENSE_CH_EVAL_RESETVALUE 0x00000000UL /**< Default value for LESENSE_CH_EVAL */ #define _LESENSE_CH_EVAL_MASK 0x007FFFFFUL /**< Mask for LESENSE_CH_EVAL */ #define _LESENSE_CH_EVAL_COMPTHRES_SHIFT 0 /**< Shift value for LESENSE_COMPTHRES */ #define _LESENSE_CH_EVAL_COMPTHRES_MASK 0xFFFFUL /**< Bit mask for LESENSE_COMPTHRES */ #define _LESENSE_CH_EVAL_COMPTHRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_EVAL */ #define LESENSE_CH_EVAL_COMPTHRES_DEFAULT (_LESENSE_CH_EVAL_COMPTHRES_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_CH_EVAL */ #define LESENSE_CH_EVAL_COMP (0x1UL << 16) /**< Select Mode for Threshold Comparison */ #define _LESENSE_CH_EVAL_COMP_SHIFT 16 /**< Shift value for LESENSE_COMP */ #define _LESENSE_CH_EVAL_COMP_MASK 0x10000UL /**< Bit mask for LESENSE_COMP */ #define _LESENSE_CH_EVAL_COMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_EVAL */ #define _LESENSE_CH_EVAL_COMP_LESS 0x00000000UL /**< Mode LESS for LESENSE_CH_EVAL */ #define _LESENSE_CH_EVAL_COMP_GE 0x00000001UL /**< Mode GE for LESENSE_CH_EVAL */ #define LESENSE_CH_EVAL_COMP_DEFAULT (_LESENSE_CH_EVAL_COMP_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_CH_EVAL */ #define LESENSE_CH_EVAL_COMP_LESS (_LESENSE_CH_EVAL_COMP_LESS << 16) /**< Shifted mode LESS for LESENSE_CH_EVAL */ #define LESENSE_CH_EVAL_COMP_GE (_LESENSE_CH_EVAL_COMP_GE << 16) /**< Shifted mode GE for LESENSE_CH_EVAL */ #define LESENSE_CH_EVAL_DECODE (0x1UL << 17) /**< Send Result to Decoder */ #define _LESENSE_CH_EVAL_DECODE_SHIFT 17 /**< Shift value for LESENSE_DECODE */ #define _LESENSE_CH_EVAL_DECODE_MASK 0x20000UL /**< Bit mask for LESENSE_DECODE */ #define _LESENSE_CH_EVAL_DECODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_EVAL */ #define LESENSE_CH_EVAL_DECODE_DEFAULT (_LESENSE_CH_EVAL_DECODE_DEFAULT << 17) /**< Shifted mode DEFAULT for LESENSE_CH_EVAL */ #define _LESENSE_CH_EVAL_STRSAMPLE_SHIFT 18 /**< Shift value for LESENSE_STRSAMPLE */ #define _LESENSE_CH_EVAL_STRSAMPLE_MASK 0xC0000UL /**< Bit mask for LESENSE_STRSAMPLE */ #define _LESENSE_CH_EVAL_STRSAMPLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_EVAL */ #define _LESENSE_CH_EVAL_STRSAMPLE_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_CH_EVAL */ #define _LESENSE_CH_EVAL_STRSAMPLE_DATA 0x00000001UL /**< Mode DATA for LESENSE_CH_EVAL */ #define _LESENSE_CH_EVAL_STRSAMPLE_DATASRC 0x00000002UL /**< Mode DATASRC for LESENSE_CH_EVAL */ #define LESENSE_CH_EVAL_STRSAMPLE_DEFAULT (_LESENSE_CH_EVAL_STRSAMPLE_DEFAULT << 18) /**< Shifted mode DEFAULT for LESENSE_CH_EVAL */ #define LESENSE_CH_EVAL_STRSAMPLE_DISABLE (_LESENSE_CH_EVAL_STRSAMPLE_DISABLE << 18) /**< Shifted mode DISABLE for LESENSE_CH_EVAL */ #define LESENSE_CH_EVAL_STRSAMPLE_DATA (_LESENSE_CH_EVAL_STRSAMPLE_DATA << 18) /**< Shifted mode DATA for LESENSE_CH_EVAL */ #define LESENSE_CH_EVAL_STRSAMPLE_DATASRC (_LESENSE_CH_EVAL_STRSAMPLE_DATASRC << 18) /**< Shifted mode DATASRC for LESENSE_CH_EVAL */ #define LESENSE_CH_EVAL_SCANRESINV (0x1UL << 20) /**< Enable Inversion of Result */ #define _LESENSE_CH_EVAL_SCANRESINV_SHIFT 20 /**< Shift value for LESENSE_SCANRESINV */ #define _LESENSE_CH_EVAL_SCANRESINV_MASK 0x100000UL /**< Bit mask for LESENSE_SCANRESINV */ #define _LESENSE_CH_EVAL_SCANRESINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_EVAL */ #define LESENSE_CH_EVAL_SCANRESINV_DEFAULT (_LESENSE_CH_EVAL_SCANRESINV_DEFAULT << 20) /**< Shifted mode DEFAULT for LESENSE_CH_EVAL */ #define _LESENSE_CH_EVAL_MODE_SHIFT 21 /**< Shift value for LESENSE_MODE */ #define _LESENSE_CH_EVAL_MODE_MASK 0x600000UL /**< Bit mask for LESENSE_MODE */ #define _LESENSE_CH_EVAL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_EVAL */ #define _LESENSE_CH_EVAL_MODE_THRES 0x00000000UL /**< Mode THRES for LESENSE_CH_EVAL */ #define _LESENSE_CH_EVAL_MODE_SLIDINGWIN 0x00000001UL /**< Mode SLIDINGWIN for LESENSE_CH_EVAL */ #define _LESENSE_CH_EVAL_MODE_STEPDET 0x00000002UL /**< Mode STEPDET for LESENSE_CH_EVAL */ #define LESENSE_CH_EVAL_MODE_DEFAULT (_LESENSE_CH_EVAL_MODE_DEFAULT << 21) /**< Shifted mode DEFAULT for LESENSE_CH_EVAL */ #define LESENSE_CH_EVAL_MODE_THRES (_LESENSE_CH_EVAL_MODE_THRES << 21) /**< Shifted mode THRES for LESENSE_CH_EVAL */ #define LESENSE_CH_EVAL_MODE_SLIDINGWIN (_LESENSE_CH_EVAL_MODE_SLIDINGWIN << 21) /**< Shifted mode SLIDINGWIN for LESENSE_CH_EVAL */ #define LESENSE_CH_EVAL_MODE_STEPDET (_LESENSE_CH_EVAL_MODE_STEPDET << 21) /**< Shifted mode STEPDET for LESENSE_CH_EVAL */ /** @} */ /** @} End of group EFR32MG12P_LESENSE */ /** @} End of group Parts */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_lesense_buf.h.
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/***************************************************************************//** * @file * @brief EFR32MG12P_LESENSE_BUF register and bit field definitions * @version 5.7.0 ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * SPDX-License-Identifier: Zlib * * The licensor of this software is Silicon Laboratories Inc. * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be * appreciated but is not required. * 2. Altered source versions must be plainly marked as such, and must not be * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * ******************************************************************************/ #if defined(__ICCARM__) #pragma system_include /* Treat file as system include file. */ #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang system_header /* Treat file as system include file. */ #endif /***************************************************************************//** * @addtogroup Parts * @{ ******************************************************************************/ /***************************************************************************//** * @brief LESENSE_BUF LESENSE BUF Register * @ingroup EFR32MG12P_LESENSE ******************************************************************************/ typedef struct { __IOM uint32_t DATA; /**< Scan Results */ } LESENSE_BUF_TypeDef; /** @} End of group Parts */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_lesense_ch.h.
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/***************************************************************************//** * @file * @brief EFR32MG12P_LESENSE_CH register and bit field definitions * @version 5.7.0 ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * SPDX-License-Identifier: Zlib * * The licensor of this software is Silicon Laboratories Inc. * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be * appreciated but is not required. * 2. Altered source versions must be plainly marked as such, and must not be * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * ******************************************************************************/ #if defined(__ICCARM__) #pragma system_include /* Treat file as system include file. */ #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang system_header /* Treat file as system include file. */ #endif /***************************************************************************//** * @addtogroup Parts * @{ ******************************************************************************/ /***************************************************************************//** * @brief LESENSE_CH LESENSE CH Register * @ingroup EFR32MG12P_LESENSE ******************************************************************************/ typedef struct { __IOM uint32_t TIMING; /**< Scan Configuration */ __IOM uint32_t INTERACT; /**< Scan Configuration */ __IOM uint32_t EVAL; /**< Scan Configuration */ uint32_t RESERVED0[1U]; /**< Reserved future */ } LESENSE_CH_TypeDef; /** @} End of group Parts */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_lesense_st.h.
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/***************************************************************************//** * @file * @brief EFR32MG12P_LESENSE_ST register and bit field definitions * @version 5.7.0 ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * SPDX-License-Identifier: Zlib * * The licensor of this software is Silicon Laboratories Inc. * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be * appreciated but is not required. * 2. Altered source versions must be plainly marked as such, and must not be * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * ******************************************************************************/ #if defined(__ICCARM__) #pragma system_include /* Treat file as system include file. */ #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang system_header /* Treat file as system include file. */ #endif /***************************************************************************//** * @addtogroup Parts * @{ ******************************************************************************/ /***************************************************************************//** * @brief LESENSE_ST LESENSE ST Register * @ingroup EFR32MG12P_LESENSE ******************************************************************************/ typedef struct { __IOM uint32_t TCONFA; /**< State Transition Configuration a */ __IOM uint32_t TCONFB; /**< State Transition Configuration B */ } LESENSE_ST_TypeDef; /** @} End of group Parts */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_letimer.h.
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/***************************************************************************//** * @file * @brief EFR32MG12P_LETIMER register and bit field definitions * @version 5.7.0 ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * SPDX-License-Identifier: Zlib * * The licensor of this software is Silicon Laboratories Inc. * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be * appreciated but is not required. * 2. Altered source versions must be plainly marked as such, and must not be * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * ******************************************************************************/ #if defined(__ICCARM__) #pragma system_include /* Treat file as system include file. */ #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang system_header /* Treat file as system include file. */ #endif /***************************************************************************//** * @addtogroup Parts * @{ ******************************************************************************/ /***************************************************************************//** * @defgroup EFR32MG12P_LETIMER LETIMER * @{ * @brief EFR32MG12P_LETIMER Register Declaration ******************************************************************************/ /** LETIMER Register Declaration */ typedef struct { __IOM uint32_t CTRL; /**< Control Register */ __IOM uint32_t CMD; /**< Command Register */ __IM uint32_t STATUS; /**< Status Register */ __IOM uint32_t CNT; /**< Counter Value Register */ __IOM uint32_t COMP0; /**< Compare Value Register 0 */ __IOM uint32_t COMP1; /**< Compare Value Register 1 */ __IOM uint32_t REP0; /**< Repeat Counter Register 0 */ __IOM uint32_t REP1; /**< Repeat Counter Register 1 */ __IM uint32_t IF; /**< Interrupt Flag Register */ __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ __IOM uint32_t IEN; /**< Interrupt Enable Register */ uint32_t RESERVED0[1U]; /**< Reserved for future use **/ __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ uint32_t RESERVED1[2U]; /**< Reserved for future use **/ __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ uint32_t RESERVED2[2U]; /**< Reserved for future use **/ __IOM uint32_t PRSSEL; /**< PRS Input Select Register */ } LETIMER_TypeDef; /** @} */ /***************************************************************************//** * @addtogroup EFR32MG12P_LETIMER * @{ * @defgroup EFR32MG12P_LETIMER_BitFields LETIMER Bit Fields * @{ ******************************************************************************/ /* Bit fields for LETIMER CTRL */ #define _LETIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for LETIMER_CTRL */ #define _LETIMER_CTRL_MASK 0x000013FFUL /**< Mask for LETIMER_CTRL */ #define _LETIMER_CTRL_REPMODE_SHIFT 0 /**< Shift value for LETIMER_REPMODE */ #define _LETIMER_CTRL_REPMODE_MASK 0x3UL /**< Bit mask for LETIMER_REPMODE */ #define _LETIMER_CTRL_REPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ #define _LETIMER_CTRL_REPMODE_FREE 0x00000000UL /**< Mode FREE for LETIMER_CTRL */ #define _LETIMER_CTRL_REPMODE_ONESHOT 0x00000001UL /**< Mode ONESHOT for LETIMER_CTRL */ #define _LETIMER_CTRL_REPMODE_BUFFERED 0x00000002UL /**< Mode BUFFERED for LETIMER_CTRL */ #define _LETIMER_CTRL_REPMODE_DOUBLE 0x00000003UL /**< Mode DOUBLE for LETIMER_CTRL */ #define LETIMER_CTRL_REPMODE_DEFAULT (_LETIMER_CTRL_REPMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_CTRL */ #define LETIMER_CTRL_REPMODE_FREE (_LETIMER_CTRL_REPMODE_FREE << 0) /**< Shifted mode FREE for LETIMER_CTRL */ #define LETIMER_CTRL_REPMODE_ONESHOT (_LETIMER_CTRL_REPMODE_ONESHOT << 0) /**< Shifted mode ONESHOT for LETIMER_CTRL */ #define LETIMER_CTRL_REPMODE_BUFFERED (_LETIMER_CTRL_REPMODE_BUFFERED << 0) /**< Shifted mode BUFFERED for LETIMER_CTRL */ #define LETIMER_CTRL_REPMODE_DOUBLE (_LETIMER_CTRL_REPMODE_DOUBLE << 0) /**< Shifted mode DOUBLE for LETIMER_CTRL */ #define _LETIMER_CTRL_UFOA0_SHIFT 2 /**< Shift value for LETIMER_UFOA0 */ #define _LETIMER_CTRL_UFOA0_MASK 0xCUL /**< Bit mask for LETIMER_UFOA0 */ #define _LETIMER_CTRL_UFOA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ #define _LETIMER_CTRL_UFOA0_NONE 0x00000000UL /**< Mode NONE for LETIMER_CTRL */ #define _LETIMER_CTRL_UFOA0_TOGGLE 0x00000001UL /**< Mode TOGGLE for LETIMER_CTRL */ #define _LETIMER_CTRL_UFOA0_PULSE 0x00000002UL /**< Mode PULSE for LETIMER_CTRL */ #define _LETIMER_CTRL_UFOA0_PWM 0x00000003UL /**< Mode PWM for LETIMER_CTRL */ #define LETIMER_CTRL_UFOA0_DEFAULT (_LETIMER_CTRL_UFOA0_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_CTRL */ #define LETIMER_CTRL_UFOA0_NONE (_LETIMER_CTRL_UFOA0_NONE << 2) /**< Shifted mode NONE for LETIMER_CTRL */ #define LETIMER_CTRL_UFOA0_TOGGLE (_LETIMER_CTRL_UFOA0_TOGGLE << 2) /**< Shifted mode TOGGLE for LETIMER_CTRL */ #define LETIMER_CTRL_UFOA0_PULSE (_LETIMER_CTRL_UFOA0_PULSE << 2) /**< Shifted mode PULSE for LETIMER_CTRL */ #define LETIMER_CTRL_UFOA0_PWM (_LETIMER_CTRL_UFOA0_PWM << 2) /**< Shifted mode PWM for LETIMER_CTRL */ #define _LETIMER_CTRL_UFOA1_SHIFT 4 /**< Shift value for LETIMER_UFOA1 */ #define _LETIMER_CTRL_UFOA1_MASK 0x30UL /**< Bit mask for LETIMER_UFOA1 */ #define _LETIMER_CTRL_UFOA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ #define _LETIMER_CTRL_UFOA1_NONE 0x00000000UL /**< Mode NONE for LETIMER_CTRL */ #define _LETIMER_CTRL_UFOA1_TOGGLE 0x00000001UL /**< Mode TOGGLE for LETIMER_CTRL */ #define _LETIMER_CTRL_UFOA1_PULSE 0x00000002UL /**< Mode PULSE for LETIMER_CTRL */ #define _LETIMER_CTRL_UFOA1_PWM 0x00000003UL /**< Mode PWM for LETIMER_CTRL */ #define LETIMER_CTRL_UFOA1_DEFAULT (_LETIMER_CTRL_UFOA1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_CTRL */ #define LETIMER_CTRL_UFOA1_NONE (_LETIMER_CTRL_UFOA1_NONE << 4) /**< Shifted mode NONE for LETIMER_CTRL */ #define LETIMER_CTRL_UFOA1_TOGGLE (_LETIMER_CTRL_UFOA1_TOGGLE << 4) /**< Shifted mode TOGGLE for LETIMER_CTRL */ #define LETIMER_CTRL_UFOA1_PULSE (_LETIMER_CTRL_UFOA1_PULSE << 4) /**< Shifted mode PULSE for LETIMER_CTRL */ #define LETIMER_CTRL_UFOA1_PWM (_LETIMER_CTRL_UFOA1_PWM << 4) /**< Shifted mode PWM for LETIMER_CTRL */ #define LETIMER_CTRL_OPOL0 (0x1UL << 6) /**< Output 0 Polarity */ #define _LETIMER_CTRL_OPOL0_SHIFT 6 /**< Shift value for LETIMER_OPOL0 */ #define _LETIMER_CTRL_OPOL0_MASK 0x40UL /**< Bit mask for LETIMER_OPOL0 */ #define _LETIMER_CTRL_OPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ #define LETIMER_CTRL_OPOL0_DEFAULT (_LETIMER_CTRL_OPOL0_DEFAULT << 6) /**< Shifted mode DEFAULT for LETIMER_CTRL */ #define LETIMER_CTRL_OPOL1 (0x1UL << 7) /**< Output 1 Polarity */ #define _LETIMER_CTRL_OPOL1_SHIFT 7 /**< Shift value for LETIMER_OPOL1 */ #define _LETIMER_CTRL_OPOL1_MASK 0x80UL /**< Bit mask for LETIMER_OPOL1 */ #define _LETIMER_CTRL_OPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ #define LETIMER_CTRL_OPOL1_DEFAULT (_LETIMER_CTRL_OPOL1_DEFAULT << 7) /**< Shifted mode DEFAULT for LETIMER_CTRL */ #define LETIMER_CTRL_BUFTOP (0x1UL << 8) /**< Buffered Top */ #define _LETIMER_CTRL_BUFTOP_SHIFT 8 /**< Shift value for LETIMER_BUFTOP */ #define _LETIMER_CTRL_BUFTOP_MASK 0x100UL /**< Bit mask for LETIMER_BUFTOP */ #define _LETIMER_CTRL_BUFTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ #define LETIMER_CTRL_BUFTOP_DEFAULT (_LETIMER_CTRL_BUFTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for LETIMER_CTRL */ #define LETIMER_CTRL_COMP0TOP (0x1UL << 9) /**< Compare Value 0 is Top Value */ #define _LETIMER_CTRL_COMP0TOP_SHIFT 9 /**< Shift value for LETIMER_COMP0TOP */ #define _LETIMER_CTRL_COMP0TOP_MASK 0x200UL /**< Bit mask for LETIMER_COMP0TOP */ #define _LETIMER_CTRL_COMP0TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ #define LETIMER_CTRL_COMP0TOP_DEFAULT (_LETIMER_CTRL_COMP0TOP_DEFAULT << 9) /**< Shifted mode DEFAULT for LETIMER_CTRL */ #define LETIMER_CTRL_DEBUGRUN (0x1UL << 12) /**< Debug Mode Run Enable */ #define _LETIMER_CTRL_DEBUGRUN_SHIFT 12 /**< Shift value for LETIMER_DEBUGRUN */ #define _LETIMER_CTRL_DEBUGRUN_MASK 0x1000UL /**< Bit mask for LETIMER_DEBUGRUN */ #define _LETIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ #define LETIMER_CTRL_DEBUGRUN_DEFAULT (_LETIMER_CTRL_DEBUGRUN_DEFAULT << 12) /**< Shifted mode DEFAULT for LETIMER_CTRL */ /* Bit fields for LETIMER CMD */ #define _LETIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for LETIMER_CMD */ #define _LETIMER_CMD_MASK 0x0000001FUL /**< Mask for LETIMER_CMD */ #define LETIMER_CMD_START (0x1UL << 0) /**< Start LETIMER */ #define _LETIMER_CMD_START_SHIFT 0 /**< Shift value for LETIMER_START */ #define _LETIMER_CMD_START_MASK 0x1UL /**< Bit mask for LETIMER_START */ #define _LETIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */ #define LETIMER_CMD_START_DEFAULT (_LETIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_CMD */ #define LETIMER_CMD_STOP (0x1UL << 1) /**< Stop LETIMER */ #define _LETIMER_CMD_STOP_SHIFT 1 /**< Shift value for LETIMER_STOP */ #define _LETIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for LETIMER_STOP */ #define _LETIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */ #define LETIMER_CMD_STOP_DEFAULT (_LETIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_CMD */ #define LETIMER_CMD_CLEAR (0x1UL << 2) /**< Clear LETIMER */ #define _LETIMER_CMD_CLEAR_SHIFT 2 /**< Shift value for LETIMER_CLEAR */ #define _LETIMER_CMD_CLEAR_MASK 0x4UL /**< Bit mask for LETIMER_CLEAR */ #define _LETIMER_CMD_CLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */ #define LETIMER_CMD_CLEAR_DEFAULT (_LETIMER_CMD_CLEAR_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_CMD */ #define LETIMER_CMD_CTO0 (0x1UL << 3) /**< Clear Toggle Output 0 */ #define _LETIMER_CMD_CTO0_SHIFT 3 /**< Shift value for LETIMER_CTO0 */ #define _LETIMER_CMD_CTO0_MASK 0x8UL /**< Bit mask for LETIMER_CTO0 */ #define _LETIMER_CMD_CTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */ #define LETIMER_CMD_CTO0_DEFAULT (_LETIMER_CMD_CTO0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_CMD */ #define LETIMER_CMD_CTO1 (0x1UL << 4) /**< Clear Toggle Output 1 */ #define _LETIMER_CMD_CTO1_SHIFT 4 /**< Shift value for LETIMER_CTO1 */ #define _LETIMER_CMD_CTO1_MASK 0x10UL /**< Bit mask for LETIMER_CTO1 */ #define _LETIMER_CMD_CTO1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */ #define LETIMER_CMD_CTO1_DEFAULT (_LETIMER_CMD_CTO1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_CMD */ /* Bit fields for LETIMER STATUS */ #define _LETIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for LETIMER_STATUS */ #define _LETIMER_STATUS_MASK 0x00000001UL /**< Mask for LETIMER_STATUS */ #define LETIMER_STATUS_RUNNING (0x1UL << 0) /**< LETIMER Running */ #define _LETIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for LETIMER_RUNNING */ #define _LETIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for LETIMER_RUNNING */ #define _LETIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_STATUS */ #define LETIMER_STATUS_RUNNING_DEFAULT (_LETIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_STATUS */ /* Bit fields for LETIMER CNT */ #define _LETIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for LETIMER_CNT */ #define _LETIMER_CNT_MASK 0x0000FFFFUL /**< Mask for LETIMER_CNT */ #define _LETIMER_CNT_CNT_SHIFT 0 /**< Shift value for LETIMER_CNT */ #define _LETIMER_CNT_CNT_MASK 0xFFFFUL /**< Bit mask for LETIMER_CNT */ #define _LETIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CNT */ #define LETIMER_CNT_CNT_DEFAULT (_LETIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_CNT */ /* Bit fields for LETIMER COMP0 */ #define _LETIMER_COMP0_RESETVALUE 0x00000000UL /**< Default value for LETIMER_COMP0 */ #define _LETIMER_COMP0_MASK 0x0000FFFFUL /**< Mask for LETIMER_COMP0 */ #define _LETIMER_COMP0_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */ #define _LETIMER_COMP0_COMP0_MASK 0xFFFFUL /**< Bit mask for LETIMER_COMP0 */ #define _LETIMER_COMP0_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_COMP0 */ #define LETIMER_COMP0_COMP0_DEFAULT (_LETIMER_COMP0_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_COMP0 */ /* Bit fields for LETIMER COMP1 */ #define _LETIMER_COMP1_RESETVALUE 0x00000000UL /**< Default value for LETIMER_COMP1 */ #define _LETIMER_COMP1_MASK 0x0000FFFFUL /**< Mask for LETIMER_COMP1 */ #define _LETIMER_COMP1_COMP1_SHIFT 0 /**< Shift value for LETIMER_COMP1 */ #define _LETIMER_COMP1_COMP1_MASK 0xFFFFUL /**< Bit mask for LETIMER_COMP1 */ #define _LETIMER_COMP1_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_COMP1 */ #define LETIMER_COMP1_COMP1_DEFAULT (_LETIMER_COMP1_COMP1_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_COMP1 */ /* Bit fields for LETIMER REP0 */ #define _LETIMER_REP0_RESETVALUE 0x00000000UL /**< Default value for LETIMER_REP0 */ #define _LETIMER_REP0_MASK 0x000000FFUL /**< Mask for LETIMER_REP0 */ #define _LETIMER_REP0_REP0_SHIFT 0 /**< Shift value for LETIMER_REP0 */ #define _LETIMER_REP0_REP0_MASK 0xFFUL /**< Bit mask for LETIMER_REP0 */ #define _LETIMER_REP0_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_REP0 */ #define LETIMER_REP0_REP0_DEFAULT (_LETIMER_REP0_REP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_REP0 */ /* Bit fields for LETIMER REP1 */ #define _LETIMER_REP1_RESETVALUE 0x00000000UL /**< Default value for LETIMER_REP1 */ #define _LETIMER_REP1_MASK 0x000000FFUL /**< Mask for LETIMER_REP1 */ #define _LETIMER_REP1_REP1_SHIFT 0 /**< Shift value for LETIMER_REP1 */ #define _LETIMER_REP1_REP1_MASK 0xFFUL /**< Bit mask for LETIMER_REP1 */ #define _LETIMER_REP1_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_REP1 */ #define LETIMER_REP1_REP1_DEFAULT (_LETIMER_REP1_REP1_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_REP1 */ /* Bit fields for LETIMER IF */ #define _LETIMER_IF_RESETVALUE 0x00000000UL /**< Default value for LETIMER_IF */ #define _LETIMER_IF_MASK 0x0000001FUL /**< Mask for LETIMER_IF */ #define LETIMER_IF_COMP0 (0x1UL << 0) /**< Compare Match 0 Interrupt Flag */ #define _LETIMER_IF_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */ #define _LETIMER_IF_COMP0_MASK 0x1UL /**< Bit mask for LETIMER_COMP0 */ #define _LETIMER_IF_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */ #define LETIMER_IF_COMP0_DEFAULT (_LETIMER_IF_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_IF */ #define LETIMER_IF_COMP1 (0x1UL << 1) /**< Compare Match 1 Interrupt Flag */ #define _LETIMER_IF_COMP1_SHIFT 1 /**< Shift value for LETIMER_COMP1 */ #define _LETIMER_IF_COMP1_MASK 0x2UL /**< Bit mask for LETIMER_COMP1 */ #define _LETIMER_IF_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */ #define LETIMER_IF_COMP1_DEFAULT (_LETIMER_IF_COMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_IF */ #define LETIMER_IF_UF (0x1UL << 2) /**< Underflow Interrupt Flag */ #define _LETIMER_IF_UF_SHIFT 2 /**< Shift value for LETIMER_UF */ #define _LETIMER_IF_UF_MASK 0x4UL /**< Bit mask for LETIMER_UF */ #define _LETIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */ #define LETIMER_IF_UF_DEFAULT (_LETIMER_IF_UF_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_IF */ #define LETIMER_IF_REP0 (0x1UL << 3) /**< Repeat Counter 0 Interrupt Flag */ #define _LETIMER_IF_REP0_SHIFT 3 /**< Shift value for LETIMER_REP0 */ #define _LETIMER_IF_REP0_MASK 0x8UL /**< Bit mask for LETIMER_REP0 */ #define _LETIMER_IF_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */ #define LETIMER_IF_REP0_DEFAULT (_LETIMER_IF_REP0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_IF */ #define LETIMER_IF_REP1 (0x1UL << 4) /**< Repeat Counter 1 Interrupt Flag */ #define _LETIMER_IF_REP1_SHIFT 4 /**< Shift value for LETIMER_REP1 */ #define _LETIMER_IF_REP1_MASK 0x10UL /**< Bit mask for LETIMER_REP1 */ #define _LETIMER_IF_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */ #define LETIMER_IF_REP1_DEFAULT (_LETIMER_IF_REP1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_IF */ /* Bit fields for LETIMER IFS */ #define _LETIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for LETIMER_IFS */ #define _LETIMER_IFS_MASK 0x0000001FUL /**< Mask for LETIMER_IFS */ #define LETIMER_IFS_COMP0 (0x1UL << 0) /**< Set COMP0 Interrupt Flag */ #define _LETIMER_IFS_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */ #define _LETIMER_IFS_COMP0_MASK 0x1UL /**< Bit mask for LETIMER_COMP0 */ #define _LETIMER_IFS_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFS */ #define LETIMER_IFS_COMP0_DEFAULT (_LETIMER_IFS_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_IFS */ #define LETIMER_IFS_COMP1 (0x1UL << 1) /**< Set COMP1 Interrupt Flag */ #define _LETIMER_IFS_COMP1_SHIFT 1 /**< Shift value for LETIMER_COMP1 */ #define _LETIMER_IFS_COMP1_MASK 0x2UL /**< Bit mask for LETIMER_COMP1 */ #define _LETIMER_IFS_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFS */ #define LETIMER_IFS_COMP1_DEFAULT (_LETIMER_IFS_COMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_IFS */ #define LETIMER_IFS_UF (0x1UL << 2) /**< Set UF Interrupt Flag */ #define _LETIMER_IFS_UF_SHIFT 2 /**< Shift value for LETIMER_UF */ #define _LETIMER_IFS_UF_MASK 0x4UL /**< Bit mask for LETIMER_UF */ #define _LETIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFS */ #define LETIMER_IFS_UF_DEFAULT (_LETIMER_IFS_UF_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_IFS */ #define LETIMER_IFS_REP0 (0x1UL << 3) /**< Set REP0 Interrupt Flag */ #define _LETIMER_IFS_REP0_SHIFT 3 /**< Shift value for LETIMER_REP0 */ #define _LETIMER_IFS_REP0_MASK 0x8UL /**< Bit mask for LETIMER_REP0 */ #define _LETIMER_IFS_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFS */ #define LETIMER_IFS_REP0_DEFAULT (_LETIMER_IFS_REP0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_IFS */ #define LETIMER_IFS_REP1 (0x1UL << 4) /**< Set REP1 Interrupt Flag */ #define _LETIMER_IFS_REP1_SHIFT 4 /**< Shift value for LETIMER_REP1 */ #define _LETIMER_IFS_REP1_MASK 0x10UL /**< Bit mask for LETIMER_REP1 */ #define _LETIMER_IFS_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFS */ #define LETIMER_IFS_REP1_DEFAULT (_LETIMER_IFS_REP1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_IFS */ /* Bit fields for LETIMER IFC */ #define _LETIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for LETIMER_IFC */ #define _LETIMER_IFC_MASK 0x0000001FUL /**< Mask for LETIMER_IFC */ #define LETIMER_IFC_COMP0 (0x1UL << 0) /**< Clear COMP0 Interrupt Flag */ #define _LETIMER_IFC_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */ #define _LETIMER_IFC_COMP0_MASK 0x1UL /**< Bit mask for LETIMER_COMP0 */ #define _LETIMER_IFC_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFC */ #define LETIMER_IFC_COMP0_DEFAULT (_LETIMER_IFC_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_IFC */ #define LETIMER_IFC_COMP1 (0x1UL << 1) /**< Clear COMP1 Interrupt Flag */ #define _LETIMER_IFC_COMP1_SHIFT 1 /**< Shift value for LETIMER_COMP1 */ #define _LETIMER_IFC_COMP1_MASK 0x2UL /**< Bit mask for LETIMER_COMP1 */ #define _LETIMER_IFC_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFC */ #define LETIMER_IFC_COMP1_DEFAULT (_LETIMER_IFC_COMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_IFC */ #define LETIMER_IFC_UF (0x1UL << 2) /**< Clear UF Interrupt Flag */ #define _LETIMER_IFC_UF_SHIFT 2 /**< Shift value for LETIMER_UF */ #define _LETIMER_IFC_UF_MASK 0x4UL /**< Bit mask for LETIMER_UF */ #define _LETIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFC */ #define LETIMER_IFC_UF_DEFAULT (_LETIMER_IFC_UF_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_IFC */ #define LETIMER_IFC_REP0 (0x1UL << 3) /**< Clear REP0 Interrupt Flag */ #define _LETIMER_IFC_REP0_SHIFT 3 /**< Shift value for LETIMER_REP0 */ #define _LETIMER_IFC_REP0_MASK 0x8UL /**< Bit mask for LETIMER_REP0 */ #define _LETIMER_IFC_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFC */ #define LETIMER_IFC_REP0_DEFAULT (_LETIMER_IFC_REP0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_IFC */ #define LETIMER_IFC_REP1 (0x1UL << 4) /**< Clear REP1 Interrupt Flag */ #define _LETIMER_IFC_REP1_SHIFT 4 /**< Shift value for LETIMER_REP1 */ #define _LETIMER_IFC_REP1_MASK 0x10UL /**< Bit mask for LETIMER_REP1 */ #define _LETIMER_IFC_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFC */ #define LETIMER_IFC_REP1_DEFAULT (_LETIMER_IFC_REP1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_IFC */ /* Bit fields for LETIMER IEN */ #define _LETIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for LETIMER_IEN */ #define _LETIMER_IEN_MASK 0x0000001FUL /**< Mask for LETIMER_IEN */ #define LETIMER_IEN_COMP0 (0x1UL << 0) /**< COMP0 Interrupt Enable */ #define _LETIMER_IEN_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */ #define _LETIMER_IEN_COMP0_MASK 0x1UL /**< Bit mask for LETIMER_COMP0 */ #define _LETIMER_IEN_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */ #define LETIMER_IEN_COMP0_DEFAULT (_LETIMER_IEN_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_IEN */ #define LETIMER_IEN_COMP1 (0x1UL << 1) /**< COMP1 Interrupt Enable */ #define _LETIMER_IEN_COMP1_SHIFT 1 /**< Shift value for LETIMER_COMP1 */ #define _LETIMER_IEN_COMP1_MASK 0x2UL /**< Bit mask for LETIMER_COMP1 */ #define _LETIMER_IEN_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */ #define LETIMER_IEN_COMP1_DEFAULT (_LETIMER_IEN_COMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_IEN */ #define LETIMER_IEN_UF (0x1UL << 2) /**< UF Interrupt Enable */ #define _LETIMER_IEN_UF_SHIFT 2 /**< Shift value for LETIMER_UF */ #define _LETIMER_IEN_UF_MASK 0x4UL /**< Bit mask for LETIMER_UF */ #define _LETIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */ #define LETIMER_IEN_UF_DEFAULT (_LETIMER_IEN_UF_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_IEN */ #define LETIMER_IEN_REP0 (0x1UL << 3) /**< REP0 Interrupt Enable */ #define _LETIMER_IEN_REP0_SHIFT 3 /**< Shift value for LETIMER_REP0 */ #define _LETIMER_IEN_REP0_MASK 0x8UL /**< Bit mask for LETIMER_REP0 */ #define _LETIMER_IEN_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */ #define LETIMER_IEN_REP0_DEFAULT (_LETIMER_IEN_REP0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_IEN */ #define LETIMER_IEN_REP1 (0x1UL << 4) /**< REP1 Interrupt Enable */ #define _LETIMER_IEN_REP1_SHIFT 4 /**< Shift value for LETIMER_REP1 */ #define _LETIMER_IEN_REP1_MASK 0x10UL /**< Bit mask for LETIMER_REP1 */ #define _LETIMER_IEN_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */ #define LETIMER_IEN_REP1_DEFAULT (_LETIMER_IEN_REP1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_IEN */ /* Bit fields for LETIMER SYNCBUSY */ #define _LETIMER_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for LETIMER_SYNCBUSY */ #define _LETIMER_SYNCBUSY_MASK 0x00000002UL /**< Mask for LETIMER_SYNCBUSY */ #define LETIMER_SYNCBUSY_CMD (0x1UL << 1) /**< CMD Register Busy */ #define _LETIMER_SYNCBUSY_CMD_SHIFT 1 /**< Shift value for LETIMER_CMD */ #define _LETIMER_SYNCBUSY_CMD_MASK 0x2UL /**< Bit mask for LETIMER_CMD */ #define _LETIMER_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ #define LETIMER_SYNCBUSY_CMD_DEFAULT (_LETIMER_SYNCBUSY_CMD_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ /* Bit fields for LETIMER ROUTEPEN */ #define _LETIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for LETIMER_ROUTEPEN */ #define _LETIMER_ROUTEPEN_MASK 0x00000003UL /**< Mask for LETIMER_ROUTEPEN */ #define LETIMER_ROUTEPEN_OUT0PEN (0x1UL << 0) /**< Output 0 Pin Enable */ #define _LETIMER_ROUTEPEN_OUT0PEN_SHIFT 0 /**< Shift value for LETIMER_OUT0PEN */ #define _LETIMER_ROUTEPEN_OUT0PEN_MASK 0x1UL /**< Bit mask for LETIMER_OUT0PEN */ #define _LETIMER_ROUTEPEN_OUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_ROUTEPEN */ #define LETIMER_ROUTEPEN_OUT0PEN_DEFAULT (_LETIMER_ROUTEPEN_OUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_ROUTEPEN */ #define LETIMER_ROUTEPEN_OUT1PEN (0x1UL << 1) /**< Output 1 Pin Enable */ #define _LETIMER_ROUTEPEN_OUT1PEN_SHIFT 1 /**< Shift value for LETIMER_OUT1PEN */ #define _LETIMER_ROUTEPEN_OUT1PEN_MASK 0x2UL /**< Bit mask for LETIMER_OUT1PEN */ #define _LETIMER_ROUTEPEN_OUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_ROUTEPEN */ #define LETIMER_ROUTEPEN_OUT1PEN_DEFAULT (_LETIMER_ROUTEPEN_OUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_ROUTEPEN */ /* Bit fields for LETIMER ROUTELOC0 */ #define _LETIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for LETIMER_ROUTELOC0 */ #define _LETIMER_ROUTELOC0_MASK 0x00001F1FUL /**< Mask for LETIMER_ROUTELOC0 */ #define _LETIMER_ROUTELOC0_OUT0LOC_SHIFT 0 /**< Shift value for LETIMER_OUT0LOC */ #define _LETIMER_ROUTELOC0_OUT0LOC_MASK 0x1FUL /**< Bit mask for LETIMER_OUT0LOC */ #define _LETIMER_ROUTELOC0_OUT0LOC_LOC0 0x00000000UL /**< Mode LOC0 for LETIMER_ROUTELOC0 */ #define _LETIMER_ROUTELOC0_OUT0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_ROUTELOC0 */ #define _LETIMER_ROUTELOC0_OUT0LOC_LOC1 0x00000001UL /**< Mode LOC1 for LETIMER_ROUTELOC0 */ #define _LETIMER_ROUTELOC0_OUT0LOC_LOC2 0x00000002UL /**< Mode LOC2 for LETIMER_ROUTELOC0 */ #define _LETIMER_ROUTELOC0_OUT0LOC_LOC3 0x00000003UL /**< Mode LOC3 for LETIMER_ROUTELOC0 */ #define _LETIMER_ROUTELOC0_OUT0LOC_LOC4 0x00000004UL /**< Mode LOC4 for LETIMER_ROUTELOC0 */ #define _LETIMER_ROUTELOC0_OUT0LOC_LOC5 0x00000005UL /**< Mode LOC5 for LETIMER_ROUTELOC0 */ #define _LETIMER_ROUTELOC0_OUT0LOC_LOC6 0x00000006UL /**< Mode LOC6 for LETIMER_ROUTELOC0 */ #define _LETIMER_ROUTELOC0_OUT0LOC_LOC7 0x00000007UL /**< Mode LOC7 for LETIMER_ROUTELOC0 */ #define _LETIMER_ROUTELOC0_OUT0LOC_LOC8 0x00000008UL /**< Mode LOC8 for LETIMER_ROUTELOC0 */ #define _LETIMER_ROUTELOC0_OUT0LOC_LOC9 0x00000009UL /**< Mode LOC9 for LETIMER_ROUTELOC0 */ #define _LETIMER_ROUTELOC0_OUT0LOC_LOC10 0x0000000AUL /**< Mode LOC10 for LETIMER_ROUTELOC0 */ #define _LETIMER_ROUTELOC0_OUT0LOC_LOC11 0x0000000BUL /**< Mode LOC11 for LETIMER_ROUTELOC0 */ #define _LETIMER_ROUTELOC0_OUT0LOC_LOC12 0x0000000CUL /**< Mode LOC12 for LETIMER_ROUTELOC0 */ #define _LETIMER_ROUTELOC0_OUT0LOC_LOC13 0x0000000DUL /**< Mode LOC13 for LETIMER_ROUTELOC0 */ #define _LETIMER_ROUTELOC0_OUT0LOC_LOC14 0x0000000EUL /**< Mode LOC14 for LETIMER_ROUTELOC0 */ #define _LETIMER_ROUTELOC0_OUT0LOC_LOC15 0x0000000FUL /**< Mode LOC15 for LETIMER_ROUTELOC0 */ #define _LETIMER_ROUTELOC0_OUT0LOC_LOC16 0x00000010UL /**< Mode LOC16 for LETIMER_ROUTELOC0 */ #define _LETIMER_ROUTELOC0_OUT0LOC_LOC17 0x00000011UL /**< Mode LOC17 for LETIMER_ROUTELOC0 */ #define _LETIMER_ROUTELOC0_OUT0LOC_LOC18 0x00000012UL /**< Mode LOC18 for LETIMER_ROUTELOC0 */ #define _LETIMER_ROUTELOC0_OUT0LOC_LOC19 0x00000013UL /**< Mode LOC19 for LETIMER_ROUTELOC0 */ #define _LETIMER_ROUTELOC0_OUT0LOC_LOC20 0x00000014UL /**< Mode LOC20 for LETIMER_ROUTELOC0 */ #define _LETIMER_ROUTELOC0_OUT0LOC_LOC21 0x00000015UL /**< Mode LOC21 for LETIMER_ROUTELOC0 */ #define _LETIMER_ROUTELOC0_OUT0LOC_LOC22 0x00000016UL /**< Mode LOC22 for LETIMER_ROUTELOC0 */ #define _LETIMER_ROUTELOC0_OUT0LOC_LOC23 0x00000017UL /**< Mode LOC23 for LETIMER_ROUTELOC0 */ #define _LETIMER_ROUTELOC0_OUT0LOC_LOC24 0x00000018UL /**< Mode LOC24 for LETIMER_ROUTELOC0 */ #define _LETIMER_ROUTELOC0_OUT0LOC_LOC25 0x00000019UL /**< Mode LOC25 for LETIMER_ROUTELOC0 */ #define _LETIMER_ROUTELOC0_OUT0LOC_LOC26 0x0000001AUL /**< Mode LOC26 for LETIMER_ROUTELOC0 */ #define _LETIMER_ROUTELOC0_OUT0LOC_LOC27 0x0000001BUL /**< Mode LOC27 for LETIMER_ROUTELOC0 */ #define _LETIMER_ROUTELOC0_OUT0LOC_LOC28 0x0000001CUL /**< Mode LOC28 for LETIMER_ROUTELOC0 */ #define _LETIMER_ROUTELOC0_OUT0LOC_LOC29 0x0000001DUL /**< Mode LOC29 for LETIMER_ROUTELOC0 */ #define _LETIMER_ROUTELOC0_OUT0LOC_LOC30 0x0000001EUL /**< Mode LOC30 for LETIMER_ROUTELOC0 */ #define _LETIMER_ROUTELOC0_OUT0LOC_LOC31 0x0000001FUL /**< Mode LOC31 for LETIMER_ROUTELOC0 */ #define LETIMER_ROUTELOC0_OUT0LOC_LOC0 (_LETIMER_ROUTELOC0_OUT0LOC_LOC0 << 0) /**< Shifted mode LOC0 for LETIMER_ROUTELOC0 */ #define LETIMER_ROUTELOC0_OUT0LOC_DEFAULT (_LETIMER_ROUTELOC0_OUT0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_ROUTELOC0 */ #define LETIMER_ROUTELOC0_OUT0LOC_LOC1 (_LETIMER_ROUTELOC0_OUT0LOC_LOC1 << 0) /**< Shifted mode LOC1 for LETIMER_ROUTELOC0 */ #define LETIMER_ROUTELOC0_OUT0LOC_LOC2 (_LETIMER_ROUTELOC0_OUT0LOC_LOC2 << 0) /**< Shifted mode LOC2 for LETIMER_ROUTELOC0 */ #define LETIMER_ROUTELOC0_OUT0LOC_LOC3 (_LETIMER_ROUTELOC0_OUT0LOC_LOC3 << 0) /**< Shifted mode LOC3 for LETIMER_ROUTELOC0 */ #define LETIMER_ROUTELOC0_OUT0LOC_LOC4 (_LETIMER_ROUTELOC0_OUT0LOC_LOC4 << 0) /**< Shifted mode LOC4 for LETIMER_ROUTELOC0 */ #define LETIMER_ROUTELOC0_OUT0LOC_LOC5 (_LETIMER_ROUTELOC0_OUT0LOC_LOC5 << 0) /**< Shifted mode LOC5 for LETIMER_ROUTELOC0 */ #define LETIMER_ROUTELOC0_OUT0LOC_LOC6 (_LETIMER_ROUTELOC0_OUT0LOC_LOC6 << 0) /**< Shifted mode LOC6 for LETIMER_ROUTELOC0 */ #define LETIMER_ROUTELOC0_OUT0LOC_LOC7 (_LETIMER_ROUTELOC0_OUT0LOC_LOC7 << 0) /**< Shifted mode LOC7 for LETIMER_ROUTELOC0 */ #define LETIMER_ROUTELOC0_OUT0LOC_LOC8 (_LETIMER_ROUTELOC0_OUT0LOC_LOC8 << 0) /**< Shifted mode LOC8 for LETIMER_ROUTELOC0 */ #define LETIMER_ROUTELOC0_OUT0LOC_LOC9 (_LETIMER_ROUTELOC0_OUT0LOC_LOC9 << 0) /**< Shifted mode LOC9 for LETIMER_ROUTELOC0 */ #define LETIMER_ROUTELOC0_OUT0LOC_LOC10 (_LETIMER_ROUTELOC0_OUT0LOC_LOC10 << 0) /**< Shifted mode LOC10 for LETIMER_ROUTELOC0 */ #define LETIMER_ROUTELOC0_OUT0LOC_LOC11 (_LETIMER_ROUTELOC0_OUT0LOC_LOC11 << 0) /**< Shifted mode LOC11 for LETIMER_ROUTELOC0 */ #define LETIMER_ROUTELOC0_OUT0LOC_LOC12 (_LETIMER_ROUTELOC0_OUT0LOC_LOC12 << 0) /**< Shifted mode LOC12 for LETIMER_ROUTELOC0 */ #define LETIMER_ROUTELOC0_OUT0LOC_LOC13 (_LETIMER_ROUTELOC0_OUT0LOC_LOC13 << 0) /**< Shifted mode LOC13 for LETIMER_ROUTELOC0 */ #define LETIMER_ROUTELOC0_OUT0LOC_LOC14 (_LETIMER_ROUTELOC0_OUT0LOC_LOC14 << 0) /**< Shifted mode LOC14 for LETIMER_ROUTELOC0 */ #define LETIMER_ROUTELOC0_OUT0LOC_LOC15 (_LETIMER_ROUTELOC0_OUT0LOC_LOC15 << 0) /**< Shifted mode LOC15 for LETIMER_ROUTELOC0 */ #define LETIMER_ROUTELOC0_OUT0LOC_LOC16 (_LETIMER_ROUTELOC0_OUT0LOC_LOC16 << 0) /**< Shifted mode LOC16 for LETIMER_ROUTELOC0 */ #define LETIMER_ROUTELOC0_OUT0LOC_LOC17 (_LETIMER_ROUTELOC0_OUT0LOC_LOC17 << 0) /**< Shifted mode LOC17 for LETIMER_ROUTELOC0 */ #define LETIMER_ROUTELOC0_OUT0LOC_LOC18 (_LETIMER_ROUTELOC0_OUT0LOC_LOC18 << 0) /**< Shifted mode LOC18 for LETIMER_ROUTELOC0 */ #define LETIMER_ROUTELOC0_OUT0LOC_LOC19 (_LETIMER_ROUTELOC0_OUT0LOC_LOC19 << 0) /**< Shifted mode LOC19 for LETIMER_ROUTELOC0 */ #define LETIMER_ROUTELOC0_OUT0LOC_LOC20 (_LETIMER_ROUTELOC0_OUT0LOC_LOC20 << 0) /**< Shifted mode LOC20 for LETIMER_ROUTELOC0 */ #define LETIMER_ROUTELOC0_OUT0LOC_LOC21 (_LETIMER_ROUTELOC0_OUT0LOC_LOC21 << 0) /**< Shifted mode LOC21 for LETIMER_ROUTELOC0 */ #define LETIMER_ROUTELOC0_OUT0LOC_LOC22 (_LETIMER_ROUTELOC0_OUT0LOC_LOC22 << 0) /**< Shifted mode LOC22 for LETIMER_ROUTELOC0 */ #define LETIMER_ROUTELOC0_OUT0LOC_LOC23 (_LETIMER_ROUTELOC0_OUT0LOC_LOC23 << 0) /**< Shifted mode LOC23 for LETIMER_ROUTELOC0 */ #define LETIMER_ROUTELOC0_OUT0LOC_LOC24 (_LETIMER_ROUTELOC0_OUT0LOC_LOC24 << 0) /**< Shifted mode LOC24 for LETIMER_ROUTELOC0 */ #define LETIMER_ROUTELOC0_OUT0LOC_LOC25 (_LETIMER_ROUTELOC0_OUT0LOC_LOC25 << 0) /**< Shifted mode LOC25 for LETIMER_ROUTELOC0 */ #define LETIMER_ROUTELOC0_OUT0LOC_LOC26 (_LETIMER_ROUTELOC0_OUT0LOC_LOC26 << 0) /**< Shifted mode LOC26 for LETIMER_ROUTELOC0 */ #define LETIMER_ROUTELOC0_OUT0LOC_LOC27 (_LETIMER_ROUTELOC0_OUT0LOC_LOC27 << 0) /**< Shifted mode LOC27 for LETIMER_ROUTELOC0 */ #define LETIMER_ROUTELOC0_OUT0LOC_LOC28 (_LETIMER_ROUTELOC0_OUT0LOC_LOC28 << 0) /**< Shifted mode LOC28 for LETIMER_ROUTELOC0 */ #define LETIMER_ROUTELOC0_OUT0LOC_LOC29 (_LETIMER_ROUTELOC0_OUT0LOC_LOC29 << 0) /**< Shifted mode LOC29 for LETIMER_ROUTELOC0 */ #define LETIMER_ROUTELOC0_OUT0LOC_LOC30 (_LETIMER_ROUTELOC0_OUT0LOC_LOC30 << 0) /**< Shifted mode LOC30 for LETIMER_ROUTELOC0 */ #define LETIMER_ROUTELOC0_OUT0LOC_LOC31 (_LETIMER_ROUTELOC0_OUT0LOC_LOC31 << 0) /**< Shifted mode LOC31 for LETIMER_ROUTELOC0 */ #define _LETIMER_ROUTELOC0_OUT1LOC_SHIFT 8 /**< Shift value for LETIMER_OUT1LOC */ #define _LETIMER_ROUTELOC0_OUT1LOC_MASK 0x1F00UL /**< Bit mask for LETIMER_OUT1LOC */ #define _LETIMER_ROUTELOC0_OUT1LOC_LOC0 0x00000000UL /**< Mode LOC0 for LETIMER_ROUTELOC0 */ #define _LETIMER_ROUTELOC0_OUT1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_ROUTELOC0 */ #define _LETIMER_ROUTELOC0_OUT1LOC_LOC1 0x00000001UL /**< Mode LOC1 for LETIMER_ROUTELOC0 */ #define _LETIMER_ROUTELOC0_OUT1LOC_LOC2 0x00000002UL /**< Mode LOC2 for LETIMER_ROUTELOC0 */ #define _LETIMER_ROUTELOC0_OUT1LOC_LOC3 0x00000003UL /**< Mode LOC3 for LETIMER_ROUTELOC0 */ #define _LETIMER_ROUTELOC0_OUT1LOC_LOC4 0x00000004UL /**< Mode LOC4 for LETIMER_ROUTELOC0 */ #define _LETIMER_ROUTELOC0_OUT1LOC_LOC5 0x00000005UL /**< Mode LOC5 for LETIMER_ROUTELOC0 */ #define _LETIMER_ROUTELOC0_OUT1LOC_LOC6 0x00000006UL /**< Mode LOC6 for LETIMER_ROUTELOC0 */ #define _LETIMER_ROUTELOC0_OUT1LOC_LOC7 0x00000007UL /**< Mode LOC7 for LETIMER_ROUTELOC0 */ #define _LETIMER_ROUTELOC0_OUT1LOC_LOC8 0x00000008UL /**< Mode LOC8 for LETIMER_ROUTELOC0 */ #define _LETIMER_ROUTELOC0_OUT1LOC_LOC9 0x00000009UL /**< Mode LOC9 for LETIMER_ROUTELOC0 */ #define _LETIMER_ROUTELOC0_OUT1LOC_LOC10 0x0000000AUL /**< Mode LOC10 for LETIMER_ROUTELOC0 */ #define _LETIMER_ROUTELOC0_OUT1LOC_LOC11 0x0000000BUL /**< Mode LOC11 for LETIMER_ROUTELOC0 */ #define _LETIMER_ROUTELOC0_OUT1LOC_LOC12 0x0000000CUL /**< Mode LOC12 for LETIMER_ROUTELOC0 */ #define _LETIMER_ROUTELOC0_OUT1LOC_LOC13 0x0000000DUL /**< Mode LOC13 for LETIMER_ROUTELOC0 */ #define _LETIMER_ROUTELOC0_OUT1LOC_LOC14 0x0000000EUL /**< Mode LOC14 for LETIMER_ROUTELOC0 */ #define _LETIMER_ROUTELOC0_OUT1LOC_LOC15 0x0000000FUL /**< Mode LOC15 for LETIMER_ROUTELOC0 */ #define _LETIMER_ROUTELOC0_OUT1LOC_LOC16 0x00000010UL /**< Mode LOC16 for LETIMER_ROUTELOC0 */ #define _LETIMER_ROUTELOC0_OUT1LOC_LOC17 0x00000011UL /**< Mode LOC17 for LETIMER_ROUTELOC0 */ #define _LETIMER_ROUTELOC0_OUT1LOC_LOC18 0x00000012UL /**< Mode LOC18 for LETIMER_ROUTELOC0 */ #define _LETIMER_ROUTELOC0_OUT1LOC_LOC19 0x00000013UL /**< Mode LOC19 for LETIMER_ROUTELOC0 */ #define _LETIMER_ROUTELOC0_OUT1LOC_LOC20 0x00000014UL /**< Mode LOC20 for LETIMER_ROUTELOC0 */ #define _LETIMER_ROUTELOC0_OUT1LOC_LOC21 0x00000015UL /**< Mode LOC21 for LETIMER_ROUTELOC0 */ #define _LETIMER_ROUTELOC0_OUT1LOC_LOC22 0x00000016UL /**< Mode LOC22 for LETIMER_ROUTELOC0 */ #define _LETIMER_ROUTELOC0_OUT1LOC_LOC23 0x00000017UL /**< Mode LOC23 for LETIMER_ROUTELOC0 */ #define _LETIMER_ROUTELOC0_OUT1LOC_LOC24 0x00000018UL /**< Mode LOC24 for LETIMER_ROUTELOC0 */ #define _LETIMER_ROUTELOC0_OUT1LOC_LOC25 0x00000019UL /**< Mode LOC25 for LETIMER_ROUTELOC0 */ #define _LETIMER_ROUTELOC0_OUT1LOC_LOC26 0x0000001AUL /**< Mode LOC26 for LETIMER_ROUTELOC0 */ #define _LETIMER_ROUTELOC0_OUT1LOC_LOC27 0x0000001BUL /**< Mode LOC27 for LETIMER_ROUTELOC0 */ #define _LETIMER_ROUTELOC0_OUT1LOC_LOC28 0x0000001CUL /**< Mode LOC28 for LETIMER_ROUTELOC0 */ #define _LETIMER_ROUTELOC0_OUT1LOC_LOC29 0x0000001DUL /**< Mode LOC29 for LETIMER_ROUTELOC0 */ #define _LETIMER_ROUTELOC0_OUT1LOC_LOC30 0x0000001EUL /**< Mode LOC30 for LETIMER_ROUTELOC0 */ #define _LETIMER_ROUTELOC0_OUT1LOC_LOC31 0x0000001FUL /**< Mode LOC31 for LETIMER_ROUTELOC0 */ #define LETIMER_ROUTELOC0_OUT1LOC_LOC0 (_LETIMER_ROUTELOC0_OUT1LOC_LOC0 << 8) /**< Shifted mode LOC0 for LETIMER_ROUTELOC0 */ #define LETIMER_ROUTELOC0_OUT1LOC_DEFAULT (_LETIMER_ROUTELOC0_OUT1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for LETIMER_ROUTELOC0 */ #define LETIMER_ROUTELOC0_OUT1LOC_LOC1 (_LETIMER_ROUTELOC0_OUT1LOC_LOC1 << 8) /**< Shifted mode LOC1 for LETIMER_ROUTELOC0 */ #define LETIMER_ROUTELOC0_OUT1LOC_LOC2 (_LETIMER_ROUTELOC0_OUT1LOC_LOC2 << 8) /**< Shifted mode LOC2 for LETIMER_ROUTELOC0 */ #define LETIMER_ROUTELOC0_OUT1LOC_LOC3 (_LETIMER_ROUTELOC0_OUT1LOC_LOC3 << 8) /**< Shifted mode LOC3 for LETIMER_ROUTELOC0 */ #define LETIMER_ROUTELOC0_OUT1LOC_LOC4 (_LETIMER_ROUTELOC0_OUT1LOC_LOC4 << 8) /**< Shifted mode LOC4 for LETIMER_ROUTELOC0 */ #define LETIMER_ROUTELOC0_OUT1LOC_LOC5 (_LETIMER_ROUTELOC0_OUT1LOC_LOC5 << 8) /**< Shifted mode LOC5 for LETIMER_ROUTELOC0 */ #define LETIMER_ROUTELOC0_OUT1LOC_LOC6 (_LETIMER_ROUTELOC0_OUT1LOC_LOC6 << 8) /**< Shifted mode LOC6 for LETIMER_ROUTELOC0 */ #define LETIMER_ROUTELOC0_OUT1LOC_LOC7 (_LETIMER_ROUTELOC0_OUT1LOC_LOC7 << 8) /**< Shifted mode LOC7 for LETIMER_ROUTELOC0 */ #define LETIMER_ROUTELOC0_OUT1LOC_LOC8 (_LETIMER_ROUTELOC0_OUT1LOC_LOC8 << 8) /**< Shifted mode LOC8 for LETIMER_ROUTELOC0 */ #define LETIMER_ROUTELOC0_OUT1LOC_LOC9 (_LETIMER_ROUTELOC0_OUT1LOC_LOC9 << 8) /**< Shifted mode LOC9 for LETIMER_ROUTELOC0 */ #define LETIMER_ROUTELOC0_OUT1LOC_LOC10 (_LETIMER_ROUTELOC0_OUT1LOC_LOC10 << 8) /**< Shifted mode LOC10 for LETIMER_ROUTELOC0 */ #define LETIMER_ROUTELOC0_OUT1LOC_LOC11 (_LETIMER_ROUTELOC0_OUT1LOC_LOC11 << 8) /**< Shifted mode LOC11 for LETIMER_ROUTELOC0 */ #define LETIMER_ROUTELOC0_OUT1LOC_LOC12 (_LETIMER_ROUTELOC0_OUT1LOC_LOC12 << 8) /**< Shifted mode LOC12 for LETIMER_ROUTELOC0 */ #define LETIMER_ROUTELOC0_OUT1LOC_LOC13 (_LETIMER_ROUTELOC0_OUT1LOC_LOC13 << 8) /**< Shifted mode LOC13 for LETIMER_ROUTELOC0 */ #define LETIMER_ROUTELOC0_OUT1LOC_LOC14 (_LETIMER_ROUTELOC0_OUT1LOC_LOC14 << 8) /**< Shifted mode LOC14 for LETIMER_ROUTELOC0 */ #define LETIMER_ROUTELOC0_OUT1LOC_LOC15 (_LETIMER_ROUTELOC0_OUT1LOC_LOC15 << 8) /**< Shifted mode LOC15 for LETIMER_ROUTELOC0 */ #define LETIMER_ROUTELOC0_OUT1LOC_LOC16 (_LETIMER_ROUTELOC0_OUT1LOC_LOC16 << 8) /**< Shifted mode LOC16 for LETIMER_ROUTELOC0 */ #define LETIMER_ROUTELOC0_OUT1LOC_LOC17 (_LETIMER_ROUTELOC0_OUT1LOC_LOC17 << 8) /**< Shifted mode LOC17 for LETIMER_ROUTELOC0 */ #define LETIMER_ROUTELOC0_OUT1LOC_LOC18 (_LETIMER_ROUTELOC0_OUT1LOC_LOC18 << 8) /**< Shifted mode LOC18 for LETIMER_ROUTELOC0 */ #define LETIMER_ROUTELOC0_OUT1LOC_LOC19 (_LETIMER_ROUTELOC0_OUT1LOC_LOC19 << 8) /**< Shifted mode LOC19 for LETIMER_ROUTELOC0 */ #define LETIMER_ROUTELOC0_OUT1LOC_LOC20 (_LETIMER_ROUTELOC0_OUT1LOC_LOC20 << 8) /**< Shifted mode LOC20 for LETIMER_ROUTELOC0 */ #define LETIMER_ROUTELOC0_OUT1LOC_LOC21 (_LETIMER_ROUTELOC0_OUT1LOC_LOC21 << 8) /**< Shifted mode LOC21 for LETIMER_ROUTELOC0 */ #define LETIMER_ROUTELOC0_OUT1LOC_LOC22 (_LETIMER_ROUTELOC0_OUT1LOC_LOC22 << 8) /**< Shifted mode LOC22 for LETIMER_ROUTELOC0 */ #define LETIMER_ROUTELOC0_OUT1LOC_LOC23 (_LETIMER_ROUTELOC0_OUT1LOC_LOC23 << 8) /**< Shifted mode LOC23 for LETIMER_ROUTELOC0 */ #define LETIMER_ROUTELOC0_OUT1LOC_LOC24 (_LETIMER_ROUTELOC0_OUT1LOC_LOC24 << 8) /**< Shifted mode LOC24 for LETIMER_ROUTELOC0 */ #define LETIMER_ROUTELOC0_OUT1LOC_LOC25 (_LETIMER_ROUTELOC0_OUT1LOC_LOC25 << 8) /**< Shifted mode LOC25 for LETIMER_ROUTELOC0 */ #define LETIMER_ROUTELOC0_OUT1LOC_LOC26 (_LETIMER_ROUTELOC0_OUT1LOC_LOC26 << 8) /**< Shifted mode LOC26 for LETIMER_ROUTELOC0 */ #define LETIMER_ROUTELOC0_OUT1LOC_LOC27 (_LETIMER_ROUTELOC0_OUT1LOC_LOC27 << 8) /**< Shifted mode LOC27 for LETIMER_ROUTELOC0 */ #define LETIMER_ROUTELOC0_OUT1LOC_LOC28 (_LETIMER_ROUTELOC0_OUT1LOC_LOC28 << 8) /**< Shifted mode LOC28 for LETIMER_ROUTELOC0 */ #define LETIMER_ROUTELOC0_OUT1LOC_LOC29 (_LETIMER_ROUTELOC0_OUT1LOC_LOC29 << 8) /**< Shifted mode LOC29 for LETIMER_ROUTELOC0 */ #define LETIMER_ROUTELOC0_OUT1LOC_LOC30 (_LETIMER_ROUTELOC0_OUT1LOC_LOC30 << 8) /**< Shifted mode LOC30 for LETIMER_ROUTELOC0 */ #define LETIMER_ROUTELOC0_OUT1LOC_LOC31 (_LETIMER_ROUTELOC0_OUT1LOC_LOC31 << 8) /**< Shifted mode LOC31 for LETIMER_ROUTELOC0 */ /* Bit fields for LETIMER PRSSEL */ #define _LETIMER_PRSSEL_RESETVALUE 0x00000000UL /**< Default value for LETIMER_PRSSEL */ #define _LETIMER_PRSSEL_MASK 0x0CCCF3CFUL /**< Mask for LETIMER_PRSSEL */ #define _LETIMER_PRSSEL_PRSSTARTSEL_SHIFT 0 /**< Shift value for LETIMER_PRSSTARTSEL */ #define _LETIMER_PRSSEL_PRSSTARTSEL_MASK 0xFUL /**< Bit mask for LETIMER_PRSSTARTSEL */ #define _LETIMER_PRSSEL_PRSSTARTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_PRSSEL */ #define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for LETIMER_PRSSEL */ #define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for LETIMER_PRSSEL */ #define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for LETIMER_PRSSEL */ #define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for LETIMER_PRSSEL */ #define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for LETIMER_PRSSEL */ #define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for LETIMER_PRSSEL */ #define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for LETIMER_PRSSEL */ #define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for LETIMER_PRSSEL */ #define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for LETIMER_PRSSEL */ #define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for LETIMER_PRSSEL */ #define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for LETIMER_PRSSEL */ #define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for LETIMER_PRSSEL */ #define LETIMER_PRSSEL_PRSSTARTSEL_DEFAULT (_LETIMER_PRSSEL_PRSSTARTSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_PRSSEL */ #define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH0 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for LETIMER_PRSSEL */ #define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH1 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for LETIMER_PRSSEL */ #define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH2 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for LETIMER_PRSSEL */ #define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH3 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for LETIMER_PRSSEL */ #define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH4 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for LETIMER_PRSSEL */ #define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH5 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for LETIMER_PRSSEL */ #define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH6 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for LETIMER_PRSSEL */ #define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH7 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for LETIMER_PRSSEL */ #define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH8 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for LETIMER_PRSSEL */ #define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH9 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for LETIMER_PRSSEL */ #define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH10 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for LETIMER_PRSSEL */ #define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH11 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for LETIMER_PRSSEL */ #define _LETIMER_PRSSEL_PRSSTOPSEL_SHIFT 6 /**< Shift value for LETIMER_PRSSTOPSEL */ #define _LETIMER_PRSSEL_PRSSTOPSEL_MASK 0x3C0UL /**< Bit mask for LETIMER_PRSSTOPSEL */ #define _LETIMER_PRSSEL_PRSSTOPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_PRSSEL */ #define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for LETIMER_PRSSEL */ #define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for LETIMER_PRSSEL */ #define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for LETIMER_PRSSEL */ #define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for LETIMER_PRSSEL */ #define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for LETIMER_PRSSEL */ #define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for LETIMER_PRSSEL */ #define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for LETIMER_PRSSEL */ #define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for LETIMER_PRSSEL */ #define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for LETIMER_PRSSEL */ #define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for LETIMER_PRSSEL */ #define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for LETIMER_PRSSEL */ #define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for LETIMER_PRSSEL */ #define LETIMER_PRSSEL_PRSSTOPSEL_DEFAULT (_LETIMER_PRSSEL_PRSSTOPSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for LETIMER_PRSSEL */ #define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH0 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for LETIMER_PRSSEL */ #define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH1 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for LETIMER_PRSSEL */ #define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH2 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for LETIMER_PRSSEL */ #define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH3 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for LETIMER_PRSSEL */ #define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH4 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for LETIMER_PRSSEL */ #define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH5 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for LETIMER_PRSSEL */ #define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH6 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for LETIMER_PRSSEL */ #define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH7 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for LETIMER_PRSSEL */ #define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH8 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for LETIMER_PRSSEL */ #define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH9 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for LETIMER_PRSSEL */ #define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH10 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for LETIMER_PRSSEL */ #define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH11 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for LETIMER_PRSSEL */ #define _LETIMER_PRSSEL_PRSCLEARSEL_SHIFT 12 /**< Shift value for LETIMER_PRSCLEARSEL */ #define _LETIMER_PRSSEL_PRSCLEARSEL_MASK 0xF000UL /**< Bit mask for LETIMER_PRSCLEARSEL */ #define _LETIMER_PRSSEL_PRSCLEARSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_PRSSEL */ #define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for LETIMER_PRSSEL */ #define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for LETIMER_PRSSEL */ #define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for LETIMER_PRSSEL */ #define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for LETIMER_PRSSEL */ #define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for LETIMER_PRSSEL */ #define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for LETIMER_PRSSEL */ #define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for LETIMER_PRSSEL */ #define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for LETIMER_PRSSEL */ #define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for LETIMER_PRSSEL */ #define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for LETIMER_PRSSEL */ #define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for LETIMER_PRSSEL */ #define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for LETIMER_PRSSEL */ #define LETIMER_PRSSEL_PRSCLEARSEL_DEFAULT (_LETIMER_PRSSEL_PRSCLEARSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for LETIMER_PRSSEL */ #define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH0 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH0 << 12) /**< Shifted mode PRSCH0 for LETIMER_PRSSEL */ #define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH1 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH1 << 12) /**< Shifted mode PRSCH1 for LETIMER_PRSSEL */ #define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH2 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH2 << 12) /**< Shifted mode PRSCH2 for LETIMER_PRSSEL */ #define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH3 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH3 << 12) /**< Shifted mode PRSCH3 for LETIMER_PRSSEL */ #define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH4 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH4 << 12) /**< Shifted mode PRSCH4 for LETIMER_PRSSEL */ #define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH5 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH5 << 12) /**< Shifted mode PRSCH5 for LETIMER_PRSSEL */ #define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH6 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH6 << 12) /**< Shifted mode PRSCH6 for LETIMER_PRSSEL */ #define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH7 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH7 << 12) /**< Shifted mode PRSCH7 for LETIMER_PRSSEL */ #define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH8 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH8 << 12) /**< Shifted mode PRSCH8 for LETIMER_PRSSEL */ #define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH9 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH9 << 12) /**< Shifted mode PRSCH9 for LETIMER_PRSSEL */ #define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH10 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH10 << 12) /**< Shifted mode PRSCH10 for LETIMER_PRSSEL */ #define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH11 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH11 << 12) /**< Shifted mode PRSCH11 for LETIMER_PRSSEL */ #define _LETIMER_PRSSEL_PRSSTARTMODE_SHIFT 18 /**< Shift value for LETIMER_PRSSTARTMODE */ #define _LETIMER_PRSSEL_PRSSTARTMODE_MASK 0xC0000UL /**< Bit mask for LETIMER_PRSSTARTMODE */ #define _LETIMER_PRSSEL_PRSSTARTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_PRSSEL */ #define _LETIMER_PRSSEL_PRSSTARTMODE_NONE 0x00000000UL /**< Mode NONE for LETIMER_PRSSEL */ #define _LETIMER_PRSSEL_PRSSTARTMODE_RISING 0x00000001UL /**< Mode RISING for LETIMER_PRSSEL */ #define _LETIMER_PRSSEL_PRSSTARTMODE_FALLING 0x00000002UL /**< Mode FALLING for LETIMER_PRSSEL */ #define _LETIMER_PRSSEL_PRSSTARTMODE_BOTH 0x00000003UL /**< Mode BOTH for LETIMER_PRSSEL */ #define LETIMER_PRSSEL_PRSSTARTMODE_DEFAULT (_LETIMER_PRSSEL_PRSSTARTMODE_DEFAULT << 18) /**< Shifted mode DEFAULT for LETIMER_PRSSEL */ #define LETIMER_PRSSEL_PRSSTARTMODE_NONE (_LETIMER_PRSSEL_PRSSTARTMODE_NONE << 18) /**< Shifted mode NONE for LETIMER_PRSSEL */ #define LETIMER_PRSSEL_PRSSTARTMODE_RISING (_LETIMER_PRSSEL_PRSSTARTMODE_RISING << 18) /**< Shifted mode RISING for LETIMER_PRSSEL */ #define LETIMER_PRSSEL_PRSSTARTMODE_FALLING (_LETIMER_PRSSEL_PRSSTARTMODE_FALLING << 18) /**< Shifted mode FALLING for LETIMER_PRSSEL */ #define LETIMER_PRSSEL_PRSSTARTMODE_BOTH (_LETIMER_PRSSEL_PRSSTARTMODE_BOTH << 18) /**< Shifted mode BOTH for LETIMER_PRSSEL */ #define _LETIMER_PRSSEL_PRSSTOPMODE_SHIFT 22 /**< Shift value for LETIMER_PRSSTOPMODE */ #define _LETIMER_PRSSEL_PRSSTOPMODE_MASK 0xC00000UL /**< Bit mask for LETIMER_PRSSTOPMODE */ #define _LETIMER_PRSSEL_PRSSTOPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_PRSSEL */ #define _LETIMER_PRSSEL_PRSSTOPMODE_NONE 0x00000000UL /**< Mode NONE for LETIMER_PRSSEL */ #define _LETIMER_PRSSEL_PRSSTOPMODE_RISING 0x00000001UL /**< Mode RISING for LETIMER_PRSSEL */ #define _LETIMER_PRSSEL_PRSSTOPMODE_FALLING 0x00000002UL /**< Mode FALLING for LETIMER_PRSSEL */ #define _LETIMER_PRSSEL_PRSSTOPMODE_BOTH 0x00000003UL /**< Mode BOTH for LETIMER_PRSSEL */ #define LETIMER_PRSSEL_PRSSTOPMODE_DEFAULT (_LETIMER_PRSSEL_PRSSTOPMODE_DEFAULT << 22) /**< Shifted mode DEFAULT for LETIMER_PRSSEL */ #define LETIMER_PRSSEL_PRSSTOPMODE_NONE (_LETIMER_PRSSEL_PRSSTOPMODE_NONE << 22) /**< Shifted mode NONE for LETIMER_PRSSEL */ #define LETIMER_PRSSEL_PRSSTOPMODE_RISING (_LETIMER_PRSSEL_PRSSTOPMODE_RISING << 22) /**< Shifted mode RISING for LETIMER_PRSSEL */ #define LETIMER_PRSSEL_PRSSTOPMODE_FALLING (_LETIMER_PRSSEL_PRSSTOPMODE_FALLING << 22) /**< Shifted mode FALLING for LETIMER_PRSSEL */ #define LETIMER_PRSSEL_PRSSTOPMODE_BOTH (_LETIMER_PRSSEL_PRSSTOPMODE_BOTH << 22) /**< Shifted mode BOTH for LETIMER_PRSSEL */ #define _LETIMER_PRSSEL_PRSCLEARMODE_SHIFT 26 /**< Shift value for LETIMER_PRSCLEARMODE */ #define _LETIMER_PRSSEL_PRSCLEARMODE_MASK 0xC000000UL /**< Bit mask for LETIMER_PRSCLEARMODE */ #define _LETIMER_PRSSEL_PRSCLEARMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_PRSSEL */ #define _LETIMER_PRSSEL_PRSCLEARMODE_NONE 0x00000000UL /**< Mode NONE for LETIMER_PRSSEL */ #define _LETIMER_PRSSEL_PRSCLEARMODE_RISING 0x00000001UL /**< Mode RISING for LETIMER_PRSSEL */ #define _LETIMER_PRSSEL_PRSCLEARMODE_FALLING 0x00000002UL /**< Mode FALLING for LETIMER_PRSSEL */ #define _LETIMER_PRSSEL_PRSCLEARMODE_BOTH 0x00000003UL /**< Mode BOTH for LETIMER_PRSSEL */ #define LETIMER_PRSSEL_PRSCLEARMODE_DEFAULT (_LETIMER_PRSSEL_PRSCLEARMODE_DEFAULT << 26) /**< Shifted mode DEFAULT for LETIMER_PRSSEL */ #define LETIMER_PRSSEL_PRSCLEARMODE_NONE (_LETIMER_PRSSEL_PRSCLEARMODE_NONE << 26) /**< Shifted mode NONE for LETIMER_PRSSEL */ #define LETIMER_PRSSEL_PRSCLEARMODE_RISING (_LETIMER_PRSSEL_PRSCLEARMODE_RISING << 26) /**< Shifted mode RISING for LETIMER_PRSSEL */ #define LETIMER_PRSSEL_PRSCLEARMODE_FALLING (_LETIMER_PRSSEL_PRSCLEARMODE_FALLING << 26) /**< Shifted mode FALLING for LETIMER_PRSSEL */ #define LETIMER_PRSSEL_PRSCLEARMODE_BOTH (_LETIMER_PRSSEL_PRSCLEARMODE_BOTH << 26) /**< Shifted mode BOTH for LETIMER_PRSSEL */ /** @} */ /** @} End of group EFR32MG12P_LETIMER */ /** @} End of group Parts */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_leuart.h.
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/***************************************************************************//** * @file * @brief EFR32MG12P_LEUART register and bit field definitions * @version 5.7.0 ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * SPDX-License-Identifier: Zlib * * The licensor of this software is Silicon Laboratories Inc. * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be * appreciated but is not required. * 2. Altered source versions must be plainly marked as such, and must not be * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * ******************************************************************************/ #if defined(__ICCARM__) #pragma system_include /* Treat file as system include file. */ #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang system_header /* Treat file as system include file. */ #endif /***************************************************************************//** * @addtogroup Parts * @{ ******************************************************************************/ /***************************************************************************//** * @defgroup EFR32MG12P_LEUART LEUART * @{ * @brief EFR32MG12P_LEUART Register Declaration ******************************************************************************/ /** LEUART Register Declaration */ typedef struct { __IOM uint32_t CTRL; /**< Control Register */ __IOM uint32_t CMD; /**< Command Register */ __IM uint32_t STATUS; /**< Status Register */ __IOM uint32_t CLKDIV; /**< Clock Control Register */ __IOM uint32_t STARTFRAME; /**< Start Frame Register */ __IOM uint32_t SIGFRAME; /**< Signal Frame Register */ __IM uint32_t RXDATAX; /**< Receive Buffer Data Extended Register */ __IM uint32_t RXDATA; /**< Receive Buffer Data Register */ __IM uint32_t RXDATAXP; /**< Receive Buffer Data Extended Peek Register */ __IOM uint32_t TXDATAX; /**< Transmit Buffer Data Extended Register */ __IOM uint32_t TXDATA; /**< Transmit Buffer Data Register */ __IM uint32_t IF; /**< Interrupt Flag Register */ __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ __IOM uint32_t IEN; /**< Interrupt Enable Register */ __IOM uint32_t PULSECTRL; /**< Pulse Control Register */ __IOM uint32_t FREEZE; /**< Freeze Register */ __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ uint32_t RESERVED0[3U]; /**< Reserved for future use **/ __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ uint32_t RESERVED1[2U]; /**< Reserved for future use **/ __IOM uint32_t INPUT; /**< LEUART Input Register */ } LEUART_TypeDef; /** @} */ /***************************************************************************//** * @addtogroup EFR32MG12P_LEUART * @{ * @defgroup EFR32MG12P_LEUART_BitFields LEUART Bit Fields * @{ ******************************************************************************/ /* Bit fields for LEUART CTRL */ #define _LEUART_CTRL_RESETVALUE 0x00000000UL /**< Default value for LEUART_CTRL */ #define _LEUART_CTRL_MASK 0x0000FFFFUL /**< Mask for LEUART_CTRL */ #define LEUART_CTRL_AUTOTRI (0x1UL << 0) /**< Automatic Transmitter Tristate */ #define _LEUART_CTRL_AUTOTRI_SHIFT 0 /**< Shift value for LEUART_AUTOTRI */ #define _LEUART_CTRL_AUTOTRI_MASK 0x1UL /**< Bit mask for LEUART_AUTOTRI */ #define _LEUART_CTRL_AUTOTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ #define LEUART_CTRL_AUTOTRI_DEFAULT (_LEUART_CTRL_AUTOTRI_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_CTRL */ #define LEUART_CTRL_DATABITS (0x1UL << 1) /**< Data-Bit Mode */ #define _LEUART_CTRL_DATABITS_SHIFT 1 /**< Shift value for LEUART_DATABITS */ #define _LEUART_CTRL_DATABITS_MASK 0x2UL /**< Bit mask for LEUART_DATABITS */ #define _LEUART_CTRL_DATABITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ #define _LEUART_CTRL_DATABITS_EIGHT 0x00000000UL /**< Mode EIGHT for LEUART_CTRL */ #define _LEUART_CTRL_DATABITS_NINE 0x00000001UL /**< Mode NINE for LEUART_CTRL */ #define LEUART_CTRL_DATABITS_DEFAULT (_LEUART_CTRL_DATABITS_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_CTRL */ #define LEUART_CTRL_DATABITS_EIGHT (_LEUART_CTRL_DATABITS_EIGHT << 1) /**< Shifted mode EIGHT for LEUART_CTRL */ #define LEUART_CTRL_DATABITS_NINE (_LEUART_CTRL_DATABITS_NINE << 1) /**< Shifted mode NINE for LEUART_CTRL */ #define _LEUART_CTRL_PARITY_SHIFT 2 /**< Shift value for LEUART_PARITY */ #define _LEUART_CTRL_PARITY_MASK 0xCUL /**< Bit mask for LEUART_PARITY */ #define _LEUART_CTRL_PARITY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ #define _LEUART_CTRL_PARITY_NONE 0x00000000UL /**< Mode NONE for LEUART_CTRL */ #define _LEUART_CTRL_PARITY_EVEN 0x00000002UL /**< Mode EVEN for LEUART_CTRL */ #define _LEUART_CTRL_PARITY_ODD 0x00000003UL /**< Mode ODD for LEUART_CTRL */ #define LEUART_CTRL_PARITY_DEFAULT (_LEUART_CTRL_PARITY_DEFAULT << 2) /**< Shifted mode DEFAULT for LEUART_CTRL */ #define LEUART_CTRL_PARITY_NONE (_LEUART_CTRL_PARITY_NONE << 2) /**< Shifted mode NONE for LEUART_CTRL */ #define LEUART_CTRL_PARITY_EVEN (_LEUART_CTRL_PARITY_EVEN << 2) /**< Shifted mode EVEN for LEUART_CTRL */ #define LEUART_CTRL_PARITY_ODD (_LEUART_CTRL_PARITY_ODD << 2) /**< Shifted mode ODD for LEUART_CTRL */ #define LEUART_CTRL_STOPBITS (0x1UL << 4) /**< Stop-Bit Mode */ #define _LEUART_CTRL_STOPBITS_SHIFT 4 /**< Shift value for LEUART_STOPBITS */ #define _LEUART_CTRL_STOPBITS_MASK 0x10UL /**< Bit mask for LEUART_STOPBITS */ #define _LEUART_CTRL_STOPBITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ #define _LEUART_CTRL_STOPBITS_ONE 0x00000000UL /**< Mode ONE for LEUART_CTRL */ #define _LEUART_CTRL_STOPBITS_TWO 0x00000001UL /**< Mode TWO for LEUART_CTRL */ #define LEUART_CTRL_STOPBITS_DEFAULT (_LEUART_CTRL_STOPBITS_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_CTRL */ #define LEUART_CTRL_STOPBITS_ONE (_LEUART_CTRL_STOPBITS_ONE << 4) /**< Shifted mode ONE for LEUART_CTRL */ #define LEUART_CTRL_STOPBITS_TWO (_LEUART_CTRL_STOPBITS_TWO << 4) /**< Shifted mode TWO for LEUART_CTRL */ #define LEUART_CTRL_INV (0x1UL << 5) /**< Invert Input and Output */ #define _LEUART_CTRL_INV_SHIFT 5 /**< Shift value for LEUART_INV */ #define _LEUART_CTRL_INV_MASK 0x20UL /**< Bit mask for LEUART_INV */ #define _LEUART_CTRL_INV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ #define LEUART_CTRL_INV_DEFAULT (_LEUART_CTRL_INV_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_CTRL */ #define LEUART_CTRL_ERRSDMA (0x1UL << 6) /**< Clear RX DMA on Error */ #define _LEUART_CTRL_ERRSDMA_SHIFT 6 /**< Shift value for LEUART_ERRSDMA */ #define _LEUART_CTRL_ERRSDMA_MASK 0x40UL /**< Bit mask for LEUART_ERRSDMA */ #define _LEUART_CTRL_ERRSDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ #define LEUART_CTRL_ERRSDMA_DEFAULT (_LEUART_CTRL_ERRSDMA_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_CTRL */ #define LEUART_CTRL_LOOPBK (0x1UL << 7) /**< Loopback Enable */ #define _LEUART_CTRL_LOOPBK_SHIFT 7 /**< Shift value for LEUART_LOOPBK */ #define _LEUART_CTRL_LOOPBK_MASK 0x80UL /**< Bit mask for LEUART_LOOPBK */ #define _LEUART_CTRL_LOOPBK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ #define LEUART_CTRL_LOOPBK_DEFAULT (_LEUART_CTRL_LOOPBK_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_CTRL */ #define LEUART_CTRL_SFUBRX (0x1UL << 8) /**< Start-Frame UnBlock RX */ #define _LEUART_CTRL_SFUBRX_SHIFT 8 /**< Shift value for LEUART_SFUBRX */ #define _LEUART_CTRL_SFUBRX_MASK 0x100UL /**< Bit mask for LEUART_SFUBRX */ #define _LEUART_CTRL_SFUBRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ #define LEUART_CTRL_SFUBRX_DEFAULT (_LEUART_CTRL_SFUBRX_DEFAULT << 8) /**< Shifted mode DEFAULT for LEUART_CTRL */ #define LEUART_CTRL_MPM (0x1UL << 9) /**< Multi-Processor Mode */ #define _LEUART_CTRL_MPM_SHIFT 9 /**< Shift value for LEUART_MPM */ #define _LEUART_CTRL_MPM_MASK 0x200UL /**< Bit mask for LEUART_MPM */ #define _LEUART_CTRL_MPM_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ #define LEUART_CTRL_MPM_DEFAULT (_LEUART_CTRL_MPM_DEFAULT << 9) /**< Shifted mode DEFAULT for LEUART_CTRL */ #define LEUART_CTRL_MPAB (0x1UL << 10) /**< Multi-Processor Address-Bit */ #define _LEUART_CTRL_MPAB_SHIFT 10 /**< Shift value for LEUART_MPAB */ #define _LEUART_CTRL_MPAB_MASK 0x400UL /**< Bit mask for LEUART_MPAB */ #define _LEUART_CTRL_MPAB_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ #define LEUART_CTRL_MPAB_DEFAULT (_LEUART_CTRL_MPAB_DEFAULT << 10) /**< Shifted mode DEFAULT for LEUART_CTRL */ #define LEUART_CTRL_BIT8DV (0x1UL << 11) /**< Bit 8 Default Value */ #define _LEUART_CTRL_BIT8DV_SHIFT 11 /**< Shift value for LEUART_BIT8DV */ #define _LEUART_CTRL_BIT8DV_MASK 0x800UL /**< Bit mask for LEUART_BIT8DV */ #define _LEUART_CTRL_BIT8DV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ #define LEUART_CTRL_BIT8DV_DEFAULT (_LEUART_CTRL_BIT8DV_DEFAULT << 11) /**< Shifted mode DEFAULT for LEUART_CTRL */ #define LEUART_CTRL_RXDMAWU (0x1UL << 12) /**< RX DMA Wakeup */ #define _LEUART_CTRL_RXDMAWU_SHIFT 12 /**< Shift value for LEUART_RXDMAWU */ #define _LEUART_CTRL_RXDMAWU_MASK 0x1000UL /**< Bit mask for LEUART_RXDMAWU */ #define _LEUART_CTRL_RXDMAWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ #define LEUART_CTRL_RXDMAWU_DEFAULT (_LEUART_CTRL_RXDMAWU_DEFAULT << 12) /**< Shifted mode DEFAULT for LEUART_CTRL */ #define LEUART_CTRL_TXDMAWU (0x1UL << 13) /**< TX DMA Wakeup */ #define _LEUART_CTRL_TXDMAWU_SHIFT 13 /**< Shift value for LEUART_TXDMAWU */ #define _LEUART_CTRL_TXDMAWU_MASK 0x2000UL /**< Bit mask for LEUART_TXDMAWU */ #define _LEUART_CTRL_TXDMAWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ #define LEUART_CTRL_TXDMAWU_DEFAULT (_LEUART_CTRL_TXDMAWU_DEFAULT << 13) /**< Shifted mode DEFAULT for LEUART_CTRL */ #define _LEUART_CTRL_TXDELAY_SHIFT 14 /**< Shift value for LEUART_TXDELAY */ #define _LEUART_CTRL_TXDELAY_MASK 0xC000UL /**< Bit mask for LEUART_TXDELAY */ #define _LEUART_CTRL_TXDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ #define _LEUART_CTRL_TXDELAY_NONE 0x00000000UL /**< Mode NONE for LEUART_CTRL */ #define _LEUART_CTRL_TXDELAY_SINGLE 0x00000001UL /**< Mode SINGLE for LEUART_CTRL */ #define _LEUART_CTRL_TXDELAY_DOUBLE 0x00000002UL /**< Mode DOUBLE for LEUART_CTRL */ #define _LEUART_CTRL_TXDELAY_TRIPLE 0x00000003UL /**< Mode TRIPLE for LEUART_CTRL */ #define LEUART_CTRL_TXDELAY_DEFAULT (_LEUART_CTRL_TXDELAY_DEFAULT << 14) /**< Shifted mode DEFAULT for LEUART_CTRL */ #define LEUART_CTRL_TXDELAY_NONE (_LEUART_CTRL_TXDELAY_NONE << 14) /**< Shifted mode NONE for LEUART_CTRL */ #define LEUART_CTRL_TXDELAY_SINGLE (_LEUART_CTRL_TXDELAY_SINGLE << 14) /**< Shifted mode SINGLE for LEUART_CTRL */ #define LEUART_CTRL_TXDELAY_DOUBLE (_LEUART_CTRL_TXDELAY_DOUBLE << 14) /**< Shifted mode DOUBLE for LEUART_CTRL */ #define LEUART_CTRL_TXDELAY_TRIPLE (_LEUART_CTRL_TXDELAY_TRIPLE << 14) /**< Shifted mode TRIPLE for LEUART_CTRL */ /* Bit fields for LEUART CMD */ #define _LEUART_CMD_RESETVALUE 0x00000000UL /**< Default value for LEUART_CMD */ #define _LEUART_CMD_MASK 0x000000FFUL /**< Mask for LEUART_CMD */ #define LEUART_CMD_RXEN (0x1UL << 0) /**< Receiver Enable */ #define _LEUART_CMD_RXEN_SHIFT 0 /**< Shift value for LEUART_RXEN */ #define _LEUART_CMD_RXEN_MASK 0x1UL /**< Bit mask for LEUART_RXEN */ #define _LEUART_CMD_RXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */ #define LEUART_CMD_RXEN_DEFAULT (_LEUART_CMD_RXEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_CMD */ #define LEUART_CMD_RXDIS (0x1UL << 1) /**< Receiver Disable */ #define _LEUART_CMD_RXDIS_SHIFT 1 /**< Shift value for LEUART_RXDIS */ #define _LEUART_CMD_RXDIS_MASK 0x2UL /**< Bit mask for LEUART_RXDIS */ #define _LEUART_CMD_RXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */ #define LEUART_CMD_RXDIS_DEFAULT (_LEUART_CMD_RXDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_CMD */ #define LEUART_CMD_TXEN (0x1UL << 2) /**< Transmitter Enable */ #define _LEUART_CMD_TXEN_SHIFT 2 /**< Shift value for LEUART_TXEN */ #define _LEUART_CMD_TXEN_MASK 0x4UL /**< Bit mask for LEUART_TXEN */ #define _LEUART_CMD_TXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */ #define LEUART_CMD_TXEN_DEFAULT (_LEUART_CMD_TXEN_DEFAULT << 2) /**< Shifted mode DEFAULT for LEUART_CMD */ #define LEUART_CMD_TXDIS (0x1UL << 3) /**< Transmitter Disable */ #define _LEUART_CMD_TXDIS_SHIFT 3 /**< Shift value for LEUART_TXDIS */ #define _LEUART_CMD_TXDIS_MASK 0x8UL /**< Bit mask for LEUART_TXDIS */ #define _LEUART_CMD_TXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */ #define LEUART_CMD_TXDIS_DEFAULT (_LEUART_CMD_TXDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_CMD */ #define LEUART_CMD_RXBLOCKEN (0x1UL << 4) /**< Receiver Block Enable */ #define _LEUART_CMD_RXBLOCKEN_SHIFT 4 /**< Shift value for LEUART_RXBLOCKEN */ #define _LEUART_CMD_RXBLOCKEN_MASK 0x10UL /**< Bit mask for LEUART_RXBLOCKEN */ #define _LEUART_CMD_RXBLOCKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */ #define LEUART_CMD_RXBLOCKEN_DEFAULT (_LEUART_CMD_RXBLOCKEN_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_CMD */ #define LEUART_CMD_RXBLOCKDIS (0x1UL << 5) /**< Receiver Block Disable */ #define _LEUART_CMD_RXBLOCKDIS_SHIFT 5 /**< Shift value for LEUART_RXBLOCKDIS */ #define _LEUART_CMD_RXBLOCKDIS_MASK 0x20UL /**< Bit mask for LEUART_RXBLOCKDIS */ #define _LEUART_CMD_RXBLOCKDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */ #define LEUART_CMD_RXBLOCKDIS_DEFAULT (_LEUART_CMD_RXBLOCKDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_CMD */ #define LEUART_CMD_CLEARTX (0x1UL << 6) /**< Clear TX */ #define _LEUART_CMD_CLEARTX_SHIFT 6 /**< Shift value for LEUART_CLEARTX */ #define _LEUART_CMD_CLEARTX_MASK 0x40UL /**< Bit mask for LEUART_CLEARTX */ #define _LEUART_CMD_CLEARTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */ #define LEUART_CMD_CLEARTX_DEFAULT (_LEUART_CMD_CLEARTX_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_CMD */ #define LEUART_CMD_CLEARRX (0x1UL << 7) /**< Clear RX */ #define _LEUART_CMD_CLEARRX_SHIFT 7 /**< Shift value for LEUART_CLEARRX */ #define _LEUART_CMD_CLEARRX_MASK 0x80UL /**< Bit mask for LEUART_CLEARRX */ #define _LEUART_CMD_CLEARRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */ #define LEUART_CMD_CLEARRX_DEFAULT (_LEUART_CMD_CLEARRX_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_CMD */ /* Bit fields for LEUART STATUS */ #define _LEUART_STATUS_RESETVALUE 0x00000050UL /**< Default value for LEUART_STATUS */ #define _LEUART_STATUS_MASK 0x0000007FUL /**< Mask for LEUART_STATUS */ #define LEUART_STATUS_RXENS (0x1UL << 0) /**< Receiver Enable Status */ #define _LEUART_STATUS_RXENS_SHIFT 0 /**< Shift value for LEUART_RXENS */ #define _LEUART_STATUS_RXENS_MASK 0x1UL /**< Bit mask for LEUART_RXENS */ #define _LEUART_STATUS_RXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_STATUS */ #define LEUART_STATUS_RXENS_DEFAULT (_LEUART_STATUS_RXENS_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_STATUS */ #define LEUART_STATUS_TXENS (0x1UL << 1) /**< Transmitter Enable Status */ #define _LEUART_STATUS_TXENS_SHIFT 1 /**< Shift value for LEUART_TXENS */ #define _LEUART_STATUS_TXENS_MASK 0x2UL /**< Bit mask for LEUART_TXENS */ #define _LEUART_STATUS_TXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_STATUS */ #define LEUART_STATUS_TXENS_DEFAULT (_LEUART_STATUS_TXENS_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_STATUS */ #define LEUART_STATUS_RXBLOCK (0x1UL << 2) /**< Block Incoming Data */ #define _LEUART_STATUS_RXBLOCK_SHIFT 2 /**< Shift value for LEUART_RXBLOCK */ #define _LEUART_STATUS_RXBLOCK_MASK 0x4UL /**< Bit mask for LEUART_RXBLOCK */ #define _LEUART_STATUS_RXBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_STATUS */ #define LEUART_STATUS_RXBLOCK_DEFAULT (_LEUART_STATUS_RXBLOCK_DEFAULT << 2) /**< Shifted mode DEFAULT for LEUART_STATUS */ #define LEUART_STATUS_TXC (0x1UL << 3) /**< TX Complete */ #define _LEUART_STATUS_TXC_SHIFT 3 /**< Shift value for LEUART_TXC */ #define _LEUART_STATUS_TXC_MASK 0x8UL /**< Bit mask for LEUART_TXC */ #define _LEUART_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_STATUS */ #define LEUART_STATUS_TXC_DEFAULT (_LEUART_STATUS_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_STATUS */ #define LEUART_STATUS_TXBL (0x1UL << 4) /**< TX Buffer Level */ #define _LEUART_STATUS_TXBL_SHIFT 4 /**< Shift value for LEUART_TXBL */ #define _LEUART_STATUS_TXBL_MASK 0x10UL /**< Bit mask for LEUART_TXBL */ #define _LEUART_STATUS_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for LEUART_STATUS */ #define LEUART_STATUS_TXBL_DEFAULT (_LEUART_STATUS_TXBL_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_STATUS */ #define LEUART_STATUS_RXDATAV (0x1UL << 5) /**< RX Data Valid */ #define _LEUART_STATUS_RXDATAV_SHIFT 5 /**< Shift value for LEUART_RXDATAV */ #define _LEUART_STATUS_RXDATAV_MASK 0x20UL /**< Bit mask for LEUART_RXDATAV */ #define _LEUART_STATUS_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_STATUS */ #define LEUART_STATUS_RXDATAV_DEFAULT (_LEUART_STATUS_RXDATAV_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_STATUS */ #define LEUART_STATUS_TXIDLE (0x1UL << 6) /**< TX Idle */ #define _LEUART_STATUS_TXIDLE_SHIFT 6 /**< Shift value for LEUART_TXIDLE */ #define _LEUART_STATUS_TXIDLE_MASK 0x40UL /**< Bit mask for LEUART_TXIDLE */ #define _LEUART_STATUS_TXIDLE_DEFAULT 0x00000001UL /**< Mode DEFAULT for LEUART_STATUS */ #define LEUART_STATUS_TXIDLE_DEFAULT (_LEUART_STATUS_TXIDLE_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_STATUS */ /* Bit fields for LEUART CLKDIV */ #define _LEUART_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for LEUART_CLKDIV */ #define _LEUART_CLKDIV_MASK 0x0001FFF8UL /**< Mask for LEUART_CLKDIV */ #define _LEUART_CLKDIV_DIV_SHIFT 3 /**< Shift value for LEUART_DIV */ #define _LEUART_CLKDIV_DIV_MASK 0x1FFF8UL /**< Bit mask for LEUART_DIV */ #define _LEUART_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CLKDIV */ #define LEUART_CLKDIV_DIV_DEFAULT (_LEUART_CLKDIV_DIV_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_CLKDIV */ /* Bit fields for LEUART STARTFRAME */ #define _LEUART_STARTFRAME_RESETVALUE 0x00000000UL /**< Default value for LEUART_STARTFRAME */ #define _LEUART_STARTFRAME_MASK 0x000001FFUL /**< Mask for LEUART_STARTFRAME */ #define _LEUART_STARTFRAME_STARTFRAME_SHIFT 0 /**< Shift value for LEUART_STARTFRAME */ #define _LEUART_STARTFRAME_STARTFRAME_MASK 0x1FFUL /**< Bit mask for LEUART_STARTFRAME */ #define _LEUART_STARTFRAME_STARTFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_STARTFRAME */ #define LEUART_STARTFRAME_STARTFRAME_DEFAULT (_LEUART_STARTFRAME_STARTFRAME_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_STARTFRAME */ /* Bit fields for LEUART SIGFRAME */ #define _LEUART_SIGFRAME_RESETVALUE 0x00000000UL /**< Default value for LEUART_SIGFRAME */ #define _LEUART_SIGFRAME_MASK 0x000001FFUL /**< Mask for LEUART_SIGFRAME */ #define _LEUART_SIGFRAME_SIGFRAME_SHIFT 0 /**< Shift value for LEUART_SIGFRAME */ #define _LEUART_SIGFRAME_SIGFRAME_MASK 0x1FFUL /**< Bit mask for LEUART_SIGFRAME */ #define _LEUART_SIGFRAME_SIGFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SIGFRAME */ #define LEUART_SIGFRAME_SIGFRAME_DEFAULT (_LEUART_SIGFRAME_SIGFRAME_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_SIGFRAME */ /* Bit fields for LEUART RXDATAX */ #define _LEUART_RXDATAX_RESETVALUE 0x00000000UL /**< Default value for LEUART_RXDATAX */ #define _LEUART_RXDATAX_MASK 0x0000C1FFUL /**< Mask for LEUART_RXDATAX */ #define _LEUART_RXDATAX_RXDATA_SHIFT 0 /**< Shift value for LEUART_RXDATA */ #define _LEUART_RXDATAX_RXDATA_MASK 0x1FFUL /**< Bit mask for LEUART_RXDATA */ #define _LEUART_RXDATAX_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATAX */ #define LEUART_RXDATAX_RXDATA_DEFAULT (_LEUART_RXDATAX_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_RXDATAX */ #define LEUART_RXDATAX_PERR (0x1UL << 14) /**< Receive Data Parity Error */ #define _LEUART_RXDATAX_PERR_SHIFT 14 /**< Shift value for LEUART_PERR */ #define _LEUART_RXDATAX_PERR_MASK 0x4000UL /**< Bit mask for LEUART_PERR */ #define _LEUART_RXDATAX_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATAX */ #define LEUART_RXDATAX_PERR_DEFAULT (_LEUART_RXDATAX_PERR_DEFAULT << 14) /**< Shifted mode DEFAULT for LEUART_RXDATAX */ #define LEUART_RXDATAX_FERR (0x1UL << 15) /**< Receive Data Framing Error */ #define _LEUART_RXDATAX_FERR_SHIFT 15 /**< Shift value for LEUART_FERR */ #define _LEUART_RXDATAX_FERR_MASK 0x8000UL /**< Bit mask for LEUART_FERR */ #define _LEUART_RXDATAX_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATAX */ #define LEUART_RXDATAX_FERR_DEFAULT (_LEUART_RXDATAX_FERR_DEFAULT << 15) /**< Shifted mode DEFAULT for LEUART_RXDATAX */ /* Bit fields for LEUART RXDATA */ #define _LEUART_RXDATA_RESETVALUE 0x00000000UL /**< Default value for LEUART_RXDATA */ #define _LEUART_RXDATA_MASK 0x000000FFUL /**< Mask for LEUART_RXDATA */ #define _LEUART_RXDATA_RXDATA_SHIFT 0 /**< Shift value for LEUART_RXDATA */ #define _LEUART_RXDATA_RXDATA_MASK 0xFFUL /**< Bit mask for LEUART_RXDATA */ #define _LEUART_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATA */ #define LEUART_RXDATA_RXDATA_DEFAULT (_LEUART_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_RXDATA */ /* Bit fields for LEUART RXDATAXP */ #define _LEUART_RXDATAXP_RESETVALUE 0x00000000UL /**< Default value for LEUART_RXDATAXP */ #define _LEUART_RXDATAXP_MASK 0x0000C1FFUL /**< Mask for LEUART_RXDATAXP */ #define _LEUART_RXDATAXP_RXDATAP_SHIFT 0 /**< Shift value for LEUART_RXDATAP */ #define _LEUART_RXDATAXP_RXDATAP_MASK 0x1FFUL /**< Bit mask for LEUART_RXDATAP */ #define _LEUART_RXDATAXP_RXDATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATAXP */ #define LEUART_RXDATAXP_RXDATAP_DEFAULT (_LEUART_RXDATAXP_RXDATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_RXDATAXP */ #define LEUART_RXDATAXP_PERRP (0x1UL << 14) /**< Receive Data Parity Error Peek */ #define _LEUART_RXDATAXP_PERRP_SHIFT 14 /**< Shift value for LEUART_PERRP */ #define _LEUART_RXDATAXP_PERRP_MASK 0x4000UL /**< Bit mask for LEUART_PERRP */ #define _LEUART_RXDATAXP_PERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATAXP */ #define LEUART_RXDATAXP_PERRP_DEFAULT (_LEUART_RXDATAXP_PERRP_DEFAULT << 14) /**< Shifted mode DEFAULT for LEUART_RXDATAXP */ #define LEUART_RXDATAXP_FERRP (0x1UL << 15) /**< Receive Data Framing Error Peek */ #define _LEUART_RXDATAXP_FERRP_SHIFT 15 /**< Shift value for LEUART_FERRP */ #define _LEUART_RXDATAXP_FERRP_MASK 0x8000UL /**< Bit mask for LEUART_FERRP */ #define _LEUART_RXDATAXP_FERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATAXP */ #define LEUART_RXDATAXP_FERRP_DEFAULT (_LEUART_RXDATAXP_FERRP_DEFAULT << 15) /**< Shifted mode DEFAULT for LEUART_RXDATAXP */ /* Bit fields for LEUART TXDATAX */ #define _LEUART_TXDATAX_RESETVALUE 0x00000000UL /**< Default value for LEUART_TXDATAX */ #define _LEUART_TXDATAX_MASK 0x0000E1FFUL /**< Mask for LEUART_TXDATAX */ #define _LEUART_TXDATAX_TXDATA_SHIFT 0 /**< Shift value for LEUART_TXDATA */ #define _LEUART_TXDATAX_TXDATA_MASK 0x1FFUL /**< Bit mask for LEUART_TXDATA */ #define _LEUART_TXDATAX_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_TXDATAX */ #define LEUART_TXDATAX_TXDATA_DEFAULT (_LEUART_TXDATAX_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_TXDATAX */ #define LEUART_TXDATAX_TXBREAK (0x1UL << 13) /**< Transmit Data as Break */ #define _LEUART_TXDATAX_TXBREAK_SHIFT 13 /**< Shift value for LEUART_TXBREAK */ #define _LEUART_TXDATAX_TXBREAK_MASK 0x2000UL /**< Bit mask for LEUART_TXBREAK */ #define _LEUART_TXDATAX_TXBREAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_TXDATAX */ #define LEUART_TXDATAX_TXBREAK_DEFAULT (_LEUART_TXDATAX_TXBREAK_DEFAULT << 13) /**< Shifted mode DEFAULT for LEUART_TXDATAX */ #define LEUART_TXDATAX_TXDISAT (0x1UL << 14) /**< Disable TX After Transmission */ #define _LEUART_TXDATAX_TXDISAT_SHIFT 14 /**< Shift value for LEUART_TXDISAT */ #define _LEUART_TXDATAX_TXDISAT_MASK 0x4000UL /**< Bit mask for LEUART_TXDISAT */ #define _LEUART_TXDATAX_TXDISAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_TXDATAX */ #define LEUART_TXDATAX_TXDISAT_DEFAULT (_LEUART_TXDATAX_TXDISAT_DEFAULT << 14) /**< Shifted mode DEFAULT for LEUART_TXDATAX */ #define LEUART_TXDATAX_RXENAT (0x1UL << 15) /**< Enable RX After Transmission */ #define _LEUART_TXDATAX_RXENAT_SHIFT 15 /**< Shift value for LEUART_RXENAT */ #define _LEUART_TXDATAX_RXENAT_MASK 0x8000UL /**< Bit mask for LEUART_RXENAT */ #define _LEUART_TXDATAX_RXENAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_TXDATAX */ #define LEUART_TXDATAX_RXENAT_DEFAULT (_LEUART_TXDATAX_RXENAT_DEFAULT << 15) /**< Shifted mode DEFAULT for LEUART_TXDATAX */ /* Bit fields for LEUART TXDATA */ #define _LEUART_TXDATA_RESETVALUE 0x00000000UL /**< Default value for LEUART_TXDATA */ #define _LEUART_TXDATA_MASK 0x000000FFUL /**< Mask for LEUART_TXDATA */ #define _LEUART_TXDATA_TXDATA_SHIFT 0 /**< Shift value for LEUART_TXDATA */ #define _LEUART_TXDATA_TXDATA_MASK 0xFFUL /**< Bit mask for LEUART_TXDATA */ #define _LEUART_TXDATA_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_TXDATA */ #define LEUART_TXDATA_TXDATA_DEFAULT (_LEUART_TXDATA_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_TXDATA */ /* Bit fields for LEUART IF */ #define _LEUART_IF_RESETVALUE 0x00000002UL /**< Default value for LEUART_IF */ #define _LEUART_IF_MASK 0x000007FFUL /**< Mask for LEUART_IF */ #define LEUART_IF_TXC (0x1UL << 0) /**< TX Complete Interrupt Flag */ #define _LEUART_IF_TXC_SHIFT 0 /**< Shift value for LEUART_TXC */ #define _LEUART_IF_TXC_MASK 0x1UL /**< Bit mask for LEUART_TXC */ #define _LEUART_IF_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */ #define LEUART_IF_TXC_DEFAULT (_LEUART_IF_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_IF */ #define LEUART_IF_TXBL (0x1UL << 1) /**< TX Buffer Level Interrupt Flag */ #define _LEUART_IF_TXBL_SHIFT 1 /**< Shift value for LEUART_TXBL */ #define _LEUART_IF_TXBL_MASK 0x2UL /**< Bit mask for LEUART_TXBL */ #define _LEUART_IF_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for LEUART_IF */ #define LEUART_IF_TXBL_DEFAULT (_LEUART_IF_TXBL_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_IF */ #define LEUART_IF_RXDATAV (0x1UL << 2) /**< RX Data Valid Interrupt Flag */ #define _LEUART_IF_RXDATAV_SHIFT 2 /**< Shift value for LEUART_RXDATAV */ #define _LEUART_IF_RXDATAV_MASK 0x4UL /**< Bit mask for LEUART_RXDATAV */ #define _LEUART_IF_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */ #define LEUART_IF_RXDATAV_DEFAULT (_LEUART_IF_RXDATAV_DEFAULT << 2) /**< Shifted mode DEFAULT for LEUART_IF */ #define LEUART_IF_RXOF (0x1UL << 3) /**< RX Overflow Interrupt Flag */ #define _LEUART_IF_RXOF_SHIFT 3 /**< Shift value for LEUART_RXOF */ #define _LEUART_IF_RXOF_MASK 0x8UL /**< Bit mask for LEUART_RXOF */ #define _LEUART_IF_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */ #define LEUART_IF_RXOF_DEFAULT (_LEUART_IF_RXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_IF */ #define LEUART_IF_RXUF (0x1UL << 4) /**< RX Underflow Interrupt Flag */ #define _LEUART_IF_RXUF_SHIFT 4 /**< Shift value for LEUART_RXUF */ #define _LEUART_IF_RXUF_MASK 0x10UL /**< Bit mask for LEUART_RXUF */ #define _LEUART_IF_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */ #define LEUART_IF_RXUF_DEFAULT (_LEUART_IF_RXUF_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_IF */ #define LEUART_IF_TXOF (0x1UL << 5) /**< TX Overflow Interrupt Flag */ #define _LEUART_IF_TXOF_SHIFT 5 /**< Shift value for LEUART_TXOF */ #define _LEUART_IF_TXOF_MASK 0x20UL /**< Bit mask for LEUART_TXOF */ #define _LEUART_IF_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */ #define LEUART_IF_TXOF_DEFAULT (_LEUART_IF_TXOF_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_IF */ #define LEUART_IF_PERR (0x1UL << 6) /**< Parity Error Interrupt Flag */ #define _LEUART_IF_PERR_SHIFT 6 /**< Shift value for LEUART_PERR */ #define _LEUART_IF_PERR_MASK 0x40UL /**< Bit mask for LEUART_PERR */ #define _LEUART_IF_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */ #define LEUART_IF_PERR_DEFAULT (_LEUART_IF_PERR_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_IF */ #define LEUART_IF_FERR (0x1UL << 7) /**< Framing Error Interrupt Flag */ #define _LEUART_IF_FERR_SHIFT 7 /**< Shift value for LEUART_FERR */ #define _LEUART_IF_FERR_MASK 0x80UL /**< Bit mask for LEUART_FERR */ #define _LEUART_IF_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */ #define LEUART_IF_FERR_DEFAULT (_LEUART_IF_FERR_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_IF */ #define LEUART_IF_MPAF (0x1UL << 8) /**< Multi-Processor Address Frame Interrupt Flag */ #define _LEUART_IF_MPAF_SHIFT 8 /**< Shift value for LEUART_MPAF */ #define _LEUART_IF_MPAF_MASK 0x100UL /**< Bit mask for LEUART_MPAF */ #define _LEUART_IF_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */ #define LEUART_IF_MPAF_DEFAULT (_LEUART_IF_MPAF_DEFAULT << 8) /**< Shifted mode DEFAULT for LEUART_IF */ #define LEUART_IF_STARTF (0x1UL << 9) /**< Start Frame Interrupt Flag */ #define _LEUART_IF_STARTF_SHIFT 9 /**< Shift value for LEUART_STARTF */ #define _LEUART_IF_STARTF_MASK 0x200UL /**< Bit mask for LEUART_STARTF */ #define _LEUART_IF_STARTF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */ #define LEUART_IF_STARTF_DEFAULT (_LEUART_IF_STARTF_DEFAULT << 9) /**< Shifted mode DEFAULT for LEUART_IF */ #define LEUART_IF_SIGF (0x1UL << 10) /**< Signal Frame Interrupt Flag */ #define _LEUART_IF_SIGF_SHIFT 10 /**< Shift value for LEUART_SIGF */ #define _LEUART_IF_SIGF_MASK 0x400UL /**< Bit mask for LEUART_SIGF */ #define _LEUART_IF_SIGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */ #define LEUART_IF_SIGF_DEFAULT (_LEUART_IF_SIGF_DEFAULT << 10) /**< Shifted mode DEFAULT for LEUART_IF */ /* Bit fields for LEUART IFS */ #define _LEUART_IFS_RESETVALUE 0x00000000UL /**< Default value for LEUART_IFS */ #define _LEUART_IFS_MASK 0x000007F9UL /**< Mask for LEUART_IFS */ #define LEUART_IFS_TXC (0x1UL << 0) /**< Set TXC Interrupt Flag */ #define _LEUART_IFS_TXC_SHIFT 0 /**< Shift value for LEUART_TXC */ #define _LEUART_IFS_TXC_MASK 0x1UL /**< Bit mask for LEUART_TXC */ #define _LEUART_IFS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */ #define LEUART_IFS_TXC_DEFAULT (_LEUART_IFS_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_IFS */ #define LEUART_IFS_RXOF (0x1UL << 3) /**< Set RXOF Interrupt Flag */ #define _LEUART_IFS_RXOF_SHIFT 3 /**< Shift value for LEUART_RXOF */ #define _LEUART_IFS_RXOF_MASK 0x8UL /**< Bit mask for LEUART_RXOF */ #define _LEUART_IFS_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */ #define LEUART_IFS_RXOF_DEFAULT (_LEUART_IFS_RXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_IFS */ #define LEUART_IFS_RXUF (0x1UL << 4) /**< Set RXUF Interrupt Flag */ #define _LEUART_IFS_RXUF_SHIFT 4 /**< Shift value for LEUART_RXUF */ #define _LEUART_IFS_RXUF_MASK 0x10UL /**< Bit mask for LEUART_RXUF */ #define _LEUART_IFS_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */ #define LEUART_IFS_RXUF_DEFAULT (_LEUART_IFS_RXUF_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_IFS */ #define LEUART_IFS_TXOF (0x1UL << 5) /**< Set TXOF Interrupt Flag */ #define _LEUART_IFS_TXOF_SHIFT 5 /**< Shift value for LEUART_TXOF */ #define _LEUART_IFS_TXOF_MASK 0x20UL /**< Bit mask for LEUART_TXOF */ #define _LEUART_IFS_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */ #define LEUART_IFS_TXOF_DEFAULT (_LEUART_IFS_TXOF_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_IFS */ #define LEUART_IFS_PERR (0x1UL << 6) /**< Set PERR Interrupt Flag */ #define _LEUART_IFS_PERR_SHIFT 6 /**< Shift value for LEUART_PERR */ #define _LEUART_IFS_PERR_MASK 0x40UL /**< Bit mask for LEUART_PERR */ #define _LEUART_IFS_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */ #define LEUART_IFS_PERR_DEFAULT (_LEUART_IFS_PERR_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_IFS */ #define LEUART_IFS_FERR (0x1UL << 7) /**< Set FERR Interrupt Flag */ #define _LEUART_IFS_FERR_SHIFT 7 /**< Shift value for LEUART_FERR */ #define _LEUART_IFS_FERR_MASK 0x80UL /**< Bit mask for LEUART_FERR */ #define _LEUART_IFS_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */ #define LEUART_IFS_FERR_DEFAULT (_LEUART_IFS_FERR_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_IFS */ #define LEUART_IFS_MPAF (0x1UL << 8) /**< Set MPAF Interrupt Flag */ #define _LEUART_IFS_MPAF_SHIFT 8 /**< Shift value for LEUART_MPAF */ #define _LEUART_IFS_MPAF_MASK 0x100UL /**< Bit mask for LEUART_MPAF */ #define _LEUART_IFS_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */ #define LEUART_IFS_MPAF_DEFAULT (_LEUART_IFS_MPAF_DEFAULT << 8) /**< Shifted mode DEFAULT for LEUART_IFS */ #define LEUART_IFS_STARTF (0x1UL << 9) /**< Set STARTF Interrupt Flag */ #define _LEUART_IFS_STARTF_SHIFT 9 /**< Shift value for LEUART_STARTF */ #define _LEUART_IFS_STARTF_MASK 0x200UL /**< Bit mask for LEUART_STARTF */ #define _LEUART_IFS_STARTF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */ #define LEUART_IFS_STARTF_DEFAULT (_LEUART_IFS_STARTF_DEFAULT << 9) /**< Shifted mode DEFAULT for LEUART_IFS */ #define LEUART_IFS_SIGF (0x1UL << 10) /**< Set SIGF Interrupt Flag */ #define _LEUART_IFS_SIGF_SHIFT 10 /**< Shift value for LEUART_SIGF */ #define _LEUART_IFS_SIGF_MASK 0x400UL /**< Bit mask for LEUART_SIGF */ #define _LEUART_IFS_SIGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */ #define LEUART_IFS_SIGF_DEFAULT (_LEUART_IFS_SIGF_DEFAULT << 10) /**< Shifted mode DEFAULT for LEUART_IFS */ /* Bit fields for LEUART IFC */ #define _LEUART_IFC_RESETVALUE 0x00000000UL /**< Default value for LEUART_IFC */ #define _LEUART_IFC_MASK 0x000007F9UL /**< Mask for LEUART_IFC */ #define LEUART_IFC_TXC (0x1UL << 0) /**< Clear TXC Interrupt Flag */ #define _LEUART_IFC_TXC_SHIFT 0 /**< Shift value for LEUART_TXC */ #define _LEUART_IFC_TXC_MASK 0x1UL /**< Bit mask for LEUART_TXC */ #define _LEUART_IFC_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */ #define LEUART_IFC_TXC_DEFAULT (_LEUART_IFC_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_IFC */ #define LEUART_IFC_RXOF (0x1UL << 3) /**< Clear RXOF Interrupt Flag */ #define _LEUART_IFC_RXOF_SHIFT 3 /**< Shift value for LEUART_RXOF */ #define _LEUART_IFC_RXOF_MASK 0x8UL /**< Bit mask for LEUART_RXOF */ #define _LEUART_IFC_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */ #define LEUART_IFC_RXOF_DEFAULT (_LEUART_IFC_RXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_IFC */ #define LEUART_IFC_RXUF (0x1UL << 4) /**< Clear RXUF Interrupt Flag */ #define _LEUART_IFC_RXUF_SHIFT 4 /**< Shift value for LEUART_RXUF */ #define _LEUART_IFC_RXUF_MASK 0x10UL /**< Bit mask for LEUART_RXUF */ #define _LEUART_IFC_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */ #define LEUART_IFC_RXUF_DEFAULT (_LEUART_IFC_RXUF_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_IFC */ #define LEUART_IFC_TXOF (0x1UL << 5) /**< Clear TXOF Interrupt Flag */ #define _LEUART_IFC_TXOF_SHIFT 5 /**< Shift value for LEUART_TXOF */ #define _LEUART_IFC_TXOF_MASK 0x20UL /**< Bit mask for LEUART_TXOF */ #define _LEUART_IFC_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */ #define LEUART_IFC_TXOF_DEFAULT (_LEUART_IFC_TXOF_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_IFC */ #define LEUART_IFC_PERR (0x1UL << 6) /**< Clear PERR Interrupt Flag */ #define _LEUART_IFC_PERR_SHIFT 6 /**< Shift value for LEUART_PERR */ #define _LEUART_IFC_PERR_MASK 0x40UL /**< Bit mask for LEUART_PERR */ #define _LEUART_IFC_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */ #define LEUART_IFC_PERR_DEFAULT (_LEUART_IFC_PERR_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_IFC */ #define LEUART_IFC_FERR (0x1UL << 7) /**< Clear FERR Interrupt Flag */ #define _LEUART_IFC_FERR_SHIFT 7 /**< Shift value for LEUART_FERR */ #define _LEUART_IFC_FERR_MASK 0x80UL /**< Bit mask for LEUART_FERR */ #define _LEUART_IFC_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */ #define LEUART_IFC_FERR_DEFAULT (_LEUART_IFC_FERR_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_IFC */ #define LEUART_IFC_MPAF (0x1UL << 8) /**< Clear MPAF Interrupt Flag */ #define _LEUART_IFC_MPAF_SHIFT 8 /**< Shift value for LEUART_MPAF */ #define _LEUART_IFC_MPAF_MASK 0x100UL /**< Bit mask for LEUART_MPAF */ #define _LEUART_IFC_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */ #define LEUART_IFC_MPAF_DEFAULT (_LEUART_IFC_MPAF_DEFAULT << 8) /**< Shifted mode DEFAULT for LEUART_IFC */ #define LEUART_IFC_STARTF (0x1UL << 9) /**< Clear STARTF Interrupt Flag */ #define _LEUART_IFC_STARTF_SHIFT 9 /**< Shift value for LEUART_STARTF */ #define _LEUART_IFC_STARTF_MASK 0x200UL /**< Bit mask for LEUART_STARTF */ #define _LEUART_IFC_STARTF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */ #define LEUART_IFC_STARTF_DEFAULT (_LEUART_IFC_STARTF_DEFAULT << 9) /**< Shifted mode DEFAULT for LEUART_IFC */ #define LEUART_IFC_SIGF (0x1UL << 10) /**< Clear SIGF Interrupt Flag */ #define _LEUART_IFC_SIGF_SHIFT 10 /**< Shift value for LEUART_SIGF */ #define _LEUART_IFC_SIGF_MASK 0x400UL /**< Bit mask for LEUART_SIGF */ #define _LEUART_IFC_SIGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */ #define LEUART_IFC_SIGF_DEFAULT (_LEUART_IFC_SIGF_DEFAULT << 10) /**< Shifted mode DEFAULT for LEUART_IFC */ /* Bit fields for LEUART IEN */ #define _LEUART_IEN_RESETVALUE 0x00000000UL /**< Default value for LEUART_IEN */ #define _LEUART_IEN_MASK 0x000007FFUL /**< Mask for LEUART_IEN */ #define LEUART_IEN_TXC (0x1UL << 0) /**< TXC Interrupt Enable */ #define _LEUART_IEN_TXC_SHIFT 0 /**< Shift value for LEUART_TXC */ #define _LEUART_IEN_TXC_MASK 0x1UL /**< Bit mask for LEUART_TXC */ #define _LEUART_IEN_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */ #define LEUART_IEN_TXC_DEFAULT (_LEUART_IEN_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_IEN */ #define LEUART_IEN_TXBL (0x1UL << 1) /**< TXBL Interrupt Enable */ #define _LEUART_IEN_TXBL_SHIFT 1 /**< Shift value for LEUART_TXBL */ #define _LEUART_IEN_TXBL_MASK 0x2UL /**< Bit mask for LEUART_TXBL */ #define _LEUART_IEN_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */ #define LEUART_IEN_TXBL_DEFAULT (_LEUART_IEN_TXBL_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_IEN */ #define LEUART_IEN_RXDATAV (0x1UL << 2) /**< RXDATAV Interrupt Enable */ #define _LEUART_IEN_RXDATAV_SHIFT 2 /**< Shift value for LEUART_RXDATAV */ #define _LEUART_IEN_RXDATAV_MASK 0x4UL /**< Bit mask for LEUART_RXDATAV */ #define _LEUART_IEN_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */ #define LEUART_IEN_RXDATAV_DEFAULT (_LEUART_IEN_RXDATAV_DEFAULT << 2) /**< Shifted mode DEFAULT for LEUART_IEN */ #define LEUART_IEN_RXOF (0x1UL << 3) /**< RXOF Interrupt Enable */ #define _LEUART_IEN_RXOF_SHIFT 3 /**< Shift value for LEUART_RXOF */ #define _LEUART_IEN_RXOF_MASK 0x8UL /**< Bit mask for LEUART_RXOF */ #define _LEUART_IEN_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */ #define LEUART_IEN_RXOF_DEFAULT (_LEUART_IEN_RXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_IEN */ #define LEUART_IEN_RXUF (0x1UL << 4) /**< RXUF Interrupt Enable */ #define _LEUART_IEN_RXUF_SHIFT 4 /**< Shift value for LEUART_RXUF */ #define _LEUART_IEN_RXUF_MASK 0x10UL /**< Bit mask for LEUART_RXUF */ #define _LEUART_IEN_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */ #define LEUART_IEN_RXUF_DEFAULT (_LEUART_IEN_RXUF_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_IEN */ #define LEUART_IEN_TXOF (0x1UL << 5) /**< TXOF Interrupt Enable */ #define _LEUART_IEN_TXOF_SHIFT 5 /**< Shift value for LEUART_TXOF */ #define _LEUART_IEN_TXOF_MASK 0x20UL /**< Bit mask for LEUART_TXOF */ #define _LEUART_IEN_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */ #define LEUART_IEN_TXOF_DEFAULT (_LEUART_IEN_TXOF_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_IEN */ #define LEUART_IEN_PERR (0x1UL << 6) /**< PERR Interrupt Enable */ #define _LEUART_IEN_PERR_SHIFT 6 /**< Shift value for LEUART_PERR */ #define _LEUART_IEN_PERR_MASK 0x40UL /**< Bit mask for LEUART_PERR */ #define _LEUART_IEN_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */ #define LEUART_IEN_PERR_DEFAULT (_LEUART_IEN_PERR_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_IEN */ #define LEUART_IEN_FERR (0x1UL << 7) /**< FERR Interrupt Enable */ #define _LEUART_IEN_FERR_SHIFT 7 /**< Shift value for LEUART_FERR */ #define _LEUART_IEN_FERR_MASK 0x80UL /**< Bit mask for LEUART_FERR */ #define _LEUART_IEN_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */ #define LEUART_IEN_FERR_DEFAULT (_LEUART_IEN_FERR_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_IEN */ #define LEUART_IEN_MPAF (0x1UL << 8) /**< MPAF Interrupt Enable */ #define _LEUART_IEN_MPAF_SHIFT 8 /**< Shift value for LEUART_MPAF */ #define _LEUART_IEN_MPAF_MASK 0x100UL /**< Bit mask for LEUART_MPAF */ #define _LEUART_IEN_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */ #define LEUART_IEN_MPAF_DEFAULT (_LEUART_IEN_MPAF_DEFAULT << 8) /**< Shifted mode DEFAULT for LEUART_IEN */ #define LEUART_IEN_STARTF (0x1UL << 9) /**< STARTF Interrupt Enable */ #define _LEUART_IEN_STARTF_SHIFT 9 /**< Shift value for LEUART_STARTF */ #define _LEUART_IEN_STARTF_MASK 0x200UL /**< Bit mask for LEUART_STARTF */ #define _LEUART_IEN_STARTF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */ #define LEUART_IEN_STARTF_DEFAULT (_LEUART_IEN_STARTF_DEFAULT << 9) /**< Shifted mode DEFAULT for LEUART_IEN */ #define LEUART_IEN_SIGF (0x1UL << 10) /**< SIGF Interrupt Enable */ #define _LEUART_IEN_SIGF_SHIFT 10 /**< Shift value for LEUART_SIGF */ #define _LEUART_IEN_SIGF_MASK 0x400UL /**< Bit mask for LEUART_SIGF */ #define _LEUART_IEN_SIGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */ #define LEUART_IEN_SIGF_DEFAULT (_LEUART_IEN_SIGF_DEFAULT << 10) /**< Shifted mode DEFAULT for LEUART_IEN */ /* Bit fields for LEUART PULSECTRL */ #define _LEUART_PULSECTRL_RESETVALUE 0x00000000UL /**< Default value for LEUART_PULSECTRL */ #define _LEUART_PULSECTRL_MASK 0x0000003FUL /**< Mask for LEUART_PULSECTRL */ #define _LEUART_PULSECTRL_PULSEW_SHIFT 0 /**< Shift value for LEUART_PULSEW */ #define _LEUART_PULSECTRL_PULSEW_MASK 0xFUL /**< Bit mask for LEUART_PULSEW */ #define _LEUART_PULSECTRL_PULSEW_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_PULSECTRL */ #define LEUART_PULSECTRL_PULSEW_DEFAULT (_LEUART_PULSECTRL_PULSEW_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_PULSECTRL */ #define LEUART_PULSECTRL_PULSEEN (0x1UL << 4) /**< Pulse Generator/Extender Enable */ #define _LEUART_PULSECTRL_PULSEEN_SHIFT 4 /**< Shift value for LEUART_PULSEEN */ #define _LEUART_PULSECTRL_PULSEEN_MASK 0x10UL /**< Bit mask for LEUART_PULSEEN */ #define _LEUART_PULSECTRL_PULSEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_PULSECTRL */ #define LEUART_PULSECTRL_PULSEEN_DEFAULT (_LEUART_PULSECTRL_PULSEEN_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_PULSECTRL */ #define LEUART_PULSECTRL_PULSEFILT (0x1UL << 5) /**< Pulse Filter */ #define _LEUART_PULSECTRL_PULSEFILT_SHIFT 5 /**< Shift value for LEUART_PULSEFILT */ #define _LEUART_PULSECTRL_PULSEFILT_MASK 0x20UL /**< Bit mask for LEUART_PULSEFILT */ #define _LEUART_PULSECTRL_PULSEFILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_PULSECTRL */ #define LEUART_PULSECTRL_PULSEFILT_DEFAULT (_LEUART_PULSECTRL_PULSEFILT_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_PULSECTRL */ /* Bit fields for LEUART FREEZE */ #define _LEUART_FREEZE_RESETVALUE 0x00000000UL /**< Default value for LEUART_FREEZE */ #define _LEUART_FREEZE_MASK 0x00000001UL /**< Mask for LEUART_FREEZE */ #define LEUART_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */ #define _LEUART_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for LEUART_REGFREEZE */ #define _LEUART_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for LEUART_REGFREEZE */ #define _LEUART_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_FREEZE */ #define _LEUART_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for LEUART_FREEZE */ #define _LEUART_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for LEUART_FREEZE */ #define LEUART_FREEZE_REGFREEZE_DEFAULT (_LEUART_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_FREEZE */ #define LEUART_FREEZE_REGFREEZE_UPDATE (_LEUART_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for LEUART_FREEZE */ #define LEUART_FREEZE_REGFREEZE_FREEZE (_LEUART_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for LEUART_FREEZE */ /* Bit fields for LEUART SYNCBUSY */ #define _LEUART_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for LEUART_SYNCBUSY */ #define _LEUART_SYNCBUSY_MASK 0x000000FFUL /**< Mask for LEUART_SYNCBUSY */ #define LEUART_SYNCBUSY_CTRL (0x1UL << 0) /**< CTRL Register Busy */ #define _LEUART_SYNCBUSY_CTRL_SHIFT 0 /**< Shift value for LEUART_CTRL */ #define _LEUART_SYNCBUSY_CTRL_MASK 0x1UL /**< Bit mask for LEUART_CTRL */ #define _LEUART_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */ #define LEUART_SYNCBUSY_CTRL_DEFAULT (_LEUART_SYNCBUSY_CTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */ #define LEUART_SYNCBUSY_CMD (0x1UL << 1) /**< CMD Register Busy */ #define _LEUART_SYNCBUSY_CMD_SHIFT 1 /**< Shift value for LEUART_CMD */ #define _LEUART_SYNCBUSY_CMD_MASK 0x2UL /**< Bit mask for LEUART_CMD */ #define _LEUART_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */ #define LEUART_SYNCBUSY_CMD_DEFAULT (_LEUART_SYNCBUSY_CMD_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */ #define LEUART_SYNCBUSY_CLKDIV (0x1UL << 2) /**< CLKDIV Register Busy */ #define _LEUART_SYNCBUSY_CLKDIV_SHIFT 2 /**< Shift value for LEUART_CLKDIV */ #define _LEUART_SYNCBUSY_CLKDIV_MASK 0x4UL /**< Bit mask for LEUART_CLKDIV */ #define _LEUART_SYNCBUSY_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */ #define LEUART_SYNCBUSY_CLKDIV_DEFAULT (_LEUART_SYNCBUSY_CLKDIV_DEFAULT << 2) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */ #define LEUART_SYNCBUSY_STARTFRAME (0x1UL << 3) /**< STARTFRAME Register Busy */ #define _LEUART_SYNCBUSY_STARTFRAME_SHIFT 3 /**< Shift value for LEUART_STARTFRAME */ #define _LEUART_SYNCBUSY_STARTFRAME_MASK 0x8UL /**< Bit mask for LEUART_STARTFRAME */ #define _LEUART_SYNCBUSY_STARTFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */ #define LEUART_SYNCBUSY_STARTFRAME_DEFAULT (_LEUART_SYNCBUSY_STARTFRAME_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */ #define LEUART_SYNCBUSY_SIGFRAME (0x1UL << 4) /**< SIGFRAME Register Busy */ #define _LEUART_SYNCBUSY_SIGFRAME_SHIFT 4 /**< Shift value for LEUART_SIGFRAME */ #define _LEUART_SYNCBUSY_SIGFRAME_MASK 0x10UL /**< Bit mask for LEUART_SIGFRAME */ #define _LEUART_SYNCBUSY_SIGFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */ #define LEUART_SYNCBUSY_SIGFRAME_DEFAULT (_LEUART_SYNCBUSY_SIGFRAME_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */ #define LEUART_SYNCBUSY_TXDATAX (0x1UL << 5) /**< TXDATAX Register Busy */ #define _LEUART_SYNCBUSY_TXDATAX_SHIFT 5 /**< Shift value for LEUART_TXDATAX */ #define _LEUART_SYNCBUSY_TXDATAX_MASK 0x20UL /**< Bit mask for LEUART_TXDATAX */ #define _LEUART_SYNCBUSY_TXDATAX_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */ #define LEUART_SYNCBUSY_TXDATAX_DEFAULT (_LEUART_SYNCBUSY_TXDATAX_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */ #define LEUART_SYNCBUSY_TXDATA (0x1UL << 6) /**< TXDATA Register Busy */ #define _LEUART_SYNCBUSY_TXDATA_SHIFT 6 /**< Shift value for LEUART_TXDATA */ #define _LEUART_SYNCBUSY_TXDATA_MASK 0x40UL /**< Bit mask for LEUART_TXDATA */ #define _LEUART_SYNCBUSY_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */ #define LEUART_SYNCBUSY_TXDATA_DEFAULT (_LEUART_SYNCBUSY_TXDATA_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */ #define LEUART_SYNCBUSY_PULSECTRL (0x1UL << 7) /**< PULSECTRL Register Busy */ #define _LEUART_SYNCBUSY_PULSECTRL_SHIFT 7 /**< Shift value for LEUART_PULSECTRL */ #define _LEUART_SYNCBUSY_PULSECTRL_MASK 0x80UL /**< Bit mask for LEUART_PULSECTRL */ #define _LEUART_SYNCBUSY_PULSECTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */ #define LEUART_SYNCBUSY_PULSECTRL_DEFAULT (_LEUART_SYNCBUSY_PULSECTRL_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */ /* Bit fields for LEUART ROUTEPEN */ #define _LEUART_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for LEUART_ROUTEPEN */ #define _LEUART_ROUTEPEN_MASK 0x00000003UL /**< Mask for LEUART_ROUTEPEN */ #define LEUART_ROUTEPEN_RXPEN (0x1UL << 0) /**< RX Pin Enable */ #define _LEUART_ROUTEPEN_RXPEN_SHIFT 0 /**< Shift value for LEUART_RXPEN */ #define _LEUART_ROUTEPEN_RXPEN_MASK 0x1UL /**< Bit mask for LEUART_RXPEN */ #define _LEUART_ROUTEPEN_RXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_ROUTEPEN */ #define LEUART_ROUTEPEN_RXPEN_DEFAULT (_LEUART_ROUTEPEN_RXPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_ROUTEPEN */ #define LEUART_ROUTEPEN_TXPEN (0x1UL << 1) /**< TX Pin Enable */ #define _LEUART_ROUTEPEN_TXPEN_SHIFT 1 /**< Shift value for LEUART_TXPEN */ #define _LEUART_ROUTEPEN_TXPEN_MASK 0x2UL /**< Bit mask for LEUART_TXPEN */ #define _LEUART_ROUTEPEN_TXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_ROUTEPEN */ #define LEUART_ROUTEPEN_TXPEN_DEFAULT (_LEUART_ROUTEPEN_TXPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_ROUTEPEN */ /* Bit fields for LEUART ROUTELOC0 */ #define _LEUART_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for LEUART_ROUTELOC0 */ #define _LEUART_ROUTELOC0_MASK 0x00001F1FUL /**< Mask for LEUART_ROUTELOC0 */ #define _LEUART_ROUTELOC0_RXLOC_SHIFT 0 /**< Shift value for LEUART_RXLOC */ #define _LEUART_ROUTELOC0_RXLOC_MASK 0x1FUL /**< Bit mask for LEUART_RXLOC */ #define _LEUART_ROUTELOC0_RXLOC_LOC0 0x00000000UL /**< Mode LOC0 for LEUART_ROUTELOC0 */ #define _LEUART_ROUTELOC0_RXLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_ROUTELOC0 */ #define _LEUART_ROUTELOC0_RXLOC_LOC1 0x00000001UL /**< Mode LOC1 for LEUART_ROUTELOC0 */ #define _LEUART_ROUTELOC0_RXLOC_LOC2 0x00000002UL /**< Mode LOC2 for LEUART_ROUTELOC0 */ #define _LEUART_ROUTELOC0_RXLOC_LOC3 0x00000003UL /**< Mode LOC3 for LEUART_ROUTELOC0 */ #define _LEUART_ROUTELOC0_RXLOC_LOC4 0x00000004UL /**< Mode LOC4 for LEUART_ROUTELOC0 */ #define _LEUART_ROUTELOC0_RXLOC_LOC5 0x00000005UL /**< Mode LOC5 for LEUART_ROUTELOC0 */ #define _LEUART_ROUTELOC0_RXLOC_LOC6 0x00000006UL /**< Mode LOC6 for LEUART_ROUTELOC0 */ #define _LEUART_ROUTELOC0_RXLOC_LOC7 0x00000007UL /**< Mode LOC7 for LEUART_ROUTELOC0 */ #define _LEUART_ROUTELOC0_RXLOC_LOC8 0x00000008UL /**< Mode LOC8 for LEUART_ROUTELOC0 */ #define _LEUART_ROUTELOC0_RXLOC_LOC9 0x00000009UL /**< Mode LOC9 for LEUART_ROUTELOC0 */ #define _LEUART_ROUTELOC0_RXLOC_LOC10 0x0000000AUL /**< Mode LOC10 for LEUART_ROUTELOC0 */ #define _LEUART_ROUTELOC0_RXLOC_LOC11 0x0000000BUL /**< Mode LOC11 for LEUART_ROUTELOC0 */ #define _LEUART_ROUTELOC0_RXLOC_LOC12 0x0000000CUL /**< Mode LOC12 for LEUART_ROUTELOC0 */ #define _LEUART_ROUTELOC0_RXLOC_LOC13 0x0000000DUL /**< Mode LOC13 for LEUART_ROUTELOC0 */ #define _LEUART_ROUTELOC0_RXLOC_LOC14 0x0000000EUL /**< Mode LOC14 for LEUART_ROUTELOC0 */ #define _LEUART_ROUTELOC0_RXLOC_LOC15 0x0000000FUL /**< Mode LOC15 for LEUART_ROUTELOC0 */ #define _LEUART_ROUTELOC0_RXLOC_LOC16 0x00000010UL /**< Mode LOC16 for LEUART_ROUTELOC0 */ #define _LEUART_ROUTELOC0_RXLOC_LOC17 0x00000011UL /**< Mode LOC17 for LEUART_ROUTELOC0 */ #define _LEUART_ROUTELOC0_RXLOC_LOC18 0x00000012UL /**< Mode LOC18 for LEUART_ROUTELOC0 */ #define _LEUART_ROUTELOC0_RXLOC_LOC19 0x00000013UL /**< Mode LOC19 for LEUART_ROUTELOC0 */ #define _LEUART_ROUTELOC0_RXLOC_LOC20 0x00000014UL /**< Mode LOC20 for LEUART_ROUTELOC0 */ #define _LEUART_ROUTELOC0_RXLOC_LOC21 0x00000015UL /**< Mode LOC21 for LEUART_ROUTELOC0 */ #define _LEUART_ROUTELOC0_RXLOC_LOC22 0x00000016UL /**< Mode LOC22 for LEUART_ROUTELOC0 */ #define _LEUART_ROUTELOC0_RXLOC_LOC23 0x00000017UL /**< Mode LOC23 for LEUART_ROUTELOC0 */ #define _LEUART_ROUTELOC0_RXLOC_LOC24 0x00000018UL /**< Mode LOC24 for LEUART_ROUTELOC0 */ #define _LEUART_ROUTELOC0_RXLOC_LOC25 0x00000019UL /**< Mode LOC25 for LEUART_ROUTELOC0 */ #define _LEUART_ROUTELOC0_RXLOC_LOC26 0x0000001AUL /**< Mode LOC26 for LEUART_ROUTELOC0 */ #define _LEUART_ROUTELOC0_RXLOC_LOC27 0x0000001BUL /**< Mode LOC27 for LEUART_ROUTELOC0 */ #define _LEUART_ROUTELOC0_RXLOC_LOC28 0x0000001CUL /**< Mode LOC28 for LEUART_ROUTELOC0 */ #define _LEUART_ROUTELOC0_RXLOC_LOC29 0x0000001DUL /**< Mode LOC29 for LEUART_ROUTELOC0 */ #define _LEUART_ROUTELOC0_RXLOC_LOC30 0x0000001EUL /**< Mode LOC30 for LEUART_ROUTELOC0 */ #define _LEUART_ROUTELOC0_RXLOC_LOC31 0x0000001FUL /**< Mode LOC31 for LEUART_ROUTELOC0 */ #define LEUART_ROUTELOC0_RXLOC_LOC0 (_LEUART_ROUTELOC0_RXLOC_LOC0 << 0) /**< Shifted mode LOC0 for LEUART_ROUTELOC0 */ #define LEUART_ROUTELOC0_RXLOC_DEFAULT (_LEUART_ROUTELOC0_RXLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_ROUTELOC0 */ #define LEUART_ROUTELOC0_RXLOC_LOC1 (_LEUART_ROUTELOC0_RXLOC_LOC1 << 0) /**< Shifted mode LOC1 for LEUART_ROUTELOC0 */ #define LEUART_ROUTELOC0_RXLOC_LOC2 (_LEUART_ROUTELOC0_RXLOC_LOC2 << 0) /**< Shifted mode LOC2 for LEUART_ROUTELOC0 */ #define LEUART_ROUTELOC0_RXLOC_LOC3 (_LEUART_ROUTELOC0_RXLOC_LOC3 << 0) /**< Shifted mode LOC3 for LEUART_ROUTELOC0 */ #define LEUART_ROUTELOC0_RXLOC_LOC4 (_LEUART_ROUTELOC0_RXLOC_LOC4 << 0) /**< Shifted mode LOC4 for LEUART_ROUTELOC0 */ #define LEUART_ROUTELOC0_RXLOC_LOC5 (_LEUART_ROUTELOC0_RXLOC_LOC5 << 0) /**< Shifted mode LOC5 for LEUART_ROUTELOC0 */ #define LEUART_ROUTELOC0_RXLOC_LOC6 (_LEUART_ROUTELOC0_RXLOC_LOC6 << 0) /**< Shifted mode LOC6 for LEUART_ROUTELOC0 */ #define LEUART_ROUTELOC0_RXLOC_LOC7 (_LEUART_ROUTELOC0_RXLOC_LOC7 << 0) /**< Shifted mode LOC7 for LEUART_ROUTELOC0 */ #define LEUART_ROUTELOC0_RXLOC_LOC8 (_LEUART_ROUTELOC0_RXLOC_LOC8 << 0) /**< Shifted mode LOC8 for LEUART_ROUTELOC0 */ #define LEUART_ROUTELOC0_RXLOC_LOC9 (_LEUART_ROUTELOC0_RXLOC_LOC9 << 0) /**< Shifted mode LOC9 for LEUART_ROUTELOC0 */ #define LEUART_ROUTELOC0_RXLOC_LOC10 (_LEUART_ROUTELOC0_RXLOC_LOC10 << 0) /**< Shifted mode LOC10 for LEUART_ROUTELOC0 */ #define LEUART_ROUTELOC0_RXLOC_LOC11 (_LEUART_ROUTELOC0_RXLOC_LOC11 << 0) /**< Shifted mode LOC11 for LEUART_ROUTELOC0 */ #define LEUART_ROUTELOC0_RXLOC_LOC12 (_LEUART_ROUTELOC0_RXLOC_LOC12 << 0) /**< Shifted mode LOC12 for LEUART_ROUTELOC0 */ #define LEUART_ROUTELOC0_RXLOC_LOC13 (_LEUART_ROUTELOC0_RXLOC_LOC13 << 0) /**< Shifted mode LOC13 for LEUART_ROUTELOC0 */ #define LEUART_ROUTELOC0_RXLOC_LOC14 (_LEUART_ROUTELOC0_RXLOC_LOC14 << 0) /**< Shifted mode LOC14 for LEUART_ROUTELOC0 */ #define LEUART_ROUTELOC0_RXLOC_LOC15 (_LEUART_ROUTELOC0_RXLOC_LOC15 << 0) /**< Shifted mode LOC15 for LEUART_ROUTELOC0 */ #define LEUART_ROUTELOC0_RXLOC_LOC16 (_LEUART_ROUTELOC0_RXLOC_LOC16 << 0) /**< Shifted mode LOC16 for LEUART_ROUTELOC0 */ #define LEUART_ROUTELOC0_RXLOC_LOC17 (_LEUART_ROUTELOC0_RXLOC_LOC17 << 0) /**< Shifted mode LOC17 for LEUART_ROUTELOC0 */ #define LEUART_ROUTELOC0_RXLOC_LOC18 (_LEUART_ROUTELOC0_RXLOC_LOC18 << 0) /**< Shifted mode LOC18 for LEUART_ROUTELOC0 */ #define LEUART_ROUTELOC0_RXLOC_LOC19 (_LEUART_ROUTELOC0_RXLOC_LOC19 << 0) /**< Shifted mode LOC19 for LEUART_ROUTELOC0 */ #define LEUART_ROUTELOC0_RXLOC_LOC20 (_LEUART_ROUTELOC0_RXLOC_LOC20 << 0) /**< Shifted mode LOC20 for LEUART_ROUTELOC0 */ #define LEUART_ROUTELOC0_RXLOC_LOC21 (_LEUART_ROUTELOC0_RXLOC_LOC21 << 0) /**< Shifted mode LOC21 for LEUART_ROUTELOC0 */ #define LEUART_ROUTELOC0_RXLOC_LOC22 (_LEUART_ROUTELOC0_RXLOC_LOC22 << 0) /**< Shifted mode LOC22 for LEUART_ROUTELOC0 */ #define LEUART_ROUTELOC0_RXLOC_LOC23 (_LEUART_ROUTELOC0_RXLOC_LOC23 << 0) /**< Shifted mode LOC23 for LEUART_ROUTELOC0 */ #define LEUART_ROUTELOC0_RXLOC_LOC24 (_LEUART_ROUTELOC0_RXLOC_LOC24 << 0) /**< Shifted mode LOC24 for LEUART_ROUTELOC0 */ #define LEUART_ROUTELOC0_RXLOC_LOC25 (_LEUART_ROUTELOC0_RXLOC_LOC25 << 0) /**< Shifted mode LOC25 for LEUART_ROUTELOC0 */ #define LEUART_ROUTELOC0_RXLOC_LOC26 (_LEUART_ROUTELOC0_RXLOC_LOC26 << 0) /**< Shifted mode LOC26 for LEUART_ROUTELOC0 */ #define LEUART_ROUTELOC0_RXLOC_LOC27 (_LEUART_ROUTELOC0_RXLOC_LOC27 << 0) /**< Shifted mode LOC27 for LEUART_ROUTELOC0 */ #define LEUART_ROUTELOC0_RXLOC_LOC28 (_LEUART_ROUTELOC0_RXLOC_LOC28 << 0) /**< Shifted mode LOC28 for LEUART_ROUTELOC0 */ #define LEUART_ROUTELOC0_RXLOC_LOC29 (_LEUART_ROUTELOC0_RXLOC_LOC29 << 0) /**< Shifted mode LOC29 for LEUART_ROUTELOC0 */ #define LEUART_ROUTELOC0_RXLOC_LOC30 (_LEUART_ROUTELOC0_RXLOC_LOC30 << 0) /**< Shifted mode LOC30 for LEUART_ROUTELOC0 */ #define LEUART_ROUTELOC0_RXLOC_LOC31 (_LEUART_ROUTELOC0_RXLOC_LOC31 << 0) /**< Shifted mode LOC31 for LEUART_ROUTELOC0 */ #define _LEUART_ROUTELOC0_TXLOC_SHIFT 8 /**< Shift value for LEUART_TXLOC */ #define _LEUART_ROUTELOC0_TXLOC_MASK 0x1F00UL /**< Bit mask for LEUART_TXLOC */ #define _LEUART_ROUTELOC0_TXLOC_LOC0 0x00000000UL /**< Mode LOC0 for LEUART_ROUTELOC0 */ #define _LEUART_ROUTELOC0_TXLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_ROUTELOC0 */ #define _LEUART_ROUTELOC0_TXLOC_LOC1 0x00000001UL /**< Mode LOC1 for LEUART_ROUTELOC0 */ #define _LEUART_ROUTELOC0_TXLOC_LOC2 0x00000002UL /**< Mode LOC2 for LEUART_ROUTELOC0 */ #define _LEUART_ROUTELOC0_TXLOC_LOC3 0x00000003UL /**< Mode LOC3 for LEUART_ROUTELOC0 */ #define _LEUART_ROUTELOC0_TXLOC_LOC4 0x00000004UL /**< Mode LOC4 for LEUART_ROUTELOC0 */ #define _LEUART_ROUTELOC0_TXLOC_LOC5 0x00000005UL /**< Mode LOC5 for LEUART_ROUTELOC0 */ #define _LEUART_ROUTELOC0_TXLOC_LOC6 0x00000006UL /**< Mode LOC6 for LEUART_ROUTELOC0 */ #define _LEUART_ROUTELOC0_TXLOC_LOC7 0x00000007UL /**< Mode LOC7 for LEUART_ROUTELOC0 */ #define _LEUART_ROUTELOC0_TXLOC_LOC8 0x00000008UL /**< Mode LOC8 for LEUART_ROUTELOC0 */ #define _LEUART_ROUTELOC0_TXLOC_LOC9 0x00000009UL /**< Mode LOC9 for LEUART_ROUTELOC0 */ #define _LEUART_ROUTELOC0_TXLOC_LOC10 0x0000000AUL /**< Mode LOC10 for LEUART_ROUTELOC0 */ #define _LEUART_ROUTELOC0_TXLOC_LOC11 0x0000000BUL /**< Mode LOC11 for LEUART_ROUTELOC0 */ #define _LEUART_ROUTELOC0_TXLOC_LOC12 0x0000000CUL /**< Mode LOC12 for LEUART_ROUTELOC0 */ #define _LEUART_ROUTELOC0_TXLOC_LOC13 0x0000000DUL /**< Mode LOC13 for LEUART_ROUTELOC0 */ #define _LEUART_ROUTELOC0_TXLOC_LOC14 0x0000000EUL /**< Mode LOC14 for LEUART_ROUTELOC0 */ #define _LEUART_ROUTELOC0_TXLOC_LOC15 0x0000000FUL /**< Mode LOC15 for LEUART_ROUTELOC0 */ #define _LEUART_ROUTELOC0_TXLOC_LOC16 0x00000010UL /**< Mode LOC16 for LEUART_ROUTELOC0 */ #define _LEUART_ROUTELOC0_TXLOC_LOC17 0x00000011UL /**< Mode LOC17 for LEUART_ROUTELOC0 */ #define _LEUART_ROUTELOC0_TXLOC_LOC18 0x00000012UL /**< Mode LOC18 for LEUART_ROUTELOC0 */ #define _LEUART_ROUTELOC0_TXLOC_LOC19 0x00000013UL /**< Mode LOC19 for LEUART_ROUTELOC0 */ #define _LEUART_ROUTELOC0_TXLOC_LOC20 0x00000014UL /**< Mode LOC20 for LEUART_ROUTELOC0 */ #define _LEUART_ROUTELOC0_TXLOC_LOC21 0x00000015UL /**< Mode LOC21 for LEUART_ROUTELOC0 */ #define _LEUART_ROUTELOC0_TXLOC_LOC22 0x00000016UL /**< Mode LOC22 for LEUART_ROUTELOC0 */ #define _LEUART_ROUTELOC0_TXLOC_LOC23 0x00000017UL /**< Mode LOC23 for LEUART_ROUTELOC0 */ #define _LEUART_ROUTELOC0_TXLOC_LOC24 0x00000018UL /**< Mode LOC24 for LEUART_ROUTELOC0 */ #define _LEUART_ROUTELOC0_TXLOC_LOC25 0x00000019UL /**< Mode LOC25 for LEUART_ROUTELOC0 */ #define _LEUART_ROUTELOC0_TXLOC_LOC26 0x0000001AUL /**< Mode LOC26 for LEUART_ROUTELOC0 */ #define _LEUART_ROUTELOC0_TXLOC_LOC27 0x0000001BUL /**< Mode LOC27 for LEUART_ROUTELOC0 */ #define _LEUART_ROUTELOC0_TXLOC_LOC28 0x0000001CUL /**< Mode LOC28 for LEUART_ROUTELOC0 */ #define _LEUART_ROUTELOC0_TXLOC_LOC29 0x0000001DUL /**< Mode LOC29 for LEUART_ROUTELOC0 */ #define _LEUART_ROUTELOC0_TXLOC_LOC30 0x0000001EUL /**< Mode LOC30 for LEUART_ROUTELOC0 */ #define _LEUART_ROUTELOC0_TXLOC_LOC31 0x0000001FUL /**< Mode LOC31 for LEUART_ROUTELOC0 */ #define LEUART_ROUTELOC0_TXLOC_LOC0 (_LEUART_ROUTELOC0_TXLOC_LOC0 << 8) /**< Shifted mode LOC0 for LEUART_ROUTELOC0 */ #define LEUART_ROUTELOC0_TXLOC_DEFAULT (_LEUART_ROUTELOC0_TXLOC_DEFAULT << 8) /**< Shifted mode DEFAULT for LEUART_ROUTELOC0 */ #define LEUART_ROUTELOC0_TXLOC_LOC1 (_LEUART_ROUTELOC0_TXLOC_LOC1 << 8) /**< Shifted mode LOC1 for LEUART_ROUTELOC0 */ #define LEUART_ROUTELOC0_TXLOC_LOC2 (_LEUART_ROUTELOC0_TXLOC_LOC2 << 8) /**< Shifted mode LOC2 for LEUART_ROUTELOC0 */ #define LEUART_ROUTELOC0_TXLOC_LOC3 (_LEUART_ROUTELOC0_TXLOC_LOC3 << 8) /**< Shifted mode LOC3 for LEUART_ROUTELOC0 */ #define LEUART_ROUTELOC0_TXLOC_LOC4 (_LEUART_ROUTELOC0_TXLOC_LOC4 << 8) /**< Shifted mode LOC4 for LEUART_ROUTELOC0 */ #define LEUART_ROUTELOC0_TXLOC_LOC5 (_LEUART_ROUTELOC0_TXLOC_LOC5 << 8) /**< Shifted mode LOC5 for LEUART_ROUTELOC0 */ #define LEUART_ROUTELOC0_TXLOC_LOC6 (_LEUART_ROUTELOC0_TXLOC_LOC6 << 8) /**< Shifted mode LOC6 for LEUART_ROUTELOC0 */ #define LEUART_ROUTELOC0_TXLOC_LOC7 (_LEUART_ROUTELOC0_TXLOC_LOC7 << 8) /**< Shifted mode LOC7 for LEUART_ROUTELOC0 */ #define LEUART_ROUTELOC0_TXLOC_LOC8 (_LEUART_ROUTELOC0_TXLOC_LOC8 << 8) /**< Shifted mode LOC8 for LEUART_ROUTELOC0 */ #define LEUART_ROUTELOC0_TXLOC_LOC9 (_LEUART_ROUTELOC0_TXLOC_LOC9 << 8) /**< Shifted mode LOC9 for LEUART_ROUTELOC0 */ #define LEUART_ROUTELOC0_TXLOC_LOC10 (_LEUART_ROUTELOC0_TXLOC_LOC10 << 8) /**< Shifted mode LOC10 for LEUART_ROUTELOC0 */ #define LEUART_ROUTELOC0_TXLOC_LOC11 (_LEUART_ROUTELOC0_TXLOC_LOC11 << 8) /**< Shifted mode LOC11 for LEUART_ROUTELOC0 */ #define LEUART_ROUTELOC0_TXLOC_LOC12 (_LEUART_ROUTELOC0_TXLOC_LOC12 << 8) /**< Shifted mode LOC12 for LEUART_ROUTELOC0 */ #define LEUART_ROUTELOC0_TXLOC_LOC13 (_LEUART_ROUTELOC0_TXLOC_LOC13 << 8) /**< Shifted mode LOC13 for LEUART_ROUTELOC0 */ #define LEUART_ROUTELOC0_TXLOC_LOC14 (_LEUART_ROUTELOC0_TXLOC_LOC14 << 8) /**< Shifted mode LOC14 for LEUART_ROUTELOC0 */ #define LEUART_ROUTELOC0_TXLOC_LOC15 (_LEUART_ROUTELOC0_TXLOC_LOC15 << 8) /**< Shifted mode LOC15 for LEUART_ROUTELOC0 */ #define LEUART_ROUTELOC0_TXLOC_LOC16 (_LEUART_ROUTELOC0_TXLOC_LOC16 << 8) /**< Shifted mode LOC16 for LEUART_ROUTELOC0 */ #define LEUART_ROUTELOC0_TXLOC_LOC17 (_LEUART_ROUTELOC0_TXLOC_LOC17 << 8) /**< Shifted mode LOC17 for LEUART_ROUTELOC0 */ #define LEUART_ROUTELOC0_TXLOC_LOC18 (_LEUART_ROUTELOC0_TXLOC_LOC18 << 8) /**< Shifted mode LOC18 for LEUART_ROUTELOC0 */ #define LEUART_ROUTELOC0_TXLOC_LOC19 (_LEUART_ROUTELOC0_TXLOC_LOC19 << 8) /**< Shifted mode LOC19 for LEUART_ROUTELOC0 */ #define LEUART_ROUTELOC0_TXLOC_LOC20 (_LEUART_ROUTELOC0_TXLOC_LOC20 << 8) /**< Shifted mode LOC20 for LEUART_ROUTELOC0 */ #define LEUART_ROUTELOC0_TXLOC_LOC21 (_LEUART_ROUTELOC0_TXLOC_LOC21 << 8) /**< Shifted mode LOC21 for LEUART_ROUTELOC0 */ #define LEUART_ROUTELOC0_TXLOC_LOC22 (_LEUART_ROUTELOC0_TXLOC_LOC22 << 8) /**< Shifted mode LOC22 for LEUART_ROUTELOC0 */ #define LEUART_ROUTELOC0_TXLOC_LOC23 (_LEUART_ROUTELOC0_TXLOC_LOC23 << 8) /**< Shifted mode LOC23 for LEUART_ROUTELOC0 */ #define LEUART_ROUTELOC0_TXLOC_LOC24 (_LEUART_ROUTELOC0_TXLOC_LOC24 << 8) /**< Shifted mode LOC24 for LEUART_ROUTELOC0 */ #define LEUART_ROUTELOC0_TXLOC_LOC25 (_LEUART_ROUTELOC0_TXLOC_LOC25 << 8) /**< Shifted mode LOC25 for LEUART_ROUTELOC0 */ #define LEUART_ROUTELOC0_TXLOC_LOC26 (_LEUART_ROUTELOC0_TXLOC_LOC26 << 8) /**< Shifted mode LOC26 for LEUART_ROUTELOC0 */ #define LEUART_ROUTELOC0_TXLOC_LOC27 (_LEUART_ROUTELOC0_TXLOC_LOC27 << 8) /**< Shifted mode LOC27 for LEUART_ROUTELOC0 */ #define LEUART_ROUTELOC0_TXLOC_LOC28 (_LEUART_ROUTELOC0_TXLOC_LOC28 << 8) /**< Shifted mode LOC28 for LEUART_ROUTELOC0 */ #define LEUART_ROUTELOC0_TXLOC_LOC29 (_LEUART_ROUTELOC0_TXLOC_LOC29 << 8) /**< Shifted mode LOC29 for LEUART_ROUTELOC0 */ #define LEUART_ROUTELOC0_TXLOC_LOC30 (_LEUART_ROUTELOC0_TXLOC_LOC30 << 8) /**< Shifted mode LOC30 for LEUART_ROUTELOC0 */ #define LEUART_ROUTELOC0_TXLOC_LOC31 (_LEUART_ROUTELOC0_TXLOC_LOC31 << 8) /**< Shifted mode LOC31 for LEUART_ROUTELOC0 */ /* Bit fields for LEUART INPUT */ #define _LEUART_INPUT_RESETVALUE 0x00000000UL /**< Default value for LEUART_INPUT */ #define _LEUART_INPUT_MASK 0x0000002FUL /**< Mask for LEUART_INPUT */ #define _LEUART_INPUT_RXPRSSEL_SHIFT 0 /**< Shift value for LEUART_RXPRSSEL */ #define _LEUART_INPUT_RXPRSSEL_MASK 0xFUL /**< Bit mask for LEUART_RXPRSSEL */ #define _LEUART_INPUT_RXPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_INPUT */ #define _LEUART_INPUT_RXPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for LEUART_INPUT */ #define _LEUART_INPUT_RXPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for LEUART_INPUT */ #define _LEUART_INPUT_RXPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for LEUART_INPUT */ #define _LEUART_INPUT_RXPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for LEUART_INPUT */ #define _LEUART_INPUT_RXPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for LEUART_INPUT */ #define _LEUART_INPUT_RXPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for LEUART_INPUT */ #define _LEUART_INPUT_RXPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for LEUART_INPUT */ #define _LEUART_INPUT_RXPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for LEUART_INPUT */ #define _LEUART_INPUT_RXPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for LEUART_INPUT */ #define _LEUART_INPUT_RXPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for LEUART_INPUT */ #define _LEUART_INPUT_RXPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for LEUART_INPUT */ #define _LEUART_INPUT_RXPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for LEUART_INPUT */ #define LEUART_INPUT_RXPRSSEL_DEFAULT (_LEUART_INPUT_RXPRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_INPUT */ #define LEUART_INPUT_RXPRSSEL_PRSCH0 (_LEUART_INPUT_RXPRSSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for LEUART_INPUT */ #define LEUART_INPUT_RXPRSSEL_PRSCH1 (_LEUART_INPUT_RXPRSSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for LEUART_INPUT */ #define LEUART_INPUT_RXPRSSEL_PRSCH2 (_LEUART_INPUT_RXPRSSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for LEUART_INPUT */ #define LEUART_INPUT_RXPRSSEL_PRSCH3 (_LEUART_INPUT_RXPRSSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for LEUART_INPUT */ #define LEUART_INPUT_RXPRSSEL_PRSCH4 (_LEUART_INPUT_RXPRSSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for LEUART_INPUT */ #define LEUART_INPUT_RXPRSSEL_PRSCH5 (_LEUART_INPUT_RXPRSSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for LEUART_INPUT */ #define LEUART_INPUT_RXPRSSEL_PRSCH6 (_LEUART_INPUT_RXPRSSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for LEUART_INPUT */ #define LEUART_INPUT_RXPRSSEL_PRSCH7 (_LEUART_INPUT_RXPRSSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for LEUART_INPUT */ #define LEUART_INPUT_RXPRSSEL_PRSCH8 (_LEUART_INPUT_RXPRSSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for LEUART_INPUT */ #define LEUART_INPUT_RXPRSSEL_PRSCH9 (_LEUART_INPUT_RXPRSSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for LEUART_INPUT */ #define LEUART_INPUT_RXPRSSEL_PRSCH10 (_LEUART_INPUT_RXPRSSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for LEUART_INPUT */ #define LEUART_INPUT_RXPRSSEL_PRSCH11 (_LEUART_INPUT_RXPRSSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for LEUART_INPUT */ #define LEUART_INPUT_RXPRS (0x1UL << 5) /**< PRS RX Enable */ #define _LEUART_INPUT_RXPRS_SHIFT 5 /**< Shift value for LEUART_RXPRS */ #define _LEUART_INPUT_RXPRS_MASK 0x20UL /**< Bit mask for LEUART_RXPRS */ #define _LEUART_INPUT_RXPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_INPUT */ #define LEUART_INPUT_RXPRS_DEFAULT (_LEUART_INPUT_RXPRS_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_INPUT */ /** @} */ /** @} End of group EFR32MG12P_LEUART */ /** @} End of group Parts */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_msc.h.
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/***************************************************************************//** * @file * @brief EFR32MG12P_MSC register and bit field definitions * @version 5.7.0 ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * SPDX-License-Identifier: Zlib * * The licensor of this software is Silicon Laboratories Inc. * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be * appreciated but is not required. * 2. Altered source versions must be plainly marked as such, and must not be * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * ******************************************************************************/ #if defined(__ICCARM__) #pragma system_include /* Treat file as system include file. */ #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang system_header /* Treat file as system include file. */ #endif /***************************************************************************//** * @addtogroup Parts * @{ ******************************************************************************/ /***************************************************************************//** * @defgroup EFR32MG12P_MSC MSC * @{ * @brief EFR32MG12P_MSC Register Declaration ******************************************************************************/ /** MSC Register Declaration */ typedef struct { __IOM uint32_t CTRL; /**< Memory System Control Register */ __IOM uint32_t READCTRL; /**< Read Control Register */ __IOM uint32_t WRITECTRL; /**< Write Control Register */ __IOM uint32_t WRITECMD; /**< Write Command Register */ __IOM uint32_t ADDRB; /**< Page Erase/Write Address Buffer */ uint32_t RESERVED0[1U]; /**< Reserved for future use **/ __IOM uint32_t WDATA; /**< Write Data Register */ __IM uint32_t STATUS; /**< Status Register */ uint32_t RESERVED1[4U]; /**< Reserved for future use **/ __IM uint32_t IF; /**< Interrupt Flag Register */ __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ __IOM uint32_t IEN; /**< Interrupt Enable Register */ __IOM uint32_t LOCK; /**< Configuration Lock Register */ __IOM uint32_t CACHECMD; /**< Flash Cache Command Register */ __IM uint32_t CACHEHITS; /**< Cache Hits Performance Counter */ __IM uint32_t CACHEMISSES; /**< Cache Misses Performance Counter */ uint32_t RESERVED2[1U]; /**< Reserved for future use **/ __IOM uint32_t MASSLOCK; /**< Mass Erase Lock Register */ uint32_t RESERVED3[1U]; /**< Reserved for future use **/ __IOM uint32_t STARTUP; /**< Startup Control */ uint32_t RESERVED4[4U]; /**< Reserved for future use **/ __IOM uint32_t BANKSWITCHLOCK; /**< Bank Switching Lock Register */ __IOM uint32_t CMD; /**< Command Register */ uint32_t RESERVED5[6U]; /**< Reserved for future use **/ __IOM uint32_t BOOTLOADERCTRL; /**< Bootloader Read and Write Enable, Write Once Register */ __IOM uint32_t AAPUNLOCKCMD; /**< Software Unlock AAP Command Register */ __IOM uint32_t CACHECONFIG0; /**< Cache Configuration Register 0 */ uint32_t RESERVED6[25U]; /**< Reserved for future use **/ __IOM uint32_t RAMCTRL; /**< RAM Control Enable Register */ } MSC_TypeDef; /** @} */ /***************************************************************************//** * @addtogroup EFR32MG12P_MSC * @{ * @defgroup EFR32MG12P_MSC_BitFields MSC Bit Fields * @{ ******************************************************************************/ /* Bit fields for MSC CTRL */ #define _MSC_CTRL_RESETVALUE 0x00000001UL /**< Default value for MSC_CTRL */ #define _MSC_CTRL_MASK 0x0000001FUL /**< Mask for MSC_CTRL */ #define MSC_CTRL_ADDRFAULTEN (0x1UL << 0) /**< Invalid Address Bus Fault Response Enable */ #define _MSC_CTRL_ADDRFAULTEN_SHIFT 0 /**< Shift value for MSC_ADDRFAULTEN */ #define _MSC_CTRL_ADDRFAULTEN_MASK 0x1UL /**< Bit mask for MSC_ADDRFAULTEN */ #define _MSC_CTRL_ADDRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_CTRL */ #define MSC_CTRL_ADDRFAULTEN_DEFAULT (_MSC_CTRL_ADDRFAULTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CTRL */ #define MSC_CTRL_CLKDISFAULTEN (0x1UL << 1) /**< Clock-disabled Bus Fault Response Enable */ #define _MSC_CTRL_CLKDISFAULTEN_SHIFT 1 /**< Shift value for MSC_CLKDISFAULTEN */ #define _MSC_CTRL_CLKDISFAULTEN_MASK 0x2UL /**< Bit mask for MSC_CLKDISFAULTEN */ #define _MSC_CTRL_CLKDISFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ #define MSC_CTRL_CLKDISFAULTEN_DEFAULT (_MSC_CTRL_CLKDISFAULTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CTRL */ #define MSC_CTRL_PWRUPONDEMAND (0x1UL << 2) /**< Power Up on Demand During Wake Up */ #define _MSC_CTRL_PWRUPONDEMAND_SHIFT 2 /**< Shift value for MSC_PWRUPONDEMAND */ #define _MSC_CTRL_PWRUPONDEMAND_MASK 0x4UL /**< Bit mask for MSC_PWRUPONDEMAND */ #define _MSC_CTRL_PWRUPONDEMAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ #define MSC_CTRL_PWRUPONDEMAND_DEFAULT (_MSC_CTRL_PWRUPONDEMAND_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_CTRL */ #define MSC_CTRL_IFCREADCLEAR (0x1UL << 3) /**< IFC Read Clears IF */ #define _MSC_CTRL_IFCREADCLEAR_SHIFT 3 /**< Shift value for MSC_IFCREADCLEAR */ #define _MSC_CTRL_IFCREADCLEAR_MASK 0x8UL /**< Bit mask for MSC_IFCREADCLEAR */ #define _MSC_CTRL_IFCREADCLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ #define MSC_CTRL_IFCREADCLEAR_DEFAULT (_MSC_CTRL_IFCREADCLEAR_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_CTRL */ #define MSC_CTRL_TIMEOUTFAULTEN (0x1UL << 4) /**< Timeout Bus Fault Response Enable */ #define _MSC_CTRL_TIMEOUTFAULTEN_SHIFT 4 /**< Shift value for MSC_TIMEOUTFAULTEN */ #define _MSC_CTRL_TIMEOUTFAULTEN_MASK 0x10UL /**< Bit mask for MSC_TIMEOUTFAULTEN */ #define _MSC_CTRL_TIMEOUTFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ #define MSC_CTRL_TIMEOUTFAULTEN_DEFAULT (_MSC_CTRL_TIMEOUTFAULTEN_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_CTRL */ /* Bit fields for MSC READCTRL */ #define _MSC_READCTRL_RESETVALUE 0x01000100UL /**< Default value for MSC_READCTRL */ #define _MSC_READCTRL_MASK 0x13000338UL /**< Mask for MSC_READCTRL */ #define MSC_READCTRL_IFCDIS (0x1UL << 3) /**< Internal Flash Cache Disable */ #define _MSC_READCTRL_IFCDIS_SHIFT 3 /**< Shift value for MSC_IFCDIS */ #define _MSC_READCTRL_IFCDIS_MASK 0x8UL /**< Bit mask for MSC_IFCDIS */ #define _MSC_READCTRL_IFCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ #define MSC_READCTRL_IFCDIS_DEFAULT (_MSC_READCTRL_IFCDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_READCTRL */ #define MSC_READCTRL_AIDIS (0x1UL << 4) /**< Automatic Invalidate Disable */ #define _MSC_READCTRL_AIDIS_SHIFT 4 /**< Shift value for MSC_AIDIS */ #define _MSC_READCTRL_AIDIS_MASK 0x10UL /**< Bit mask for MSC_AIDIS */ #define _MSC_READCTRL_AIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ #define MSC_READCTRL_AIDIS_DEFAULT (_MSC_READCTRL_AIDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_READCTRL */ #define MSC_READCTRL_ICCDIS (0x1UL << 5) /**< Interrupt Context Cache Disable */ #define _MSC_READCTRL_ICCDIS_SHIFT 5 /**< Shift value for MSC_ICCDIS */ #define _MSC_READCTRL_ICCDIS_MASK 0x20UL /**< Bit mask for MSC_ICCDIS */ #define _MSC_READCTRL_ICCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ #define MSC_READCTRL_ICCDIS_DEFAULT (_MSC_READCTRL_ICCDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_READCTRL */ #define MSC_READCTRL_PREFETCH (0x1UL << 8) /**< Prefetch Mode */ #define _MSC_READCTRL_PREFETCH_SHIFT 8 /**< Shift value for MSC_PREFETCH */ #define _MSC_READCTRL_PREFETCH_MASK 0x100UL /**< Bit mask for MSC_PREFETCH */ #define _MSC_READCTRL_PREFETCH_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_READCTRL */ #define MSC_READCTRL_PREFETCH_DEFAULT (_MSC_READCTRL_PREFETCH_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_READCTRL */ #define MSC_READCTRL_USEHPROT (0x1UL << 9) /**< AHB_HPROT Mode */ #define _MSC_READCTRL_USEHPROT_SHIFT 9 /**< Shift value for MSC_USEHPROT */ #define _MSC_READCTRL_USEHPROT_MASK 0x200UL /**< Bit mask for MSC_USEHPROT */ #define _MSC_READCTRL_USEHPROT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ #define MSC_READCTRL_USEHPROT_DEFAULT (_MSC_READCTRL_USEHPROT_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_READCTRL */ #define _MSC_READCTRL_MODE_SHIFT 24 /**< Shift value for MSC_MODE */ #define _MSC_READCTRL_MODE_MASK 0x3000000UL /**< Bit mask for MSC_MODE */ #define _MSC_READCTRL_MODE_WS0 0x00000000UL /**< Mode WS0 for MSC_READCTRL */ #define _MSC_READCTRL_MODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_READCTRL */ #define _MSC_READCTRL_MODE_WS1 0x00000001UL /**< Mode WS1 for MSC_READCTRL */ #define _MSC_READCTRL_MODE_WS2 0x00000002UL /**< Mode WS2 for MSC_READCTRL */ #define _MSC_READCTRL_MODE_WS3 0x00000003UL /**< Mode WS3 for MSC_READCTRL */ #define MSC_READCTRL_MODE_WS0 (_MSC_READCTRL_MODE_WS0 << 24) /**< Shifted mode WS0 for MSC_READCTRL */ #define MSC_READCTRL_MODE_DEFAULT (_MSC_READCTRL_MODE_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_READCTRL */ #define MSC_READCTRL_MODE_WS1 (_MSC_READCTRL_MODE_WS1 << 24) /**< Shifted mode WS1 for MSC_READCTRL */ #define MSC_READCTRL_MODE_WS2 (_MSC_READCTRL_MODE_WS2 << 24) /**< Shifted mode WS2 for MSC_READCTRL */ #define MSC_READCTRL_MODE_WS3 (_MSC_READCTRL_MODE_WS3 << 24) /**< Shifted mode WS3 for MSC_READCTRL */ #define MSC_READCTRL_SCBTP (0x1UL << 28) /**< Suppress Conditional Branch Target Perfetch */ #define _MSC_READCTRL_SCBTP_SHIFT 28 /**< Shift value for MSC_SCBTP */ #define _MSC_READCTRL_SCBTP_MASK 0x10000000UL /**< Bit mask for MSC_SCBTP */ #define _MSC_READCTRL_SCBTP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ #define MSC_READCTRL_SCBTP_DEFAULT (_MSC_READCTRL_SCBTP_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_READCTRL */ /* Bit fields for MSC WRITECTRL */ #define _MSC_WRITECTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECTRL */ #define _MSC_WRITECTRL_MASK 0x00000023UL /**< Mask for MSC_WRITECTRL */ #define MSC_WRITECTRL_WREN (0x1UL << 0) /**< Enable Write/Erase Controller */ #define _MSC_WRITECTRL_WREN_SHIFT 0 /**< Shift value for MSC_WREN */ #define _MSC_WRITECTRL_WREN_MASK 0x1UL /**< Bit mask for MSC_WREN */ #define _MSC_WRITECTRL_WREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ #define MSC_WRITECTRL_WREN_DEFAULT (_MSC_WRITECTRL_WREN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ #define MSC_WRITECTRL_IRQERASEABORT (0x1UL << 1) /**< Abort Page Erase on Interrupt */ #define _MSC_WRITECTRL_IRQERASEABORT_SHIFT 1 /**< Shift value for MSC_IRQERASEABORT */ #define _MSC_WRITECTRL_IRQERASEABORT_MASK 0x2UL /**< Bit mask for MSC_IRQERASEABORT */ #define _MSC_WRITECTRL_IRQERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ #define MSC_WRITECTRL_IRQERASEABORT_DEFAULT (_MSC_WRITECTRL_IRQERASEABORT_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ #define MSC_WRITECTRL_RWWEN (0x1UL << 5) /**< Read-While-Write Enable */ #define _MSC_WRITECTRL_RWWEN_SHIFT 5 /**< Shift value for MSC_RWWEN */ #define _MSC_WRITECTRL_RWWEN_MASK 0x20UL /**< Bit mask for MSC_RWWEN */ #define _MSC_WRITECTRL_RWWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ #define MSC_WRITECTRL_RWWEN_DEFAULT (_MSC_WRITECTRL_RWWEN_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ /* Bit fields for MSC WRITECMD */ #define _MSC_WRITECMD_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECMD */ #define _MSC_WRITECMD_MASK 0x0000133FUL /**< Mask for MSC_WRITECMD */ #define MSC_WRITECMD_LADDRIM (0x1UL << 0) /**< Load MSC_ADDRB Into ADDR */ #define _MSC_WRITECMD_LADDRIM_SHIFT 0 /**< Shift value for MSC_LADDRIM */ #define _MSC_WRITECMD_LADDRIM_MASK 0x1UL /**< Bit mask for MSC_LADDRIM */ #define _MSC_WRITECMD_LADDRIM_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ #define MSC_WRITECMD_LADDRIM_DEFAULT (_MSC_WRITECMD_LADDRIM_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECMD */ #define MSC_WRITECMD_ERASEPAGE (0x1UL << 1) /**< Erase Page */ #define _MSC_WRITECMD_ERASEPAGE_SHIFT 1 /**< Shift value for MSC_ERASEPAGE */ #define _MSC_WRITECMD_ERASEPAGE_MASK 0x2UL /**< Bit mask for MSC_ERASEPAGE */ #define _MSC_WRITECMD_ERASEPAGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ #define MSC_WRITECMD_ERASEPAGE_DEFAULT (_MSC_WRITECMD_ERASEPAGE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECMD */ #define MSC_WRITECMD_WRITEEND (0x1UL << 2) /**< End Write Mode */ #define _MSC_WRITECMD_WRITEEND_SHIFT 2 /**< Shift value for MSC_WRITEEND */ #define _MSC_WRITECMD_WRITEEND_MASK 0x4UL /**< Bit mask for MSC_WRITEEND */ #define _MSC_WRITECMD_WRITEEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ #define MSC_WRITECMD_WRITEEND_DEFAULT (_MSC_WRITECMD_WRITEEND_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_WRITECMD */ #define MSC_WRITECMD_WRITEONCE (0x1UL << 3) /**< Word Write-Once Trigger */ #define _MSC_WRITECMD_WRITEONCE_SHIFT 3 /**< Shift value for MSC_WRITEONCE */ #define _MSC_WRITECMD_WRITEONCE_MASK 0x8UL /**< Bit mask for MSC_WRITEONCE */ #define _MSC_WRITECMD_WRITEONCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ #define MSC_WRITECMD_WRITEONCE_DEFAULT (_MSC_WRITECMD_WRITEONCE_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_WRITECMD */ #define MSC_WRITECMD_WRITETRIG (0x1UL << 4) /**< Word Write Sequence Trigger */ #define _MSC_WRITECMD_WRITETRIG_SHIFT 4 /**< Shift value for MSC_WRITETRIG */ #define _MSC_WRITECMD_WRITETRIG_MASK 0x10UL /**< Bit mask for MSC_WRITETRIG */ #define _MSC_WRITECMD_WRITETRIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ #define MSC_WRITECMD_WRITETRIG_DEFAULT (_MSC_WRITECMD_WRITETRIG_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_WRITECMD */ #define MSC_WRITECMD_ERASEABORT (0x1UL << 5) /**< Abort Erase Sequence */ #define _MSC_WRITECMD_ERASEABORT_SHIFT 5 /**< Shift value for MSC_ERASEABORT */ #define _MSC_WRITECMD_ERASEABORT_MASK 0x20UL /**< Bit mask for MSC_ERASEABORT */ #define _MSC_WRITECMD_ERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ #define MSC_WRITECMD_ERASEABORT_DEFAULT (_MSC_WRITECMD_ERASEABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_WRITECMD */ #define MSC_WRITECMD_ERASEMAIN0 (0x1UL << 8) /**< Mass Erase Region 0 */ #define _MSC_WRITECMD_ERASEMAIN0_SHIFT 8 /**< Shift value for MSC_ERASEMAIN0 */ #define _MSC_WRITECMD_ERASEMAIN0_MASK 0x100UL /**< Bit mask for MSC_ERASEMAIN0 */ #define _MSC_WRITECMD_ERASEMAIN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ #define MSC_WRITECMD_ERASEMAIN0_DEFAULT (_MSC_WRITECMD_ERASEMAIN0_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_WRITECMD */ #define MSC_WRITECMD_ERASEMAIN1 (0x1UL << 9) /**< Mass Erase Region 1 */ #define _MSC_WRITECMD_ERASEMAIN1_SHIFT 9 /**< Shift value for MSC_ERASEMAIN1 */ #define _MSC_WRITECMD_ERASEMAIN1_MASK 0x200UL /**< Bit mask for MSC_ERASEMAIN1 */ #define _MSC_WRITECMD_ERASEMAIN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ #define MSC_WRITECMD_ERASEMAIN1_DEFAULT (_MSC_WRITECMD_ERASEMAIN1_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_WRITECMD */ #define MSC_WRITECMD_CLEARWDATA (0x1UL << 12) /**< Clear WDATA State */ #define _MSC_WRITECMD_CLEARWDATA_SHIFT 12 /**< Shift value for MSC_CLEARWDATA */ #define _MSC_WRITECMD_CLEARWDATA_MASK 0x1000UL /**< Bit mask for MSC_CLEARWDATA */ #define _MSC_WRITECMD_CLEARWDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ #define MSC_WRITECMD_CLEARWDATA_DEFAULT (_MSC_WRITECMD_CLEARWDATA_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_WRITECMD */ /* Bit fields for MSC ADDRB */ #define _MSC_ADDRB_RESETVALUE 0x00000000UL /**< Default value for MSC_ADDRB */ #define _MSC_ADDRB_MASK 0xFFFFFFFFUL /**< Mask for MSC_ADDRB */ #define _MSC_ADDRB_ADDRB_SHIFT 0 /**< Shift value for MSC_ADDRB */ #define _MSC_ADDRB_ADDRB_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_ADDRB */ #define _MSC_ADDRB_ADDRB_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ADDRB */ #define MSC_ADDRB_ADDRB_DEFAULT (_MSC_ADDRB_ADDRB_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_ADDRB */ /* Bit fields for MSC WDATA */ #define _MSC_WDATA_RESETVALUE 0x00000000UL /**< Default value for MSC_WDATA */ #define _MSC_WDATA_MASK 0xFFFFFFFFUL /**< Mask for MSC_WDATA */ #define _MSC_WDATA_WDATA_SHIFT 0 /**< Shift value for MSC_WDATA */ #define _MSC_WDATA_WDATA_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_WDATA */ #define _MSC_WDATA_WDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WDATA */ #define MSC_WDATA_WDATA_DEFAULT (_MSC_WDATA_WDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WDATA */ /* Bit fields for MSC STATUS */ #define _MSC_STATUS_RESETVALUE 0x00000008UL /**< Default value for MSC_STATUS */ #define _MSC_STATUS_MASK 0xFF0000FFUL /**< Mask for MSC_STATUS */ #define MSC_STATUS_BUSY (0x1UL << 0) /**< Erase/Write Busy */ #define _MSC_STATUS_BUSY_SHIFT 0 /**< Shift value for MSC_BUSY */ #define _MSC_STATUS_BUSY_MASK 0x1UL /**< Bit mask for MSC_BUSY */ #define _MSC_STATUS_BUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ #define MSC_STATUS_BUSY_DEFAULT (_MSC_STATUS_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_STATUS */ #define MSC_STATUS_LOCKED (0x1UL << 1) /**< Access Locked */ #define _MSC_STATUS_LOCKED_SHIFT 1 /**< Shift value for MSC_LOCKED */ #define _MSC_STATUS_LOCKED_MASK 0x2UL /**< Bit mask for MSC_LOCKED */ #define _MSC_STATUS_LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ #define MSC_STATUS_LOCKED_DEFAULT (_MSC_STATUS_LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_STATUS */ #define MSC_STATUS_INVADDR (0x1UL << 2) /**< Invalid Write Address or Erase Page */ #define _MSC_STATUS_INVADDR_SHIFT 2 /**< Shift value for MSC_INVADDR */ #define _MSC_STATUS_INVADDR_MASK 0x4UL /**< Bit mask for MSC_INVADDR */ #define _MSC_STATUS_INVADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ #define MSC_STATUS_INVADDR_DEFAULT (_MSC_STATUS_INVADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_STATUS */ #define MSC_STATUS_WDATAREADY (0x1UL << 3) /**< WDATA Write Ready */ #define _MSC_STATUS_WDATAREADY_SHIFT 3 /**< Shift value for MSC_WDATAREADY */ #define _MSC_STATUS_WDATAREADY_MASK 0x8UL /**< Bit mask for MSC_WDATAREADY */ #define _MSC_STATUS_WDATAREADY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STATUS */ #define MSC_STATUS_WDATAREADY_DEFAULT (_MSC_STATUS_WDATAREADY_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_STATUS */ #define MSC_STATUS_WORDTIMEOUT (0x1UL << 4) /**< Flash Write Word Timeout */ #define _MSC_STATUS_WORDTIMEOUT_SHIFT 4 /**< Shift value for MSC_WORDTIMEOUT */ #define _MSC_STATUS_WORDTIMEOUT_MASK 0x10UL /**< Bit mask for MSC_WORDTIMEOUT */ #define _MSC_STATUS_WORDTIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ #define MSC_STATUS_WORDTIMEOUT_DEFAULT (_MSC_STATUS_WORDTIMEOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_STATUS */ #define MSC_STATUS_ERASEABORTED (0x1UL << 5) /**< The Current Flash Erase Operation Aborted */ #define _MSC_STATUS_ERASEABORTED_SHIFT 5 /**< Shift value for MSC_ERASEABORTED */ #define _MSC_STATUS_ERASEABORTED_MASK 0x20UL /**< Bit mask for MSC_ERASEABORTED */ #define _MSC_STATUS_ERASEABORTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ #define MSC_STATUS_ERASEABORTED_DEFAULT (_MSC_STATUS_ERASEABORTED_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_STATUS */ #define MSC_STATUS_PCRUNNING (0x1UL << 6) /**< Performance Counters Running */ #define _MSC_STATUS_PCRUNNING_SHIFT 6 /**< Shift value for MSC_PCRUNNING */ #define _MSC_STATUS_PCRUNNING_MASK 0x40UL /**< Bit mask for MSC_PCRUNNING */ #define _MSC_STATUS_PCRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ #define MSC_STATUS_PCRUNNING_DEFAULT (_MSC_STATUS_PCRUNNING_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_STATUS */ #define MSC_STATUS_BANKSWITCHED (0x1UL << 7) /**< BANK SWITCHING STATUS */ #define _MSC_STATUS_BANKSWITCHED_SHIFT 7 /**< Shift value for MSC_BANKSWITCHED */ #define _MSC_STATUS_BANKSWITCHED_MASK 0x80UL /**< Bit mask for MSC_BANKSWITCHED */ #define _MSC_STATUS_BANKSWITCHED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ #define MSC_STATUS_BANKSWITCHED_DEFAULT (_MSC_STATUS_BANKSWITCHED_DEFAULT << 7) /**< Shifted mode DEFAULT for MSC_STATUS */ #define _MSC_STATUS_WDATAVALID_SHIFT 24 /**< Shift value for MSC_WDATAVALID */ #define _MSC_STATUS_WDATAVALID_MASK 0xF000000UL /**< Bit mask for MSC_WDATAVALID */ #define _MSC_STATUS_WDATAVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ #define MSC_STATUS_WDATAVALID_DEFAULT (_MSC_STATUS_WDATAVALID_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_STATUS */ #define _MSC_STATUS_PWRUPCKBDFAILCOUNT_SHIFT 28 /**< Shift value for MSC_PWRUPCKBDFAILCOUNT */ #define _MSC_STATUS_PWRUPCKBDFAILCOUNT_MASK 0xF0000000UL /**< Bit mask for MSC_PWRUPCKBDFAILCOUNT */ #define _MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ #define MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT (_MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_STATUS */ /* Bit fields for MSC IF */ #define _MSC_IF_RESETVALUE 0x00000000UL /**< Default value for MSC_IF */ #define _MSC_IF_MASK 0x0000017FUL /**< Mask for MSC_IF */ #define MSC_IF_ERASE (0x1UL << 0) /**< Erase Done Interrupt Read Flag */ #define _MSC_IF_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ #define _MSC_IF_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ #define _MSC_IF_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ #define MSC_IF_ERASE_DEFAULT (_MSC_IF_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IF */ #define MSC_IF_WRITE (0x1UL << 1) /**< Write Done Interrupt Read Flag */ #define _MSC_IF_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ #define _MSC_IF_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ #define _MSC_IF_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ #define MSC_IF_WRITE_DEFAULT (_MSC_IF_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IF */ #define MSC_IF_CHOF (0x1UL << 2) /**< Cache Hits Overflow Interrupt Flag */ #define _MSC_IF_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ #define _MSC_IF_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ #define _MSC_IF_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ #define MSC_IF_CHOF_DEFAULT (_MSC_IF_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IF */ #define MSC_IF_CMOF (0x1UL << 3) /**< Cache Misses Overflow Interrupt Flag */ #define _MSC_IF_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ #define _MSC_IF_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ #define _MSC_IF_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ #define MSC_IF_CMOF_DEFAULT (_MSC_IF_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IF */ #define MSC_IF_PWRUPF (0x1UL << 4) /**< Flash Power Up Sequence Complete Flag */ #define _MSC_IF_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ #define _MSC_IF_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ #define _MSC_IF_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ #define MSC_IF_PWRUPF_DEFAULT (_MSC_IF_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IF */ #define MSC_IF_ICACHERR (0x1UL << 5) /**< ICache RAM Parity Error Flag */ #define _MSC_IF_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ #define _MSC_IF_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ #define _MSC_IF_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ #define MSC_IF_ICACHERR_DEFAULT (_MSC_IF_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IF */ #define MSC_IF_WDATAOV (0x1UL << 6) /**< Flash Controller Write Buffer Overflow */ #define _MSC_IF_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ #define _MSC_IF_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ #define _MSC_IF_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ #define MSC_IF_WDATAOV_DEFAULT (_MSC_IF_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IF */ #define MSC_IF_LVEWRITE (0x1UL << 8) /**< Flash LVE Write Error Flag */ #define _MSC_IF_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ #define _MSC_IF_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ #define _MSC_IF_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ #define MSC_IF_LVEWRITE_DEFAULT (_MSC_IF_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IF */ /* Bit fields for MSC IFS */ #define _MSC_IFS_RESETVALUE 0x00000000UL /**< Default value for MSC_IFS */ #define _MSC_IFS_MASK 0x0000017FUL /**< Mask for MSC_IFS */ #define MSC_IFS_ERASE (0x1UL << 0) /**< Set ERASE Interrupt Flag */ #define _MSC_IFS_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ #define _MSC_IFS_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ #define _MSC_IFS_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ #define MSC_IFS_ERASE_DEFAULT (_MSC_IFS_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IFS */ #define MSC_IFS_WRITE (0x1UL << 1) /**< Set WRITE Interrupt Flag */ #define _MSC_IFS_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ #define _MSC_IFS_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ #define _MSC_IFS_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ #define MSC_IFS_WRITE_DEFAULT (_MSC_IFS_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IFS */ #define MSC_IFS_CHOF (0x1UL << 2) /**< Set CHOF Interrupt Flag */ #define _MSC_IFS_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ #define _MSC_IFS_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ #define _MSC_IFS_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ #define MSC_IFS_CHOF_DEFAULT (_MSC_IFS_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IFS */ #define MSC_IFS_CMOF (0x1UL << 3) /**< Set CMOF Interrupt Flag */ #define _MSC_IFS_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ #define _MSC_IFS_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ #define _MSC_IFS_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ #define MSC_IFS_CMOF_DEFAULT (_MSC_IFS_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IFS */ #define MSC_IFS_PWRUPF (0x1UL << 4) /**< Set PWRUPF Interrupt Flag */ #define _MSC_IFS_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ #define _MSC_IFS_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ #define _MSC_IFS_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ #define MSC_IFS_PWRUPF_DEFAULT (_MSC_IFS_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IFS */ #define MSC_IFS_ICACHERR (0x1UL << 5) /**< Set ICACHERR Interrupt Flag */ #define _MSC_IFS_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ #define _MSC_IFS_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ #define _MSC_IFS_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ #define MSC_IFS_ICACHERR_DEFAULT (_MSC_IFS_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IFS */ #define MSC_IFS_WDATAOV (0x1UL << 6) /**< Set WDATAOV Interrupt Flag */ #define _MSC_IFS_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ #define _MSC_IFS_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ #define _MSC_IFS_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ #define MSC_IFS_WDATAOV_DEFAULT (_MSC_IFS_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IFS */ #define MSC_IFS_LVEWRITE (0x1UL << 8) /**< Set LVEWRITE Interrupt Flag */ #define _MSC_IFS_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ #define _MSC_IFS_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ #define _MSC_IFS_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ #define MSC_IFS_LVEWRITE_DEFAULT (_MSC_IFS_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IFS */ /* Bit fields for MSC IFC */ #define _MSC_IFC_RESETVALUE 0x00000000UL /**< Default value for MSC_IFC */ #define _MSC_IFC_MASK 0x0000017FUL /**< Mask for MSC_IFC */ #define MSC_IFC_ERASE (0x1UL << 0) /**< Clear ERASE Interrupt Flag */ #define _MSC_IFC_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ #define _MSC_IFC_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ #define _MSC_IFC_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ #define MSC_IFC_ERASE_DEFAULT (_MSC_IFC_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IFC */ #define MSC_IFC_WRITE (0x1UL << 1) /**< Clear WRITE Interrupt Flag */ #define _MSC_IFC_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ #define _MSC_IFC_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ #define _MSC_IFC_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ #define MSC_IFC_WRITE_DEFAULT (_MSC_IFC_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IFC */ #define MSC_IFC_CHOF (0x1UL << 2) /**< Clear CHOF Interrupt Flag */ #define _MSC_IFC_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ #define _MSC_IFC_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ #define _MSC_IFC_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ #define MSC_IFC_CHOF_DEFAULT (_MSC_IFC_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IFC */ #define MSC_IFC_CMOF (0x1UL << 3) /**< Clear CMOF Interrupt Flag */ #define _MSC_IFC_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ #define _MSC_IFC_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ #define _MSC_IFC_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ #define MSC_IFC_CMOF_DEFAULT (_MSC_IFC_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IFC */ #define MSC_IFC_PWRUPF (0x1UL << 4) /**< Clear PWRUPF Interrupt Flag */ #define _MSC_IFC_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ #define _MSC_IFC_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ #define _MSC_IFC_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ #define MSC_IFC_PWRUPF_DEFAULT (_MSC_IFC_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IFC */ #define MSC_IFC_ICACHERR (0x1UL << 5) /**< Clear ICACHERR Interrupt Flag */ #define _MSC_IFC_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ #define _MSC_IFC_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ #define _MSC_IFC_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ #define MSC_IFC_ICACHERR_DEFAULT (_MSC_IFC_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IFC */ #define MSC_IFC_WDATAOV (0x1UL << 6) /**< Clear WDATAOV Interrupt Flag */ #define _MSC_IFC_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ #define _MSC_IFC_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ #define _MSC_IFC_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ #define MSC_IFC_WDATAOV_DEFAULT (_MSC_IFC_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IFC */ #define MSC_IFC_LVEWRITE (0x1UL << 8) /**< Clear LVEWRITE Interrupt Flag */ #define _MSC_IFC_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ #define _MSC_IFC_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ #define _MSC_IFC_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ #define MSC_IFC_LVEWRITE_DEFAULT (_MSC_IFC_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IFC */ /* Bit fields for MSC IEN */ #define _MSC_IEN_RESETVALUE 0x00000000UL /**< Default value for MSC_IEN */ #define _MSC_IEN_MASK 0x0000017FUL /**< Mask for MSC_IEN */ #define MSC_IEN_ERASE (0x1UL << 0) /**< ERASE Interrupt Enable */ #define _MSC_IEN_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ #define _MSC_IEN_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ #define _MSC_IEN_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ #define MSC_IEN_ERASE_DEFAULT (_MSC_IEN_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IEN */ #define MSC_IEN_WRITE (0x1UL << 1) /**< WRITE Interrupt Enable */ #define _MSC_IEN_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ #define _MSC_IEN_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ #define _MSC_IEN_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ #define MSC_IEN_WRITE_DEFAULT (_MSC_IEN_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IEN */ #define MSC_IEN_CHOF (0x1UL << 2) /**< CHOF Interrupt Enable */ #define _MSC_IEN_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ #define _MSC_IEN_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ #define _MSC_IEN_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ #define MSC_IEN_CHOF_DEFAULT (_MSC_IEN_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IEN */ #define MSC_IEN_CMOF (0x1UL << 3) /**< CMOF Interrupt Enable */ #define _MSC_IEN_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ #define _MSC_IEN_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ #define _MSC_IEN_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ #define MSC_IEN_CMOF_DEFAULT (_MSC_IEN_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IEN */ #define MSC_IEN_PWRUPF (0x1UL << 4) /**< PWRUPF Interrupt Enable */ #define _MSC_IEN_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ #define _MSC_IEN_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ #define _MSC_IEN_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ #define MSC_IEN_PWRUPF_DEFAULT (_MSC_IEN_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IEN */ #define MSC_IEN_ICACHERR (0x1UL << 5) /**< ICACHERR Interrupt Enable */ #define _MSC_IEN_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ #define _MSC_IEN_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ #define _MSC_IEN_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ #define MSC_IEN_ICACHERR_DEFAULT (_MSC_IEN_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IEN */ #define MSC_IEN_WDATAOV (0x1UL << 6) /**< WDATAOV Interrupt Enable */ #define _MSC_IEN_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ #define _MSC_IEN_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ #define _MSC_IEN_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ #define MSC_IEN_WDATAOV_DEFAULT (_MSC_IEN_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IEN */ #define MSC_IEN_LVEWRITE (0x1UL << 8) /**< LVEWRITE Interrupt Enable */ #define _MSC_IEN_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ #define _MSC_IEN_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ #define _MSC_IEN_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ #define MSC_IEN_LVEWRITE_DEFAULT (_MSC_IEN_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IEN */ /* Bit fields for MSC LOCK */ #define _MSC_LOCK_RESETVALUE 0x00000000UL /**< Default value for MSC_LOCK */ #define _MSC_LOCK_MASK 0x0000FFFFUL /**< Mask for MSC_LOCK */ #define _MSC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */ #define _MSC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */ #define _MSC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_LOCK */ #define _MSC_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_LOCK */ #define _MSC_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_LOCK */ #define _MSC_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_LOCK */ #define _MSC_LOCK_LOCKKEY_UNLOCK 0x00001B71UL /**< Mode UNLOCK for MSC_LOCK */ #define MSC_LOCK_LOCKKEY_DEFAULT (_MSC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_LOCK */ #define MSC_LOCK_LOCKKEY_LOCK (_MSC_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_LOCK */ #define MSC_LOCK_LOCKKEY_UNLOCKED (_MSC_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_LOCK */ #define MSC_LOCK_LOCKKEY_LOCKED (_MSC_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_LOCK */ #define MSC_LOCK_LOCKKEY_UNLOCK (_MSC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_LOCK */ /* Bit fields for MSC CACHECMD */ #define _MSC_CACHECMD_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHECMD */ #define _MSC_CACHECMD_MASK 0x00000007UL /**< Mask for MSC_CACHECMD */ #define MSC_CACHECMD_INVCACHE (0x1UL << 0) /**< Invalidate Instruction Cache */ #define _MSC_CACHECMD_INVCACHE_SHIFT 0 /**< Shift value for MSC_INVCACHE */ #define _MSC_CACHECMD_INVCACHE_MASK 0x1UL /**< Bit mask for MSC_INVCACHE */ #define _MSC_CACHECMD_INVCACHE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */ #define MSC_CACHECMD_INVCACHE_DEFAULT (_MSC_CACHECMD_INVCACHE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHECMD */ #define MSC_CACHECMD_STARTPC (0x1UL << 1) /**< Start Performance Counters */ #define _MSC_CACHECMD_STARTPC_SHIFT 1 /**< Shift value for MSC_STARTPC */ #define _MSC_CACHECMD_STARTPC_MASK 0x2UL /**< Bit mask for MSC_STARTPC */ #define _MSC_CACHECMD_STARTPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */ #define MSC_CACHECMD_STARTPC_DEFAULT (_MSC_CACHECMD_STARTPC_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CACHECMD */ #define MSC_CACHECMD_STOPPC (0x1UL << 2) /**< Stop Performance Counters */ #define _MSC_CACHECMD_STOPPC_SHIFT 2 /**< Shift value for MSC_STOPPC */ #define _MSC_CACHECMD_STOPPC_MASK 0x4UL /**< Bit mask for MSC_STOPPC */ #define _MSC_CACHECMD_STOPPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */ #define MSC_CACHECMD_STOPPC_DEFAULT (_MSC_CACHECMD_STOPPC_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_CACHECMD */ /* Bit fields for MSC CACHEHITS */ #define _MSC_CACHEHITS_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHEHITS */ #define _MSC_CACHEHITS_MASK 0x000FFFFFUL /**< Mask for MSC_CACHEHITS */ #define _MSC_CACHEHITS_CACHEHITS_SHIFT 0 /**< Shift value for MSC_CACHEHITS */ #define _MSC_CACHEHITS_CACHEHITS_MASK 0xFFFFFUL /**< Bit mask for MSC_CACHEHITS */ #define _MSC_CACHEHITS_CACHEHITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHEHITS */ #define MSC_CACHEHITS_CACHEHITS_DEFAULT (_MSC_CACHEHITS_CACHEHITS_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHEHITS */ /* Bit fields for MSC CACHEMISSES */ #define _MSC_CACHEMISSES_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHEMISSES */ #define _MSC_CACHEMISSES_MASK 0x000FFFFFUL /**< Mask for MSC_CACHEMISSES */ #define _MSC_CACHEMISSES_CACHEMISSES_SHIFT 0 /**< Shift value for MSC_CACHEMISSES */ #define _MSC_CACHEMISSES_CACHEMISSES_MASK 0xFFFFFUL /**< Bit mask for MSC_CACHEMISSES */ #define _MSC_CACHEMISSES_CACHEMISSES_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHEMISSES */ #define MSC_CACHEMISSES_CACHEMISSES_DEFAULT (_MSC_CACHEMISSES_CACHEMISSES_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHEMISSES */ /* Bit fields for MSC MASSLOCK */ #define _MSC_MASSLOCK_RESETVALUE 0x00000001UL /**< Default value for MSC_MASSLOCK */ #define _MSC_MASSLOCK_MASK 0x0000FFFFUL /**< Mask for MSC_MASSLOCK */ #define _MSC_MASSLOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */ #define _MSC_MASSLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */ #define _MSC_MASSLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_MASSLOCK */ #define _MSC_MASSLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_MASSLOCK */ #define _MSC_MASSLOCK_LOCKKEY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_MASSLOCK */ #define _MSC_MASSLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_MASSLOCK */ #define _MSC_MASSLOCK_LOCKKEY_UNLOCK 0x0000631AUL /**< Mode UNLOCK for MSC_MASSLOCK */ #define MSC_MASSLOCK_LOCKKEY_LOCK (_MSC_MASSLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_MASSLOCK */ #define MSC_MASSLOCK_LOCKKEY_UNLOCKED (_MSC_MASSLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_MASSLOCK */ #define MSC_MASSLOCK_LOCKKEY_DEFAULT (_MSC_MASSLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_MASSLOCK */ #define MSC_MASSLOCK_LOCKKEY_LOCKED (_MSC_MASSLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_MASSLOCK */ #define MSC_MASSLOCK_LOCKKEY_UNLOCK (_MSC_MASSLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_MASSLOCK */ /* Bit fields for MSC STARTUP */ #define _MSC_STARTUP_RESETVALUE 0x1300104DUL /**< Default value for MSC_STARTUP */ #define _MSC_STARTUP_MASK 0x773FF3FFUL /**< Mask for MSC_STARTUP */ #define _MSC_STARTUP_STDLY0_SHIFT 0 /**< Shift value for MSC_STDLY0 */ #define _MSC_STARTUP_STDLY0_MASK 0x3FFUL /**< Bit mask for MSC_STDLY0 */ #define _MSC_STARTUP_STDLY0_DEFAULT 0x0000004DUL /**< Mode DEFAULT for MSC_STARTUP */ #define MSC_STARTUP_STDLY0_DEFAULT (_MSC_STARTUP_STDLY0_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_STARTUP */ #define _MSC_STARTUP_STDLY1_SHIFT 12 /**< Shift value for MSC_STDLY1 */ #define _MSC_STARTUP_STDLY1_MASK 0x3FF000UL /**< Bit mask for MSC_STDLY1 */ #define _MSC_STARTUP_STDLY1_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ #define MSC_STARTUP_STDLY1_DEFAULT (_MSC_STARTUP_STDLY1_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_STARTUP */ #define MSC_STARTUP_ASTWAIT (0x1UL << 24) /**< Active Startup Wait */ #define _MSC_STARTUP_ASTWAIT_SHIFT 24 /**< Shift value for MSC_ASTWAIT */ #define _MSC_STARTUP_ASTWAIT_MASK 0x1000000UL /**< Bit mask for MSC_ASTWAIT */ #define _MSC_STARTUP_ASTWAIT_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ #define MSC_STARTUP_ASTWAIT_DEFAULT (_MSC_STARTUP_ASTWAIT_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_STARTUP */ #define MSC_STARTUP_STWSEN (0x1UL << 25) /**< Startup Waitstates Enable */ #define _MSC_STARTUP_STWSEN_SHIFT 25 /**< Shift value for MSC_STWSEN */ #define _MSC_STARTUP_STWSEN_MASK 0x2000000UL /**< Bit mask for MSC_STWSEN */ #define _MSC_STARTUP_STWSEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ #define MSC_STARTUP_STWSEN_DEFAULT (_MSC_STARTUP_STWSEN_DEFAULT << 25) /**< Shifted mode DEFAULT for MSC_STARTUP */ #define MSC_STARTUP_STWSAEN (0x1UL << 26) /**< Startup Waitstates Always Enable */ #define _MSC_STARTUP_STWSAEN_SHIFT 26 /**< Shift value for MSC_STWSAEN */ #define _MSC_STARTUP_STWSAEN_MASK 0x4000000UL /**< Bit mask for MSC_STWSAEN */ #define _MSC_STARTUP_STWSAEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STARTUP */ #define MSC_STARTUP_STWSAEN_DEFAULT (_MSC_STARTUP_STWSAEN_DEFAULT << 26) /**< Shifted mode DEFAULT for MSC_STARTUP */ #define _MSC_STARTUP_STWS_SHIFT 28 /**< Shift value for MSC_STWS */ #define _MSC_STARTUP_STWS_MASK 0x70000000UL /**< Bit mask for MSC_STWS */ #define _MSC_STARTUP_STWS_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ #define MSC_STARTUP_STWS_DEFAULT (_MSC_STARTUP_STWS_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_STARTUP */ /* Bit fields for MSC BANKSWITCHLOCK */ #define _MSC_BANKSWITCHLOCK_RESETVALUE 0x00000001UL /**< Default value for MSC_BANKSWITCHLOCK */ #define _MSC_BANKSWITCHLOCK_MASK 0x0000FFFFUL /**< Mask for MSC_BANKSWITCHLOCK */ #define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_SHIFT 0 /**< Shift value for MSC_BANKSWITCHLOCKKEY */ #define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_BANKSWITCHLOCKKEY */ #define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_BANKSWITCHLOCK */ #define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_BANKSWITCHLOCK */ #define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_BANKSWITCHLOCK */ #define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_BANKSWITCHLOCK */ #define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK 0x00007C2BUL /**< Mode UNLOCK for MSC_BANKSWITCHLOCK */ #define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_BANKSWITCHLOCK */ #define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_BANKSWITCHLOCK */ #define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_BANKSWITCHLOCK */ #define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_BANKSWITCHLOCK */ #define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_BANKSWITCHLOCK */ /* Bit fields for MSC CMD */ #define _MSC_CMD_RESETVALUE 0x00000000UL /**< Default value for MSC_CMD */ #define _MSC_CMD_MASK 0x00000003UL /**< Mask for MSC_CMD */ #define MSC_CMD_PWRUP (0x1UL << 0) /**< Flash Power Up Command */ #define _MSC_CMD_PWRUP_SHIFT 0 /**< Shift value for MSC_PWRUP */ #define _MSC_CMD_PWRUP_MASK 0x1UL /**< Bit mask for MSC_PWRUP */ #define _MSC_CMD_PWRUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */ #define MSC_CMD_PWRUP_DEFAULT (_MSC_CMD_PWRUP_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CMD */ #define MSC_CMD_SWITCHINGBANK (0x1UL << 1) /**< BANK SWITCHING COMMAND */ #define _MSC_CMD_SWITCHINGBANK_SHIFT 1 /**< Shift value for MSC_SWITCHINGBANK */ #define _MSC_CMD_SWITCHINGBANK_MASK 0x2UL /**< Bit mask for MSC_SWITCHINGBANK */ #define _MSC_CMD_SWITCHINGBANK_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */ #define MSC_CMD_SWITCHINGBANK_DEFAULT (_MSC_CMD_SWITCHINGBANK_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CMD */ /* Bit fields for MSC BOOTLOADERCTRL */ #define _MSC_BOOTLOADERCTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_BOOTLOADERCTRL */ #define _MSC_BOOTLOADERCTRL_MASK 0x00000003UL /**< Mask for MSC_BOOTLOADERCTRL */ #define MSC_BOOTLOADERCTRL_BLRDIS (0x1UL << 0) /**< Flash Bootloader Read Disable */ #define _MSC_BOOTLOADERCTRL_BLRDIS_SHIFT 0 /**< Shift value for MSC_BLRDIS */ #define _MSC_BOOTLOADERCTRL_BLRDIS_MASK 0x1UL /**< Bit mask for MSC_BLRDIS */ #define _MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_BOOTLOADERCTRL */ #define MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT (_MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_BOOTLOADERCTRL */ #define MSC_BOOTLOADERCTRL_BLWDIS (0x1UL << 1) /**< Flash Bootloader Write/Erase Disable */ #define _MSC_BOOTLOADERCTRL_BLWDIS_SHIFT 1 /**< Shift value for MSC_BLWDIS */ #define _MSC_BOOTLOADERCTRL_BLWDIS_MASK 0x2UL /**< Bit mask for MSC_BLWDIS */ #define _MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_BOOTLOADERCTRL */ #define MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT (_MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_BOOTLOADERCTRL */ /* Bit fields for MSC AAPUNLOCKCMD */ #define _MSC_AAPUNLOCKCMD_RESETVALUE 0x00000000UL /**< Default value for MSC_AAPUNLOCKCMD */ #define _MSC_AAPUNLOCKCMD_MASK 0x00000001UL /**< Mask for MSC_AAPUNLOCKCMD */ #define MSC_AAPUNLOCKCMD_UNLOCKAAP (0x1UL << 0) /**< Software Unlock AAP Command */ #define _MSC_AAPUNLOCKCMD_UNLOCKAAP_SHIFT 0 /**< Shift value for MSC_UNLOCKAAP */ #define _MSC_AAPUNLOCKCMD_UNLOCKAAP_MASK 0x1UL /**< Bit mask for MSC_UNLOCKAAP */ #define _MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_AAPUNLOCKCMD */ #define MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT (_MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_AAPUNLOCKCMD */ /* Bit fields for MSC CACHECONFIG0 */ #define _MSC_CACHECONFIG0_RESETVALUE 0x00000003UL /**< Default value for MSC_CACHECONFIG0 */ #define _MSC_CACHECONFIG0_MASK 0x00000003UL /**< Mask for MSC_CACHECONFIG0 */ #define _MSC_CACHECONFIG0_CACHELPLEVEL_SHIFT 0 /**< Shift value for MSC_CACHELPLEVEL */ #define _MSC_CACHECONFIG0_CACHELPLEVEL_MASK 0x3UL /**< Bit mask for MSC_CACHELPLEVEL */ #define _MSC_CACHECONFIG0_CACHELPLEVEL_BASE 0x00000000UL /**< Mode BASE for MSC_CACHECONFIG0 */ #define _MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED 0x00000001UL /**< Mode ADVANCED for MSC_CACHECONFIG0 */ #define _MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for MSC_CACHECONFIG0 */ #define _MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY 0x00000003UL /**< Mode MINACTIVITY for MSC_CACHECONFIG0 */ #define MSC_CACHECONFIG0_CACHELPLEVEL_BASE (_MSC_CACHECONFIG0_CACHELPLEVEL_BASE << 0) /**< Shifted mode BASE for MSC_CACHECONFIG0 */ #define MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED (_MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED << 0) /**< Shifted mode ADVANCED for MSC_CACHECONFIG0 */ #define MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT (_MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHECONFIG0 */ #define MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY (_MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY << 0) /**< Shifted mode MINACTIVITY for MSC_CACHECONFIG0 */ /* Bit fields for MSC RAMCTRL */ #define _MSC_RAMCTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_RAMCTRL */ #define _MSC_RAMCTRL_MASK 0x00000101UL /**< Mask for MSC_RAMCTRL */ #define MSC_RAMCTRL_RAMCACHEEN (0x1UL << 0) /**< RAM CACHE Enable */ #define _MSC_RAMCTRL_RAMCACHEEN_SHIFT 0 /**< Shift value for MSC_RAMCACHEEN */ #define _MSC_RAMCTRL_RAMCACHEEN_MASK 0x1UL /**< Bit mask for MSC_RAMCACHEEN */ #define _MSC_RAMCTRL_RAMCACHEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ #define MSC_RAMCTRL_RAMCACHEEN_DEFAULT (_MSC_RAMCTRL_RAMCACHEEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ #define MSC_RAMCTRL_RAM1CACHEEN (0x1UL << 8) /**< RAM1 CACHE Enable */ #define _MSC_RAMCTRL_RAM1CACHEEN_SHIFT 8 /**< Shift value for MSC_RAM1CACHEEN */ #define _MSC_RAMCTRL_RAM1CACHEEN_MASK 0x100UL /**< Bit mask for MSC_RAM1CACHEEN */ #define _MSC_RAMCTRL_RAM1CACHEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ #define MSC_RAMCTRL_RAM1CACHEEN_DEFAULT (_MSC_RAMCTRL_RAM1CACHEEN_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ /** @} */ /** @} End of group EFR32MG12P_MSC */ /** @} End of group Parts */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_pcnt.h.
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/***************************************************************************//** * @file * @brief EFR32MG12P_PCNT register and bit field definitions * @version 5.7.0 ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * SPDX-License-Identifier: Zlib * * The licensor of this software is Silicon Laboratories Inc. * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be * appreciated but is not required. * 2. Altered source versions must be plainly marked as such, and must not be * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * ******************************************************************************/ #if defined(__ICCARM__) #pragma system_include /* Treat file as system include file. */ #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang system_header /* Treat file as system include file. */ #endif /***************************************************************************//** * @addtogroup Parts * @{ ******************************************************************************/ /***************************************************************************//** * @defgroup EFR32MG12P_PCNT PCNT * @{ * @brief EFR32MG12P_PCNT Register Declaration ******************************************************************************/ /** PCNT Register Declaration */ typedef struct { __IOM uint32_t CTRL; /**< Control Register */ __IOM uint32_t CMD; /**< Command Register */ __IM uint32_t STATUS; /**< Status Register */ __IM uint32_t CNT; /**< Counter Value Register */ __IM uint32_t TOP; /**< Top Value Register */ __IOM uint32_t TOPB; /**< Top Value Buffer Register */ __IM uint32_t IF; /**< Interrupt Flag Register */ __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ __IOM uint32_t IEN; /**< Interrupt Enable Register */ uint32_t RESERVED0[1U]; /**< Reserved for future use **/ __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ uint32_t RESERVED1[4U]; /**< Reserved for future use **/ __IOM uint32_t FREEZE; /**< Freeze Register */ __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ uint32_t RESERVED2[7U]; /**< Reserved for future use **/ __IM uint32_t AUXCNT; /**< Auxiliary Counter Value Register */ __IOM uint32_t INPUT; /**< PCNT Input Register */ __IOM uint32_t OVSCFG; /**< Oversampling Config Register */ } PCNT_TypeDef; /** @} */ /***************************************************************************//** * @addtogroup EFR32MG12P_PCNT * @{ * @defgroup EFR32MG12P_PCNT_BitFields PCNT Bit Fields * @{ ******************************************************************************/ /* Bit fields for PCNT CTRL */ #define _PCNT_CTRL_RESETVALUE 0x00000000UL /**< Default value for PCNT_CTRL */ #define _PCNT_CTRL_MASK 0xBFDBFFFFUL /**< Mask for PCNT_CTRL */ #define _PCNT_CTRL_MODE_SHIFT 0 /**< Shift value for PCNT_MODE */ #define _PCNT_CTRL_MODE_MASK 0x7UL /**< Bit mask for PCNT_MODE */ #define _PCNT_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ #define _PCNT_CTRL_MODE_DISABLE 0x00000000UL /**< Mode DISABLE for PCNT_CTRL */ #define _PCNT_CTRL_MODE_OVSSINGLE 0x00000001UL /**< Mode OVSSINGLE for PCNT_CTRL */ #define _PCNT_CTRL_MODE_EXTCLKSINGLE 0x00000002UL /**< Mode EXTCLKSINGLE for PCNT_CTRL */ #define _PCNT_CTRL_MODE_EXTCLKQUAD 0x00000003UL /**< Mode EXTCLKQUAD for PCNT_CTRL */ #define _PCNT_CTRL_MODE_OVSQUAD1X 0x00000004UL /**< Mode OVSQUAD1X for PCNT_CTRL */ #define _PCNT_CTRL_MODE_OVSQUAD2X 0x00000005UL /**< Mode OVSQUAD2X for PCNT_CTRL */ #define _PCNT_CTRL_MODE_OVSQUAD4X 0x00000006UL /**< Mode OVSQUAD4X for PCNT_CTRL */ #define PCNT_CTRL_MODE_DEFAULT (_PCNT_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_CTRL */ #define PCNT_CTRL_MODE_DISABLE (_PCNT_CTRL_MODE_DISABLE << 0) /**< Shifted mode DISABLE for PCNT_CTRL */ #define PCNT_CTRL_MODE_OVSSINGLE (_PCNT_CTRL_MODE_OVSSINGLE << 0) /**< Shifted mode OVSSINGLE for PCNT_CTRL */ #define PCNT_CTRL_MODE_EXTCLKSINGLE (_PCNT_CTRL_MODE_EXTCLKSINGLE << 0) /**< Shifted mode EXTCLKSINGLE for PCNT_CTRL */ #define PCNT_CTRL_MODE_EXTCLKQUAD (_PCNT_CTRL_MODE_EXTCLKQUAD << 0) /**< Shifted mode EXTCLKQUAD for PCNT_CTRL */ #define PCNT_CTRL_MODE_OVSQUAD1X (_PCNT_CTRL_MODE_OVSQUAD1X << 0) /**< Shifted mode OVSQUAD1X for PCNT_CTRL */ #define PCNT_CTRL_MODE_OVSQUAD2X (_PCNT_CTRL_MODE_OVSQUAD2X << 0) /**< Shifted mode OVSQUAD2X for PCNT_CTRL */ #define PCNT_CTRL_MODE_OVSQUAD4X (_PCNT_CTRL_MODE_OVSQUAD4X << 0) /**< Shifted mode OVSQUAD4X for PCNT_CTRL */ #define PCNT_CTRL_FILT (0x1UL << 3) /**< Enable Digital Pulse Width Filter */ #define _PCNT_CTRL_FILT_SHIFT 3 /**< Shift value for PCNT_FILT */ #define _PCNT_CTRL_FILT_MASK 0x8UL /**< Bit mask for PCNT_FILT */ #define _PCNT_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ #define PCNT_CTRL_FILT_DEFAULT (_PCNT_CTRL_FILT_DEFAULT << 3) /**< Shifted mode DEFAULT for PCNT_CTRL */ #define PCNT_CTRL_RSTEN (0x1UL << 4) /**< Enable PCNT Clock Domain Reset */ #define _PCNT_CTRL_RSTEN_SHIFT 4 /**< Shift value for PCNT_RSTEN */ #define _PCNT_CTRL_RSTEN_MASK 0x10UL /**< Bit mask for PCNT_RSTEN */ #define _PCNT_CTRL_RSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ #define PCNT_CTRL_RSTEN_DEFAULT (_PCNT_CTRL_RSTEN_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_CTRL */ #define PCNT_CTRL_CNTRSTEN (0x1UL << 5) /**< Enable CNT Reset */ #define _PCNT_CTRL_CNTRSTEN_SHIFT 5 /**< Shift value for PCNT_CNTRSTEN */ #define _PCNT_CTRL_CNTRSTEN_MASK 0x20UL /**< Bit mask for PCNT_CNTRSTEN */ #define _PCNT_CTRL_CNTRSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ #define PCNT_CTRL_CNTRSTEN_DEFAULT (_PCNT_CTRL_CNTRSTEN_DEFAULT << 5) /**< Shifted mode DEFAULT for PCNT_CTRL */ #define PCNT_CTRL_AUXCNTRSTEN (0x1UL << 6) /**< Enable AUXCNT Reset */ #define _PCNT_CTRL_AUXCNTRSTEN_SHIFT 6 /**< Shift value for PCNT_AUXCNTRSTEN */ #define _PCNT_CTRL_AUXCNTRSTEN_MASK 0x40UL /**< Bit mask for PCNT_AUXCNTRSTEN */ #define _PCNT_CTRL_AUXCNTRSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ #define PCNT_CTRL_AUXCNTRSTEN_DEFAULT (_PCNT_CTRL_AUXCNTRSTEN_DEFAULT << 6) /**< Shifted mode DEFAULT for PCNT_CTRL */ #define PCNT_CTRL_DEBUGHALT (0x1UL << 7) /**< Debug Mode Halt Enable */ #define _PCNT_CTRL_DEBUGHALT_SHIFT 7 /**< Shift value for PCNT_DEBUGHALT */ #define _PCNT_CTRL_DEBUGHALT_MASK 0x80UL /**< Bit mask for PCNT_DEBUGHALT */ #define _PCNT_CTRL_DEBUGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ #define PCNT_CTRL_DEBUGHALT_DEFAULT (_PCNT_CTRL_DEBUGHALT_DEFAULT << 7) /**< Shifted mode DEFAULT for PCNT_CTRL */ #define PCNT_CTRL_HYST (0x1UL << 8) /**< Enable Hysteresis */ #define _PCNT_CTRL_HYST_SHIFT 8 /**< Shift value for PCNT_HYST */ #define _PCNT_CTRL_HYST_MASK 0x100UL /**< Bit mask for PCNT_HYST */ #define _PCNT_CTRL_HYST_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ #define PCNT_CTRL_HYST_DEFAULT (_PCNT_CTRL_HYST_DEFAULT << 8) /**< Shifted mode DEFAULT for PCNT_CTRL */ #define PCNT_CTRL_S1CDIR (0x1UL << 9) /**< Count Direction Determined By S1 */ #define _PCNT_CTRL_S1CDIR_SHIFT 9 /**< Shift value for PCNT_S1CDIR */ #define _PCNT_CTRL_S1CDIR_MASK 0x200UL /**< Bit mask for PCNT_S1CDIR */ #define _PCNT_CTRL_S1CDIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ #define PCNT_CTRL_S1CDIR_DEFAULT (_PCNT_CTRL_S1CDIR_DEFAULT << 9) /**< Shifted mode DEFAULT for PCNT_CTRL */ #define _PCNT_CTRL_CNTEV_SHIFT 10 /**< Shift value for PCNT_CNTEV */ #define _PCNT_CTRL_CNTEV_MASK 0xC00UL /**< Bit mask for PCNT_CNTEV */ #define _PCNT_CTRL_CNTEV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ #define _PCNT_CTRL_CNTEV_BOTH 0x00000000UL /**< Mode BOTH for PCNT_CTRL */ #define _PCNT_CTRL_CNTEV_UP 0x00000001UL /**< Mode UP for PCNT_CTRL */ #define _PCNT_CTRL_CNTEV_DOWN 0x00000002UL /**< Mode DOWN for PCNT_CTRL */ #define _PCNT_CTRL_CNTEV_NONE 0x00000003UL /**< Mode NONE for PCNT_CTRL */ #define PCNT_CTRL_CNTEV_DEFAULT (_PCNT_CTRL_CNTEV_DEFAULT << 10) /**< Shifted mode DEFAULT for PCNT_CTRL */ #define PCNT_CTRL_CNTEV_BOTH (_PCNT_CTRL_CNTEV_BOTH << 10) /**< Shifted mode BOTH for PCNT_CTRL */ #define PCNT_CTRL_CNTEV_UP (_PCNT_CTRL_CNTEV_UP << 10) /**< Shifted mode UP for PCNT_CTRL */ #define PCNT_CTRL_CNTEV_DOWN (_PCNT_CTRL_CNTEV_DOWN << 10) /**< Shifted mode DOWN for PCNT_CTRL */ #define PCNT_CTRL_CNTEV_NONE (_PCNT_CTRL_CNTEV_NONE << 10) /**< Shifted mode NONE for PCNT_CTRL */ #define _PCNT_CTRL_AUXCNTEV_SHIFT 12 /**< Shift value for PCNT_AUXCNTEV */ #define _PCNT_CTRL_AUXCNTEV_MASK 0x3000UL /**< Bit mask for PCNT_AUXCNTEV */ #define _PCNT_CTRL_AUXCNTEV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ #define _PCNT_CTRL_AUXCNTEV_NONE 0x00000000UL /**< Mode NONE for PCNT_CTRL */ #define _PCNT_CTRL_AUXCNTEV_UP 0x00000001UL /**< Mode UP for PCNT_CTRL */ #define _PCNT_CTRL_AUXCNTEV_DOWN 0x00000002UL /**< Mode DOWN for PCNT_CTRL */ #define _PCNT_CTRL_AUXCNTEV_BOTH 0x00000003UL /**< Mode BOTH for PCNT_CTRL */ #define PCNT_CTRL_AUXCNTEV_DEFAULT (_PCNT_CTRL_AUXCNTEV_DEFAULT << 12) /**< Shifted mode DEFAULT for PCNT_CTRL */ #define PCNT_CTRL_AUXCNTEV_NONE (_PCNT_CTRL_AUXCNTEV_NONE << 12) /**< Shifted mode NONE for PCNT_CTRL */ #define PCNT_CTRL_AUXCNTEV_UP (_PCNT_CTRL_AUXCNTEV_UP << 12) /**< Shifted mode UP for PCNT_CTRL */ #define PCNT_CTRL_AUXCNTEV_DOWN (_PCNT_CTRL_AUXCNTEV_DOWN << 12) /**< Shifted mode DOWN for PCNT_CTRL */ #define PCNT_CTRL_AUXCNTEV_BOTH (_PCNT_CTRL_AUXCNTEV_BOTH << 12) /**< Shifted mode BOTH for PCNT_CTRL */ #define PCNT_CTRL_CNTDIR (0x1UL << 14) /**< Non-Quadrature Mode Counter Direction Control */ #define _PCNT_CTRL_CNTDIR_SHIFT 14 /**< Shift value for PCNT_CNTDIR */ #define _PCNT_CTRL_CNTDIR_MASK 0x4000UL /**< Bit mask for PCNT_CNTDIR */ #define _PCNT_CTRL_CNTDIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ #define _PCNT_CTRL_CNTDIR_UP 0x00000000UL /**< Mode UP for PCNT_CTRL */ #define _PCNT_CTRL_CNTDIR_DOWN 0x00000001UL /**< Mode DOWN for PCNT_CTRL */ #define PCNT_CTRL_CNTDIR_DEFAULT (_PCNT_CTRL_CNTDIR_DEFAULT << 14) /**< Shifted mode DEFAULT for PCNT_CTRL */ #define PCNT_CTRL_CNTDIR_UP (_PCNT_CTRL_CNTDIR_UP << 14) /**< Shifted mode UP for PCNT_CTRL */ #define PCNT_CTRL_CNTDIR_DOWN (_PCNT_CTRL_CNTDIR_DOWN << 14) /**< Shifted mode DOWN for PCNT_CTRL */ #define PCNT_CTRL_EDGE (0x1UL << 15) /**< Edge Select */ #define _PCNT_CTRL_EDGE_SHIFT 15 /**< Shift value for PCNT_EDGE */ #define _PCNT_CTRL_EDGE_MASK 0x8000UL /**< Bit mask for PCNT_EDGE */ #define _PCNT_CTRL_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ #define _PCNT_CTRL_EDGE_POS 0x00000000UL /**< Mode POS for PCNT_CTRL */ #define _PCNT_CTRL_EDGE_NEG 0x00000001UL /**< Mode NEG for PCNT_CTRL */ #define PCNT_CTRL_EDGE_DEFAULT (_PCNT_CTRL_EDGE_DEFAULT << 15) /**< Shifted mode DEFAULT for PCNT_CTRL */ #define PCNT_CTRL_EDGE_POS (_PCNT_CTRL_EDGE_POS << 15) /**< Shifted mode POS for PCNT_CTRL */ #define PCNT_CTRL_EDGE_NEG (_PCNT_CTRL_EDGE_NEG << 15) /**< Shifted mode NEG for PCNT_CTRL */ #define _PCNT_CTRL_TCCMODE_SHIFT 16 /**< Shift value for PCNT_TCCMODE */ #define _PCNT_CTRL_TCCMODE_MASK 0x30000UL /**< Bit mask for PCNT_TCCMODE */ #define _PCNT_CTRL_TCCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ #define _PCNT_CTRL_TCCMODE_DISABLED 0x00000000UL /**< Mode DISABLED for PCNT_CTRL */ #define _PCNT_CTRL_TCCMODE_LFA 0x00000001UL /**< Mode LFA for PCNT_CTRL */ #define _PCNT_CTRL_TCCMODE_PRS 0x00000002UL /**< Mode PRS for PCNT_CTRL */ #define PCNT_CTRL_TCCMODE_DEFAULT (_PCNT_CTRL_TCCMODE_DEFAULT << 16) /**< Shifted mode DEFAULT for PCNT_CTRL */ #define PCNT_CTRL_TCCMODE_DISABLED (_PCNT_CTRL_TCCMODE_DISABLED << 16) /**< Shifted mode DISABLED for PCNT_CTRL */ #define PCNT_CTRL_TCCMODE_LFA (_PCNT_CTRL_TCCMODE_LFA << 16) /**< Shifted mode LFA for PCNT_CTRL */ #define PCNT_CTRL_TCCMODE_PRS (_PCNT_CTRL_TCCMODE_PRS << 16) /**< Shifted mode PRS for PCNT_CTRL */ #define _PCNT_CTRL_TCCPRESC_SHIFT 19 /**< Shift value for PCNT_TCCPRESC */ #define _PCNT_CTRL_TCCPRESC_MASK 0x180000UL /**< Bit mask for PCNT_TCCPRESC */ #define _PCNT_CTRL_TCCPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ #define _PCNT_CTRL_TCCPRESC_DIV1 0x00000000UL /**< Mode DIV1 for PCNT_CTRL */ #define _PCNT_CTRL_TCCPRESC_DIV2 0x00000001UL /**< Mode DIV2 for PCNT_CTRL */ #define _PCNT_CTRL_TCCPRESC_DIV4 0x00000002UL /**< Mode DIV4 for PCNT_CTRL */ #define _PCNT_CTRL_TCCPRESC_DIV8 0x00000003UL /**< Mode DIV8 for PCNT_CTRL */ #define PCNT_CTRL_TCCPRESC_DEFAULT (_PCNT_CTRL_TCCPRESC_DEFAULT << 19) /**< Shifted mode DEFAULT for PCNT_CTRL */ #define PCNT_CTRL_TCCPRESC_DIV1 (_PCNT_CTRL_TCCPRESC_DIV1 << 19) /**< Shifted mode DIV1 for PCNT_CTRL */ #define PCNT_CTRL_TCCPRESC_DIV2 (_PCNT_CTRL_TCCPRESC_DIV2 << 19) /**< Shifted mode DIV2 for PCNT_CTRL */ #define PCNT_CTRL_TCCPRESC_DIV4 (_PCNT_CTRL_TCCPRESC_DIV4 << 19) /**< Shifted mode DIV4 for PCNT_CTRL */ #define PCNT_CTRL_TCCPRESC_DIV8 (_PCNT_CTRL_TCCPRESC_DIV8 << 19) /**< Shifted mode DIV8 for PCNT_CTRL */ #define _PCNT_CTRL_TCCCOMP_SHIFT 22 /**< Shift value for PCNT_TCCCOMP */ #define _PCNT_CTRL_TCCCOMP_MASK 0xC00000UL /**< Bit mask for PCNT_TCCCOMP */ #define _PCNT_CTRL_TCCCOMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ #define _PCNT_CTRL_TCCCOMP_LTOE 0x00000000UL /**< Mode LTOE for PCNT_CTRL */ #define _PCNT_CTRL_TCCCOMP_GTOE 0x00000001UL /**< Mode GTOE for PCNT_CTRL */ #define _PCNT_CTRL_TCCCOMP_RANGE 0x00000002UL /**< Mode RANGE for PCNT_CTRL */ #define PCNT_CTRL_TCCCOMP_DEFAULT (_PCNT_CTRL_TCCCOMP_DEFAULT << 22) /**< Shifted mode DEFAULT for PCNT_CTRL */ #define PCNT_CTRL_TCCCOMP_LTOE (_PCNT_CTRL_TCCCOMP_LTOE << 22) /**< Shifted mode LTOE for PCNT_CTRL */ #define PCNT_CTRL_TCCCOMP_GTOE (_PCNT_CTRL_TCCCOMP_GTOE << 22) /**< Shifted mode GTOE for PCNT_CTRL */ #define PCNT_CTRL_TCCCOMP_RANGE (_PCNT_CTRL_TCCCOMP_RANGE << 22) /**< Shifted mode RANGE for PCNT_CTRL */ #define PCNT_CTRL_PRSGATEEN (0x1UL << 24) /**< PRS Gate Enable */ #define _PCNT_CTRL_PRSGATEEN_SHIFT 24 /**< Shift value for PCNT_PRSGATEEN */ #define _PCNT_CTRL_PRSGATEEN_MASK 0x1000000UL /**< Bit mask for PCNT_PRSGATEEN */ #define _PCNT_CTRL_PRSGATEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ #define PCNT_CTRL_PRSGATEEN_DEFAULT (_PCNT_CTRL_PRSGATEEN_DEFAULT << 24) /**< Shifted mode DEFAULT for PCNT_CTRL */ #define PCNT_CTRL_TCCPRSPOL (0x1UL << 25) /**< TCC PRS Polarity Select */ #define _PCNT_CTRL_TCCPRSPOL_SHIFT 25 /**< Shift value for PCNT_TCCPRSPOL */ #define _PCNT_CTRL_TCCPRSPOL_MASK 0x2000000UL /**< Bit mask for PCNT_TCCPRSPOL */ #define _PCNT_CTRL_TCCPRSPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ #define _PCNT_CTRL_TCCPRSPOL_RISING 0x00000000UL /**< Mode RISING for PCNT_CTRL */ #define _PCNT_CTRL_TCCPRSPOL_FALLING 0x00000001UL /**< Mode FALLING for PCNT_CTRL */ #define PCNT_CTRL_TCCPRSPOL_DEFAULT (_PCNT_CTRL_TCCPRSPOL_DEFAULT << 25) /**< Shifted mode DEFAULT for PCNT_CTRL */ #define PCNT_CTRL_TCCPRSPOL_RISING (_PCNT_CTRL_TCCPRSPOL_RISING << 25) /**< Shifted mode RISING for PCNT_CTRL */ #define PCNT_CTRL_TCCPRSPOL_FALLING (_PCNT_CTRL_TCCPRSPOL_FALLING << 25) /**< Shifted mode FALLING for PCNT_CTRL */ #define _PCNT_CTRL_TCCPRSSEL_SHIFT 26 /**< Shift value for PCNT_TCCPRSSEL */ #define _PCNT_CTRL_TCCPRSSEL_MASK 0x3C000000UL /**< Bit mask for PCNT_TCCPRSSEL */ #define _PCNT_CTRL_TCCPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ #define _PCNT_CTRL_TCCPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PCNT_CTRL */ #define _PCNT_CTRL_TCCPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PCNT_CTRL */ #define _PCNT_CTRL_TCCPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PCNT_CTRL */ #define _PCNT_CTRL_TCCPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PCNT_CTRL */ #define _PCNT_CTRL_TCCPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PCNT_CTRL */ #define _PCNT_CTRL_TCCPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PCNT_CTRL */ #define _PCNT_CTRL_TCCPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PCNT_CTRL */ #define _PCNT_CTRL_TCCPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PCNT_CTRL */ #define _PCNT_CTRL_TCCPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PCNT_CTRL */ #define _PCNT_CTRL_TCCPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PCNT_CTRL */ #define _PCNT_CTRL_TCCPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PCNT_CTRL */ #define _PCNT_CTRL_TCCPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PCNT_CTRL */ #define PCNT_CTRL_TCCPRSSEL_DEFAULT (_PCNT_CTRL_TCCPRSSEL_DEFAULT << 26) /**< Shifted mode DEFAULT for PCNT_CTRL */ #define PCNT_CTRL_TCCPRSSEL_PRSCH0 (_PCNT_CTRL_TCCPRSSEL_PRSCH0 << 26) /**< Shifted mode PRSCH0 for PCNT_CTRL */ #define PCNT_CTRL_TCCPRSSEL_PRSCH1 (_PCNT_CTRL_TCCPRSSEL_PRSCH1 << 26) /**< Shifted mode PRSCH1 for PCNT_CTRL */ #define PCNT_CTRL_TCCPRSSEL_PRSCH2 (_PCNT_CTRL_TCCPRSSEL_PRSCH2 << 26) /**< Shifted mode PRSCH2 for PCNT_CTRL */ #define PCNT_CTRL_TCCPRSSEL_PRSCH3 (_PCNT_CTRL_TCCPRSSEL_PRSCH3 << 26) /**< Shifted mode PRSCH3 for PCNT_CTRL */ #define PCNT_CTRL_TCCPRSSEL_PRSCH4 (_PCNT_CTRL_TCCPRSSEL_PRSCH4 << 26) /**< Shifted mode PRSCH4 for PCNT_CTRL */ #define PCNT_CTRL_TCCPRSSEL_PRSCH5 (_PCNT_CTRL_TCCPRSSEL_PRSCH5 << 26) /**< Shifted mode PRSCH5 for PCNT_CTRL */ #define PCNT_CTRL_TCCPRSSEL_PRSCH6 (_PCNT_CTRL_TCCPRSSEL_PRSCH6 << 26) /**< Shifted mode PRSCH6 for PCNT_CTRL */ #define PCNT_CTRL_TCCPRSSEL_PRSCH7 (_PCNT_CTRL_TCCPRSSEL_PRSCH7 << 26) /**< Shifted mode PRSCH7 for PCNT_CTRL */ #define PCNT_CTRL_TCCPRSSEL_PRSCH8 (_PCNT_CTRL_TCCPRSSEL_PRSCH8 << 26) /**< Shifted mode PRSCH8 for PCNT_CTRL */ #define PCNT_CTRL_TCCPRSSEL_PRSCH9 (_PCNT_CTRL_TCCPRSSEL_PRSCH9 << 26) /**< Shifted mode PRSCH9 for PCNT_CTRL */ #define PCNT_CTRL_TCCPRSSEL_PRSCH10 (_PCNT_CTRL_TCCPRSSEL_PRSCH10 << 26) /**< Shifted mode PRSCH10 for PCNT_CTRL */ #define PCNT_CTRL_TCCPRSSEL_PRSCH11 (_PCNT_CTRL_TCCPRSSEL_PRSCH11 << 26) /**< Shifted mode PRSCH11 for PCNT_CTRL */ #define PCNT_CTRL_TOPBHFSEL (0x1UL << 31) /**< TOPB High Frequency Value Select */ #define _PCNT_CTRL_TOPBHFSEL_SHIFT 31 /**< Shift value for PCNT_TOPBHFSEL */ #define _PCNT_CTRL_TOPBHFSEL_MASK 0x80000000UL /**< Bit mask for PCNT_TOPBHFSEL */ #define _PCNT_CTRL_TOPBHFSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ #define PCNT_CTRL_TOPBHFSEL_DEFAULT (_PCNT_CTRL_TOPBHFSEL_DEFAULT << 31) /**< Shifted mode DEFAULT for PCNT_CTRL */ /* Bit fields for PCNT CMD */ #define _PCNT_CMD_RESETVALUE 0x00000000UL /**< Default value for PCNT_CMD */ #define _PCNT_CMD_MASK 0x00000003UL /**< Mask for PCNT_CMD */ #define PCNT_CMD_LCNTIM (0x1UL << 0) /**< Load CNT Immediately */ #define _PCNT_CMD_LCNTIM_SHIFT 0 /**< Shift value for PCNT_LCNTIM */ #define _PCNT_CMD_LCNTIM_MASK 0x1UL /**< Bit mask for PCNT_LCNTIM */ #define _PCNT_CMD_LCNTIM_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CMD */ #define PCNT_CMD_LCNTIM_DEFAULT (_PCNT_CMD_LCNTIM_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_CMD */ #define PCNT_CMD_LTOPBIM (0x1UL << 1) /**< Load TOPB Immediately */ #define _PCNT_CMD_LTOPBIM_SHIFT 1 /**< Shift value for PCNT_LTOPBIM */ #define _PCNT_CMD_LTOPBIM_MASK 0x2UL /**< Bit mask for PCNT_LTOPBIM */ #define _PCNT_CMD_LTOPBIM_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CMD */ #define PCNT_CMD_LTOPBIM_DEFAULT (_PCNT_CMD_LTOPBIM_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_CMD */ /* Bit fields for PCNT STATUS */ #define _PCNT_STATUS_RESETVALUE 0x00000000UL /**< Default value for PCNT_STATUS */ #define _PCNT_STATUS_MASK 0x00000001UL /**< Mask for PCNT_STATUS */ #define PCNT_STATUS_DIR (0x1UL << 0) /**< Current Counter Direction */ #define _PCNT_STATUS_DIR_SHIFT 0 /**< Shift value for PCNT_DIR */ #define _PCNT_STATUS_DIR_MASK 0x1UL /**< Bit mask for PCNT_DIR */ #define _PCNT_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_STATUS */ #define _PCNT_STATUS_DIR_UP 0x00000000UL /**< Mode UP for PCNT_STATUS */ #define _PCNT_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for PCNT_STATUS */ #define PCNT_STATUS_DIR_DEFAULT (_PCNT_STATUS_DIR_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_STATUS */ #define PCNT_STATUS_DIR_UP (_PCNT_STATUS_DIR_UP << 0) /**< Shifted mode UP for PCNT_STATUS */ #define PCNT_STATUS_DIR_DOWN (_PCNT_STATUS_DIR_DOWN << 0) /**< Shifted mode DOWN for PCNT_STATUS */ /* Bit fields for PCNT CNT */ #define _PCNT_CNT_RESETVALUE 0x00000000UL /**< Default value for PCNT_CNT */ #define _PCNT_CNT_MASK 0x0000FFFFUL /**< Mask for PCNT_CNT */ #define _PCNT_CNT_CNT_SHIFT 0 /**< Shift value for PCNT_CNT */ #define _PCNT_CNT_CNT_MASK 0xFFFFUL /**< Bit mask for PCNT_CNT */ #define _PCNT_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CNT */ #define PCNT_CNT_CNT_DEFAULT (_PCNT_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_CNT */ /* Bit fields for PCNT TOP */ #define _PCNT_TOP_RESETVALUE 0x000000FFUL /**< Default value for PCNT_TOP */ #define _PCNT_TOP_MASK 0x0000FFFFUL /**< Mask for PCNT_TOP */ #define _PCNT_TOP_TOP_SHIFT 0 /**< Shift value for PCNT_TOP */ #define _PCNT_TOP_TOP_MASK 0xFFFFUL /**< Bit mask for PCNT_TOP */ #define _PCNT_TOP_TOP_DEFAULT 0x000000FFUL /**< Mode DEFAULT for PCNT_TOP */ #define PCNT_TOP_TOP_DEFAULT (_PCNT_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_TOP */ /* Bit fields for PCNT TOPB */ #define _PCNT_TOPB_RESETVALUE 0x000000FFUL /**< Default value for PCNT_TOPB */ #define _PCNT_TOPB_MASK 0x0000FFFFUL /**< Mask for PCNT_TOPB */ #define _PCNT_TOPB_TOPB_SHIFT 0 /**< Shift value for PCNT_TOPB */ #define _PCNT_TOPB_TOPB_MASK 0xFFFFUL /**< Bit mask for PCNT_TOPB */ #define _PCNT_TOPB_TOPB_DEFAULT 0x000000FFUL /**< Mode DEFAULT for PCNT_TOPB */ #define PCNT_TOPB_TOPB_DEFAULT (_PCNT_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_TOPB */ /* Bit fields for PCNT IF */ #define _PCNT_IF_RESETVALUE 0x00000000UL /**< Default value for PCNT_IF */ #define _PCNT_IF_MASK 0x0000003FUL /**< Mask for PCNT_IF */ #define PCNT_IF_UF (0x1UL << 0) /**< Underflow Interrupt Read Flag */ #define _PCNT_IF_UF_SHIFT 0 /**< Shift value for PCNT_UF */ #define _PCNT_IF_UF_MASK 0x1UL /**< Bit mask for PCNT_UF */ #define _PCNT_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */ #define PCNT_IF_UF_DEFAULT (_PCNT_IF_UF_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_IF */ #define PCNT_IF_OF (0x1UL << 1) /**< Overflow Interrupt Read Flag */ #define _PCNT_IF_OF_SHIFT 1 /**< Shift value for PCNT_OF */ #define _PCNT_IF_OF_MASK 0x2UL /**< Bit mask for PCNT_OF */ #define _PCNT_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */ #define PCNT_IF_OF_DEFAULT (_PCNT_IF_OF_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_IF */ #define PCNT_IF_DIRCNG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ #define _PCNT_IF_DIRCNG_SHIFT 2 /**< Shift value for PCNT_DIRCNG */ #define _PCNT_IF_DIRCNG_MASK 0x4UL /**< Bit mask for PCNT_DIRCNG */ #define _PCNT_IF_DIRCNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */ #define PCNT_IF_DIRCNG_DEFAULT (_PCNT_IF_DIRCNG_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_IF */ #define PCNT_IF_AUXOF (0x1UL << 3) /**< Auxiliary Overflow Interrupt Read Flag */ #define _PCNT_IF_AUXOF_SHIFT 3 /**< Shift value for PCNT_AUXOF */ #define _PCNT_IF_AUXOF_MASK 0x8UL /**< Bit mask for PCNT_AUXOF */ #define _PCNT_IF_AUXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */ #define PCNT_IF_AUXOF_DEFAULT (_PCNT_IF_AUXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for PCNT_IF */ #define PCNT_IF_TCC (0x1UL << 4) /**< Triggered Compare Interrupt Read Flag */ #define _PCNT_IF_TCC_SHIFT 4 /**< Shift value for PCNT_TCC */ #define _PCNT_IF_TCC_MASK 0x10UL /**< Bit mask for PCNT_TCC */ #define _PCNT_IF_TCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */ #define PCNT_IF_TCC_DEFAULT (_PCNT_IF_TCC_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_IF */ #define PCNT_IF_OQSTERR (0x1UL << 5) /**< Oversampling Quadrature State Error Interrupt */ #define _PCNT_IF_OQSTERR_SHIFT 5 /**< Shift value for PCNT_OQSTERR */ #define _PCNT_IF_OQSTERR_MASK 0x20UL /**< Bit mask for PCNT_OQSTERR */ #define _PCNT_IF_OQSTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */ #define PCNT_IF_OQSTERR_DEFAULT (_PCNT_IF_OQSTERR_DEFAULT << 5) /**< Shifted mode DEFAULT for PCNT_IF */ /* Bit fields for PCNT IFS */ #define _PCNT_IFS_RESETVALUE 0x00000000UL /**< Default value for PCNT_IFS */ #define _PCNT_IFS_MASK 0x0000003FUL /**< Mask for PCNT_IFS */ #define PCNT_IFS_UF (0x1UL << 0) /**< Set UF Interrupt Flag */ #define _PCNT_IFS_UF_SHIFT 0 /**< Shift value for PCNT_UF */ #define _PCNT_IFS_UF_MASK 0x1UL /**< Bit mask for PCNT_UF */ #define _PCNT_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFS */ #define PCNT_IFS_UF_DEFAULT (_PCNT_IFS_UF_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_IFS */ #define PCNT_IFS_OF (0x1UL << 1) /**< Set OF Interrupt Flag */ #define _PCNT_IFS_OF_SHIFT 1 /**< Shift value for PCNT_OF */ #define _PCNT_IFS_OF_MASK 0x2UL /**< Bit mask for PCNT_OF */ #define _PCNT_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFS */ #define PCNT_IFS_OF_DEFAULT (_PCNT_IFS_OF_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_IFS */ #define PCNT_IFS_DIRCNG (0x1UL << 2) /**< Set DIRCNG Interrupt Flag */ #define _PCNT_IFS_DIRCNG_SHIFT 2 /**< Shift value for PCNT_DIRCNG */ #define _PCNT_IFS_DIRCNG_MASK 0x4UL /**< Bit mask for PCNT_DIRCNG */ #define _PCNT_IFS_DIRCNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFS */ #define PCNT_IFS_DIRCNG_DEFAULT (_PCNT_IFS_DIRCNG_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_IFS */ #define PCNT_IFS_AUXOF (0x1UL << 3) /**< Set AUXOF Interrupt Flag */ #define _PCNT_IFS_AUXOF_SHIFT 3 /**< Shift value for PCNT_AUXOF */ #define _PCNT_IFS_AUXOF_MASK 0x8UL /**< Bit mask for PCNT_AUXOF */ #define _PCNT_IFS_AUXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFS */ #define PCNT_IFS_AUXOF_DEFAULT (_PCNT_IFS_AUXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for PCNT_IFS */ #define PCNT_IFS_TCC (0x1UL << 4) /**< Set TCC Interrupt Flag */ #define _PCNT_IFS_TCC_SHIFT 4 /**< Shift value for PCNT_TCC */ #define _PCNT_IFS_TCC_MASK 0x10UL /**< Bit mask for PCNT_TCC */ #define _PCNT_IFS_TCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFS */ #define PCNT_IFS_TCC_DEFAULT (_PCNT_IFS_TCC_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_IFS */ #define PCNT_IFS_OQSTERR (0x1UL << 5) /**< Set OQSTERR Interrupt Flag */ #define _PCNT_IFS_OQSTERR_SHIFT 5 /**< Shift value for PCNT_OQSTERR */ #define _PCNT_IFS_OQSTERR_MASK 0x20UL /**< Bit mask for PCNT_OQSTERR */ #define _PCNT_IFS_OQSTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFS */ #define PCNT_IFS_OQSTERR_DEFAULT (_PCNT_IFS_OQSTERR_DEFAULT << 5) /**< Shifted mode DEFAULT for PCNT_IFS */ /* Bit fields for PCNT IFC */ #define _PCNT_IFC_RESETVALUE 0x00000000UL /**< Default value for PCNT_IFC */ #define _PCNT_IFC_MASK 0x0000003FUL /**< Mask for PCNT_IFC */ #define PCNT_IFC_UF (0x1UL << 0) /**< Clear UF Interrupt Flag */ #define _PCNT_IFC_UF_SHIFT 0 /**< Shift value for PCNT_UF */ #define _PCNT_IFC_UF_MASK 0x1UL /**< Bit mask for PCNT_UF */ #define _PCNT_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFC */ #define PCNT_IFC_UF_DEFAULT (_PCNT_IFC_UF_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_IFC */ #define PCNT_IFC_OF (0x1UL << 1) /**< Clear OF Interrupt Flag */ #define _PCNT_IFC_OF_SHIFT 1 /**< Shift value for PCNT_OF */ #define _PCNT_IFC_OF_MASK 0x2UL /**< Bit mask for PCNT_OF */ #define _PCNT_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFC */ #define PCNT_IFC_OF_DEFAULT (_PCNT_IFC_OF_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_IFC */ #define PCNT_IFC_DIRCNG (0x1UL << 2) /**< Clear DIRCNG Interrupt Flag */ #define _PCNT_IFC_DIRCNG_SHIFT 2 /**< Shift value for PCNT_DIRCNG */ #define _PCNT_IFC_DIRCNG_MASK 0x4UL /**< Bit mask for PCNT_DIRCNG */ #define _PCNT_IFC_DIRCNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFC */ #define PCNT_IFC_DIRCNG_DEFAULT (_PCNT_IFC_DIRCNG_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_IFC */ #define PCNT_IFC_AUXOF (0x1UL << 3) /**< Clear AUXOF Interrupt Flag */ #define _PCNT_IFC_AUXOF_SHIFT 3 /**< Shift value for PCNT_AUXOF */ #define _PCNT_IFC_AUXOF_MASK 0x8UL /**< Bit mask for PCNT_AUXOF */ #define _PCNT_IFC_AUXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFC */ #define PCNT_IFC_AUXOF_DEFAULT (_PCNT_IFC_AUXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for PCNT_IFC */ #define PCNT_IFC_TCC (0x1UL << 4) /**< Clear TCC Interrupt Flag */ #define _PCNT_IFC_TCC_SHIFT 4 /**< Shift value for PCNT_TCC */ #define _PCNT_IFC_TCC_MASK 0x10UL /**< Bit mask for PCNT_TCC */ #define _PCNT_IFC_TCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFC */ #define PCNT_IFC_TCC_DEFAULT (_PCNT_IFC_TCC_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_IFC */ #define PCNT_IFC_OQSTERR (0x1UL << 5) /**< Clear OQSTERR Interrupt Flag */ #define _PCNT_IFC_OQSTERR_SHIFT 5 /**< Shift value for PCNT_OQSTERR */ #define _PCNT_IFC_OQSTERR_MASK 0x20UL /**< Bit mask for PCNT_OQSTERR */ #define _PCNT_IFC_OQSTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFC */ #define PCNT_IFC_OQSTERR_DEFAULT (_PCNT_IFC_OQSTERR_DEFAULT << 5) /**< Shifted mode DEFAULT for PCNT_IFC */ /* Bit fields for PCNT IEN */ #define _PCNT_IEN_RESETVALUE 0x00000000UL /**< Default value for PCNT_IEN */ #define _PCNT_IEN_MASK 0x0000003FUL /**< Mask for PCNT_IEN */ #define PCNT_IEN_UF (0x1UL << 0) /**< UF Interrupt Enable */ #define _PCNT_IEN_UF_SHIFT 0 /**< Shift value for PCNT_UF */ #define _PCNT_IEN_UF_MASK 0x1UL /**< Bit mask for PCNT_UF */ #define _PCNT_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */ #define PCNT_IEN_UF_DEFAULT (_PCNT_IEN_UF_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_IEN */ #define PCNT_IEN_OF (0x1UL << 1) /**< OF Interrupt Enable */ #define _PCNT_IEN_OF_SHIFT 1 /**< Shift value for PCNT_OF */ #define _PCNT_IEN_OF_MASK 0x2UL /**< Bit mask for PCNT_OF */ #define _PCNT_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */ #define PCNT_IEN_OF_DEFAULT (_PCNT_IEN_OF_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_IEN */ #define PCNT_IEN_DIRCNG (0x1UL << 2) /**< DIRCNG Interrupt Enable */ #define _PCNT_IEN_DIRCNG_SHIFT 2 /**< Shift value for PCNT_DIRCNG */ #define _PCNT_IEN_DIRCNG_MASK 0x4UL /**< Bit mask for PCNT_DIRCNG */ #define _PCNT_IEN_DIRCNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */ #define PCNT_IEN_DIRCNG_DEFAULT (_PCNT_IEN_DIRCNG_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_IEN */ #define PCNT_IEN_AUXOF (0x1UL << 3) /**< AUXOF Interrupt Enable */ #define _PCNT_IEN_AUXOF_SHIFT 3 /**< Shift value for PCNT_AUXOF */ #define _PCNT_IEN_AUXOF_MASK 0x8UL /**< Bit mask for PCNT_AUXOF */ #define _PCNT_IEN_AUXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */ #define PCNT_IEN_AUXOF_DEFAULT (_PCNT_IEN_AUXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for PCNT_IEN */ #define PCNT_IEN_TCC (0x1UL << 4) /**< TCC Interrupt Enable */ #define _PCNT_IEN_TCC_SHIFT 4 /**< Shift value for PCNT_TCC */ #define _PCNT_IEN_TCC_MASK 0x10UL /**< Bit mask for PCNT_TCC */ #define _PCNT_IEN_TCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */ #define PCNT_IEN_TCC_DEFAULT (_PCNT_IEN_TCC_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_IEN */ #define PCNT_IEN_OQSTERR (0x1UL << 5) /**< OQSTERR Interrupt Enable */ #define _PCNT_IEN_OQSTERR_SHIFT 5 /**< Shift value for PCNT_OQSTERR */ #define _PCNT_IEN_OQSTERR_MASK 0x20UL /**< Bit mask for PCNT_OQSTERR */ #define _PCNT_IEN_OQSTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */ #define PCNT_IEN_OQSTERR_DEFAULT (_PCNT_IEN_OQSTERR_DEFAULT << 5) /**< Shifted mode DEFAULT for PCNT_IEN */ /* Bit fields for PCNT ROUTELOC0 */ #define _PCNT_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for PCNT_ROUTELOC0 */ #define _PCNT_ROUTELOC0_MASK 0x00001F1FUL /**< Mask for PCNT_ROUTELOC0 */ #define _PCNT_ROUTELOC0_S0INLOC_SHIFT 0 /**< Shift value for PCNT_S0INLOC */ #define _PCNT_ROUTELOC0_S0INLOC_MASK 0x1FUL /**< Bit mask for PCNT_S0INLOC */ #define _PCNT_ROUTELOC0_S0INLOC_LOC0 0x00000000UL /**< Mode LOC0 for PCNT_ROUTELOC0 */ #define _PCNT_ROUTELOC0_S0INLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_ROUTELOC0 */ #define _PCNT_ROUTELOC0_S0INLOC_LOC1 0x00000001UL /**< Mode LOC1 for PCNT_ROUTELOC0 */ #define _PCNT_ROUTELOC0_S0INLOC_LOC2 0x00000002UL /**< Mode LOC2 for PCNT_ROUTELOC0 */ #define _PCNT_ROUTELOC0_S0INLOC_LOC3 0x00000003UL /**< Mode LOC3 for PCNT_ROUTELOC0 */ #define _PCNT_ROUTELOC0_S0INLOC_LOC4 0x00000004UL /**< Mode LOC4 for PCNT_ROUTELOC0 */ #define _PCNT_ROUTELOC0_S0INLOC_LOC5 0x00000005UL /**< Mode LOC5 for PCNT_ROUTELOC0 */ #define _PCNT_ROUTELOC0_S0INLOC_LOC6 0x00000006UL /**< Mode LOC6 for PCNT_ROUTELOC0 */ #define _PCNT_ROUTELOC0_S0INLOC_LOC7 0x00000007UL /**< Mode LOC7 for PCNT_ROUTELOC0 */ #define _PCNT_ROUTELOC0_S0INLOC_LOC8 0x00000008UL /**< Mode LOC8 for PCNT_ROUTELOC0 */ #define _PCNT_ROUTELOC0_S0INLOC_LOC9 0x00000009UL /**< Mode LOC9 for PCNT_ROUTELOC0 */ #define _PCNT_ROUTELOC0_S0INLOC_LOC10 0x0000000AUL /**< Mode LOC10 for PCNT_ROUTELOC0 */ #define _PCNT_ROUTELOC0_S0INLOC_LOC11 0x0000000BUL /**< Mode LOC11 for PCNT_ROUTELOC0 */ #define _PCNT_ROUTELOC0_S0INLOC_LOC12 0x0000000CUL /**< Mode LOC12 for PCNT_ROUTELOC0 */ #define _PCNT_ROUTELOC0_S0INLOC_LOC13 0x0000000DUL /**< Mode LOC13 for PCNT_ROUTELOC0 */ #define _PCNT_ROUTELOC0_S0INLOC_LOC14 0x0000000EUL /**< Mode LOC14 for PCNT_ROUTELOC0 */ #define _PCNT_ROUTELOC0_S0INLOC_LOC15 0x0000000FUL /**< Mode LOC15 for PCNT_ROUTELOC0 */ #define _PCNT_ROUTELOC0_S0INLOC_LOC16 0x00000010UL /**< Mode LOC16 for PCNT_ROUTELOC0 */ #define _PCNT_ROUTELOC0_S0INLOC_LOC17 0x00000011UL /**< Mode LOC17 for PCNT_ROUTELOC0 */ #define _PCNT_ROUTELOC0_S0INLOC_LOC18 0x00000012UL /**< Mode LOC18 for PCNT_ROUTELOC0 */ #define _PCNT_ROUTELOC0_S0INLOC_LOC19 0x00000013UL /**< Mode LOC19 for PCNT_ROUTELOC0 */ #define _PCNT_ROUTELOC0_S0INLOC_LOC20 0x00000014UL /**< Mode LOC20 for PCNT_ROUTELOC0 */ #define _PCNT_ROUTELOC0_S0INLOC_LOC21 0x00000015UL /**< Mode LOC21 for PCNT_ROUTELOC0 */ #define _PCNT_ROUTELOC0_S0INLOC_LOC22 0x00000016UL /**< Mode LOC22 for PCNT_ROUTELOC0 */ #define _PCNT_ROUTELOC0_S0INLOC_LOC23 0x00000017UL /**< Mode LOC23 for PCNT_ROUTELOC0 */ #define _PCNT_ROUTELOC0_S0INLOC_LOC24 0x00000018UL /**< Mode LOC24 for PCNT_ROUTELOC0 */ #define _PCNT_ROUTELOC0_S0INLOC_LOC25 0x00000019UL /**< Mode LOC25 for PCNT_ROUTELOC0 */ #define _PCNT_ROUTELOC0_S0INLOC_LOC26 0x0000001AUL /**< Mode LOC26 for PCNT_ROUTELOC0 */ #define _PCNT_ROUTELOC0_S0INLOC_LOC27 0x0000001BUL /**< Mode LOC27 for PCNT_ROUTELOC0 */ #define _PCNT_ROUTELOC0_S0INLOC_LOC28 0x0000001CUL /**< Mode LOC28 for PCNT_ROUTELOC0 */ #define _PCNT_ROUTELOC0_S0INLOC_LOC29 0x0000001DUL /**< Mode LOC29 for PCNT_ROUTELOC0 */ #define _PCNT_ROUTELOC0_S0INLOC_LOC30 0x0000001EUL /**< Mode LOC30 for PCNT_ROUTELOC0 */ #define _PCNT_ROUTELOC0_S0INLOC_LOC31 0x0000001FUL /**< Mode LOC31 for PCNT_ROUTELOC0 */ #define PCNT_ROUTELOC0_S0INLOC_LOC0 (_PCNT_ROUTELOC0_S0INLOC_LOC0 << 0) /**< Shifted mode LOC0 for PCNT_ROUTELOC0 */ #define PCNT_ROUTELOC0_S0INLOC_DEFAULT (_PCNT_ROUTELOC0_S0INLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_ROUTELOC0 */ #define PCNT_ROUTELOC0_S0INLOC_LOC1 (_PCNT_ROUTELOC0_S0INLOC_LOC1 << 0) /**< Shifted mode LOC1 for PCNT_ROUTELOC0 */ #define PCNT_ROUTELOC0_S0INLOC_LOC2 (_PCNT_ROUTELOC0_S0INLOC_LOC2 << 0) /**< Shifted mode LOC2 for PCNT_ROUTELOC0 */ #define PCNT_ROUTELOC0_S0INLOC_LOC3 (_PCNT_ROUTELOC0_S0INLOC_LOC3 << 0) /**< Shifted mode LOC3 for PCNT_ROUTELOC0 */ #define PCNT_ROUTELOC0_S0INLOC_LOC4 (_PCNT_ROUTELOC0_S0INLOC_LOC4 << 0) /**< Shifted mode LOC4 for PCNT_ROUTELOC0 */ #define PCNT_ROUTELOC0_S0INLOC_LOC5 (_PCNT_ROUTELOC0_S0INLOC_LOC5 << 0) /**< Shifted mode LOC5 for PCNT_ROUTELOC0 */ #define PCNT_ROUTELOC0_S0INLOC_LOC6 (_PCNT_ROUTELOC0_S0INLOC_LOC6 << 0) /**< Shifted mode LOC6 for PCNT_ROUTELOC0 */ #define PCNT_ROUTELOC0_S0INLOC_LOC7 (_PCNT_ROUTELOC0_S0INLOC_LOC7 << 0) /**< Shifted mode LOC7 for PCNT_ROUTELOC0 */ #define PCNT_ROUTELOC0_S0INLOC_LOC8 (_PCNT_ROUTELOC0_S0INLOC_LOC8 << 0) /**< Shifted mode LOC8 for PCNT_ROUTELOC0 */ #define PCNT_ROUTELOC0_S0INLOC_LOC9 (_PCNT_ROUTELOC0_S0INLOC_LOC9 << 0) /**< Shifted mode LOC9 for PCNT_ROUTELOC0 */ #define PCNT_ROUTELOC0_S0INLOC_LOC10 (_PCNT_ROUTELOC0_S0INLOC_LOC10 << 0) /**< Shifted mode LOC10 for PCNT_ROUTELOC0 */ #define PCNT_ROUTELOC0_S0INLOC_LOC11 (_PCNT_ROUTELOC0_S0INLOC_LOC11 << 0) /**< Shifted mode LOC11 for PCNT_ROUTELOC0 */ #define PCNT_ROUTELOC0_S0INLOC_LOC12 (_PCNT_ROUTELOC0_S0INLOC_LOC12 << 0) /**< Shifted mode LOC12 for PCNT_ROUTELOC0 */ #define PCNT_ROUTELOC0_S0INLOC_LOC13 (_PCNT_ROUTELOC0_S0INLOC_LOC13 << 0) /**< Shifted mode LOC13 for PCNT_ROUTELOC0 */ #define PCNT_ROUTELOC0_S0INLOC_LOC14 (_PCNT_ROUTELOC0_S0INLOC_LOC14 << 0) /**< Shifted mode LOC14 for PCNT_ROUTELOC0 */ #define PCNT_ROUTELOC0_S0INLOC_LOC15 (_PCNT_ROUTELOC0_S0INLOC_LOC15 << 0) /**< Shifted mode LOC15 for PCNT_ROUTELOC0 */ #define PCNT_ROUTELOC0_S0INLOC_LOC16 (_PCNT_ROUTELOC0_S0INLOC_LOC16 << 0) /**< Shifted mode LOC16 for PCNT_ROUTELOC0 */ #define PCNT_ROUTELOC0_S0INLOC_LOC17 (_PCNT_ROUTELOC0_S0INLOC_LOC17 << 0) /**< Shifted mode LOC17 for PCNT_ROUTELOC0 */ #define PCNT_ROUTELOC0_S0INLOC_LOC18 (_PCNT_ROUTELOC0_S0INLOC_LOC18 << 0) /**< Shifted mode LOC18 for PCNT_ROUTELOC0 */ #define PCNT_ROUTELOC0_S0INLOC_LOC19 (_PCNT_ROUTELOC0_S0INLOC_LOC19 << 0) /**< Shifted mode LOC19 for PCNT_ROUTELOC0 */ #define PCNT_ROUTELOC0_S0INLOC_LOC20 (_PCNT_ROUTELOC0_S0INLOC_LOC20 << 0) /**< Shifted mode LOC20 for PCNT_ROUTELOC0 */ #define PCNT_ROUTELOC0_S0INLOC_LOC21 (_PCNT_ROUTELOC0_S0INLOC_LOC21 << 0) /**< Shifted mode LOC21 for PCNT_ROUTELOC0 */ #define PCNT_ROUTELOC0_S0INLOC_LOC22 (_PCNT_ROUTELOC0_S0INLOC_LOC22 << 0) /**< Shifted mode LOC22 for PCNT_ROUTELOC0 */ #define PCNT_ROUTELOC0_S0INLOC_LOC23 (_PCNT_ROUTELOC0_S0INLOC_LOC23 << 0) /**< Shifted mode LOC23 for PCNT_ROUTELOC0 */ #define PCNT_ROUTELOC0_S0INLOC_LOC24 (_PCNT_ROUTELOC0_S0INLOC_LOC24 << 0) /**< Shifted mode LOC24 for PCNT_ROUTELOC0 */ #define PCNT_ROUTELOC0_S0INLOC_LOC25 (_PCNT_ROUTELOC0_S0INLOC_LOC25 << 0) /**< Shifted mode LOC25 for PCNT_ROUTELOC0 */ #define PCNT_ROUTELOC0_S0INLOC_LOC26 (_PCNT_ROUTELOC0_S0INLOC_LOC26 << 0) /**< Shifted mode LOC26 for PCNT_ROUTELOC0 */ #define PCNT_ROUTELOC0_S0INLOC_LOC27 (_PCNT_ROUTELOC0_S0INLOC_LOC27 << 0) /**< Shifted mode LOC27 for PCNT_ROUTELOC0 */ #define PCNT_ROUTELOC0_S0INLOC_LOC28 (_PCNT_ROUTELOC0_S0INLOC_LOC28 << 0) /**< Shifted mode LOC28 for PCNT_ROUTELOC0 */ #define PCNT_ROUTELOC0_S0INLOC_LOC29 (_PCNT_ROUTELOC0_S0INLOC_LOC29 << 0) /**< Shifted mode LOC29 for PCNT_ROUTELOC0 */ #define PCNT_ROUTELOC0_S0INLOC_LOC30 (_PCNT_ROUTELOC0_S0INLOC_LOC30 << 0) /**< Shifted mode LOC30 for PCNT_ROUTELOC0 */ #define PCNT_ROUTELOC0_S0INLOC_LOC31 (_PCNT_ROUTELOC0_S0INLOC_LOC31 << 0) /**< Shifted mode LOC31 for PCNT_ROUTELOC0 */ #define _PCNT_ROUTELOC0_S1INLOC_SHIFT 8 /**< Shift value for PCNT_S1INLOC */ #define _PCNT_ROUTELOC0_S1INLOC_MASK 0x1F00UL /**< Bit mask for PCNT_S1INLOC */ #define _PCNT_ROUTELOC0_S1INLOC_LOC0 0x00000000UL /**< Mode LOC0 for PCNT_ROUTELOC0 */ #define _PCNT_ROUTELOC0_S1INLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_ROUTELOC0 */ #define _PCNT_ROUTELOC0_S1INLOC_LOC1 0x00000001UL /**< Mode LOC1 for PCNT_ROUTELOC0 */ #define _PCNT_ROUTELOC0_S1INLOC_LOC2 0x00000002UL /**< Mode LOC2 for PCNT_ROUTELOC0 */ #define _PCNT_ROUTELOC0_S1INLOC_LOC3 0x00000003UL /**< Mode LOC3 for PCNT_ROUTELOC0 */ #define _PCNT_ROUTELOC0_S1INLOC_LOC4 0x00000004UL /**< Mode LOC4 for PCNT_ROUTELOC0 */ #define _PCNT_ROUTELOC0_S1INLOC_LOC5 0x00000005UL /**< Mode LOC5 for PCNT_ROUTELOC0 */ #define _PCNT_ROUTELOC0_S1INLOC_LOC6 0x00000006UL /**< Mode LOC6 for PCNT_ROUTELOC0 */ #define _PCNT_ROUTELOC0_S1INLOC_LOC7 0x00000007UL /**< Mode LOC7 for PCNT_ROUTELOC0 */ #define _PCNT_ROUTELOC0_S1INLOC_LOC8 0x00000008UL /**< Mode LOC8 for PCNT_ROUTELOC0 */ #define _PCNT_ROUTELOC0_S1INLOC_LOC9 0x00000009UL /**< Mode LOC9 for PCNT_ROUTELOC0 */ #define _PCNT_ROUTELOC0_S1INLOC_LOC10 0x0000000AUL /**< Mode LOC10 for PCNT_ROUTELOC0 */ #define _PCNT_ROUTELOC0_S1INLOC_LOC11 0x0000000BUL /**< Mode LOC11 for PCNT_ROUTELOC0 */ #define _PCNT_ROUTELOC0_S1INLOC_LOC12 0x0000000CUL /**< Mode LOC12 for PCNT_ROUTELOC0 */ #define _PCNT_ROUTELOC0_S1INLOC_LOC13 0x0000000DUL /**< Mode LOC13 for PCNT_ROUTELOC0 */ #define _PCNT_ROUTELOC0_S1INLOC_LOC14 0x0000000EUL /**< Mode LOC14 for PCNT_ROUTELOC0 */ #define _PCNT_ROUTELOC0_S1INLOC_LOC15 0x0000000FUL /**< Mode LOC15 for PCNT_ROUTELOC0 */ #define _PCNT_ROUTELOC0_S1INLOC_LOC16 0x00000010UL /**< Mode LOC16 for PCNT_ROUTELOC0 */ #define _PCNT_ROUTELOC0_S1INLOC_LOC17 0x00000011UL /**< Mode LOC17 for PCNT_ROUTELOC0 */ #define _PCNT_ROUTELOC0_S1INLOC_LOC18 0x00000012UL /**< Mode LOC18 for PCNT_ROUTELOC0 */ #define _PCNT_ROUTELOC0_S1INLOC_LOC19 0x00000013UL /**< Mode LOC19 for PCNT_ROUTELOC0 */ #define _PCNT_ROUTELOC0_S1INLOC_LOC20 0x00000014UL /**< Mode LOC20 for PCNT_ROUTELOC0 */ #define _PCNT_ROUTELOC0_S1INLOC_LOC21 0x00000015UL /**< Mode LOC21 for PCNT_ROUTELOC0 */ #define _PCNT_ROUTELOC0_S1INLOC_LOC22 0x00000016UL /**< Mode LOC22 for PCNT_ROUTELOC0 */ #define _PCNT_ROUTELOC0_S1INLOC_LOC23 0x00000017UL /**< Mode LOC23 for PCNT_ROUTELOC0 */ #define _PCNT_ROUTELOC0_S1INLOC_LOC24 0x00000018UL /**< Mode LOC24 for PCNT_ROUTELOC0 */ #define _PCNT_ROUTELOC0_S1INLOC_LOC25 0x00000019UL /**< Mode LOC25 for PCNT_ROUTELOC0 */ #define _PCNT_ROUTELOC0_S1INLOC_LOC26 0x0000001AUL /**< Mode LOC26 for PCNT_ROUTELOC0 */ #define _PCNT_ROUTELOC0_S1INLOC_LOC27 0x0000001BUL /**< Mode LOC27 for PCNT_ROUTELOC0 */ #define _PCNT_ROUTELOC0_S1INLOC_LOC28 0x0000001CUL /**< Mode LOC28 for PCNT_ROUTELOC0 */ #define _PCNT_ROUTELOC0_S1INLOC_LOC29 0x0000001DUL /**< Mode LOC29 for PCNT_ROUTELOC0 */ #define _PCNT_ROUTELOC0_S1INLOC_LOC30 0x0000001EUL /**< Mode LOC30 for PCNT_ROUTELOC0 */ #define _PCNT_ROUTELOC0_S1INLOC_LOC31 0x0000001FUL /**< Mode LOC31 for PCNT_ROUTELOC0 */ #define PCNT_ROUTELOC0_S1INLOC_LOC0 (_PCNT_ROUTELOC0_S1INLOC_LOC0 << 8) /**< Shifted mode LOC0 for PCNT_ROUTELOC0 */ #define PCNT_ROUTELOC0_S1INLOC_DEFAULT (_PCNT_ROUTELOC0_S1INLOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PCNT_ROUTELOC0 */ #define PCNT_ROUTELOC0_S1INLOC_LOC1 (_PCNT_ROUTELOC0_S1INLOC_LOC1 << 8) /**< Shifted mode LOC1 for PCNT_ROUTELOC0 */ #define PCNT_ROUTELOC0_S1INLOC_LOC2 (_PCNT_ROUTELOC0_S1INLOC_LOC2 << 8) /**< Shifted mode LOC2 for PCNT_ROUTELOC0 */ #define PCNT_ROUTELOC0_S1INLOC_LOC3 (_PCNT_ROUTELOC0_S1INLOC_LOC3 << 8) /**< Shifted mode LOC3 for PCNT_ROUTELOC0 */ #define PCNT_ROUTELOC0_S1INLOC_LOC4 (_PCNT_ROUTELOC0_S1INLOC_LOC4 << 8) /**< Shifted mode LOC4 for PCNT_ROUTELOC0 */ #define PCNT_ROUTELOC0_S1INLOC_LOC5 (_PCNT_ROUTELOC0_S1INLOC_LOC5 << 8) /**< Shifted mode LOC5 for PCNT_ROUTELOC0 */ #define PCNT_ROUTELOC0_S1INLOC_LOC6 (_PCNT_ROUTELOC0_S1INLOC_LOC6 << 8) /**< Shifted mode LOC6 for PCNT_ROUTELOC0 */ #define PCNT_ROUTELOC0_S1INLOC_LOC7 (_PCNT_ROUTELOC0_S1INLOC_LOC7 << 8) /**< Shifted mode LOC7 for PCNT_ROUTELOC0 */ #define PCNT_ROUTELOC0_S1INLOC_LOC8 (_PCNT_ROUTELOC0_S1INLOC_LOC8 << 8) /**< Shifted mode LOC8 for PCNT_ROUTELOC0 */ #define PCNT_ROUTELOC0_S1INLOC_LOC9 (_PCNT_ROUTELOC0_S1INLOC_LOC9 << 8) /**< Shifted mode LOC9 for PCNT_ROUTELOC0 */ #define PCNT_ROUTELOC0_S1INLOC_LOC10 (_PCNT_ROUTELOC0_S1INLOC_LOC10 << 8) /**< Shifted mode LOC10 for PCNT_ROUTELOC0 */ #define PCNT_ROUTELOC0_S1INLOC_LOC11 (_PCNT_ROUTELOC0_S1INLOC_LOC11 << 8) /**< Shifted mode LOC11 for PCNT_ROUTELOC0 */ #define PCNT_ROUTELOC0_S1INLOC_LOC12 (_PCNT_ROUTELOC0_S1INLOC_LOC12 << 8) /**< Shifted mode LOC12 for PCNT_ROUTELOC0 */ #define PCNT_ROUTELOC0_S1INLOC_LOC13 (_PCNT_ROUTELOC0_S1INLOC_LOC13 << 8) /**< Shifted mode LOC13 for PCNT_ROUTELOC0 */ #define PCNT_ROUTELOC0_S1INLOC_LOC14 (_PCNT_ROUTELOC0_S1INLOC_LOC14 << 8) /**< Shifted mode LOC14 for PCNT_ROUTELOC0 */ #define PCNT_ROUTELOC0_S1INLOC_LOC15 (_PCNT_ROUTELOC0_S1INLOC_LOC15 << 8) /**< Shifted mode LOC15 for PCNT_ROUTELOC0 */ #define PCNT_ROUTELOC0_S1INLOC_LOC16 (_PCNT_ROUTELOC0_S1INLOC_LOC16 << 8) /**< Shifted mode LOC16 for PCNT_ROUTELOC0 */ #define PCNT_ROUTELOC0_S1INLOC_LOC17 (_PCNT_ROUTELOC0_S1INLOC_LOC17 << 8) /**< Shifted mode LOC17 for PCNT_ROUTELOC0 */ #define PCNT_ROUTELOC0_S1INLOC_LOC18 (_PCNT_ROUTELOC0_S1INLOC_LOC18 << 8) /**< Shifted mode LOC18 for PCNT_ROUTELOC0 */ #define PCNT_ROUTELOC0_S1INLOC_LOC19 (_PCNT_ROUTELOC0_S1INLOC_LOC19 << 8) /**< Shifted mode LOC19 for PCNT_ROUTELOC0 */ #define PCNT_ROUTELOC0_S1INLOC_LOC20 (_PCNT_ROUTELOC0_S1INLOC_LOC20 << 8) /**< Shifted mode LOC20 for PCNT_ROUTELOC0 */ #define PCNT_ROUTELOC0_S1INLOC_LOC21 (_PCNT_ROUTELOC0_S1INLOC_LOC21 << 8) /**< Shifted mode LOC21 for PCNT_ROUTELOC0 */ #define PCNT_ROUTELOC0_S1INLOC_LOC22 (_PCNT_ROUTELOC0_S1INLOC_LOC22 << 8) /**< Shifted mode LOC22 for PCNT_ROUTELOC0 */ #define PCNT_ROUTELOC0_S1INLOC_LOC23 (_PCNT_ROUTELOC0_S1INLOC_LOC23 << 8) /**< Shifted mode LOC23 for PCNT_ROUTELOC0 */ #define PCNT_ROUTELOC0_S1INLOC_LOC24 (_PCNT_ROUTELOC0_S1INLOC_LOC24 << 8) /**< Shifted mode LOC24 for PCNT_ROUTELOC0 */ #define PCNT_ROUTELOC0_S1INLOC_LOC25 (_PCNT_ROUTELOC0_S1INLOC_LOC25 << 8) /**< Shifted mode LOC25 for PCNT_ROUTELOC0 */ #define PCNT_ROUTELOC0_S1INLOC_LOC26 (_PCNT_ROUTELOC0_S1INLOC_LOC26 << 8) /**< Shifted mode LOC26 for PCNT_ROUTELOC0 */ #define PCNT_ROUTELOC0_S1INLOC_LOC27 (_PCNT_ROUTELOC0_S1INLOC_LOC27 << 8) /**< Shifted mode LOC27 for PCNT_ROUTELOC0 */ #define PCNT_ROUTELOC0_S1INLOC_LOC28 (_PCNT_ROUTELOC0_S1INLOC_LOC28 << 8) /**< Shifted mode LOC28 for PCNT_ROUTELOC0 */ #define PCNT_ROUTELOC0_S1INLOC_LOC29 (_PCNT_ROUTELOC0_S1INLOC_LOC29 << 8) /**< Shifted mode LOC29 for PCNT_ROUTELOC0 */ #define PCNT_ROUTELOC0_S1INLOC_LOC30 (_PCNT_ROUTELOC0_S1INLOC_LOC30 << 8) /**< Shifted mode LOC30 for PCNT_ROUTELOC0 */ #define PCNT_ROUTELOC0_S1INLOC_LOC31 (_PCNT_ROUTELOC0_S1INLOC_LOC31 << 8) /**< Shifted mode LOC31 for PCNT_ROUTELOC0 */ /* Bit fields for PCNT FREEZE */ #define _PCNT_FREEZE_RESETVALUE 0x00000000UL /**< Default value for PCNT_FREEZE */ #define _PCNT_FREEZE_MASK 0x00000001UL /**< Mask for PCNT_FREEZE */ #define PCNT_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */ #define _PCNT_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for PCNT_REGFREEZE */ #define _PCNT_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for PCNT_REGFREEZE */ #define _PCNT_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_FREEZE */ #define _PCNT_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for PCNT_FREEZE */ #define _PCNT_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for PCNT_FREEZE */ #define PCNT_FREEZE_REGFREEZE_DEFAULT (_PCNT_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_FREEZE */ #define PCNT_FREEZE_REGFREEZE_UPDATE (_PCNT_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for PCNT_FREEZE */ #define PCNT_FREEZE_REGFREEZE_FREEZE (_PCNT_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for PCNT_FREEZE */ /* Bit fields for PCNT SYNCBUSY */ #define _PCNT_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for PCNT_SYNCBUSY */ #define _PCNT_SYNCBUSY_MASK 0x0000000FUL /**< Mask for PCNT_SYNCBUSY */ #define PCNT_SYNCBUSY_CTRL (0x1UL << 0) /**< CTRL Register Busy */ #define _PCNT_SYNCBUSY_CTRL_SHIFT 0 /**< Shift value for PCNT_CTRL */ #define _PCNT_SYNCBUSY_CTRL_MASK 0x1UL /**< Bit mask for PCNT_CTRL */ #define _PCNT_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_SYNCBUSY */ #define PCNT_SYNCBUSY_CTRL_DEFAULT (_PCNT_SYNCBUSY_CTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_SYNCBUSY */ #define PCNT_SYNCBUSY_CMD (0x1UL << 1) /**< CMD Register Busy */ #define _PCNT_SYNCBUSY_CMD_SHIFT 1 /**< Shift value for PCNT_CMD */ #define _PCNT_SYNCBUSY_CMD_MASK 0x2UL /**< Bit mask for PCNT_CMD */ #define _PCNT_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_SYNCBUSY */ #define PCNT_SYNCBUSY_CMD_DEFAULT (_PCNT_SYNCBUSY_CMD_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_SYNCBUSY */ #define PCNT_SYNCBUSY_TOPB (0x1UL << 2) /**< TOPB Register Busy */ #define _PCNT_SYNCBUSY_TOPB_SHIFT 2 /**< Shift value for PCNT_TOPB */ #define _PCNT_SYNCBUSY_TOPB_MASK 0x4UL /**< Bit mask for PCNT_TOPB */ #define _PCNT_SYNCBUSY_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_SYNCBUSY */ #define PCNT_SYNCBUSY_TOPB_DEFAULT (_PCNT_SYNCBUSY_TOPB_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_SYNCBUSY */ #define PCNT_SYNCBUSY_OVSCFG (0x1UL << 3) /**< OVSCFG Register Busy */ #define _PCNT_SYNCBUSY_OVSCFG_SHIFT 3 /**< Shift value for PCNT_OVSCFG */ #define _PCNT_SYNCBUSY_OVSCFG_MASK 0x8UL /**< Bit mask for PCNT_OVSCFG */ #define _PCNT_SYNCBUSY_OVSCFG_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_SYNCBUSY */ #define PCNT_SYNCBUSY_OVSCFG_DEFAULT (_PCNT_SYNCBUSY_OVSCFG_DEFAULT << 3) /**< Shifted mode DEFAULT for PCNT_SYNCBUSY */ /* Bit fields for PCNT AUXCNT */ #define _PCNT_AUXCNT_RESETVALUE 0x00000000UL /**< Default value for PCNT_AUXCNT */ #define _PCNT_AUXCNT_MASK 0x0000FFFFUL /**< Mask for PCNT_AUXCNT */ #define _PCNT_AUXCNT_AUXCNT_SHIFT 0 /**< Shift value for PCNT_AUXCNT */ #define _PCNT_AUXCNT_AUXCNT_MASK 0xFFFFUL /**< Bit mask for PCNT_AUXCNT */ #define _PCNT_AUXCNT_AUXCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_AUXCNT */ #define PCNT_AUXCNT_AUXCNT_DEFAULT (_PCNT_AUXCNT_AUXCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_AUXCNT */ /* Bit fields for PCNT INPUT */ #define _PCNT_INPUT_RESETVALUE 0x00000000UL /**< Default value for PCNT_INPUT */ #define _PCNT_INPUT_MASK 0x00000BEFUL /**< Mask for PCNT_INPUT */ #define _PCNT_INPUT_S0PRSSEL_SHIFT 0 /**< Shift value for PCNT_S0PRSSEL */ #define _PCNT_INPUT_S0PRSSEL_MASK 0xFUL /**< Bit mask for PCNT_S0PRSSEL */ #define _PCNT_INPUT_S0PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_INPUT */ #define _PCNT_INPUT_S0PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PCNT_INPUT */ #define _PCNT_INPUT_S0PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PCNT_INPUT */ #define _PCNT_INPUT_S0PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PCNT_INPUT */ #define _PCNT_INPUT_S0PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PCNT_INPUT */ #define _PCNT_INPUT_S0PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PCNT_INPUT */ #define _PCNT_INPUT_S0PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PCNT_INPUT */ #define _PCNT_INPUT_S0PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PCNT_INPUT */ #define _PCNT_INPUT_S0PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PCNT_INPUT */ #define _PCNT_INPUT_S0PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PCNT_INPUT */ #define _PCNT_INPUT_S0PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PCNT_INPUT */ #define _PCNT_INPUT_S0PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PCNT_INPUT */ #define _PCNT_INPUT_S0PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PCNT_INPUT */ #define PCNT_INPUT_S0PRSSEL_DEFAULT (_PCNT_INPUT_S0PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_INPUT */ #define PCNT_INPUT_S0PRSSEL_PRSCH0 (_PCNT_INPUT_S0PRSSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for PCNT_INPUT */ #define PCNT_INPUT_S0PRSSEL_PRSCH1 (_PCNT_INPUT_S0PRSSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for PCNT_INPUT */ #define PCNT_INPUT_S0PRSSEL_PRSCH2 (_PCNT_INPUT_S0PRSSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for PCNT_INPUT */ #define PCNT_INPUT_S0PRSSEL_PRSCH3 (_PCNT_INPUT_S0PRSSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for PCNT_INPUT */ #define PCNT_INPUT_S0PRSSEL_PRSCH4 (_PCNT_INPUT_S0PRSSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for PCNT_INPUT */ #define PCNT_INPUT_S0PRSSEL_PRSCH5 (_PCNT_INPUT_S0PRSSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for PCNT_INPUT */ #define PCNT_INPUT_S0PRSSEL_PRSCH6 (_PCNT_INPUT_S0PRSSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for PCNT_INPUT */ #define PCNT_INPUT_S0PRSSEL_PRSCH7 (_PCNT_INPUT_S0PRSSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for PCNT_INPUT */ #define PCNT_INPUT_S0PRSSEL_PRSCH8 (_PCNT_INPUT_S0PRSSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for PCNT_INPUT */ #define PCNT_INPUT_S0PRSSEL_PRSCH9 (_PCNT_INPUT_S0PRSSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for PCNT_INPUT */ #define PCNT_INPUT_S0PRSSEL_PRSCH10 (_PCNT_INPUT_S0PRSSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for PCNT_INPUT */ #define PCNT_INPUT_S0PRSSEL_PRSCH11 (_PCNT_INPUT_S0PRSSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for PCNT_INPUT */ #define PCNT_INPUT_S0PRSEN (0x1UL << 5) /**< S0IN PRS Enable */ #define _PCNT_INPUT_S0PRSEN_SHIFT 5 /**< Shift value for PCNT_S0PRSEN */ #define _PCNT_INPUT_S0PRSEN_MASK 0x20UL /**< Bit mask for PCNT_S0PRSEN */ #define _PCNT_INPUT_S0PRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_INPUT */ #define PCNT_INPUT_S0PRSEN_DEFAULT (_PCNT_INPUT_S0PRSEN_DEFAULT << 5) /**< Shifted mode DEFAULT for PCNT_INPUT */ #define _PCNT_INPUT_S1PRSSEL_SHIFT 6 /**< Shift value for PCNT_S1PRSSEL */ #define _PCNT_INPUT_S1PRSSEL_MASK 0x3C0UL /**< Bit mask for PCNT_S1PRSSEL */ #define _PCNT_INPUT_S1PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_INPUT */ #define _PCNT_INPUT_S1PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PCNT_INPUT */ #define _PCNT_INPUT_S1PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PCNT_INPUT */ #define _PCNT_INPUT_S1PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PCNT_INPUT */ #define _PCNT_INPUT_S1PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PCNT_INPUT */ #define _PCNT_INPUT_S1PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PCNT_INPUT */ #define _PCNT_INPUT_S1PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PCNT_INPUT */ #define _PCNT_INPUT_S1PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PCNT_INPUT */ #define _PCNT_INPUT_S1PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PCNT_INPUT */ #define _PCNT_INPUT_S1PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PCNT_INPUT */ #define _PCNT_INPUT_S1PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PCNT_INPUT */ #define _PCNT_INPUT_S1PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PCNT_INPUT */ #define _PCNT_INPUT_S1PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PCNT_INPUT */ #define PCNT_INPUT_S1PRSSEL_DEFAULT (_PCNT_INPUT_S1PRSSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PCNT_INPUT */ #define PCNT_INPUT_S1PRSSEL_PRSCH0 (_PCNT_INPUT_S1PRSSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for PCNT_INPUT */ #define PCNT_INPUT_S1PRSSEL_PRSCH1 (_PCNT_INPUT_S1PRSSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for PCNT_INPUT */ #define PCNT_INPUT_S1PRSSEL_PRSCH2 (_PCNT_INPUT_S1PRSSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for PCNT_INPUT */ #define PCNT_INPUT_S1PRSSEL_PRSCH3 (_PCNT_INPUT_S1PRSSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for PCNT_INPUT */ #define PCNT_INPUT_S1PRSSEL_PRSCH4 (_PCNT_INPUT_S1PRSSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for PCNT_INPUT */ #define PCNT_INPUT_S1PRSSEL_PRSCH5 (_PCNT_INPUT_S1PRSSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for PCNT_INPUT */ #define PCNT_INPUT_S1PRSSEL_PRSCH6 (_PCNT_INPUT_S1PRSSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for PCNT_INPUT */ #define PCNT_INPUT_S1PRSSEL_PRSCH7 (_PCNT_INPUT_S1PRSSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for PCNT_INPUT */ #define PCNT_INPUT_S1PRSSEL_PRSCH8 (_PCNT_INPUT_S1PRSSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for PCNT_INPUT */ #define PCNT_INPUT_S1PRSSEL_PRSCH9 (_PCNT_INPUT_S1PRSSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for PCNT_INPUT */ #define PCNT_INPUT_S1PRSSEL_PRSCH10 (_PCNT_INPUT_S1PRSSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for PCNT_INPUT */ #define PCNT_INPUT_S1PRSSEL_PRSCH11 (_PCNT_INPUT_S1PRSSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for PCNT_INPUT */ #define PCNT_INPUT_S1PRSEN (0x1UL << 11) /**< S1IN PRS Enable */ #define _PCNT_INPUT_S1PRSEN_SHIFT 11 /**< Shift value for PCNT_S1PRSEN */ #define _PCNT_INPUT_S1PRSEN_MASK 0x800UL /**< Bit mask for PCNT_S1PRSEN */ #define _PCNT_INPUT_S1PRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_INPUT */ #define PCNT_INPUT_S1PRSEN_DEFAULT (_PCNT_INPUT_S1PRSEN_DEFAULT << 11) /**< Shifted mode DEFAULT for PCNT_INPUT */ /* Bit fields for PCNT OVSCFG */ #define _PCNT_OVSCFG_RESETVALUE 0x00000000UL /**< Default value for PCNT_OVSCFG */ #define _PCNT_OVSCFG_MASK 0x000010FFUL /**< Mask for PCNT_OVSCFG */ #define _PCNT_OVSCFG_FILTLEN_SHIFT 0 /**< Shift value for PCNT_FILTLEN */ #define _PCNT_OVSCFG_FILTLEN_MASK 0xFFUL /**< Bit mask for PCNT_FILTLEN */ #define _PCNT_OVSCFG_FILTLEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_OVSCFG */ #define PCNT_OVSCFG_FILTLEN_DEFAULT (_PCNT_OVSCFG_FILTLEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_OVSCFG */ #define PCNT_OVSCFG_FLUTTERRM (0x1UL << 12) /**< Flutter Remove */ #define _PCNT_OVSCFG_FLUTTERRM_SHIFT 12 /**< Shift value for PCNT_FLUTTERRM */ #define _PCNT_OVSCFG_FLUTTERRM_MASK 0x1000UL /**< Bit mask for PCNT_FLUTTERRM */ #define _PCNT_OVSCFG_FLUTTERRM_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_OVSCFG */ #define PCNT_OVSCFG_FLUTTERRM_DEFAULT (_PCNT_OVSCFG_FLUTTERRM_DEFAULT << 12) /**< Shifted mode DEFAULT for PCNT_OVSCFG */ /** @} */ /** @} End of group EFR32MG12P_PCNT */ /** @} End of group Parts */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_prs.h.
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/***************************************************************************//** * @file * @brief EFR32MG12P_PRS register and bit field definitions * @version 5.7.0 ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * SPDX-License-Identifier: Zlib * * The licensor of this software is Silicon Laboratories Inc. * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be * appreciated but is not required. * 2. Altered source versions must be plainly marked as such, and must not be * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * ******************************************************************************/ #if defined(__ICCARM__) #pragma system_include /* Treat file as system include file. */ #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang system_header /* Treat file as system include file. */ #endif /***************************************************************************//** * @addtogroup Parts * @{ ******************************************************************************/ /***************************************************************************//** * @defgroup EFR32MG12P_PRS PRS * @{ * @brief EFR32MG12P_PRS Register Declaration ******************************************************************************/ /** PRS Register Declaration */ typedef struct { __IOM uint32_t SWPULSE; /**< Software Pulse Register */ __IOM uint32_t SWLEVEL; /**< Software Level Register */ __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ uint32_t RESERVED0[1U]; /**< Reserved for future use **/ __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ __IOM uint32_t ROUTELOC1; /**< I/O Routing Location Register */ __IOM uint32_t ROUTELOC2; /**< I/O Routing Location Register */ uint32_t RESERVED1[5U]; /**< Reserved for future use **/ __IOM uint32_t CTRL; /**< Control Register */ __IOM uint32_t DMAREQ0; /**< DMA Request 0 Register */ __IOM uint32_t DMAREQ1; /**< DMA Request 1 Register */ uint32_t RESERVED2[1U]; /**< Reserved for future use **/ __IM uint32_t PEEK; /**< PRS Channel Values */ uint32_t RESERVED3[3U]; /**< Reserved registers */ PRS_CH_TypeDef CH[12U]; /**< Channel registers */ } PRS_TypeDef; /** @} */ /***************************************************************************//** * @addtogroup EFR32MG12P_PRS * @{ * @defgroup EFR32MG12P_PRS_BitFields PRS Bit Fields * @{ ******************************************************************************/ /* Bit fields for PRS SWPULSE */ #define _PRS_SWPULSE_RESETVALUE 0x00000000UL /**< Default value for PRS_SWPULSE */ #define _PRS_SWPULSE_MASK 0x00000FFFUL /**< Mask for PRS_SWPULSE */ #define PRS_SWPULSE_CH0PULSE (0x1UL << 0) /**< Channel 0 Pulse Generation */ #define _PRS_SWPULSE_CH0PULSE_SHIFT 0 /**< Shift value for PRS_CH0PULSE */ #define _PRS_SWPULSE_CH0PULSE_MASK 0x1UL /**< Bit mask for PRS_CH0PULSE */ #define _PRS_SWPULSE_CH0PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ #define PRS_SWPULSE_CH0PULSE_DEFAULT (_PRS_SWPULSE_CH0PULSE_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWPULSE */ #define PRS_SWPULSE_CH1PULSE (0x1UL << 1) /**< Channel 1 Pulse Generation */ #define _PRS_SWPULSE_CH1PULSE_SHIFT 1 /**< Shift value for PRS_CH1PULSE */ #define _PRS_SWPULSE_CH1PULSE_MASK 0x2UL /**< Bit mask for PRS_CH1PULSE */ #define _PRS_SWPULSE_CH1PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ #define PRS_SWPULSE_CH1PULSE_DEFAULT (_PRS_SWPULSE_CH1PULSE_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWPULSE */ #define PRS_SWPULSE_CH2PULSE (0x1UL << 2) /**< Channel 2 Pulse Generation */ #define _PRS_SWPULSE_CH2PULSE_SHIFT 2 /**< Shift value for PRS_CH2PULSE */ #define _PRS_SWPULSE_CH2PULSE_MASK 0x4UL /**< Bit mask for PRS_CH2PULSE */ #define _PRS_SWPULSE_CH2PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ #define PRS_SWPULSE_CH2PULSE_DEFAULT (_PRS_SWPULSE_CH2PULSE_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWPULSE */ #define PRS_SWPULSE_CH3PULSE (0x1UL << 3) /**< Channel 3 Pulse Generation */ #define _PRS_SWPULSE_CH3PULSE_SHIFT 3 /**< Shift value for PRS_CH3PULSE */ #define _PRS_SWPULSE_CH3PULSE_MASK 0x8UL /**< Bit mask for PRS_CH3PULSE */ #define _PRS_SWPULSE_CH3PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ #define PRS_SWPULSE_CH3PULSE_DEFAULT (_PRS_SWPULSE_CH3PULSE_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWPULSE */ #define PRS_SWPULSE_CH4PULSE (0x1UL << 4) /**< Channel 4 Pulse Generation */ #define _PRS_SWPULSE_CH4PULSE_SHIFT 4 /**< Shift value for PRS_CH4PULSE */ #define _PRS_SWPULSE_CH4PULSE_MASK 0x10UL /**< Bit mask for PRS_CH4PULSE */ #define _PRS_SWPULSE_CH4PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ #define PRS_SWPULSE_CH4PULSE_DEFAULT (_PRS_SWPULSE_CH4PULSE_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWPULSE */ #define PRS_SWPULSE_CH5PULSE (0x1UL << 5) /**< Channel 5 Pulse Generation */ #define _PRS_SWPULSE_CH5PULSE_SHIFT 5 /**< Shift value for PRS_CH5PULSE */ #define _PRS_SWPULSE_CH5PULSE_MASK 0x20UL /**< Bit mask for PRS_CH5PULSE */ #define _PRS_SWPULSE_CH5PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ #define PRS_SWPULSE_CH5PULSE_DEFAULT (_PRS_SWPULSE_CH5PULSE_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWPULSE */ #define PRS_SWPULSE_CH6PULSE (0x1UL << 6) /**< Channel 6 Pulse Generation */ #define _PRS_SWPULSE_CH6PULSE_SHIFT 6 /**< Shift value for PRS_CH6PULSE */ #define _PRS_SWPULSE_CH6PULSE_MASK 0x40UL /**< Bit mask for PRS_CH6PULSE */ #define _PRS_SWPULSE_CH6PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ #define PRS_SWPULSE_CH6PULSE_DEFAULT (_PRS_SWPULSE_CH6PULSE_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWPULSE */ #define PRS_SWPULSE_CH7PULSE (0x1UL << 7) /**< Channel 7 Pulse Generation */ #define _PRS_SWPULSE_CH7PULSE_SHIFT 7 /**< Shift value for PRS_CH7PULSE */ #define _PRS_SWPULSE_CH7PULSE_MASK 0x80UL /**< Bit mask for PRS_CH7PULSE */ #define _PRS_SWPULSE_CH7PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ #define PRS_SWPULSE_CH7PULSE_DEFAULT (_PRS_SWPULSE_CH7PULSE_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWPULSE */ #define PRS_SWPULSE_CH8PULSE (0x1UL << 8) /**< Channel 8 Pulse Generation */ #define _PRS_SWPULSE_CH8PULSE_SHIFT 8 /**< Shift value for PRS_CH8PULSE */ #define _PRS_SWPULSE_CH8PULSE_MASK 0x100UL /**< Bit mask for PRS_CH8PULSE */ #define _PRS_SWPULSE_CH8PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ #define PRS_SWPULSE_CH8PULSE_DEFAULT (_PRS_SWPULSE_CH8PULSE_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWPULSE */ #define PRS_SWPULSE_CH9PULSE (0x1UL << 9) /**< Channel 9 Pulse Generation */ #define _PRS_SWPULSE_CH9PULSE_SHIFT 9 /**< Shift value for PRS_CH9PULSE */ #define _PRS_SWPULSE_CH9PULSE_MASK 0x200UL /**< Bit mask for PRS_CH9PULSE */ #define _PRS_SWPULSE_CH9PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ #define PRS_SWPULSE_CH9PULSE_DEFAULT (_PRS_SWPULSE_CH9PULSE_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWPULSE */ #define PRS_SWPULSE_CH10PULSE (0x1UL << 10) /**< Channel 10 Pulse Generation */ #define _PRS_SWPULSE_CH10PULSE_SHIFT 10 /**< Shift value for PRS_CH10PULSE */ #define _PRS_SWPULSE_CH10PULSE_MASK 0x400UL /**< Bit mask for PRS_CH10PULSE */ #define _PRS_SWPULSE_CH10PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ #define PRS_SWPULSE_CH10PULSE_DEFAULT (_PRS_SWPULSE_CH10PULSE_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWPULSE */ #define PRS_SWPULSE_CH11PULSE (0x1UL << 11) /**< Channel 11 Pulse Generation */ #define _PRS_SWPULSE_CH11PULSE_SHIFT 11 /**< Shift value for PRS_CH11PULSE */ #define _PRS_SWPULSE_CH11PULSE_MASK 0x800UL /**< Bit mask for PRS_CH11PULSE */ #define _PRS_SWPULSE_CH11PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ #define PRS_SWPULSE_CH11PULSE_DEFAULT (_PRS_SWPULSE_CH11PULSE_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWPULSE */ /* Bit fields for PRS SWLEVEL */ #define _PRS_SWLEVEL_RESETVALUE 0x00000000UL /**< Default value for PRS_SWLEVEL */ #define _PRS_SWLEVEL_MASK 0x00000FFFUL /**< Mask for PRS_SWLEVEL */ #define PRS_SWLEVEL_CH0LEVEL (0x1UL << 0) /**< Channel 0 Software Level */ #define _PRS_SWLEVEL_CH0LEVEL_SHIFT 0 /**< Shift value for PRS_CH0LEVEL */ #define _PRS_SWLEVEL_CH0LEVEL_MASK 0x1UL /**< Bit mask for PRS_CH0LEVEL */ #define _PRS_SWLEVEL_CH0LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ #define PRS_SWLEVEL_CH0LEVEL_DEFAULT (_PRS_SWLEVEL_CH0LEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ #define PRS_SWLEVEL_CH1LEVEL (0x1UL << 1) /**< Channel 1 Software Level */ #define _PRS_SWLEVEL_CH1LEVEL_SHIFT 1 /**< Shift value for PRS_CH1LEVEL */ #define _PRS_SWLEVEL_CH1LEVEL_MASK 0x2UL /**< Bit mask for PRS_CH1LEVEL */ #define _PRS_SWLEVEL_CH1LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ #define PRS_SWLEVEL_CH1LEVEL_DEFAULT (_PRS_SWLEVEL_CH1LEVEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ #define PRS_SWLEVEL_CH2LEVEL (0x1UL << 2) /**< Channel 2 Software Level */ #define _PRS_SWLEVEL_CH2LEVEL_SHIFT 2 /**< Shift value for PRS_CH2LEVEL */ #define _PRS_SWLEVEL_CH2LEVEL_MASK 0x4UL /**< Bit mask for PRS_CH2LEVEL */ #define _PRS_SWLEVEL_CH2LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ #define PRS_SWLEVEL_CH2LEVEL_DEFAULT (_PRS_SWLEVEL_CH2LEVEL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ #define PRS_SWLEVEL_CH3LEVEL (0x1UL << 3) /**< Channel 3 Software Level */ #define _PRS_SWLEVEL_CH3LEVEL_SHIFT 3 /**< Shift value for PRS_CH3LEVEL */ #define _PRS_SWLEVEL_CH3LEVEL_MASK 0x8UL /**< Bit mask for PRS_CH3LEVEL */ #define _PRS_SWLEVEL_CH3LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ #define PRS_SWLEVEL_CH3LEVEL_DEFAULT (_PRS_SWLEVEL_CH3LEVEL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ #define PRS_SWLEVEL_CH4LEVEL (0x1UL << 4) /**< Channel 4 Software Level */ #define _PRS_SWLEVEL_CH4LEVEL_SHIFT 4 /**< Shift value for PRS_CH4LEVEL */ #define _PRS_SWLEVEL_CH4LEVEL_MASK 0x10UL /**< Bit mask for PRS_CH4LEVEL */ #define _PRS_SWLEVEL_CH4LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ #define PRS_SWLEVEL_CH4LEVEL_DEFAULT (_PRS_SWLEVEL_CH4LEVEL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ #define PRS_SWLEVEL_CH5LEVEL (0x1UL << 5) /**< Channel 5 Software Level */ #define _PRS_SWLEVEL_CH5LEVEL_SHIFT 5 /**< Shift value for PRS_CH5LEVEL */ #define _PRS_SWLEVEL_CH5LEVEL_MASK 0x20UL /**< Bit mask for PRS_CH5LEVEL */ #define _PRS_SWLEVEL_CH5LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ #define PRS_SWLEVEL_CH5LEVEL_DEFAULT (_PRS_SWLEVEL_CH5LEVEL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ #define PRS_SWLEVEL_CH6LEVEL (0x1UL << 6) /**< Channel 6 Software Level */ #define _PRS_SWLEVEL_CH6LEVEL_SHIFT 6 /**< Shift value for PRS_CH6LEVEL */ #define _PRS_SWLEVEL_CH6LEVEL_MASK 0x40UL /**< Bit mask for PRS_CH6LEVEL */ #define _PRS_SWLEVEL_CH6LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ #define PRS_SWLEVEL_CH6LEVEL_DEFAULT (_PRS_SWLEVEL_CH6LEVEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ #define PRS_SWLEVEL_CH7LEVEL (0x1UL << 7) /**< Channel 7 Software Level */ #define _PRS_SWLEVEL_CH7LEVEL_SHIFT 7 /**< Shift value for PRS_CH7LEVEL */ #define _PRS_SWLEVEL_CH7LEVEL_MASK 0x80UL /**< Bit mask for PRS_CH7LEVEL */ #define _PRS_SWLEVEL_CH7LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ #define PRS_SWLEVEL_CH7LEVEL_DEFAULT (_PRS_SWLEVEL_CH7LEVEL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ #define PRS_SWLEVEL_CH8LEVEL (0x1UL << 8) /**< Channel 8 Software Level */ #define _PRS_SWLEVEL_CH8LEVEL_SHIFT 8 /**< Shift value for PRS_CH8LEVEL */ #define _PRS_SWLEVEL_CH8LEVEL_MASK 0x100UL /**< Bit mask for PRS_CH8LEVEL */ #define _PRS_SWLEVEL_CH8LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ #define PRS_SWLEVEL_CH8LEVEL_DEFAULT (_PRS_SWLEVEL_CH8LEVEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ #define PRS_SWLEVEL_CH9LEVEL (0x1UL << 9) /**< Channel 9 Software Level */ #define _PRS_SWLEVEL_CH9LEVEL_SHIFT 9 /**< Shift value for PRS_CH9LEVEL */ #define _PRS_SWLEVEL_CH9LEVEL_MASK 0x200UL /**< Bit mask for PRS_CH9LEVEL */ #define _PRS_SWLEVEL_CH9LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ #define PRS_SWLEVEL_CH9LEVEL_DEFAULT (_PRS_SWLEVEL_CH9LEVEL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ #define PRS_SWLEVEL_CH10LEVEL (0x1UL << 10) /**< Channel 10 Software Level */ #define _PRS_SWLEVEL_CH10LEVEL_SHIFT 10 /**< Shift value for PRS_CH10LEVEL */ #define _PRS_SWLEVEL_CH10LEVEL_MASK 0x400UL /**< Bit mask for PRS_CH10LEVEL */ #define _PRS_SWLEVEL_CH10LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ #define PRS_SWLEVEL_CH10LEVEL_DEFAULT (_PRS_SWLEVEL_CH10LEVEL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ #define PRS_SWLEVEL_CH11LEVEL (0x1UL << 11) /**< Channel 11 Software Level */ #define _PRS_SWLEVEL_CH11LEVEL_SHIFT 11 /**< Shift value for PRS_CH11LEVEL */ #define _PRS_SWLEVEL_CH11LEVEL_MASK 0x800UL /**< Bit mask for PRS_CH11LEVEL */ #define _PRS_SWLEVEL_CH11LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ #define PRS_SWLEVEL_CH11LEVEL_DEFAULT (_PRS_SWLEVEL_CH11LEVEL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ /* Bit fields for PRS ROUTEPEN */ #define _PRS_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTEPEN */ #define _PRS_ROUTEPEN_MASK 0x00000FFFUL /**< Mask for PRS_ROUTEPEN */ #define PRS_ROUTEPEN_CH0PEN (0x1UL << 0) /**< CH0 Pin Enable */ #define _PRS_ROUTEPEN_CH0PEN_SHIFT 0 /**< Shift value for PRS_CH0PEN */ #define _PRS_ROUTEPEN_CH0PEN_MASK 0x1UL /**< Bit mask for PRS_CH0PEN */ #define _PRS_ROUTEPEN_CH0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ #define PRS_ROUTEPEN_CH0PEN_DEFAULT (_PRS_ROUTEPEN_CH0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ #define PRS_ROUTEPEN_CH1PEN (0x1UL << 1) /**< CH1 Pin Enable */ #define _PRS_ROUTEPEN_CH1PEN_SHIFT 1 /**< Shift value for PRS_CH1PEN */ #define _PRS_ROUTEPEN_CH1PEN_MASK 0x2UL /**< Bit mask for PRS_CH1PEN */ #define _PRS_ROUTEPEN_CH1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ #define PRS_ROUTEPEN_CH1PEN_DEFAULT (_PRS_ROUTEPEN_CH1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ #define PRS_ROUTEPEN_CH2PEN (0x1UL << 2) /**< CH2 Pin Enable */ #define _PRS_ROUTEPEN_CH2PEN_SHIFT 2 /**< Shift value for PRS_CH2PEN */ #define _PRS_ROUTEPEN_CH2PEN_MASK 0x4UL /**< Bit mask for PRS_CH2PEN */ #define _PRS_ROUTEPEN_CH2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ #define PRS_ROUTEPEN_CH2PEN_DEFAULT (_PRS_ROUTEPEN_CH2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ #define PRS_ROUTEPEN_CH3PEN (0x1UL << 3) /**< CH3 Pin Enable */ #define _PRS_ROUTEPEN_CH3PEN_SHIFT 3 /**< Shift value for PRS_CH3PEN */ #define _PRS_ROUTEPEN_CH3PEN_MASK 0x8UL /**< Bit mask for PRS_CH3PEN */ #define _PRS_ROUTEPEN_CH3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ #define PRS_ROUTEPEN_CH3PEN_DEFAULT (_PRS_ROUTEPEN_CH3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ #define PRS_ROUTEPEN_CH4PEN (0x1UL << 4) /**< CH4 Pin Enable */ #define _PRS_ROUTEPEN_CH4PEN_SHIFT 4 /**< Shift value for PRS_CH4PEN */ #define _PRS_ROUTEPEN_CH4PEN_MASK 0x10UL /**< Bit mask for PRS_CH4PEN */ #define _PRS_ROUTEPEN_CH4PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ #define PRS_ROUTEPEN_CH4PEN_DEFAULT (_PRS_ROUTEPEN_CH4PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ #define PRS_ROUTEPEN_CH5PEN (0x1UL << 5) /**< CH5 Pin Enable */ #define _PRS_ROUTEPEN_CH5PEN_SHIFT 5 /**< Shift value for PRS_CH5PEN */ #define _PRS_ROUTEPEN_CH5PEN_MASK 0x20UL /**< Bit mask for PRS_CH5PEN */ #define _PRS_ROUTEPEN_CH5PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ #define PRS_ROUTEPEN_CH5PEN_DEFAULT (_PRS_ROUTEPEN_CH5PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ #define PRS_ROUTEPEN_CH6PEN (0x1UL << 6) /**< CH6 Pin Enable */ #define _PRS_ROUTEPEN_CH6PEN_SHIFT 6 /**< Shift value for PRS_CH6PEN */ #define _PRS_ROUTEPEN_CH6PEN_MASK 0x40UL /**< Bit mask for PRS_CH6PEN */ #define _PRS_ROUTEPEN_CH6PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ #define PRS_ROUTEPEN_CH6PEN_DEFAULT (_PRS_ROUTEPEN_CH6PEN_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ #define PRS_ROUTEPEN_CH7PEN (0x1UL << 7) /**< CH7 Pin Enable */ #define _PRS_ROUTEPEN_CH7PEN_SHIFT 7 /**< Shift value for PRS_CH7PEN */ #define _PRS_ROUTEPEN_CH7PEN_MASK 0x80UL /**< Bit mask for PRS_CH7PEN */ #define _PRS_ROUTEPEN_CH7PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ #define PRS_ROUTEPEN_CH7PEN_DEFAULT (_PRS_ROUTEPEN_CH7PEN_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ #define PRS_ROUTEPEN_CH8PEN (0x1UL << 8) /**< CH8 Pin Enable */ #define _PRS_ROUTEPEN_CH8PEN_SHIFT 8 /**< Shift value for PRS_CH8PEN */ #define _PRS_ROUTEPEN_CH8PEN_MASK 0x100UL /**< Bit mask for PRS_CH8PEN */ #define _PRS_ROUTEPEN_CH8PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ #define PRS_ROUTEPEN_CH8PEN_DEFAULT (_PRS_ROUTEPEN_CH8PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ #define PRS_ROUTEPEN_CH9PEN (0x1UL << 9) /**< CH9 Pin Enable */ #define _PRS_ROUTEPEN_CH9PEN_SHIFT 9 /**< Shift value for PRS_CH9PEN */ #define _PRS_ROUTEPEN_CH9PEN_MASK 0x200UL /**< Bit mask for PRS_CH9PEN */ #define _PRS_ROUTEPEN_CH9PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ #define PRS_ROUTEPEN_CH9PEN_DEFAULT (_PRS_ROUTEPEN_CH9PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ #define PRS_ROUTEPEN_CH10PEN (0x1UL << 10) /**< CH10 Pin Enable */ #define _PRS_ROUTEPEN_CH10PEN_SHIFT 10 /**< Shift value for PRS_CH10PEN */ #define _PRS_ROUTEPEN_CH10PEN_MASK 0x400UL /**< Bit mask for PRS_CH10PEN */ #define _PRS_ROUTEPEN_CH10PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ #define PRS_ROUTEPEN_CH10PEN_DEFAULT (_PRS_ROUTEPEN_CH10PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ #define PRS_ROUTEPEN_CH11PEN (0x1UL << 11) /**< CH11 Pin Enable */ #define _PRS_ROUTEPEN_CH11PEN_SHIFT 11 /**< Shift value for PRS_CH11PEN */ #define _PRS_ROUTEPEN_CH11PEN_MASK 0x800UL /**< Bit mask for PRS_CH11PEN */ #define _PRS_ROUTEPEN_CH11PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ #define PRS_ROUTEPEN_CH11PEN_DEFAULT (_PRS_ROUTEPEN_CH11PEN_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ /* Bit fields for PRS ROUTELOC0 */ #define _PRS_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC0 */ #define _PRS_ROUTELOC0_MASK 0x0F07070FUL /**< Mask for PRS_ROUTELOC0 */ #define _PRS_ROUTELOC0_CH0LOC_SHIFT 0 /**< Shift value for PRS_CH0LOC */ #define _PRS_ROUTELOC0_CH0LOC_MASK 0xFUL /**< Bit mask for PRS_CH0LOC */ #define _PRS_ROUTELOC0_CH0LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ #define _PRS_ROUTELOC0_CH0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ #define _PRS_ROUTELOC0_CH0LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ #define _PRS_ROUTELOC0_CH0LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ #define _PRS_ROUTELOC0_CH0LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ #define _PRS_ROUTELOC0_CH0LOC_LOC4 0x00000004UL /**< Mode LOC4 for PRS_ROUTELOC0 */ #define _PRS_ROUTELOC0_CH0LOC_LOC5 0x00000005UL /**< Mode LOC5 for PRS_ROUTELOC0 */ #define _PRS_ROUTELOC0_CH0LOC_LOC6 0x00000006UL /**< Mode LOC6 for PRS_ROUTELOC0 */ #define _PRS_ROUTELOC0_CH0LOC_LOC7 0x00000007UL /**< Mode LOC7 for PRS_ROUTELOC0 */ #define _PRS_ROUTELOC0_CH0LOC_LOC8 0x00000008UL /**< Mode LOC8 for PRS_ROUTELOC0 */ #define _PRS_ROUTELOC0_CH0LOC_LOC9 0x00000009UL /**< Mode LOC9 for PRS_ROUTELOC0 */ #define _PRS_ROUTELOC0_CH0LOC_LOC10 0x0000000AUL /**< Mode LOC10 for PRS_ROUTELOC0 */ #define _PRS_ROUTELOC0_CH0LOC_LOC11 0x0000000BUL /**< Mode LOC11 for PRS_ROUTELOC0 */ #define _PRS_ROUTELOC0_CH0LOC_LOC12 0x0000000CUL /**< Mode LOC12 for PRS_ROUTELOC0 */ #define _PRS_ROUTELOC0_CH0LOC_LOC13 0x0000000DUL /**< Mode LOC13 for PRS_ROUTELOC0 */ #define PRS_ROUTELOC0_CH0LOC_LOC0 (_PRS_ROUTELOC0_CH0LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ #define PRS_ROUTELOC0_CH0LOC_DEFAULT (_PRS_ROUTELOC0_CH0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ #define PRS_ROUTELOC0_CH0LOC_LOC1 (_PRS_ROUTELOC0_CH0LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ #define PRS_ROUTELOC0_CH0LOC_LOC2 (_PRS_ROUTELOC0_CH0LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ #define PRS_ROUTELOC0_CH0LOC_LOC3 (_PRS_ROUTELOC0_CH0LOC_LOC3 << 0) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ #define PRS_ROUTELOC0_CH0LOC_LOC4 (_PRS_ROUTELOC0_CH0LOC_LOC4 << 0) /**< Shifted mode LOC4 for PRS_ROUTELOC0 */ #define PRS_ROUTELOC0_CH0LOC_LOC5 (_PRS_ROUTELOC0_CH0LOC_LOC5 << 0) /**< Shifted mode LOC5 for PRS_ROUTELOC0 */ #define PRS_ROUTELOC0_CH0LOC_LOC6 (_PRS_ROUTELOC0_CH0LOC_LOC6 << 0) /**< Shifted mode LOC6 for PRS_ROUTELOC0 */ #define PRS_ROUTELOC0_CH0LOC_LOC7 (_PRS_ROUTELOC0_CH0LOC_LOC7 << 0) /**< Shifted mode LOC7 for PRS_ROUTELOC0 */ #define PRS_ROUTELOC0_CH0LOC_LOC8 (_PRS_ROUTELOC0_CH0LOC_LOC8 << 0) /**< Shifted mode LOC8 for PRS_ROUTELOC0 */ #define PRS_ROUTELOC0_CH0LOC_LOC9 (_PRS_ROUTELOC0_CH0LOC_LOC9 << 0) /**< Shifted mode LOC9 for PRS_ROUTELOC0 */ #define PRS_ROUTELOC0_CH0LOC_LOC10 (_PRS_ROUTELOC0_CH0LOC_LOC10 << 0) /**< Shifted mode LOC10 for PRS_ROUTELOC0 */ #define PRS_ROUTELOC0_CH0LOC_LOC11 (_PRS_ROUTELOC0_CH0LOC_LOC11 << 0) /**< Shifted mode LOC11 for PRS_ROUTELOC0 */ #define PRS_ROUTELOC0_CH0LOC_LOC12 (_PRS_ROUTELOC0_CH0LOC_LOC12 << 0) /**< Shifted mode LOC12 for PRS_ROUTELOC0 */ #define PRS_ROUTELOC0_CH0LOC_LOC13 (_PRS_ROUTELOC0_CH0LOC_LOC13 << 0) /**< Shifted mode LOC13 for PRS_ROUTELOC0 */ #define _PRS_ROUTELOC0_CH1LOC_SHIFT 8 /**< Shift value for PRS_CH1LOC */ #define _PRS_ROUTELOC0_CH1LOC_MASK 0x700UL /**< Bit mask for PRS_CH1LOC */ #define _PRS_ROUTELOC0_CH1LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ #define _PRS_ROUTELOC0_CH1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ #define _PRS_ROUTELOC0_CH1LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ #define _PRS_ROUTELOC0_CH1LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ #define _PRS_ROUTELOC0_CH1LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ #define _PRS_ROUTELOC0_CH1LOC_LOC4 0x00000004UL /**< Mode LOC4 for PRS_ROUTELOC0 */ #define _PRS_ROUTELOC0_CH1LOC_LOC5 0x00000005UL /**< Mode LOC5 for PRS_ROUTELOC0 */ #define _PRS_ROUTELOC0_CH1LOC_LOC6 0x00000006UL /**< Mode LOC6 for PRS_ROUTELOC0 */ #define _PRS_ROUTELOC0_CH1LOC_LOC7 0x00000007UL /**< Mode LOC7 for PRS_ROUTELOC0 */ #define PRS_ROUTELOC0_CH1LOC_LOC0 (_PRS_ROUTELOC0_CH1LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ #define PRS_ROUTELOC0_CH1LOC_DEFAULT (_PRS_ROUTELOC0_CH1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ #define PRS_ROUTELOC0_CH1LOC_LOC1 (_PRS_ROUTELOC0_CH1LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ #define PRS_ROUTELOC0_CH1LOC_LOC2 (_PRS_ROUTELOC0_CH1LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ #define PRS_ROUTELOC0_CH1LOC_LOC3 (_PRS_ROUTELOC0_CH1LOC_LOC3 << 8) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ #define PRS_ROUTELOC0_CH1LOC_LOC4 (_PRS_ROUTELOC0_CH1LOC_LOC4 << 8) /**< Shifted mode LOC4 for PRS_ROUTELOC0 */ #define PRS_ROUTELOC0_CH1LOC_LOC5 (_PRS_ROUTELOC0_CH1LOC_LOC5 << 8) /**< Shifted mode LOC5 for PRS_ROUTELOC0 */ #define PRS_ROUTELOC0_CH1LOC_LOC6 (_PRS_ROUTELOC0_CH1LOC_LOC6 << 8) /**< Shifted mode LOC6 for PRS_ROUTELOC0 */ #define PRS_ROUTELOC0_CH1LOC_LOC7 (_PRS_ROUTELOC0_CH1LOC_LOC7 << 8) /**< Shifted mode LOC7 for PRS_ROUTELOC0 */ #define _PRS_ROUTELOC0_CH2LOC_SHIFT 16 /**< Shift value for PRS_CH2LOC */ #define _PRS_ROUTELOC0_CH2LOC_MASK 0x70000UL /**< Bit mask for PRS_CH2LOC */ #define _PRS_ROUTELOC0_CH2LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ #define _PRS_ROUTELOC0_CH2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ #define _PRS_ROUTELOC0_CH2LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ #define _PRS_ROUTELOC0_CH2LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ #define _PRS_ROUTELOC0_CH2LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ #define _PRS_ROUTELOC0_CH2LOC_LOC4 0x00000004UL /**< Mode LOC4 for PRS_ROUTELOC0 */ #define _PRS_ROUTELOC0_CH2LOC_LOC5 0x00000005UL /**< Mode LOC5 for PRS_ROUTELOC0 */ #define _PRS_ROUTELOC0_CH2LOC_LOC6 0x00000006UL /**< Mode LOC6 for PRS_ROUTELOC0 */ #define _PRS_ROUTELOC0_CH2LOC_LOC7 0x00000007UL /**< Mode LOC7 for PRS_ROUTELOC0 */ #define PRS_ROUTELOC0_CH2LOC_LOC0 (_PRS_ROUTELOC0_CH2LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ #define PRS_ROUTELOC0_CH2LOC_DEFAULT (_PRS_ROUTELOC0_CH2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ #define PRS_ROUTELOC0_CH2LOC_LOC1 (_PRS_ROUTELOC0_CH2LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ #define PRS_ROUTELOC0_CH2LOC_LOC2 (_PRS_ROUTELOC0_CH2LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ #define PRS_ROUTELOC0_CH2LOC_LOC3 (_PRS_ROUTELOC0_CH2LOC_LOC3 << 16) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ #define PRS_ROUTELOC0_CH2LOC_LOC4 (_PRS_ROUTELOC0_CH2LOC_LOC4 << 16) /**< Shifted mode LOC4 for PRS_ROUTELOC0 */ #define PRS_ROUTELOC0_CH2LOC_LOC5 (_PRS_ROUTELOC0_CH2LOC_LOC5 << 16) /**< Shifted mode LOC5 for PRS_ROUTELOC0 */ #define PRS_ROUTELOC0_CH2LOC_LOC6 (_PRS_ROUTELOC0_CH2LOC_LOC6 << 16) /**< Shifted mode LOC6 for PRS_ROUTELOC0 */ #define PRS_ROUTELOC0_CH2LOC_LOC7 (_PRS_ROUTELOC0_CH2LOC_LOC7 << 16) /**< Shifted mode LOC7 for PRS_ROUTELOC0 */ #define _PRS_ROUTELOC0_CH3LOC_SHIFT 24 /**< Shift value for PRS_CH3LOC */ #define _PRS_ROUTELOC0_CH3LOC_MASK 0xF000000UL /**< Bit mask for PRS_CH3LOC */ #define _PRS_ROUTELOC0_CH3LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ #define _PRS_ROUTELOC0_CH3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ #define _PRS_ROUTELOC0_CH3LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ #define _PRS_ROUTELOC0_CH3LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ #define _PRS_ROUTELOC0_CH3LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ #define _PRS_ROUTELOC0_CH3LOC_LOC4 0x00000004UL /**< Mode LOC4 for PRS_ROUTELOC0 */ #define _PRS_ROUTELOC0_CH3LOC_LOC5 0x00000005UL /**< Mode LOC5 for PRS_ROUTELOC0 */ #define _PRS_ROUTELOC0_CH3LOC_LOC6 0x00000006UL /**< Mode LOC6 for PRS_ROUTELOC0 */ #define _PRS_ROUTELOC0_CH3LOC_LOC7 0x00000007UL /**< Mode LOC7 for PRS_ROUTELOC0 */ #define _PRS_ROUTELOC0_CH3LOC_LOC8 0x00000008UL /**< Mode LOC8 for PRS_ROUTELOC0 */ #define _PRS_ROUTELOC0_CH3LOC_LOC9 0x00000009UL /**< Mode LOC9 for PRS_ROUTELOC0 */ #define _PRS_ROUTELOC0_CH3LOC_LOC10 0x0000000AUL /**< Mode LOC10 for PRS_ROUTELOC0 */ #define _PRS_ROUTELOC0_CH3LOC_LOC11 0x0000000BUL /**< Mode LOC11 for PRS_ROUTELOC0 */ #define _PRS_ROUTELOC0_CH3LOC_LOC12 0x0000000CUL /**< Mode LOC12 for PRS_ROUTELOC0 */ #define _PRS_ROUTELOC0_CH3LOC_LOC13 0x0000000DUL /**< Mode LOC13 for PRS_ROUTELOC0 */ #define _PRS_ROUTELOC0_CH3LOC_LOC14 0x0000000EUL /**< Mode LOC14 for PRS_ROUTELOC0 */ #define PRS_ROUTELOC0_CH3LOC_LOC0 (_PRS_ROUTELOC0_CH3LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ #define PRS_ROUTELOC0_CH3LOC_DEFAULT (_PRS_ROUTELOC0_CH3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ #define PRS_ROUTELOC0_CH3LOC_LOC1 (_PRS_ROUTELOC0_CH3LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ #define PRS_ROUTELOC0_CH3LOC_LOC2 (_PRS_ROUTELOC0_CH3LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ #define PRS_ROUTELOC0_CH3LOC_LOC3 (_PRS_ROUTELOC0_CH3LOC_LOC3 << 24) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ #define PRS_ROUTELOC0_CH3LOC_LOC4 (_PRS_ROUTELOC0_CH3LOC_LOC4 << 24) /**< Shifted mode LOC4 for PRS_ROUTELOC0 */ #define PRS_ROUTELOC0_CH3LOC_LOC5 (_PRS_ROUTELOC0_CH3LOC_LOC5 << 24) /**< Shifted mode LOC5 for PRS_ROUTELOC0 */ #define PRS_ROUTELOC0_CH3LOC_LOC6 (_PRS_ROUTELOC0_CH3LOC_LOC6 << 24) /**< Shifted mode LOC6 for PRS_ROUTELOC0 */ #define PRS_ROUTELOC0_CH3LOC_LOC7 (_PRS_ROUTELOC0_CH3LOC_LOC7 << 24) /**< Shifted mode LOC7 for PRS_ROUTELOC0 */ #define PRS_ROUTELOC0_CH3LOC_LOC8 (_PRS_ROUTELOC0_CH3LOC_LOC8 << 24) /**< Shifted mode LOC8 for PRS_ROUTELOC0 */ #define PRS_ROUTELOC0_CH3LOC_LOC9 (_PRS_ROUTELOC0_CH3LOC_LOC9 << 24) /**< Shifted mode LOC9 for PRS_ROUTELOC0 */ #define PRS_ROUTELOC0_CH3LOC_LOC10 (_PRS_ROUTELOC0_CH3LOC_LOC10 << 24) /**< Shifted mode LOC10 for PRS_ROUTELOC0 */ #define PRS_ROUTELOC0_CH3LOC_LOC11 (_PRS_ROUTELOC0_CH3LOC_LOC11 << 24) /**< Shifted mode LOC11 for PRS_ROUTELOC0 */ #define PRS_ROUTELOC0_CH3LOC_LOC12 (_PRS_ROUTELOC0_CH3LOC_LOC12 << 24) /**< Shifted mode LOC12 for PRS_ROUTELOC0 */ #define PRS_ROUTELOC0_CH3LOC_LOC13 (_PRS_ROUTELOC0_CH3LOC_LOC13 << 24) /**< Shifted mode LOC13 for PRS_ROUTELOC0 */ #define PRS_ROUTELOC0_CH3LOC_LOC14 (_PRS_ROUTELOC0_CH3LOC_LOC14 << 24) /**< Shifted mode LOC14 for PRS_ROUTELOC0 */ /* Bit fields for PRS ROUTELOC1 */ #define _PRS_ROUTELOC1_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC1 */ #define _PRS_ROUTELOC1_MASK 0x0F1F0707UL /**< Mask for PRS_ROUTELOC1 */ #define _PRS_ROUTELOC1_CH4LOC_SHIFT 0 /**< Shift value for PRS_CH4LOC */ #define _PRS_ROUTELOC1_CH4LOC_MASK 0x7UL /**< Bit mask for PRS_CH4LOC */ #define _PRS_ROUTELOC1_CH4LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ #define _PRS_ROUTELOC1_CH4LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ #define _PRS_ROUTELOC1_CH4LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ #define _PRS_ROUTELOC1_CH4LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ #define _PRS_ROUTELOC1_CH4LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC1 */ #define _PRS_ROUTELOC1_CH4LOC_LOC4 0x00000004UL /**< Mode LOC4 for PRS_ROUTELOC1 */ #define _PRS_ROUTELOC1_CH4LOC_LOC5 0x00000005UL /**< Mode LOC5 for PRS_ROUTELOC1 */ #define _PRS_ROUTELOC1_CH4LOC_LOC6 0x00000006UL /**< Mode LOC6 for PRS_ROUTELOC1 */ #define PRS_ROUTELOC1_CH4LOC_LOC0 (_PRS_ROUTELOC1_CH4LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ #define PRS_ROUTELOC1_CH4LOC_DEFAULT (_PRS_ROUTELOC1_CH4LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ #define PRS_ROUTELOC1_CH4LOC_LOC1 (_PRS_ROUTELOC1_CH4LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ #define PRS_ROUTELOC1_CH4LOC_LOC2 (_PRS_ROUTELOC1_CH4LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ #define PRS_ROUTELOC1_CH4LOC_LOC3 (_PRS_ROUTELOC1_CH4LOC_LOC3 << 0) /**< Shifted mode LOC3 for PRS_ROUTELOC1 */ #define PRS_ROUTELOC1_CH4LOC_LOC4 (_PRS_ROUTELOC1_CH4LOC_LOC4 << 0) /**< Shifted mode LOC4 for PRS_ROUTELOC1 */ #define PRS_ROUTELOC1_CH4LOC_LOC5 (_PRS_ROUTELOC1_CH4LOC_LOC5 << 0) /**< Shifted mode LOC5 for PRS_ROUTELOC1 */ #define PRS_ROUTELOC1_CH4LOC_LOC6 (_PRS_ROUTELOC1_CH4LOC_LOC6 << 0) /**< Shifted mode LOC6 for PRS_ROUTELOC1 */ #define _PRS_ROUTELOC1_CH5LOC_SHIFT 8 /**< Shift value for PRS_CH5LOC */ #define _PRS_ROUTELOC1_CH5LOC_MASK 0x700UL /**< Bit mask for PRS_CH5LOC */ #define _PRS_ROUTELOC1_CH5LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ #define _PRS_ROUTELOC1_CH5LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ #define _PRS_ROUTELOC1_CH5LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ #define _PRS_ROUTELOC1_CH5LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ #define _PRS_ROUTELOC1_CH5LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC1 */ #define _PRS_ROUTELOC1_CH5LOC_LOC4 0x00000004UL /**< Mode LOC4 for PRS_ROUTELOC1 */ #define _PRS_ROUTELOC1_CH5LOC_LOC5 0x00000005UL /**< Mode LOC5 for PRS_ROUTELOC1 */ #define _PRS_ROUTELOC1_CH5LOC_LOC6 0x00000006UL /**< Mode LOC6 for PRS_ROUTELOC1 */ #define PRS_ROUTELOC1_CH5LOC_LOC0 (_PRS_ROUTELOC1_CH5LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ #define PRS_ROUTELOC1_CH5LOC_DEFAULT (_PRS_ROUTELOC1_CH5LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ #define PRS_ROUTELOC1_CH5LOC_LOC1 (_PRS_ROUTELOC1_CH5LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ #define PRS_ROUTELOC1_CH5LOC_LOC2 (_PRS_ROUTELOC1_CH5LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ #define PRS_ROUTELOC1_CH5LOC_LOC3 (_PRS_ROUTELOC1_CH5LOC_LOC3 << 8) /**< Shifted mode LOC3 for PRS_ROUTELOC1 */ #define PRS_ROUTELOC1_CH5LOC_LOC4 (_PRS_ROUTELOC1_CH5LOC_LOC4 << 8) /**< Shifted mode LOC4 for PRS_ROUTELOC1 */ #define PRS_ROUTELOC1_CH5LOC_LOC5 (_PRS_ROUTELOC1_CH5LOC_LOC5 << 8) /**< Shifted mode LOC5 for PRS_ROUTELOC1 */ #define PRS_ROUTELOC1_CH5LOC_LOC6 (_PRS_ROUTELOC1_CH5LOC_LOC6 << 8) /**< Shifted mode LOC6 for PRS_ROUTELOC1 */ #define _PRS_ROUTELOC1_CH6LOC_SHIFT 16 /**< Shift value for PRS_CH6LOC */ #define _PRS_ROUTELOC1_CH6LOC_MASK 0x1F0000UL /**< Bit mask for PRS_CH6LOC */ #define _PRS_ROUTELOC1_CH6LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ #define _PRS_ROUTELOC1_CH6LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ #define _PRS_ROUTELOC1_CH6LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ #define _PRS_ROUTELOC1_CH6LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ #define _PRS_ROUTELOC1_CH6LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC1 */ #define _PRS_ROUTELOC1_CH6LOC_LOC4 0x00000004UL /**< Mode LOC4 for PRS_ROUTELOC1 */ #define _PRS_ROUTELOC1_CH6LOC_LOC5 0x00000005UL /**< Mode LOC5 for PRS_ROUTELOC1 */ #define _PRS_ROUTELOC1_CH6LOC_LOC6 0x00000006UL /**< Mode LOC6 for PRS_ROUTELOC1 */ #define _PRS_ROUTELOC1_CH6LOC_LOC7 0x00000007UL /**< Mode LOC7 for PRS_ROUTELOC1 */ #define _PRS_ROUTELOC1_CH6LOC_LOC8 0x00000008UL /**< Mode LOC8 for PRS_ROUTELOC1 */ #define _PRS_ROUTELOC1_CH6LOC_LOC9 0x00000009UL /**< Mode LOC9 for PRS_ROUTELOC1 */ #define _PRS_ROUTELOC1_CH6LOC_LOC10 0x0000000AUL /**< Mode LOC10 for PRS_ROUTELOC1 */ #define _PRS_ROUTELOC1_CH6LOC_LOC11 0x0000000BUL /**< Mode LOC11 for PRS_ROUTELOC1 */ #define _PRS_ROUTELOC1_CH6LOC_LOC12 0x0000000CUL /**< Mode LOC12 for PRS_ROUTELOC1 */ #define _PRS_ROUTELOC1_CH6LOC_LOC13 0x0000000DUL /**< Mode LOC13 for PRS_ROUTELOC1 */ #define _PRS_ROUTELOC1_CH6LOC_LOC14 0x0000000EUL /**< Mode LOC14 for PRS_ROUTELOC1 */ #define _PRS_ROUTELOC1_CH6LOC_LOC15 0x0000000FUL /**< Mode LOC15 for PRS_ROUTELOC1 */ #define _PRS_ROUTELOC1_CH6LOC_LOC16 0x00000010UL /**< Mode LOC16 for PRS_ROUTELOC1 */ #define _PRS_ROUTELOC1_CH6LOC_LOC17 0x00000011UL /**< Mode LOC17 for PRS_ROUTELOC1 */ #define PRS_ROUTELOC1_CH6LOC_LOC0 (_PRS_ROUTELOC1_CH6LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ #define PRS_ROUTELOC1_CH6LOC_DEFAULT (_PRS_ROUTELOC1_CH6LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ #define PRS_ROUTELOC1_CH6LOC_LOC1 (_PRS_ROUTELOC1_CH6LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ #define PRS_ROUTELOC1_CH6LOC_LOC2 (_PRS_ROUTELOC1_CH6LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ #define PRS_ROUTELOC1_CH6LOC_LOC3 (_PRS_ROUTELOC1_CH6LOC_LOC3 << 16) /**< Shifted mode LOC3 for PRS_ROUTELOC1 */ #define PRS_ROUTELOC1_CH6LOC_LOC4 (_PRS_ROUTELOC1_CH6LOC_LOC4 << 16) /**< Shifted mode LOC4 for PRS_ROUTELOC1 */ #define PRS_ROUTELOC1_CH6LOC_LOC5 (_PRS_ROUTELOC1_CH6LOC_LOC5 << 16) /**< Shifted mode LOC5 for PRS_ROUTELOC1 */ #define PRS_ROUTELOC1_CH6LOC_LOC6 (_PRS_ROUTELOC1_CH6LOC_LOC6 << 16) /**< Shifted mode LOC6 for PRS_ROUTELOC1 */ #define PRS_ROUTELOC1_CH6LOC_LOC7 (_PRS_ROUTELOC1_CH6LOC_LOC7 << 16) /**< Shifted mode LOC7 for PRS_ROUTELOC1 */ #define PRS_ROUTELOC1_CH6LOC_LOC8 (_PRS_ROUTELOC1_CH6LOC_LOC8 << 16) /**< Shifted mode LOC8 for PRS_ROUTELOC1 */ #define PRS_ROUTELOC1_CH6LOC_LOC9 (_PRS_ROUTELOC1_CH6LOC_LOC9 << 16) /**< Shifted mode LOC9 for PRS_ROUTELOC1 */ #define PRS_ROUTELOC1_CH6LOC_LOC10 (_PRS_ROUTELOC1_CH6LOC_LOC10 << 16) /**< Shifted mode LOC10 for PRS_ROUTELOC1 */ #define PRS_ROUTELOC1_CH6LOC_LOC11 (_PRS_ROUTELOC1_CH6LOC_LOC11 << 16) /**< Shifted mode LOC11 for PRS_ROUTELOC1 */ #define PRS_ROUTELOC1_CH6LOC_LOC12 (_PRS_ROUTELOC1_CH6LOC_LOC12 << 16) /**< Shifted mode LOC12 for PRS_ROUTELOC1 */ #define PRS_ROUTELOC1_CH6LOC_LOC13 (_PRS_ROUTELOC1_CH6LOC_LOC13 << 16) /**< Shifted mode LOC13 for PRS_ROUTELOC1 */ #define PRS_ROUTELOC1_CH6LOC_LOC14 (_PRS_ROUTELOC1_CH6LOC_LOC14 << 16) /**< Shifted mode LOC14 for PRS_ROUTELOC1 */ #define PRS_ROUTELOC1_CH6LOC_LOC15 (_PRS_ROUTELOC1_CH6LOC_LOC15 << 16) /**< Shifted mode LOC15 for PRS_ROUTELOC1 */ #define PRS_ROUTELOC1_CH6LOC_LOC16 (_PRS_ROUTELOC1_CH6LOC_LOC16 << 16) /**< Shifted mode LOC16 for PRS_ROUTELOC1 */ #define PRS_ROUTELOC1_CH6LOC_LOC17 (_PRS_ROUTELOC1_CH6LOC_LOC17 << 16) /**< Shifted mode LOC17 for PRS_ROUTELOC1 */ #define _PRS_ROUTELOC1_CH7LOC_SHIFT 24 /**< Shift value for PRS_CH7LOC */ #define _PRS_ROUTELOC1_CH7LOC_MASK 0xF000000UL /**< Bit mask for PRS_CH7LOC */ #define _PRS_ROUTELOC1_CH7LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ #define _PRS_ROUTELOC1_CH7LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ #define _PRS_ROUTELOC1_CH7LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ #define _PRS_ROUTELOC1_CH7LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ #define _PRS_ROUTELOC1_CH7LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC1 */ #define _PRS_ROUTELOC1_CH7LOC_LOC4 0x00000004UL /**< Mode LOC4 for PRS_ROUTELOC1 */ #define _PRS_ROUTELOC1_CH7LOC_LOC5 0x00000005UL /**< Mode LOC5 for PRS_ROUTELOC1 */ #define _PRS_ROUTELOC1_CH7LOC_LOC6 0x00000006UL /**< Mode LOC6 for PRS_ROUTELOC1 */ #define _PRS_ROUTELOC1_CH7LOC_LOC7 0x00000007UL /**< Mode LOC7 for PRS_ROUTELOC1 */ #define _PRS_ROUTELOC1_CH7LOC_LOC8 0x00000008UL /**< Mode LOC8 for PRS_ROUTELOC1 */ #define _PRS_ROUTELOC1_CH7LOC_LOC9 0x00000009UL /**< Mode LOC9 for PRS_ROUTELOC1 */ #define _PRS_ROUTELOC1_CH7LOC_LOC10 0x0000000AUL /**< Mode LOC10 for PRS_ROUTELOC1 */ #define PRS_ROUTELOC1_CH7LOC_LOC0 (_PRS_ROUTELOC1_CH7LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ #define PRS_ROUTELOC1_CH7LOC_DEFAULT (_PRS_ROUTELOC1_CH7LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ #define PRS_ROUTELOC1_CH7LOC_LOC1 (_PRS_ROUTELOC1_CH7LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ #define PRS_ROUTELOC1_CH7LOC_LOC2 (_PRS_ROUTELOC1_CH7LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ #define PRS_ROUTELOC1_CH7LOC_LOC3 (_PRS_ROUTELOC1_CH7LOC_LOC3 << 24) /**< Shifted mode LOC3 for PRS_ROUTELOC1 */ #define PRS_ROUTELOC1_CH7LOC_LOC4 (_PRS_ROUTELOC1_CH7LOC_LOC4 << 24) /**< Shifted mode LOC4 for PRS_ROUTELOC1 */ #define PRS_ROUTELOC1_CH7LOC_LOC5 (_PRS_ROUTELOC1_CH7LOC_LOC5 << 24) /**< Shifted mode LOC5 for PRS_ROUTELOC1 */ #define PRS_ROUTELOC1_CH7LOC_LOC6 (_PRS_ROUTELOC1_CH7LOC_LOC6 << 24) /**< Shifted mode LOC6 for PRS_ROUTELOC1 */ #define PRS_ROUTELOC1_CH7LOC_LOC7 (_PRS_ROUTELOC1_CH7LOC_LOC7 << 24) /**< Shifted mode LOC7 for PRS_ROUTELOC1 */ #define PRS_ROUTELOC1_CH7LOC_LOC8 (_PRS_ROUTELOC1_CH7LOC_LOC8 << 24) /**< Shifted mode LOC8 for PRS_ROUTELOC1 */ #define PRS_ROUTELOC1_CH7LOC_LOC9 (_PRS_ROUTELOC1_CH7LOC_LOC9 << 24) /**< Shifted mode LOC9 for PRS_ROUTELOC1 */ #define PRS_ROUTELOC1_CH7LOC_LOC10 (_PRS_ROUTELOC1_CH7LOC_LOC10 << 24) /**< Shifted mode LOC10 for PRS_ROUTELOC1 */ /* Bit fields for PRS ROUTELOC2 */ #define _PRS_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC2 */ #define _PRS_ROUTELOC2_MASK 0x07071F0FUL /**< Mask for PRS_ROUTELOC2 */ #define _PRS_ROUTELOC2_CH8LOC_SHIFT 0 /**< Shift value for PRS_CH8LOC */ #define _PRS_ROUTELOC2_CH8LOC_MASK 0xFUL /**< Bit mask for PRS_CH8LOC */ #define _PRS_ROUTELOC2_CH8LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ #define _PRS_ROUTELOC2_CH8LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ #define _PRS_ROUTELOC2_CH8LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ #define _PRS_ROUTELOC2_CH8LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ #define _PRS_ROUTELOC2_CH8LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC2 */ #define _PRS_ROUTELOC2_CH8LOC_LOC4 0x00000004UL /**< Mode LOC4 for PRS_ROUTELOC2 */ #define _PRS_ROUTELOC2_CH8LOC_LOC5 0x00000005UL /**< Mode LOC5 for PRS_ROUTELOC2 */ #define _PRS_ROUTELOC2_CH8LOC_LOC6 0x00000006UL /**< Mode LOC6 for PRS_ROUTELOC2 */ #define _PRS_ROUTELOC2_CH8LOC_LOC7 0x00000007UL /**< Mode LOC7 for PRS_ROUTELOC2 */ #define _PRS_ROUTELOC2_CH8LOC_LOC8 0x00000008UL /**< Mode LOC8 for PRS_ROUTELOC2 */ #define _PRS_ROUTELOC2_CH8LOC_LOC9 0x00000009UL /**< Mode LOC9 for PRS_ROUTELOC2 */ #define _PRS_ROUTELOC2_CH8LOC_LOC10 0x0000000AUL /**< Mode LOC10 for PRS_ROUTELOC2 */ #define PRS_ROUTELOC2_CH8LOC_LOC0 (_PRS_ROUTELOC2_CH8LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ #define PRS_ROUTELOC2_CH8LOC_DEFAULT (_PRS_ROUTELOC2_CH8LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ #define PRS_ROUTELOC2_CH8LOC_LOC1 (_PRS_ROUTELOC2_CH8LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ #define PRS_ROUTELOC2_CH8LOC_LOC2 (_PRS_ROUTELOC2_CH8LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ #define PRS_ROUTELOC2_CH8LOC_LOC3 (_PRS_ROUTELOC2_CH8LOC_LOC3 << 0) /**< Shifted mode LOC3 for PRS_ROUTELOC2 */ #define PRS_ROUTELOC2_CH8LOC_LOC4 (_PRS_ROUTELOC2_CH8LOC_LOC4 << 0) /**< Shifted mode LOC4 for PRS_ROUTELOC2 */ #define PRS_ROUTELOC2_CH8LOC_LOC5 (_PRS_ROUTELOC2_CH8LOC_LOC5 << 0) /**< Shifted mode LOC5 for PRS_ROUTELOC2 */ #define PRS_ROUTELOC2_CH8LOC_LOC6 (_PRS_ROUTELOC2_CH8LOC_LOC6 << 0) /**< Shifted mode LOC6 for PRS_ROUTELOC2 */ #define PRS_ROUTELOC2_CH8LOC_LOC7 (_PRS_ROUTELOC2_CH8LOC_LOC7 << 0) /**< Shifted mode LOC7 for PRS_ROUTELOC2 */ #define PRS_ROUTELOC2_CH8LOC_LOC8 (_PRS_ROUTELOC2_CH8LOC_LOC8 << 0) /**< Shifted mode LOC8 for PRS_ROUTELOC2 */ #define PRS_ROUTELOC2_CH8LOC_LOC9 (_PRS_ROUTELOC2_CH8LOC_LOC9 << 0) /**< Shifted mode LOC9 for PRS_ROUTELOC2 */ #define PRS_ROUTELOC2_CH8LOC_LOC10 (_PRS_ROUTELOC2_CH8LOC_LOC10 << 0) /**< Shifted mode LOC10 for PRS_ROUTELOC2 */ #define _PRS_ROUTELOC2_CH9LOC_SHIFT 8 /**< Shift value for PRS_CH9LOC */ #define _PRS_ROUTELOC2_CH9LOC_MASK 0x1F00UL /**< Bit mask for PRS_CH9LOC */ #define _PRS_ROUTELOC2_CH9LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ #define _PRS_ROUTELOC2_CH9LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ #define _PRS_ROUTELOC2_CH9LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ #define _PRS_ROUTELOC2_CH9LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ #define _PRS_ROUTELOC2_CH9LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC2 */ #define _PRS_ROUTELOC2_CH9LOC_LOC4 0x00000004UL /**< Mode LOC4 for PRS_ROUTELOC2 */ #define _PRS_ROUTELOC2_CH9LOC_LOC5 0x00000005UL /**< Mode LOC5 for PRS_ROUTELOC2 */ #define _PRS_ROUTELOC2_CH9LOC_LOC6 0x00000006UL /**< Mode LOC6 for PRS_ROUTELOC2 */ #define _PRS_ROUTELOC2_CH9LOC_LOC7 0x00000007UL /**< Mode LOC7 for PRS_ROUTELOC2 */ #define _PRS_ROUTELOC2_CH9LOC_LOC8 0x00000008UL /**< Mode LOC8 for PRS_ROUTELOC2 */ #define _PRS_ROUTELOC2_CH9LOC_LOC9 0x00000009UL /**< Mode LOC9 for PRS_ROUTELOC2 */ #define _PRS_ROUTELOC2_CH9LOC_LOC10 0x0000000AUL /**< Mode LOC10 for PRS_ROUTELOC2 */ #define _PRS_ROUTELOC2_CH9LOC_LOC11 0x0000000BUL /**< Mode LOC11 for PRS_ROUTELOC2 */ #define _PRS_ROUTELOC2_CH9LOC_LOC12 0x0000000CUL /**< Mode LOC12 for PRS_ROUTELOC2 */ #define _PRS_ROUTELOC2_CH9LOC_LOC13 0x0000000DUL /**< Mode LOC13 for PRS_ROUTELOC2 */ #define _PRS_ROUTELOC2_CH9LOC_LOC14 0x0000000EUL /**< Mode LOC14 for PRS_ROUTELOC2 */ #define _PRS_ROUTELOC2_CH9LOC_LOC15 0x0000000FUL /**< Mode LOC15 for PRS_ROUTELOC2 */ #define _PRS_ROUTELOC2_CH9LOC_LOC16 0x00000010UL /**< Mode LOC16 for PRS_ROUTELOC2 */ #define PRS_ROUTELOC2_CH9LOC_LOC0 (_PRS_ROUTELOC2_CH9LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ #define PRS_ROUTELOC2_CH9LOC_DEFAULT (_PRS_ROUTELOC2_CH9LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ #define PRS_ROUTELOC2_CH9LOC_LOC1 (_PRS_ROUTELOC2_CH9LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ #define PRS_ROUTELOC2_CH9LOC_LOC2 (_PRS_ROUTELOC2_CH9LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ #define PRS_ROUTELOC2_CH9LOC_LOC3 (_PRS_ROUTELOC2_CH9LOC_LOC3 << 8) /**< Shifted mode LOC3 for PRS_ROUTELOC2 */ #define PRS_ROUTELOC2_CH9LOC_LOC4 (_PRS_ROUTELOC2_CH9LOC_LOC4 << 8) /**< Shifted mode LOC4 for PRS_ROUTELOC2 */ #define PRS_ROUTELOC2_CH9LOC_LOC5 (_PRS_ROUTELOC2_CH9LOC_LOC5 << 8) /**< Shifted mode LOC5 for PRS_ROUTELOC2 */ #define PRS_ROUTELOC2_CH9LOC_LOC6 (_PRS_ROUTELOC2_CH9LOC_LOC6 << 8) /**< Shifted mode LOC6 for PRS_ROUTELOC2 */ #define PRS_ROUTELOC2_CH9LOC_LOC7 (_PRS_ROUTELOC2_CH9LOC_LOC7 << 8) /**< Shifted mode LOC7 for PRS_ROUTELOC2 */ #define PRS_ROUTELOC2_CH9LOC_LOC8 (_PRS_ROUTELOC2_CH9LOC_LOC8 << 8) /**< Shifted mode LOC8 for PRS_ROUTELOC2 */ #define PRS_ROUTELOC2_CH9LOC_LOC9 (_PRS_ROUTELOC2_CH9LOC_LOC9 << 8) /**< Shifted mode LOC9 for PRS_ROUTELOC2 */ #define PRS_ROUTELOC2_CH9LOC_LOC10 (_PRS_ROUTELOC2_CH9LOC_LOC10 << 8) /**< Shifted mode LOC10 for PRS_ROUTELOC2 */ #define PRS_ROUTELOC2_CH9LOC_LOC11 (_PRS_ROUTELOC2_CH9LOC_LOC11 << 8) /**< Shifted mode LOC11 for PRS_ROUTELOC2 */ #define PRS_ROUTELOC2_CH9LOC_LOC12 (_PRS_ROUTELOC2_CH9LOC_LOC12 << 8) /**< Shifted mode LOC12 for PRS_ROUTELOC2 */ #define PRS_ROUTELOC2_CH9LOC_LOC13 (_PRS_ROUTELOC2_CH9LOC_LOC13 << 8) /**< Shifted mode LOC13 for PRS_ROUTELOC2 */ #define PRS_ROUTELOC2_CH9LOC_LOC14 (_PRS_ROUTELOC2_CH9LOC_LOC14 << 8) /**< Shifted mode LOC14 for PRS_ROUTELOC2 */ #define PRS_ROUTELOC2_CH9LOC_LOC15 (_PRS_ROUTELOC2_CH9LOC_LOC15 << 8) /**< Shifted mode LOC15 for PRS_ROUTELOC2 */ #define PRS_ROUTELOC2_CH9LOC_LOC16 (_PRS_ROUTELOC2_CH9LOC_LOC16 << 8) /**< Shifted mode LOC16 for PRS_ROUTELOC2 */ #define _PRS_ROUTELOC2_CH10LOC_SHIFT 16 /**< Shift value for PRS_CH10LOC */ #define _PRS_ROUTELOC2_CH10LOC_MASK 0x70000UL /**< Bit mask for PRS_CH10LOC */ #define _PRS_ROUTELOC2_CH10LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ #define _PRS_ROUTELOC2_CH10LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ #define _PRS_ROUTELOC2_CH10LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ #define _PRS_ROUTELOC2_CH10LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ #define _PRS_ROUTELOC2_CH10LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC2 */ #define _PRS_ROUTELOC2_CH10LOC_LOC4 0x00000004UL /**< Mode LOC4 for PRS_ROUTELOC2 */ #define _PRS_ROUTELOC2_CH10LOC_LOC5 0x00000005UL /**< Mode LOC5 for PRS_ROUTELOC2 */ #define PRS_ROUTELOC2_CH10LOC_LOC0 (_PRS_ROUTELOC2_CH10LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ #define PRS_ROUTELOC2_CH10LOC_DEFAULT (_PRS_ROUTELOC2_CH10LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ #define PRS_ROUTELOC2_CH10LOC_LOC1 (_PRS_ROUTELOC2_CH10LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ #define PRS_ROUTELOC2_CH10LOC_LOC2 (_PRS_ROUTELOC2_CH10LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ #define PRS_ROUTELOC2_CH10LOC_LOC3 (_PRS_ROUTELOC2_CH10LOC_LOC3 << 16) /**< Shifted mode LOC3 for PRS_ROUTELOC2 */ #define PRS_ROUTELOC2_CH10LOC_LOC4 (_PRS_ROUTELOC2_CH10LOC_LOC4 << 16) /**< Shifted mode LOC4 for PRS_ROUTELOC2 */ #define PRS_ROUTELOC2_CH10LOC_LOC5 (_PRS_ROUTELOC2_CH10LOC_LOC5 << 16) /**< Shifted mode LOC5 for PRS_ROUTELOC2 */ #define _PRS_ROUTELOC2_CH11LOC_SHIFT 24 /**< Shift value for PRS_CH11LOC */ #define _PRS_ROUTELOC2_CH11LOC_MASK 0x7000000UL /**< Bit mask for PRS_CH11LOC */ #define _PRS_ROUTELOC2_CH11LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ #define _PRS_ROUTELOC2_CH11LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ #define _PRS_ROUTELOC2_CH11LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ #define _PRS_ROUTELOC2_CH11LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ #define _PRS_ROUTELOC2_CH11LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC2 */ #define _PRS_ROUTELOC2_CH11LOC_LOC4 0x00000004UL /**< Mode LOC4 for PRS_ROUTELOC2 */ #define _PRS_ROUTELOC2_CH11LOC_LOC5 0x00000005UL /**< Mode LOC5 for PRS_ROUTELOC2 */ #define PRS_ROUTELOC2_CH11LOC_LOC0 (_PRS_ROUTELOC2_CH11LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ #define PRS_ROUTELOC2_CH11LOC_DEFAULT (_PRS_ROUTELOC2_CH11LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ #define PRS_ROUTELOC2_CH11LOC_LOC1 (_PRS_ROUTELOC2_CH11LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ #define PRS_ROUTELOC2_CH11LOC_LOC2 (_PRS_ROUTELOC2_CH11LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ #define PRS_ROUTELOC2_CH11LOC_LOC3 (_PRS_ROUTELOC2_CH11LOC_LOC3 << 24) /**< Shifted mode LOC3 for PRS_ROUTELOC2 */ #define PRS_ROUTELOC2_CH11LOC_LOC4 (_PRS_ROUTELOC2_CH11LOC_LOC4 << 24) /**< Shifted mode LOC4 for PRS_ROUTELOC2 */ #define PRS_ROUTELOC2_CH11LOC_LOC5 (_PRS_ROUTELOC2_CH11LOC_LOC5 << 24) /**< Shifted mode LOC5 for PRS_ROUTELOC2 */ /* Bit fields for PRS CTRL */ #define _PRS_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CTRL */ #define _PRS_CTRL_MASK 0x0000001FUL /**< Mask for PRS_CTRL */ #define PRS_CTRL_SEVONPRS (0x1UL << 0) /**< Set Event on PRS */ #define _PRS_CTRL_SEVONPRS_SHIFT 0 /**< Shift value for PRS_SEVONPRS */ #define _PRS_CTRL_SEVONPRS_MASK 0x1UL /**< Bit mask for PRS_SEVONPRS */ #define _PRS_CTRL_SEVONPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CTRL */ #define PRS_CTRL_SEVONPRS_DEFAULT (_PRS_CTRL_SEVONPRS_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CTRL */ #define _PRS_CTRL_SEVONPRSSEL_SHIFT 1 /**< Shift value for PRS_SEVONPRSSEL */ #define _PRS_CTRL_SEVONPRSSEL_MASK 0x1EUL /**< Bit mask for PRS_SEVONPRSSEL */ #define _PRS_CTRL_SEVONPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CTRL */ #define _PRS_CTRL_SEVONPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_CTRL */ #define _PRS_CTRL_SEVONPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_CTRL */ #define _PRS_CTRL_SEVONPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_CTRL */ #define _PRS_CTRL_SEVONPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_CTRL */ #define _PRS_CTRL_SEVONPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_CTRL */ #define _PRS_CTRL_SEVONPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_CTRL */ #define _PRS_CTRL_SEVONPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_CTRL */ #define _PRS_CTRL_SEVONPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_CTRL */ #define _PRS_CTRL_SEVONPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_CTRL */ #define _PRS_CTRL_SEVONPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_CTRL */ #define _PRS_CTRL_SEVONPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_CTRL */ #define _PRS_CTRL_SEVONPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_CTRL */ #define PRS_CTRL_SEVONPRSSEL_DEFAULT (_PRS_CTRL_SEVONPRSSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_CTRL */ #define PRS_CTRL_SEVONPRSSEL_PRSCH0 (_PRS_CTRL_SEVONPRSSEL_PRSCH0 << 1) /**< Shifted mode PRSCH0 for PRS_CTRL */ #define PRS_CTRL_SEVONPRSSEL_PRSCH1 (_PRS_CTRL_SEVONPRSSEL_PRSCH1 << 1) /**< Shifted mode PRSCH1 for PRS_CTRL */ #define PRS_CTRL_SEVONPRSSEL_PRSCH2 (_PRS_CTRL_SEVONPRSSEL_PRSCH2 << 1) /**< Shifted mode PRSCH2 for PRS_CTRL */ #define PRS_CTRL_SEVONPRSSEL_PRSCH3 (_PRS_CTRL_SEVONPRSSEL_PRSCH3 << 1) /**< Shifted mode PRSCH3 for PRS_CTRL */ #define PRS_CTRL_SEVONPRSSEL_PRSCH4 (_PRS_CTRL_SEVONPRSSEL_PRSCH4 << 1) /**< Shifted mode PRSCH4 for PRS_CTRL */ #define PRS_CTRL_SEVONPRSSEL_PRSCH5 (_PRS_CTRL_SEVONPRSSEL_PRSCH5 << 1) /**< Shifted mode PRSCH5 for PRS_CTRL */ #define PRS_CTRL_SEVONPRSSEL_PRSCH6 (_PRS_CTRL_SEVONPRSSEL_PRSCH6 << 1) /**< Shifted mode PRSCH6 for PRS_CTRL */ #define PRS_CTRL_SEVONPRSSEL_PRSCH7 (_PRS_CTRL_SEVONPRSSEL_PRSCH7 << 1) /**< Shifted mode PRSCH7 for PRS_CTRL */ #define PRS_CTRL_SEVONPRSSEL_PRSCH8 (_PRS_CTRL_SEVONPRSSEL_PRSCH8 << 1) /**< Shifted mode PRSCH8 for PRS_CTRL */ #define PRS_CTRL_SEVONPRSSEL_PRSCH9 (_PRS_CTRL_SEVONPRSSEL_PRSCH9 << 1) /**< Shifted mode PRSCH9 for PRS_CTRL */ #define PRS_CTRL_SEVONPRSSEL_PRSCH10 (_PRS_CTRL_SEVONPRSSEL_PRSCH10 << 1) /**< Shifted mode PRSCH10 for PRS_CTRL */ #define PRS_CTRL_SEVONPRSSEL_PRSCH11 (_PRS_CTRL_SEVONPRSSEL_PRSCH11 << 1) /**< Shifted mode PRSCH11 for PRS_CTRL */ /* Bit fields for PRS DMAREQ0 */ #define _PRS_DMAREQ0_RESETVALUE 0x00000000UL /**< Default value for PRS_DMAREQ0 */ #define _PRS_DMAREQ0_MASK 0x000003C0UL /**< Mask for PRS_DMAREQ0 */ #define _PRS_DMAREQ0_PRSSEL_SHIFT 6 /**< Shift value for PRS_PRSSEL */ #define _PRS_DMAREQ0_PRSSEL_MASK 0x3C0UL /**< Bit mask for PRS_PRSSEL */ #define _PRS_DMAREQ0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_DMAREQ0 */ #define _PRS_DMAREQ0_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_DMAREQ0 */ #define _PRS_DMAREQ0_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_DMAREQ0 */ #define _PRS_DMAREQ0_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_DMAREQ0 */ #define _PRS_DMAREQ0_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_DMAREQ0 */ #define _PRS_DMAREQ0_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_DMAREQ0 */ #define _PRS_DMAREQ0_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_DMAREQ0 */ #define _PRS_DMAREQ0_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_DMAREQ0 */ #define _PRS_DMAREQ0_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_DMAREQ0 */ #define _PRS_DMAREQ0_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_DMAREQ0 */ #define _PRS_DMAREQ0_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_DMAREQ0 */ #define _PRS_DMAREQ0_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_DMAREQ0 */ #define _PRS_DMAREQ0_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_DMAREQ0 */ #define PRS_DMAREQ0_PRSSEL_DEFAULT (_PRS_DMAREQ0_PRSSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_DMAREQ0 */ #define PRS_DMAREQ0_PRSSEL_PRSCH0 (_PRS_DMAREQ0_PRSSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for PRS_DMAREQ0 */ #define PRS_DMAREQ0_PRSSEL_PRSCH1 (_PRS_DMAREQ0_PRSSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for PRS_DMAREQ0 */ #define PRS_DMAREQ0_PRSSEL_PRSCH2 (_PRS_DMAREQ0_PRSSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for PRS_DMAREQ0 */ #define PRS_DMAREQ0_PRSSEL_PRSCH3 (_PRS_DMAREQ0_PRSSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for PRS_DMAREQ0 */ #define PRS_DMAREQ0_PRSSEL_PRSCH4 (_PRS_DMAREQ0_PRSSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for PRS_DMAREQ0 */ #define PRS_DMAREQ0_PRSSEL_PRSCH5 (_PRS_DMAREQ0_PRSSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for PRS_DMAREQ0 */ #define PRS_DMAREQ0_PRSSEL_PRSCH6 (_PRS_DMAREQ0_PRSSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for PRS_DMAREQ0 */ #define PRS_DMAREQ0_PRSSEL_PRSCH7 (_PRS_DMAREQ0_PRSSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for PRS_DMAREQ0 */ #define PRS_DMAREQ0_PRSSEL_PRSCH8 (_PRS_DMAREQ0_PRSSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for PRS_DMAREQ0 */ #define PRS_DMAREQ0_PRSSEL_PRSCH9 (_PRS_DMAREQ0_PRSSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for PRS_DMAREQ0 */ #define PRS_DMAREQ0_PRSSEL_PRSCH10 (_PRS_DMAREQ0_PRSSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for PRS_DMAREQ0 */ #define PRS_DMAREQ0_PRSSEL_PRSCH11 (_PRS_DMAREQ0_PRSSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for PRS_DMAREQ0 */ /* Bit fields for PRS DMAREQ1 */ #define _PRS_DMAREQ1_RESETVALUE 0x00000000UL /**< Default value for PRS_DMAREQ1 */ #define _PRS_DMAREQ1_MASK 0x000003C0UL /**< Mask for PRS_DMAREQ1 */ #define _PRS_DMAREQ1_PRSSEL_SHIFT 6 /**< Shift value for PRS_PRSSEL */ #define _PRS_DMAREQ1_PRSSEL_MASK 0x3C0UL /**< Bit mask for PRS_PRSSEL */ #define _PRS_DMAREQ1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_DMAREQ1 */ #define _PRS_DMAREQ1_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_DMAREQ1 */ #define _PRS_DMAREQ1_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_DMAREQ1 */ #define _PRS_DMAREQ1_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_DMAREQ1 */ #define _PRS_DMAREQ1_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_DMAREQ1 */ #define _PRS_DMAREQ1_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_DMAREQ1 */ #define _PRS_DMAREQ1_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_DMAREQ1 */ #define _PRS_DMAREQ1_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_DMAREQ1 */ #define _PRS_DMAREQ1_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_DMAREQ1 */ #define _PRS_DMAREQ1_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_DMAREQ1 */ #define _PRS_DMAREQ1_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_DMAREQ1 */ #define _PRS_DMAREQ1_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_DMAREQ1 */ #define _PRS_DMAREQ1_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_DMAREQ1 */ #define PRS_DMAREQ1_PRSSEL_DEFAULT (_PRS_DMAREQ1_PRSSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_DMAREQ1 */ #define PRS_DMAREQ1_PRSSEL_PRSCH0 (_PRS_DMAREQ1_PRSSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for PRS_DMAREQ1 */ #define PRS_DMAREQ1_PRSSEL_PRSCH1 (_PRS_DMAREQ1_PRSSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for PRS_DMAREQ1 */ #define PRS_DMAREQ1_PRSSEL_PRSCH2 (_PRS_DMAREQ1_PRSSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for PRS_DMAREQ1 */ #define PRS_DMAREQ1_PRSSEL_PRSCH3 (_PRS_DMAREQ1_PRSSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for PRS_DMAREQ1 */ #define PRS_DMAREQ1_PRSSEL_PRSCH4 (_PRS_DMAREQ1_PRSSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for PRS_DMAREQ1 */ #define PRS_DMAREQ1_PRSSEL_PRSCH5 (_PRS_DMAREQ1_PRSSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for PRS_DMAREQ1 */ #define PRS_DMAREQ1_PRSSEL_PRSCH6 (_PRS_DMAREQ1_PRSSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for PRS_DMAREQ1 */ #define PRS_DMAREQ1_PRSSEL_PRSCH7 (_PRS_DMAREQ1_PRSSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for PRS_DMAREQ1 */ #define PRS_DMAREQ1_PRSSEL_PRSCH8 (_PRS_DMAREQ1_PRSSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for PRS_DMAREQ1 */ #define PRS_DMAREQ1_PRSSEL_PRSCH9 (_PRS_DMAREQ1_PRSSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for PRS_DMAREQ1 */ #define PRS_DMAREQ1_PRSSEL_PRSCH10 (_PRS_DMAREQ1_PRSSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for PRS_DMAREQ1 */ #define PRS_DMAREQ1_PRSSEL_PRSCH11 (_PRS_DMAREQ1_PRSSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for PRS_DMAREQ1 */ /* Bit fields for PRS PEEK */ #define _PRS_PEEK_RESETVALUE 0x00000000UL /**< Default value for PRS_PEEK */ #define _PRS_PEEK_MASK 0x00000FFFUL /**< Mask for PRS_PEEK */ #define PRS_PEEK_CH0VAL (0x1UL << 0) /**< Channel 0 Current Value */ #define _PRS_PEEK_CH0VAL_SHIFT 0 /**< Shift value for PRS_CH0VAL */ #define _PRS_PEEK_CH0VAL_MASK 0x1UL /**< Bit mask for PRS_CH0VAL */ #define _PRS_PEEK_CH0VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ #define PRS_PEEK_CH0VAL_DEFAULT (_PRS_PEEK_CH0VAL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_PEEK */ #define PRS_PEEK_CH1VAL (0x1UL << 1) /**< Channel 1 Current Value */ #define _PRS_PEEK_CH1VAL_SHIFT 1 /**< Shift value for PRS_CH1VAL */ #define _PRS_PEEK_CH1VAL_MASK 0x2UL /**< Bit mask for PRS_CH1VAL */ #define _PRS_PEEK_CH1VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ #define PRS_PEEK_CH1VAL_DEFAULT (_PRS_PEEK_CH1VAL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_PEEK */ #define PRS_PEEK_CH2VAL (0x1UL << 2) /**< Channel 2 Current Value */ #define _PRS_PEEK_CH2VAL_SHIFT 2 /**< Shift value for PRS_CH2VAL */ #define _PRS_PEEK_CH2VAL_MASK 0x4UL /**< Bit mask for PRS_CH2VAL */ #define _PRS_PEEK_CH2VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ #define PRS_PEEK_CH2VAL_DEFAULT (_PRS_PEEK_CH2VAL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_PEEK */ #define PRS_PEEK_CH3VAL (0x1UL << 3) /**< Channel 3 Current Value */ #define _PRS_PEEK_CH3VAL_SHIFT 3 /**< Shift value for PRS_CH3VAL */ #define _PRS_PEEK_CH3VAL_MASK 0x8UL /**< Bit mask for PRS_CH3VAL */ #define _PRS_PEEK_CH3VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ #define PRS_PEEK_CH3VAL_DEFAULT (_PRS_PEEK_CH3VAL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_PEEK */ #define PRS_PEEK_CH4VAL (0x1UL << 4) /**< Channel 4 Current Value */ #define _PRS_PEEK_CH4VAL_SHIFT 4 /**< Shift value for PRS_CH4VAL */ #define _PRS_PEEK_CH4VAL_MASK 0x10UL /**< Bit mask for PRS_CH4VAL */ #define _PRS_PEEK_CH4VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ #define PRS_PEEK_CH4VAL_DEFAULT (_PRS_PEEK_CH4VAL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_PEEK */ #define PRS_PEEK_CH5VAL (0x1UL << 5) /**< Channel 5 Current Value */ #define _PRS_PEEK_CH5VAL_SHIFT 5 /**< Shift value for PRS_CH5VAL */ #define _PRS_PEEK_CH5VAL_MASK 0x20UL /**< Bit mask for PRS_CH5VAL */ #define _PRS_PEEK_CH5VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ #define PRS_PEEK_CH5VAL_DEFAULT (_PRS_PEEK_CH5VAL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_PEEK */ #define PRS_PEEK_CH6VAL (0x1UL << 6) /**< Channel 6 Current Value */ #define _PRS_PEEK_CH6VAL_SHIFT 6 /**< Shift value for PRS_CH6VAL */ #define _PRS_PEEK_CH6VAL_MASK 0x40UL /**< Bit mask for PRS_CH6VAL */ #define _PRS_PEEK_CH6VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ #define PRS_PEEK_CH6VAL_DEFAULT (_PRS_PEEK_CH6VAL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_PEEK */ #define PRS_PEEK_CH7VAL (0x1UL << 7) /**< Channel 7 Current Value */ #define _PRS_PEEK_CH7VAL_SHIFT 7 /**< Shift value for PRS_CH7VAL */ #define _PRS_PEEK_CH7VAL_MASK 0x80UL /**< Bit mask for PRS_CH7VAL */ #define _PRS_PEEK_CH7VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ #define PRS_PEEK_CH7VAL_DEFAULT (_PRS_PEEK_CH7VAL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_PEEK */ #define PRS_PEEK_CH8VAL (0x1UL << 8) /**< Channel 8 Current Value */ #define _PRS_PEEK_CH8VAL_SHIFT 8 /**< Shift value for PRS_CH8VAL */ #define _PRS_PEEK_CH8VAL_MASK 0x100UL /**< Bit mask for PRS_CH8VAL */ #define _PRS_PEEK_CH8VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ #define PRS_PEEK_CH8VAL_DEFAULT (_PRS_PEEK_CH8VAL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_PEEK */ #define PRS_PEEK_CH9VAL (0x1UL << 9) /**< Channel 9 Current Value */ #define _PRS_PEEK_CH9VAL_SHIFT 9 /**< Shift value for PRS_CH9VAL */ #define _PRS_PEEK_CH9VAL_MASK 0x200UL /**< Bit mask for PRS_CH9VAL */ #define _PRS_PEEK_CH9VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ #define PRS_PEEK_CH9VAL_DEFAULT (_PRS_PEEK_CH9VAL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_PEEK */ #define PRS_PEEK_CH10VAL (0x1UL << 10) /**< Channel 10 Current Value */ #define _PRS_PEEK_CH10VAL_SHIFT 10 /**< Shift value for PRS_CH10VAL */ #define _PRS_PEEK_CH10VAL_MASK 0x400UL /**< Bit mask for PRS_CH10VAL */ #define _PRS_PEEK_CH10VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ #define PRS_PEEK_CH10VAL_DEFAULT (_PRS_PEEK_CH10VAL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_PEEK */ #define PRS_PEEK_CH11VAL (0x1UL << 11) /**< Channel 11 Current Value */ #define _PRS_PEEK_CH11VAL_SHIFT 11 /**< Shift value for PRS_CH11VAL */ #define _PRS_PEEK_CH11VAL_MASK 0x800UL /**< Bit mask for PRS_CH11VAL */ #define _PRS_PEEK_CH11VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ #define PRS_PEEK_CH11VAL_DEFAULT (_PRS_PEEK_CH11VAL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_PEEK */ /* Bit fields for PRS CH_CTRL */ #define _PRS_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CH_CTRL */ #define _PRS_CH_CTRL_MASK 0x5E307F07UL /**< Mask for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for PRS_SIGSEL */ #define _PRS_CH_CTRL_SIGSEL_MASK 0x7UL /**< Bit mask for PRS_SIGSEL */ #define _PRS_CH_CTRL_SIGSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_PRSCH8 0x00000000UL /**< Mode PRSCH8 for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_ACMP0OUT 0x00000000UL /**< Mode ACMP0OUT for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_ACMP1OUT 0x00000000UL /**< Mode ACMP1OUT for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 0x00000000UL /**< Mode LESENSESCANRES0 for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 0x00000000UL /**< Mode LESENSESCANRES8 for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_LESENSEDEC0 0x00000000UL /**< Mode LESENSEDEC0 for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_LESENSEMEASACT 0x00000000UL /**< Mode LESENSEMEASACT for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_GPIOPIN0 0x00000000UL /**< Mode GPIOPIN0 for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_GPIOPIN8 0x00000000UL /**< Mode GPIOPIN8 for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_LETIMER0CH0 0x00000000UL /**< Mode LETIMER0CH0 for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_PCNT0TCC 0x00000000UL /**< Mode PCNT0TCC for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_PCNT1TCC 0x00000000UL /**< Mode PCNT1TCC for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_PCNT2TCC 0x00000000UL /**< Mode PCNT2TCC for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 0x00000000UL /**< Mode CMUCLKOUT0 for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_VDAC0CH0 0x00000000UL /**< Mode VDAC0CH0 for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD 0x00000000UL /**< Mode CRYOTIMERPERIOD for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_USART0IRTX 0x00000000UL /**< Mode USART0IRTX for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_USART2IRTX 0x00000000UL /**< Mode USART2IRTX for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_TIMER0UF 0x00000000UL /**< Mode TIMER0UF for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_TIMER1UF 0x00000000UL /**< Mode TIMER1UF for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_WTIMER0UF 0x00000000UL /**< Mode WTIMER0UF for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_WTIMER1UF 0x00000000UL /**< Mode WTIMER1UF for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_CM4TXEV 0x00000000UL /**< Mode CM4TXEV for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_PRSCH9 0x00000001UL /**< Mode PRSCH9 for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 0x00000001UL /**< Mode LESENSESCANRES1 for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 0x00000001UL /**< Mode LESENSESCANRES9 for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_LESENSEDEC1 0x00000001UL /**< Mode LESENSEDEC1 for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_RTCCCCV0 0x00000001UL /**< Mode RTCCCCV0 for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_GPIOPIN1 0x00000001UL /**< Mode GPIOPIN1 for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_GPIOPIN9 0x00000001UL /**< Mode GPIOPIN9 for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_LETIMER0CH1 0x00000001UL /**< Mode LETIMER0CH1 for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_PCNT0UFOF 0x00000001UL /**< Mode PCNT0UFOF for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_PCNT1UFOF 0x00000001UL /**< Mode PCNT1UFOF for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_PCNT2UFOF 0x00000001UL /**< Mode PCNT2UFOF for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 0x00000001UL /**< Mode CMUCLKOUT1 for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_VDAC0CH1 0x00000001UL /**< Mode VDAC0CH1 for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_USART0TXC 0x00000001UL /**< Mode USART0TXC for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_USART1TXC 0x00000001UL /**< Mode USART1TXC for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_USART2TXC 0x00000001UL /**< Mode USART2TXC for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_USART3TXC 0x00000001UL /**< Mode USART3TXC for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_TIMER0OF 0x00000001UL /**< Mode TIMER0OF for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_TIMER1OF 0x00000001UL /**< Mode TIMER1OF for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_WTIMER0OF 0x00000001UL /**< Mode WTIMER0OF for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_WTIMER1OF 0x00000001UL /**< Mode WTIMER1OF for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF 0x00000001UL /**< Mode CM4ICACHEPCHITSOF for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_PRSCH10 0x00000002UL /**< Mode PRSCH10 for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 0x00000002UL /**< Mode LESENSESCANRES2 for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 0x00000002UL /**< Mode LESENSESCANRES10 for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_LESENSEDEC2 0x00000002UL /**< Mode LESENSEDEC2 for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_RTCCCCV1 0x00000002UL /**< Mode RTCCCCV1 for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_GPIOPIN2 0x00000002UL /**< Mode GPIOPIN2 for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_GPIOPIN10 0x00000002UL /**< Mode GPIOPIN10 for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_PCNT0DIR 0x00000002UL /**< Mode PCNT0DIR for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_PCNT1DIR 0x00000002UL /**< Mode PCNT1DIR for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_PCNT2DIR 0x00000002UL /**< Mode PCNT2DIR for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_VDAC0OPA0 0x00000002UL /**< Mode VDAC0OPA0 for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000002UL /**< Mode USART0RXDATAV for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000002UL /**< Mode USART1RXDATAV for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_USART2RXDATAV 0x00000002UL /**< Mode USART2RXDATAV for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_USART3RXDATAV 0x00000002UL /**< Mode USART3RXDATAV for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_TIMER0CC0 0x00000002UL /**< Mode TIMER0CC0 for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_TIMER1CC0 0x00000002UL /**< Mode TIMER1CC0 for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_WTIMER0CC0 0x00000002UL /**< Mode WTIMER0CC0 for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_WTIMER1CC0 0x00000002UL /**< Mode WTIMER1CC0 for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF 0x00000002UL /**< Mode CM4ICACHEPCMISSESOF for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_PRSCH11 0x00000003UL /**< Mode PRSCH11 for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 0x00000003UL /**< Mode LESENSESCANRES3 for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 0x00000003UL /**< Mode LESENSESCANRES11 for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_LESENSEDECCMP 0x00000003UL /**< Mode LESENSEDECCMP for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_RTCCCCV2 0x00000003UL /**< Mode RTCCCCV2 for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_GPIOPIN3 0x00000003UL /**< Mode GPIOPIN3 for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_GPIOPIN11 0x00000003UL /**< Mode GPIOPIN11 for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_VDAC0OPA1 0x00000003UL /**< Mode VDAC0OPA1 for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_USART0RTS 0x00000003UL /**< Mode USART0RTS for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_USART1RTS 0x00000003UL /**< Mode USART1RTS for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_USART2RTS 0x00000003UL /**< Mode USART2RTS for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_USART3RTS 0x00000003UL /**< Mode USART3RTS for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_TIMER0CC1 0x00000003UL /**< Mode TIMER0CC1 for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_TIMER1CC1 0x00000003UL /**< Mode TIMER1CC1 for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_WTIMER0CC1 0x00000003UL /**< Mode WTIMER0CC1 for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_WTIMER1CC1 0x00000003UL /**< Mode WTIMER1CC1 for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 0x00000004UL /**< Mode LESENSESCANRES4 for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 0x00000004UL /**< Mode LESENSESCANRES12 for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_GPIOPIN4 0x00000004UL /**< Mode GPIOPIN4 for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_GPIOPIN12 0x00000004UL /**< Mode GPIOPIN12 for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_VDAC0OPA2 0x00000004UL /**< Mode VDAC0OPA2 for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_TIMER0CC2 0x00000004UL /**< Mode TIMER0CC2 for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_TIMER1CC2 0x00000004UL /**< Mode TIMER1CC2 for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_WTIMER0CC2 0x00000004UL /**< Mode WTIMER0CC2 for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_WTIMER1CC2 0x00000004UL /**< Mode WTIMER1CC2 for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 0x00000005UL /**< Mode LESENSESCANRES5 for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 0x00000005UL /**< Mode LESENSESCANRES13 for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_GPIOPIN5 0x00000005UL /**< Mode GPIOPIN5 for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_GPIOPIN13 0x00000005UL /**< Mode GPIOPIN13 for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_USART0TX 0x00000005UL /**< Mode USART0TX for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_USART1TX 0x00000005UL /**< Mode USART1TX for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_USART2TX 0x00000005UL /**< Mode USART2TX for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_USART3TX 0x00000005UL /**< Mode USART3TX for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_TIMER1CC3 0x00000005UL /**< Mode TIMER1CC3 for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_WTIMER1CC3 0x00000005UL /**< Mode WTIMER1CC3 for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 0x00000006UL /**< Mode LESENSESCANRES6 for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 0x00000006UL /**< Mode LESENSESCANRES14 for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_GPIOPIN6 0x00000006UL /**< Mode GPIOPIN6 for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_GPIOPIN14 0x00000006UL /**< Mode GPIOPIN14 for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_USART0CS 0x00000006UL /**< Mode USART0CS for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_USART1CS 0x00000006UL /**< Mode USART1CS for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_USART2CS 0x00000006UL /**< Mode USART2CS for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_USART3CS 0x00000006UL /**< Mode USART3CS for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 0x00000007UL /**< Mode LESENSESCANRES7 for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 0x00000007UL /**< Mode LESENSESCANRES15 for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_GPIOPIN7 0x00000007UL /**< Mode GPIOPIN7 for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_GPIOPIN15 0x00000007UL /**< Mode GPIOPIN15 for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_PRSCH0 (_PRS_CH_CTRL_SIGSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_PRSCH8 (_PRS_CH_CTRL_SIGSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_ACMP0OUT (_PRS_CH_CTRL_SIGSEL_ACMP0OUT << 0) /**< Shifted mode ACMP0OUT for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_ACMP1OUT (_PRS_CH_CTRL_SIGSEL_ACMP1OUT << 0) /**< Shifted mode ACMP1OUT for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_ADC0SINGLE (_PRS_CH_CTRL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 << 0) /**< Shifted mode LESENSESCANRES0 for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 << 0) /**< Shifted mode LESENSESCANRES8 for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_LESENSEDEC0 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC0 << 0) /**< Shifted mode LESENSEDEC0 for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_LESENSEMEASACT (_PRS_CH_CTRL_SIGSEL_LESENSEMEASACT << 0) /**< Shifted mode LESENSEMEASACT for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_GPIOPIN0 (_PRS_CH_CTRL_SIGSEL_GPIOPIN0 << 0) /**< Shifted mode GPIOPIN0 for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_GPIOPIN8 (_PRS_CH_CTRL_SIGSEL_GPIOPIN8 << 0) /**< Shifted mode GPIOPIN8 for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_LETIMER0CH0 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH0 << 0) /**< Shifted mode LETIMER0CH0 for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_PCNT0TCC (_PRS_CH_CTRL_SIGSEL_PCNT0TCC << 0) /**< Shifted mode PCNT0TCC for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_PCNT1TCC (_PRS_CH_CTRL_SIGSEL_PCNT1TCC << 0) /**< Shifted mode PCNT1TCC for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_PCNT2TCC (_PRS_CH_CTRL_SIGSEL_PCNT2TCC << 0) /**< Shifted mode PCNT2TCC for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 << 0) /**< Shifted mode CMUCLKOUT0 for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_VDAC0CH0 (_PRS_CH_CTRL_SIGSEL_VDAC0CH0 << 0) /**< Shifted mode VDAC0CH0 for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD (_PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD << 0) /**< Shifted mode CRYOTIMERPERIOD for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_USART0IRTX (_PRS_CH_CTRL_SIGSEL_USART0IRTX << 0) /**< Shifted mode USART0IRTX for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_USART2IRTX (_PRS_CH_CTRL_SIGSEL_USART2IRTX << 0) /**< Shifted mode USART2IRTX for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_TIMER0UF (_PRS_CH_CTRL_SIGSEL_TIMER0UF << 0) /**< Shifted mode TIMER0UF for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_TIMER1UF (_PRS_CH_CTRL_SIGSEL_TIMER1UF << 0) /**< Shifted mode TIMER1UF for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_WTIMER0UF (_PRS_CH_CTRL_SIGSEL_WTIMER0UF << 0) /**< Shifted mode WTIMER0UF for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_WTIMER1UF (_PRS_CH_CTRL_SIGSEL_WTIMER1UF << 0) /**< Shifted mode WTIMER1UF for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_CM4TXEV (_PRS_CH_CTRL_SIGSEL_CM4TXEV << 0) /**< Shifted mode CM4TXEV for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_PRSCH1 (_PRS_CH_CTRL_SIGSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_PRSCH9 (_PRS_CH_CTRL_SIGSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_ADC0SCAN (_PRS_CH_CTRL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 << 0) /**< Shifted mode LESENSESCANRES1 for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 << 0) /**< Shifted mode LESENSESCANRES9 for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_LESENSEDEC1 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC1 << 0) /**< Shifted mode LESENSEDEC1 for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_RTCCCCV0 (_PRS_CH_CTRL_SIGSEL_RTCCCCV0 << 0) /**< Shifted mode RTCCCCV0 for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_GPIOPIN1 (_PRS_CH_CTRL_SIGSEL_GPIOPIN1 << 0) /**< Shifted mode GPIOPIN1 for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_GPIOPIN9 (_PRS_CH_CTRL_SIGSEL_GPIOPIN9 << 0) /**< Shifted mode GPIOPIN9 for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_LETIMER0CH1 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH1 << 0) /**< Shifted mode LETIMER0CH1 for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_PCNT0UFOF (_PRS_CH_CTRL_SIGSEL_PCNT0UFOF << 0) /**< Shifted mode PCNT0UFOF for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_PCNT1UFOF (_PRS_CH_CTRL_SIGSEL_PCNT1UFOF << 0) /**< Shifted mode PCNT1UFOF for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_PCNT2UFOF (_PRS_CH_CTRL_SIGSEL_PCNT2UFOF << 0) /**< Shifted mode PCNT2UFOF for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 << 0) /**< Shifted mode CMUCLKOUT1 for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_VDAC0CH1 (_PRS_CH_CTRL_SIGSEL_VDAC0CH1 << 0) /**< Shifted mode VDAC0CH1 for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_USART0TXC (_PRS_CH_CTRL_SIGSEL_USART0TXC << 0) /**< Shifted mode USART0TXC for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_USART1TXC (_PRS_CH_CTRL_SIGSEL_USART1TXC << 0) /**< Shifted mode USART1TXC for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_USART2TXC (_PRS_CH_CTRL_SIGSEL_USART2TXC << 0) /**< Shifted mode USART2TXC for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_USART3TXC (_PRS_CH_CTRL_SIGSEL_USART3TXC << 0) /**< Shifted mode USART3TXC for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_TIMER0OF (_PRS_CH_CTRL_SIGSEL_TIMER0OF << 0) /**< Shifted mode TIMER0OF for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_TIMER1OF (_PRS_CH_CTRL_SIGSEL_TIMER1OF << 0) /**< Shifted mode TIMER1OF for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_WTIMER0OF (_PRS_CH_CTRL_SIGSEL_WTIMER0OF << 0) /**< Shifted mode WTIMER0OF for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_WTIMER1OF (_PRS_CH_CTRL_SIGSEL_WTIMER1OF << 0) /**< Shifted mode WTIMER1OF for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF (_PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF << 0) /**< Shifted mode CM4ICACHEPCHITSOF for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_PRSCH2 (_PRS_CH_CTRL_SIGSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_PRSCH10 (_PRS_CH_CTRL_SIGSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 << 0) /**< Shifted mode LESENSESCANRES2 for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 << 0) /**< Shifted mode LESENSESCANRES10 for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_LESENSEDEC2 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC2 << 0) /**< Shifted mode LESENSEDEC2 for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_RTCCCCV1 (_PRS_CH_CTRL_SIGSEL_RTCCCCV1 << 0) /**< Shifted mode RTCCCCV1 for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_GPIOPIN2 (_PRS_CH_CTRL_SIGSEL_GPIOPIN2 << 0) /**< Shifted mode GPIOPIN2 for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_GPIOPIN10 (_PRS_CH_CTRL_SIGSEL_GPIOPIN10 << 0) /**< Shifted mode GPIOPIN10 for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_PCNT0DIR (_PRS_CH_CTRL_SIGSEL_PCNT0DIR << 0) /**< Shifted mode PCNT0DIR for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_PCNT1DIR (_PRS_CH_CTRL_SIGSEL_PCNT1DIR << 0) /**< Shifted mode PCNT1DIR for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_PCNT2DIR (_PRS_CH_CTRL_SIGSEL_PCNT2DIR << 0) /**< Shifted mode PCNT2DIR for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_VDAC0OPA0 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA0 << 0) /**< Shifted mode VDAC0OPA0 for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_USART0RXDATAV (_PRS_CH_CTRL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_USART1RXDATAV (_PRS_CH_CTRL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_USART2RXDATAV (_PRS_CH_CTRL_SIGSEL_USART2RXDATAV << 0) /**< Shifted mode USART2RXDATAV for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_USART3RXDATAV (_PRS_CH_CTRL_SIGSEL_USART3RXDATAV << 0) /**< Shifted mode USART3RXDATAV for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_TIMER0CC0 (_PRS_CH_CTRL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_TIMER1CC0 (_PRS_CH_CTRL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_WTIMER0CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER0CC0 << 0) /**< Shifted mode WTIMER0CC0 for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_WTIMER1CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC0 << 0) /**< Shifted mode WTIMER1CC0 for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF (_PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF << 0) /**< Shifted mode CM4ICACHEPCMISSESOF for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_PRSCH3 (_PRS_CH_CTRL_SIGSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_PRSCH11 (_PRS_CH_CTRL_SIGSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 << 0) /**< Shifted mode LESENSESCANRES3 for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 << 0) /**< Shifted mode LESENSESCANRES11 for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_LESENSEDECCMP (_PRS_CH_CTRL_SIGSEL_LESENSEDECCMP << 0) /**< Shifted mode LESENSEDECCMP for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_RTCCCCV2 (_PRS_CH_CTRL_SIGSEL_RTCCCCV2 << 0) /**< Shifted mode RTCCCCV2 for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_GPIOPIN3 (_PRS_CH_CTRL_SIGSEL_GPIOPIN3 << 0) /**< Shifted mode GPIOPIN3 for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_GPIOPIN11 (_PRS_CH_CTRL_SIGSEL_GPIOPIN11 << 0) /**< Shifted mode GPIOPIN11 for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_VDAC0OPA1 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA1 << 0) /**< Shifted mode VDAC0OPA1 for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_USART0RTS (_PRS_CH_CTRL_SIGSEL_USART0RTS << 0) /**< Shifted mode USART0RTS for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_USART1RTS (_PRS_CH_CTRL_SIGSEL_USART1RTS << 0) /**< Shifted mode USART1RTS for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_USART2RTS (_PRS_CH_CTRL_SIGSEL_USART2RTS << 0) /**< Shifted mode USART2RTS for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_USART3RTS (_PRS_CH_CTRL_SIGSEL_USART3RTS << 0) /**< Shifted mode USART3RTS for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_TIMER0CC1 (_PRS_CH_CTRL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_TIMER1CC1 (_PRS_CH_CTRL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_WTIMER0CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER0CC1 << 0) /**< Shifted mode WTIMER0CC1 for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_WTIMER1CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC1 << 0) /**< Shifted mode WTIMER1CC1 for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_PRSCH4 (_PRS_CH_CTRL_SIGSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 << 0) /**< Shifted mode LESENSESCANRES4 for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 << 0) /**< Shifted mode LESENSESCANRES12 for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_GPIOPIN4 (_PRS_CH_CTRL_SIGSEL_GPIOPIN4 << 0) /**< Shifted mode GPIOPIN4 for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_GPIOPIN12 (_PRS_CH_CTRL_SIGSEL_GPIOPIN12 << 0) /**< Shifted mode GPIOPIN12 for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_VDAC0OPA2 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA2 << 0) /**< Shifted mode VDAC0OPA2 for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_TIMER0CC2 (_PRS_CH_CTRL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_TIMER1CC2 (_PRS_CH_CTRL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_WTIMER0CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER0CC2 << 0) /**< Shifted mode WTIMER0CC2 for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_WTIMER1CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC2 << 0) /**< Shifted mode WTIMER1CC2 for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_PRSCH5 (_PRS_CH_CTRL_SIGSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 << 0) /**< Shifted mode LESENSESCANRES5 for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 << 0) /**< Shifted mode LESENSESCANRES13 for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_GPIOPIN5 (_PRS_CH_CTRL_SIGSEL_GPIOPIN5 << 0) /**< Shifted mode GPIOPIN5 for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_GPIOPIN13 (_PRS_CH_CTRL_SIGSEL_GPIOPIN13 << 0) /**< Shifted mode GPIOPIN13 for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_USART0TX (_PRS_CH_CTRL_SIGSEL_USART0TX << 0) /**< Shifted mode USART0TX for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_USART1TX (_PRS_CH_CTRL_SIGSEL_USART1TX << 0) /**< Shifted mode USART1TX for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_USART2TX (_PRS_CH_CTRL_SIGSEL_USART2TX << 0) /**< Shifted mode USART2TX for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_USART3TX (_PRS_CH_CTRL_SIGSEL_USART3TX << 0) /**< Shifted mode USART3TX for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_TIMER1CC3 (_PRS_CH_CTRL_SIGSEL_TIMER1CC3 << 0) /**< Shifted mode TIMER1CC3 for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_WTIMER1CC3 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC3 << 0) /**< Shifted mode WTIMER1CC3 for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_PRSCH6 (_PRS_CH_CTRL_SIGSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 << 0) /**< Shifted mode LESENSESCANRES6 for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 << 0) /**< Shifted mode LESENSESCANRES14 for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_GPIOPIN6 (_PRS_CH_CTRL_SIGSEL_GPIOPIN6 << 0) /**< Shifted mode GPIOPIN6 for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_GPIOPIN14 (_PRS_CH_CTRL_SIGSEL_GPIOPIN14 << 0) /**< Shifted mode GPIOPIN14 for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_USART0CS (_PRS_CH_CTRL_SIGSEL_USART0CS << 0) /**< Shifted mode USART0CS for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_USART1CS (_PRS_CH_CTRL_SIGSEL_USART1CS << 0) /**< Shifted mode USART1CS for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_USART2CS (_PRS_CH_CTRL_SIGSEL_USART2CS << 0) /**< Shifted mode USART2CS for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_USART3CS (_PRS_CH_CTRL_SIGSEL_USART3CS << 0) /**< Shifted mode USART3CS for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_PRSCH7 (_PRS_CH_CTRL_SIGSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 << 0) /**< Shifted mode LESENSESCANRES7 for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 << 0) /**< Shifted mode LESENSESCANRES15 for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_GPIOPIN7 (_PRS_CH_CTRL_SIGSEL_GPIOPIN7 << 0) /**< Shifted mode GPIOPIN7 for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_GPIOPIN15 (_PRS_CH_CTRL_SIGSEL_GPIOPIN15 << 0) /**< Shifted mode GPIOPIN15 for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SOURCESEL_SHIFT 8 /**< Shift value for PRS_SOURCESEL */ #define _PRS_CH_CTRL_SOURCESEL_MASK 0x7F00UL /**< Bit mask for PRS_SOURCESEL */ #define _PRS_CH_CTRL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SOURCESEL_PRSL 0x00000001UL /**< Mode PRSL for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SOURCESEL_PRSH 0x00000002UL /**< Mode PRSH for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SOURCESEL_ACMP0 0x00000003UL /**< Mode ACMP0 for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SOURCESEL_ACMP1 0x00000004UL /**< Mode ACMP1 for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SOURCESEL_ADC0 0x00000005UL /**< Mode ADC0 for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SOURCESEL_LESENSEL 0x00000007UL /**< Mode LESENSEL for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SOURCESEL_LESENSEH 0x00000008UL /**< Mode LESENSEH for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SOURCESEL_LESENSED 0x00000009UL /**< Mode LESENSED for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SOURCESEL_LESENSE 0x0000000AUL /**< Mode LESENSE for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SOURCESEL_RTCC 0x0000000BUL /**< Mode RTCC for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SOURCESEL_GPIOL 0x0000000CUL /**< Mode GPIOL for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SOURCESEL_GPIOH 0x0000000DUL /**< Mode GPIOH for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SOURCESEL_LETIMER0 0x0000000EUL /**< Mode LETIMER0 for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SOURCESEL_PCNT0 0x0000000FUL /**< Mode PCNT0 for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SOURCESEL_PCNT1 0x00000010UL /**< Mode PCNT1 for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SOURCESEL_PCNT2 0x00000011UL /**< Mode PCNT2 for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SOURCESEL_CMU 0x00000012UL /**< Mode CMU for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SOURCESEL_VDAC0 0x00000018UL /**< Mode VDAC0 for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SOURCESEL_CRYOTIMER 0x0000001AUL /**< Mode CRYOTIMER for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SOURCESEL_USART0 0x00000030UL /**< Mode USART0 for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SOURCESEL_USART1 0x00000031UL /**< Mode USART1 for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SOURCESEL_USART2 0x00000032UL /**< Mode USART2 for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SOURCESEL_USART3 0x00000033UL /**< Mode USART3 for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000003CUL /**< Mode TIMER0 for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SOURCESEL_TIMER1 0x0000003DUL /**< Mode TIMER1 for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SOURCESEL_WTIMER0 0x0000003EUL /**< Mode WTIMER0 for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SOURCESEL_WTIMER1 0x0000003FUL /**< Mode WTIMER1 for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SOURCESEL_CM4 0x00000043UL /**< Mode CM4 for PRS_CH_CTRL */ #define PRS_CH_CTRL_SOURCESEL_NONE (_PRS_CH_CTRL_SOURCESEL_NONE << 8) /**< Shifted mode NONE for PRS_CH_CTRL */ #define PRS_CH_CTRL_SOURCESEL_PRSL (_PRS_CH_CTRL_SOURCESEL_PRSL << 8) /**< Shifted mode PRSL for PRS_CH_CTRL */ #define PRS_CH_CTRL_SOURCESEL_PRSH (_PRS_CH_CTRL_SOURCESEL_PRSH << 8) /**< Shifted mode PRSH for PRS_CH_CTRL */ #define PRS_CH_CTRL_SOURCESEL_ACMP0 (_PRS_CH_CTRL_SOURCESEL_ACMP0 << 8) /**< Shifted mode ACMP0 for PRS_CH_CTRL */ #define PRS_CH_CTRL_SOURCESEL_ACMP1 (_PRS_CH_CTRL_SOURCESEL_ACMP1 << 8) /**< Shifted mode ACMP1 for PRS_CH_CTRL */ #define PRS_CH_CTRL_SOURCESEL_ADC0 (_PRS_CH_CTRL_SOURCESEL_ADC0 << 8) /**< Shifted mode ADC0 for PRS_CH_CTRL */ #define PRS_CH_CTRL_SOURCESEL_LESENSEL (_PRS_CH_CTRL_SOURCESEL_LESENSEL << 8) /**< Shifted mode LESENSEL for PRS_CH_CTRL */ #define PRS_CH_CTRL_SOURCESEL_LESENSEH (_PRS_CH_CTRL_SOURCESEL_LESENSEH << 8) /**< Shifted mode LESENSEH for PRS_CH_CTRL */ #define PRS_CH_CTRL_SOURCESEL_LESENSED (_PRS_CH_CTRL_SOURCESEL_LESENSED << 8) /**< Shifted mode LESENSED for PRS_CH_CTRL */ #define PRS_CH_CTRL_SOURCESEL_LESENSE (_PRS_CH_CTRL_SOURCESEL_LESENSE << 8) /**< Shifted mode LESENSE for PRS_CH_CTRL */ #define PRS_CH_CTRL_SOURCESEL_RTCC (_PRS_CH_CTRL_SOURCESEL_RTCC << 8) /**< Shifted mode RTCC for PRS_CH_CTRL */ #define PRS_CH_CTRL_SOURCESEL_GPIOL (_PRS_CH_CTRL_SOURCESEL_GPIOL << 8) /**< Shifted mode GPIOL for PRS_CH_CTRL */ #define PRS_CH_CTRL_SOURCESEL_GPIOH (_PRS_CH_CTRL_SOURCESEL_GPIOH << 8) /**< Shifted mode GPIOH for PRS_CH_CTRL */ #define PRS_CH_CTRL_SOURCESEL_LETIMER0 (_PRS_CH_CTRL_SOURCESEL_LETIMER0 << 8) /**< Shifted mode LETIMER0 for PRS_CH_CTRL */ #define PRS_CH_CTRL_SOURCESEL_PCNT0 (_PRS_CH_CTRL_SOURCESEL_PCNT0 << 8) /**< Shifted mode PCNT0 for PRS_CH_CTRL */ #define PRS_CH_CTRL_SOURCESEL_PCNT1 (_PRS_CH_CTRL_SOURCESEL_PCNT1 << 8) /**< Shifted mode PCNT1 for PRS_CH_CTRL */ #define PRS_CH_CTRL_SOURCESEL_PCNT2 (_PRS_CH_CTRL_SOURCESEL_PCNT2 << 8) /**< Shifted mode PCNT2 for PRS_CH_CTRL */ #define PRS_CH_CTRL_SOURCESEL_CMU (_PRS_CH_CTRL_SOURCESEL_CMU << 8) /**< Shifted mode CMU for PRS_CH_CTRL */ #define PRS_CH_CTRL_SOURCESEL_VDAC0 (_PRS_CH_CTRL_SOURCESEL_VDAC0 << 8) /**< Shifted mode VDAC0 for PRS_CH_CTRL */ #define PRS_CH_CTRL_SOURCESEL_CRYOTIMER (_PRS_CH_CTRL_SOURCESEL_CRYOTIMER << 8) /**< Shifted mode CRYOTIMER for PRS_CH_CTRL */ #define PRS_CH_CTRL_SOURCESEL_USART0 (_PRS_CH_CTRL_SOURCESEL_USART0 << 8) /**< Shifted mode USART0 for PRS_CH_CTRL */ #define PRS_CH_CTRL_SOURCESEL_USART1 (_PRS_CH_CTRL_SOURCESEL_USART1 << 8) /**< Shifted mode USART1 for PRS_CH_CTRL */ #define PRS_CH_CTRL_SOURCESEL_USART2 (_PRS_CH_CTRL_SOURCESEL_USART2 << 8) /**< Shifted mode USART2 for PRS_CH_CTRL */ #define PRS_CH_CTRL_SOURCESEL_USART3 (_PRS_CH_CTRL_SOURCESEL_USART3 << 8) /**< Shifted mode USART3 for PRS_CH_CTRL */ #define PRS_CH_CTRL_SOURCESEL_TIMER0 (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 8) /**< Shifted mode TIMER0 for PRS_CH_CTRL */ #define PRS_CH_CTRL_SOURCESEL_TIMER1 (_PRS_CH_CTRL_SOURCESEL_TIMER1 << 8) /**< Shifted mode TIMER1 for PRS_CH_CTRL */ #define PRS_CH_CTRL_SOURCESEL_WTIMER0 (_PRS_CH_CTRL_SOURCESEL_WTIMER0 << 8) /**< Shifted mode WTIMER0 for PRS_CH_CTRL */ #define PRS_CH_CTRL_SOURCESEL_WTIMER1 (_PRS_CH_CTRL_SOURCESEL_WTIMER1 << 8) /**< Shifted mode WTIMER1 for PRS_CH_CTRL */ #define PRS_CH_CTRL_SOURCESEL_CM4 (_PRS_CH_CTRL_SOURCESEL_CM4 << 8) /**< Shifted mode CM4 for PRS_CH_CTRL */ #define _PRS_CH_CTRL_EDSEL_SHIFT 20 /**< Shift value for PRS_EDSEL */ #define _PRS_CH_CTRL_EDSEL_MASK 0x300000UL /**< Bit mask for PRS_EDSEL */ #define _PRS_CH_CTRL_EDSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ #define _PRS_CH_CTRL_EDSEL_OFF 0x00000000UL /**< Mode OFF for PRS_CH_CTRL */ #define _PRS_CH_CTRL_EDSEL_POSEDGE 0x00000001UL /**< Mode POSEDGE for PRS_CH_CTRL */ #define _PRS_CH_CTRL_EDSEL_NEGEDGE 0x00000002UL /**< Mode NEGEDGE for PRS_CH_CTRL */ #define _PRS_CH_CTRL_EDSEL_BOTHEDGES 0x00000003UL /**< Mode BOTHEDGES for PRS_CH_CTRL */ #define PRS_CH_CTRL_EDSEL_DEFAULT (_PRS_CH_CTRL_EDSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ #define PRS_CH_CTRL_EDSEL_OFF (_PRS_CH_CTRL_EDSEL_OFF << 20) /**< Shifted mode OFF for PRS_CH_CTRL */ #define PRS_CH_CTRL_EDSEL_POSEDGE (_PRS_CH_CTRL_EDSEL_POSEDGE << 20) /**< Shifted mode POSEDGE for PRS_CH_CTRL */ #define PRS_CH_CTRL_EDSEL_NEGEDGE (_PRS_CH_CTRL_EDSEL_NEGEDGE << 20) /**< Shifted mode NEGEDGE for PRS_CH_CTRL */ #define PRS_CH_CTRL_EDSEL_BOTHEDGES (_PRS_CH_CTRL_EDSEL_BOTHEDGES << 20) /**< Shifted mode BOTHEDGES for PRS_CH_CTRL */ #define PRS_CH_CTRL_STRETCH (0x1UL << 25) /**< Stretch Channel Output */ #define _PRS_CH_CTRL_STRETCH_SHIFT 25 /**< Shift value for PRS_STRETCH */ #define _PRS_CH_CTRL_STRETCH_MASK 0x2000000UL /**< Bit mask for PRS_STRETCH */ #define _PRS_CH_CTRL_STRETCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ #define PRS_CH_CTRL_STRETCH_DEFAULT (_PRS_CH_CTRL_STRETCH_DEFAULT << 25) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ #define PRS_CH_CTRL_INV (0x1UL << 26) /**< Invert Channel */ #define _PRS_CH_CTRL_INV_SHIFT 26 /**< Shift value for PRS_INV */ #define _PRS_CH_CTRL_INV_MASK 0x4000000UL /**< Bit mask for PRS_INV */ #define _PRS_CH_CTRL_INV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ #define PRS_CH_CTRL_INV_DEFAULT (_PRS_CH_CTRL_INV_DEFAULT << 26) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ #define PRS_CH_CTRL_ORPREV (0x1UL << 27) /**< Or Previous */ #define _PRS_CH_CTRL_ORPREV_SHIFT 27 /**< Shift value for PRS_ORPREV */ #define _PRS_CH_CTRL_ORPREV_MASK 0x8000000UL /**< Bit mask for PRS_ORPREV */ #define _PRS_CH_CTRL_ORPREV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ #define PRS_CH_CTRL_ORPREV_DEFAULT (_PRS_CH_CTRL_ORPREV_DEFAULT << 27) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ #define PRS_CH_CTRL_ANDNEXT (0x1UL << 28) /**< And Next */ #define _PRS_CH_CTRL_ANDNEXT_SHIFT 28 /**< Shift value for PRS_ANDNEXT */ #define _PRS_CH_CTRL_ANDNEXT_MASK 0x10000000UL /**< Bit mask for PRS_ANDNEXT */ #define _PRS_CH_CTRL_ANDNEXT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ #define PRS_CH_CTRL_ANDNEXT_DEFAULT (_PRS_CH_CTRL_ANDNEXT_DEFAULT << 28) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ #define PRS_CH_CTRL_ASYNC (0x1UL << 30) /**< Asynchronous Reflex */ #define _PRS_CH_CTRL_ASYNC_SHIFT 30 /**< Shift value for PRS_ASYNC */ #define _PRS_CH_CTRL_ASYNC_MASK 0x40000000UL /**< Bit mask for PRS_ASYNC */ #define _PRS_CH_CTRL_ASYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ #define PRS_CH_CTRL_ASYNC_DEFAULT (_PRS_CH_CTRL_ASYNC_DEFAULT << 30) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ /** @} */ /** @} End of group EFR32MG12P_PRS */ /** @} End of group Parts */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_prs_ch.h.
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/***************************************************************************//** * @file * @brief EFR32MG12P_PRS_CH register and bit field definitions * @version 5.7.0 ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * SPDX-License-Identifier: Zlib * * The licensor of this software is Silicon Laboratories Inc. * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be * appreciated but is not required. * 2. Altered source versions must be plainly marked as such, and must not be * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * ******************************************************************************/ #if defined(__ICCARM__) #pragma system_include /* Treat file as system include file. */ #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang system_header /* Treat file as system include file. */ #endif /***************************************************************************//** * @addtogroup Parts * @{ ******************************************************************************/ /***************************************************************************//** * @brief PRS_CH PRS CH Register * @ingroup EFR32MG12P_PRS ******************************************************************************/ typedef struct { __IOM uint32_t CTRL; /**< Channel Control Register */ } PRS_CH_TypeDef; /** @} End of group Parts */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_prs_signals.h.
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/***************************************************************************//** * @file * @brief EFR32MG12P_PRS_SIGNALS register and bit field definitions * @version 5.7.0 ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * SPDX-License-Identifier: Zlib * * The licensor of this software is Silicon Laboratories Inc. * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be * appreciated but is not required. * 2. Altered source versions must be plainly marked as such, and must not be * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * ******************************************************************************/ #if defined(__ICCARM__) #pragma system_include /* Treat file as system include file. */ #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang system_header /* Treat file as system include file. */ #endif /***************************************************************************//** * @addtogroup Parts * @{ ******************************************************************************/ /***************************************************************************//** * @addtogroup EFR32MG12P_PRS * @{ * @addtogroup EFR32MG12P_PRS_Signals PRS Signals * @{ * @brief PRS Signal names ******************************************************************************/ #define PRS_PRS_CH0 ((1 << 8) + 0) /**< PRS PRS channel 0 */ #define PRS_PRS_CH1 ((1 << 8) + 1) /**< PRS PRS channel 1 */ #define PRS_PRS_CH2 ((1 << 8) + 2) /**< PRS PRS channel 2 */ #define PRS_PRS_CH3 ((1 << 8) + 3) /**< PRS PRS channel 3 */ #define PRS_PRS_CH4 ((1 << 8) + 4) /**< PRS PRS channel 4 */ #define PRS_PRS_CH5 ((1 << 8) + 5) /**< PRS PRS channel 5 */ #define PRS_PRS_CH6 ((1 << 8) + 6) /**< PRS PRS channel 6 */ #define PRS_PRS_CH7 ((1 << 8) + 7) /**< PRS PRS channel 7 */ #define PRS_PRS_CH8 ((2 << 8) + 0) /**< PRS PRS channel 8 */ #define PRS_PRS_CH9 ((2 << 8) + 1) /**< PRS PRS channel 9 */ #define PRS_PRS_CH10 ((2 << 8) + 2) /**< PRS PRS channel 10 */ #define PRS_PRS_CH11 ((2 << 8) + 3) /**< PRS PRS channel 11 */ #define PRS_ACMP0_OUT ((3 << 8) + 0) /**< PRS Analog comparator output */ #define PRS_ACMP1_OUT ((4 << 8) + 0) /**< PRS Analog comparator output */ #define PRS_ADC0_SINGLE ((5 << 8) + 0) /**< PRS ADC single conversion done */ #define PRS_ADC0_SCAN ((5 << 8) + 1) /**< PRS ADC scan conversion done */ #define PRS_LESENSE_SCANRES0 ((7 << 8) + 0) /**< PRS LESENSE SCANRES register, bit 0 */ #define PRS_LESENSE_SCANRES1 ((7 << 8) + 1) /**< PRS LESENSE SCANRES register, bit 1 */ #define PRS_LESENSE_SCANRES2 ((7 << 8) + 2) /**< PRS LESENSE SCANRES register, bit 2 */ #define PRS_LESENSE_SCANRES3 ((7 << 8) + 3) /**< PRS LESENSE SCANRES register, bit 3 */ #define PRS_LESENSE_SCANRES4 ((7 << 8) + 4) /**< PRS LESENSE SCANRES register, bit 4 */ #define PRS_LESENSE_SCANRES5 ((7 << 8) + 5) /**< PRS LESENSE SCANRES register, bit 5 */ #define PRS_LESENSE_SCANRES6 ((7 << 8) + 6) /**< PRS LESENSE SCANRES register, bit 6 */ #define PRS_LESENSE_SCANRES7 ((7 << 8) + 7) /**< PRS LESENSE SCANRES register, bit 7 */ #define PRS_LESENSE_SCANRES8 ((8 << 8) + 0) /**< PRS LESENSE SCANRES register, bit 8 */ #define PRS_LESENSE_SCANRES9 ((8 << 8) + 1) /**< PRS LESENSE SCANRES register, bit 9 */ #define PRS_LESENSE_SCANRES10 ((8 << 8) + 2) /**< PRS LESENSE SCANRES register, bit 10 */ #define PRS_LESENSE_SCANRES11 ((8 << 8) + 3) /**< PRS LESENSE SCANRES register, bit 11 */ #define PRS_LESENSE_SCANRES12 ((8 << 8) + 4) /**< PRS LESENSE SCANRES register, bit 12 */ #define PRS_LESENSE_SCANRES13 ((8 << 8) + 5) /**< PRS LESENSE SCANRES register, bit 13 */ #define PRS_LESENSE_SCANRES14 ((8 << 8) + 6) /**< PRS LESENSE SCANRES register, bit 14 */ #define PRS_LESENSE_SCANRES15 ((8 << 8) + 7) /**< PRS LESENSE SCANRES register, bit 15 */ #define PRS_LESENSE_DEC0 ((9 << 8) + 0) /**< PRS LESENSE Decoder PRS out 0 */ #define PRS_LESENSE_DEC1 ((9 << 8) + 1) /**< PRS LESENSE Decoder PRS out 1 */ #define PRS_LESENSE_DEC2 ((9 << 8) + 2) /**< PRS LESENSE Decoder PRS out 2 */ #define PRS_LESENSE_DECCMP ((9 << 8) + 3) /**< PRS LESENSE Decoder PRS compare value match channel */ #define PRS_LESENSE_MEASACT ((10 << 8) + 0) /**< PRS LESENSE Measurement active */ #define PRS_RTCC_CCV0 ((11 << 8) + 1) /**< PRS RTCC Compare 0 */ #define PRS_RTCC_CCV1 ((11 << 8) + 2) /**< PRS RTCC Compare 1 */ #define PRS_RTCC_CCV2 ((11 << 8) + 3) /**< PRS RTCC Compare 2 */ #define PRS_GPIO_PIN0 ((12 << 8) + 0) /**< PRS GPIO pin 0 */ #define PRS_GPIO_PIN1 ((12 << 8) + 1) /**< PRS GPIO pin 1 */ #define PRS_GPIO_PIN2 ((12 << 8) + 2) /**< PRS GPIO pin 2 */ #define PRS_GPIO_PIN3 ((12 << 8) + 3) /**< PRS GPIO pin 3 */ #define PRS_GPIO_PIN4 ((12 << 8) + 4) /**< PRS GPIO pin 4 */ #define PRS_GPIO_PIN5 ((12 << 8) + 5) /**< PRS GPIO pin 5 */ #define PRS_GPIO_PIN6 ((12 << 8) + 6) /**< PRS GPIO pin 6 */ #define PRS_GPIO_PIN7 ((12 << 8) + 7) /**< PRS GPIO pin 7 */ #define PRS_GPIO_PIN8 ((13 << 8) + 0) /**< PRS GPIO pin 8 */ #define PRS_GPIO_PIN9 ((13 << 8) + 1) /**< PRS GPIO pin 9 */ #define PRS_GPIO_PIN10 ((13 << 8) + 2) /**< PRS GPIO pin 10 */ #define PRS_GPIO_PIN11 ((13 << 8) + 3) /**< PRS GPIO pin 11 */ #define PRS_GPIO_PIN12 ((13 << 8) + 4) /**< PRS GPIO pin 12 */ #define PRS_GPIO_PIN13 ((13 << 8) + 5) /**< PRS GPIO pin 13 */ #define PRS_GPIO_PIN14 ((13 << 8) + 6) /**< PRS GPIO pin 14 */ #define PRS_GPIO_PIN15 ((13 << 8) + 7) /**< PRS GPIO pin 15 */ #define PRS_LETIMER0_CH0 ((14 << 8) + 0) /**< PRS LETIMER CH0 Out */ #define PRS_LETIMER0_CH1 ((14 << 8) + 1) /**< PRS LETIMER CH1 Out */ #define PRS_PCNT0_TCC ((15 << 8) + 0) /**< PRS PCNT0 Triggered compare match */ #define PRS_PCNT0_UFOF ((15 << 8) + 1) /**< PRS PCNT0 Counter overflow or underflow */ #define PRS_PCNT0_DIR ((15 << 8) + 2) /**< PRS PCNT0 Counter direction */ #define PRS_PCNT1_TCC ((16 << 8) + 0) /**< PRS PCNT1 Triggered compare match */ #define PRS_PCNT1_UFOF ((16 << 8) + 1) /**< PRS PCNT1 Counter overflow or underflow */ #define PRS_PCNT1_DIR ((16 << 8) + 2) /**< PRS PCNT1 Counter direction */ #define PRS_PCNT2_TCC ((17 << 8) + 0) /**< PRS PCNT2 Triggered compare match */ #define PRS_PCNT2_UFOF ((17 << 8) + 1) /**< PRS PCNT2 Counter overflow or underflow */ #define PRS_PCNT2_DIR ((17 << 8) + 2) /**< PRS PCNT2 Counter direction */ #define PRS_CMU_CLKOUT0 ((18 << 8) + 0) /**< PRS Clock Output 0 */ #define PRS_CMU_CLKOUT1 ((18 << 8) + 1) /**< PRS Clock Output 1 */ #define PRS_VDAC0_CH0 ((24 << 8) + 0) /**< PRS DAC ch0 conversion done */ #define PRS_VDAC0_CH1 ((24 << 8) + 1) /**< PRS DAC ch1 conversion done */ #define PRS_VDAC0_OPA0 ((24 << 8) + 2) /**< PRS OPA0 warmedup or outputvalid based on OPA0PRSOUTMODE mode in OPACTRL. */ #define PRS_VDAC0_OPA1 ((24 << 8) + 3) /**< PRS OPA1 warmedup or outputvalid based on OPA1PRSOUTMODE mode in OPACTRL. */ #define PRS_VDAC0_OPA2 ((24 << 8) + 4) /**< PRS OPA2 warmedup or outputvalid based on OPA2PRSOUTMODE mode in OPACTRL. */ #define PRS_RFSENSE_WU ((25 << 8) + 0) /**< PRS RFSENSE Output */ #define PRS_CRYOTIMER_PERIOD ((26 << 8) + 0) /**< PRS CRYOTIMER Output */ #define PRS_USART0_IRTX ((48 << 8) + 0) /**< PRS USART 0 IRDA out */ #define PRS_USART0_TXC ((48 << 8) + 1) /**< PRS USART 0 TX complete */ #define PRS_USART0_RXDATAV ((48 << 8) + 2) /**< PRS USART 0 RX Data Valid */ #define PRS_USART0_RTS ((48 << 8) + 3) /**< PRS USART 0 RTS */ #define PRS_USART0_TX ((48 << 8) + 5) /**< PRS USART 0 TX */ #define PRS_USART0_CS ((48 << 8) + 6) /**< PRS USART 0 CS */ #define PRS_USART1_TXC ((49 << 8) + 1) /**< PRS USART 1 TX complete */ #define PRS_USART1_RXDATAV ((49 << 8) + 2) /**< PRS USART 1 RX Data Valid */ #define PRS_USART1_RTS ((49 << 8) + 3) /**< PRS USART 1 RTS */ #define PRS_USART1_TX ((49 << 8) + 5) /**< PRS USART 1 TX */ #define PRS_USART1_CS ((49 << 8) + 6) /**< PRS USART 1 CS */ #define PRS_USART2_IRTX ((50 << 8) + 0) /**< PRS USART 2 IRDA out */ #define PRS_USART2_TXC ((50 << 8) + 1) /**< PRS USART 2 TX complete */ #define PRS_USART2_RXDATAV ((50 << 8) + 2) /**< PRS USART 2 RX Data Valid */ #define PRS_USART2_RTS ((50 << 8) + 3) /**< PRS USART 2 RTS */ #define PRS_USART2_TX ((50 << 8) + 5) /**< PRS USART 2 TX */ #define PRS_USART2_CS ((50 << 8) + 6) /**< PRS USART 2 CS */ #define PRS_USART3_TXC ((51 << 8) + 1) /**< PRS USART 3 TX complete */ #define PRS_USART3_RXDATAV ((51 << 8) + 2) /**< PRS USART 3 RX Data Valid */ #define PRS_USART3_RTS ((51 << 8) + 3) /**< PRS USART 3 RTS */ #define PRS_USART3_TX ((51 << 8) + 5) /**< PRS USART 3 TX */ #define PRS_USART3_CS ((51 << 8) + 6) /**< PRS USART 3 CS */ #define PRS_TIMER0_UF ((60 << 8) + 0) /**< PRS Timer 0 Underflow */ #define PRS_TIMER0_OF ((60 << 8) + 1) /**< PRS Timer 0 Overflow */ #define PRS_TIMER0_CC0 ((60 << 8) + 2) /**< PRS Timer 0 Compare/Capture 0 */ #define PRS_TIMER0_CC1 ((60 << 8) + 3) /**< PRS Timer 0 Compare/Capture 1 */ #define PRS_TIMER0_CC2 ((60 << 8) + 4) /**< PRS Timer 0 Compare/Capture 2 */ #define PRS_TIMER1_UF ((61 << 8) + 0) /**< PRS Timer 1 Underflow */ #define PRS_TIMER1_OF ((61 << 8) + 1) /**< PRS Timer 1 Overflow */ #define PRS_TIMER1_CC0 ((61 << 8) + 2) /**< PRS Timer 1 Compare/Capture 0 */ #define PRS_TIMER1_CC1 ((61 << 8) + 3) /**< PRS Timer 1 Compare/Capture 1 */ #define PRS_TIMER1_CC2 ((61 << 8) + 4) /**< PRS Timer 1 Compare/Capture 2 */ #define PRS_TIMER1_CC3 ((61 << 8) + 5) /**< PRS Timer 1 Compare/Capture 3 */ #define PRS_WTIMER0_UF ((62 << 8) + 0) /**< PRS Timer 2 Underflow */ #define PRS_WTIMER0_OF ((62 << 8) + 1) /**< PRS Timer 2 Overflow */ #define PRS_WTIMER0_CC0 ((62 << 8) + 2) /**< PRS Timer 2 Compare/Capture 0 */ #define PRS_WTIMER0_CC1 ((62 << 8) + 3) /**< PRS Timer 2 Compare/Capture 1 */ #define PRS_WTIMER0_CC2 ((62 << 8) + 4) /**< PRS Timer 2 Compare/Capture 2 */ #define PRS_WTIMER1_UF ((63 << 8) + 0) /**< PRS Timer 3 Underflow */ #define PRS_WTIMER1_OF ((63 << 8) + 1) /**< PRS Timer 3 Overflow */ #define PRS_WTIMER1_CC0 ((63 << 8) + 2) /**< PRS Timer 3 Compare/Capture 0 */ #define PRS_WTIMER1_CC1 ((63 << 8) + 3) /**< PRS Timer 3 Compare/Capture 1 */ #define PRS_WTIMER1_CC2 ((63 << 8) + 4) /**< PRS Timer 3 Compare/Capture 2 */ #define PRS_WTIMER1_CC3 ((63 << 8) + 5) /**< PRS Timer 3 Compare/Capture 3 */ #define PRS_CM4_TXEV ((67 << 8) + 0) /**< PRS */ #define PRS_CM4_ICACHEPCHITSOF ((67 << 8) + 1) /**< PRS */ #define PRS_CM4_ICACHEPCMISSESOF ((67 << 8) + 2) /**< PRS */ #define PRS_RAC_ACTIVE ((81 << 8) + 0) /**< PRS RAC is active */ #define PRS_RAC_TX ((81 << 8) + 1) /**< PRS RAC is in TX */ #define PRS_RAC_RX ((81 << 8) + 2) /**< PRS RAC is in RX */ #define PRS_RAC_LNAEN ((81 << 8) + 3) /**< PRS LNA enable */ #define PRS_RAC_PAEN ((81 << 8) + 4) /**< PRS PA enable */ #define PRS_PROTIMER_LBTS ((84 << 8) + 5) /**< PRS Listen Before Talk Success */ #define PRS_PROTIMER_LBTR ((84 << 8) + 6) /**< PRS Listen Before Talk Retry */ #define PRS_PROTIMER_LBTF ((84 << 8) + 7) /**< PRS Listen Before Talk Failure */ #define PRS_MODEM_FRAMEDET ((86 << 8) + 0) /**< PRS Frame detected */ #define PRS_MODEM_PREDET ((86 << 8) + 1) /**< PRS Receive preamble detected */ #define PRS_MODEM_TIMDET ((86 << 8) + 2) /**< PRS Receive timing detected */ #define PRS_MODEM_FRAMESENT ((86 << 8) + 3) /**< PRS Entire frame transmitted */ #define PRS_MODEM_SYNCSENT ((86 << 8) + 4) /**< PRS Syncword transmitted */ #define PRS_MODEM_PRESENT ((86 << 8) + 5) /**< PRS Preamble transmitted */ #define PRS_MODEM_ANT0 ((87 << 8) + 5) /**< PRS Antenna 0 select */ #define PRS_MODEM_ANT1 ((87 << 8) + 6) /**< PRS Antenna 1 select */ /** @} */ /** @} End of group EFR32MG12P_PRS */ /** @} End of group Parts */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_rmu.h.
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/***************************************************************************//** * @file * @brief EFR32MG12P_RMU register and bit field definitions * @version 5.7.0 ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * SPDX-License-Identifier: Zlib * * The licensor of this software is Silicon Laboratories Inc. * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be * appreciated but is not required. * 2. Altered source versions must be plainly marked as such, and must not be * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * ******************************************************************************/ #if defined(__ICCARM__) #pragma system_include /* Treat file as system include file. */ #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang system_header /* Treat file as system include file. */ #endif /***************************************************************************//** * @addtogroup Parts * @{ ******************************************************************************/ /***************************************************************************//** * @defgroup EFR32MG12P_RMU RMU * @{ * @brief EFR32MG12P_RMU Register Declaration ******************************************************************************/ /** RMU Register Declaration */ typedef struct { __IOM uint32_t CTRL; /**< Control Register */ __IM uint32_t RSTCAUSE; /**< Reset Cause Register */ __IOM uint32_t CMD; /**< Command Register */ __IOM uint32_t RST; /**< Reset Control Register */ __IOM uint32_t LOCK; /**< Configuration Lock Register */ } RMU_TypeDef; /** @} */ /***************************************************************************//** * @addtogroup EFR32MG12P_RMU * @{ * @defgroup EFR32MG12P_RMU_BitFields RMU Bit Fields * @{ ******************************************************************************/ /* Bit fields for RMU CTRL */ #define _RMU_CTRL_RESETVALUE 0x00004204UL /**< Default value for RMU_CTRL */ #define _RMU_CTRL_MASK 0x03007777UL /**< Mask for RMU_CTRL */ #define _RMU_CTRL_WDOGRMODE_SHIFT 0 /**< Shift value for RMU_WDOGRMODE */ #define _RMU_CTRL_WDOGRMODE_MASK 0x7UL /**< Bit mask for RMU_WDOGRMODE */ #define _RMU_CTRL_WDOGRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for RMU_CTRL */ #define _RMU_CTRL_WDOGRMODE_LIMITED 0x00000001UL /**< Mode LIMITED for RMU_CTRL */ #define _RMU_CTRL_WDOGRMODE_EXTENDED 0x00000002UL /**< Mode EXTENDED for RMU_CTRL */ #define _RMU_CTRL_WDOGRMODE_DEFAULT 0x00000004UL /**< Mode DEFAULT for RMU_CTRL */ #define _RMU_CTRL_WDOGRMODE_FULL 0x00000004UL /**< Mode FULL for RMU_CTRL */ #define RMU_CTRL_WDOGRMODE_DISABLED (_RMU_CTRL_WDOGRMODE_DISABLED << 0) /**< Shifted mode DISABLED for RMU_CTRL */ #define RMU_CTRL_WDOGRMODE_LIMITED (_RMU_CTRL_WDOGRMODE_LIMITED << 0) /**< Shifted mode LIMITED for RMU_CTRL */ #define RMU_CTRL_WDOGRMODE_EXTENDED (_RMU_CTRL_WDOGRMODE_EXTENDED << 0) /**< Shifted mode EXTENDED for RMU_CTRL */ #define RMU_CTRL_WDOGRMODE_DEFAULT (_RMU_CTRL_WDOGRMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for RMU_CTRL */ #define RMU_CTRL_WDOGRMODE_FULL (_RMU_CTRL_WDOGRMODE_FULL << 0) /**< Shifted mode FULL for RMU_CTRL */ #define _RMU_CTRL_LOCKUPRMODE_SHIFT 4 /**< Shift value for RMU_LOCKUPRMODE */ #define _RMU_CTRL_LOCKUPRMODE_MASK 0x70UL /**< Bit mask for RMU_LOCKUPRMODE */ #define _RMU_CTRL_LOCKUPRMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_CTRL */ #define _RMU_CTRL_LOCKUPRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for RMU_CTRL */ #define _RMU_CTRL_LOCKUPRMODE_LIMITED 0x00000001UL /**< Mode LIMITED for RMU_CTRL */ #define _RMU_CTRL_LOCKUPRMODE_EXTENDED 0x00000002UL /**< Mode EXTENDED for RMU_CTRL */ #define _RMU_CTRL_LOCKUPRMODE_FULL 0x00000004UL /**< Mode FULL for RMU_CTRL */ #define RMU_CTRL_LOCKUPRMODE_DEFAULT (_RMU_CTRL_LOCKUPRMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for RMU_CTRL */ #define RMU_CTRL_LOCKUPRMODE_DISABLED (_RMU_CTRL_LOCKUPRMODE_DISABLED << 4) /**< Shifted mode DISABLED for RMU_CTRL */ #define RMU_CTRL_LOCKUPRMODE_LIMITED (_RMU_CTRL_LOCKUPRMODE_LIMITED << 4) /**< Shifted mode LIMITED for RMU_CTRL */ #define RMU_CTRL_LOCKUPRMODE_EXTENDED (_RMU_CTRL_LOCKUPRMODE_EXTENDED << 4) /**< Shifted mode EXTENDED for RMU_CTRL */ #define RMU_CTRL_LOCKUPRMODE_FULL (_RMU_CTRL_LOCKUPRMODE_FULL << 4) /**< Shifted mode FULL for RMU_CTRL */ #define _RMU_CTRL_SYSRMODE_SHIFT 8 /**< Shift value for RMU_SYSRMODE */ #define _RMU_CTRL_SYSRMODE_MASK 0x700UL /**< Bit mask for RMU_SYSRMODE */ #define _RMU_CTRL_SYSRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for RMU_CTRL */ #define _RMU_CTRL_SYSRMODE_LIMITED 0x00000001UL /**< Mode LIMITED for RMU_CTRL */ #define _RMU_CTRL_SYSRMODE_DEFAULT 0x00000002UL /**< Mode DEFAULT for RMU_CTRL */ #define _RMU_CTRL_SYSRMODE_EXTENDED 0x00000002UL /**< Mode EXTENDED for RMU_CTRL */ #define _RMU_CTRL_SYSRMODE_FULL 0x00000004UL /**< Mode FULL for RMU_CTRL */ #define RMU_CTRL_SYSRMODE_DISABLED (_RMU_CTRL_SYSRMODE_DISABLED << 8) /**< Shifted mode DISABLED for RMU_CTRL */ #define RMU_CTRL_SYSRMODE_LIMITED (_RMU_CTRL_SYSRMODE_LIMITED << 8) /**< Shifted mode LIMITED for RMU_CTRL */ #define RMU_CTRL_SYSRMODE_DEFAULT (_RMU_CTRL_SYSRMODE_DEFAULT << 8) /**< Shifted mode DEFAULT for RMU_CTRL */ #define RMU_CTRL_SYSRMODE_EXTENDED (_RMU_CTRL_SYSRMODE_EXTENDED << 8) /**< Shifted mode EXTENDED for RMU_CTRL */ #define RMU_CTRL_SYSRMODE_FULL (_RMU_CTRL_SYSRMODE_FULL << 8) /**< Shifted mode FULL for RMU_CTRL */ #define _RMU_CTRL_PINRMODE_SHIFT 12 /**< Shift value for RMU_PINRMODE */ #define _RMU_CTRL_PINRMODE_MASK 0x7000UL /**< Bit mask for RMU_PINRMODE */ #define _RMU_CTRL_PINRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for RMU_CTRL */ #define _RMU_CTRL_PINRMODE_LIMITED 0x00000001UL /**< Mode LIMITED for RMU_CTRL */ #define _RMU_CTRL_PINRMODE_EXTENDED 0x00000002UL /**< Mode EXTENDED for RMU_CTRL */ #define _RMU_CTRL_PINRMODE_DEFAULT 0x00000004UL /**< Mode DEFAULT for RMU_CTRL */ #define _RMU_CTRL_PINRMODE_FULL 0x00000004UL /**< Mode FULL for RMU_CTRL */ #define RMU_CTRL_PINRMODE_DISABLED (_RMU_CTRL_PINRMODE_DISABLED << 12) /**< Shifted mode DISABLED for RMU_CTRL */ #define RMU_CTRL_PINRMODE_LIMITED (_RMU_CTRL_PINRMODE_LIMITED << 12) /**< Shifted mode LIMITED for RMU_CTRL */ #define RMU_CTRL_PINRMODE_EXTENDED (_RMU_CTRL_PINRMODE_EXTENDED << 12) /**< Shifted mode EXTENDED for RMU_CTRL */ #define RMU_CTRL_PINRMODE_DEFAULT (_RMU_CTRL_PINRMODE_DEFAULT << 12) /**< Shifted mode DEFAULT for RMU_CTRL */ #define RMU_CTRL_PINRMODE_FULL (_RMU_CTRL_PINRMODE_FULL << 12) /**< Shifted mode FULL for RMU_CTRL */ #define _RMU_CTRL_RESETSTATE_SHIFT 24 /**< Shift value for RMU_RESETSTATE */ #define _RMU_CTRL_RESETSTATE_MASK 0x3000000UL /**< Bit mask for RMU_RESETSTATE */ #define _RMU_CTRL_RESETSTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_CTRL */ #define RMU_CTRL_RESETSTATE_DEFAULT (_RMU_CTRL_RESETSTATE_DEFAULT << 24) /**< Shifted mode DEFAULT for RMU_CTRL */ /* Bit fields for RMU RSTCAUSE */ #define _RMU_RSTCAUSE_RESETVALUE 0x00000000UL /**< Default value for RMU_RSTCAUSE */ #define _RMU_RSTCAUSE_MASK 0x00010F1DUL /**< Mask for RMU_RSTCAUSE */ #define RMU_RSTCAUSE_PORST (0x1UL << 0) /**< Power on Reset */ #define _RMU_RSTCAUSE_PORST_SHIFT 0 /**< Shift value for RMU_PORST */ #define _RMU_RSTCAUSE_PORST_MASK 0x1UL /**< Bit mask for RMU_PORST */ #define _RMU_RSTCAUSE_PORST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ #define RMU_RSTCAUSE_PORST_DEFAULT (_RMU_RSTCAUSE_PORST_DEFAULT << 0) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ #define RMU_RSTCAUSE_AVDDBOD (0x1UL << 2) /**< Brown Out Detector AVDD Reset */ #define _RMU_RSTCAUSE_AVDDBOD_SHIFT 2 /**< Shift value for RMU_AVDDBOD */ #define _RMU_RSTCAUSE_AVDDBOD_MASK 0x4UL /**< Bit mask for RMU_AVDDBOD */ #define _RMU_RSTCAUSE_AVDDBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ #define RMU_RSTCAUSE_AVDDBOD_DEFAULT (_RMU_RSTCAUSE_AVDDBOD_DEFAULT << 2) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ #define RMU_RSTCAUSE_DVDDBOD (0x1UL << 3) /**< Brown Out Detector DVDD Reset */ #define _RMU_RSTCAUSE_DVDDBOD_SHIFT 3 /**< Shift value for RMU_DVDDBOD */ #define _RMU_RSTCAUSE_DVDDBOD_MASK 0x8UL /**< Bit mask for RMU_DVDDBOD */ #define _RMU_RSTCAUSE_DVDDBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ #define RMU_RSTCAUSE_DVDDBOD_DEFAULT (_RMU_RSTCAUSE_DVDDBOD_DEFAULT << 3) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ #define RMU_RSTCAUSE_DECBOD (0x1UL << 4) /**< Brown Out Detector Decouple Domain Reset */ #define _RMU_RSTCAUSE_DECBOD_SHIFT 4 /**< Shift value for RMU_DECBOD */ #define _RMU_RSTCAUSE_DECBOD_MASK 0x10UL /**< Bit mask for RMU_DECBOD */ #define _RMU_RSTCAUSE_DECBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ #define RMU_RSTCAUSE_DECBOD_DEFAULT (_RMU_RSTCAUSE_DECBOD_DEFAULT << 4) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ #define RMU_RSTCAUSE_EXTRST (0x1UL << 8) /**< External Pin Reset */ #define _RMU_RSTCAUSE_EXTRST_SHIFT 8 /**< Shift value for RMU_EXTRST */ #define _RMU_RSTCAUSE_EXTRST_MASK 0x100UL /**< Bit mask for RMU_EXTRST */ #define _RMU_RSTCAUSE_EXTRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ #define RMU_RSTCAUSE_EXTRST_DEFAULT (_RMU_RSTCAUSE_EXTRST_DEFAULT << 8) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ #define RMU_RSTCAUSE_LOCKUPRST (0x1UL << 9) /**< LOCKUP Reset */ #define _RMU_RSTCAUSE_LOCKUPRST_SHIFT 9 /**< Shift value for RMU_LOCKUPRST */ #define _RMU_RSTCAUSE_LOCKUPRST_MASK 0x200UL /**< Bit mask for RMU_LOCKUPRST */ #define _RMU_RSTCAUSE_LOCKUPRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ #define RMU_RSTCAUSE_LOCKUPRST_DEFAULT (_RMU_RSTCAUSE_LOCKUPRST_DEFAULT << 9) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ #define RMU_RSTCAUSE_SYSREQRST (0x1UL << 10) /**< System Request Reset */ #define _RMU_RSTCAUSE_SYSREQRST_SHIFT 10 /**< Shift value for RMU_SYSREQRST */ #define _RMU_RSTCAUSE_SYSREQRST_MASK 0x400UL /**< Bit mask for RMU_SYSREQRST */ #define _RMU_RSTCAUSE_SYSREQRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ #define RMU_RSTCAUSE_SYSREQRST_DEFAULT (_RMU_RSTCAUSE_SYSREQRST_DEFAULT << 10) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ #define RMU_RSTCAUSE_WDOGRST (0x1UL << 11) /**< Watchdog Reset */ #define _RMU_RSTCAUSE_WDOGRST_SHIFT 11 /**< Shift value for RMU_WDOGRST */ #define _RMU_RSTCAUSE_WDOGRST_MASK 0x800UL /**< Bit mask for RMU_WDOGRST */ #define _RMU_RSTCAUSE_WDOGRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ #define RMU_RSTCAUSE_WDOGRST_DEFAULT (_RMU_RSTCAUSE_WDOGRST_DEFAULT << 11) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ #define RMU_RSTCAUSE_EM4RST (0x1UL << 16) /**< EM4 Reset */ #define _RMU_RSTCAUSE_EM4RST_SHIFT 16 /**< Shift value for RMU_EM4RST */ #define _RMU_RSTCAUSE_EM4RST_MASK 0x10000UL /**< Bit mask for RMU_EM4RST */ #define _RMU_RSTCAUSE_EM4RST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ #define RMU_RSTCAUSE_EM4RST_DEFAULT (_RMU_RSTCAUSE_EM4RST_DEFAULT << 16) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ /* Bit fields for RMU CMD */ #define _RMU_CMD_RESETVALUE 0x00000000UL /**< Default value for RMU_CMD */ #define _RMU_CMD_MASK 0x00000001UL /**< Mask for RMU_CMD */ #define RMU_CMD_RCCLR (0x1UL << 0) /**< Reset Cause Clear */ #define _RMU_CMD_RCCLR_SHIFT 0 /**< Shift value for RMU_RCCLR */ #define _RMU_CMD_RCCLR_MASK 0x1UL /**< Bit mask for RMU_RCCLR */ #define _RMU_CMD_RCCLR_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_CMD */ #define RMU_CMD_RCCLR_DEFAULT (_RMU_CMD_RCCLR_DEFAULT << 0) /**< Shifted mode DEFAULT for RMU_CMD */ /* Bit fields for RMU RST */ #define _RMU_RST_RESETVALUE 0x00000000UL /**< Default value for RMU_RST */ #define _RMU_RST_MASK 0x00000000UL /**< Mask for RMU_RST */ /* Bit fields for RMU LOCK */ #define _RMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for RMU_LOCK */ #define _RMU_LOCK_MASK 0x0000FFFFUL /**< Mask for RMU_LOCK */ #define _RMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for RMU_LOCKKEY */ #define _RMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for RMU_LOCKKEY */ #define _RMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_LOCK */ #define _RMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for RMU_LOCK */ #define _RMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for RMU_LOCK */ #define _RMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for RMU_LOCK */ #define _RMU_LOCK_LOCKKEY_UNLOCK 0x0000E084UL /**< Mode UNLOCK for RMU_LOCK */ #define RMU_LOCK_LOCKKEY_DEFAULT (_RMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for RMU_LOCK */ #define RMU_LOCK_LOCKKEY_LOCK (_RMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for RMU_LOCK */ #define RMU_LOCK_LOCKKEY_UNLOCKED (_RMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for RMU_LOCK */ #define RMU_LOCK_LOCKKEY_LOCKED (_RMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for RMU_LOCK */ #define RMU_LOCK_LOCKKEY_UNLOCK (_RMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for RMU_LOCK */ /** @} */ /** @} End of group EFR32MG12P_RMU */ /** @} End of group Parts */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_romtable.h.
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/***************************************************************************//** * @file * @brief EFR32MG12P_ROMTABLE register and bit field definitions * @version 5.7.0 ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * SPDX-License-Identifier: Zlib * * The licensor of this software is Silicon Laboratories Inc. * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be * appreciated but is not required. * 2. Altered source versions must be plainly marked as such, and must not be * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * ******************************************************************************/ #if defined(__ICCARM__) #pragma system_include /* Treat file as system include file. */ #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang system_header /* Treat file as system include file. */ #endif /***************************************************************************//** * @addtogroup Parts * @{ ******************************************************************************/ /***************************************************************************//** * @defgroup EFR32MG12P_ROMTABLE ROM Table, Chip Revision Information * @{ * @brief Chip Information, Revision numbers ******************************************************************************/ /** ROMTABLE Register Declaration */ typedef struct { __IM uint32_t PID4; /**< JEP_106_BANK */ __IM uint32_t PID5; /**< Unused */ __IM uint32_t PID6; /**< Unused */ __IM uint32_t PID7; /**< Unused */ __IM uint32_t PID0; /**< Chip family LSB, chip major revision */ __IM uint32_t PID1; /**< JEP_106_NO, Chip family MSB */ __IM uint32_t PID2; /**< Chip minor rev MSB, JEP_106_PRESENT, JEP_106_NO */ __IM uint32_t PID3; /**< Chip minor rev LSB */ __IM uint32_t CID0; /**< Unused */ } ROMTABLE_TypeDef; /** @} */ /***************************************************************************//** * @addtogroup EFR32MG12P_ROMTABLE * @{ * @defgroup EFR32MG12P_ROMTABLE_BitFields ROM Table Bit Field definitions * @{ ******************************************************************************/ /* Bit fields for EFR32MG12P_ROMTABLE */ #define _ROMTABLE_PID0_FAMILYLSB_MASK 0x000000C0UL /**< Least Significant Bits [1:0] of CHIP FAMILY, mask */ #define _ROMTABLE_PID0_FAMILYLSB_SHIFT 6 /**< Least Significant Bits [1:0] of CHIP FAMILY, shift */ #define _ROMTABLE_PID0_REVMAJOR_MASK 0x0000003FUL /**< CHIP MAJOR Revison, mask */ #define _ROMTABLE_PID0_REVMAJOR_SHIFT 0 /**< CHIP MAJOR Revison, shift */ #define _ROMTABLE_PID1_FAMILYMSB_MASK 0x0000000FUL /**< Most Significant Bits [5:2] of CHIP FAMILY, mask */ #define _ROMTABLE_PID1_FAMILYMSB_SHIFT 0 /**< Most Significant Bits [5:2] of CHIP FAMILY, shift */ #define _ROMTABLE_PID2_REVMINORMSB_MASK 0x000000F0UL /**< Most Significant Bits [7:4] of CHIP MINOR revision, mask */ #define _ROMTABLE_PID2_REVMINORMSB_SHIFT 4 /**< Most Significant Bits [7:4] of CHIP MINOR revision, mask */ #define _ROMTABLE_PID3_REVMINORLSB_MASK 0x000000F0UL /**< Least Significant Bits [3:0] of CHIP MINOR revision, mask */ #define _ROMTABLE_PID3_REVMINORLSB_SHIFT 4 /**< Least Significant Bits [3:0] of CHIP MINOR revision, shift */ /** @} */ /** @} End of group EFR32MG12P_ROMTABLE */ /** @} End of group Parts */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_rtcc.h.
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/***************************************************************************//** * @file * @brief EFR32MG12P_RTCC register and bit field definitions * @version 5.7.0 ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * SPDX-License-Identifier: Zlib * * The licensor of this software is Silicon Laboratories Inc. * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be * appreciated but is not required. * 2. Altered source versions must be plainly marked as such, and must not be * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * ******************************************************************************/ #if defined(__ICCARM__) #pragma system_include /* Treat file as system include file. */ #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang system_header /* Treat file as system include file. */ #endif /***************************************************************************//** * @addtogroup Parts * @{ ******************************************************************************/ /***************************************************************************//** * @defgroup EFR32MG12P_RTCC RTCC * @{ * @brief EFR32MG12P_RTCC Register Declaration ******************************************************************************/ /** RTCC Register Declaration */ typedef struct { __IOM uint32_t CTRL; /**< Control Register */ __IOM uint32_t PRECNT; /**< Pre-Counter Value Register */ __IOM uint32_t CNT; /**< Counter Value Register */ __IM uint32_t COMBCNT; /**< Combined Pre-Counter and Counter Value Register */ __IOM uint32_t TIME; /**< Time of Day Register */ __IOM uint32_t DATE; /**< Date Register */ __IM uint32_t IF; /**< RTCC Interrupt Flags */ __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ __IOM uint32_t IEN; /**< Interrupt Enable Register */ __IM uint32_t STATUS; /**< Status Register */ __IOM uint32_t CMD; /**< Command Register */ __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ __IOM uint32_t POWERDOWN; /**< Retention RAM Power-down Register */ __IOM uint32_t LOCK; /**< Configuration Lock Register */ __IOM uint32_t EM4WUEN; /**< Wake Up Enable */ RTCC_CC_TypeDef CC[3U]; /**< Capture/Compare Channel */ uint32_t RESERVED0[37U]; /**< Reserved registers */ RTCC_RET_TypeDef RET[32U]; /**< RetentionReg */ } RTCC_TypeDef; /** @} */ /***************************************************************************//** * @addtogroup EFR32MG12P_RTCC * @{ * @defgroup EFR32MG12P_RTCC_BitFields RTCC Bit Fields * @{ ******************************************************************************/ /* Bit fields for RTCC CTRL */ #define _RTCC_CTRL_RESETVALUE 0x00000000UL /**< Default value for RTCC_CTRL */ #define _RTCC_CTRL_MASK 0x00039F35UL /**< Mask for RTCC_CTRL */ #define RTCC_CTRL_ENABLE (0x1UL << 0) /**< RTCC Enable */ #define _RTCC_CTRL_ENABLE_SHIFT 0 /**< Shift value for RTCC_ENABLE */ #define _RTCC_CTRL_ENABLE_MASK 0x1UL /**< Bit mask for RTCC_ENABLE */ #define _RTCC_CTRL_ENABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */ #define RTCC_CTRL_ENABLE_DEFAULT (_RTCC_CTRL_ENABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CTRL */ #define RTCC_CTRL_DEBUGRUN (0x1UL << 2) /**< Debug Mode Run Enable */ #define _RTCC_CTRL_DEBUGRUN_SHIFT 2 /**< Shift value for RTCC_DEBUGRUN */ #define _RTCC_CTRL_DEBUGRUN_MASK 0x4UL /**< Bit mask for RTCC_DEBUGRUN */ #define _RTCC_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */ #define RTCC_CTRL_DEBUGRUN_DEFAULT (_RTCC_CTRL_DEBUGRUN_DEFAULT << 2) /**< Shifted mode DEFAULT for RTCC_CTRL */ #define RTCC_CTRL_PRECCV0TOP (0x1UL << 4) /**< Pre-counter CCV0 Top Value Enable */ #define _RTCC_CTRL_PRECCV0TOP_SHIFT 4 /**< Shift value for RTCC_PRECCV0TOP */ #define _RTCC_CTRL_PRECCV0TOP_MASK 0x10UL /**< Bit mask for RTCC_PRECCV0TOP */ #define _RTCC_CTRL_PRECCV0TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */ #define RTCC_CTRL_PRECCV0TOP_DEFAULT (_RTCC_CTRL_PRECCV0TOP_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_CTRL */ #define RTCC_CTRL_CCV1TOP (0x1UL << 5) /**< CCV1 Top Value Enable */ #define _RTCC_CTRL_CCV1TOP_SHIFT 5 /**< Shift value for RTCC_CCV1TOP */ #define _RTCC_CTRL_CCV1TOP_MASK 0x20UL /**< Bit mask for RTCC_CCV1TOP */ #define _RTCC_CTRL_CCV1TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */ #define RTCC_CTRL_CCV1TOP_DEFAULT (_RTCC_CTRL_CCV1TOP_DEFAULT << 5) /**< Shifted mode DEFAULT for RTCC_CTRL */ #define _RTCC_CTRL_CNTPRESC_SHIFT 8 /**< Shift value for RTCC_CNTPRESC */ #define _RTCC_CTRL_CNTPRESC_MASK 0xF00UL /**< Bit mask for RTCC_CNTPRESC */ #define _RTCC_CTRL_CNTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */ #define _RTCC_CTRL_CNTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for RTCC_CTRL */ #define _RTCC_CTRL_CNTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for RTCC_CTRL */ #define _RTCC_CTRL_CNTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for RTCC_CTRL */ #define _RTCC_CTRL_CNTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for RTCC_CTRL */ #define _RTCC_CTRL_CNTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for RTCC_CTRL */ #define _RTCC_CTRL_CNTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for RTCC_CTRL */ #define _RTCC_CTRL_CNTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for RTCC_CTRL */ #define _RTCC_CTRL_CNTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for RTCC_CTRL */ #define _RTCC_CTRL_CNTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for RTCC_CTRL */ #define _RTCC_CTRL_CNTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for RTCC_CTRL */ #define _RTCC_CTRL_CNTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for RTCC_CTRL */ #define _RTCC_CTRL_CNTPRESC_DIV2048 0x0000000BUL /**< Mode DIV2048 for RTCC_CTRL */ #define _RTCC_CTRL_CNTPRESC_DIV4096 0x0000000CUL /**< Mode DIV4096 for RTCC_CTRL */ #define _RTCC_CTRL_CNTPRESC_DIV8192 0x0000000DUL /**< Mode DIV8192 for RTCC_CTRL */ #define _RTCC_CTRL_CNTPRESC_DIV16384 0x0000000EUL /**< Mode DIV16384 for RTCC_CTRL */ #define _RTCC_CTRL_CNTPRESC_DIV32768 0x0000000FUL /**< Mode DIV32768 for RTCC_CTRL */ #define RTCC_CTRL_CNTPRESC_DEFAULT (_RTCC_CTRL_CNTPRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_CTRL */ #define RTCC_CTRL_CNTPRESC_DIV1 (_RTCC_CTRL_CNTPRESC_DIV1 << 8) /**< Shifted mode DIV1 for RTCC_CTRL */ #define RTCC_CTRL_CNTPRESC_DIV2 (_RTCC_CTRL_CNTPRESC_DIV2 << 8) /**< Shifted mode DIV2 for RTCC_CTRL */ #define RTCC_CTRL_CNTPRESC_DIV4 (_RTCC_CTRL_CNTPRESC_DIV4 << 8) /**< Shifted mode DIV4 for RTCC_CTRL */ #define RTCC_CTRL_CNTPRESC_DIV8 (_RTCC_CTRL_CNTPRESC_DIV8 << 8) /**< Shifted mode DIV8 for RTCC_CTRL */ #define RTCC_CTRL_CNTPRESC_DIV16 (_RTCC_CTRL_CNTPRESC_DIV16 << 8) /**< Shifted mode DIV16 for RTCC_CTRL */ #define RTCC_CTRL_CNTPRESC_DIV32 (_RTCC_CTRL_CNTPRESC_DIV32 << 8) /**< Shifted mode DIV32 for RTCC_CTRL */ #define RTCC_CTRL_CNTPRESC_DIV64 (_RTCC_CTRL_CNTPRESC_DIV64 << 8) /**< Shifted mode DIV64 for RTCC_CTRL */ #define RTCC_CTRL_CNTPRESC_DIV128 (_RTCC_CTRL_CNTPRESC_DIV128 << 8) /**< Shifted mode DIV128 for RTCC_CTRL */ #define RTCC_CTRL_CNTPRESC_DIV256 (_RTCC_CTRL_CNTPRESC_DIV256 << 8) /**< Shifted mode DIV256 for RTCC_CTRL */ #define RTCC_CTRL_CNTPRESC_DIV512 (_RTCC_CTRL_CNTPRESC_DIV512 << 8) /**< Shifted mode DIV512 for RTCC_CTRL */ #define RTCC_CTRL_CNTPRESC_DIV1024 (_RTCC_CTRL_CNTPRESC_DIV1024 << 8) /**< Shifted mode DIV1024 for RTCC_CTRL */ #define RTCC_CTRL_CNTPRESC_DIV2048 (_RTCC_CTRL_CNTPRESC_DIV2048 << 8) /**< Shifted mode DIV2048 for RTCC_CTRL */ #define RTCC_CTRL_CNTPRESC_DIV4096 (_RTCC_CTRL_CNTPRESC_DIV4096 << 8) /**< Shifted mode DIV4096 for RTCC_CTRL */ #define RTCC_CTRL_CNTPRESC_DIV8192 (_RTCC_CTRL_CNTPRESC_DIV8192 << 8) /**< Shifted mode DIV8192 for RTCC_CTRL */ #define RTCC_CTRL_CNTPRESC_DIV16384 (_RTCC_CTRL_CNTPRESC_DIV16384 << 8) /**< Shifted mode DIV16384 for RTCC_CTRL */ #define RTCC_CTRL_CNTPRESC_DIV32768 (_RTCC_CTRL_CNTPRESC_DIV32768 << 8) /**< Shifted mode DIV32768 for RTCC_CTRL */ #define RTCC_CTRL_CNTTICK (0x1UL << 12) /**< Counter Prescaler Mode */ #define _RTCC_CTRL_CNTTICK_SHIFT 12 /**< Shift value for RTCC_CNTTICK */ #define _RTCC_CTRL_CNTTICK_MASK 0x1000UL /**< Bit mask for RTCC_CNTTICK */ #define _RTCC_CTRL_CNTTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */ #define _RTCC_CTRL_CNTTICK_PRESC 0x00000000UL /**< Mode PRESC for RTCC_CTRL */ #define _RTCC_CTRL_CNTTICK_CCV0MATCH 0x00000001UL /**< Mode CCV0MATCH for RTCC_CTRL */ #define RTCC_CTRL_CNTTICK_DEFAULT (_RTCC_CTRL_CNTTICK_DEFAULT << 12) /**< Shifted mode DEFAULT for RTCC_CTRL */ #define RTCC_CTRL_CNTTICK_PRESC (_RTCC_CTRL_CNTTICK_PRESC << 12) /**< Shifted mode PRESC for RTCC_CTRL */ #define RTCC_CTRL_CNTTICK_CCV0MATCH (_RTCC_CTRL_CNTTICK_CCV0MATCH << 12) /**< Shifted mode CCV0MATCH for RTCC_CTRL */ #define RTCC_CTRL_OSCFDETEN (0x1UL << 15) /**< Oscillator Failure Detection Enable */ #define _RTCC_CTRL_OSCFDETEN_SHIFT 15 /**< Shift value for RTCC_OSCFDETEN */ #define _RTCC_CTRL_OSCFDETEN_MASK 0x8000UL /**< Bit mask for RTCC_OSCFDETEN */ #define _RTCC_CTRL_OSCFDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */ #define RTCC_CTRL_OSCFDETEN_DEFAULT (_RTCC_CTRL_OSCFDETEN_DEFAULT << 15) /**< Shifted mode DEFAULT for RTCC_CTRL */ #define RTCC_CTRL_CNTMODE (0x1UL << 16) /**< Main Counter Mode */ #define _RTCC_CTRL_CNTMODE_SHIFT 16 /**< Shift value for RTCC_CNTMODE */ #define _RTCC_CTRL_CNTMODE_MASK 0x10000UL /**< Bit mask for RTCC_CNTMODE */ #define _RTCC_CTRL_CNTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */ #define _RTCC_CTRL_CNTMODE_NORMAL 0x00000000UL /**< Mode NORMAL for RTCC_CTRL */ #define _RTCC_CTRL_CNTMODE_CALENDAR 0x00000001UL /**< Mode CALENDAR for RTCC_CTRL */ #define RTCC_CTRL_CNTMODE_DEFAULT (_RTCC_CTRL_CNTMODE_DEFAULT << 16) /**< Shifted mode DEFAULT for RTCC_CTRL */ #define RTCC_CTRL_CNTMODE_NORMAL (_RTCC_CTRL_CNTMODE_NORMAL << 16) /**< Shifted mode NORMAL for RTCC_CTRL */ #define RTCC_CTRL_CNTMODE_CALENDAR (_RTCC_CTRL_CNTMODE_CALENDAR << 16) /**< Shifted mode CALENDAR for RTCC_CTRL */ #define RTCC_CTRL_LYEARCORRDIS (0x1UL << 17) /**< Leap Year Correction Disabled */ #define _RTCC_CTRL_LYEARCORRDIS_SHIFT 17 /**< Shift value for RTCC_LYEARCORRDIS */ #define _RTCC_CTRL_LYEARCORRDIS_MASK 0x20000UL /**< Bit mask for RTCC_LYEARCORRDIS */ #define _RTCC_CTRL_LYEARCORRDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */ #define RTCC_CTRL_LYEARCORRDIS_DEFAULT (_RTCC_CTRL_LYEARCORRDIS_DEFAULT << 17) /**< Shifted mode DEFAULT for RTCC_CTRL */ /* Bit fields for RTCC PRECNT */ #define _RTCC_PRECNT_RESETVALUE 0x00000000UL /**< Default value for RTCC_PRECNT */ #define _RTCC_PRECNT_MASK 0x00007FFFUL /**< Mask for RTCC_PRECNT */ #define _RTCC_PRECNT_PRECNT_SHIFT 0 /**< Shift value for RTCC_PRECNT */ #define _RTCC_PRECNT_PRECNT_MASK 0x7FFFUL /**< Bit mask for RTCC_PRECNT */ #define _RTCC_PRECNT_PRECNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_PRECNT */ #define RTCC_PRECNT_PRECNT_DEFAULT (_RTCC_PRECNT_PRECNT_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_PRECNT */ /* Bit fields for RTCC CNT */ #define _RTCC_CNT_RESETVALUE 0x00000000UL /**< Default value for RTCC_CNT */ #define _RTCC_CNT_MASK 0xFFFFFFFFUL /**< Mask for RTCC_CNT */ #define _RTCC_CNT_CNT_SHIFT 0 /**< Shift value for RTCC_CNT */ #define _RTCC_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for RTCC_CNT */ #define _RTCC_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CNT */ #define RTCC_CNT_CNT_DEFAULT (_RTCC_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CNT */ /* Bit fields for RTCC COMBCNT */ #define _RTCC_COMBCNT_RESETVALUE 0x00000000UL /**< Default value for RTCC_COMBCNT */ #define _RTCC_COMBCNT_MASK 0xFFFFFFFFUL /**< Mask for RTCC_COMBCNT */ #define _RTCC_COMBCNT_PRECNT_SHIFT 0 /**< Shift value for RTCC_PRECNT */ #define _RTCC_COMBCNT_PRECNT_MASK 0x7FFFUL /**< Bit mask for RTCC_PRECNT */ #define _RTCC_COMBCNT_PRECNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_COMBCNT */ #define RTCC_COMBCNT_PRECNT_DEFAULT (_RTCC_COMBCNT_PRECNT_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_COMBCNT */ #define _RTCC_COMBCNT_CNTLSB_SHIFT 15 /**< Shift value for RTCC_CNTLSB */ #define _RTCC_COMBCNT_CNTLSB_MASK 0xFFFF8000UL /**< Bit mask for RTCC_CNTLSB */ #define _RTCC_COMBCNT_CNTLSB_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_COMBCNT */ #define RTCC_COMBCNT_CNTLSB_DEFAULT (_RTCC_COMBCNT_CNTLSB_DEFAULT << 15) /**< Shifted mode DEFAULT for RTCC_COMBCNT */ /* Bit fields for RTCC TIME */ #define _RTCC_TIME_RESETVALUE 0x00000000UL /**< Default value for RTCC_TIME */ #define _RTCC_TIME_MASK 0x003F7F7FUL /**< Mask for RTCC_TIME */ #define _RTCC_TIME_SECU_SHIFT 0 /**< Shift value for RTCC_SECU */ #define _RTCC_TIME_SECU_MASK 0xFUL /**< Bit mask for RTCC_SECU */ #define _RTCC_TIME_SECU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_TIME */ #define RTCC_TIME_SECU_DEFAULT (_RTCC_TIME_SECU_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_TIME */ #define _RTCC_TIME_SECT_SHIFT 4 /**< Shift value for RTCC_SECT */ #define _RTCC_TIME_SECT_MASK 0x70UL /**< Bit mask for RTCC_SECT */ #define _RTCC_TIME_SECT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_TIME */ #define RTCC_TIME_SECT_DEFAULT (_RTCC_TIME_SECT_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_TIME */ #define _RTCC_TIME_MINU_SHIFT 8 /**< Shift value for RTCC_MINU */ #define _RTCC_TIME_MINU_MASK 0xF00UL /**< Bit mask for RTCC_MINU */ #define _RTCC_TIME_MINU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_TIME */ #define RTCC_TIME_MINU_DEFAULT (_RTCC_TIME_MINU_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_TIME */ #define _RTCC_TIME_MINT_SHIFT 12 /**< Shift value for RTCC_MINT */ #define _RTCC_TIME_MINT_MASK 0x7000UL /**< Bit mask for RTCC_MINT */ #define _RTCC_TIME_MINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_TIME */ #define RTCC_TIME_MINT_DEFAULT (_RTCC_TIME_MINT_DEFAULT << 12) /**< Shifted mode DEFAULT for RTCC_TIME */ #define _RTCC_TIME_HOURU_SHIFT 16 /**< Shift value for RTCC_HOURU */ #define _RTCC_TIME_HOURU_MASK 0xF0000UL /**< Bit mask for RTCC_HOURU */ #define _RTCC_TIME_HOURU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_TIME */ #define RTCC_TIME_HOURU_DEFAULT (_RTCC_TIME_HOURU_DEFAULT << 16) /**< Shifted mode DEFAULT for RTCC_TIME */ #define _RTCC_TIME_HOURT_SHIFT 20 /**< Shift value for RTCC_HOURT */ #define _RTCC_TIME_HOURT_MASK 0x300000UL /**< Bit mask for RTCC_HOURT */ #define _RTCC_TIME_HOURT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_TIME */ #define RTCC_TIME_HOURT_DEFAULT (_RTCC_TIME_HOURT_DEFAULT << 20) /**< Shifted mode DEFAULT for RTCC_TIME */ /* Bit fields for RTCC DATE */ #define _RTCC_DATE_RESETVALUE 0x00000000UL /**< Default value for RTCC_DATE */ #define _RTCC_DATE_MASK 0x07FF1F3FUL /**< Mask for RTCC_DATE */ #define _RTCC_DATE_DAYOMU_SHIFT 0 /**< Shift value for RTCC_DAYOMU */ #define _RTCC_DATE_DAYOMU_MASK 0xFUL /**< Bit mask for RTCC_DAYOMU */ #define _RTCC_DATE_DAYOMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_DATE */ #define RTCC_DATE_DAYOMU_DEFAULT (_RTCC_DATE_DAYOMU_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_DATE */ #define _RTCC_DATE_DAYOMT_SHIFT 4 /**< Shift value for RTCC_DAYOMT */ #define _RTCC_DATE_DAYOMT_MASK 0x30UL /**< Bit mask for RTCC_DAYOMT */ #define _RTCC_DATE_DAYOMT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_DATE */ #define RTCC_DATE_DAYOMT_DEFAULT (_RTCC_DATE_DAYOMT_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_DATE */ #define _RTCC_DATE_MONTHU_SHIFT 8 /**< Shift value for RTCC_MONTHU */ #define _RTCC_DATE_MONTHU_MASK 0xF00UL /**< Bit mask for RTCC_MONTHU */ #define _RTCC_DATE_MONTHU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_DATE */ #define RTCC_DATE_MONTHU_DEFAULT (_RTCC_DATE_MONTHU_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_DATE */ #define RTCC_DATE_MONTHT (0x1UL << 12) /**< Month, Tens */ #define _RTCC_DATE_MONTHT_SHIFT 12 /**< Shift value for RTCC_MONTHT */ #define _RTCC_DATE_MONTHT_MASK 0x1000UL /**< Bit mask for RTCC_MONTHT */ #define _RTCC_DATE_MONTHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_DATE */ #define RTCC_DATE_MONTHT_DEFAULT (_RTCC_DATE_MONTHT_DEFAULT << 12) /**< Shifted mode DEFAULT for RTCC_DATE */ #define _RTCC_DATE_YEARU_SHIFT 16 /**< Shift value for RTCC_YEARU */ #define _RTCC_DATE_YEARU_MASK 0xF0000UL /**< Bit mask for RTCC_YEARU */ #define _RTCC_DATE_YEARU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_DATE */ #define RTCC_DATE_YEARU_DEFAULT (_RTCC_DATE_YEARU_DEFAULT << 16) /**< Shifted mode DEFAULT for RTCC_DATE */ #define _RTCC_DATE_YEART_SHIFT 20 /**< Shift value for RTCC_YEART */ #define _RTCC_DATE_YEART_MASK 0xF00000UL /**< Bit mask for RTCC_YEART */ #define _RTCC_DATE_YEART_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_DATE */ #define RTCC_DATE_YEART_DEFAULT (_RTCC_DATE_YEART_DEFAULT << 20) /**< Shifted mode DEFAULT for RTCC_DATE */ #define _RTCC_DATE_DAYOW_SHIFT 24 /**< Shift value for RTCC_DAYOW */ #define _RTCC_DATE_DAYOW_MASK 0x7000000UL /**< Bit mask for RTCC_DAYOW */ #define _RTCC_DATE_DAYOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_DATE */ #define RTCC_DATE_DAYOW_DEFAULT (_RTCC_DATE_DAYOW_DEFAULT << 24) /**< Shifted mode DEFAULT for RTCC_DATE */ /* Bit fields for RTCC IF */ #define _RTCC_IF_RESETVALUE 0x00000000UL /**< Default value for RTCC_IF */ #define _RTCC_IF_MASK 0x000007FFUL /**< Mask for RTCC_IF */ #define RTCC_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ #define _RTCC_IF_OF_SHIFT 0 /**< Shift value for RTCC_OF */ #define _RTCC_IF_OF_MASK 0x1UL /**< Bit mask for RTCC_OF */ #define _RTCC_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */ #define RTCC_IF_OF_DEFAULT (_RTCC_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_IF */ #define RTCC_IF_CC0 (0x1UL << 1) /**< Channel 0 Interrupt Flag */ #define _RTCC_IF_CC0_SHIFT 1 /**< Shift value for RTCC_CC0 */ #define _RTCC_IF_CC0_MASK 0x2UL /**< Bit mask for RTCC_CC0 */ #define _RTCC_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */ #define RTCC_IF_CC0_DEFAULT (_RTCC_IF_CC0_DEFAULT << 1) /**< Shifted mode DEFAULT for RTCC_IF */ #define RTCC_IF_CC1 (0x1UL << 2) /**< Channel 1 Interrupt Flag */ #define _RTCC_IF_CC1_SHIFT 2 /**< Shift value for RTCC_CC1 */ #define _RTCC_IF_CC1_MASK 0x4UL /**< Bit mask for RTCC_CC1 */ #define _RTCC_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */ #define RTCC_IF_CC1_DEFAULT (_RTCC_IF_CC1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTCC_IF */ #define RTCC_IF_CC2 (0x1UL << 3) /**< Channel 2 Interrupt Flag */ #define _RTCC_IF_CC2_SHIFT 3 /**< Shift value for RTCC_CC2 */ #define _RTCC_IF_CC2_MASK 0x8UL /**< Bit mask for RTCC_CC2 */ #define _RTCC_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */ #define RTCC_IF_CC2_DEFAULT (_RTCC_IF_CC2_DEFAULT << 3) /**< Shifted mode DEFAULT for RTCC_IF */ #define RTCC_IF_OSCFAIL (0x1UL << 4) /**< Oscillator Failure Interrupt Flag */ #define _RTCC_IF_OSCFAIL_SHIFT 4 /**< Shift value for RTCC_OSCFAIL */ #define _RTCC_IF_OSCFAIL_MASK 0x10UL /**< Bit mask for RTCC_OSCFAIL */ #define _RTCC_IF_OSCFAIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */ #define RTCC_IF_OSCFAIL_DEFAULT (_RTCC_IF_OSCFAIL_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_IF */ #define RTCC_IF_CNTTICK (0x1UL << 5) /**< Main Counter Tick */ #define _RTCC_IF_CNTTICK_SHIFT 5 /**< Shift value for RTCC_CNTTICK */ #define _RTCC_IF_CNTTICK_MASK 0x20UL /**< Bit mask for RTCC_CNTTICK */ #define _RTCC_IF_CNTTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */ #define RTCC_IF_CNTTICK_DEFAULT (_RTCC_IF_CNTTICK_DEFAULT << 5) /**< Shifted mode DEFAULT for RTCC_IF */ #define RTCC_IF_MINTICK (0x1UL << 6) /**< Minute Tick */ #define _RTCC_IF_MINTICK_SHIFT 6 /**< Shift value for RTCC_MINTICK */ #define _RTCC_IF_MINTICK_MASK 0x40UL /**< Bit mask for RTCC_MINTICK */ #define _RTCC_IF_MINTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */ #define RTCC_IF_MINTICK_DEFAULT (_RTCC_IF_MINTICK_DEFAULT << 6) /**< Shifted mode DEFAULT for RTCC_IF */ #define RTCC_IF_HOURTICK (0x1UL << 7) /**< Hour Tick */ #define _RTCC_IF_HOURTICK_SHIFT 7 /**< Shift value for RTCC_HOURTICK */ #define _RTCC_IF_HOURTICK_MASK 0x80UL /**< Bit mask for RTCC_HOURTICK */ #define _RTCC_IF_HOURTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */ #define RTCC_IF_HOURTICK_DEFAULT (_RTCC_IF_HOURTICK_DEFAULT << 7) /**< Shifted mode DEFAULT for RTCC_IF */ #define RTCC_IF_DAYTICK (0x1UL << 8) /**< Day Tick */ #define _RTCC_IF_DAYTICK_SHIFT 8 /**< Shift value for RTCC_DAYTICK */ #define _RTCC_IF_DAYTICK_MASK 0x100UL /**< Bit mask for RTCC_DAYTICK */ #define _RTCC_IF_DAYTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */ #define RTCC_IF_DAYTICK_DEFAULT (_RTCC_IF_DAYTICK_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_IF */ #define RTCC_IF_DAYOWOF (0x1UL << 9) /**< Day of Week Overflow */ #define _RTCC_IF_DAYOWOF_SHIFT 9 /**< Shift value for RTCC_DAYOWOF */ #define _RTCC_IF_DAYOWOF_MASK 0x200UL /**< Bit mask for RTCC_DAYOWOF */ #define _RTCC_IF_DAYOWOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */ #define RTCC_IF_DAYOWOF_DEFAULT (_RTCC_IF_DAYOWOF_DEFAULT << 9) /**< Shifted mode DEFAULT for RTCC_IF */ #define RTCC_IF_MONTHTICK (0x1UL << 10) /**< Month Tick */ #define _RTCC_IF_MONTHTICK_SHIFT 10 /**< Shift value for RTCC_MONTHTICK */ #define _RTCC_IF_MONTHTICK_MASK 0x400UL /**< Bit mask for RTCC_MONTHTICK */ #define _RTCC_IF_MONTHTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */ #define RTCC_IF_MONTHTICK_DEFAULT (_RTCC_IF_MONTHTICK_DEFAULT << 10) /**< Shifted mode DEFAULT for RTCC_IF */ /* Bit fields for RTCC IFS */ #define _RTCC_IFS_RESETVALUE 0x00000000UL /**< Default value for RTCC_IFS */ #define _RTCC_IFS_MASK 0x000007FFUL /**< Mask for RTCC_IFS */ #define RTCC_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */ #define _RTCC_IFS_OF_SHIFT 0 /**< Shift value for RTCC_OF */ #define _RTCC_IFS_OF_MASK 0x1UL /**< Bit mask for RTCC_OF */ #define _RTCC_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */ #define RTCC_IFS_OF_DEFAULT (_RTCC_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_IFS */ #define RTCC_IFS_CC0 (0x1UL << 1) /**< Set CC0 Interrupt Flag */ #define _RTCC_IFS_CC0_SHIFT 1 /**< Shift value for RTCC_CC0 */ #define _RTCC_IFS_CC0_MASK 0x2UL /**< Bit mask for RTCC_CC0 */ #define _RTCC_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */ #define RTCC_IFS_CC0_DEFAULT (_RTCC_IFS_CC0_DEFAULT << 1) /**< Shifted mode DEFAULT for RTCC_IFS */ #define RTCC_IFS_CC1 (0x1UL << 2) /**< Set CC1 Interrupt Flag */ #define _RTCC_IFS_CC1_SHIFT 2 /**< Shift value for RTCC_CC1 */ #define _RTCC_IFS_CC1_MASK 0x4UL /**< Bit mask for RTCC_CC1 */ #define _RTCC_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */ #define RTCC_IFS_CC1_DEFAULT (_RTCC_IFS_CC1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTCC_IFS */ #define RTCC_IFS_CC2 (0x1UL << 3) /**< Set CC2 Interrupt Flag */ #define _RTCC_IFS_CC2_SHIFT 3 /**< Shift value for RTCC_CC2 */ #define _RTCC_IFS_CC2_MASK 0x8UL /**< Bit mask for RTCC_CC2 */ #define _RTCC_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */ #define RTCC_IFS_CC2_DEFAULT (_RTCC_IFS_CC2_DEFAULT << 3) /**< Shifted mode DEFAULT for RTCC_IFS */ #define RTCC_IFS_OSCFAIL (0x1UL << 4) /**< Set OSCFAIL Interrupt Flag */ #define _RTCC_IFS_OSCFAIL_SHIFT 4 /**< Shift value for RTCC_OSCFAIL */ #define _RTCC_IFS_OSCFAIL_MASK 0x10UL /**< Bit mask for RTCC_OSCFAIL */ #define _RTCC_IFS_OSCFAIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */ #define RTCC_IFS_OSCFAIL_DEFAULT (_RTCC_IFS_OSCFAIL_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_IFS */ #define RTCC_IFS_CNTTICK (0x1UL << 5) /**< Set CNTTICK Interrupt Flag */ #define _RTCC_IFS_CNTTICK_SHIFT 5 /**< Shift value for RTCC_CNTTICK */ #define _RTCC_IFS_CNTTICK_MASK 0x20UL /**< Bit mask for RTCC_CNTTICK */ #define _RTCC_IFS_CNTTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */ #define RTCC_IFS_CNTTICK_DEFAULT (_RTCC_IFS_CNTTICK_DEFAULT << 5) /**< Shifted mode DEFAULT for RTCC_IFS */ #define RTCC_IFS_MINTICK (0x1UL << 6) /**< Set MINTICK Interrupt Flag */ #define _RTCC_IFS_MINTICK_SHIFT 6 /**< Shift value for RTCC_MINTICK */ #define _RTCC_IFS_MINTICK_MASK 0x40UL /**< Bit mask for RTCC_MINTICK */ #define _RTCC_IFS_MINTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */ #define RTCC_IFS_MINTICK_DEFAULT (_RTCC_IFS_MINTICK_DEFAULT << 6) /**< Shifted mode DEFAULT for RTCC_IFS */ #define RTCC_IFS_HOURTICK (0x1UL << 7) /**< Set HOURTICK Interrupt Flag */ #define _RTCC_IFS_HOURTICK_SHIFT 7 /**< Shift value for RTCC_HOURTICK */ #define _RTCC_IFS_HOURTICK_MASK 0x80UL /**< Bit mask for RTCC_HOURTICK */ #define _RTCC_IFS_HOURTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */ #define RTCC_IFS_HOURTICK_DEFAULT (_RTCC_IFS_HOURTICK_DEFAULT << 7) /**< Shifted mode DEFAULT for RTCC_IFS */ #define RTCC_IFS_DAYTICK (0x1UL << 8) /**< Set DAYTICK Interrupt Flag */ #define _RTCC_IFS_DAYTICK_SHIFT 8 /**< Shift value for RTCC_DAYTICK */ #define _RTCC_IFS_DAYTICK_MASK 0x100UL /**< Bit mask for RTCC_DAYTICK */ #define _RTCC_IFS_DAYTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */ #define RTCC_IFS_DAYTICK_DEFAULT (_RTCC_IFS_DAYTICK_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_IFS */ #define RTCC_IFS_DAYOWOF (0x1UL << 9) /**< Set DAYOWOF Interrupt Flag */ #define _RTCC_IFS_DAYOWOF_SHIFT 9 /**< Shift value for RTCC_DAYOWOF */ #define _RTCC_IFS_DAYOWOF_MASK 0x200UL /**< Bit mask for RTCC_DAYOWOF */ #define _RTCC_IFS_DAYOWOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */ #define RTCC_IFS_DAYOWOF_DEFAULT (_RTCC_IFS_DAYOWOF_DEFAULT << 9) /**< Shifted mode DEFAULT for RTCC_IFS */ #define RTCC_IFS_MONTHTICK (0x1UL << 10) /**< Set MONTHTICK Interrupt Flag */ #define _RTCC_IFS_MONTHTICK_SHIFT 10 /**< Shift value for RTCC_MONTHTICK */ #define _RTCC_IFS_MONTHTICK_MASK 0x400UL /**< Bit mask for RTCC_MONTHTICK */ #define _RTCC_IFS_MONTHTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */ #define RTCC_IFS_MONTHTICK_DEFAULT (_RTCC_IFS_MONTHTICK_DEFAULT << 10) /**< Shifted mode DEFAULT for RTCC_IFS */ /* Bit fields for RTCC IFC */ #define _RTCC_IFC_RESETVALUE 0x00000000UL /**< Default value for RTCC_IFC */ #define _RTCC_IFC_MASK 0x000007FFUL /**< Mask for RTCC_IFC */ #define RTCC_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */ #define _RTCC_IFC_OF_SHIFT 0 /**< Shift value for RTCC_OF */ #define _RTCC_IFC_OF_MASK 0x1UL /**< Bit mask for RTCC_OF */ #define _RTCC_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */ #define RTCC_IFC_OF_DEFAULT (_RTCC_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_IFC */ #define RTCC_IFC_CC0 (0x1UL << 1) /**< Clear CC0 Interrupt Flag */ #define _RTCC_IFC_CC0_SHIFT 1 /**< Shift value for RTCC_CC0 */ #define _RTCC_IFC_CC0_MASK 0x2UL /**< Bit mask for RTCC_CC0 */ #define _RTCC_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */ #define RTCC_IFC_CC0_DEFAULT (_RTCC_IFC_CC0_DEFAULT << 1) /**< Shifted mode DEFAULT for RTCC_IFC */ #define RTCC_IFC_CC1 (0x1UL << 2) /**< Clear CC1 Interrupt Flag */ #define _RTCC_IFC_CC1_SHIFT 2 /**< Shift value for RTCC_CC1 */ #define _RTCC_IFC_CC1_MASK 0x4UL /**< Bit mask for RTCC_CC1 */ #define _RTCC_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */ #define RTCC_IFC_CC1_DEFAULT (_RTCC_IFC_CC1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTCC_IFC */ #define RTCC_IFC_CC2 (0x1UL << 3) /**< Clear CC2 Interrupt Flag */ #define _RTCC_IFC_CC2_SHIFT 3 /**< Shift value for RTCC_CC2 */ #define _RTCC_IFC_CC2_MASK 0x8UL /**< Bit mask for RTCC_CC2 */ #define _RTCC_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */ #define RTCC_IFC_CC2_DEFAULT (_RTCC_IFC_CC2_DEFAULT << 3) /**< Shifted mode DEFAULT for RTCC_IFC */ #define RTCC_IFC_OSCFAIL (0x1UL << 4) /**< Clear OSCFAIL Interrupt Flag */ #define _RTCC_IFC_OSCFAIL_SHIFT 4 /**< Shift value for RTCC_OSCFAIL */ #define _RTCC_IFC_OSCFAIL_MASK 0x10UL /**< Bit mask for RTCC_OSCFAIL */ #define _RTCC_IFC_OSCFAIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */ #define RTCC_IFC_OSCFAIL_DEFAULT (_RTCC_IFC_OSCFAIL_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_IFC */ #define RTCC_IFC_CNTTICK (0x1UL << 5) /**< Clear CNTTICK Interrupt Flag */ #define _RTCC_IFC_CNTTICK_SHIFT 5 /**< Shift value for RTCC_CNTTICK */ #define _RTCC_IFC_CNTTICK_MASK 0x20UL /**< Bit mask for RTCC_CNTTICK */ #define _RTCC_IFC_CNTTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */ #define RTCC_IFC_CNTTICK_DEFAULT (_RTCC_IFC_CNTTICK_DEFAULT << 5) /**< Shifted mode DEFAULT for RTCC_IFC */ #define RTCC_IFC_MINTICK (0x1UL << 6) /**< Clear MINTICK Interrupt Flag */ #define _RTCC_IFC_MINTICK_SHIFT 6 /**< Shift value for RTCC_MINTICK */ #define _RTCC_IFC_MINTICK_MASK 0x40UL /**< Bit mask for RTCC_MINTICK */ #define _RTCC_IFC_MINTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */ #define RTCC_IFC_MINTICK_DEFAULT (_RTCC_IFC_MINTICK_DEFAULT << 6) /**< Shifted mode DEFAULT for RTCC_IFC */ #define RTCC_IFC_HOURTICK (0x1UL << 7) /**< Clear HOURTICK Interrupt Flag */ #define _RTCC_IFC_HOURTICK_SHIFT 7 /**< Shift value for RTCC_HOURTICK */ #define _RTCC_IFC_HOURTICK_MASK 0x80UL /**< Bit mask for RTCC_HOURTICK */ #define _RTCC_IFC_HOURTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */ #define RTCC_IFC_HOURTICK_DEFAULT (_RTCC_IFC_HOURTICK_DEFAULT << 7) /**< Shifted mode DEFAULT for RTCC_IFC */ #define RTCC_IFC_DAYTICK (0x1UL << 8) /**< Clear DAYTICK Interrupt Flag */ #define _RTCC_IFC_DAYTICK_SHIFT 8 /**< Shift value for RTCC_DAYTICK */ #define _RTCC_IFC_DAYTICK_MASK 0x100UL /**< Bit mask for RTCC_DAYTICK */ #define _RTCC_IFC_DAYTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */ #define RTCC_IFC_DAYTICK_DEFAULT (_RTCC_IFC_DAYTICK_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_IFC */ #define RTCC_IFC_DAYOWOF (0x1UL << 9) /**< Clear DAYOWOF Interrupt Flag */ #define _RTCC_IFC_DAYOWOF_SHIFT 9 /**< Shift value for RTCC_DAYOWOF */ #define _RTCC_IFC_DAYOWOF_MASK 0x200UL /**< Bit mask for RTCC_DAYOWOF */ #define _RTCC_IFC_DAYOWOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */ #define RTCC_IFC_DAYOWOF_DEFAULT (_RTCC_IFC_DAYOWOF_DEFAULT << 9) /**< Shifted mode DEFAULT for RTCC_IFC */ #define RTCC_IFC_MONTHTICK (0x1UL << 10) /**< Clear MONTHTICK Interrupt Flag */ #define _RTCC_IFC_MONTHTICK_SHIFT 10 /**< Shift value for RTCC_MONTHTICK */ #define _RTCC_IFC_MONTHTICK_MASK 0x400UL /**< Bit mask for RTCC_MONTHTICK */ #define _RTCC_IFC_MONTHTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */ #define RTCC_IFC_MONTHTICK_DEFAULT (_RTCC_IFC_MONTHTICK_DEFAULT << 10) /**< Shifted mode DEFAULT for RTCC_IFC */ /* Bit fields for RTCC IEN */ #define _RTCC_IEN_RESETVALUE 0x00000000UL /**< Default value for RTCC_IEN */ #define _RTCC_IEN_MASK 0x000007FFUL /**< Mask for RTCC_IEN */ #define RTCC_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ #define _RTCC_IEN_OF_SHIFT 0 /**< Shift value for RTCC_OF */ #define _RTCC_IEN_OF_MASK 0x1UL /**< Bit mask for RTCC_OF */ #define _RTCC_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */ #define RTCC_IEN_OF_DEFAULT (_RTCC_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_IEN */ #define RTCC_IEN_CC0 (0x1UL << 1) /**< CC0 Interrupt Enable */ #define _RTCC_IEN_CC0_SHIFT 1 /**< Shift value for RTCC_CC0 */ #define _RTCC_IEN_CC0_MASK 0x2UL /**< Bit mask for RTCC_CC0 */ #define _RTCC_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */ #define RTCC_IEN_CC0_DEFAULT (_RTCC_IEN_CC0_DEFAULT << 1) /**< Shifted mode DEFAULT for RTCC_IEN */ #define RTCC_IEN_CC1 (0x1UL << 2) /**< CC1 Interrupt Enable */ #define _RTCC_IEN_CC1_SHIFT 2 /**< Shift value for RTCC_CC1 */ #define _RTCC_IEN_CC1_MASK 0x4UL /**< Bit mask for RTCC_CC1 */ #define _RTCC_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */ #define RTCC_IEN_CC1_DEFAULT (_RTCC_IEN_CC1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTCC_IEN */ #define RTCC_IEN_CC2 (0x1UL << 3) /**< CC2 Interrupt Enable */ #define _RTCC_IEN_CC2_SHIFT 3 /**< Shift value for RTCC_CC2 */ #define _RTCC_IEN_CC2_MASK 0x8UL /**< Bit mask for RTCC_CC2 */ #define _RTCC_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */ #define RTCC_IEN_CC2_DEFAULT (_RTCC_IEN_CC2_DEFAULT << 3) /**< Shifted mode DEFAULT for RTCC_IEN */ #define RTCC_IEN_OSCFAIL (0x1UL << 4) /**< OSCFAIL Interrupt Enable */ #define _RTCC_IEN_OSCFAIL_SHIFT 4 /**< Shift value for RTCC_OSCFAIL */ #define _RTCC_IEN_OSCFAIL_MASK 0x10UL /**< Bit mask for RTCC_OSCFAIL */ #define _RTCC_IEN_OSCFAIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */ #define RTCC_IEN_OSCFAIL_DEFAULT (_RTCC_IEN_OSCFAIL_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_IEN */ #define RTCC_IEN_CNTTICK (0x1UL << 5) /**< CNTTICK Interrupt Enable */ #define _RTCC_IEN_CNTTICK_SHIFT 5 /**< Shift value for RTCC_CNTTICK */ #define _RTCC_IEN_CNTTICK_MASK 0x20UL /**< Bit mask for RTCC_CNTTICK */ #define _RTCC_IEN_CNTTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */ #define RTCC_IEN_CNTTICK_DEFAULT (_RTCC_IEN_CNTTICK_DEFAULT << 5) /**< Shifted mode DEFAULT for RTCC_IEN */ #define RTCC_IEN_MINTICK (0x1UL << 6) /**< MINTICK Interrupt Enable */ #define _RTCC_IEN_MINTICK_SHIFT 6 /**< Shift value for RTCC_MINTICK */ #define _RTCC_IEN_MINTICK_MASK 0x40UL /**< Bit mask for RTCC_MINTICK */ #define _RTCC_IEN_MINTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */ #define RTCC_IEN_MINTICK_DEFAULT (_RTCC_IEN_MINTICK_DEFAULT << 6) /**< Shifted mode DEFAULT for RTCC_IEN */ #define RTCC_IEN_HOURTICK (0x1UL << 7) /**< HOURTICK Interrupt Enable */ #define _RTCC_IEN_HOURTICK_SHIFT 7 /**< Shift value for RTCC_HOURTICK */ #define _RTCC_IEN_HOURTICK_MASK 0x80UL /**< Bit mask for RTCC_HOURTICK */ #define _RTCC_IEN_HOURTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */ #define RTCC_IEN_HOURTICK_DEFAULT (_RTCC_IEN_HOURTICK_DEFAULT << 7) /**< Shifted mode DEFAULT for RTCC_IEN */ #define RTCC_IEN_DAYTICK (0x1UL << 8) /**< DAYTICK Interrupt Enable */ #define _RTCC_IEN_DAYTICK_SHIFT 8 /**< Shift value for RTCC_DAYTICK */ #define _RTCC_IEN_DAYTICK_MASK 0x100UL /**< Bit mask for RTCC_DAYTICK */ #define _RTCC_IEN_DAYTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */ #define RTCC_IEN_DAYTICK_DEFAULT (_RTCC_IEN_DAYTICK_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_IEN */ #define RTCC_IEN_DAYOWOF (0x1UL << 9) /**< DAYOWOF Interrupt Enable */ #define _RTCC_IEN_DAYOWOF_SHIFT 9 /**< Shift value for RTCC_DAYOWOF */ #define _RTCC_IEN_DAYOWOF_MASK 0x200UL /**< Bit mask for RTCC_DAYOWOF */ #define _RTCC_IEN_DAYOWOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */ #define RTCC_IEN_DAYOWOF_DEFAULT (_RTCC_IEN_DAYOWOF_DEFAULT << 9) /**< Shifted mode DEFAULT for RTCC_IEN */ #define RTCC_IEN_MONTHTICK (0x1UL << 10) /**< MONTHTICK Interrupt Enable */ #define _RTCC_IEN_MONTHTICK_SHIFT 10 /**< Shift value for RTCC_MONTHTICK */ #define _RTCC_IEN_MONTHTICK_MASK 0x400UL /**< Bit mask for RTCC_MONTHTICK */ #define _RTCC_IEN_MONTHTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */ #define RTCC_IEN_MONTHTICK_DEFAULT (_RTCC_IEN_MONTHTICK_DEFAULT << 10) /**< Shifted mode DEFAULT for RTCC_IEN */ /* Bit fields for RTCC STATUS */ #define _RTCC_STATUS_RESETVALUE 0x00000000UL /**< Default value for RTCC_STATUS */ #define _RTCC_STATUS_MASK 0x00000000UL /**< Mask for RTCC_STATUS */ /* Bit fields for RTCC CMD */ #define _RTCC_CMD_RESETVALUE 0x00000000UL /**< Default value for RTCC_CMD */ #define _RTCC_CMD_MASK 0x00000001UL /**< Mask for RTCC_CMD */ #define RTCC_CMD_CLRSTATUS (0x1UL << 0) /**< Clear RTCC_STATUS Register */ #define _RTCC_CMD_CLRSTATUS_SHIFT 0 /**< Shift value for RTCC_CLRSTATUS */ #define _RTCC_CMD_CLRSTATUS_MASK 0x1UL /**< Bit mask for RTCC_CLRSTATUS */ #define _RTCC_CMD_CLRSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CMD */ #define RTCC_CMD_CLRSTATUS_DEFAULT (_RTCC_CMD_CLRSTATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CMD */ /* Bit fields for RTCC SYNCBUSY */ #define _RTCC_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for RTCC_SYNCBUSY */ #define _RTCC_SYNCBUSY_MASK 0x00000020UL /**< Mask for RTCC_SYNCBUSY */ #define RTCC_SYNCBUSY_CMD (0x1UL << 5) /**< CMD Register Busy */ #define _RTCC_SYNCBUSY_CMD_SHIFT 5 /**< Shift value for RTCC_CMD */ #define _RTCC_SYNCBUSY_CMD_MASK 0x20UL /**< Bit mask for RTCC_CMD */ #define _RTCC_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_SYNCBUSY */ #define RTCC_SYNCBUSY_CMD_DEFAULT (_RTCC_SYNCBUSY_CMD_DEFAULT << 5) /**< Shifted mode DEFAULT for RTCC_SYNCBUSY */ /* Bit fields for RTCC POWERDOWN */ #define _RTCC_POWERDOWN_RESETVALUE 0x00000000UL /**< Default value for RTCC_POWERDOWN */ #define _RTCC_POWERDOWN_MASK 0x00000001UL /**< Mask for RTCC_POWERDOWN */ #define RTCC_POWERDOWN_RAM (0x1UL << 0) /**< Retention RAM Power-down */ #define _RTCC_POWERDOWN_RAM_SHIFT 0 /**< Shift value for RTCC_RAM */ #define _RTCC_POWERDOWN_RAM_MASK 0x1UL /**< Bit mask for RTCC_RAM */ #define _RTCC_POWERDOWN_RAM_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_POWERDOWN */ #define RTCC_POWERDOWN_RAM_DEFAULT (_RTCC_POWERDOWN_RAM_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_POWERDOWN */ /* Bit fields for RTCC LOCK */ #define _RTCC_LOCK_RESETVALUE 0x00000000UL /**< Default value for RTCC_LOCK */ #define _RTCC_LOCK_MASK 0x0000FFFFUL /**< Mask for RTCC_LOCK */ #define _RTCC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for RTCC_LOCKKEY */ #define _RTCC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for RTCC_LOCKKEY */ #define _RTCC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_LOCK */ #define _RTCC_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for RTCC_LOCK */ #define _RTCC_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for RTCC_LOCK */ #define _RTCC_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for RTCC_LOCK */ #define _RTCC_LOCK_LOCKKEY_UNLOCK 0x0000AEE8UL /**< Mode UNLOCK for RTCC_LOCK */ #define RTCC_LOCK_LOCKKEY_DEFAULT (_RTCC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_LOCK */ #define RTCC_LOCK_LOCKKEY_LOCK (_RTCC_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for RTCC_LOCK */ #define RTCC_LOCK_LOCKKEY_UNLOCKED (_RTCC_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for RTCC_LOCK */ #define RTCC_LOCK_LOCKKEY_LOCKED (_RTCC_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for RTCC_LOCK */ #define RTCC_LOCK_LOCKKEY_UNLOCK (_RTCC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for RTCC_LOCK */ /* Bit fields for RTCC EM4WUEN */ #define _RTCC_EM4WUEN_RESETVALUE 0x00000000UL /**< Default value for RTCC_EM4WUEN */ #define _RTCC_EM4WUEN_MASK 0x00000001UL /**< Mask for RTCC_EM4WUEN */ #define RTCC_EM4WUEN_EM4WU (0x1UL << 0) /**< EM4 Wake-up Enable */ #define _RTCC_EM4WUEN_EM4WU_SHIFT 0 /**< Shift value for RTCC_EM4WU */ #define _RTCC_EM4WUEN_EM4WU_MASK 0x1UL /**< Bit mask for RTCC_EM4WU */ #define _RTCC_EM4WUEN_EM4WU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_EM4WUEN */ #define RTCC_EM4WUEN_EM4WU_DEFAULT (_RTCC_EM4WUEN_EM4WU_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_EM4WUEN */ /* Bit fields for RTCC CC_CTRL */ #define _RTCC_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for RTCC_CC_CTRL */ #define _RTCC_CC_CTRL_MASK 0x0003FBFFUL /**< Mask for RTCC_CC_CTRL */ #define _RTCC_CC_CTRL_MODE_SHIFT 0 /**< Shift value for CC_MODE */ #define _RTCC_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for CC_MODE */ #define _RTCC_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */ #define _RTCC_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for RTCC_CC_CTRL */ #define _RTCC_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for RTCC_CC_CTRL */ #define _RTCC_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for RTCC_CC_CTRL */ #define RTCC_CC_CTRL_MODE_DEFAULT (_RTCC_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */ #define RTCC_CC_CTRL_MODE_OFF (_RTCC_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for RTCC_CC_CTRL */ #define RTCC_CC_CTRL_MODE_INPUTCAPTURE (_RTCC_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for RTCC_CC_CTRL */ #define RTCC_CC_CTRL_MODE_OUTPUTCOMPARE (_RTCC_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for RTCC_CC_CTRL */ #define _RTCC_CC_CTRL_CMOA_SHIFT 2 /**< Shift value for CC_CMOA */ #define _RTCC_CC_CTRL_CMOA_MASK 0xCUL /**< Bit mask for CC_CMOA */ #define _RTCC_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */ #define _RTCC_CC_CTRL_CMOA_PULSE 0x00000000UL /**< Mode PULSE for RTCC_CC_CTRL */ #define _RTCC_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for RTCC_CC_CTRL */ #define _RTCC_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for RTCC_CC_CTRL */ #define _RTCC_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for RTCC_CC_CTRL */ #define RTCC_CC_CTRL_CMOA_DEFAULT (_RTCC_CC_CTRL_CMOA_DEFAULT << 2) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */ #define RTCC_CC_CTRL_CMOA_PULSE (_RTCC_CC_CTRL_CMOA_PULSE << 2) /**< Shifted mode PULSE for RTCC_CC_CTRL */ #define RTCC_CC_CTRL_CMOA_TOGGLE (_RTCC_CC_CTRL_CMOA_TOGGLE << 2) /**< Shifted mode TOGGLE for RTCC_CC_CTRL */ #define RTCC_CC_CTRL_CMOA_CLEAR (_RTCC_CC_CTRL_CMOA_CLEAR << 2) /**< Shifted mode CLEAR for RTCC_CC_CTRL */ #define RTCC_CC_CTRL_CMOA_SET (_RTCC_CC_CTRL_CMOA_SET << 2) /**< Shifted mode SET for RTCC_CC_CTRL */ #define _RTCC_CC_CTRL_ICEDGE_SHIFT 4 /**< Shift value for CC_ICEDGE */ #define _RTCC_CC_CTRL_ICEDGE_MASK 0x30UL /**< Bit mask for CC_ICEDGE */ #define _RTCC_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */ #define _RTCC_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for RTCC_CC_CTRL */ #define _RTCC_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for RTCC_CC_CTRL */ #define _RTCC_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for RTCC_CC_CTRL */ #define _RTCC_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for RTCC_CC_CTRL */ #define RTCC_CC_CTRL_ICEDGE_DEFAULT (_RTCC_CC_CTRL_ICEDGE_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */ #define RTCC_CC_CTRL_ICEDGE_RISING (_RTCC_CC_CTRL_ICEDGE_RISING << 4) /**< Shifted mode RISING for RTCC_CC_CTRL */ #define RTCC_CC_CTRL_ICEDGE_FALLING (_RTCC_CC_CTRL_ICEDGE_FALLING << 4) /**< Shifted mode FALLING for RTCC_CC_CTRL */ #define RTCC_CC_CTRL_ICEDGE_BOTH (_RTCC_CC_CTRL_ICEDGE_BOTH << 4) /**< Shifted mode BOTH for RTCC_CC_CTRL */ #define RTCC_CC_CTRL_ICEDGE_NONE (_RTCC_CC_CTRL_ICEDGE_NONE << 4) /**< Shifted mode NONE for RTCC_CC_CTRL */ #define _RTCC_CC_CTRL_PRSSEL_SHIFT 6 /**< Shift value for CC_PRSSEL */ #define _RTCC_CC_CTRL_PRSSEL_MASK 0x3C0UL /**< Bit mask for CC_PRSSEL */ #define _RTCC_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */ #define _RTCC_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for RTCC_CC_CTRL */ #define _RTCC_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for RTCC_CC_CTRL */ #define _RTCC_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for RTCC_CC_CTRL */ #define _RTCC_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for RTCC_CC_CTRL */ #define _RTCC_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for RTCC_CC_CTRL */ #define _RTCC_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for RTCC_CC_CTRL */ #define _RTCC_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for RTCC_CC_CTRL */ #define _RTCC_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for RTCC_CC_CTRL */ #define _RTCC_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for RTCC_CC_CTRL */ #define _RTCC_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for RTCC_CC_CTRL */ #define _RTCC_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for RTCC_CC_CTRL */ #define _RTCC_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for RTCC_CC_CTRL */ #define RTCC_CC_CTRL_PRSSEL_DEFAULT (_RTCC_CC_CTRL_PRSSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */ #define RTCC_CC_CTRL_PRSSEL_PRSCH0 (_RTCC_CC_CTRL_PRSSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for RTCC_CC_CTRL */ #define RTCC_CC_CTRL_PRSSEL_PRSCH1 (_RTCC_CC_CTRL_PRSSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for RTCC_CC_CTRL */ #define RTCC_CC_CTRL_PRSSEL_PRSCH2 (_RTCC_CC_CTRL_PRSSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for RTCC_CC_CTRL */ #define RTCC_CC_CTRL_PRSSEL_PRSCH3 (_RTCC_CC_CTRL_PRSSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for RTCC_CC_CTRL */ #define RTCC_CC_CTRL_PRSSEL_PRSCH4 (_RTCC_CC_CTRL_PRSSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for RTCC_CC_CTRL */ #define RTCC_CC_CTRL_PRSSEL_PRSCH5 (_RTCC_CC_CTRL_PRSSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for RTCC_CC_CTRL */ #define RTCC_CC_CTRL_PRSSEL_PRSCH6 (_RTCC_CC_CTRL_PRSSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for RTCC_CC_CTRL */ #define RTCC_CC_CTRL_PRSSEL_PRSCH7 (_RTCC_CC_CTRL_PRSSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for RTCC_CC_CTRL */ #define RTCC_CC_CTRL_PRSSEL_PRSCH8 (_RTCC_CC_CTRL_PRSSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for RTCC_CC_CTRL */ #define RTCC_CC_CTRL_PRSSEL_PRSCH9 (_RTCC_CC_CTRL_PRSSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for RTCC_CC_CTRL */ #define RTCC_CC_CTRL_PRSSEL_PRSCH10 (_RTCC_CC_CTRL_PRSSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for RTCC_CC_CTRL */ #define RTCC_CC_CTRL_PRSSEL_PRSCH11 (_RTCC_CC_CTRL_PRSSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for RTCC_CC_CTRL */ #define RTCC_CC_CTRL_COMPBASE (0x1UL << 11) /**< Capture Compare Channel Comparison Base */ #define _RTCC_CC_CTRL_COMPBASE_SHIFT 11 /**< Shift value for CC_COMPBASE */ #define _RTCC_CC_CTRL_COMPBASE_MASK 0x800UL /**< Bit mask for CC_COMPBASE */ #define _RTCC_CC_CTRL_COMPBASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */ #define _RTCC_CC_CTRL_COMPBASE_CNT 0x00000000UL /**< Mode CNT for RTCC_CC_CTRL */ #define _RTCC_CC_CTRL_COMPBASE_PRECNT 0x00000001UL /**< Mode PRECNT for RTCC_CC_CTRL */ #define RTCC_CC_CTRL_COMPBASE_DEFAULT (_RTCC_CC_CTRL_COMPBASE_DEFAULT << 11) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */ #define RTCC_CC_CTRL_COMPBASE_CNT (_RTCC_CC_CTRL_COMPBASE_CNT << 11) /**< Shifted mode CNT for RTCC_CC_CTRL */ #define RTCC_CC_CTRL_COMPBASE_PRECNT (_RTCC_CC_CTRL_COMPBASE_PRECNT << 11) /**< Shifted mode PRECNT for RTCC_CC_CTRL */ #define _RTCC_CC_CTRL_COMPMASK_SHIFT 12 /**< Shift value for CC_COMPMASK */ #define _RTCC_CC_CTRL_COMPMASK_MASK 0x1F000UL /**< Bit mask for CC_COMPMASK */ #define _RTCC_CC_CTRL_COMPMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */ #define RTCC_CC_CTRL_COMPMASK_DEFAULT (_RTCC_CC_CTRL_COMPMASK_DEFAULT << 12) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */ #define RTCC_CC_CTRL_DAYCC (0x1UL << 17) /**< Day Capture/Compare Selection */ #define _RTCC_CC_CTRL_DAYCC_SHIFT 17 /**< Shift value for CC_DAYCC */ #define _RTCC_CC_CTRL_DAYCC_MASK 0x20000UL /**< Bit mask for CC_DAYCC */ #define _RTCC_CC_CTRL_DAYCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */ #define _RTCC_CC_CTRL_DAYCC_MONTH 0x00000000UL /**< Mode MONTH for RTCC_CC_CTRL */ #define _RTCC_CC_CTRL_DAYCC_WEEK 0x00000001UL /**< Mode WEEK for RTCC_CC_CTRL */ #define RTCC_CC_CTRL_DAYCC_DEFAULT (_RTCC_CC_CTRL_DAYCC_DEFAULT << 17) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */ #define RTCC_CC_CTRL_DAYCC_MONTH (_RTCC_CC_CTRL_DAYCC_MONTH << 17) /**< Shifted mode MONTH for RTCC_CC_CTRL */ #define RTCC_CC_CTRL_DAYCC_WEEK (_RTCC_CC_CTRL_DAYCC_WEEK << 17) /**< Shifted mode WEEK for RTCC_CC_CTRL */ /* Bit fields for RTCC CC_CCV */ #define _RTCC_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for RTCC_CC_CCV */ #define _RTCC_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for RTCC_CC_CCV */ #define _RTCC_CC_CCV_CCV_SHIFT 0 /**< Shift value for CC_CCV */ #define _RTCC_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for CC_CCV */ #define _RTCC_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CCV */ #define RTCC_CC_CCV_CCV_DEFAULT (_RTCC_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CC_CCV */ /* Bit fields for RTCC CC_TIME */ #define _RTCC_CC_TIME_RESETVALUE 0x00000000UL /**< Default value for RTCC_CC_TIME */ #define _RTCC_CC_TIME_MASK 0x003F7F7FUL /**< Mask for RTCC_CC_TIME */ #define _RTCC_CC_TIME_SECU_SHIFT 0 /**< Shift value for CC_SECU */ #define _RTCC_CC_TIME_SECU_MASK 0xFUL /**< Bit mask for CC_SECU */ #define _RTCC_CC_TIME_SECU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_TIME */ #define RTCC_CC_TIME_SECU_DEFAULT (_RTCC_CC_TIME_SECU_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CC_TIME */ #define _RTCC_CC_TIME_SECT_SHIFT 4 /**< Shift value for CC_SECT */ #define _RTCC_CC_TIME_SECT_MASK 0x70UL /**< Bit mask for CC_SECT */ #define _RTCC_CC_TIME_SECT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_TIME */ #define RTCC_CC_TIME_SECT_DEFAULT (_RTCC_CC_TIME_SECT_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_CC_TIME */ #define _RTCC_CC_TIME_MINU_SHIFT 8 /**< Shift value for CC_MINU */ #define _RTCC_CC_TIME_MINU_MASK 0xF00UL /**< Bit mask for CC_MINU */ #define _RTCC_CC_TIME_MINU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_TIME */ #define RTCC_CC_TIME_MINU_DEFAULT (_RTCC_CC_TIME_MINU_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_CC_TIME */ #define _RTCC_CC_TIME_MINT_SHIFT 12 /**< Shift value for CC_MINT */ #define _RTCC_CC_TIME_MINT_MASK 0x7000UL /**< Bit mask for CC_MINT */ #define _RTCC_CC_TIME_MINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_TIME */ #define RTCC_CC_TIME_MINT_DEFAULT (_RTCC_CC_TIME_MINT_DEFAULT << 12) /**< Shifted mode DEFAULT for RTCC_CC_TIME */ #define _RTCC_CC_TIME_HOURU_SHIFT 16 /**< Shift value for CC_HOURU */ #define _RTCC_CC_TIME_HOURU_MASK 0xF0000UL /**< Bit mask for CC_HOURU */ #define _RTCC_CC_TIME_HOURU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_TIME */ #define RTCC_CC_TIME_HOURU_DEFAULT (_RTCC_CC_TIME_HOURU_DEFAULT << 16) /**< Shifted mode DEFAULT for RTCC_CC_TIME */ #define _RTCC_CC_TIME_HOURT_SHIFT 20 /**< Shift value for CC_HOURT */ #define _RTCC_CC_TIME_HOURT_MASK 0x300000UL /**< Bit mask for CC_HOURT */ #define _RTCC_CC_TIME_HOURT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_TIME */ #define RTCC_CC_TIME_HOURT_DEFAULT (_RTCC_CC_TIME_HOURT_DEFAULT << 20) /**< Shifted mode DEFAULT for RTCC_CC_TIME */ /* Bit fields for RTCC CC_DATE */ #define _RTCC_CC_DATE_RESETVALUE 0x00000000UL /**< Default value for RTCC_CC_DATE */ #define _RTCC_CC_DATE_MASK 0x00001F3FUL /**< Mask for RTCC_CC_DATE */ #define _RTCC_CC_DATE_DAYU_SHIFT 0 /**< Shift value for CC_DAYU */ #define _RTCC_CC_DATE_DAYU_MASK 0xFUL /**< Bit mask for CC_DAYU */ #define _RTCC_CC_DATE_DAYU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_DATE */ #define RTCC_CC_DATE_DAYU_DEFAULT (_RTCC_CC_DATE_DAYU_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CC_DATE */ #define _RTCC_CC_DATE_DAYT_SHIFT 4 /**< Shift value for CC_DAYT */ #define _RTCC_CC_DATE_DAYT_MASK 0x30UL /**< Bit mask for CC_DAYT */ #define _RTCC_CC_DATE_DAYT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_DATE */ #define RTCC_CC_DATE_DAYT_DEFAULT (_RTCC_CC_DATE_DAYT_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_CC_DATE */ #define _RTCC_CC_DATE_MONTHU_SHIFT 8 /**< Shift value for CC_MONTHU */ #define _RTCC_CC_DATE_MONTHU_MASK 0xF00UL /**< Bit mask for CC_MONTHU */ #define _RTCC_CC_DATE_MONTHU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_DATE */ #define RTCC_CC_DATE_MONTHU_DEFAULT (_RTCC_CC_DATE_MONTHU_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_CC_DATE */ #define RTCC_CC_DATE_MONTHT (0x1UL << 12) /**< Month, Tens */ #define _RTCC_CC_DATE_MONTHT_SHIFT 12 /**< Shift value for CC_MONTHT */ #define _RTCC_CC_DATE_MONTHT_MASK 0x1000UL /**< Bit mask for CC_MONTHT */ #define _RTCC_CC_DATE_MONTHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_DATE */ #define RTCC_CC_DATE_MONTHT_DEFAULT (_RTCC_CC_DATE_MONTHT_DEFAULT << 12) /**< Shifted mode DEFAULT for RTCC_CC_DATE */ /* Bit fields for RTCC RET_REG */ #define _RTCC_RET_REG_RESETVALUE 0x00000000UL /**< Default value for RTCC_RET_REG */ #define _RTCC_RET_REG_MASK 0xFFFFFFFFUL /**< Mask for RTCC_RET_REG */ #define _RTCC_RET_REG_REG_SHIFT 0 /**< Shift value for RET_REG */ #define _RTCC_RET_REG_REG_MASK 0xFFFFFFFFUL /**< Bit mask for RET_REG */ #define _RTCC_RET_REG_REG_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_RET_REG */ #define RTCC_RET_REG_REG_DEFAULT (_RTCC_RET_REG_REG_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_RET_REG */ /** @} */ /** @} End of group EFR32MG12P_RTCC */ /** @} End of group Parts */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_rtcc_cc.h.
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/***************************************************************************//** * @file * @brief EFR32MG12P_RTCC_CC register and bit field definitions * @version 5.7.0 ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * SPDX-License-Identifier: Zlib * * The licensor of this software is Silicon Laboratories Inc. * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be * appreciated but is not required. * 2. Altered source versions must be plainly marked as such, and must not be * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * ******************************************************************************/ #if defined(__ICCARM__) #pragma system_include /* Treat file as system include file. */ #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang system_header /* Treat file as system include file. */ #endif /***************************************************************************//** * @addtogroup Parts * @{ ******************************************************************************/ /***************************************************************************//** * @brief RTCC_CC RTCC CC Register * @ingroup EFR32MG12P_RTCC ******************************************************************************/ typedef struct { __IOM uint32_t CTRL; /**< CC Channel Control Register */ __IOM uint32_t CCV; /**< Capture/Compare Value Register */ __IOM uint32_t TIME; /**< Capture/Compare Time Register */ __IOM uint32_t DATE; /**< Capture/Compare Date Register */ } RTCC_CC_TypeDef; /** @} End of group Parts */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_rtcc_ret.h.
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/***************************************************************************//** * @file * @brief EFR32MG12P_RTCC_RET register and bit field definitions * @version 5.7.0 ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * SPDX-License-Identifier: Zlib * * The licensor of this software is Silicon Laboratories Inc. * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be * appreciated but is not required. * 2. Altered source versions must be plainly marked as such, and must not be * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * ******************************************************************************/ #if defined(__ICCARM__) #pragma system_include /* Treat file as system include file. */ #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang system_header /* Treat file as system include file. */ #endif /***************************************************************************//** * @addtogroup Parts * @{ ******************************************************************************/ /***************************************************************************//** * @brief RTCC_RET RTCC RET Register * @ingroup EFR32MG12P_RTCC ******************************************************************************/ typedef struct { __IOM uint32_t REG; /**< Retention Register */ } RTCC_RET_TypeDef; /** @} End of group Parts */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_smu.h.
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/***************************************************************************//** * @file * @brief EFR32MG12P_SMU register and bit field definitions * @version 5.7.0 ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * SPDX-License-Identifier: Zlib * * The licensor of this software is Silicon Laboratories Inc. * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be * appreciated but is not required. * 2. Altered source versions must be plainly marked as such, and must not be * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * ******************************************************************************/ #if defined(__ICCARM__) #pragma system_include /* Treat file as system include file. */ #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang system_header /* Treat file as system include file. */ #endif /***************************************************************************//** * @addtogroup Parts * @{ ******************************************************************************/ /***************************************************************************//** * @defgroup EFR32MG12P_SMU SMU * @{ * @brief EFR32MG12P_SMU Register Declaration ******************************************************************************/ /** SMU Register Declaration */ typedef struct { uint32_t RESERVED0[3U]; /**< Reserved for future use **/ __IM uint32_t IF; /**< Interrupt Flag Register */ __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ __IOM uint32_t IEN; /**< Interrupt Enable Register */ uint32_t RESERVED1[9U]; /**< Reserved for future use **/ __IOM uint32_t PPUCTRL; /**< PPU Control Register */ uint32_t RESERVED2[3U]; /**< Reserved for future use **/ __IOM uint32_t PPUPATD0; /**< PPU Privilege Access Type Descriptor 0 */ __IOM uint32_t PPUPATD1; /**< PPU Privilege Access Type Descriptor 1 */ uint32_t RESERVED3[14U]; /**< Reserved for future use **/ __IM uint32_t PPUFS; /**< PPU Fault Status */ } SMU_TypeDef; /** @} */ /***************************************************************************//** * @addtogroup EFR32MG12P_SMU * @{ * @defgroup EFR32MG12P_SMU_BitFields SMU Bit Fields * @{ ******************************************************************************/ /* Bit fields for SMU IF */ #define _SMU_IF_RESETVALUE 0x00000000UL /**< Default value for SMU_IF */ #define _SMU_IF_MASK 0x00000001UL /**< Mask for SMU_IF */ #define SMU_IF_PPUPRIV (0x1UL << 0) /**< PPU Privilege Interrupt Flag */ #define _SMU_IF_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ #define _SMU_IF_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ #define _SMU_IF_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IF */ #define SMU_IF_PPUPRIV_DEFAULT (_SMU_IF_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IF */ /* Bit fields for SMU IFS */ #define _SMU_IFS_RESETVALUE 0x00000000UL /**< Default value for SMU_IFS */ #define _SMU_IFS_MASK 0x00000001UL /**< Mask for SMU_IFS */ #define SMU_IFS_PPUPRIV (0x1UL << 0) /**< Set PPUPRIV Interrupt Flag */ #define _SMU_IFS_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ #define _SMU_IFS_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ #define _SMU_IFS_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IFS */ #define SMU_IFS_PPUPRIV_DEFAULT (_SMU_IFS_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IFS */ /* Bit fields for SMU IFC */ #define _SMU_IFC_RESETVALUE 0x00000000UL /**< Default value for SMU_IFC */ #define _SMU_IFC_MASK 0x00000001UL /**< Mask for SMU_IFC */ #define SMU_IFC_PPUPRIV (0x1UL << 0) /**< Clear PPUPRIV Interrupt Flag */ #define _SMU_IFC_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ #define _SMU_IFC_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ #define _SMU_IFC_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IFC */ #define SMU_IFC_PPUPRIV_DEFAULT (_SMU_IFC_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IFC */ /* Bit fields for SMU IEN */ #define _SMU_IEN_RESETVALUE 0x00000000UL /**< Default value for SMU_IEN */ #define _SMU_IEN_MASK 0x00000001UL /**< Mask for SMU_IEN */ #define SMU_IEN_PPUPRIV (0x1UL << 0) /**< PPUPRIV Interrupt Enable */ #define _SMU_IEN_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ #define _SMU_IEN_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ #define _SMU_IEN_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IEN */ #define SMU_IEN_PPUPRIV_DEFAULT (_SMU_IEN_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IEN */ /* Bit fields for SMU PPUCTRL */ #define _SMU_PPUCTRL_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUCTRL */ #define _SMU_PPUCTRL_MASK 0x00000001UL /**< Mask for SMU_PPUCTRL */ #define SMU_PPUCTRL_ENABLE (0x1UL << 0) /**< */ #define _SMU_PPUCTRL_ENABLE_SHIFT 0 /**< Shift value for SMU_ENABLE */ #define _SMU_PPUCTRL_ENABLE_MASK 0x1UL /**< Bit mask for SMU_ENABLE */ #define _SMU_PPUCTRL_ENABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUCTRL */ #define SMU_PPUCTRL_ENABLE_DEFAULT (_SMU_PPUCTRL_ENABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUCTRL */ /* Bit fields for SMU PPUPATD0 */ #define _SMU_PPUPATD0_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUPATD0 */ #define _SMU_PPUPATD0_MASK 0x3BFF7FA7UL /**< Mask for SMU_PPUPATD0 */ #define SMU_PPUPATD0_ACMP0 (0x1UL << 0) /**< Analog Comparator 0 access control bit */ #define _SMU_PPUPATD0_ACMP0_SHIFT 0 /**< Shift value for SMU_ACMP0 */ #define _SMU_PPUPATD0_ACMP0_MASK 0x1UL /**< Bit mask for SMU_ACMP0 */ #define _SMU_PPUPATD0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ #define SMU_PPUPATD0_ACMP0_DEFAULT (_SMU_PPUPATD0_ACMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ #define SMU_PPUPATD0_ACMP1 (0x1UL << 1) /**< Analog Comparator 1 access control bit */ #define _SMU_PPUPATD0_ACMP1_SHIFT 1 /**< Shift value for SMU_ACMP1 */ #define _SMU_PPUPATD0_ACMP1_MASK 0x2UL /**< Bit mask for SMU_ACMP1 */ #define _SMU_PPUPATD0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ #define SMU_PPUPATD0_ACMP1_DEFAULT (_SMU_PPUPATD0_ACMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ #define SMU_PPUPATD0_ADC0 (0x1UL << 2) /**< Analog to Digital Converter 0 access control bit */ #define _SMU_PPUPATD0_ADC0_SHIFT 2 /**< Shift value for SMU_ADC0 */ #define _SMU_PPUPATD0_ADC0_MASK 0x4UL /**< Bit mask for SMU_ADC0 */ #define _SMU_PPUPATD0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ #define SMU_PPUPATD0_ADC0_DEFAULT (_SMU_PPUPATD0_ADC0_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ #define SMU_PPUPATD0_CMU (0x1UL << 5) /**< Clock Management Unit access control bit */ #define _SMU_PPUPATD0_CMU_SHIFT 5 /**< Shift value for SMU_CMU */ #define _SMU_PPUPATD0_CMU_MASK 0x20UL /**< Bit mask for SMU_CMU */ #define _SMU_PPUPATD0_CMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ #define SMU_PPUPATD0_CMU_DEFAULT (_SMU_PPUPATD0_CMU_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ #define SMU_PPUPATD0_CRYOTIMER (0x1UL << 7) /**< CryoTimer access control bit */ #define _SMU_PPUPATD0_CRYOTIMER_SHIFT 7 /**< Shift value for SMU_CRYOTIMER */ #define _SMU_PPUPATD0_CRYOTIMER_MASK 0x80UL /**< Bit mask for SMU_CRYOTIMER */ #define _SMU_PPUPATD0_CRYOTIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ #define SMU_PPUPATD0_CRYOTIMER_DEFAULT (_SMU_PPUPATD0_CRYOTIMER_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ #define SMU_PPUPATD0_CRYPTO0 (0x1UL << 8) /**< Advanced Encryption Standard Accelerator 0 access control bit */ #define _SMU_PPUPATD0_CRYPTO0_SHIFT 8 /**< Shift value for SMU_CRYPTO0 */ #define _SMU_PPUPATD0_CRYPTO0_MASK 0x100UL /**< Bit mask for SMU_CRYPTO0 */ #define _SMU_PPUPATD0_CRYPTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ #define SMU_PPUPATD0_CRYPTO0_DEFAULT (_SMU_PPUPATD0_CRYPTO0_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ #define SMU_PPUPATD0_CRYPTO1 (0x1UL << 9) /**< Advanced Encryption Standard Accelerator 1 access control bit */ #define _SMU_PPUPATD0_CRYPTO1_SHIFT 9 /**< Shift value for SMU_CRYPTO1 */ #define _SMU_PPUPATD0_CRYPTO1_MASK 0x200UL /**< Bit mask for SMU_CRYPTO1 */ #define _SMU_PPUPATD0_CRYPTO1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ #define SMU_PPUPATD0_CRYPTO1_DEFAULT (_SMU_PPUPATD0_CRYPTO1_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ #define SMU_PPUPATD0_CSEN (0x1UL << 10) /**< Capacitive touch sense module access control bit */ #define _SMU_PPUPATD0_CSEN_SHIFT 10 /**< Shift value for SMU_CSEN */ #define _SMU_PPUPATD0_CSEN_MASK 0x400UL /**< Bit mask for SMU_CSEN */ #define _SMU_PPUPATD0_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ #define SMU_PPUPATD0_CSEN_DEFAULT (_SMU_PPUPATD0_CSEN_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ #define SMU_PPUPATD0_VDAC0 (0x1UL << 11) /**< Digital to Analog Converter 0 access control bit */ #define _SMU_PPUPATD0_VDAC0_SHIFT 11 /**< Shift value for SMU_VDAC0 */ #define _SMU_PPUPATD0_VDAC0_MASK 0x800UL /**< Bit mask for SMU_VDAC0 */ #define _SMU_PPUPATD0_VDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ #define SMU_PPUPATD0_VDAC0_DEFAULT (_SMU_PPUPATD0_VDAC0_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ #define SMU_PPUPATD0_PRS (0x1UL << 12) /**< Peripheral Reflex System access control bit */ #define _SMU_PPUPATD0_PRS_SHIFT 12 /**< Shift value for SMU_PRS */ #define _SMU_PPUPATD0_PRS_MASK 0x1000UL /**< Bit mask for SMU_PRS */ #define _SMU_PPUPATD0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ #define SMU_PPUPATD0_PRS_DEFAULT (_SMU_PPUPATD0_PRS_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ #define SMU_PPUPATD0_EMU (0x1UL << 13) /**< Energy Management Unit access control bit */ #define _SMU_PPUPATD0_EMU_SHIFT 13 /**< Shift value for SMU_EMU */ #define _SMU_PPUPATD0_EMU_MASK 0x2000UL /**< Bit mask for SMU_EMU */ #define _SMU_PPUPATD0_EMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ #define SMU_PPUPATD0_EMU_DEFAULT (_SMU_PPUPATD0_EMU_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ #define SMU_PPUPATD0_FPUEH (0x1UL << 14) /**< FPU Exception Handler access control bit */ #define _SMU_PPUPATD0_FPUEH_SHIFT 14 /**< Shift value for SMU_FPUEH */ #define _SMU_PPUPATD0_FPUEH_MASK 0x4000UL /**< Bit mask for SMU_FPUEH */ #define _SMU_PPUPATD0_FPUEH_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ #define SMU_PPUPATD0_FPUEH_DEFAULT (_SMU_PPUPATD0_FPUEH_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ #define SMU_PPUPATD0_GPCRC (0x1UL << 16) /**< General Purpose CRC access control bit */ #define _SMU_PPUPATD0_GPCRC_SHIFT 16 /**< Shift value for SMU_GPCRC */ #define _SMU_PPUPATD0_GPCRC_MASK 0x10000UL /**< Bit mask for SMU_GPCRC */ #define _SMU_PPUPATD0_GPCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ #define SMU_PPUPATD0_GPCRC_DEFAULT (_SMU_PPUPATD0_GPCRC_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ #define SMU_PPUPATD0_GPIO (0x1UL << 17) /**< General purpose Input/Output access control bit */ #define _SMU_PPUPATD0_GPIO_SHIFT 17 /**< Shift value for SMU_GPIO */ #define _SMU_PPUPATD0_GPIO_MASK 0x20000UL /**< Bit mask for SMU_GPIO */ #define _SMU_PPUPATD0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ #define SMU_PPUPATD0_GPIO_DEFAULT (_SMU_PPUPATD0_GPIO_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ #define SMU_PPUPATD0_I2C0 (0x1UL << 18) /**< I2C 0 access control bit */ #define _SMU_PPUPATD0_I2C0_SHIFT 18 /**< Shift value for SMU_I2C0 */ #define _SMU_PPUPATD0_I2C0_MASK 0x40000UL /**< Bit mask for SMU_I2C0 */ #define _SMU_PPUPATD0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ #define SMU_PPUPATD0_I2C0_DEFAULT (_SMU_PPUPATD0_I2C0_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ #define SMU_PPUPATD0_I2C1 (0x1UL << 19) /**< I2C 1 access control bit */ #define _SMU_PPUPATD0_I2C1_SHIFT 19 /**< Shift value for SMU_I2C1 */ #define _SMU_PPUPATD0_I2C1_MASK 0x80000UL /**< Bit mask for SMU_I2C1 */ #define _SMU_PPUPATD0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ #define SMU_PPUPATD0_I2C1_DEFAULT (_SMU_PPUPATD0_I2C1_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ #define SMU_PPUPATD0_IDAC0 (0x1UL << 20) /**< Current Digital to Analog Converter 0 access control bit */ #define _SMU_PPUPATD0_IDAC0_SHIFT 20 /**< Shift value for SMU_IDAC0 */ #define _SMU_PPUPATD0_IDAC0_MASK 0x100000UL /**< Bit mask for SMU_IDAC0 */ #define _SMU_PPUPATD0_IDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ #define SMU_PPUPATD0_IDAC0_DEFAULT (_SMU_PPUPATD0_IDAC0_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ #define SMU_PPUPATD0_MSC (0x1UL << 21) /**< Memory System Controller access control bit */ #define _SMU_PPUPATD0_MSC_SHIFT 21 /**< Shift value for SMU_MSC */ #define _SMU_PPUPATD0_MSC_MASK 0x200000UL /**< Bit mask for SMU_MSC */ #define _SMU_PPUPATD0_MSC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ #define SMU_PPUPATD0_MSC_DEFAULT (_SMU_PPUPATD0_MSC_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ #define SMU_PPUPATD0_LDMA (0x1UL << 22) /**< Linked Direct Memory Access Controller access control bit */ #define _SMU_PPUPATD0_LDMA_SHIFT 22 /**< Shift value for SMU_LDMA */ #define _SMU_PPUPATD0_LDMA_MASK 0x400000UL /**< Bit mask for SMU_LDMA */ #define _SMU_PPUPATD0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ #define SMU_PPUPATD0_LDMA_DEFAULT (_SMU_PPUPATD0_LDMA_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ #define SMU_PPUPATD0_LESENSE (0x1UL << 23) /**< Low Energy Sensor Interface access control bit */ #define _SMU_PPUPATD0_LESENSE_SHIFT 23 /**< Shift value for SMU_LESENSE */ #define _SMU_PPUPATD0_LESENSE_MASK 0x800000UL /**< Bit mask for SMU_LESENSE */ #define _SMU_PPUPATD0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ #define SMU_PPUPATD0_LESENSE_DEFAULT (_SMU_PPUPATD0_LESENSE_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ #define SMU_PPUPATD0_LETIMER0 (0x1UL << 24) /**< Low Energy Timer 0 access control bit */ #define _SMU_PPUPATD0_LETIMER0_SHIFT 24 /**< Shift value for SMU_LETIMER0 */ #define _SMU_PPUPATD0_LETIMER0_MASK 0x1000000UL /**< Bit mask for SMU_LETIMER0 */ #define _SMU_PPUPATD0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ #define SMU_PPUPATD0_LETIMER0_DEFAULT (_SMU_PPUPATD0_LETIMER0_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ #define SMU_PPUPATD0_LEUART0 (0x1UL << 25) /**< Low Energy UART 0 access control bit */ #define _SMU_PPUPATD0_LEUART0_SHIFT 25 /**< Shift value for SMU_LEUART0 */ #define _SMU_PPUPATD0_LEUART0_MASK 0x2000000UL /**< Bit mask for SMU_LEUART0 */ #define _SMU_PPUPATD0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ #define SMU_PPUPATD0_LEUART0_DEFAULT (_SMU_PPUPATD0_LEUART0_DEFAULT << 25) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ #define SMU_PPUPATD0_PCNT0 (0x1UL << 27) /**< Pulse Counter 0 access control bit */ #define _SMU_PPUPATD0_PCNT0_SHIFT 27 /**< Shift value for SMU_PCNT0 */ #define _SMU_PPUPATD0_PCNT0_MASK 0x8000000UL /**< Bit mask for SMU_PCNT0 */ #define _SMU_PPUPATD0_PCNT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ #define SMU_PPUPATD0_PCNT0_DEFAULT (_SMU_PPUPATD0_PCNT0_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ #define SMU_PPUPATD0_PCNT1 (0x1UL << 28) /**< Pulse Counter 1 access control bit */ #define _SMU_PPUPATD0_PCNT1_SHIFT 28 /**< Shift value for SMU_PCNT1 */ #define _SMU_PPUPATD0_PCNT1_MASK 0x10000000UL /**< Bit mask for SMU_PCNT1 */ #define _SMU_PPUPATD0_PCNT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ #define SMU_PPUPATD0_PCNT1_DEFAULT (_SMU_PPUPATD0_PCNT1_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ #define SMU_PPUPATD0_PCNT2 (0x1UL << 29) /**< Pulse Counter 2 access control bit */ #define _SMU_PPUPATD0_PCNT2_SHIFT 29 /**< Shift value for SMU_PCNT2 */ #define _SMU_PPUPATD0_PCNT2_MASK 0x20000000UL /**< Bit mask for SMU_PCNT2 */ #define _SMU_PPUPATD0_PCNT2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ #define SMU_PPUPATD0_PCNT2_DEFAULT (_SMU_PPUPATD0_PCNT2_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ /* Bit fields for SMU PPUPATD1 */ #define _SMU_PPUPATD1_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUPATD1 */ #define _SMU_PPUPATD1_MASK 0x0000FFEEUL /**< Mask for SMU_PPUPATD1 */ #define SMU_PPUPATD1_RMU (0x1UL << 1) /**< Reset Management Unit access control bit */ #define _SMU_PPUPATD1_RMU_SHIFT 1 /**< Shift value for SMU_RMU */ #define _SMU_PPUPATD1_RMU_MASK 0x2UL /**< Bit mask for SMU_RMU */ #define _SMU_PPUPATD1_RMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ #define SMU_PPUPATD1_RMU_DEFAULT (_SMU_PPUPATD1_RMU_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ #define SMU_PPUPATD1_RTCC (0x1UL << 2) /**< Real-Time Counter and Calendar access control bit */ #define _SMU_PPUPATD1_RTCC_SHIFT 2 /**< Shift value for SMU_RTCC */ #define _SMU_PPUPATD1_RTCC_MASK 0x4UL /**< Bit mask for SMU_RTCC */ #define _SMU_PPUPATD1_RTCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ #define SMU_PPUPATD1_RTCC_DEFAULT (_SMU_PPUPATD1_RTCC_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ #define SMU_PPUPATD1_SMU (0x1UL << 3) /**< Security Management Unit access control bit */ #define _SMU_PPUPATD1_SMU_SHIFT 3 /**< Shift value for SMU_SMU */ #define _SMU_PPUPATD1_SMU_MASK 0x8UL /**< Bit mask for SMU_SMU */ #define _SMU_PPUPATD1_SMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ #define SMU_PPUPATD1_SMU_DEFAULT (_SMU_PPUPATD1_SMU_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ #define SMU_PPUPATD1_TIMER0 (0x1UL << 5) /**< Timer 0 access control bit */ #define _SMU_PPUPATD1_TIMER0_SHIFT 5 /**< Shift value for SMU_TIMER0 */ #define _SMU_PPUPATD1_TIMER0_MASK 0x20UL /**< Bit mask for SMU_TIMER0 */ #define _SMU_PPUPATD1_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ #define SMU_PPUPATD1_TIMER0_DEFAULT (_SMU_PPUPATD1_TIMER0_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ #define SMU_PPUPATD1_TIMER1 (0x1UL << 6) /**< Timer 1 access control bit */ #define _SMU_PPUPATD1_TIMER1_SHIFT 6 /**< Shift value for SMU_TIMER1 */ #define _SMU_PPUPATD1_TIMER1_MASK 0x40UL /**< Bit mask for SMU_TIMER1 */ #define _SMU_PPUPATD1_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ #define SMU_PPUPATD1_TIMER1_DEFAULT (_SMU_PPUPATD1_TIMER1_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ #define SMU_PPUPATD1_TRNG0 (0x1UL << 7) /**< True Random Number Generator 0 access control bit */ #define _SMU_PPUPATD1_TRNG0_SHIFT 7 /**< Shift value for SMU_TRNG0 */ #define _SMU_PPUPATD1_TRNG0_MASK 0x80UL /**< Bit mask for SMU_TRNG0 */ #define _SMU_PPUPATD1_TRNG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ #define SMU_PPUPATD1_TRNG0_DEFAULT (_SMU_PPUPATD1_TRNG0_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ #define SMU_PPUPATD1_USART0 (0x1UL << 8) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 access control bit */ #define _SMU_PPUPATD1_USART0_SHIFT 8 /**< Shift value for SMU_USART0 */ #define _SMU_PPUPATD1_USART0_MASK 0x100UL /**< Bit mask for SMU_USART0 */ #define _SMU_PPUPATD1_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ #define SMU_PPUPATD1_USART0_DEFAULT (_SMU_PPUPATD1_USART0_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ #define SMU_PPUPATD1_USART1 (0x1UL << 9) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 access control bit */ #define _SMU_PPUPATD1_USART1_SHIFT 9 /**< Shift value for SMU_USART1 */ #define _SMU_PPUPATD1_USART1_MASK 0x200UL /**< Bit mask for SMU_USART1 */ #define _SMU_PPUPATD1_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ #define SMU_PPUPATD1_USART1_DEFAULT (_SMU_PPUPATD1_USART1_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ #define SMU_PPUPATD1_USART2 (0x1UL << 10) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 access control bit */ #define _SMU_PPUPATD1_USART2_SHIFT 10 /**< Shift value for SMU_USART2 */ #define _SMU_PPUPATD1_USART2_MASK 0x400UL /**< Bit mask for SMU_USART2 */ #define _SMU_PPUPATD1_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ #define SMU_PPUPATD1_USART2_DEFAULT (_SMU_PPUPATD1_USART2_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ #define SMU_PPUPATD1_USART3 (0x1UL << 11) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 3 access control bit */ #define _SMU_PPUPATD1_USART3_SHIFT 11 /**< Shift value for SMU_USART3 */ #define _SMU_PPUPATD1_USART3_MASK 0x800UL /**< Bit mask for SMU_USART3 */ #define _SMU_PPUPATD1_USART3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ #define SMU_PPUPATD1_USART3_DEFAULT (_SMU_PPUPATD1_USART3_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ #define SMU_PPUPATD1_WDOG0 (0x1UL << 12) /**< Watchdog 0 access control bit */ #define _SMU_PPUPATD1_WDOG0_SHIFT 12 /**< Shift value for SMU_WDOG0 */ #define _SMU_PPUPATD1_WDOG0_MASK 0x1000UL /**< Bit mask for SMU_WDOG0 */ #define _SMU_PPUPATD1_WDOG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ #define SMU_PPUPATD1_WDOG0_DEFAULT (_SMU_PPUPATD1_WDOG0_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ #define SMU_PPUPATD1_WDOG1 (0x1UL << 13) /**< Watchdog 1 access control bit */ #define _SMU_PPUPATD1_WDOG1_SHIFT 13 /**< Shift value for SMU_WDOG1 */ #define _SMU_PPUPATD1_WDOG1_MASK 0x2000UL /**< Bit mask for SMU_WDOG1 */ #define _SMU_PPUPATD1_WDOG1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ #define SMU_PPUPATD1_WDOG1_DEFAULT (_SMU_PPUPATD1_WDOG1_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ #define SMU_PPUPATD1_WTIMER0 (0x1UL << 14) /**< Wide Timer 0 access control bit */ #define _SMU_PPUPATD1_WTIMER0_SHIFT 14 /**< Shift value for SMU_WTIMER0 */ #define _SMU_PPUPATD1_WTIMER0_MASK 0x4000UL /**< Bit mask for SMU_WTIMER0 */ #define _SMU_PPUPATD1_WTIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ #define SMU_PPUPATD1_WTIMER0_DEFAULT (_SMU_PPUPATD1_WTIMER0_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ #define SMU_PPUPATD1_WTIMER1 (0x1UL << 15) /**< Wide Timer 1 access control bit */ #define _SMU_PPUPATD1_WTIMER1_SHIFT 15 /**< Shift value for SMU_WTIMER1 */ #define _SMU_PPUPATD1_WTIMER1_MASK 0x8000UL /**< Bit mask for SMU_WTIMER1 */ #define _SMU_PPUPATD1_WTIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ #define SMU_PPUPATD1_WTIMER1_DEFAULT (_SMU_PPUPATD1_WTIMER1_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ /* Bit fields for SMU PPUFS */ #define _SMU_PPUFS_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUFS */ #define _SMU_PPUFS_MASK 0x0000007FUL /**< Mask for SMU_PPUFS */ #define _SMU_PPUFS_PERIPHID_SHIFT 0 /**< Shift value for SMU_PERIPHID */ #define _SMU_PPUFS_PERIPHID_MASK 0x7FUL /**< Bit mask for SMU_PERIPHID */ #define _SMU_PPUFS_PERIPHID_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUFS */ #define _SMU_PPUFS_PERIPHID_ACMP0 0x00000000UL /**< Mode ACMP0 for SMU_PPUFS */ #define _SMU_PPUFS_PERIPHID_ACMP1 0x00000001UL /**< Mode ACMP1 for SMU_PPUFS */ #define _SMU_PPUFS_PERIPHID_ADC0 0x00000002UL /**< Mode ADC0 for SMU_PPUFS */ #define _SMU_PPUFS_PERIPHID_CMU 0x00000005UL /**< Mode CMU for SMU_PPUFS */ #define _SMU_PPUFS_PERIPHID_CRYOTIMER 0x00000007UL /**< Mode CRYOTIMER for SMU_PPUFS */ #define _SMU_PPUFS_PERIPHID_CRYPTO0 0x00000008UL /**< Mode CRYPTO0 for SMU_PPUFS */ #define _SMU_PPUFS_PERIPHID_CRYPTO1 0x00000009UL /**< Mode CRYPTO1 for SMU_PPUFS */ #define _SMU_PPUFS_PERIPHID_CSEN 0x0000000AUL /**< Mode CSEN for SMU_PPUFS */ #define _SMU_PPUFS_PERIPHID_VDAC0 0x0000000BUL /**< Mode VDAC0 for SMU_PPUFS */ #define _SMU_PPUFS_PERIPHID_PRS 0x0000000CUL /**< Mode PRS for SMU_PPUFS */ #define _SMU_PPUFS_PERIPHID_EMU 0x0000000DUL /**< Mode EMU for SMU_PPUFS */ #define _SMU_PPUFS_PERIPHID_FPUEH 0x0000000EUL /**< Mode FPUEH for SMU_PPUFS */ #define _SMU_PPUFS_PERIPHID_GPCRC 0x00000010UL /**< Mode GPCRC for SMU_PPUFS */ #define _SMU_PPUFS_PERIPHID_GPIO 0x00000011UL /**< Mode GPIO for SMU_PPUFS */ #define _SMU_PPUFS_PERIPHID_I2C0 0x00000012UL /**< Mode I2C0 for SMU_PPUFS */ #define _SMU_PPUFS_PERIPHID_I2C1 0x00000013UL /**< Mode I2C1 for SMU_PPUFS */ #define _SMU_PPUFS_PERIPHID_IDAC0 0x00000014UL /**< Mode IDAC0 for SMU_PPUFS */ #define _SMU_PPUFS_PERIPHID_MSC 0x00000015UL /**< Mode MSC for SMU_PPUFS */ #define _SMU_PPUFS_PERIPHID_LDMA 0x00000016UL /**< Mode LDMA for SMU_PPUFS */ #define _SMU_PPUFS_PERIPHID_LESENSE 0x00000017UL /**< Mode LESENSE for SMU_PPUFS */ #define _SMU_PPUFS_PERIPHID_LETIMER0 0x00000018UL /**< Mode LETIMER0 for SMU_PPUFS */ #define _SMU_PPUFS_PERIPHID_LEUART0 0x00000019UL /**< Mode LEUART0 for SMU_PPUFS */ #define _SMU_PPUFS_PERIPHID_PCNT0 0x0000001BUL /**< Mode PCNT0 for SMU_PPUFS */ #define _SMU_PPUFS_PERIPHID_PCNT1 0x0000001CUL /**< Mode PCNT1 for SMU_PPUFS */ #define _SMU_PPUFS_PERIPHID_PCNT2 0x0000001DUL /**< Mode PCNT2 for SMU_PPUFS */ #define _SMU_PPUFS_PERIPHID_RMU 0x00000021UL /**< Mode RMU for SMU_PPUFS */ #define _SMU_PPUFS_PERIPHID_RTCC 0x00000022UL /**< Mode RTCC for SMU_PPUFS */ #define _SMU_PPUFS_PERIPHID_SMU 0x00000023UL /**< Mode SMU for SMU_PPUFS */ #define _SMU_PPUFS_PERIPHID_TIMER0 0x00000025UL /**< Mode TIMER0 for SMU_PPUFS */ #define _SMU_PPUFS_PERIPHID_TIMER1 0x00000026UL /**< Mode TIMER1 for SMU_PPUFS */ #define _SMU_PPUFS_PERIPHID_TRNG0 0x00000027UL /**< Mode TRNG0 for SMU_PPUFS */ #define _SMU_PPUFS_PERIPHID_USART0 0x00000028UL /**< Mode USART0 for SMU_PPUFS */ #define _SMU_PPUFS_PERIPHID_USART1 0x00000029UL /**< Mode USART1 for SMU_PPUFS */ #define _SMU_PPUFS_PERIPHID_USART2 0x0000002AUL /**< Mode USART2 for SMU_PPUFS */ #define _SMU_PPUFS_PERIPHID_USART3 0x0000002BUL /**< Mode USART3 for SMU_PPUFS */ #define _SMU_PPUFS_PERIPHID_WDOG0 0x0000002CUL /**< Mode WDOG0 for SMU_PPUFS */ #define _SMU_PPUFS_PERIPHID_WDOG1 0x0000002DUL /**< Mode WDOG1 for SMU_PPUFS */ #define _SMU_PPUFS_PERIPHID_WTIMER0 0x0000002EUL /**< Mode WTIMER0 for SMU_PPUFS */ #define _SMU_PPUFS_PERIPHID_WTIMER1 0x0000002FUL /**< Mode WTIMER1 for SMU_PPUFS */ #define SMU_PPUFS_PERIPHID_DEFAULT (_SMU_PPUFS_PERIPHID_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUFS */ #define SMU_PPUFS_PERIPHID_ACMP0 (_SMU_PPUFS_PERIPHID_ACMP0 << 0) /**< Shifted mode ACMP0 for SMU_PPUFS */ #define SMU_PPUFS_PERIPHID_ACMP1 (_SMU_PPUFS_PERIPHID_ACMP1 << 0) /**< Shifted mode ACMP1 for SMU_PPUFS */ #define SMU_PPUFS_PERIPHID_ADC0 (_SMU_PPUFS_PERIPHID_ADC0 << 0) /**< Shifted mode ADC0 for SMU_PPUFS */ #define SMU_PPUFS_PERIPHID_CMU (_SMU_PPUFS_PERIPHID_CMU << 0) /**< Shifted mode CMU for SMU_PPUFS */ #define SMU_PPUFS_PERIPHID_CRYOTIMER (_SMU_PPUFS_PERIPHID_CRYOTIMER << 0) /**< Shifted mode CRYOTIMER for SMU_PPUFS */ #define SMU_PPUFS_PERIPHID_CRYPTO0 (_SMU_PPUFS_PERIPHID_CRYPTO0 << 0) /**< Shifted mode CRYPTO0 for SMU_PPUFS */ #define SMU_PPUFS_PERIPHID_CRYPTO1 (_SMU_PPUFS_PERIPHID_CRYPTO1 << 0) /**< Shifted mode CRYPTO1 for SMU_PPUFS */ #define SMU_PPUFS_PERIPHID_CSEN (_SMU_PPUFS_PERIPHID_CSEN << 0) /**< Shifted mode CSEN for SMU_PPUFS */ #define SMU_PPUFS_PERIPHID_VDAC0 (_SMU_PPUFS_PERIPHID_VDAC0 << 0) /**< Shifted mode VDAC0 for SMU_PPUFS */ #define SMU_PPUFS_PERIPHID_PRS (_SMU_PPUFS_PERIPHID_PRS << 0) /**< Shifted mode PRS for SMU_PPUFS */ #define SMU_PPUFS_PERIPHID_EMU (_SMU_PPUFS_PERIPHID_EMU << 0) /**< Shifted mode EMU for SMU_PPUFS */ #define SMU_PPUFS_PERIPHID_FPUEH (_SMU_PPUFS_PERIPHID_FPUEH << 0) /**< Shifted mode FPUEH for SMU_PPUFS */ #define SMU_PPUFS_PERIPHID_GPCRC (_SMU_PPUFS_PERIPHID_GPCRC << 0) /**< Shifted mode GPCRC for SMU_PPUFS */ #define SMU_PPUFS_PERIPHID_GPIO (_SMU_PPUFS_PERIPHID_GPIO << 0) /**< Shifted mode GPIO for SMU_PPUFS */ #define SMU_PPUFS_PERIPHID_I2C0 (_SMU_PPUFS_PERIPHID_I2C0 << 0) /**< Shifted mode I2C0 for SMU_PPUFS */ #define SMU_PPUFS_PERIPHID_I2C1 (_SMU_PPUFS_PERIPHID_I2C1 << 0) /**< Shifted mode I2C1 for SMU_PPUFS */ #define SMU_PPUFS_PERIPHID_IDAC0 (_SMU_PPUFS_PERIPHID_IDAC0 << 0) /**< Shifted mode IDAC0 for SMU_PPUFS */ #define SMU_PPUFS_PERIPHID_MSC (_SMU_PPUFS_PERIPHID_MSC << 0) /**< Shifted mode MSC for SMU_PPUFS */ #define SMU_PPUFS_PERIPHID_LDMA (_SMU_PPUFS_PERIPHID_LDMA << 0) /**< Shifted mode LDMA for SMU_PPUFS */ #define SMU_PPUFS_PERIPHID_LESENSE (_SMU_PPUFS_PERIPHID_LESENSE << 0) /**< Shifted mode LESENSE for SMU_PPUFS */ #define SMU_PPUFS_PERIPHID_LETIMER0 (_SMU_PPUFS_PERIPHID_LETIMER0 << 0) /**< Shifted mode LETIMER0 for SMU_PPUFS */ #define SMU_PPUFS_PERIPHID_LEUART0 (_SMU_PPUFS_PERIPHID_LEUART0 << 0) /**< Shifted mode LEUART0 for SMU_PPUFS */ #define SMU_PPUFS_PERIPHID_PCNT0 (_SMU_PPUFS_PERIPHID_PCNT0 << 0) /**< Shifted mode PCNT0 for SMU_PPUFS */ #define SMU_PPUFS_PERIPHID_PCNT1 (_SMU_PPUFS_PERIPHID_PCNT1 << 0) /**< Shifted mode PCNT1 for SMU_PPUFS */ #define SMU_PPUFS_PERIPHID_PCNT2 (_SMU_PPUFS_PERIPHID_PCNT2 << 0) /**< Shifted mode PCNT2 for SMU_PPUFS */ #define SMU_PPUFS_PERIPHID_RMU (_SMU_PPUFS_PERIPHID_RMU << 0) /**< Shifted mode RMU for SMU_PPUFS */ #define SMU_PPUFS_PERIPHID_RTCC (_SMU_PPUFS_PERIPHID_RTCC << 0) /**< Shifted mode RTCC for SMU_PPUFS */ #define SMU_PPUFS_PERIPHID_SMU (_SMU_PPUFS_PERIPHID_SMU << 0) /**< Shifted mode SMU for SMU_PPUFS */ #define SMU_PPUFS_PERIPHID_TIMER0 (_SMU_PPUFS_PERIPHID_TIMER0 << 0) /**< Shifted mode TIMER0 for SMU_PPUFS */ #define SMU_PPUFS_PERIPHID_TIMER1 (_SMU_PPUFS_PERIPHID_TIMER1 << 0) /**< Shifted mode TIMER1 for SMU_PPUFS */ #define SMU_PPUFS_PERIPHID_TRNG0 (_SMU_PPUFS_PERIPHID_TRNG0 << 0) /**< Shifted mode TRNG0 for SMU_PPUFS */ #define SMU_PPUFS_PERIPHID_USART0 (_SMU_PPUFS_PERIPHID_USART0 << 0) /**< Shifted mode USART0 for SMU_PPUFS */ #define SMU_PPUFS_PERIPHID_USART1 (_SMU_PPUFS_PERIPHID_USART1 << 0) /**< Shifted mode USART1 for SMU_PPUFS */ #define SMU_PPUFS_PERIPHID_USART2 (_SMU_PPUFS_PERIPHID_USART2 << 0) /**< Shifted mode USART2 for SMU_PPUFS */ #define SMU_PPUFS_PERIPHID_USART3 (_SMU_PPUFS_PERIPHID_USART3 << 0) /**< Shifted mode USART3 for SMU_PPUFS */ #define SMU_PPUFS_PERIPHID_WDOG0 (_SMU_PPUFS_PERIPHID_WDOG0 << 0) /**< Shifted mode WDOG0 for SMU_PPUFS */ #define SMU_PPUFS_PERIPHID_WDOG1 (_SMU_PPUFS_PERIPHID_WDOG1 << 0) /**< Shifted mode WDOG1 for SMU_PPUFS */ #define SMU_PPUFS_PERIPHID_WTIMER0 (_SMU_PPUFS_PERIPHID_WTIMER0 << 0) /**< Shifted mode WTIMER0 for SMU_PPUFS */ #define SMU_PPUFS_PERIPHID_WTIMER1 (_SMU_PPUFS_PERIPHID_WTIMER1 << 0) /**< Shifted mode WTIMER1 for SMU_PPUFS */ /** @} */ /** @} End of group EFR32MG12P_SMU */ /** @} End of group Parts */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_timer.h.
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/***************************************************************************//** * @file * @brief EFR32MG12P_TIMER register and bit field definitions * @version 5.7.0 ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * SPDX-License-Identifier: Zlib * * The licensor of this software is Silicon Laboratories Inc. * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be * appreciated but is not required. * 2. Altered source versions must be plainly marked as such, and must not be * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * ******************************************************************************/ #if defined(__ICCARM__) #pragma system_include /* Treat file as system include file. */ #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang system_header /* Treat file as system include file. */ #endif /***************************************************************************//** * @addtogroup Parts * @{ ******************************************************************************/ /***************************************************************************//** * @defgroup EFR32MG12P_TIMER TIMER * @{ * @brief EFR32MG12P_TIMER Register Declaration ******************************************************************************/ /** TIMER Register Declaration */ typedef struct { __IOM uint32_t CTRL; /**< Control Register */ __IOM uint32_t CMD; /**< Command Register */ __IM uint32_t STATUS; /**< Status Register */ __IM uint32_t IF; /**< Interrupt Flag Register */ __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ __IOM uint32_t IEN; /**< Interrupt Enable Register */ __IOM uint32_t TOP; /**< Counter Top Value Register */ __IOM uint32_t TOPB; /**< Counter Top Value Buffer Register */ __IOM uint32_t CNT; /**< Counter Value Register */ uint32_t RESERVED0[1U]; /**< Reserved for future use **/ __IOM uint32_t LOCK; /**< TIMER Configuration Lock Register */ __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ uint32_t RESERVED1[1U]; /**< Reserved for future use **/ __IOM uint32_t ROUTELOC2; /**< I/O Routing Location Register */ uint32_t RESERVED2[8U]; /**< Reserved registers */ TIMER_CC_TypeDef CC[4U]; /**< Compare/Capture Channel */ __IOM uint32_t DTCTRL; /**< DTI Control Register */ __IOM uint32_t DTTIME; /**< DTI Time Control Register */ __IOM uint32_t DTFC; /**< DTI Fault Configuration Register */ __IOM uint32_t DTOGEN; /**< DTI Output Generation Enable Register */ __IM uint32_t DTFAULT; /**< DTI Fault Register */ __IOM uint32_t DTFAULTC; /**< DTI Fault Clear Register */ __IOM uint32_t DTLOCK; /**< DTI Configuration Lock Register */ } TIMER_TypeDef; /** @} */ /***************************************************************************//** * @addtogroup EFR32MG12P_TIMER * @{ * @defgroup EFR32MG12P_TIMER_BitFields TIMER Bit Fields * @{ ******************************************************************************/ /* Bit fields for TIMER CTRL */ #define _TIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for TIMER_CTRL */ #define _TIMER_CTRL_MASK 0x3F032FFBUL /**< Mask for TIMER_CTRL */ #define _TIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ #define _TIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ #define _TIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ #define _TIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for TIMER_CTRL */ #define _TIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for TIMER_CTRL */ #define _TIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for TIMER_CTRL */ #define _TIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for TIMER_CTRL */ #define TIMER_CTRL_MODE_DEFAULT (_TIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CTRL */ #define TIMER_CTRL_MODE_UP (_TIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for TIMER_CTRL */ #define TIMER_CTRL_MODE_DOWN (_TIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for TIMER_CTRL */ #define TIMER_CTRL_MODE_UPDOWN (_TIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for TIMER_CTRL */ #define TIMER_CTRL_MODE_QDEC (_TIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for TIMER_CTRL */ #define TIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ #define _TIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ #define _TIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ #define _TIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ #define TIMER_CTRL_SYNC_DEFAULT (_TIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_CTRL */ #define TIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ #define _TIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ #define _TIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ #define _TIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ #define TIMER_CTRL_OSMEN_DEFAULT (_TIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_CTRL */ #define TIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ #define _TIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ #define _TIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ #define _TIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ #define _TIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for TIMER_CTRL */ #define _TIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for TIMER_CTRL */ #define TIMER_CTRL_QDM_DEFAULT (_TIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_CTRL */ #define TIMER_CTRL_QDM_X2 (_TIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for TIMER_CTRL */ #define TIMER_CTRL_QDM_X4 (_TIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for TIMER_CTRL */ #define TIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ #define _TIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ #define _TIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ #define _TIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ #define TIMER_CTRL_DEBUGRUN_DEFAULT (_TIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_CTRL */ #define TIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ #define _TIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ #define _TIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ #define _TIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ #define TIMER_CTRL_DMACLRACT_DEFAULT (_TIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for TIMER_CTRL */ #define _TIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */ #define _TIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */ #define _TIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ #define _TIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for TIMER_CTRL */ #define _TIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for TIMER_CTRL */ #define _TIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for TIMER_CTRL */ #define _TIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for TIMER_CTRL */ #define TIMER_CTRL_RISEA_DEFAULT (_TIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_CTRL */ #define TIMER_CTRL_RISEA_NONE (_TIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for TIMER_CTRL */ #define TIMER_CTRL_RISEA_START (_TIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for TIMER_CTRL */ #define TIMER_CTRL_RISEA_STOP (_TIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for TIMER_CTRL */ #define TIMER_CTRL_RISEA_RELOADSTART (_TIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for TIMER_CTRL */ #define _TIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */ #define _TIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */ #define _TIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ #define _TIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for TIMER_CTRL */ #define _TIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for TIMER_CTRL */ #define _TIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for TIMER_CTRL */ #define _TIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for TIMER_CTRL */ #define TIMER_CTRL_FALLA_DEFAULT (_TIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_CTRL */ #define TIMER_CTRL_FALLA_NONE (_TIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for TIMER_CTRL */ #define TIMER_CTRL_FALLA_START (_TIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for TIMER_CTRL */ #define TIMER_CTRL_FALLA_STOP (_TIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for TIMER_CTRL */ #define TIMER_CTRL_FALLA_RELOADSTART (_TIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for TIMER_CTRL */ #define TIMER_CTRL_X2CNT (0x1UL << 13) /**< 2x Count Mode */ #define _TIMER_CTRL_X2CNT_SHIFT 13 /**< Shift value for TIMER_X2CNT */ #define _TIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */ #define _TIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ #define TIMER_CTRL_X2CNT_DEFAULT (_TIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for TIMER_CTRL */ #define _TIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */ #define _TIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */ #define _TIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ #define _TIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for TIMER_CTRL */ #define _TIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for TIMER_CTRL */ #define _TIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for TIMER_CTRL */ #define TIMER_CTRL_CLKSEL_DEFAULT (_TIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_CTRL */ #define TIMER_CTRL_CLKSEL_PRESCHFPERCLK (_TIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for TIMER_CTRL */ #define TIMER_CTRL_CLKSEL_CC1 (_TIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for TIMER_CTRL */ #define TIMER_CTRL_CLKSEL_TIMEROUF (_TIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for TIMER_CTRL */ #define _TIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */ #define _TIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */ #define _TIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ #define _TIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for TIMER_CTRL */ #define _TIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for TIMER_CTRL */ #define _TIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for TIMER_CTRL */ #define _TIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for TIMER_CTRL */ #define _TIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for TIMER_CTRL */ #define _TIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for TIMER_CTRL */ #define _TIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for TIMER_CTRL */ #define _TIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for TIMER_CTRL */ #define _TIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for TIMER_CTRL */ #define _TIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for TIMER_CTRL */ #define _TIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for TIMER_CTRL */ #define TIMER_CTRL_PRESC_DEFAULT (_TIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_CTRL */ #define TIMER_CTRL_PRESC_DIV1 (_TIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for TIMER_CTRL */ #define TIMER_CTRL_PRESC_DIV2 (_TIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for TIMER_CTRL */ #define TIMER_CTRL_PRESC_DIV4 (_TIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for TIMER_CTRL */ #define TIMER_CTRL_PRESC_DIV8 (_TIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for TIMER_CTRL */ #define TIMER_CTRL_PRESC_DIV16 (_TIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for TIMER_CTRL */ #define TIMER_CTRL_PRESC_DIV32 (_TIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for TIMER_CTRL */ #define TIMER_CTRL_PRESC_DIV64 (_TIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for TIMER_CTRL */ #define TIMER_CTRL_PRESC_DIV128 (_TIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for TIMER_CTRL */ #define TIMER_CTRL_PRESC_DIV256 (_TIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for TIMER_CTRL */ #define TIMER_CTRL_PRESC_DIV512 (_TIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for TIMER_CTRL */ #define TIMER_CTRL_PRESC_DIV1024 (_TIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for TIMER_CTRL */ #define TIMER_CTRL_ATI (0x1UL << 28) /**< Always Track Inputs */ #define _TIMER_CTRL_ATI_SHIFT 28 /**< Shift value for TIMER_ATI */ #define _TIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */ #define _TIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ #define TIMER_CTRL_ATI_DEFAULT (_TIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for TIMER_CTRL */ #define TIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output Initial State */ #define _TIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */ #define _TIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */ #define _TIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ #define TIMER_CTRL_RSSCOIST_DEFAULT (_TIMER_CTRL_RSSCOIST_DEFAULT << 29) /**< Shifted mode DEFAULT for TIMER_CTRL */ /* Bit fields for TIMER CMD */ #define _TIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for TIMER_CMD */ #define _TIMER_CMD_MASK 0x00000003UL /**< Mask for TIMER_CMD */ #define TIMER_CMD_START (0x1UL << 0) /**< Start Timer */ #define _TIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ #define _TIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ #define _TIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CMD */ #define TIMER_CMD_START_DEFAULT (_TIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CMD */ #define TIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ #define _TIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ #define _TIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ #define _TIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CMD */ #define TIMER_CMD_STOP_DEFAULT (_TIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_CMD */ /* Bit fields for TIMER STATUS */ #define _TIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for TIMER_STATUS */ #define _TIMER_STATUS_MASK 0x0F0F0F07UL /**< Mask for TIMER_STATUS */ #define TIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ #define _TIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ #define _TIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ #define _TIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ #define TIMER_STATUS_RUNNING_DEFAULT (_TIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_STATUS */ #define TIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ #define _TIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ #define _TIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ #define _TIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ #define _TIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for TIMER_STATUS */ #define _TIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for TIMER_STATUS */ #define TIMER_STATUS_DIR_DEFAULT (_TIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_STATUS */ #define TIMER_STATUS_DIR_UP (_TIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for TIMER_STATUS */ #define TIMER_STATUS_DIR_DOWN (_TIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for TIMER_STATUS */ #define TIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */ #define _TIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ #define _TIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ #define _TIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ #define TIMER_STATUS_TOPBV_DEFAULT (_TIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_STATUS */ #define TIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */ #define _TIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */ #define _TIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */ #define _TIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ #define TIMER_STATUS_CCVBV0_DEFAULT (_TIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_STATUS */ #define TIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */ #define _TIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */ #define _TIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */ #define _TIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ #define TIMER_STATUS_CCVBV1_DEFAULT (_TIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_STATUS */ #define TIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */ #define _TIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */ #define _TIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */ #define _TIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ #define TIMER_STATUS_CCVBV2_DEFAULT (_TIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_STATUS */ #define TIMER_STATUS_CCVBV3 (0x1UL << 11) /**< CC3 CCVB Valid */ #define _TIMER_STATUS_CCVBV3_SHIFT 11 /**< Shift value for TIMER_CCVBV3 */ #define _TIMER_STATUS_CCVBV3_MASK 0x800UL /**< Bit mask for TIMER_CCVBV3 */ #define _TIMER_STATUS_CCVBV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ #define TIMER_STATUS_CCVBV3_DEFAULT (_TIMER_STATUS_CCVBV3_DEFAULT << 11) /**< Shifted mode DEFAULT for TIMER_STATUS */ #define TIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */ #define _TIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */ #define _TIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */ #define _TIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ #define TIMER_STATUS_ICV0_DEFAULT (_TIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_STATUS */ #define TIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */ #define _TIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */ #define _TIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */ #define _TIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ #define TIMER_STATUS_ICV1_DEFAULT (_TIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for TIMER_STATUS */ #define TIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */ #define _TIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */ #define _TIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */ #define _TIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ #define TIMER_STATUS_ICV2_DEFAULT (_TIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for TIMER_STATUS */ #define TIMER_STATUS_ICV3 (0x1UL << 19) /**< CC3 Input Capture Valid */ #define _TIMER_STATUS_ICV3_SHIFT 19 /**< Shift value for TIMER_ICV3 */ #define _TIMER_STATUS_ICV3_MASK 0x80000UL /**< Bit mask for TIMER_ICV3 */ #define _TIMER_STATUS_ICV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ #define TIMER_STATUS_ICV3_DEFAULT (_TIMER_STATUS_ICV3_DEFAULT << 19) /**< Shifted mode DEFAULT for TIMER_STATUS */ #define TIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */ #define _TIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ #define _TIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ #define _TIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ #define _TIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for TIMER_STATUS */ #define _TIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for TIMER_STATUS */ #define TIMER_STATUS_CCPOL0_DEFAULT (_TIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_STATUS */ #define TIMER_STATUS_CCPOL0_LOWRISE (_TIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for TIMER_STATUS */ #define TIMER_STATUS_CCPOL0_HIGHFALL (_TIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for TIMER_STATUS */ #define TIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */ #define _TIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ #define _TIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ #define _TIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ #define _TIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for TIMER_STATUS */ #define _TIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for TIMER_STATUS */ #define TIMER_STATUS_CCPOL1_DEFAULT (_TIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for TIMER_STATUS */ #define TIMER_STATUS_CCPOL1_LOWRISE (_TIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for TIMER_STATUS */ #define TIMER_STATUS_CCPOL1_HIGHFALL (_TIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for TIMER_STATUS */ #define TIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */ #define _TIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ #define _TIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ #define _TIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ #define _TIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for TIMER_STATUS */ #define _TIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for TIMER_STATUS */ #define TIMER_STATUS_CCPOL2_DEFAULT (_TIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for TIMER_STATUS */ #define TIMER_STATUS_CCPOL2_LOWRISE (_TIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for TIMER_STATUS */ #define TIMER_STATUS_CCPOL2_HIGHFALL (_TIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for TIMER_STATUS */ #define TIMER_STATUS_CCPOL3 (0x1UL << 27) /**< CC3 Polarity */ #define _TIMER_STATUS_CCPOL3_SHIFT 27 /**< Shift value for TIMER_CCPOL3 */ #define _TIMER_STATUS_CCPOL3_MASK 0x8000000UL /**< Bit mask for TIMER_CCPOL3 */ #define _TIMER_STATUS_CCPOL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ #define _TIMER_STATUS_CCPOL3_LOWRISE 0x00000000UL /**< Mode LOWRISE for TIMER_STATUS */ #define _TIMER_STATUS_CCPOL3_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for TIMER_STATUS */ #define TIMER_STATUS_CCPOL3_DEFAULT (_TIMER_STATUS_CCPOL3_DEFAULT << 27) /**< Shifted mode DEFAULT for TIMER_STATUS */ #define TIMER_STATUS_CCPOL3_LOWRISE (_TIMER_STATUS_CCPOL3_LOWRISE << 27) /**< Shifted mode LOWRISE for TIMER_STATUS */ #define TIMER_STATUS_CCPOL3_HIGHFALL (_TIMER_STATUS_CCPOL3_HIGHFALL << 27) /**< Shifted mode HIGHFALL for TIMER_STATUS */ /* Bit fields for TIMER IF */ #define _TIMER_IF_RESETVALUE 0x00000000UL /**< Default value for TIMER_IF */ #define _TIMER_IF_MASK 0x00000FF7UL /**< Mask for TIMER_IF */ #define TIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ #define _TIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ #define _TIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ #define _TIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ #define TIMER_IF_OF_DEFAULT (_TIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_IF */ #define TIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ #define _TIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ #define _TIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ #define _TIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ #define TIMER_IF_UF_DEFAULT (_TIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_IF */ #define TIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ #define _TIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ #define _TIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ #define _TIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ #define TIMER_IF_DIRCHG_DEFAULT (_TIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_IF */ #define TIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */ #define _TIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ #define _TIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ #define _TIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ #define TIMER_IF_CC0_DEFAULT (_TIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_IF */ #define TIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */ #define _TIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ #define _TIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ #define _TIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ #define TIMER_IF_CC1_DEFAULT (_TIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_IF */ #define TIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */ #define _TIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ #define _TIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ #define _TIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ #define TIMER_IF_CC2_DEFAULT (_TIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_IF */ #define TIMER_IF_CC3 (0x1UL << 7) /**< CC Channel 3 Interrupt Flag */ #define _TIMER_IF_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ #define _TIMER_IF_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ #define _TIMER_IF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ #define TIMER_IF_CC3_DEFAULT (_TIMER_IF_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for TIMER_IF */ #define TIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */ #define _TIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ #define _TIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ #define _TIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ #define TIMER_IF_ICBOF0_DEFAULT (_TIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_IF */ #define TIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */ #define _TIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ #define _TIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ #define _TIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ #define TIMER_IF_ICBOF1_DEFAULT (_TIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_IF */ #define TIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */ #define _TIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ #define _TIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ #define _TIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ #define TIMER_IF_ICBOF2_DEFAULT (_TIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_IF */ #define TIMER_IF_ICBOF3 (0x1UL << 11) /**< CC Channel 3 Input Capture Buffer Overflow Interrupt Flag */ #define _TIMER_IF_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ #define _TIMER_IF_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ #define _TIMER_IF_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ #define TIMER_IF_ICBOF3_DEFAULT (_TIMER_IF_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for TIMER_IF */ /* Bit fields for TIMER IFS */ #define _TIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for TIMER_IFS */ #define _TIMER_IFS_MASK 0x00000FF7UL /**< Mask for TIMER_IFS */ #define TIMER_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */ #define _TIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */ #define _TIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ #define _TIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */ #define TIMER_IFS_OF_DEFAULT (_TIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_IFS */ #define TIMER_IFS_UF (0x1UL << 1) /**< Set UF Interrupt Flag */ #define _TIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */ #define _TIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ #define _TIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */ #define TIMER_IFS_UF_DEFAULT (_TIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_IFS */ #define TIMER_IFS_DIRCHG (0x1UL << 2) /**< Set DIRCHG Interrupt Flag */ #define _TIMER_IFS_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ #define _TIMER_IFS_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ #define _TIMER_IFS_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */ #define TIMER_IFS_DIRCHG_DEFAULT (_TIMER_IFS_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_IFS */ #define TIMER_IFS_CC0 (0x1UL << 4) /**< Set CC0 Interrupt Flag */ #define _TIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ #define _TIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ #define _TIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */ #define TIMER_IFS_CC0_DEFAULT (_TIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_IFS */ #define TIMER_IFS_CC1 (0x1UL << 5) /**< Set CC1 Interrupt Flag */ #define _TIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ #define _TIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ #define _TIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */ #define TIMER_IFS_CC1_DEFAULT (_TIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_IFS */ #define TIMER_IFS_CC2 (0x1UL << 6) /**< Set CC2 Interrupt Flag */ #define _TIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ #define _TIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ #define _TIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */ #define TIMER_IFS_CC2_DEFAULT (_TIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_IFS */ #define TIMER_IFS_CC3 (0x1UL << 7) /**< Set CC3 Interrupt Flag */ #define _TIMER_IFS_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ #define _TIMER_IFS_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ #define _TIMER_IFS_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */ #define TIMER_IFS_CC3_DEFAULT (_TIMER_IFS_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for TIMER_IFS */ #define TIMER_IFS_ICBOF0 (0x1UL << 8) /**< Set ICBOF0 Interrupt Flag */ #define _TIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ #define _TIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ #define _TIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */ #define TIMER_IFS_ICBOF0_DEFAULT (_TIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_IFS */ #define TIMER_IFS_ICBOF1 (0x1UL << 9) /**< Set ICBOF1 Interrupt Flag */ #define _TIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ #define _TIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ #define _TIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */ #define TIMER_IFS_ICBOF1_DEFAULT (_TIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_IFS */ #define TIMER_IFS_ICBOF2 (0x1UL << 10) /**< Set ICBOF2 Interrupt Flag */ #define _TIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ #define _TIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ #define _TIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */ #define TIMER_IFS_ICBOF2_DEFAULT (_TIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_IFS */ #define TIMER_IFS_ICBOF3 (0x1UL << 11) /**< Set ICBOF3 Interrupt Flag */ #define _TIMER_IFS_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ #define _TIMER_IFS_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ #define _TIMER_IFS_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */ #define TIMER_IFS_ICBOF3_DEFAULT (_TIMER_IFS_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for TIMER_IFS */ /* Bit fields for TIMER IFC */ #define _TIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for TIMER_IFC */ #define _TIMER_IFC_MASK 0x00000FF7UL /**< Mask for TIMER_IFC */ #define TIMER_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */ #define _TIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */ #define _TIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ #define _TIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */ #define TIMER_IFC_OF_DEFAULT (_TIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_IFC */ #define TIMER_IFC_UF (0x1UL << 1) /**< Clear UF Interrupt Flag */ #define _TIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */ #define _TIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ #define _TIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */ #define TIMER_IFC_UF_DEFAULT (_TIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_IFC */ #define TIMER_IFC_DIRCHG (0x1UL << 2) /**< Clear DIRCHG Interrupt Flag */ #define _TIMER_IFC_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ #define _TIMER_IFC_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ #define _TIMER_IFC_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */ #define TIMER_IFC_DIRCHG_DEFAULT (_TIMER_IFC_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_IFC */ #define TIMER_IFC_CC0 (0x1UL << 4) /**< Clear CC0 Interrupt Flag */ #define _TIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ #define _TIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ #define _TIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */ #define TIMER_IFC_CC0_DEFAULT (_TIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_IFC */ #define TIMER_IFC_CC1 (0x1UL << 5) /**< Clear CC1 Interrupt Flag */ #define _TIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ #define _TIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ #define _TIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */ #define TIMER_IFC_CC1_DEFAULT (_TIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_IFC */ #define TIMER_IFC_CC2 (0x1UL << 6) /**< Clear CC2 Interrupt Flag */ #define _TIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ #define _TIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ #define _TIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */ #define TIMER_IFC_CC2_DEFAULT (_TIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_IFC */ #define TIMER_IFC_CC3 (0x1UL << 7) /**< Clear CC3 Interrupt Flag */ #define _TIMER_IFC_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ #define _TIMER_IFC_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ #define _TIMER_IFC_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */ #define TIMER_IFC_CC3_DEFAULT (_TIMER_IFC_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for TIMER_IFC */ #define TIMER_IFC_ICBOF0 (0x1UL << 8) /**< Clear ICBOF0 Interrupt Flag */ #define _TIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ #define _TIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ #define _TIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */ #define TIMER_IFC_ICBOF0_DEFAULT (_TIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_IFC */ #define TIMER_IFC_ICBOF1 (0x1UL << 9) /**< Clear ICBOF1 Interrupt Flag */ #define _TIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ #define _TIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ #define _TIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */ #define TIMER_IFC_ICBOF1_DEFAULT (_TIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_IFC */ #define TIMER_IFC_ICBOF2 (0x1UL << 10) /**< Clear ICBOF2 Interrupt Flag */ #define _TIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ #define _TIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ #define _TIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */ #define TIMER_IFC_ICBOF2_DEFAULT (_TIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_IFC */ #define TIMER_IFC_ICBOF3 (0x1UL << 11) /**< Clear ICBOF3 Interrupt Flag */ #define _TIMER_IFC_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ #define _TIMER_IFC_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ #define _TIMER_IFC_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */ #define TIMER_IFC_ICBOF3_DEFAULT (_TIMER_IFC_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for TIMER_IFC */ /* Bit fields for TIMER IEN */ #define _TIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for TIMER_IEN */ #define _TIMER_IEN_MASK 0x00000FF7UL /**< Mask for TIMER_IEN */ #define TIMER_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ #define _TIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ #define _TIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ #define _TIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ #define TIMER_IEN_OF_DEFAULT (_TIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_IEN */ #define TIMER_IEN_UF (0x1UL << 1) /**< UF Interrupt Enable */ #define _TIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ #define _TIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ #define _TIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ #define TIMER_IEN_UF_DEFAULT (_TIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_IEN */ #define TIMER_IEN_DIRCHG (0x1UL << 2) /**< DIRCHG Interrupt Enable */ #define _TIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ #define _TIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ #define _TIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ #define TIMER_IEN_DIRCHG_DEFAULT (_TIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_IEN */ #define TIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ #define _TIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ #define _TIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ #define _TIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ #define TIMER_IEN_CC0_DEFAULT (_TIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_IEN */ #define TIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ #define _TIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ #define _TIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ #define _TIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ #define TIMER_IEN_CC1_DEFAULT (_TIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_IEN */ #define TIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ #define _TIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ #define _TIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ #define _TIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ #define TIMER_IEN_CC2_DEFAULT (_TIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_IEN */ #define TIMER_IEN_CC3 (0x1UL << 7) /**< CC3 Interrupt Enable */ #define _TIMER_IEN_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ #define _TIMER_IEN_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ #define _TIMER_IEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ #define TIMER_IEN_CC3_DEFAULT (_TIMER_IEN_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for TIMER_IEN */ #define TIMER_IEN_ICBOF0 (0x1UL << 8) /**< ICBOF0 Interrupt Enable */ #define _TIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ #define _TIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ #define _TIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ #define TIMER_IEN_ICBOF0_DEFAULT (_TIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_IEN */ #define TIMER_IEN_ICBOF1 (0x1UL << 9) /**< ICBOF1 Interrupt Enable */ #define _TIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ #define _TIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ #define _TIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ #define TIMER_IEN_ICBOF1_DEFAULT (_TIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_IEN */ #define TIMER_IEN_ICBOF2 (0x1UL << 10) /**< ICBOF2 Interrupt Enable */ #define _TIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ #define _TIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ #define _TIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ #define TIMER_IEN_ICBOF2_DEFAULT (_TIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_IEN */ #define TIMER_IEN_ICBOF3 (0x1UL << 11) /**< ICBOF3 Interrupt Enable */ #define _TIMER_IEN_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ #define _TIMER_IEN_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ #define _TIMER_IEN_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ #define TIMER_IEN_ICBOF3_DEFAULT (_TIMER_IEN_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for TIMER_IEN */ /* Bit fields for TIMER TOP */ #define _TIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for TIMER_TOP */ #define _TIMER_TOP_MASK 0x0000FFFFUL /**< Mask for TIMER_TOP */ #define _TIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ #define _TIMER_TOP_TOP_MASK 0xFFFFUL /**< Bit mask for TIMER_TOP */ #define _TIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for TIMER_TOP */ #define TIMER_TOP_TOP_DEFAULT (_TIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_TOP */ /* Bit fields for TIMER TOPB */ #define _TIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for TIMER_TOPB */ #define _TIMER_TOPB_MASK 0x0000FFFFUL /**< Mask for TIMER_TOPB */ #define _TIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ #define _TIMER_TOPB_TOPB_MASK 0xFFFFUL /**< Bit mask for TIMER_TOPB */ #define _TIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_TOPB */ #define TIMER_TOPB_TOPB_DEFAULT (_TIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_TOPB */ /* Bit fields for TIMER CNT */ #define _TIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for TIMER_CNT */ #define _TIMER_CNT_MASK 0x0000FFFFUL /**< Mask for TIMER_CNT */ #define _TIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ #define _TIMER_CNT_CNT_MASK 0xFFFFUL /**< Bit mask for TIMER_CNT */ #define _TIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CNT */ #define TIMER_CNT_CNT_DEFAULT (_TIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CNT */ /* Bit fields for TIMER LOCK */ #define _TIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for TIMER_LOCK */ #define _TIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for TIMER_LOCK */ #define _TIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */ #define _TIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */ #define _TIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_LOCK */ #define _TIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for TIMER_LOCK */ #define _TIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for TIMER_LOCK */ #define _TIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for TIMER_LOCK */ #define _TIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for TIMER_LOCK */ #define TIMER_LOCK_TIMERLOCKKEY_DEFAULT (_TIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_LOCK */ #define TIMER_LOCK_TIMERLOCKKEY_LOCK (_TIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for TIMER_LOCK */ #define TIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_TIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for TIMER_LOCK */ #define TIMER_LOCK_TIMERLOCKKEY_LOCKED (_TIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for TIMER_LOCK */ #define TIMER_LOCK_TIMERLOCKKEY_UNLOCK (_TIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for TIMER_LOCK */ /* Bit fields for TIMER ROUTEPEN */ #define _TIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for TIMER_ROUTEPEN */ #define _TIMER_ROUTEPEN_MASK 0x0000070FUL /**< Mask for TIMER_ROUTEPEN */ #define TIMER_ROUTEPEN_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */ #define _TIMER_ROUTEPEN_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */ #define _TIMER_ROUTEPEN_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */ #define _TIMER_ROUTEPEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTEPEN */ #define TIMER_ROUTEPEN_CC0PEN_DEFAULT (_TIMER_ROUTEPEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_ROUTEPEN */ #define TIMER_ROUTEPEN_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */ #define _TIMER_ROUTEPEN_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */ #define _TIMER_ROUTEPEN_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */ #define _TIMER_ROUTEPEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTEPEN */ #define TIMER_ROUTEPEN_CC1PEN_DEFAULT (_TIMER_ROUTEPEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_ROUTEPEN */ #define TIMER_ROUTEPEN_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */ #define _TIMER_ROUTEPEN_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */ #define _TIMER_ROUTEPEN_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */ #define _TIMER_ROUTEPEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTEPEN */ #define TIMER_ROUTEPEN_CC2PEN_DEFAULT (_TIMER_ROUTEPEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_ROUTEPEN */ #define TIMER_ROUTEPEN_CC3PEN (0x1UL << 3) /**< CC Channel 3 Pin Enable */ #define _TIMER_ROUTEPEN_CC3PEN_SHIFT 3 /**< Shift value for TIMER_CC3PEN */ #define _TIMER_ROUTEPEN_CC3PEN_MASK 0x8UL /**< Bit mask for TIMER_CC3PEN */ #define _TIMER_ROUTEPEN_CC3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTEPEN */ #define TIMER_ROUTEPEN_CC3PEN_DEFAULT (_TIMER_ROUTEPEN_CC3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_ROUTEPEN */ #define TIMER_ROUTEPEN_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */ #define _TIMER_ROUTEPEN_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */ #define _TIMER_ROUTEPEN_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */ #define _TIMER_ROUTEPEN_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTEPEN */ #define TIMER_ROUTEPEN_CDTI0PEN_DEFAULT (_TIMER_ROUTEPEN_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_ROUTEPEN */ #define TIMER_ROUTEPEN_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */ #define _TIMER_ROUTEPEN_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */ #define _TIMER_ROUTEPEN_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */ #define _TIMER_ROUTEPEN_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTEPEN */ #define TIMER_ROUTEPEN_CDTI1PEN_DEFAULT (_TIMER_ROUTEPEN_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_ROUTEPEN */ #define TIMER_ROUTEPEN_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */ #define _TIMER_ROUTEPEN_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */ #define _TIMER_ROUTEPEN_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */ #define _TIMER_ROUTEPEN_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTEPEN */ #define TIMER_ROUTEPEN_CDTI2PEN_DEFAULT (_TIMER_ROUTEPEN_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_ROUTEPEN */ /* Bit fields for TIMER ROUTELOC0 */ #define _TIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_MASK 0x1F1F1F1FUL /**< Mask for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC0LOC_SHIFT 0 /**< Shift value for TIMER_CC0LOC */ #define _TIMER_ROUTELOC0_CC0LOC_MASK 0x1FUL /**< Bit mask for TIMER_CC0LOC */ #define _TIMER_ROUTELOC0_CC0LOC_LOC0 0x00000000UL /**< Mode LOC0 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC0LOC_LOC1 0x00000001UL /**< Mode LOC1 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC0LOC_LOC2 0x00000002UL /**< Mode LOC2 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC0LOC_LOC3 0x00000003UL /**< Mode LOC3 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC0LOC_LOC4 0x00000004UL /**< Mode LOC4 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC0LOC_LOC5 0x00000005UL /**< Mode LOC5 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC0LOC_LOC6 0x00000006UL /**< Mode LOC6 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC0LOC_LOC7 0x00000007UL /**< Mode LOC7 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC0LOC_LOC8 0x00000008UL /**< Mode LOC8 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC0LOC_LOC9 0x00000009UL /**< Mode LOC9 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC0LOC_LOC10 0x0000000AUL /**< Mode LOC10 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC0LOC_LOC11 0x0000000BUL /**< Mode LOC11 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC0LOC_LOC12 0x0000000CUL /**< Mode LOC12 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC0LOC_LOC13 0x0000000DUL /**< Mode LOC13 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC0LOC_LOC14 0x0000000EUL /**< Mode LOC14 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC0LOC_LOC15 0x0000000FUL /**< Mode LOC15 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC0LOC_LOC16 0x00000010UL /**< Mode LOC16 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC0LOC_LOC17 0x00000011UL /**< Mode LOC17 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC0LOC_LOC18 0x00000012UL /**< Mode LOC18 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC0LOC_LOC19 0x00000013UL /**< Mode LOC19 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC0LOC_LOC20 0x00000014UL /**< Mode LOC20 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC0LOC_LOC21 0x00000015UL /**< Mode LOC21 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC0LOC_LOC22 0x00000016UL /**< Mode LOC22 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC0LOC_LOC23 0x00000017UL /**< Mode LOC23 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC0LOC_LOC24 0x00000018UL /**< Mode LOC24 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC0LOC_LOC25 0x00000019UL /**< Mode LOC25 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC0LOC_LOC26 0x0000001AUL /**< Mode LOC26 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC0LOC_LOC27 0x0000001BUL /**< Mode LOC27 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC0LOC_LOC28 0x0000001CUL /**< Mode LOC28 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC0LOC_LOC29 0x0000001DUL /**< Mode LOC29 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC0LOC_LOC30 0x0000001EUL /**< Mode LOC30 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC0LOC_LOC31 0x0000001FUL /**< Mode LOC31 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC0LOC_LOC0 (_TIMER_ROUTELOC0_CC0LOC_LOC0 << 0) /**< Shifted mode LOC0 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC0LOC_DEFAULT (_TIMER_ROUTELOC0_CC0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC0LOC_LOC1 (_TIMER_ROUTELOC0_CC0LOC_LOC1 << 0) /**< Shifted mode LOC1 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC0LOC_LOC2 (_TIMER_ROUTELOC0_CC0LOC_LOC2 << 0) /**< Shifted mode LOC2 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC0LOC_LOC3 (_TIMER_ROUTELOC0_CC0LOC_LOC3 << 0) /**< Shifted mode LOC3 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC0LOC_LOC4 (_TIMER_ROUTELOC0_CC0LOC_LOC4 << 0) /**< Shifted mode LOC4 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC0LOC_LOC5 (_TIMER_ROUTELOC0_CC0LOC_LOC5 << 0) /**< Shifted mode LOC5 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC0LOC_LOC6 (_TIMER_ROUTELOC0_CC0LOC_LOC6 << 0) /**< Shifted mode LOC6 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC0LOC_LOC7 (_TIMER_ROUTELOC0_CC0LOC_LOC7 << 0) /**< Shifted mode LOC7 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC0LOC_LOC8 (_TIMER_ROUTELOC0_CC0LOC_LOC8 << 0) /**< Shifted mode LOC8 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC0LOC_LOC9 (_TIMER_ROUTELOC0_CC0LOC_LOC9 << 0) /**< Shifted mode LOC9 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC0LOC_LOC10 (_TIMER_ROUTELOC0_CC0LOC_LOC10 << 0) /**< Shifted mode LOC10 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC0LOC_LOC11 (_TIMER_ROUTELOC0_CC0LOC_LOC11 << 0) /**< Shifted mode LOC11 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC0LOC_LOC12 (_TIMER_ROUTELOC0_CC0LOC_LOC12 << 0) /**< Shifted mode LOC12 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC0LOC_LOC13 (_TIMER_ROUTELOC0_CC0LOC_LOC13 << 0) /**< Shifted mode LOC13 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC0LOC_LOC14 (_TIMER_ROUTELOC0_CC0LOC_LOC14 << 0) /**< Shifted mode LOC14 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC0LOC_LOC15 (_TIMER_ROUTELOC0_CC0LOC_LOC15 << 0) /**< Shifted mode LOC15 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC0LOC_LOC16 (_TIMER_ROUTELOC0_CC0LOC_LOC16 << 0) /**< Shifted mode LOC16 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC0LOC_LOC17 (_TIMER_ROUTELOC0_CC0LOC_LOC17 << 0) /**< Shifted mode LOC17 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC0LOC_LOC18 (_TIMER_ROUTELOC0_CC0LOC_LOC18 << 0) /**< Shifted mode LOC18 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC0LOC_LOC19 (_TIMER_ROUTELOC0_CC0LOC_LOC19 << 0) /**< Shifted mode LOC19 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC0LOC_LOC20 (_TIMER_ROUTELOC0_CC0LOC_LOC20 << 0) /**< Shifted mode LOC20 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC0LOC_LOC21 (_TIMER_ROUTELOC0_CC0LOC_LOC21 << 0) /**< Shifted mode LOC21 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC0LOC_LOC22 (_TIMER_ROUTELOC0_CC0LOC_LOC22 << 0) /**< Shifted mode LOC22 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC0LOC_LOC23 (_TIMER_ROUTELOC0_CC0LOC_LOC23 << 0) /**< Shifted mode LOC23 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC0LOC_LOC24 (_TIMER_ROUTELOC0_CC0LOC_LOC24 << 0) /**< Shifted mode LOC24 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC0LOC_LOC25 (_TIMER_ROUTELOC0_CC0LOC_LOC25 << 0) /**< Shifted mode LOC25 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC0LOC_LOC26 (_TIMER_ROUTELOC0_CC0LOC_LOC26 << 0) /**< Shifted mode LOC26 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC0LOC_LOC27 (_TIMER_ROUTELOC0_CC0LOC_LOC27 << 0) /**< Shifted mode LOC27 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC0LOC_LOC28 (_TIMER_ROUTELOC0_CC0LOC_LOC28 << 0) /**< Shifted mode LOC28 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC0LOC_LOC29 (_TIMER_ROUTELOC0_CC0LOC_LOC29 << 0) /**< Shifted mode LOC29 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC0LOC_LOC30 (_TIMER_ROUTELOC0_CC0LOC_LOC30 << 0) /**< Shifted mode LOC30 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC0LOC_LOC31 (_TIMER_ROUTELOC0_CC0LOC_LOC31 << 0) /**< Shifted mode LOC31 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC1LOC_SHIFT 8 /**< Shift value for TIMER_CC1LOC */ #define _TIMER_ROUTELOC0_CC1LOC_MASK 0x1F00UL /**< Bit mask for TIMER_CC1LOC */ #define _TIMER_ROUTELOC0_CC1LOC_LOC0 0x00000000UL /**< Mode LOC0 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC1LOC_LOC1 0x00000001UL /**< Mode LOC1 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC1LOC_LOC2 0x00000002UL /**< Mode LOC2 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC1LOC_LOC3 0x00000003UL /**< Mode LOC3 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC1LOC_LOC4 0x00000004UL /**< Mode LOC4 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC1LOC_LOC5 0x00000005UL /**< Mode LOC5 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC1LOC_LOC6 0x00000006UL /**< Mode LOC6 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC1LOC_LOC7 0x00000007UL /**< Mode LOC7 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC1LOC_LOC8 0x00000008UL /**< Mode LOC8 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC1LOC_LOC9 0x00000009UL /**< Mode LOC9 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC1LOC_LOC10 0x0000000AUL /**< Mode LOC10 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC1LOC_LOC11 0x0000000BUL /**< Mode LOC11 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC1LOC_LOC12 0x0000000CUL /**< Mode LOC12 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC1LOC_LOC13 0x0000000DUL /**< Mode LOC13 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC1LOC_LOC14 0x0000000EUL /**< Mode LOC14 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC1LOC_LOC15 0x0000000FUL /**< Mode LOC15 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC1LOC_LOC16 0x00000010UL /**< Mode LOC16 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC1LOC_LOC17 0x00000011UL /**< Mode LOC17 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC1LOC_LOC18 0x00000012UL /**< Mode LOC18 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC1LOC_LOC19 0x00000013UL /**< Mode LOC19 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC1LOC_LOC20 0x00000014UL /**< Mode LOC20 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC1LOC_LOC21 0x00000015UL /**< Mode LOC21 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC1LOC_LOC22 0x00000016UL /**< Mode LOC22 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC1LOC_LOC23 0x00000017UL /**< Mode LOC23 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC1LOC_LOC24 0x00000018UL /**< Mode LOC24 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC1LOC_LOC25 0x00000019UL /**< Mode LOC25 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC1LOC_LOC26 0x0000001AUL /**< Mode LOC26 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC1LOC_LOC27 0x0000001BUL /**< Mode LOC27 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC1LOC_LOC28 0x0000001CUL /**< Mode LOC28 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC1LOC_LOC29 0x0000001DUL /**< Mode LOC29 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC1LOC_LOC30 0x0000001EUL /**< Mode LOC30 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC1LOC_LOC31 0x0000001FUL /**< Mode LOC31 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC1LOC_LOC0 (_TIMER_ROUTELOC0_CC1LOC_LOC0 << 8) /**< Shifted mode LOC0 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC1LOC_DEFAULT (_TIMER_ROUTELOC0_CC1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC1LOC_LOC1 (_TIMER_ROUTELOC0_CC1LOC_LOC1 << 8) /**< Shifted mode LOC1 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC1LOC_LOC2 (_TIMER_ROUTELOC0_CC1LOC_LOC2 << 8) /**< Shifted mode LOC2 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC1LOC_LOC3 (_TIMER_ROUTELOC0_CC1LOC_LOC3 << 8) /**< Shifted mode LOC3 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC1LOC_LOC4 (_TIMER_ROUTELOC0_CC1LOC_LOC4 << 8) /**< Shifted mode LOC4 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC1LOC_LOC5 (_TIMER_ROUTELOC0_CC1LOC_LOC5 << 8) /**< Shifted mode LOC5 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC1LOC_LOC6 (_TIMER_ROUTELOC0_CC1LOC_LOC6 << 8) /**< Shifted mode LOC6 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC1LOC_LOC7 (_TIMER_ROUTELOC0_CC1LOC_LOC7 << 8) /**< Shifted mode LOC7 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC1LOC_LOC8 (_TIMER_ROUTELOC0_CC1LOC_LOC8 << 8) /**< Shifted mode LOC8 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC1LOC_LOC9 (_TIMER_ROUTELOC0_CC1LOC_LOC9 << 8) /**< Shifted mode LOC9 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC1LOC_LOC10 (_TIMER_ROUTELOC0_CC1LOC_LOC10 << 8) /**< Shifted mode LOC10 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC1LOC_LOC11 (_TIMER_ROUTELOC0_CC1LOC_LOC11 << 8) /**< Shifted mode LOC11 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC1LOC_LOC12 (_TIMER_ROUTELOC0_CC1LOC_LOC12 << 8) /**< Shifted mode LOC12 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC1LOC_LOC13 (_TIMER_ROUTELOC0_CC1LOC_LOC13 << 8) /**< Shifted mode LOC13 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC1LOC_LOC14 (_TIMER_ROUTELOC0_CC1LOC_LOC14 << 8) /**< Shifted mode LOC14 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC1LOC_LOC15 (_TIMER_ROUTELOC0_CC1LOC_LOC15 << 8) /**< Shifted mode LOC15 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC1LOC_LOC16 (_TIMER_ROUTELOC0_CC1LOC_LOC16 << 8) /**< Shifted mode LOC16 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC1LOC_LOC17 (_TIMER_ROUTELOC0_CC1LOC_LOC17 << 8) /**< Shifted mode LOC17 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC1LOC_LOC18 (_TIMER_ROUTELOC0_CC1LOC_LOC18 << 8) /**< Shifted mode LOC18 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC1LOC_LOC19 (_TIMER_ROUTELOC0_CC1LOC_LOC19 << 8) /**< Shifted mode LOC19 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC1LOC_LOC20 (_TIMER_ROUTELOC0_CC1LOC_LOC20 << 8) /**< Shifted mode LOC20 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC1LOC_LOC21 (_TIMER_ROUTELOC0_CC1LOC_LOC21 << 8) /**< Shifted mode LOC21 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC1LOC_LOC22 (_TIMER_ROUTELOC0_CC1LOC_LOC22 << 8) /**< Shifted mode LOC22 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC1LOC_LOC23 (_TIMER_ROUTELOC0_CC1LOC_LOC23 << 8) /**< Shifted mode LOC23 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC1LOC_LOC24 (_TIMER_ROUTELOC0_CC1LOC_LOC24 << 8) /**< Shifted mode LOC24 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC1LOC_LOC25 (_TIMER_ROUTELOC0_CC1LOC_LOC25 << 8) /**< Shifted mode LOC25 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC1LOC_LOC26 (_TIMER_ROUTELOC0_CC1LOC_LOC26 << 8) /**< Shifted mode LOC26 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC1LOC_LOC27 (_TIMER_ROUTELOC0_CC1LOC_LOC27 << 8) /**< Shifted mode LOC27 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC1LOC_LOC28 (_TIMER_ROUTELOC0_CC1LOC_LOC28 << 8) /**< Shifted mode LOC28 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC1LOC_LOC29 (_TIMER_ROUTELOC0_CC1LOC_LOC29 << 8) /**< Shifted mode LOC29 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC1LOC_LOC30 (_TIMER_ROUTELOC0_CC1LOC_LOC30 << 8) /**< Shifted mode LOC30 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC1LOC_LOC31 (_TIMER_ROUTELOC0_CC1LOC_LOC31 << 8) /**< Shifted mode LOC31 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC2LOC_SHIFT 16 /**< Shift value for TIMER_CC2LOC */ #define _TIMER_ROUTELOC0_CC2LOC_MASK 0x1F0000UL /**< Bit mask for TIMER_CC2LOC */ #define _TIMER_ROUTELOC0_CC2LOC_LOC0 0x00000000UL /**< Mode LOC0 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC2LOC_LOC1 0x00000001UL /**< Mode LOC1 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC2LOC_LOC2 0x00000002UL /**< Mode LOC2 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC2LOC_LOC3 0x00000003UL /**< Mode LOC3 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC2LOC_LOC4 0x00000004UL /**< Mode LOC4 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC2LOC_LOC5 0x00000005UL /**< Mode LOC5 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC2LOC_LOC6 0x00000006UL /**< Mode LOC6 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC2LOC_LOC7 0x00000007UL /**< Mode LOC7 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC2LOC_LOC8 0x00000008UL /**< Mode LOC8 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC2LOC_LOC9 0x00000009UL /**< Mode LOC9 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC2LOC_LOC10 0x0000000AUL /**< Mode LOC10 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC2LOC_LOC11 0x0000000BUL /**< Mode LOC11 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC2LOC_LOC12 0x0000000CUL /**< Mode LOC12 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC2LOC_LOC13 0x0000000DUL /**< Mode LOC13 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC2LOC_LOC14 0x0000000EUL /**< Mode LOC14 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC2LOC_LOC15 0x0000000FUL /**< Mode LOC15 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC2LOC_LOC16 0x00000010UL /**< Mode LOC16 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC2LOC_LOC17 0x00000011UL /**< Mode LOC17 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC2LOC_LOC18 0x00000012UL /**< Mode LOC18 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC2LOC_LOC19 0x00000013UL /**< Mode LOC19 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC2LOC_LOC20 0x00000014UL /**< Mode LOC20 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC2LOC_LOC21 0x00000015UL /**< Mode LOC21 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC2LOC_LOC22 0x00000016UL /**< Mode LOC22 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC2LOC_LOC23 0x00000017UL /**< Mode LOC23 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC2LOC_LOC24 0x00000018UL /**< Mode LOC24 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC2LOC_LOC25 0x00000019UL /**< Mode LOC25 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC2LOC_LOC26 0x0000001AUL /**< Mode LOC26 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC2LOC_LOC27 0x0000001BUL /**< Mode LOC27 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC2LOC_LOC28 0x0000001CUL /**< Mode LOC28 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC2LOC_LOC29 0x0000001DUL /**< Mode LOC29 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC2LOC_LOC30 0x0000001EUL /**< Mode LOC30 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC2LOC_LOC31 0x0000001FUL /**< Mode LOC31 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC2LOC_LOC0 (_TIMER_ROUTELOC0_CC2LOC_LOC0 << 16) /**< Shifted mode LOC0 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC2LOC_DEFAULT (_TIMER_ROUTELOC0_CC2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC2LOC_LOC1 (_TIMER_ROUTELOC0_CC2LOC_LOC1 << 16) /**< Shifted mode LOC1 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC2LOC_LOC2 (_TIMER_ROUTELOC0_CC2LOC_LOC2 << 16) /**< Shifted mode LOC2 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC2LOC_LOC3 (_TIMER_ROUTELOC0_CC2LOC_LOC3 << 16) /**< Shifted mode LOC3 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC2LOC_LOC4 (_TIMER_ROUTELOC0_CC2LOC_LOC4 << 16) /**< Shifted mode LOC4 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC2LOC_LOC5 (_TIMER_ROUTELOC0_CC2LOC_LOC5 << 16) /**< Shifted mode LOC5 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC2LOC_LOC6 (_TIMER_ROUTELOC0_CC2LOC_LOC6 << 16) /**< Shifted mode LOC6 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC2LOC_LOC7 (_TIMER_ROUTELOC0_CC2LOC_LOC7 << 16) /**< Shifted mode LOC7 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC2LOC_LOC8 (_TIMER_ROUTELOC0_CC2LOC_LOC8 << 16) /**< Shifted mode LOC8 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC2LOC_LOC9 (_TIMER_ROUTELOC0_CC2LOC_LOC9 << 16) /**< Shifted mode LOC9 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC2LOC_LOC10 (_TIMER_ROUTELOC0_CC2LOC_LOC10 << 16) /**< Shifted mode LOC10 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC2LOC_LOC11 (_TIMER_ROUTELOC0_CC2LOC_LOC11 << 16) /**< Shifted mode LOC11 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC2LOC_LOC12 (_TIMER_ROUTELOC0_CC2LOC_LOC12 << 16) /**< Shifted mode LOC12 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC2LOC_LOC13 (_TIMER_ROUTELOC0_CC2LOC_LOC13 << 16) /**< Shifted mode LOC13 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC2LOC_LOC14 (_TIMER_ROUTELOC0_CC2LOC_LOC14 << 16) /**< Shifted mode LOC14 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC2LOC_LOC15 (_TIMER_ROUTELOC0_CC2LOC_LOC15 << 16) /**< Shifted mode LOC15 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC2LOC_LOC16 (_TIMER_ROUTELOC0_CC2LOC_LOC16 << 16) /**< Shifted mode LOC16 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC2LOC_LOC17 (_TIMER_ROUTELOC0_CC2LOC_LOC17 << 16) /**< Shifted mode LOC17 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC2LOC_LOC18 (_TIMER_ROUTELOC0_CC2LOC_LOC18 << 16) /**< Shifted mode LOC18 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC2LOC_LOC19 (_TIMER_ROUTELOC0_CC2LOC_LOC19 << 16) /**< Shifted mode LOC19 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC2LOC_LOC20 (_TIMER_ROUTELOC0_CC2LOC_LOC20 << 16) /**< Shifted mode LOC20 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC2LOC_LOC21 (_TIMER_ROUTELOC0_CC2LOC_LOC21 << 16) /**< Shifted mode LOC21 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC2LOC_LOC22 (_TIMER_ROUTELOC0_CC2LOC_LOC22 << 16) /**< Shifted mode LOC22 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC2LOC_LOC23 (_TIMER_ROUTELOC0_CC2LOC_LOC23 << 16) /**< Shifted mode LOC23 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC2LOC_LOC24 (_TIMER_ROUTELOC0_CC2LOC_LOC24 << 16) /**< Shifted mode LOC24 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC2LOC_LOC25 (_TIMER_ROUTELOC0_CC2LOC_LOC25 << 16) /**< Shifted mode LOC25 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC2LOC_LOC26 (_TIMER_ROUTELOC0_CC2LOC_LOC26 << 16) /**< Shifted mode LOC26 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC2LOC_LOC27 (_TIMER_ROUTELOC0_CC2LOC_LOC27 << 16) /**< Shifted mode LOC27 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC2LOC_LOC28 (_TIMER_ROUTELOC0_CC2LOC_LOC28 << 16) /**< Shifted mode LOC28 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC2LOC_LOC29 (_TIMER_ROUTELOC0_CC2LOC_LOC29 << 16) /**< Shifted mode LOC29 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC2LOC_LOC30 (_TIMER_ROUTELOC0_CC2LOC_LOC30 << 16) /**< Shifted mode LOC30 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC2LOC_LOC31 (_TIMER_ROUTELOC0_CC2LOC_LOC31 << 16) /**< Shifted mode LOC31 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC3LOC_SHIFT 24 /**< Shift value for TIMER_CC3LOC */ #define _TIMER_ROUTELOC0_CC3LOC_MASK 0x1F000000UL /**< Bit mask for TIMER_CC3LOC */ #define _TIMER_ROUTELOC0_CC3LOC_LOC0 0x00000000UL /**< Mode LOC0 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC3LOC_LOC1 0x00000001UL /**< Mode LOC1 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC3LOC_LOC2 0x00000002UL /**< Mode LOC2 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC3LOC_LOC3 0x00000003UL /**< Mode LOC3 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC3LOC_LOC4 0x00000004UL /**< Mode LOC4 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC3LOC_LOC5 0x00000005UL /**< Mode LOC5 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC3LOC_LOC6 0x00000006UL /**< Mode LOC6 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC3LOC_LOC7 0x00000007UL /**< Mode LOC7 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC3LOC_LOC8 0x00000008UL /**< Mode LOC8 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC3LOC_LOC9 0x00000009UL /**< Mode LOC9 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC3LOC_LOC10 0x0000000AUL /**< Mode LOC10 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC3LOC_LOC11 0x0000000BUL /**< Mode LOC11 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC3LOC_LOC12 0x0000000CUL /**< Mode LOC12 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC3LOC_LOC13 0x0000000DUL /**< Mode LOC13 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC3LOC_LOC14 0x0000000EUL /**< Mode LOC14 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC3LOC_LOC15 0x0000000FUL /**< Mode LOC15 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC3LOC_LOC16 0x00000010UL /**< Mode LOC16 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC3LOC_LOC17 0x00000011UL /**< Mode LOC17 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC3LOC_LOC18 0x00000012UL /**< Mode LOC18 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC3LOC_LOC19 0x00000013UL /**< Mode LOC19 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC3LOC_LOC20 0x00000014UL /**< Mode LOC20 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC3LOC_LOC21 0x00000015UL /**< Mode LOC21 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC3LOC_LOC22 0x00000016UL /**< Mode LOC22 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC3LOC_LOC23 0x00000017UL /**< Mode LOC23 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC3LOC_LOC24 0x00000018UL /**< Mode LOC24 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC3LOC_LOC25 0x00000019UL /**< Mode LOC25 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC3LOC_LOC26 0x0000001AUL /**< Mode LOC26 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC3LOC_LOC27 0x0000001BUL /**< Mode LOC27 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC3LOC_LOC28 0x0000001CUL /**< Mode LOC28 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC3LOC_LOC29 0x0000001DUL /**< Mode LOC29 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC3LOC_LOC30 0x0000001EUL /**< Mode LOC30 for TIMER_ROUTELOC0 */ #define _TIMER_ROUTELOC0_CC3LOC_LOC31 0x0000001FUL /**< Mode LOC31 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC3LOC_LOC0 (_TIMER_ROUTELOC0_CC3LOC_LOC0 << 24) /**< Shifted mode LOC0 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC3LOC_DEFAULT (_TIMER_ROUTELOC0_CC3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC3LOC_LOC1 (_TIMER_ROUTELOC0_CC3LOC_LOC1 << 24) /**< Shifted mode LOC1 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC3LOC_LOC2 (_TIMER_ROUTELOC0_CC3LOC_LOC2 << 24) /**< Shifted mode LOC2 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC3LOC_LOC3 (_TIMER_ROUTELOC0_CC3LOC_LOC3 << 24) /**< Shifted mode LOC3 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC3LOC_LOC4 (_TIMER_ROUTELOC0_CC3LOC_LOC4 << 24) /**< Shifted mode LOC4 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC3LOC_LOC5 (_TIMER_ROUTELOC0_CC3LOC_LOC5 << 24) /**< Shifted mode LOC5 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC3LOC_LOC6 (_TIMER_ROUTELOC0_CC3LOC_LOC6 << 24) /**< Shifted mode LOC6 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC3LOC_LOC7 (_TIMER_ROUTELOC0_CC3LOC_LOC7 << 24) /**< Shifted mode LOC7 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC3LOC_LOC8 (_TIMER_ROUTELOC0_CC3LOC_LOC8 << 24) /**< Shifted mode LOC8 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC3LOC_LOC9 (_TIMER_ROUTELOC0_CC3LOC_LOC9 << 24) /**< Shifted mode LOC9 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC3LOC_LOC10 (_TIMER_ROUTELOC0_CC3LOC_LOC10 << 24) /**< Shifted mode LOC10 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC3LOC_LOC11 (_TIMER_ROUTELOC0_CC3LOC_LOC11 << 24) /**< Shifted mode LOC11 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC3LOC_LOC12 (_TIMER_ROUTELOC0_CC3LOC_LOC12 << 24) /**< Shifted mode LOC12 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC3LOC_LOC13 (_TIMER_ROUTELOC0_CC3LOC_LOC13 << 24) /**< Shifted mode LOC13 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC3LOC_LOC14 (_TIMER_ROUTELOC0_CC3LOC_LOC14 << 24) /**< Shifted mode LOC14 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC3LOC_LOC15 (_TIMER_ROUTELOC0_CC3LOC_LOC15 << 24) /**< Shifted mode LOC15 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC3LOC_LOC16 (_TIMER_ROUTELOC0_CC3LOC_LOC16 << 24) /**< Shifted mode LOC16 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC3LOC_LOC17 (_TIMER_ROUTELOC0_CC3LOC_LOC17 << 24) /**< Shifted mode LOC17 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC3LOC_LOC18 (_TIMER_ROUTELOC0_CC3LOC_LOC18 << 24) /**< Shifted mode LOC18 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC3LOC_LOC19 (_TIMER_ROUTELOC0_CC3LOC_LOC19 << 24) /**< Shifted mode LOC19 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC3LOC_LOC20 (_TIMER_ROUTELOC0_CC3LOC_LOC20 << 24) /**< Shifted mode LOC20 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC3LOC_LOC21 (_TIMER_ROUTELOC0_CC3LOC_LOC21 << 24) /**< Shifted mode LOC21 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC3LOC_LOC22 (_TIMER_ROUTELOC0_CC3LOC_LOC22 << 24) /**< Shifted mode LOC22 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC3LOC_LOC23 (_TIMER_ROUTELOC0_CC3LOC_LOC23 << 24) /**< Shifted mode LOC23 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC3LOC_LOC24 (_TIMER_ROUTELOC0_CC3LOC_LOC24 << 24) /**< Shifted mode LOC24 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC3LOC_LOC25 (_TIMER_ROUTELOC0_CC3LOC_LOC25 << 24) /**< Shifted mode LOC25 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC3LOC_LOC26 (_TIMER_ROUTELOC0_CC3LOC_LOC26 << 24) /**< Shifted mode LOC26 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC3LOC_LOC27 (_TIMER_ROUTELOC0_CC3LOC_LOC27 << 24) /**< Shifted mode LOC27 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC3LOC_LOC28 (_TIMER_ROUTELOC0_CC3LOC_LOC28 << 24) /**< Shifted mode LOC28 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC3LOC_LOC29 (_TIMER_ROUTELOC0_CC3LOC_LOC29 << 24) /**< Shifted mode LOC29 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC3LOC_LOC30 (_TIMER_ROUTELOC0_CC3LOC_LOC30 << 24) /**< Shifted mode LOC30 for TIMER_ROUTELOC0 */ #define TIMER_ROUTELOC0_CC3LOC_LOC31 (_TIMER_ROUTELOC0_CC3LOC_LOC31 << 24) /**< Shifted mode LOC31 for TIMER_ROUTELOC0 */ /* Bit fields for TIMER ROUTELOC2 */ #define _TIMER_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for TIMER_ROUTELOC2 */ #define _TIMER_ROUTELOC2_MASK 0x001F1F1FUL /**< Mask for TIMER_ROUTELOC2 */ #define _TIMER_ROUTELOC2_CDTI0LOC_SHIFT 0 /**< Shift value for TIMER_CDTI0LOC */ #define _TIMER_ROUTELOC2_CDTI0LOC_MASK 0x1FUL /**< Bit mask for TIMER_CDTI0LOC */ #define _TIMER_ROUTELOC2_CDTI0LOC_LOC0 0x00000000UL /**< Mode LOC0 for TIMER_ROUTELOC2 */ #define _TIMER_ROUTELOC2_CDTI0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTELOC2 */ #define _TIMER_ROUTELOC2_CDTI0LOC_LOC1 0x00000001UL /**< Mode LOC1 for TIMER_ROUTELOC2 */ #define _TIMER_ROUTELOC2_CDTI0LOC_LOC2 0x00000002UL /**< Mode LOC2 for TIMER_ROUTELOC2 */ #define _TIMER_ROUTELOC2_CDTI0LOC_LOC3 0x00000003UL /**< Mode LOC3 for TIMER_ROUTELOC2 */ #define _TIMER_ROUTELOC2_CDTI0LOC_LOC4 0x00000004UL /**< Mode LOC4 for TIMER_ROUTELOC2 */ #define _TIMER_ROUTELOC2_CDTI0LOC_LOC5 0x00000005UL /**< Mode LOC5 for TIMER_ROUTELOC2 */ #define _TIMER_ROUTELOC2_CDTI0LOC_LOC6 0x00000006UL /**< Mode LOC6 for TIMER_ROUTELOC2 */ #define _TIMER_ROUTELOC2_CDTI0LOC_LOC7 0x00000007UL /**< Mode LOC7 for TIMER_ROUTELOC2 */ #define _TIMER_ROUTELOC2_CDTI0LOC_LOC8 0x00000008UL /**< Mode LOC8 for TIMER_ROUTELOC2 */ #define _TIMER_ROUTELOC2_CDTI0LOC_LOC9 0x00000009UL /**< Mode LOC9 for TIMER_ROUTELOC2 */ #define _TIMER_ROUTELOC2_CDTI0LOC_LOC10 0x0000000AUL /**< Mode LOC10 for TIMER_ROUTELOC2 */ #define _TIMER_ROUTELOC2_CDTI0LOC_LOC11 0x0000000BUL /**< Mode LOC11 for TIMER_ROUTELOC2 */ #define _TIMER_ROUTELOC2_CDTI0LOC_LOC12 0x0000000CUL /**< Mode LOC12 for TIMER_ROUTELOC2 */ #define _TIMER_ROUTELOC2_CDTI0LOC_LOC13 0x0000000DUL /**< Mode LOC13 for TIMER_ROUTELOC2 */ #define _TIMER_ROUTELOC2_CDTI0LOC_LOC14 0x0000000EUL /**< Mode LOC14 for TIMER_ROUTELOC2 */ #define _TIMER_ROUTELOC2_CDTI0LOC_LOC15 0x0000000FUL /**< Mode LOC15 for TIMER_ROUTELOC2 */ #define _TIMER_ROUTELOC2_CDTI0LOC_LOC16 0x00000010UL /**< Mode LOC16 for TIMER_ROUTELOC2 */ #define _TIMER_ROUTELOC2_CDTI0LOC_LOC17 0x00000011UL /**< Mode LOC17 for TIMER_ROUTELOC2 */ #define _TIMER_ROUTELOC2_CDTI0LOC_LOC18 0x00000012UL /**< Mode LOC18 for TIMER_ROUTELOC2 */ #define _TIMER_ROUTELOC2_CDTI0LOC_LOC19 0x00000013UL /**< Mode LOC19 for TIMER_ROUTELOC2 */ #define _TIMER_ROUTELOC2_CDTI0LOC_LOC20 0x00000014UL /**< Mode LOC20 for TIMER_ROUTELOC2 */ #define _TIMER_ROUTELOC2_CDTI0LOC_LOC21 0x00000015UL /**< Mode LOC21 for TIMER_ROUTELOC2 */ #define _TIMER_ROUTELOC2_CDTI0LOC_LOC22 0x00000016UL /**< Mode LOC22 for TIMER_ROUTELOC2 */ #define _TIMER_ROUTELOC2_CDTI0LOC_LOC23 0x00000017UL /**< Mode LOC23 for TIMER_ROUTELOC2 */ #define _TIMER_ROUTELOC2_CDTI0LOC_LOC24 0x00000018UL /**< Mode LOC24 for TIMER_ROUTELOC2 */ #define _TIMER_ROUTELOC2_CDTI0LOC_LOC25 0x00000019UL /**< Mode LOC25 for TIMER_ROUTELOC2 */ #define _TIMER_ROUTELOC2_CDTI0LOC_LOC26 0x0000001AUL /**< Mode LOC26 for TIMER_ROUTELOC2 */ #define _TIMER_ROUTELOC2_CDTI0LOC_LOC27 0x0000001BUL /**< Mode LOC27 for TIMER_ROUTELOC2 */ #define _TIMER_ROUTELOC2_CDTI0LOC_LOC28 0x0000001CUL /**< Mode LOC28 for TIMER_ROUTELOC2 */ #define _TIMER_ROUTELOC2_CDTI0LOC_LOC29 0x0000001DUL /**< Mode LOC29 for TIMER_ROUTELOC2 */ #define _TIMER_ROUTELOC2_CDTI0LOC_LOC30 0x0000001EUL /**< Mode LOC30 for TIMER_ROUTELOC2 */ #define _TIMER_ROUTELOC2_CDTI0LOC_LOC31 0x0000001FUL /**< Mode LOC31 for TIMER_ROUTELOC2 */ #define TIMER_ROUTELOC2_CDTI0LOC_LOC0 (_TIMER_ROUTELOC2_CDTI0LOC_LOC0 << 0) /**< Shifted mode LOC0 for TIMER_ROUTELOC2 */ #define TIMER_ROUTELOC2_CDTI0LOC_DEFAULT (_TIMER_ROUTELOC2_CDTI0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_ROUTELOC2 */ #define TIMER_ROUTELOC2_CDTI0LOC_LOC1 (_TIMER_ROUTELOC2_CDTI0LOC_LOC1 << 0) /**< Shifted mode LOC1 for TIMER_ROUTELOC2 */ #define TIMER_ROUTELOC2_CDTI0LOC_LOC2 (_TIMER_ROUTELOC2_CDTI0LOC_LOC2 << 0) /**< Shifted mode LOC2 for TIMER_ROUTELOC2 */ #define TIMER_ROUTELOC2_CDTI0LOC_LOC3 (_TIMER_ROUTELOC2_CDTI0LOC_LOC3 << 0) /**< Shifted mode LOC3 for TIMER_ROUTELOC2 */ #define TIMER_ROUTELOC2_CDTI0LOC_LOC4 (_TIMER_ROUTELOC2_CDTI0LOC_LOC4 << 0) /**< Shifted mode LOC4 for TIMER_ROUTELOC2 */ #define TIMER_ROUTELOC2_CDTI0LOC_LOC5 (_TIMER_ROUTELOC2_CDTI0LOC_LOC5 << 0) /**< Shifted mode LOC5 for TIMER_ROUTELOC2 */ #define TIMER_ROUTELOC2_CDTI0LOC_LOC6 (_TIMER_ROUTELOC2_CDTI0LOC_LOC6 << 0) /**< Shifted mode LOC6 for TIMER_ROUTELOC2 */ #define TIMER_ROUTELOC2_CDTI0LOC_LOC7 (_TIMER_ROUTELOC2_CDTI0LOC_LOC7 << 0) /**< Shifted mode LOC7 for TIMER_ROUTELOC2 */ #define TIMER_ROUTELOC2_CDTI0LOC_LOC8 (_TIMER_ROUTELOC2_CDTI0LOC_LOC8 << 0) /**< Shifted mode LOC8 for TIMER_ROUTELOC2 */ #define TIMER_ROUTELOC2_CDTI0LOC_LOC9 (_TIMER_ROUTELOC2_CDTI0LOC_LOC9 << 0) /**< Shifted mode LOC9 for TIMER_ROUTELOC2 */ #define TIMER_ROUTELOC2_CDTI0LOC_LOC10 (_TIMER_ROUTELOC2_CDTI0LOC_LOC10 << 0) /**< Shifted mode LOC10 for TIMER_ROUTELOC2 */ #define TIMER_ROUTELOC2_CDTI0LOC_LOC11 (_TIMER_ROUTELOC2_CDTI0LOC_LOC11 << 0) /**< Shifted mode LOC11 for TIMER_ROUTELOC2 */ #define TIMER_ROUTELOC2_CDTI0LOC_LOC12 (_TIMER_ROUTELOC2_CDTI0LOC_LOC12 << 0) /**< Shifted mode LOC12 for TIMER_ROUTELOC2 */ #define TIMER_ROUTELOC2_CDTI0LOC_LOC13 (_TIMER_ROUTELOC2_CDTI0LOC_LOC13 << 0) /**< Shifted mode LOC13 for TIMER_ROUTELOC2 */ #define TIMER_ROUTELOC2_CDTI0LOC_LOC14 (_TIMER_ROUTELOC2_CDTI0LOC_LOC14 << 0) /**< Shifted mode LOC14 for TIMER_ROUTELOC2 */ #define TIMER_ROUTELOC2_CDTI0LOC_LOC15 (_TIMER_ROUTELOC2_CDTI0LOC_LOC15 << 0) /**< Shifted mode LOC15 for TIMER_ROUTELOC2 */ #define TIMER_ROUTELOC2_CDTI0LOC_LOC16 (_TIMER_ROUTELOC2_CDTI0LOC_LOC16 << 0) /**< Shifted mode LOC16 for TIMER_ROUTELOC2 */ #define TIMER_ROUTELOC2_CDTI0LOC_LOC17 (_TIMER_ROUTELOC2_CDTI0LOC_LOC17 << 0) /**< Shifted mode LOC17 for TIMER_ROUTELOC2 */ #define TIMER_ROUTELOC2_CDTI0LOC_LOC18 (_TIMER_ROUTELOC2_CDTI0LOC_LOC18 << 0) /**< Shifted mode LOC18 for TIMER_ROUTELOC2 */ #define TIMER_ROUTELOC2_CDTI0LOC_LOC19 (_TIMER_ROUTELOC2_CDTI0LOC_LOC19 << 0) /**< Shifted mode LOC19 for TIMER_ROUTELOC2 */ #define TIMER_ROUTELOC2_CDTI0LOC_LOC20 (_TIMER_ROUTELOC2_CDTI0LOC_LOC20 << 0) /**< Shifted mode LOC20 for TIMER_ROUTELOC2 */ #define TIMER_ROUTELOC2_CDTI0LOC_LOC21 (_TIMER_ROUTELOC2_CDTI0LOC_LOC21 << 0) /**< Shifted mode LOC21 for TIMER_ROUTELOC2 */ #define TIMER_ROUTELOC2_CDTI0LOC_LOC22 (_TIMER_ROUTELOC2_CDTI0LOC_LOC22 << 0) /**< Shifted mode LOC22 for TIMER_ROUTELOC2 */ #define TIMER_ROUTELOC2_CDTI0LOC_LOC23 (_TIMER_ROUTELOC2_CDTI0LOC_LOC23 << 0) /**< Shifted mode LOC23 for TIMER_ROUTELOC2 */ #define TIMER_ROUTELOC2_CDTI0LOC_LOC24 (_TIMER_ROUTELOC2_CDTI0LOC_LOC24 << 0) /**< Shifted mode LOC24 for TIMER_ROUTELOC2 */ #define TIMER_ROUTELOC2_CDTI0LOC_LOC25 (_TIMER_ROUTELOC2_CDTI0LOC_LOC25 << 0) /**< Shifted mode LOC25 for TIMER_ROUTELOC2 */ #define TIMER_ROUTELOC2_CDTI0LOC_LOC26 (_TIMER_ROUTELOC2_CDTI0LOC_LOC26 << 0) /**< Shifted mode LOC26 for TIMER_ROUTELOC2 */ #define TIMER_ROUTELOC2_CDTI0LOC_LOC27 (_TIMER_ROUTELOC2_CDTI0LOC_LOC27 << 0) /**< Shifted mode LOC27 for TIMER_ROUTELOC2 */ #define TIMER_ROUTELOC2_CDTI0LOC_LOC28 (_TIMER_ROUTELOC2_CDTI0LOC_LOC28 << 0) /**< Shifted mode LOC28 for TIMER_ROUTELOC2 */ #define TIMER_ROUTELOC2_CDTI0LOC_LOC29 (_TIMER_ROUTELOC2_CDTI0LOC_LOC29 << 0) /**< Shifted mode LOC29 for TIMER_ROUTELOC2 */ #define TIMER_ROUTELOC2_CDTI0LOC_LOC30 (_TIMER_ROUTELOC2_CDTI0LOC_LOC30 << 0) /**< Shifted mode LOC30 for TIMER_ROUTELOC2 */ #define TIMER_ROUTELOC2_CDTI0LOC_LOC31 (_TIMER_ROUTELOC2_CDTI0LOC_LOC31 << 0) /**< Shifted mode LOC31 for TIMER_ROUTELOC2 */ #define _TIMER_ROUTELOC2_CDTI1LOC_SHIFT 8 /**< Shift value for TIMER_CDTI1LOC */ #define _TIMER_ROUTELOC2_CDTI1LOC_MASK 0x1F00UL /**< Bit mask for TIMER_CDTI1LOC */ #define _TIMER_ROUTELOC2_CDTI1LOC_LOC0 0x00000000UL /**< Mode LOC0 for TIMER_ROUTELOC2 */ #define _TIMER_ROUTELOC2_CDTI1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTELOC2 */ #define _TIMER_ROUTELOC2_CDTI1LOC_LOC1 0x00000001UL /**< Mode LOC1 for TIMER_ROUTELOC2 */ #define _TIMER_ROUTELOC2_CDTI1LOC_LOC2 0x00000002UL /**< Mode LOC2 for TIMER_ROUTELOC2 */ #define _TIMER_ROUTELOC2_CDTI1LOC_LOC3 0x00000003UL /**< Mode LOC3 for TIMER_ROUTELOC2 */ #define _TIMER_ROUTELOC2_CDTI1LOC_LOC4 0x00000004UL /**< Mode LOC4 for TIMER_ROUTELOC2 */ #define _TIMER_ROUTELOC2_CDTI1LOC_LOC5 0x00000005UL /**< Mode LOC5 for TIMER_ROUTELOC2 */ #define _TIMER_ROUTELOC2_CDTI1LOC_LOC6 0x00000006UL /**< Mode LOC6 for TIMER_ROUTELOC2 */ #define _TIMER_ROUTELOC2_CDTI1LOC_LOC7 0x00000007UL /**< Mode LOC7 for TIMER_ROUTELOC2 */ #define _TIMER_ROUTELOC2_CDTI1LOC_LOC8 0x00000008UL /**< Mode LOC8 for TIMER_ROUTELOC2 */ #define _TIMER_ROUTELOC2_CDTI1LOC_LOC9 0x00000009UL /**< Mode LOC9 for TIMER_ROUTELOC2 */ #define _TIMER_ROUTELOC2_CDTI1LOC_LOC10 0x0000000AUL /**< Mode LOC10 for TIMER_ROUTELOC2 */ #define _TIMER_ROUTELOC2_CDTI1LOC_LOC11 0x0000000BUL /**< Mode LOC11 for TIMER_ROUTELOC2 */ #define _TIMER_ROUTELOC2_CDTI1LOC_LOC12 0x0000000CUL /**< Mode LOC12 for TIMER_ROUTELOC2 */ #define _TIMER_ROUTELOC2_CDTI1LOC_LOC13 0x0000000DUL /**< Mode LOC13 for TIMER_ROUTELOC2 */ #define _TIMER_ROUTELOC2_CDTI1LOC_LOC14 0x0000000EUL /**< Mode LOC14 for TIMER_ROUTELOC2 */ #define _TIMER_ROUTELOC2_CDTI1LOC_LOC15 0x0000000FUL /**< Mode LOC15 for TIMER_ROUTELOC2 */ #define _TIMER_ROUTELOC2_CDTI1LOC_LOC16 0x00000010UL /**< Mode LOC16 for TIMER_ROUTELOC2 */ #define _TIMER_ROUTELOC2_CDTI1LOC_LOC17 0x00000011UL /**< Mode LOC17 for TIMER_ROUTELOC2 */ #define _TIMER_ROUTELOC2_CDTI1LOC_LOC18 0x00000012UL /**< Mode LOC18 for TIMER_ROUTELOC2 */ #define _TIMER_ROUTELOC2_CDTI1LOC_LOC19 0x00000013UL /**< Mode LOC19 for TIMER_ROUTELOC2 */ #define _TIMER_ROUTELOC2_CDTI1LOC_LOC20 0x00000014UL /**< Mode LOC20 for TIMER_ROUTELOC2 */ #define _TIMER_ROUTELOC2_CDTI1LOC_LOC21 0x00000015UL /**< Mode LOC21 for TIMER_ROUTELOC2 */ #define _TIMER_ROUTELOC2_CDTI1LOC_LOC22 0x00000016UL /**< Mode LOC22 for TIMER_ROUTELOC2 */ #define _TIMER_ROUTELOC2_CDTI1LOC_LOC23 0x00000017UL /**< Mode LOC23 for TIMER_ROUTELOC2 */ #define _TIMER_ROUTELOC2_CDTI1LOC_LOC24 0x00000018UL /**< Mode LOC24 for TIMER_ROUTELOC2 */ #define _TIMER_ROUTELOC2_CDTI1LOC_LOC25 0x00000019UL /**< Mode LOC25 for TIMER_ROUTELOC2 */ #define _TIMER_ROUTELOC2_CDTI1LOC_LOC26 0x0000001AUL /**< Mode LOC26 for TIMER_ROUTELOC2 */ #define _TIMER_ROUTELOC2_CDTI1LOC_LOC27 0x0000001BUL /**< Mode LOC27 for TIMER_ROUTELOC2 */ #define _TIMER_ROUTELOC2_CDTI1LOC_LOC28 0x0000001CUL /**< Mode LOC28 for TIMER_ROUTELOC2 */ #define _TIMER_ROUTELOC2_CDTI1LOC_LOC29 0x0000001DUL /**< Mode LOC29 for TIMER_ROUTELOC2 */ #define _TIMER_ROUTELOC2_CDTI1LOC_LOC30 0x0000001EUL /**< Mode LOC30 for TIMER_ROUTELOC2 */ #define _TIMER_ROUTELOC2_CDTI1LOC_LOC31 0x0000001FUL /**< Mode LOC31 for TIMER_ROUTELOC2 */ #define TIMER_ROUTELOC2_CDTI1LOC_LOC0 (_TIMER_ROUTELOC2_CDTI1LOC_LOC0 << 8) /**< Shifted mode LOC0 for TIMER_ROUTELOC2 */ #define TIMER_ROUTELOC2_CDTI1LOC_DEFAULT (_TIMER_ROUTELOC2_CDTI1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_ROUTELOC2 */ #define TIMER_ROUTELOC2_CDTI1LOC_LOC1 (_TIMER_ROUTELOC2_CDTI1LOC_LOC1 << 8) /**< Shifted mode LOC1 for TIMER_ROUTELOC2 */ #define TIMER_ROUTELOC2_CDTI1LOC_LOC2 (_TIMER_ROUTELOC2_CDTI1LOC_LOC2 << 8) /**< Shifted mode LOC2 for TIMER_ROUTELOC2 */ #define TIMER_ROUTELOC2_CDTI1LOC_LOC3 (_TIMER_ROUTELOC2_CDTI1LOC_LOC3 << 8) /**< Shifted mode LOC3 for TIMER_ROUTELOC2 */ #define TIMER_ROUTELOC2_CDTI1LOC_LOC4 (_TIMER_ROUTELOC2_CDTI1LOC_LOC4 << 8) /**< Shifted mode LOC4 for TIMER_ROUTELOC2 */ #define TIMER_ROUTELOC2_CDTI1LOC_LOC5 (_TIMER_ROUTELOC2_CDTI1LOC_LOC5 << 8) /**< Shifted mode LOC5 for TIMER_ROUTELOC2 */ #define TIMER_ROUTELOC2_CDTI1LOC_LOC6 (_TIMER_ROUTELOC2_CDTI1LOC_LOC6 << 8) /**< Shifted mode LOC6 for TIMER_ROUTELOC2 */ #define TIMER_ROUTELOC2_CDTI1LOC_LOC7 (_TIMER_ROUTELOC2_CDTI1LOC_LOC7 << 8) /**< Shifted mode LOC7 for TIMER_ROUTELOC2 */ #define TIMER_ROUTELOC2_CDTI1LOC_LOC8 (_TIMER_ROUTELOC2_CDTI1LOC_LOC8 << 8) /**< Shifted mode LOC8 for TIMER_ROUTELOC2 */ #define TIMER_ROUTELOC2_CDTI1LOC_LOC9 (_TIMER_ROUTELOC2_CDTI1LOC_LOC9 << 8) /**< Shifted mode LOC9 for TIMER_ROUTELOC2 */ #define TIMER_ROUTELOC2_CDTI1LOC_LOC10 (_TIMER_ROUTELOC2_CDTI1LOC_LOC10 << 8) /**< Shifted mode LOC10 for TIMER_ROUTELOC2 */ #define TIMER_ROUTELOC2_CDTI1LOC_LOC11 (_TIMER_ROUTELOC2_CDTI1LOC_LOC11 << 8) /**< Shifted mode LOC11 for TIMER_ROUTELOC2 */ #define TIMER_ROUTELOC2_CDTI1LOC_LOC12 (_TIMER_ROUTELOC2_CDTI1LOC_LOC12 << 8) /**< Shifted mode LOC12 for TIMER_ROUTELOC2 */ #define TIMER_ROUTELOC2_CDTI1LOC_LOC13 (_TIMER_ROUTELOC2_CDTI1LOC_LOC13 << 8) /**< Shifted mode LOC13 for TIMER_ROUTELOC2 */ #define TIMER_ROUTELOC2_CDTI1LOC_LOC14 (_TIMER_ROUTELOC2_CDTI1LOC_LOC14 << 8) /**< Shifted mode LOC14 for TIMER_ROUTELOC2 */ #define TIMER_ROUTELOC2_CDTI1LOC_LOC15 (_TIMER_ROUTELOC2_CDTI1LOC_LOC15 << 8) /**< Shifted mode LOC15 for TIMER_ROUTELOC2 */ #define TIMER_ROUTELOC2_CDTI1LOC_LOC16 (_TIMER_ROUTELOC2_CDTI1LOC_LOC16 << 8) /**< Shifted mode LOC16 for TIMER_ROUTELOC2 */ #define TIMER_ROUTELOC2_CDTI1LOC_LOC17 (_TIMER_ROUTELOC2_CDTI1LOC_LOC17 << 8) /**< Shifted mode LOC17 for TIMER_ROUTELOC2 */ #define TIMER_ROUTELOC2_CDTI1LOC_LOC18 (_TIMER_ROUTELOC2_CDTI1LOC_LOC18 << 8) /**< Shifted mode LOC18 for TIMER_ROUTELOC2 */ #define TIMER_ROUTELOC2_CDTI1LOC_LOC19 (_TIMER_ROUTELOC2_CDTI1LOC_LOC19 << 8) /**< Shifted mode LOC19 for TIMER_ROUTELOC2 */ #define TIMER_ROUTELOC2_CDTI1LOC_LOC20 (_TIMER_ROUTELOC2_CDTI1LOC_LOC20 << 8) /**< Shifted mode LOC20 for TIMER_ROUTELOC2 */ #define TIMER_ROUTELOC2_CDTI1LOC_LOC21 (_TIMER_ROUTELOC2_CDTI1LOC_LOC21 << 8) /**< Shifted mode LOC21 for TIMER_ROUTELOC2 */ #define TIMER_ROUTELOC2_CDTI1LOC_LOC22 (_TIMER_ROUTELOC2_CDTI1LOC_LOC22 << 8) /**< Shifted mode LOC22 for TIMER_ROUTELOC2 */ #define TIMER_ROUTELOC2_CDTI1LOC_LOC23 (_TIMER_ROUTELOC2_CDTI1LOC_LOC23 << 8) /**< Shifted mode LOC23 for TIMER_ROUTELOC2 */ #define TIMER_ROUTELOC2_CDTI1LOC_LOC24 (_TIMER_ROUTELOC2_CDTI1LOC_LOC24 << 8) /**< Shifted mode LOC24 for TIMER_ROUTELOC2 */ #define TIMER_ROUTELOC2_CDTI1LOC_LOC25 (_TIMER_ROUTELOC2_CDTI1LOC_LOC25 << 8) /**< Shifted mode LOC25 for TIMER_ROUTELOC2 */ #define TIMER_ROUTELOC2_CDTI1LOC_LOC26 (_TIMER_ROUTELOC2_CDTI1LOC_LOC26 << 8) /**< Shifted mode LOC26 for TIMER_ROUTELOC2 */ #define TIMER_ROUTELOC2_CDTI1LOC_LOC27 (_TIMER_ROUTELOC2_CDTI1LOC_LOC27 << 8) /**< Shifted mode LOC27 for TIMER_ROUTELOC2 */ #define TIMER_ROUTELOC2_CDTI1LOC_LOC28 (_TIMER_ROUTELOC2_CDTI1LOC_LOC28 << 8) /**< Shifted mode LOC28 for TIMER_ROUTELOC2 */ #define TIMER_ROUTELOC2_CDTI1LOC_LOC29 (_TIMER_ROUTELOC2_CDTI1LOC_LOC29 << 8) /**< Shifted mode LOC29 for TIMER_ROUTELOC2 */ #define TIMER_ROUTELOC2_CDTI1LOC_LOC30 (_TIMER_ROUTELOC2_CDTI1LOC_LOC30 << 8) /**< Shifted mode LOC30 for TIMER_ROUTELOC2 */ #define TIMER_ROUTELOC2_CDTI1LOC_LOC31 (_TIMER_ROUTELOC2_CDTI1LOC_LOC31 << 8) /**< Shifted mode LOC31 for TIMER_ROUTELOC2 */ #define _TIMER_ROUTELOC2_CDTI2LOC_SHIFT 16 /**< Shift value for TIMER_CDTI2LOC */ #define _TIMER_ROUTELOC2_CDTI2LOC_MASK 0x1F0000UL /**< Bit mask for TIMER_CDTI2LOC */ #define _TIMER_ROUTELOC2_CDTI2LOC_LOC0 0x00000000UL /**< Mode LOC0 for TIMER_ROUTELOC2 */ #define _TIMER_ROUTELOC2_CDTI2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTELOC2 */ #define _TIMER_ROUTELOC2_CDTI2LOC_LOC1 0x00000001UL /**< Mode LOC1 for TIMER_ROUTELOC2 */ #define _TIMER_ROUTELOC2_CDTI2LOC_LOC2 0x00000002UL /**< Mode LOC2 for TIMER_ROUTELOC2 */ #define _TIMER_ROUTELOC2_CDTI2LOC_LOC3 0x00000003UL /**< Mode LOC3 for TIMER_ROUTELOC2 */ #define _TIMER_ROUTELOC2_CDTI2LOC_LOC4 0x00000004UL /**< Mode LOC4 for TIMER_ROUTELOC2 */ #define _TIMER_ROUTELOC2_CDTI2LOC_LOC5 0x00000005UL /**< Mode LOC5 for TIMER_ROUTELOC2 */ #define _TIMER_ROUTELOC2_CDTI2LOC_LOC6 0x00000006UL /**< Mode LOC6 for TIMER_ROUTELOC2 */ #define _TIMER_ROUTELOC2_CDTI2LOC_LOC7 0x00000007UL /**< Mode LOC7 for TIMER_ROUTELOC2 */ #define _TIMER_ROUTELOC2_CDTI2LOC_LOC8 0x00000008UL /**< Mode LOC8 for TIMER_ROUTELOC2 */ #define _TIMER_ROUTELOC2_CDTI2LOC_LOC9 0x00000009UL /**< Mode LOC9 for TIMER_ROUTELOC2 */ #define _TIMER_ROUTELOC2_CDTI2LOC_LOC10 0x0000000AUL /**< Mode LOC10 for TIMER_ROUTELOC2 */ #define _TIMER_ROUTELOC2_CDTI2LOC_LOC11 0x0000000BUL /**< Mode LOC11 for TIMER_ROUTELOC2 */ #define _TIMER_ROUTELOC2_CDTI2LOC_LOC12 0x0000000CUL /**< Mode LOC12 for TIMER_ROUTELOC2 */ #define _TIMER_ROUTELOC2_CDTI2LOC_LOC13 0x0000000DUL /**< Mode LOC13 for TIMER_ROUTELOC2 */ #define _TIMER_ROUTELOC2_CDTI2LOC_LOC14 0x0000000EUL /**< Mode LOC14 for TIMER_ROUTELOC2 */ #define _TIMER_ROUTELOC2_CDTI2LOC_LOC15 0x0000000FUL /**< Mode LOC15 for TIMER_ROUTELOC2 */ #define _TIMER_ROUTELOC2_CDTI2LOC_LOC16 0x00000010UL /**< Mode LOC16 for TIMER_ROUTELOC2 */ #define _TIMER_ROUTELOC2_CDTI2LOC_LOC17 0x00000011UL /**< Mode LOC17 for TIMER_ROUTELOC2 */ #define _TIMER_ROUTELOC2_CDTI2LOC_LOC18 0x00000012UL /**< Mode LOC18 for TIMER_ROUTELOC2 */ #define _TIMER_ROUTELOC2_CDTI2LOC_LOC19 0x00000013UL /**< Mode LOC19 for TIMER_ROUTELOC2 */ #define _TIMER_ROUTELOC2_CDTI2LOC_LOC20 0x00000014UL /**< Mode LOC20 for TIMER_ROUTELOC2 */ #define _TIMER_ROUTELOC2_CDTI2LOC_LOC21 0x00000015UL /**< Mode LOC21 for TIMER_ROUTELOC2 */ #define _TIMER_ROUTELOC2_CDTI2LOC_LOC22 0x00000016UL /**< Mode LOC22 for TIMER_ROUTELOC2 */ #define _TIMER_ROUTELOC2_CDTI2LOC_LOC23 0x00000017UL /**< Mode LOC23 for TIMER_ROUTELOC2 */ #define _TIMER_ROUTELOC2_CDTI2LOC_LOC24 0x00000018UL /**< Mode LOC24 for TIMER_ROUTELOC2 */ #define _TIMER_ROUTELOC2_CDTI2LOC_LOC25 0x00000019UL /**< Mode LOC25 for TIMER_ROUTELOC2 */ #define _TIMER_ROUTELOC2_CDTI2LOC_LOC26 0x0000001AUL /**< Mode LOC26 for TIMER_ROUTELOC2 */ #define _TIMER_ROUTELOC2_CDTI2LOC_LOC27 0x0000001BUL /**< Mode LOC27 for TIMER_ROUTELOC2 */ #define _TIMER_ROUTELOC2_CDTI2LOC_LOC28 0x0000001CUL /**< Mode LOC28 for TIMER_ROUTELOC2 */ #define _TIMER_ROUTELOC2_CDTI2LOC_LOC29 0x0000001DUL /**< Mode LOC29 for TIMER_ROUTELOC2 */ #define _TIMER_ROUTELOC2_CDTI2LOC_LOC30 0x0000001EUL /**< Mode LOC30 for TIMER_ROUTELOC2 */ #define _TIMER_ROUTELOC2_CDTI2LOC_LOC31 0x0000001FUL /**< Mode LOC31 for TIMER_ROUTELOC2 */ #define TIMER_ROUTELOC2_CDTI2LOC_LOC0 (_TIMER_ROUTELOC2_CDTI2LOC_LOC0 << 16) /**< Shifted mode LOC0 for TIMER_ROUTELOC2 */ #define TIMER_ROUTELOC2_CDTI2LOC_DEFAULT (_TIMER_ROUTELOC2_CDTI2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_ROUTELOC2 */ #define TIMER_ROUTELOC2_CDTI2LOC_LOC1 (_TIMER_ROUTELOC2_CDTI2LOC_LOC1 << 16) /**< Shifted mode LOC1 for TIMER_ROUTELOC2 */ #define TIMER_ROUTELOC2_CDTI2LOC_LOC2 (_TIMER_ROUTELOC2_CDTI2LOC_LOC2 << 16) /**< Shifted mode LOC2 for TIMER_ROUTELOC2 */ #define TIMER_ROUTELOC2_CDTI2LOC_LOC3 (_TIMER_ROUTELOC2_CDTI2LOC_LOC3 << 16) /**< Shifted mode LOC3 for TIMER_ROUTELOC2 */ #define TIMER_ROUTELOC2_CDTI2LOC_LOC4 (_TIMER_ROUTELOC2_CDTI2LOC_LOC4 << 16) /**< Shifted mode LOC4 for TIMER_ROUTELOC2 */ #define TIMER_ROUTELOC2_CDTI2LOC_LOC5 (_TIMER_ROUTELOC2_CDTI2LOC_LOC5 << 16) /**< Shifted mode LOC5 for TIMER_ROUTELOC2 */ #define TIMER_ROUTELOC2_CDTI2LOC_LOC6 (_TIMER_ROUTELOC2_CDTI2LOC_LOC6 << 16) /**< Shifted mode LOC6 for TIMER_ROUTELOC2 */ #define TIMER_ROUTELOC2_CDTI2LOC_LOC7 (_TIMER_ROUTELOC2_CDTI2LOC_LOC7 << 16) /**< Shifted mode LOC7 for TIMER_ROUTELOC2 */ #define TIMER_ROUTELOC2_CDTI2LOC_LOC8 (_TIMER_ROUTELOC2_CDTI2LOC_LOC8 << 16) /**< Shifted mode LOC8 for TIMER_ROUTELOC2 */ #define TIMER_ROUTELOC2_CDTI2LOC_LOC9 (_TIMER_ROUTELOC2_CDTI2LOC_LOC9 << 16) /**< Shifted mode LOC9 for TIMER_ROUTELOC2 */ #define TIMER_ROUTELOC2_CDTI2LOC_LOC10 (_TIMER_ROUTELOC2_CDTI2LOC_LOC10 << 16) /**< Shifted mode LOC10 for TIMER_ROUTELOC2 */ #define TIMER_ROUTELOC2_CDTI2LOC_LOC11 (_TIMER_ROUTELOC2_CDTI2LOC_LOC11 << 16) /**< Shifted mode LOC11 for TIMER_ROUTELOC2 */ #define TIMER_ROUTELOC2_CDTI2LOC_LOC12 (_TIMER_ROUTELOC2_CDTI2LOC_LOC12 << 16) /**< Shifted mode LOC12 for TIMER_ROUTELOC2 */ #define TIMER_ROUTELOC2_CDTI2LOC_LOC13 (_TIMER_ROUTELOC2_CDTI2LOC_LOC13 << 16) /**< Shifted mode LOC13 for TIMER_ROUTELOC2 */ #define TIMER_ROUTELOC2_CDTI2LOC_LOC14 (_TIMER_ROUTELOC2_CDTI2LOC_LOC14 << 16) /**< Shifted mode LOC14 for TIMER_ROUTELOC2 */ #define TIMER_ROUTELOC2_CDTI2LOC_LOC15 (_TIMER_ROUTELOC2_CDTI2LOC_LOC15 << 16) /**< Shifted mode LOC15 for TIMER_ROUTELOC2 */ #define TIMER_ROUTELOC2_CDTI2LOC_LOC16 (_TIMER_ROUTELOC2_CDTI2LOC_LOC16 << 16) /**< Shifted mode LOC16 for TIMER_ROUTELOC2 */ #define TIMER_ROUTELOC2_CDTI2LOC_LOC17 (_TIMER_ROUTELOC2_CDTI2LOC_LOC17 << 16) /**< Shifted mode LOC17 for TIMER_ROUTELOC2 */ #define TIMER_ROUTELOC2_CDTI2LOC_LOC18 (_TIMER_ROUTELOC2_CDTI2LOC_LOC18 << 16) /**< Shifted mode LOC18 for TIMER_ROUTELOC2 */ #define TIMER_ROUTELOC2_CDTI2LOC_LOC19 (_TIMER_ROUTELOC2_CDTI2LOC_LOC19 << 16) /**< Shifted mode LOC19 for TIMER_ROUTELOC2 */ #define TIMER_ROUTELOC2_CDTI2LOC_LOC20 (_TIMER_ROUTELOC2_CDTI2LOC_LOC20 << 16) /**< Shifted mode LOC20 for TIMER_ROUTELOC2 */ #define TIMER_ROUTELOC2_CDTI2LOC_LOC21 (_TIMER_ROUTELOC2_CDTI2LOC_LOC21 << 16) /**< Shifted mode LOC21 for TIMER_ROUTELOC2 */ #define TIMER_ROUTELOC2_CDTI2LOC_LOC22 (_TIMER_ROUTELOC2_CDTI2LOC_LOC22 << 16) /**< Shifted mode LOC22 for TIMER_ROUTELOC2 */ #define TIMER_ROUTELOC2_CDTI2LOC_LOC23 (_TIMER_ROUTELOC2_CDTI2LOC_LOC23 << 16) /**< Shifted mode LOC23 for TIMER_ROUTELOC2 */ #define TIMER_ROUTELOC2_CDTI2LOC_LOC24 (_TIMER_ROUTELOC2_CDTI2LOC_LOC24 << 16) /**< Shifted mode LOC24 for TIMER_ROUTELOC2 */ #define TIMER_ROUTELOC2_CDTI2LOC_LOC25 (_TIMER_ROUTELOC2_CDTI2LOC_LOC25 << 16) /**< Shifted mode LOC25 for TIMER_ROUTELOC2 */ #define TIMER_ROUTELOC2_CDTI2LOC_LOC26 (_TIMER_ROUTELOC2_CDTI2LOC_LOC26 << 16) /**< Shifted mode LOC26 for TIMER_ROUTELOC2 */ #define TIMER_ROUTELOC2_CDTI2LOC_LOC27 (_TIMER_ROUTELOC2_CDTI2LOC_LOC27 << 16) /**< Shifted mode LOC27 for TIMER_ROUTELOC2 */ #define TIMER_ROUTELOC2_CDTI2LOC_LOC28 (_TIMER_ROUTELOC2_CDTI2LOC_LOC28 << 16) /**< Shifted mode LOC28 for TIMER_ROUTELOC2 */ #define TIMER_ROUTELOC2_CDTI2LOC_LOC29 (_TIMER_ROUTELOC2_CDTI2LOC_LOC29 << 16) /**< Shifted mode LOC29 for TIMER_ROUTELOC2 */ #define TIMER_ROUTELOC2_CDTI2LOC_LOC30 (_TIMER_ROUTELOC2_CDTI2LOC_LOC30 << 16) /**< Shifted mode LOC30 for TIMER_ROUTELOC2 */ #define TIMER_ROUTELOC2_CDTI2LOC_LOC31 (_TIMER_ROUTELOC2_CDTI2LOC_LOC31 << 16) /**< Shifted mode LOC31 for TIMER_ROUTELOC2 */ /* Bit fields for TIMER CC_CTRL */ #define _TIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_CTRL */ #define _TIMER_CC_CTRL_MASK 0x7F0F3F17UL /**< Mask for TIMER_CC_CTRL */ #define _TIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ #define _TIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ #define _TIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ #define _TIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for TIMER_CC_CTRL */ #define _TIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for TIMER_CC_CTRL */ #define _TIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for TIMER_CC_CTRL */ #define _TIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for TIMER_CC_CTRL */ #define TIMER_CC_CTRL_MODE_DEFAULT (_TIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ #define TIMER_CC_CTRL_MODE_OFF (_TIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for TIMER_CC_CTRL */ #define TIMER_CC_CTRL_MODE_INPUTCAPTURE (_TIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for TIMER_CC_CTRL */ #define TIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_TIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for TIMER_CC_CTRL */ #define TIMER_CC_CTRL_MODE_PWM (_TIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for TIMER_CC_CTRL */ #define TIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ #define _TIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ #define _TIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ #define _TIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ #define TIMER_CC_CTRL_OUTINV_DEFAULT (_TIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ #define TIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */ #define _TIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ #define _TIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ #define _TIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ #define TIMER_CC_CTRL_COIST_DEFAULT (_TIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ #define _TIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ #define _TIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ #define _TIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ #define _TIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for TIMER_CC_CTRL */ #define _TIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for TIMER_CC_CTRL */ #define _TIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_CC_CTRL */ #define _TIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for TIMER_CC_CTRL */ #define TIMER_CC_CTRL_CMOA_DEFAULT (_TIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ #define TIMER_CC_CTRL_CMOA_NONE (_TIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for TIMER_CC_CTRL */ #define TIMER_CC_CTRL_CMOA_TOGGLE (_TIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for TIMER_CC_CTRL */ #define TIMER_CC_CTRL_CMOA_CLEAR (_TIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for TIMER_CC_CTRL */ #define TIMER_CC_CTRL_CMOA_SET (_TIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for TIMER_CC_CTRL */ #define _TIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ #define _TIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ #define _TIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ #define _TIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for TIMER_CC_CTRL */ #define _TIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for TIMER_CC_CTRL */ #define _TIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_CC_CTRL */ #define _TIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for TIMER_CC_CTRL */ #define TIMER_CC_CTRL_COFOA_DEFAULT (_TIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ #define TIMER_CC_CTRL_COFOA_NONE (_TIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for TIMER_CC_CTRL */ #define TIMER_CC_CTRL_COFOA_TOGGLE (_TIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for TIMER_CC_CTRL */ #define TIMER_CC_CTRL_COFOA_CLEAR (_TIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for TIMER_CC_CTRL */ #define TIMER_CC_CTRL_COFOA_SET (_TIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for TIMER_CC_CTRL */ #define _TIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ #define _TIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ #define _TIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ #define _TIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for TIMER_CC_CTRL */ #define _TIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for TIMER_CC_CTRL */ #define _TIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_CC_CTRL */ #define _TIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for TIMER_CC_CTRL */ #define TIMER_CC_CTRL_CUFOA_DEFAULT (_TIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ #define TIMER_CC_CTRL_CUFOA_NONE (_TIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for TIMER_CC_CTRL */ #define TIMER_CC_CTRL_CUFOA_TOGGLE (_TIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for TIMER_CC_CTRL */ #define TIMER_CC_CTRL_CUFOA_CLEAR (_TIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for TIMER_CC_CTRL */ #define TIMER_CC_CTRL_CUFOA_SET (_TIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for TIMER_CC_CTRL */ #define _TIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */ #define _TIMER_CC_CTRL_PRSSEL_MASK 0xF0000UL /**< Bit mask for TIMER_PRSSEL */ #define _TIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ #define _TIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for TIMER_CC_CTRL */ #define _TIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for TIMER_CC_CTRL */ #define _TIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for TIMER_CC_CTRL */ #define _TIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for TIMER_CC_CTRL */ #define _TIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for TIMER_CC_CTRL */ #define _TIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for TIMER_CC_CTRL */ #define _TIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for TIMER_CC_CTRL */ #define _TIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for TIMER_CC_CTRL */ #define _TIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for TIMER_CC_CTRL */ #define _TIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for TIMER_CC_CTRL */ #define _TIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for TIMER_CC_CTRL */ #define _TIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for TIMER_CC_CTRL */ #define TIMER_CC_CTRL_PRSSEL_DEFAULT (_TIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ #define TIMER_CC_CTRL_PRSSEL_PRSCH0 (_TIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for TIMER_CC_CTRL */ #define TIMER_CC_CTRL_PRSSEL_PRSCH1 (_TIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for TIMER_CC_CTRL */ #define TIMER_CC_CTRL_PRSSEL_PRSCH2 (_TIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for TIMER_CC_CTRL */ #define TIMER_CC_CTRL_PRSSEL_PRSCH3 (_TIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for TIMER_CC_CTRL */ #define TIMER_CC_CTRL_PRSSEL_PRSCH4 (_TIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for TIMER_CC_CTRL */ #define TIMER_CC_CTRL_PRSSEL_PRSCH5 (_TIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for TIMER_CC_CTRL */ #define TIMER_CC_CTRL_PRSSEL_PRSCH6 (_TIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for TIMER_CC_CTRL */ #define TIMER_CC_CTRL_PRSSEL_PRSCH7 (_TIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for TIMER_CC_CTRL */ #define TIMER_CC_CTRL_PRSSEL_PRSCH8 (_TIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for TIMER_CC_CTRL */ #define TIMER_CC_CTRL_PRSSEL_PRSCH9 (_TIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for TIMER_CC_CTRL */ #define TIMER_CC_CTRL_PRSSEL_PRSCH10 (_TIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for TIMER_CC_CTRL */ #define TIMER_CC_CTRL_PRSSEL_PRSCH11 (_TIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for TIMER_CC_CTRL */ #define _TIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ #define _TIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ #define _TIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ #define _TIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for TIMER_CC_CTRL */ #define _TIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for TIMER_CC_CTRL */ #define _TIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for TIMER_CC_CTRL */ #define _TIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for TIMER_CC_CTRL */ #define TIMER_CC_CTRL_ICEDGE_DEFAULT (_TIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ #define TIMER_CC_CTRL_ICEDGE_RISING (_TIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for TIMER_CC_CTRL */ #define TIMER_CC_CTRL_ICEDGE_FALLING (_TIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for TIMER_CC_CTRL */ #define TIMER_CC_CTRL_ICEDGE_BOTH (_TIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for TIMER_CC_CTRL */ #define TIMER_CC_CTRL_ICEDGE_NONE (_TIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for TIMER_CC_CTRL */ #define _TIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ #define _TIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ #define _TIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ #define _TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for TIMER_CC_CTRL */ #define _TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for TIMER_CC_CTRL */ #define _TIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for TIMER_CC_CTRL */ #define _TIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for TIMER_CC_CTRL */ #define TIMER_CC_CTRL_ICEVCTRL_DEFAULT (_TIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ #define TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for TIMER_CC_CTRL */ #define TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for TIMER_CC_CTRL */ #define TIMER_CC_CTRL_ICEVCTRL_RISING (_TIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for TIMER_CC_CTRL */ #define TIMER_CC_CTRL_ICEVCTRL_FALLING (_TIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for TIMER_CC_CTRL */ #define TIMER_CC_CTRL_PRSCONF (0x1UL << 28) /**< PRS Configuration */ #define _TIMER_CC_CTRL_PRSCONF_SHIFT 28 /**< Shift value for TIMER_PRSCONF */ #define _TIMER_CC_CTRL_PRSCONF_MASK 0x10000000UL /**< Bit mask for TIMER_PRSCONF */ #define _TIMER_CC_CTRL_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ #define _TIMER_CC_CTRL_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for TIMER_CC_CTRL */ #define _TIMER_CC_CTRL_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for TIMER_CC_CTRL */ #define TIMER_CC_CTRL_PRSCONF_DEFAULT (_TIMER_CC_CTRL_PRSCONF_DEFAULT << 28) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ #define TIMER_CC_CTRL_PRSCONF_PULSE (_TIMER_CC_CTRL_PRSCONF_PULSE << 28) /**< Shifted mode PULSE for TIMER_CC_CTRL */ #define TIMER_CC_CTRL_PRSCONF_LEVEL (_TIMER_CC_CTRL_PRSCONF_LEVEL << 28) /**< Shifted mode LEVEL for TIMER_CC_CTRL */ #define TIMER_CC_CTRL_INSEL (0x1UL << 29) /**< Input Selection */ #define _TIMER_CC_CTRL_INSEL_SHIFT 29 /**< Shift value for TIMER_INSEL */ #define _TIMER_CC_CTRL_INSEL_MASK 0x20000000UL /**< Bit mask for TIMER_INSEL */ #define _TIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ #define _TIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for TIMER_CC_CTRL */ #define _TIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for TIMER_CC_CTRL */ #define TIMER_CC_CTRL_INSEL_DEFAULT (_TIMER_CC_CTRL_INSEL_DEFAULT << 29) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ #define TIMER_CC_CTRL_INSEL_PIN (_TIMER_CC_CTRL_INSEL_PIN << 29) /**< Shifted mode PIN for TIMER_CC_CTRL */ #define TIMER_CC_CTRL_INSEL_PRS (_TIMER_CC_CTRL_INSEL_PRS << 29) /**< Shifted mode PRS for TIMER_CC_CTRL */ #define TIMER_CC_CTRL_FILT (0x1UL << 30) /**< Digital Filter */ #define _TIMER_CC_CTRL_FILT_SHIFT 30 /**< Shift value for TIMER_FILT */ #define _TIMER_CC_CTRL_FILT_MASK 0x40000000UL /**< Bit mask for TIMER_FILT */ #define _TIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ #define _TIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for TIMER_CC_CTRL */ #define _TIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for TIMER_CC_CTRL */ #define TIMER_CC_CTRL_FILT_DEFAULT (_TIMER_CC_CTRL_FILT_DEFAULT << 30) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ #define TIMER_CC_CTRL_FILT_DISABLE (_TIMER_CC_CTRL_FILT_DISABLE << 30) /**< Shifted mode DISABLE for TIMER_CC_CTRL */ #define TIMER_CC_CTRL_FILT_ENABLE (_TIMER_CC_CTRL_FILT_ENABLE << 30) /**< Shifted mode ENABLE for TIMER_CC_CTRL */ /* Bit fields for TIMER CC_CCV */ #define _TIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_CCV */ #define _TIMER_CC_CCV_MASK 0x0000FFFFUL /**< Mask for TIMER_CC_CCV */ #define _TIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */ #define _TIMER_CC_CCV_CCV_MASK 0xFFFFUL /**< Bit mask for TIMER_CCV */ #define _TIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CCV */ #define TIMER_CC_CCV_CCV_DEFAULT (_TIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_CCV */ /* Bit fields for TIMER CC_CCVP */ #define _TIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_CCVP */ #define _TIMER_CC_CCVP_MASK 0x0000FFFFUL /**< Mask for TIMER_CC_CCVP */ #define _TIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */ #define _TIMER_CC_CCVP_CCVP_MASK 0xFFFFUL /**< Bit mask for TIMER_CCVP */ #define _TIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CCVP */ #define TIMER_CC_CCVP_CCVP_DEFAULT (_TIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_CCVP */ /* Bit fields for TIMER CC_CCVB */ #define _TIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_CCVB */ #define _TIMER_CC_CCVB_MASK 0x0000FFFFUL /**< Mask for TIMER_CC_CCVB */ #define _TIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */ #define _TIMER_CC_CCVB_CCVB_MASK 0xFFFFUL /**< Bit mask for TIMER_CCVB */ #define _TIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CCVB */ #define TIMER_CC_CCVB_CCVB_DEFAULT (_TIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_CCVB */ /* Bit fields for TIMER DTCTRL */ #define _TIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTCTRL */ #define _TIMER_DTCTRL_MASK 0x010006FFUL /**< Mask for TIMER_DTCTRL */ #define TIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */ #define _TIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ #define _TIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ #define _TIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */ #define TIMER_DTCTRL_DTEN_DEFAULT (_TIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTCTRL */ #define TIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ #define _TIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ #define _TIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ #define _TIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */ #define _TIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for TIMER_DTCTRL */ #define _TIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for TIMER_DTCTRL */ #define TIMER_DTCTRL_DTDAS_DEFAULT (_TIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTCTRL */ #define TIMER_DTCTRL_DTDAS_NORESTART (_TIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for TIMER_DTCTRL */ #define TIMER_DTCTRL_DTDAS_RESTART (_TIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for TIMER_DTCTRL */ #define TIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */ #define _TIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */ #define _TIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */ #define _TIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */ #define TIMER_DTCTRL_DTIPOL_DEFAULT (_TIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_DTCTRL */ #define TIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert */ #define _TIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */ #define _TIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */ #define _TIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */ #define TIMER_DTCTRL_DTCINV_DEFAULT (_TIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_DTCTRL */ #define _TIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */ #define _TIMER_DTCTRL_DTPRSSEL_MASK 0xF0UL /**< Bit mask for TIMER_DTPRSSEL */ #define _TIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */ #define _TIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for TIMER_DTCTRL */ #define _TIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for TIMER_DTCTRL */ #define _TIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for TIMER_DTCTRL */ #define _TIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for TIMER_DTCTRL */ #define _TIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for TIMER_DTCTRL */ #define _TIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for TIMER_DTCTRL */ #define _TIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for TIMER_DTCTRL */ #define _TIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for TIMER_DTCTRL */ #define _TIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for TIMER_DTCTRL */ #define _TIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for TIMER_DTCTRL */ #define _TIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for TIMER_DTCTRL */ #define _TIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for TIMER_DTCTRL */ #define TIMER_DTCTRL_DTPRSSEL_DEFAULT (_TIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_DTCTRL */ #define TIMER_DTCTRL_DTPRSSEL_PRSCH0 (_TIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for TIMER_DTCTRL */ #define TIMER_DTCTRL_DTPRSSEL_PRSCH1 (_TIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for TIMER_DTCTRL */ #define TIMER_DTCTRL_DTPRSSEL_PRSCH2 (_TIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for TIMER_DTCTRL */ #define TIMER_DTCTRL_DTPRSSEL_PRSCH3 (_TIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for TIMER_DTCTRL */ #define TIMER_DTCTRL_DTPRSSEL_PRSCH4 (_TIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for TIMER_DTCTRL */ #define TIMER_DTCTRL_DTPRSSEL_PRSCH5 (_TIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for TIMER_DTCTRL */ #define TIMER_DTCTRL_DTPRSSEL_PRSCH6 (_TIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for TIMER_DTCTRL */ #define TIMER_DTCTRL_DTPRSSEL_PRSCH7 (_TIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for TIMER_DTCTRL */ #define TIMER_DTCTRL_DTPRSSEL_PRSCH8 (_TIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for TIMER_DTCTRL */ #define TIMER_DTCTRL_DTPRSSEL_PRSCH9 (_TIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for TIMER_DTCTRL */ #define TIMER_DTCTRL_DTPRSSEL_PRSCH10 (_TIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for TIMER_DTCTRL */ #define TIMER_DTCTRL_DTPRSSEL_PRSCH11 (_TIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for TIMER_DTCTRL */ #define TIMER_DTCTRL_DTAR (0x1UL << 9) /**< DTI Always Run */ #define _TIMER_DTCTRL_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ #define _TIMER_DTCTRL_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ #define _TIMER_DTCTRL_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */ #define TIMER_DTCTRL_DTAR_DEFAULT (_TIMER_DTCTRL_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_DTCTRL */ #define TIMER_DTCTRL_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ #define _TIMER_DTCTRL_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ #define _TIMER_DTCTRL_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ #define _TIMER_DTCTRL_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */ #define TIMER_DTCTRL_DTFATS_DEFAULT (_TIMER_DTCTRL_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_DTCTRL */ #define TIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */ #define _TIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */ #define _TIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */ #define _TIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */ #define TIMER_DTCTRL_DTPRSEN_DEFAULT (_TIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_DTCTRL */ /* Bit fields for TIMER DTTIME */ #define _TIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTTIME */ #define _TIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for TIMER_DTTIME */ #define _TIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ #define _TIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */ #define _TIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTTIME */ #define _TIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for TIMER_DTTIME */ #define _TIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for TIMER_DTTIME */ #define _TIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for TIMER_DTTIME */ #define _TIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for TIMER_DTTIME */ #define _TIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for TIMER_DTTIME */ #define _TIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for TIMER_DTTIME */ #define _TIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for TIMER_DTTIME */ #define _TIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for TIMER_DTTIME */ #define _TIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for TIMER_DTTIME */ #define _TIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for TIMER_DTTIME */ #define _TIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for TIMER_DTTIME */ #define TIMER_DTTIME_DTPRESC_DEFAULT (_TIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTTIME */ #define TIMER_DTTIME_DTPRESC_DIV1 (_TIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for TIMER_DTTIME */ #define TIMER_DTTIME_DTPRESC_DIV2 (_TIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for TIMER_DTTIME */ #define TIMER_DTTIME_DTPRESC_DIV4 (_TIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for TIMER_DTTIME */ #define TIMER_DTTIME_DTPRESC_DIV8 (_TIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for TIMER_DTTIME */ #define TIMER_DTTIME_DTPRESC_DIV16 (_TIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for TIMER_DTTIME */ #define TIMER_DTTIME_DTPRESC_DIV32 (_TIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for TIMER_DTTIME */ #define TIMER_DTTIME_DTPRESC_DIV64 (_TIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for TIMER_DTTIME */ #define TIMER_DTTIME_DTPRESC_DIV128 (_TIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for TIMER_DTTIME */ #define TIMER_DTTIME_DTPRESC_DIV256 (_TIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for TIMER_DTTIME */ #define TIMER_DTTIME_DTPRESC_DIV512 (_TIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for TIMER_DTTIME */ #define TIMER_DTTIME_DTPRESC_DIV1024 (_TIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for TIMER_DTTIME */ #define _TIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */ #define _TIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */ #define _TIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTTIME */ #define TIMER_DTTIME_DTRISET_DEFAULT (_TIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_DTTIME */ #define _TIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ #define _TIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ #define _TIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTTIME */ #define TIMER_DTTIME_DTFALLT_DEFAULT (_TIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_DTTIME */ /* Bit fields for TIMER DTFC */ #define _TIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTFC */ #define _TIMER_DTFC_MASK 0x0F030F0FUL /**< Mask for TIMER_DTFC */ #define _TIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */ #define _TIMER_DTFC_DTPRS0FSEL_MASK 0xFUL /**< Bit mask for TIMER_DTPRS0FSEL */ #define _TIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFC */ #define _TIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for TIMER_DTFC */ #define _TIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for TIMER_DTFC */ #define _TIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for TIMER_DTFC */ #define _TIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for TIMER_DTFC */ #define _TIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for TIMER_DTFC */ #define _TIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for TIMER_DTFC */ #define _TIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for TIMER_DTFC */ #define _TIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for TIMER_DTFC */ #define _TIMER_DTFC_DTPRS0FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for TIMER_DTFC */ #define _TIMER_DTFC_DTPRS0FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for TIMER_DTFC */ #define _TIMER_DTFC_DTPRS0FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for TIMER_DTFC */ #define _TIMER_DTFC_DTPRS0FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for TIMER_DTFC */ #define TIMER_DTFC_DTPRS0FSEL_DEFAULT (_TIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTFC */ #define TIMER_DTFC_DTPRS0FSEL_PRSCH0 (_TIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for TIMER_DTFC */ #define TIMER_DTFC_DTPRS0FSEL_PRSCH1 (_TIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for TIMER_DTFC */ #define TIMER_DTFC_DTPRS0FSEL_PRSCH2 (_TIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for TIMER_DTFC */ #define TIMER_DTFC_DTPRS0FSEL_PRSCH3 (_TIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for TIMER_DTFC */ #define TIMER_DTFC_DTPRS0FSEL_PRSCH4 (_TIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for TIMER_DTFC */ #define TIMER_DTFC_DTPRS0FSEL_PRSCH5 (_TIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for TIMER_DTFC */ #define TIMER_DTFC_DTPRS0FSEL_PRSCH6 (_TIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for TIMER_DTFC */ #define TIMER_DTFC_DTPRS0FSEL_PRSCH7 (_TIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for TIMER_DTFC */ #define TIMER_DTFC_DTPRS0FSEL_PRSCH8 (_TIMER_DTFC_DTPRS0FSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for TIMER_DTFC */ #define TIMER_DTFC_DTPRS0FSEL_PRSCH9 (_TIMER_DTFC_DTPRS0FSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for TIMER_DTFC */ #define TIMER_DTFC_DTPRS0FSEL_PRSCH10 (_TIMER_DTFC_DTPRS0FSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for TIMER_DTFC */ #define TIMER_DTFC_DTPRS0FSEL_PRSCH11 (_TIMER_DTFC_DTPRS0FSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for TIMER_DTFC */ #define _TIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */ #define _TIMER_DTFC_DTPRS1FSEL_MASK 0xF00UL /**< Bit mask for TIMER_DTPRS1FSEL */ #define _TIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFC */ #define _TIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for TIMER_DTFC */ #define _TIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for TIMER_DTFC */ #define _TIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for TIMER_DTFC */ #define _TIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for TIMER_DTFC */ #define _TIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for TIMER_DTFC */ #define _TIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for TIMER_DTFC */ #define _TIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for TIMER_DTFC */ #define _TIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for TIMER_DTFC */ #define _TIMER_DTFC_DTPRS1FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for TIMER_DTFC */ #define _TIMER_DTFC_DTPRS1FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for TIMER_DTFC */ #define _TIMER_DTFC_DTPRS1FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for TIMER_DTFC */ #define _TIMER_DTFC_DTPRS1FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for TIMER_DTFC */ #define TIMER_DTFC_DTPRS1FSEL_DEFAULT (_TIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_DTFC */ #define TIMER_DTFC_DTPRS1FSEL_PRSCH0 (_TIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for TIMER_DTFC */ #define TIMER_DTFC_DTPRS1FSEL_PRSCH1 (_TIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for TIMER_DTFC */ #define TIMER_DTFC_DTPRS1FSEL_PRSCH2 (_TIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for TIMER_DTFC */ #define TIMER_DTFC_DTPRS1FSEL_PRSCH3 (_TIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for TIMER_DTFC */ #define TIMER_DTFC_DTPRS1FSEL_PRSCH4 (_TIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for TIMER_DTFC */ #define TIMER_DTFC_DTPRS1FSEL_PRSCH5 (_TIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for TIMER_DTFC */ #define TIMER_DTFC_DTPRS1FSEL_PRSCH6 (_TIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for TIMER_DTFC */ #define TIMER_DTFC_DTPRS1FSEL_PRSCH7 (_TIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for TIMER_DTFC */ #define TIMER_DTFC_DTPRS1FSEL_PRSCH8 (_TIMER_DTFC_DTPRS1FSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for TIMER_DTFC */ #define TIMER_DTFC_DTPRS1FSEL_PRSCH9 (_TIMER_DTFC_DTPRS1FSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for TIMER_DTFC */ #define TIMER_DTFC_DTPRS1FSEL_PRSCH10 (_TIMER_DTFC_DTPRS1FSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for TIMER_DTFC */ #define TIMER_DTFC_DTPRS1FSEL_PRSCH11 (_TIMER_DTFC_DTPRS1FSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for TIMER_DTFC */ #define _TIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ #define _TIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ #define _TIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFC */ #define _TIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for TIMER_DTFC */ #define _TIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for TIMER_DTFC */ #define _TIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_DTFC */ #define _TIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for TIMER_DTFC */ #define TIMER_DTFC_DTFA_DEFAULT (_TIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_DTFC */ #define TIMER_DTFC_DTFA_NONE (_TIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for TIMER_DTFC */ #define TIMER_DTFC_DTFA_INACTIVE (_TIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for TIMER_DTFC */ #define TIMER_DTFC_DTFA_CLEAR (_TIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for TIMER_DTFC */ #define TIMER_DTFC_DTFA_TRISTATE (_TIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for TIMER_DTFC */ #define TIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ #define _TIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ #define _TIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ #define _TIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFC */ #define TIMER_DTFC_DTPRS0FEN_DEFAULT (_TIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_DTFC */ #define TIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ #define _TIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ #define _TIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ #define _TIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFC */ #define TIMER_DTFC_DTPRS1FEN_DEFAULT (_TIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for TIMER_DTFC */ #define TIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ #define _TIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ #define _TIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ #define _TIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFC */ #define TIMER_DTFC_DTDBGFEN_DEFAULT (_TIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for TIMER_DTFC */ #define TIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ #define _TIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ #define _TIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ #define _TIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFC */ #define TIMER_DTFC_DTLOCKUPFEN_DEFAULT (_TIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for TIMER_DTFC */ /* Bit fields for TIMER DTOGEN */ #define _TIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTOGEN */ #define _TIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for TIMER_DTOGEN */ #define TIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */ #define _TIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ #define _TIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ #define _TIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ #define TIMER_DTOGEN_DTOGCC0EN_DEFAULT (_TIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ #define TIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */ #define _TIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ #define _TIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ #define _TIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ #define TIMER_DTOGEN_DTOGCC1EN_DEFAULT (_TIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ #define TIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */ #define _TIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ #define _TIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ #define _TIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ #define TIMER_DTOGEN_DTOGCC2EN_DEFAULT (_TIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ #define TIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */ #define _TIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ #define _TIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ #define _TIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ #define TIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_TIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ #define TIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */ #define _TIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ #define _TIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ #define _TIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ #define TIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_TIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ #define TIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */ #define _TIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ #define _TIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ #define _TIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ #define TIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_TIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ /* Bit fields for TIMER DTFAULT */ #define _TIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTFAULT */ #define _TIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for TIMER_DTFAULT */ #define TIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ #define _TIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ #define _TIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ #define _TIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */ #define TIMER_DTFAULT_DTPRS0F_DEFAULT (_TIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTFAULT */ #define TIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ #define _TIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ #define _TIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ #define _TIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */ #define TIMER_DTFAULT_DTPRS1F_DEFAULT (_TIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTFAULT */ #define TIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ #define _TIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ #define _TIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ #define _TIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */ #define TIMER_DTFAULT_DTDBGF_DEFAULT (_TIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_DTFAULT */ #define TIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ #define _TIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ #define _TIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ #define _TIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */ #define TIMER_DTFAULT_DTLOCKUPF_DEFAULT (_TIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_DTFAULT */ /* Bit fields for TIMER DTFAULTC */ #define _TIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTFAULTC */ #define _TIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for TIMER_DTFAULTC */ #define TIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ #define _TIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ #define _TIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ #define _TIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */ #define TIMER_DTFAULTC_DTPRS0FC_DEFAULT (_TIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */ #define TIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ #define _TIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ #define _TIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ #define _TIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */ #define TIMER_DTFAULTC_DTPRS1FC_DEFAULT (_TIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */ #define TIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ #define _TIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ #define _TIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ #define _TIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */ #define TIMER_DTFAULTC_DTDBGFC_DEFAULT (_TIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */ #define TIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ #define _TIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */ #define _TIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */ #define _TIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */ #define TIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_TIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */ /* Bit fields for TIMER DTLOCK */ #define _TIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTLOCK */ #define _TIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for TIMER_DTLOCK */ #define _TIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ #define _TIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ #define _TIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTLOCK */ #define _TIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for TIMER_DTLOCK */ #define _TIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for TIMER_DTLOCK */ #define _TIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for TIMER_DTLOCK */ #define _TIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for TIMER_DTLOCK */ #define TIMER_DTLOCK_LOCKKEY_DEFAULT (_TIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTLOCK */ #define TIMER_DTLOCK_LOCKKEY_LOCK (_TIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for TIMER_DTLOCK */ #define TIMER_DTLOCK_LOCKKEY_UNLOCKED (_TIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for TIMER_DTLOCK */ #define TIMER_DTLOCK_LOCKKEY_LOCKED (_TIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for TIMER_DTLOCK */ #define TIMER_DTLOCK_LOCKKEY_UNLOCK (_TIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for TIMER_DTLOCK */ /** @} */ /** @} End of group EFR32MG12P_TIMER */ /** @} End of group Parts */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_timer_cc.h.
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/***************************************************************************//** * @file * @brief EFR32MG12P_TIMER_CC register and bit field definitions * @version 5.7.0 ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * SPDX-License-Identifier: Zlib * * The licensor of this software is Silicon Laboratories Inc. * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be * appreciated but is not required. * 2. Altered source versions must be plainly marked as such, and must not be * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * ******************************************************************************/ #if defined(__ICCARM__) #pragma system_include /* Treat file as system include file. */ #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang system_header /* Treat file as system include file. */ #endif /***************************************************************************//** * @addtogroup Parts * @{ ******************************************************************************/ /***************************************************************************//** * @brief TIMER_CC TIMER CC Register * @ingroup EFR32MG12P_TIMER ******************************************************************************/ typedef struct { __IOM uint32_t CTRL; /**< CC Channel Control Register */ __IOM uint32_t CCV; /**< CC Channel Value Register */ __IM uint32_t CCVP; /**< CC Channel Value Peek Register */ __IOM uint32_t CCVB; /**< CC Channel Buffer Register */ } TIMER_CC_TypeDef; /** @} End of group Parts */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_trng.h.
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/***************************************************************************//** * @file * @brief EFR32MG12P_TRNG register and bit field definitions * @version 5.7.0 ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * SPDX-License-Identifier: Zlib * * The licensor of this software is Silicon Laboratories Inc. * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be * appreciated but is not required. * 2. Altered source versions must be plainly marked as such, and must not be * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * ******************************************************************************/ #if defined(__ICCARM__) #pragma system_include /* Treat file as system include file. */ #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang system_header /* Treat file as system include file. */ #endif /***************************************************************************//** * @addtogroup Parts * @{ ******************************************************************************/ /***************************************************************************//** * @defgroup EFR32MG12P_TRNG TRNG * @{ * @brief EFR32MG12P_TRNG Register Declaration ******************************************************************************/ /** TRNG Register Declaration */ typedef struct { __IOM uint32_t CONTROL; /**< Main Control Register */ __IM uint32_t FIFOLEVEL; /**< FIFO Level Register */ uint32_t RESERVED0[1U]; /**< Reserved for future use **/ __IM uint32_t FIFODEPTH; /**< FIFO Depth Register */ __IOM uint32_t KEY0; /**< Key Register 0 */ __IOM uint32_t KEY1; /**< Key Register 1 */ __IOM uint32_t KEY2; /**< Key Register 2 */ __IOM uint32_t KEY3; /**< Key Register 3 */ __IOM uint32_t TESTDATA; /**< Test Data Register */ uint32_t RESERVED1[3U]; /**< Reserved for future use **/ __IOM uint32_t STATUS; /**< Status Register */ __IOM uint32_t INITWAITVAL; /**< Initial Wait Counter */ uint32_t RESERVED2[50U]; /**< Reserved for future use **/ __IM uint32_t FIFO; /**< FIFO Data */ } TRNG_TypeDef; /** @} */ /***************************************************************************//** * @addtogroup EFR32MG12P_TRNG * @{ * @defgroup EFR32MG12P_TRNG_BitFields TRNG Bit Fields * @{ ******************************************************************************/ /* Bit fields for TRNG CONTROL */ #define _TRNG_CONTROL_RESETVALUE 0x00000000UL /**< Default value for TRNG_CONTROL */ #define _TRNG_CONTROL_MASK 0x00003FFDUL /**< Mask for TRNG_CONTROL */ #define TRNG_CONTROL_ENABLE (0x1UL << 0) /**< TRNG Module Enable */ #define _TRNG_CONTROL_ENABLE_SHIFT 0 /**< Shift value for TRNG_ENABLE */ #define _TRNG_CONTROL_ENABLE_MASK 0x1UL /**< Bit mask for TRNG_ENABLE */ #define _TRNG_CONTROL_ENABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */ #define _TRNG_CONTROL_ENABLE_DISABLED 0x00000000UL /**< Mode DISABLED for TRNG_CONTROL */ #define _TRNG_CONTROL_ENABLE_ENABLED 0x00000001UL /**< Mode ENABLED for TRNG_CONTROL */ #define TRNG_CONTROL_ENABLE_DEFAULT (_TRNG_CONTROL_ENABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_CONTROL */ #define TRNG_CONTROL_ENABLE_DISABLED (_TRNG_CONTROL_ENABLE_DISABLED << 0) /**< Shifted mode DISABLED for TRNG_CONTROL */ #define TRNG_CONTROL_ENABLE_ENABLED (_TRNG_CONTROL_ENABLE_ENABLED << 0) /**< Shifted mode ENABLED for TRNG_CONTROL */ #define TRNG_CONTROL_TESTEN (0x1UL << 2) /**< Test Enable */ #define _TRNG_CONTROL_TESTEN_SHIFT 2 /**< Shift value for TRNG_TESTEN */ #define _TRNG_CONTROL_TESTEN_MASK 0x4UL /**< Bit mask for TRNG_TESTEN */ #define _TRNG_CONTROL_TESTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */ #define _TRNG_CONTROL_TESTEN_NOISE 0x00000000UL /**< Mode NOISE for TRNG_CONTROL */ #define _TRNG_CONTROL_TESTEN_TESTDATA 0x00000001UL /**< Mode TESTDATA for TRNG_CONTROL */ #define TRNG_CONTROL_TESTEN_DEFAULT (_TRNG_CONTROL_TESTEN_DEFAULT << 2) /**< Shifted mode DEFAULT for TRNG_CONTROL */ #define TRNG_CONTROL_TESTEN_NOISE (_TRNG_CONTROL_TESTEN_NOISE << 2) /**< Shifted mode NOISE for TRNG_CONTROL */ #define TRNG_CONTROL_TESTEN_TESTDATA (_TRNG_CONTROL_TESTEN_TESTDATA << 2) /**< Shifted mode TESTDATA for TRNG_CONTROL */ #define TRNG_CONTROL_CONDBYPASS (0x1UL << 3) /**< Conditioning Bypass */ #define _TRNG_CONTROL_CONDBYPASS_SHIFT 3 /**< Shift value for TRNG_CONDBYPASS */ #define _TRNG_CONTROL_CONDBYPASS_MASK 0x8UL /**< Bit mask for TRNG_CONDBYPASS */ #define _TRNG_CONTROL_CONDBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */ #define _TRNG_CONTROL_CONDBYPASS_NORMAL 0x00000000UL /**< Mode NORMAL for TRNG_CONTROL */ #define _TRNG_CONTROL_CONDBYPASS_BYPASS 0x00000001UL /**< Mode BYPASS for TRNG_CONTROL */ #define TRNG_CONTROL_CONDBYPASS_DEFAULT (_TRNG_CONTROL_CONDBYPASS_DEFAULT << 3) /**< Shifted mode DEFAULT for TRNG_CONTROL */ #define TRNG_CONTROL_CONDBYPASS_NORMAL (_TRNG_CONTROL_CONDBYPASS_NORMAL << 3) /**< Shifted mode NORMAL for TRNG_CONTROL */ #define TRNG_CONTROL_CONDBYPASS_BYPASS (_TRNG_CONTROL_CONDBYPASS_BYPASS << 3) /**< Shifted mode BYPASS for TRNG_CONTROL */ #define TRNG_CONTROL_REPCOUNTIEN (0x1UL << 4) /**< Interrupt Enable for Repetition Count Test Failure */ #define _TRNG_CONTROL_REPCOUNTIEN_SHIFT 4 /**< Shift value for TRNG_REPCOUNTIEN */ #define _TRNG_CONTROL_REPCOUNTIEN_MASK 0x10UL /**< Bit mask for TRNG_REPCOUNTIEN */ #define _TRNG_CONTROL_REPCOUNTIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */ #define TRNG_CONTROL_REPCOUNTIEN_DEFAULT (_TRNG_CONTROL_REPCOUNTIEN_DEFAULT << 4) /**< Shifted mode DEFAULT for TRNG_CONTROL */ #define TRNG_CONTROL_APT64IEN (0x1UL << 5) /**< Interrupt Enable for Adaptive Proportion Test Failure (64-sample Window) */ #define _TRNG_CONTROL_APT64IEN_SHIFT 5 /**< Shift value for TRNG_APT64IEN */ #define _TRNG_CONTROL_APT64IEN_MASK 0x20UL /**< Bit mask for TRNG_APT64IEN */ #define _TRNG_CONTROL_APT64IEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */ #define TRNG_CONTROL_APT64IEN_DEFAULT (_TRNG_CONTROL_APT64IEN_DEFAULT << 5) /**< Shifted mode DEFAULT for TRNG_CONTROL */ #define TRNG_CONTROL_APT4096IEN (0x1UL << 6) /**< Interrupt Enable for Adaptive Proportion Test Failure (4096-sample Window) */ #define _TRNG_CONTROL_APT4096IEN_SHIFT 6 /**< Shift value for TRNG_APT4096IEN */ #define _TRNG_CONTROL_APT4096IEN_MASK 0x40UL /**< Bit mask for TRNG_APT4096IEN */ #define _TRNG_CONTROL_APT4096IEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */ #define TRNG_CONTROL_APT4096IEN_DEFAULT (_TRNG_CONTROL_APT4096IEN_DEFAULT << 6) /**< Shifted mode DEFAULT for TRNG_CONTROL */ #define TRNG_CONTROL_FULLIEN (0x1UL << 7) /**< Interrupt Enable for FIFO Full */ #define _TRNG_CONTROL_FULLIEN_SHIFT 7 /**< Shift value for TRNG_FULLIEN */ #define _TRNG_CONTROL_FULLIEN_MASK 0x80UL /**< Bit mask for TRNG_FULLIEN */ #define _TRNG_CONTROL_FULLIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */ #define TRNG_CONTROL_FULLIEN_DEFAULT (_TRNG_CONTROL_FULLIEN_DEFAULT << 7) /**< Shifted mode DEFAULT for TRNG_CONTROL */ #define TRNG_CONTROL_SOFTRESET (0x1UL << 8) /**< Software Reset */ #define _TRNG_CONTROL_SOFTRESET_SHIFT 8 /**< Shift value for TRNG_SOFTRESET */ #define _TRNG_CONTROL_SOFTRESET_MASK 0x100UL /**< Bit mask for TRNG_SOFTRESET */ #define _TRNG_CONTROL_SOFTRESET_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */ #define _TRNG_CONTROL_SOFTRESET_NORMAL 0x00000000UL /**< Mode NORMAL for TRNG_CONTROL */ #define _TRNG_CONTROL_SOFTRESET_RESET 0x00000001UL /**< Mode RESET for TRNG_CONTROL */ #define TRNG_CONTROL_SOFTRESET_DEFAULT (_TRNG_CONTROL_SOFTRESET_DEFAULT << 8) /**< Shifted mode DEFAULT for TRNG_CONTROL */ #define TRNG_CONTROL_SOFTRESET_NORMAL (_TRNG_CONTROL_SOFTRESET_NORMAL << 8) /**< Shifted mode NORMAL for TRNG_CONTROL */ #define TRNG_CONTROL_SOFTRESET_RESET (_TRNG_CONTROL_SOFTRESET_RESET << 8) /**< Shifted mode RESET for TRNG_CONTROL */ #define TRNG_CONTROL_PREIEN (0x1UL << 9) /**< Interrupt enable for AIS31 preliminary noise alarm */ #define _TRNG_CONTROL_PREIEN_SHIFT 9 /**< Shift value for TRNG_PREIEN */ #define _TRNG_CONTROL_PREIEN_MASK 0x200UL /**< Bit mask for TRNG_PREIEN */ #define _TRNG_CONTROL_PREIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */ #define TRNG_CONTROL_PREIEN_DEFAULT (_TRNG_CONTROL_PREIEN_DEFAULT << 9) /**< Shifted mode DEFAULT for TRNG_CONTROL */ #define TRNG_CONTROL_ALMIEN (0x1UL << 10) /**< Interrupt enable for AIS31 noise alarm */ #define _TRNG_CONTROL_ALMIEN_SHIFT 10 /**< Shift value for TRNG_ALMIEN */ #define _TRNG_CONTROL_ALMIEN_MASK 0x400UL /**< Bit mask for TRNG_ALMIEN */ #define _TRNG_CONTROL_ALMIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */ #define TRNG_CONTROL_ALMIEN_DEFAULT (_TRNG_CONTROL_ALMIEN_DEFAULT << 10) /**< Shifted mode DEFAULT for TRNG_CONTROL */ #define TRNG_CONTROL_FORCERUN (0x1UL << 11) /**< Oscillator Force Run */ #define _TRNG_CONTROL_FORCERUN_SHIFT 11 /**< Shift value for TRNG_FORCERUN */ #define _TRNG_CONTROL_FORCERUN_MASK 0x800UL /**< Bit mask for TRNG_FORCERUN */ #define _TRNG_CONTROL_FORCERUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */ #define _TRNG_CONTROL_FORCERUN_NORMAL 0x00000000UL /**< Mode NORMAL for TRNG_CONTROL */ #define _TRNG_CONTROL_FORCERUN_RUN 0x00000001UL /**< Mode RUN for TRNG_CONTROL */ #define TRNG_CONTROL_FORCERUN_DEFAULT (_TRNG_CONTROL_FORCERUN_DEFAULT << 11) /**< Shifted mode DEFAULT for TRNG_CONTROL */ #define TRNG_CONTROL_FORCERUN_NORMAL (_TRNG_CONTROL_FORCERUN_NORMAL << 11) /**< Shifted mode NORMAL for TRNG_CONTROL */ #define TRNG_CONTROL_FORCERUN_RUN (_TRNG_CONTROL_FORCERUN_RUN << 11) /**< Shifted mode RUN for TRNG_CONTROL */ #define TRNG_CONTROL_BYPNIST (0x1UL << 12) /**< NIST Start-up Test Bypass. */ #define _TRNG_CONTROL_BYPNIST_SHIFT 12 /**< Shift value for TRNG_BYPNIST */ #define _TRNG_CONTROL_BYPNIST_MASK 0x1000UL /**< Bit mask for TRNG_BYPNIST */ #define _TRNG_CONTROL_BYPNIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */ #define _TRNG_CONTROL_BYPNIST_NORMAL 0x00000000UL /**< Mode NORMAL for TRNG_CONTROL */ #define _TRNG_CONTROL_BYPNIST_BYPASS 0x00000001UL /**< Mode BYPASS for TRNG_CONTROL */ #define TRNG_CONTROL_BYPNIST_DEFAULT (_TRNG_CONTROL_BYPNIST_DEFAULT << 12) /**< Shifted mode DEFAULT for TRNG_CONTROL */ #define TRNG_CONTROL_BYPNIST_NORMAL (_TRNG_CONTROL_BYPNIST_NORMAL << 12) /**< Shifted mode NORMAL for TRNG_CONTROL */ #define TRNG_CONTROL_BYPNIST_BYPASS (_TRNG_CONTROL_BYPNIST_BYPASS << 12) /**< Shifted mode BYPASS for TRNG_CONTROL */ #define TRNG_CONTROL_BYPAIS31 (0x1UL << 13) /**< AIS31 Start-up Test Bypass. */ #define _TRNG_CONTROL_BYPAIS31_SHIFT 13 /**< Shift value for TRNG_BYPAIS31 */ #define _TRNG_CONTROL_BYPAIS31_MASK 0x2000UL /**< Bit mask for TRNG_BYPAIS31 */ #define _TRNG_CONTROL_BYPAIS31_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */ #define _TRNG_CONTROL_BYPAIS31_NORMAL 0x00000000UL /**< Mode NORMAL for TRNG_CONTROL */ #define _TRNG_CONTROL_BYPAIS31_BYPASS 0x00000001UL /**< Mode BYPASS for TRNG_CONTROL */ #define TRNG_CONTROL_BYPAIS31_DEFAULT (_TRNG_CONTROL_BYPAIS31_DEFAULT << 13) /**< Shifted mode DEFAULT for TRNG_CONTROL */ #define TRNG_CONTROL_BYPAIS31_NORMAL (_TRNG_CONTROL_BYPAIS31_NORMAL << 13) /**< Shifted mode NORMAL for TRNG_CONTROL */ #define TRNG_CONTROL_BYPAIS31_BYPASS (_TRNG_CONTROL_BYPAIS31_BYPASS << 13) /**< Shifted mode BYPASS for TRNG_CONTROL */ /* Bit fields for TRNG FIFOLEVEL */ #define _TRNG_FIFOLEVEL_RESETVALUE 0x00000000UL /**< Default value for TRNG_FIFOLEVEL */ #define _TRNG_FIFOLEVEL_MASK 0xFFFFFFFFUL /**< Mask for TRNG_FIFOLEVEL */ #define _TRNG_FIFOLEVEL_VALUE_SHIFT 0 /**< Shift value for TRNG_VALUE */ #define _TRNG_FIFOLEVEL_VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for TRNG_VALUE */ #define _TRNG_FIFOLEVEL_VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_FIFOLEVEL */ #define TRNG_FIFOLEVEL_VALUE_DEFAULT (_TRNG_FIFOLEVEL_VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_FIFOLEVEL */ /* Bit fields for TRNG FIFODEPTH */ #define _TRNG_FIFODEPTH_RESETVALUE 0x00000040UL /**< Default value for TRNG_FIFODEPTH */ #define _TRNG_FIFODEPTH_MASK 0xFFFFFFFFUL /**< Mask for TRNG_FIFODEPTH */ #define _TRNG_FIFODEPTH_VALUE_SHIFT 0 /**< Shift value for TRNG_VALUE */ #define _TRNG_FIFODEPTH_VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for TRNG_VALUE */ #define _TRNG_FIFODEPTH_VALUE_DEFAULT 0x00000040UL /**< Mode DEFAULT for TRNG_FIFODEPTH */ #define TRNG_FIFODEPTH_VALUE_DEFAULT (_TRNG_FIFODEPTH_VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_FIFODEPTH */ /* Bit fields for TRNG KEY0 */ #define _TRNG_KEY0_RESETVALUE 0x00000000UL /**< Default value for TRNG_KEY0 */ #define _TRNG_KEY0_MASK 0xFFFFFFFFUL /**< Mask for TRNG_KEY0 */ #define _TRNG_KEY0_VALUE_SHIFT 0 /**< Shift value for TRNG_VALUE */ #define _TRNG_KEY0_VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for TRNG_VALUE */ #define _TRNG_KEY0_VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_KEY0 */ #define TRNG_KEY0_VALUE_DEFAULT (_TRNG_KEY0_VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_KEY0 */ /* Bit fields for TRNG KEY1 */ #define _TRNG_KEY1_RESETVALUE 0x00000000UL /**< Default value for TRNG_KEY1 */ #define _TRNG_KEY1_MASK 0xFFFFFFFFUL /**< Mask for TRNG_KEY1 */ #define _TRNG_KEY1_VALUE_SHIFT 0 /**< Shift value for TRNG_VALUE */ #define _TRNG_KEY1_VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for TRNG_VALUE */ #define _TRNG_KEY1_VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_KEY1 */ #define TRNG_KEY1_VALUE_DEFAULT (_TRNG_KEY1_VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_KEY1 */ /* Bit fields for TRNG KEY2 */ #define _TRNG_KEY2_RESETVALUE 0x00000000UL /**< Default value for TRNG_KEY2 */ #define _TRNG_KEY2_MASK 0xFFFFFFFFUL /**< Mask for TRNG_KEY2 */ #define _TRNG_KEY2_VALUE_SHIFT 0 /**< Shift value for TRNG_VALUE */ #define _TRNG_KEY2_VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for TRNG_VALUE */ #define _TRNG_KEY2_VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_KEY2 */ #define TRNG_KEY2_VALUE_DEFAULT (_TRNG_KEY2_VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_KEY2 */ /* Bit fields for TRNG KEY3 */ #define _TRNG_KEY3_RESETVALUE 0x00000000UL /**< Default value for TRNG_KEY3 */ #define _TRNG_KEY3_MASK 0xFFFFFFFFUL /**< Mask for TRNG_KEY3 */ #define _TRNG_KEY3_VALUE_SHIFT 0 /**< Shift value for TRNG_VALUE */ #define _TRNG_KEY3_VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for TRNG_VALUE */ #define _TRNG_KEY3_VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_KEY3 */ #define TRNG_KEY3_VALUE_DEFAULT (_TRNG_KEY3_VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_KEY3 */ /* Bit fields for TRNG TESTDATA */ #define _TRNG_TESTDATA_RESETVALUE 0x00000000UL /**< Default value for TRNG_TESTDATA */ #define _TRNG_TESTDATA_MASK 0xFFFFFFFFUL /**< Mask for TRNG_TESTDATA */ #define _TRNG_TESTDATA_VALUE_SHIFT 0 /**< Shift value for TRNG_VALUE */ #define _TRNG_TESTDATA_VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for TRNG_VALUE */ #define _TRNG_TESTDATA_VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_TESTDATA */ #define TRNG_TESTDATA_VALUE_DEFAULT (_TRNG_TESTDATA_VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_TESTDATA */ /* Bit fields for TRNG STATUS */ #define _TRNG_STATUS_RESETVALUE 0x00000000UL /**< Default value for TRNG_STATUS */ #define _TRNG_STATUS_MASK 0x000003F1UL /**< Mask for TRNG_STATUS */ #define TRNG_STATUS_TESTDATABUSY (0x1UL << 0) /**< Test Data Busy */ #define _TRNG_STATUS_TESTDATABUSY_SHIFT 0 /**< Shift value for TRNG_TESTDATABUSY */ #define _TRNG_STATUS_TESTDATABUSY_MASK 0x1UL /**< Bit mask for TRNG_TESTDATABUSY */ #define _TRNG_STATUS_TESTDATABUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_STATUS */ #define _TRNG_STATUS_TESTDATABUSY_IDLE 0x00000000UL /**< Mode IDLE for TRNG_STATUS */ #define _TRNG_STATUS_TESTDATABUSY_BUSY 0x00000001UL /**< Mode BUSY for TRNG_STATUS */ #define TRNG_STATUS_TESTDATABUSY_DEFAULT (_TRNG_STATUS_TESTDATABUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_STATUS */ #define TRNG_STATUS_TESTDATABUSY_IDLE (_TRNG_STATUS_TESTDATABUSY_IDLE << 0) /**< Shifted mode IDLE for TRNG_STATUS */ #define TRNG_STATUS_TESTDATABUSY_BUSY (_TRNG_STATUS_TESTDATABUSY_BUSY << 0) /**< Shifted mode BUSY for TRNG_STATUS */ #define TRNG_STATUS_REPCOUNTIF (0x1UL << 4) /**< Repetition Count Test Interrupt Status */ #define _TRNG_STATUS_REPCOUNTIF_SHIFT 4 /**< Shift value for TRNG_REPCOUNTIF */ #define _TRNG_STATUS_REPCOUNTIF_MASK 0x10UL /**< Bit mask for TRNG_REPCOUNTIF */ #define _TRNG_STATUS_REPCOUNTIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_STATUS */ #define TRNG_STATUS_REPCOUNTIF_DEFAULT (_TRNG_STATUS_REPCOUNTIF_DEFAULT << 4) /**< Shifted mode DEFAULT for TRNG_STATUS */ #define TRNG_STATUS_APT64IF (0x1UL << 5) /**< Adaptive Proportion test failure (64-sample window) interrupt status */ #define _TRNG_STATUS_APT64IF_SHIFT 5 /**< Shift value for TRNG_APT64IF */ #define _TRNG_STATUS_APT64IF_MASK 0x20UL /**< Bit mask for TRNG_APT64IF */ #define _TRNG_STATUS_APT64IF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_STATUS */ #define TRNG_STATUS_APT64IF_DEFAULT (_TRNG_STATUS_APT64IF_DEFAULT << 5) /**< Shifted mode DEFAULT for TRNG_STATUS */ #define TRNG_STATUS_APT4096IF (0x1UL << 6) /**< Adaptive Proportion test failure (4096-sample window) interrupt status */ #define _TRNG_STATUS_APT4096IF_SHIFT 6 /**< Shift value for TRNG_APT4096IF */ #define _TRNG_STATUS_APT4096IF_MASK 0x40UL /**< Bit mask for TRNG_APT4096IF */ #define _TRNG_STATUS_APT4096IF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_STATUS */ #define TRNG_STATUS_APT4096IF_DEFAULT (_TRNG_STATUS_APT4096IF_DEFAULT << 6) /**< Shifted mode DEFAULT for TRNG_STATUS */ #define TRNG_STATUS_FULLIF (0x1UL << 7) /**< FIFO Full Interrupt Status */ #define _TRNG_STATUS_FULLIF_SHIFT 7 /**< Shift value for TRNG_FULLIF */ #define _TRNG_STATUS_FULLIF_MASK 0x80UL /**< Bit mask for TRNG_FULLIF */ #define _TRNG_STATUS_FULLIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_STATUS */ #define TRNG_STATUS_FULLIF_DEFAULT (_TRNG_STATUS_FULLIF_DEFAULT << 7) /**< Shifted mode DEFAULT for TRNG_STATUS */ #define TRNG_STATUS_PREIF (0x1UL << 8) /**< AIS31 Preliminary Noise Alarm interrupt status */ #define _TRNG_STATUS_PREIF_SHIFT 8 /**< Shift value for TRNG_PREIF */ #define _TRNG_STATUS_PREIF_MASK 0x100UL /**< Bit mask for TRNG_PREIF */ #define _TRNG_STATUS_PREIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_STATUS */ #define TRNG_STATUS_PREIF_DEFAULT (_TRNG_STATUS_PREIF_DEFAULT << 8) /**< Shifted mode DEFAULT for TRNG_STATUS */ #define TRNG_STATUS_ALMIF (0x1UL << 9) /**< AIS31 Noise Alarm interrupt status */ #define _TRNG_STATUS_ALMIF_SHIFT 9 /**< Shift value for TRNG_ALMIF */ #define _TRNG_STATUS_ALMIF_MASK 0x200UL /**< Bit mask for TRNG_ALMIF */ #define _TRNG_STATUS_ALMIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_STATUS */ #define TRNG_STATUS_ALMIF_DEFAULT (_TRNG_STATUS_ALMIF_DEFAULT << 9) /**< Shifted mode DEFAULT for TRNG_STATUS */ /* Bit fields for TRNG INITWAITVAL */ #define _TRNG_INITWAITVAL_RESETVALUE 0x000000FFUL /**< Default value for TRNG_INITWAITVAL */ #define _TRNG_INITWAITVAL_MASK 0x000000FFUL /**< Mask for TRNG_INITWAITVAL */ #define _TRNG_INITWAITVAL_VALUE_SHIFT 0 /**< Shift value for TRNG_VALUE */ #define _TRNG_INITWAITVAL_VALUE_MASK 0xFFUL /**< Bit mask for TRNG_VALUE */ #define _TRNG_INITWAITVAL_VALUE_DEFAULT 0x000000FFUL /**< Mode DEFAULT for TRNG_INITWAITVAL */ #define TRNG_INITWAITVAL_VALUE_DEFAULT (_TRNG_INITWAITVAL_VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_INITWAITVAL */ /* Bit fields for TRNG FIFO */ #define _TRNG_FIFO_RESETVALUE 0x00000000UL /**< Default value for TRNG_FIFO */ #define _TRNG_FIFO_MASK 0xFFFFFFFFUL /**< Mask for TRNG_FIFO */ #define _TRNG_FIFO_VALUE_SHIFT 0 /**< Shift value for TRNG_VALUE */ #define _TRNG_FIFO_VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for TRNG_VALUE */ #define _TRNG_FIFO_VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_FIFO */ #define TRNG_FIFO_VALUE_DEFAULT (_TRNG_FIFO_VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_FIFO */ /** @} */ /** @} End of group EFR32MG12P_TRNG */ /** @} End of group Parts */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_usart.h.
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/***************************************************************************//** * @file * @brief EFR32MG12P_USART register and bit field definitions * @version 5.7.0 ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * SPDX-License-Identifier: Zlib * * The licensor of this software is Silicon Laboratories Inc. * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be * appreciated but is not required. * 2. Altered source versions must be plainly marked as such, and must not be * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * ******************************************************************************/ #if defined(__ICCARM__) #pragma system_include /* Treat file as system include file. */ #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang system_header /* Treat file as system include file. */ #endif /***************************************************************************//** * @addtogroup Parts * @{ ******************************************************************************/ /***************************************************************************//** * @defgroup EFR32MG12P_USART USART * @{ * @brief EFR32MG12P_USART Register Declaration ******************************************************************************/ /** USART Register Declaration */ typedef struct { __IOM uint32_t CTRL; /**< Control Register */ __IOM uint32_t FRAME; /**< USART Frame Format Register */ __IOM uint32_t TRIGCTRL; /**< USART Trigger Control Register */ __IOM uint32_t CMD; /**< Command Register */ __IM uint32_t STATUS; /**< USART Status Register */ __IOM uint32_t CLKDIV; /**< Clock Control Register */ __IM uint32_t RXDATAX; /**< RX Buffer Data Extended Register */ __IM uint32_t RXDATA; /**< RX Buffer Data Register */ __IM uint32_t RXDOUBLEX; /**< RX Buffer Double Data Extended Register */ __IM uint32_t RXDOUBLE; /**< RX FIFO Double Data Register */ __IM uint32_t RXDATAXP; /**< RX Buffer Data Extended Peek Register */ __IM uint32_t RXDOUBLEXP; /**< RX Buffer Double Data Extended Peek Register */ __IOM uint32_t TXDATAX; /**< TX Buffer Data Extended Register */ __IOM uint32_t TXDATA; /**< TX Buffer Data Register */ __IOM uint32_t TXDOUBLEX; /**< TX Buffer Double Data Extended Register */ __IOM uint32_t TXDOUBLE; /**< TX Buffer Double Data Register */ __IM uint32_t IF; /**< Interrupt Flag Register */ __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ __IOM uint32_t IEN; /**< Interrupt Enable Register */ __IOM uint32_t IRCTRL; /**< IrDA Control Register */ uint32_t RESERVED0[1U]; /**< Reserved for future use **/ __IOM uint32_t INPUT; /**< USART Input Register */ __IOM uint32_t I2SCTRL; /**< I2S Control Register */ __IOM uint32_t TIMING; /**< Timing Register */ __IOM uint32_t CTRLX; /**< Control Register Extended */ __IOM uint32_t TIMECMP0; /**< Used to Generate Interrupts and Various Delays */ __IOM uint32_t TIMECMP1; /**< Used to Generate Interrupts and Various Delays */ __IOM uint32_t TIMECMP2; /**< Used to Generate Interrupts and Various Delays */ __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ __IOM uint32_t ROUTELOC1; /**< I/O Routing Location Register */ } USART_TypeDef; /** @} */ /***************************************************************************//** * @addtogroup EFR32MG12P_USART * @{ * @defgroup EFR32MG12P_USART_BitFields USART Bit Fields * @{ ******************************************************************************/ /* Bit fields for USART CTRL */ #define _USART_CTRL_RESETVALUE 0x00000000UL /**< Default value for USART_CTRL */ #define _USART_CTRL_MASK 0xF3FFFF7FUL /**< Mask for USART_CTRL */ #define USART_CTRL_SYNC (0x1UL << 0) /**< USART Synchronous Mode */ #define _USART_CTRL_SYNC_SHIFT 0 /**< Shift value for USART_SYNC */ #define _USART_CTRL_SYNC_MASK 0x1UL /**< Bit mask for USART_SYNC */ #define _USART_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ #define USART_CTRL_SYNC_DEFAULT (_USART_CTRL_SYNC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_CTRL */ #define USART_CTRL_LOOPBK (0x1UL << 1) /**< Loopback Enable */ #define _USART_CTRL_LOOPBK_SHIFT 1 /**< Shift value for USART_LOOPBK */ #define _USART_CTRL_LOOPBK_MASK 0x2UL /**< Bit mask for USART_LOOPBK */ #define _USART_CTRL_LOOPBK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ #define USART_CTRL_LOOPBK_DEFAULT (_USART_CTRL_LOOPBK_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_CTRL */ #define USART_CTRL_CCEN (0x1UL << 2) /**< Collision Check Enable */ #define _USART_CTRL_CCEN_SHIFT 2 /**< Shift value for USART_CCEN */ #define _USART_CTRL_CCEN_MASK 0x4UL /**< Bit mask for USART_CCEN */ #define _USART_CTRL_CCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ #define USART_CTRL_CCEN_DEFAULT (_USART_CTRL_CCEN_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_CTRL */ #define USART_CTRL_MPM (0x1UL << 3) /**< Multi-Processor Mode */ #define _USART_CTRL_MPM_SHIFT 3 /**< Shift value for USART_MPM */ #define _USART_CTRL_MPM_MASK 0x8UL /**< Bit mask for USART_MPM */ #define _USART_CTRL_MPM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ #define USART_CTRL_MPM_DEFAULT (_USART_CTRL_MPM_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_CTRL */ #define USART_CTRL_MPAB (0x1UL << 4) /**< Multi-Processor Address-Bit */ #define _USART_CTRL_MPAB_SHIFT 4 /**< Shift value for USART_MPAB */ #define _USART_CTRL_MPAB_MASK 0x10UL /**< Bit mask for USART_MPAB */ #define _USART_CTRL_MPAB_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ #define USART_CTRL_MPAB_DEFAULT (_USART_CTRL_MPAB_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_CTRL */ #define _USART_CTRL_OVS_SHIFT 5 /**< Shift value for USART_OVS */ #define _USART_CTRL_OVS_MASK 0x60UL /**< Bit mask for USART_OVS */ #define _USART_CTRL_OVS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ #define _USART_CTRL_OVS_X16 0x00000000UL /**< Mode X16 for USART_CTRL */ #define _USART_CTRL_OVS_X8 0x00000001UL /**< Mode X8 for USART_CTRL */ #define _USART_CTRL_OVS_X6 0x00000002UL /**< Mode X6 for USART_CTRL */ #define _USART_CTRL_OVS_X4 0x00000003UL /**< Mode X4 for USART_CTRL */ #define USART_CTRL_OVS_DEFAULT (_USART_CTRL_OVS_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_CTRL */ #define USART_CTRL_OVS_X16 (_USART_CTRL_OVS_X16 << 5) /**< Shifted mode X16 for USART_CTRL */ #define USART_CTRL_OVS_X8 (_USART_CTRL_OVS_X8 << 5) /**< Shifted mode X8 for USART_CTRL */ #define USART_CTRL_OVS_X6 (_USART_CTRL_OVS_X6 << 5) /**< Shifted mode X6 for USART_CTRL */ #define USART_CTRL_OVS_X4 (_USART_CTRL_OVS_X4 << 5) /**< Shifted mode X4 for USART_CTRL */ #define USART_CTRL_CLKPOL (0x1UL << 8) /**< Clock Polarity */ #define _USART_CTRL_CLKPOL_SHIFT 8 /**< Shift value for USART_CLKPOL */ #define _USART_CTRL_CLKPOL_MASK 0x100UL /**< Bit mask for USART_CLKPOL */ #define _USART_CTRL_CLKPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ #define _USART_CTRL_CLKPOL_IDLELOW 0x00000000UL /**< Mode IDLELOW for USART_CTRL */ #define _USART_CTRL_CLKPOL_IDLEHIGH 0x00000001UL /**< Mode IDLEHIGH for USART_CTRL */ #define USART_CTRL_CLKPOL_DEFAULT (_USART_CTRL_CLKPOL_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_CTRL */ #define USART_CTRL_CLKPOL_IDLELOW (_USART_CTRL_CLKPOL_IDLELOW << 8) /**< Shifted mode IDLELOW for USART_CTRL */ #define USART_CTRL_CLKPOL_IDLEHIGH (_USART_CTRL_CLKPOL_IDLEHIGH << 8) /**< Shifted mode IDLEHIGH for USART_CTRL */ #define USART_CTRL_CLKPHA (0x1UL << 9) /**< Clock Edge for Setup/Sample */ #define _USART_CTRL_CLKPHA_SHIFT 9 /**< Shift value for USART_CLKPHA */ #define _USART_CTRL_CLKPHA_MASK 0x200UL /**< Bit mask for USART_CLKPHA */ #define _USART_CTRL_CLKPHA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ #define _USART_CTRL_CLKPHA_SAMPLELEADING 0x00000000UL /**< Mode SAMPLELEADING for USART_CTRL */ #define _USART_CTRL_CLKPHA_SAMPLETRAILING 0x00000001UL /**< Mode SAMPLETRAILING for USART_CTRL */ #define USART_CTRL_CLKPHA_DEFAULT (_USART_CTRL_CLKPHA_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_CTRL */ #define USART_CTRL_CLKPHA_SAMPLELEADING (_USART_CTRL_CLKPHA_SAMPLELEADING << 9) /**< Shifted mode SAMPLELEADING for USART_CTRL */ #define USART_CTRL_CLKPHA_SAMPLETRAILING (_USART_CTRL_CLKPHA_SAMPLETRAILING << 9) /**< Shifted mode SAMPLETRAILING for USART_CTRL */ #define USART_CTRL_MSBF (0x1UL << 10) /**< Most Significant Bit First */ #define _USART_CTRL_MSBF_SHIFT 10 /**< Shift value for USART_MSBF */ #define _USART_CTRL_MSBF_MASK 0x400UL /**< Bit mask for USART_MSBF */ #define _USART_CTRL_MSBF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ #define USART_CTRL_MSBF_DEFAULT (_USART_CTRL_MSBF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_CTRL */ #define USART_CTRL_CSMA (0x1UL << 11) /**< Action on Slave-Select in Master Mode */ #define _USART_CTRL_CSMA_SHIFT 11 /**< Shift value for USART_CSMA */ #define _USART_CTRL_CSMA_MASK 0x800UL /**< Bit mask for USART_CSMA */ #define _USART_CTRL_CSMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ #define _USART_CTRL_CSMA_NOACTION 0x00000000UL /**< Mode NOACTION for USART_CTRL */ #define _USART_CTRL_CSMA_GOTOSLAVEMODE 0x00000001UL /**< Mode GOTOSLAVEMODE for USART_CTRL */ #define USART_CTRL_CSMA_DEFAULT (_USART_CTRL_CSMA_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_CTRL */ #define USART_CTRL_CSMA_NOACTION (_USART_CTRL_CSMA_NOACTION << 11) /**< Shifted mode NOACTION for USART_CTRL */ #define USART_CTRL_CSMA_GOTOSLAVEMODE (_USART_CTRL_CSMA_GOTOSLAVEMODE << 11) /**< Shifted mode GOTOSLAVEMODE for USART_CTRL */ #define USART_CTRL_TXBIL (0x1UL << 12) /**< TX Buffer Interrupt Level */ #define _USART_CTRL_TXBIL_SHIFT 12 /**< Shift value for USART_TXBIL */ #define _USART_CTRL_TXBIL_MASK 0x1000UL /**< Bit mask for USART_TXBIL */ #define _USART_CTRL_TXBIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ #define _USART_CTRL_TXBIL_EMPTY 0x00000000UL /**< Mode EMPTY for USART_CTRL */ #define _USART_CTRL_TXBIL_HALFFULL 0x00000001UL /**< Mode HALFFULL for USART_CTRL */ #define USART_CTRL_TXBIL_DEFAULT (_USART_CTRL_TXBIL_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_CTRL */ #define USART_CTRL_TXBIL_EMPTY (_USART_CTRL_TXBIL_EMPTY << 12) /**< Shifted mode EMPTY for USART_CTRL */ #define USART_CTRL_TXBIL_HALFFULL (_USART_CTRL_TXBIL_HALFFULL << 12) /**< Shifted mode HALFFULL for USART_CTRL */ #define USART_CTRL_RXINV (0x1UL << 13) /**< Receiver Input Invert */ #define _USART_CTRL_RXINV_SHIFT 13 /**< Shift value for USART_RXINV */ #define _USART_CTRL_RXINV_MASK 0x2000UL /**< Bit mask for USART_RXINV */ #define _USART_CTRL_RXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ #define USART_CTRL_RXINV_DEFAULT (_USART_CTRL_RXINV_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_CTRL */ #define USART_CTRL_TXINV (0x1UL << 14) /**< Transmitter Output Invert */ #define _USART_CTRL_TXINV_SHIFT 14 /**< Shift value for USART_TXINV */ #define _USART_CTRL_TXINV_MASK 0x4000UL /**< Bit mask for USART_TXINV */ #define _USART_CTRL_TXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ #define USART_CTRL_TXINV_DEFAULT (_USART_CTRL_TXINV_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_CTRL */ #define USART_CTRL_CSINV (0x1UL << 15) /**< Chip Select Invert */ #define _USART_CTRL_CSINV_SHIFT 15 /**< Shift value for USART_CSINV */ #define _USART_CTRL_CSINV_MASK 0x8000UL /**< Bit mask for USART_CSINV */ #define _USART_CTRL_CSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ #define USART_CTRL_CSINV_DEFAULT (_USART_CTRL_CSINV_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_CTRL */ #define USART_CTRL_AUTOCS (0x1UL << 16) /**< Automatic Chip Select */ #define _USART_CTRL_AUTOCS_SHIFT 16 /**< Shift value for USART_AUTOCS */ #define _USART_CTRL_AUTOCS_MASK 0x10000UL /**< Bit mask for USART_AUTOCS */ #define _USART_CTRL_AUTOCS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ #define USART_CTRL_AUTOCS_DEFAULT (_USART_CTRL_AUTOCS_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_CTRL */ #define USART_CTRL_AUTOTRI (0x1UL << 17) /**< Automatic TX Tristate */ #define _USART_CTRL_AUTOTRI_SHIFT 17 /**< Shift value for USART_AUTOTRI */ #define _USART_CTRL_AUTOTRI_MASK 0x20000UL /**< Bit mask for USART_AUTOTRI */ #define _USART_CTRL_AUTOTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ #define USART_CTRL_AUTOTRI_DEFAULT (_USART_CTRL_AUTOTRI_DEFAULT << 17) /**< Shifted mode DEFAULT for USART_CTRL */ #define USART_CTRL_SCMODE (0x1UL << 18) /**< SmartCard Mode */ #define _USART_CTRL_SCMODE_SHIFT 18 /**< Shift value for USART_SCMODE */ #define _USART_CTRL_SCMODE_MASK 0x40000UL /**< Bit mask for USART_SCMODE */ #define _USART_CTRL_SCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ #define USART_CTRL_SCMODE_DEFAULT (_USART_CTRL_SCMODE_DEFAULT << 18) /**< Shifted mode DEFAULT for USART_CTRL */ #define USART_CTRL_SCRETRANS (0x1UL << 19) /**< SmartCard Retransmit */ #define _USART_CTRL_SCRETRANS_SHIFT 19 /**< Shift value for USART_SCRETRANS */ #define _USART_CTRL_SCRETRANS_MASK 0x80000UL /**< Bit mask for USART_SCRETRANS */ #define _USART_CTRL_SCRETRANS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ #define USART_CTRL_SCRETRANS_DEFAULT (_USART_CTRL_SCRETRANS_DEFAULT << 19) /**< Shifted mode DEFAULT for USART_CTRL */ #define USART_CTRL_SKIPPERRF (0x1UL << 20) /**< Skip Parity Error Frames */ #define _USART_CTRL_SKIPPERRF_SHIFT 20 /**< Shift value for USART_SKIPPERRF */ #define _USART_CTRL_SKIPPERRF_MASK 0x100000UL /**< Bit mask for USART_SKIPPERRF */ #define _USART_CTRL_SKIPPERRF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ #define USART_CTRL_SKIPPERRF_DEFAULT (_USART_CTRL_SKIPPERRF_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_CTRL */ #define USART_CTRL_BIT8DV (0x1UL << 21) /**< Bit 8 Default Value */ #define _USART_CTRL_BIT8DV_SHIFT 21 /**< Shift value for USART_BIT8DV */ #define _USART_CTRL_BIT8DV_MASK 0x200000UL /**< Bit mask for USART_BIT8DV */ #define _USART_CTRL_BIT8DV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ #define USART_CTRL_BIT8DV_DEFAULT (_USART_CTRL_BIT8DV_DEFAULT << 21) /**< Shifted mode DEFAULT for USART_CTRL */ #define USART_CTRL_ERRSDMA (0x1UL << 22) /**< Halt DMA on Error */ #define _USART_CTRL_ERRSDMA_SHIFT 22 /**< Shift value for USART_ERRSDMA */ #define _USART_CTRL_ERRSDMA_MASK 0x400000UL /**< Bit mask for USART_ERRSDMA */ #define _USART_CTRL_ERRSDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ #define USART_CTRL_ERRSDMA_DEFAULT (_USART_CTRL_ERRSDMA_DEFAULT << 22) /**< Shifted mode DEFAULT for USART_CTRL */ #define USART_CTRL_ERRSRX (0x1UL << 23) /**< Disable RX on Error */ #define _USART_CTRL_ERRSRX_SHIFT 23 /**< Shift value for USART_ERRSRX */ #define _USART_CTRL_ERRSRX_MASK 0x800000UL /**< Bit mask for USART_ERRSRX */ #define _USART_CTRL_ERRSRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ #define USART_CTRL_ERRSRX_DEFAULT (_USART_CTRL_ERRSRX_DEFAULT << 23) /**< Shifted mode DEFAULT for USART_CTRL */ #define USART_CTRL_ERRSTX (0x1UL << 24) /**< Disable TX on Error */ #define _USART_CTRL_ERRSTX_SHIFT 24 /**< Shift value for USART_ERRSTX */ #define _USART_CTRL_ERRSTX_MASK 0x1000000UL /**< Bit mask for USART_ERRSTX */ #define _USART_CTRL_ERRSTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ #define USART_CTRL_ERRSTX_DEFAULT (_USART_CTRL_ERRSTX_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_CTRL */ #define USART_CTRL_SSSEARLY (0x1UL << 25) /**< Synchronous Slave Setup Early */ #define _USART_CTRL_SSSEARLY_SHIFT 25 /**< Shift value for USART_SSSEARLY */ #define _USART_CTRL_SSSEARLY_MASK 0x2000000UL /**< Bit mask for USART_SSSEARLY */ #define _USART_CTRL_SSSEARLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ #define USART_CTRL_SSSEARLY_DEFAULT (_USART_CTRL_SSSEARLY_DEFAULT << 25) /**< Shifted mode DEFAULT for USART_CTRL */ #define USART_CTRL_BYTESWAP (0x1UL << 28) /**< Byteswap in Double Accesses */ #define _USART_CTRL_BYTESWAP_SHIFT 28 /**< Shift value for USART_BYTESWAP */ #define _USART_CTRL_BYTESWAP_MASK 0x10000000UL /**< Bit mask for USART_BYTESWAP */ #define _USART_CTRL_BYTESWAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ #define USART_CTRL_BYTESWAP_DEFAULT (_USART_CTRL_BYTESWAP_DEFAULT << 28) /**< Shifted mode DEFAULT for USART_CTRL */ #define USART_CTRL_AUTOTX (0x1UL << 29) /**< Always Transmit When RX Not Full */ #define _USART_CTRL_AUTOTX_SHIFT 29 /**< Shift value for USART_AUTOTX */ #define _USART_CTRL_AUTOTX_MASK 0x20000000UL /**< Bit mask for USART_AUTOTX */ #define _USART_CTRL_AUTOTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ #define USART_CTRL_AUTOTX_DEFAULT (_USART_CTRL_AUTOTX_DEFAULT << 29) /**< Shifted mode DEFAULT for USART_CTRL */ #define USART_CTRL_MVDIS (0x1UL << 30) /**< Majority Vote Disable */ #define _USART_CTRL_MVDIS_SHIFT 30 /**< Shift value for USART_MVDIS */ #define _USART_CTRL_MVDIS_MASK 0x40000000UL /**< Bit mask for USART_MVDIS */ #define _USART_CTRL_MVDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ #define USART_CTRL_MVDIS_DEFAULT (_USART_CTRL_MVDIS_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_CTRL */ #define USART_CTRL_SMSDELAY (0x1UL << 31) /**< Synchronous Master Sample Delay */ #define _USART_CTRL_SMSDELAY_SHIFT 31 /**< Shift value for USART_SMSDELAY */ #define _USART_CTRL_SMSDELAY_MASK 0x80000000UL /**< Bit mask for USART_SMSDELAY */ #define _USART_CTRL_SMSDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ #define USART_CTRL_SMSDELAY_DEFAULT (_USART_CTRL_SMSDELAY_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_CTRL */ /* Bit fields for USART FRAME */ #define _USART_FRAME_RESETVALUE 0x00001005UL /**< Default value for USART_FRAME */ #define _USART_FRAME_MASK 0x0000330FUL /**< Mask for USART_FRAME */ #define _USART_FRAME_DATABITS_SHIFT 0 /**< Shift value for USART_DATABITS */ #define _USART_FRAME_DATABITS_MASK 0xFUL /**< Bit mask for USART_DATABITS */ #define _USART_FRAME_DATABITS_FOUR 0x00000001UL /**< Mode FOUR for USART_FRAME */ #define _USART_FRAME_DATABITS_FIVE 0x00000002UL /**< Mode FIVE for USART_FRAME */ #define _USART_FRAME_DATABITS_SIX 0x00000003UL /**< Mode SIX for USART_FRAME */ #define _USART_FRAME_DATABITS_SEVEN 0x00000004UL /**< Mode SEVEN for USART_FRAME */ #define _USART_FRAME_DATABITS_DEFAULT 0x00000005UL /**< Mode DEFAULT for USART_FRAME */ #define _USART_FRAME_DATABITS_EIGHT 0x00000005UL /**< Mode EIGHT for USART_FRAME */ #define _USART_FRAME_DATABITS_NINE 0x00000006UL /**< Mode NINE for USART_FRAME */ #define _USART_FRAME_DATABITS_TEN 0x00000007UL /**< Mode TEN for USART_FRAME */ #define _USART_FRAME_DATABITS_ELEVEN 0x00000008UL /**< Mode ELEVEN for USART_FRAME */ #define _USART_FRAME_DATABITS_TWELVE 0x00000009UL /**< Mode TWELVE for USART_FRAME */ #define _USART_FRAME_DATABITS_THIRTEEN 0x0000000AUL /**< Mode THIRTEEN for USART_FRAME */ #define _USART_FRAME_DATABITS_FOURTEEN 0x0000000BUL /**< Mode FOURTEEN for USART_FRAME */ #define _USART_FRAME_DATABITS_FIFTEEN 0x0000000CUL /**< Mode FIFTEEN for USART_FRAME */ #define _USART_FRAME_DATABITS_SIXTEEN 0x0000000DUL /**< Mode SIXTEEN for USART_FRAME */ #define USART_FRAME_DATABITS_FOUR (_USART_FRAME_DATABITS_FOUR << 0) /**< Shifted mode FOUR for USART_FRAME */ #define USART_FRAME_DATABITS_FIVE (_USART_FRAME_DATABITS_FIVE << 0) /**< Shifted mode FIVE for USART_FRAME */ #define USART_FRAME_DATABITS_SIX (_USART_FRAME_DATABITS_SIX << 0) /**< Shifted mode SIX for USART_FRAME */ #define USART_FRAME_DATABITS_SEVEN (_USART_FRAME_DATABITS_SEVEN << 0) /**< Shifted mode SEVEN for USART_FRAME */ #define USART_FRAME_DATABITS_DEFAULT (_USART_FRAME_DATABITS_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_FRAME */ #define USART_FRAME_DATABITS_EIGHT (_USART_FRAME_DATABITS_EIGHT << 0) /**< Shifted mode EIGHT for USART_FRAME */ #define USART_FRAME_DATABITS_NINE (_USART_FRAME_DATABITS_NINE << 0) /**< Shifted mode NINE for USART_FRAME */ #define USART_FRAME_DATABITS_TEN (_USART_FRAME_DATABITS_TEN << 0) /**< Shifted mode TEN for USART_FRAME */ #define USART_FRAME_DATABITS_ELEVEN (_USART_FRAME_DATABITS_ELEVEN << 0) /**< Shifted mode ELEVEN for USART_FRAME */ #define USART_FRAME_DATABITS_TWELVE (_USART_FRAME_DATABITS_TWELVE << 0) /**< Shifted mode TWELVE for USART_FRAME */ #define USART_FRAME_DATABITS_THIRTEEN (_USART_FRAME_DATABITS_THIRTEEN << 0) /**< Shifted mode THIRTEEN for USART_FRAME */ #define USART_FRAME_DATABITS_FOURTEEN (_USART_FRAME_DATABITS_FOURTEEN << 0) /**< Shifted mode FOURTEEN for USART_FRAME */ #define USART_FRAME_DATABITS_FIFTEEN (_USART_FRAME_DATABITS_FIFTEEN << 0) /**< Shifted mode FIFTEEN for USART_FRAME */ #define USART_FRAME_DATABITS_SIXTEEN (_USART_FRAME_DATABITS_SIXTEEN << 0) /**< Shifted mode SIXTEEN for USART_FRAME */ #define _USART_FRAME_PARITY_SHIFT 8 /**< Shift value for USART_PARITY */ #define _USART_FRAME_PARITY_MASK 0x300UL /**< Bit mask for USART_PARITY */ #define _USART_FRAME_PARITY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_FRAME */ #define _USART_FRAME_PARITY_NONE 0x00000000UL /**< Mode NONE for USART_FRAME */ #define _USART_FRAME_PARITY_EVEN 0x00000002UL /**< Mode EVEN for USART_FRAME */ #define _USART_FRAME_PARITY_ODD 0x00000003UL /**< Mode ODD for USART_FRAME */ #define USART_FRAME_PARITY_DEFAULT (_USART_FRAME_PARITY_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_FRAME */ #define USART_FRAME_PARITY_NONE (_USART_FRAME_PARITY_NONE << 8) /**< Shifted mode NONE for USART_FRAME */ #define USART_FRAME_PARITY_EVEN (_USART_FRAME_PARITY_EVEN << 8) /**< Shifted mode EVEN for USART_FRAME */ #define USART_FRAME_PARITY_ODD (_USART_FRAME_PARITY_ODD << 8) /**< Shifted mode ODD for USART_FRAME */ #define _USART_FRAME_STOPBITS_SHIFT 12 /**< Shift value for USART_STOPBITS */ #define _USART_FRAME_STOPBITS_MASK 0x3000UL /**< Bit mask for USART_STOPBITS */ #define _USART_FRAME_STOPBITS_HALF 0x00000000UL /**< Mode HALF for USART_FRAME */ #define _USART_FRAME_STOPBITS_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_FRAME */ #define _USART_FRAME_STOPBITS_ONE 0x00000001UL /**< Mode ONE for USART_FRAME */ #define _USART_FRAME_STOPBITS_ONEANDAHALF 0x00000002UL /**< Mode ONEANDAHALF for USART_FRAME */ #define _USART_FRAME_STOPBITS_TWO 0x00000003UL /**< Mode TWO for USART_FRAME */ #define USART_FRAME_STOPBITS_HALF (_USART_FRAME_STOPBITS_HALF << 12) /**< Shifted mode HALF for USART_FRAME */ #define USART_FRAME_STOPBITS_DEFAULT (_USART_FRAME_STOPBITS_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_FRAME */ #define USART_FRAME_STOPBITS_ONE (_USART_FRAME_STOPBITS_ONE << 12) /**< Shifted mode ONE for USART_FRAME */ #define USART_FRAME_STOPBITS_ONEANDAHALF (_USART_FRAME_STOPBITS_ONEANDAHALF << 12) /**< Shifted mode ONEANDAHALF for USART_FRAME */ #define USART_FRAME_STOPBITS_TWO (_USART_FRAME_STOPBITS_TWO << 12) /**< Shifted mode TWO for USART_FRAME */ /* Bit fields for USART TRIGCTRL */ #define _USART_TRIGCTRL_RESETVALUE 0x00000000UL /**< Default value for USART_TRIGCTRL */ #define _USART_TRIGCTRL_MASK 0x000F1FF0UL /**< Mask for USART_TRIGCTRL */ #define USART_TRIGCTRL_RXTEN (0x1UL << 4) /**< Receive Trigger Enable */ #define _USART_TRIGCTRL_RXTEN_SHIFT 4 /**< Shift value for USART_RXTEN */ #define _USART_TRIGCTRL_RXTEN_MASK 0x10UL /**< Bit mask for USART_RXTEN */ #define _USART_TRIGCTRL_RXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ #define USART_TRIGCTRL_RXTEN_DEFAULT (_USART_TRIGCTRL_RXTEN_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ #define USART_TRIGCTRL_TXTEN (0x1UL << 5) /**< Transmit Trigger Enable */ #define _USART_TRIGCTRL_TXTEN_SHIFT 5 /**< Shift value for USART_TXTEN */ #define _USART_TRIGCTRL_TXTEN_MASK 0x20UL /**< Bit mask for USART_TXTEN */ #define _USART_TRIGCTRL_TXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ #define USART_TRIGCTRL_TXTEN_DEFAULT (_USART_TRIGCTRL_TXTEN_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ #define USART_TRIGCTRL_AUTOTXTEN (0x1UL << 6) /**< AUTOTX Trigger Enable */ #define _USART_TRIGCTRL_AUTOTXTEN_SHIFT 6 /**< Shift value for USART_AUTOTXTEN */ #define _USART_TRIGCTRL_AUTOTXTEN_MASK 0x40UL /**< Bit mask for USART_AUTOTXTEN */ #define _USART_TRIGCTRL_AUTOTXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ #define USART_TRIGCTRL_AUTOTXTEN_DEFAULT (_USART_TRIGCTRL_AUTOTXTEN_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ #define USART_TRIGCTRL_TXARX0EN (0x1UL << 7) /**< Enable Transmit Trigger After RX End of Frame Plus TCMP0VAL */ #define _USART_TRIGCTRL_TXARX0EN_SHIFT 7 /**< Shift value for USART_TXARX0EN */ #define _USART_TRIGCTRL_TXARX0EN_MASK 0x80UL /**< Bit mask for USART_TXARX0EN */ #define _USART_TRIGCTRL_TXARX0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ #define USART_TRIGCTRL_TXARX0EN_DEFAULT (_USART_TRIGCTRL_TXARX0EN_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ #define USART_TRIGCTRL_TXARX1EN (0x1UL << 8) /**< Enable Transmit Trigger After RX End of Frame Plus TCMP1VAL */ #define _USART_TRIGCTRL_TXARX1EN_SHIFT 8 /**< Shift value for USART_TXARX1EN */ #define _USART_TRIGCTRL_TXARX1EN_MASK 0x100UL /**< Bit mask for USART_TXARX1EN */ #define _USART_TRIGCTRL_TXARX1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ #define USART_TRIGCTRL_TXARX1EN_DEFAULT (_USART_TRIGCTRL_TXARX1EN_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ #define USART_TRIGCTRL_TXARX2EN (0x1UL << 9) /**< Enable Transmit Trigger After RX End of Frame Plus TCMP2VAL */ #define _USART_TRIGCTRL_TXARX2EN_SHIFT 9 /**< Shift value for USART_TXARX2EN */ #define _USART_TRIGCTRL_TXARX2EN_MASK 0x200UL /**< Bit mask for USART_TXARX2EN */ #define _USART_TRIGCTRL_TXARX2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ #define USART_TRIGCTRL_TXARX2EN_DEFAULT (_USART_TRIGCTRL_TXARX2EN_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ #define USART_TRIGCTRL_RXATX0EN (0x1UL << 10) /**< Enable Receive Trigger After TX End of Frame Plus TCMPVAL0 Baud-times */ #define _USART_TRIGCTRL_RXATX0EN_SHIFT 10 /**< Shift value for USART_RXATX0EN */ #define _USART_TRIGCTRL_RXATX0EN_MASK 0x400UL /**< Bit mask for USART_RXATX0EN */ #define _USART_TRIGCTRL_RXATX0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ #define USART_TRIGCTRL_RXATX0EN_DEFAULT (_USART_TRIGCTRL_RXATX0EN_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ #define USART_TRIGCTRL_RXATX1EN (0x1UL << 11) /**< Enable Receive Trigger After TX End of Frame Plus TCMPVAL1 Baud-times */ #define _USART_TRIGCTRL_RXATX1EN_SHIFT 11 /**< Shift value for USART_RXATX1EN */ #define _USART_TRIGCTRL_RXATX1EN_MASK 0x800UL /**< Bit mask for USART_RXATX1EN */ #define _USART_TRIGCTRL_RXATX1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ #define USART_TRIGCTRL_RXATX1EN_DEFAULT (_USART_TRIGCTRL_RXATX1EN_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ #define USART_TRIGCTRL_RXATX2EN (0x1UL << 12) /**< Enable Receive Trigger After TX End of Frame Plus TCMPVAL2 Baud-times */ #define _USART_TRIGCTRL_RXATX2EN_SHIFT 12 /**< Shift value for USART_RXATX2EN */ #define _USART_TRIGCTRL_RXATX2EN_MASK 0x1000UL /**< Bit mask for USART_RXATX2EN */ #define _USART_TRIGCTRL_RXATX2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ #define USART_TRIGCTRL_RXATX2EN_DEFAULT (_USART_TRIGCTRL_RXATX2EN_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ #define _USART_TRIGCTRL_TSEL_SHIFT 16 /**< Shift value for USART_TSEL */ #define _USART_TRIGCTRL_TSEL_MASK 0xF0000UL /**< Bit mask for USART_TSEL */ #define _USART_TRIGCTRL_TSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ #define _USART_TRIGCTRL_TSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for USART_TRIGCTRL */ #define _USART_TRIGCTRL_TSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for USART_TRIGCTRL */ #define _USART_TRIGCTRL_TSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for USART_TRIGCTRL */ #define _USART_TRIGCTRL_TSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for USART_TRIGCTRL */ #define _USART_TRIGCTRL_TSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for USART_TRIGCTRL */ #define _USART_TRIGCTRL_TSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for USART_TRIGCTRL */ #define _USART_TRIGCTRL_TSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for USART_TRIGCTRL */ #define _USART_TRIGCTRL_TSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for USART_TRIGCTRL */ #define _USART_TRIGCTRL_TSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for USART_TRIGCTRL */ #define _USART_TRIGCTRL_TSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for USART_TRIGCTRL */ #define _USART_TRIGCTRL_TSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for USART_TRIGCTRL */ #define _USART_TRIGCTRL_TSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for USART_TRIGCTRL */ #define USART_TRIGCTRL_TSEL_DEFAULT (_USART_TRIGCTRL_TSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ #define USART_TRIGCTRL_TSEL_PRSCH0 (_USART_TRIGCTRL_TSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for USART_TRIGCTRL */ #define USART_TRIGCTRL_TSEL_PRSCH1 (_USART_TRIGCTRL_TSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for USART_TRIGCTRL */ #define USART_TRIGCTRL_TSEL_PRSCH2 (_USART_TRIGCTRL_TSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for USART_TRIGCTRL */ #define USART_TRIGCTRL_TSEL_PRSCH3 (_USART_TRIGCTRL_TSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for USART_TRIGCTRL */ #define USART_TRIGCTRL_TSEL_PRSCH4 (_USART_TRIGCTRL_TSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for USART_TRIGCTRL */ #define USART_TRIGCTRL_TSEL_PRSCH5 (_USART_TRIGCTRL_TSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for USART_TRIGCTRL */ #define USART_TRIGCTRL_TSEL_PRSCH6 (_USART_TRIGCTRL_TSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for USART_TRIGCTRL */ #define USART_TRIGCTRL_TSEL_PRSCH7 (_USART_TRIGCTRL_TSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for USART_TRIGCTRL */ #define USART_TRIGCTRL_TSEL_PRSCH8 (_USART_TRIGCTRL_TSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for USART_TRIGCTRL */ #define USART_TRIGCTRL_TSEL_PRSCH9 (_USART_TRIGCTRL_TSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for USART_TRIGCTRL */ #define USART_TRIGCTRL_TSEL_PRSCH10 (_USART_TRIGCTRL_TSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for USART_TRIGCTRL */ #define USART_TRIGCTRL_TSEL_PRSCH11 (_USART_TRIGCTRL_TSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for USART_TRIGCTRL */ /* Bit fields for USART CMD */ #define _USART_CMD_RESETVALUE 0x00000000UL /**< Default value for USART_CMD */ #define _USART_CMD_MASK 0x00000FFFUL /**< Mask for USART_CMD */ #define USART_CMD_RXEN (0x1UL << 0) /**< Receiver Enable */ #define _USART_CMD_RXEN_SHIFT 0 /**< Shift value for USART_RXEN */ #define _USART_CMD_RXEN_MASK 0x1UL /**< Bit mask for USART_RXEN */ #define _USART_CMD_RXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ #define USART_CMD_RXEN_DEFAULT (_USART_CMD_RXEN_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_CMD */ #define USART_CMD_RXDIS (0x1UL << 1) /**< Receiver Disable */ #define _USART_CMD_RXDIS_SHIFT 1 /**< Shift value for USART_RXDIS */ #define _USART_CMD_RXDIS_MASK 0x2UL /**< Bit mask for USART_RXDIS */ #define _USART_CMD_RXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ #define USART_CMD_RXDIS_DEFAULT (_USART_CMD_RXDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_CMD */ #define USART_CMD_TXEN (0x1UL << 2) /**< Transmitter Enable */ #define _USART_CMD_TXEN_SHIFT 2 /**< Shift value for USART_TXEN */ #define _USART_CMD_TXEN_MASK 0x4UL /**< Bit mask for USART_TXEN */ #define _USART_CMD_TXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ #define USART_CMD_TXEN_DEFAULT (_USART_CMD_TXEN_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_CMD */ #define USART_CMD_TXDIS (0x1UL << 3) /**< Transmitter Disable */ #define _USART_CMD_TXDIS_SHIFT 3 /**< Shift value for USART_TXDIS */ #define _USART_CMD_TXDIS_MASK 0x8UL /**< Bit mask for USART_TXDIS */ #define _USART_CMD_TXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ #define USART_CMD_TXDIS_DEFAULT (_USART_CMD_TXDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_CMD */ #define USART_CMD_MASTEREN (0x1UL << 4) /**< Master Enable */ #define _USART_CMD_MASTEREN_SHIFT 4 /**< Shift value for USART_MASTEREN */ #define _USART_CMD_MASTEREN_MASK 0x10UL /**< Bit mask for USART_MASTEREN */ #define _USART_CMD_MASTEREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ #define USART_CMD_MASTEREN_DEFAULT (_USART_CMD_MASTEREN_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_CMD */ #define USART_CMD_MASTERDIS (0x1UL << 5) /**< Master Disable */ #define _USART_CMD_MASTERDIS_SHIFT 5 /**< Shift value for USART_MASTERDIS */ #define _USART_CMD_MASTERDIS_MASK 0x20UL /**< Bit mask for USART_MASTERDIS */ #define _USART_CMD_MASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ #define USART_CMD_MASTERDIS_DEFAULT (_USART_CMD_MASTERDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_CMD */ #define USART_CMD_RXBLOCKEN (0x1UL << 6) /**< Receiver Block Enable */ #define _USART_CMD_RXBLOCKEN_SHIFT 6 /**< Shift value for USART_RXBLOCKEN */ #define _USART_CMD_RXBLOCKEN_MASK 0x40UL /**< Bit mask for USART_RXBLOCKEN */ #define _USART_CMD_RXBLOCKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ #define USART_CMD_RXBLOCKEN_DEFAULT (_USART_CMD_RXBLOCKEN_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_CMD */ #define USART_CMD_RXBLOCKDIS (0x1UL << 7) /**< Receiver Block Disable */ #define _USART_CMD_RXBLOCKDIS_SHIFT 7 /**< Shift value for USART_RXBLOCKDIS */ #define _USART_CMD_RXBLOCKDIS_MASK 0x80UL /**< Bit mask for USART_RXBLOCKDIS */ #define _USART_CMD_RXBLOCKDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ #define USART_CMD_RXBLOCKDIS_DEFAULT (_USART_CMD_RXBLOCKDIS_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_CMD */ #define USART_CMD_TXTRIEN (0x1UL << 8) /**< Transmitter Tristate Enable */ #define _USART_CMD_TXTRIEN_SHIFT 8 /**< Shift value for USART_TXTRIEN */ #define _USART_CMD_TXTRIEN_MASK 0x100UL /**< Bit mask for USART_TXTRIEN */ #define _USART_CMD_TXTRIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ #define USART_CMD_TXTRIEN_DEFAULT (_USART_CMD_TXTRIEN_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_CMD */ #define USART_CMD_TXTRIDIS (0x1UL << 9) /**< Transmitter Tristate Disable */ #define _USART_CMD_TXTRIDIS_SHIFT 9 /**< Shift value for USART_TXTRIDIS */ #define _USART_CMD_TXTRIDIS_MASK 0x200UL /**< Bit mask for USART_TXTRIDIS */ #define _USART_CMD_TXTRIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ #define USART_CMD_TXTRIDIS_DEFAULT (_USART_CMD_TXTRIDIS_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_CMD */ #define USART_CMD_CLEARTX (0x1UL << 10) /**< Clear TX */ #define _USART_CMD_CLEARTX_SHIFT 10 /**< Shift value for USART_CLEARTX */ #define _USART_CMD_CLEARTX_MASK 0x400UL /**< Bit mask for USART_CLEARTX */ #define _USART_CMD_CLEARTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ #define USART_CMD_CLEARTX_DEFAULT (_USART_CMD_CLEARTX_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_CMD */ #define USART_CMD_CLEARRX (0x1UL << 11) /**< Clear RX */ #define _USART_CMD_CLEARRX_SHIFT 11 /**< Shift value for USART_CLEARRX */ #define _USART_CMD_CLEARRX_MASK 0x800UL /**< Bit mask for USART_CLEARRX */ #define _USART_CMD_CLEARRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ #define USART_CMD_CLEARRX_DEFAULT (_USART_CMD_CLEARRX_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_CMD */ /* Bit fields for USART STATUS */ #define _USART_STATUS_RESETVALUE 0x00002040UL /**< Default value for USART_STATUS */ #define _USART_STATUS_MASK 0x00037FFFUL /**< Mask for USART_STATUS */ #define USART_STATUS_RXENS (0x1UL << 0) /**< Receiver Enable Status */ #define _USART_STATUS_RXENS_SHIFT 0 /**< Shift value for USART_RXENS */ #define _USART_STATUS_RXENS_MASK 0x1UL /**< Bit mask for USART_RXENS */ #define _USART_STATUS_RXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ #define USART_STATUS_RXENS_DEFAULT (_USART_STATUS_RXENS_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_STATUS */ #define USART_STATUS_TXENS (0x1UL << 1) /**< Transmitter Enable Status */ #define _USART_STATUS_TXENS_SHIFT 1 /**< Shift value for USART_TXENS */ #define _USART_STATUS_TXENS_MASK 0x2UL /**< Bit mask for USART_TXENS */ #define _USART_STATUS_TXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ #define USART_STATUS_TXENS_DEFAULT (_USART_STATUS_TXENS_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_STATUS */ #define USART_STATUS_MASTER (0x1UL << 2) /**< SPI Master Mode */ #define _USART_STATUS_MASTER_SHIFT 2 /**< Shift value for USART_MASTER */ #define _USART_STATUS_MASTER_MASK 0x4UL /**< Bit mask for USART_MASTER */ #define _USART_STATUS_MASTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ #define USART_STATUS_MASTER_DEFAULT (_USART_STATUS_MASTER_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_STATUS */ #define USART_STATUS_RXBLOCK (0x1UL << 3) /**< Block Incoming Data */ #define _USART_STATUS_RXBLOCK_SHIFT 3 /**< Shift value for USART_RXBLOCK */ #define _USART_STATUS_RXBLOCK_MASK 0x8UL /**< Bit mask for USART_RXBLOCK */ #define _USART_STATUS_RXBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ #define USART_STATUS_RXBLOCK_DEFAULT (_USART_STATUS_RXBLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_STATUS */ #define USART_STATUS_TXTRI (0x1UL << 4) /**< Transmitter Tristated */ #define _USART_STATUS_TXTRI_SHIFT 4 /**< Shift value for USART_TXTRI */ #define _USART_STATUS_TXTRI_MASK 0x10UL /**< Bit mask for USART_TXTRI */ #define _USART_STATUS_TXTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ #define USART_STATUS_TXTRI_DEFAULT (_USART_STATUS_TXTRI_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_STATUS */ #define USART_STATUS_TXC (0x1UL << 5) /**< TX Complete */ #define _USART_STATUS_TXC_SHIFT 5 /**< Shift value for USART_TXC */ #define _USART_STATUS_TXC_MASK 0x20UL /**< Bit mask for USART_TXC */ #define _USART_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ #define USART_STATUS_TXC_DEFAULT (_USART_STATUS_TXC_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_STATUS */ #define USART_STATUS_TXBL (0x1UL << 6) /**< TX Buffer Level */ #define _USART_STATUS_TXBL_SHIFT 6 /**< Shift value for USART_TXBL */ #define _USART_STATUS_TXBL_MASK 0x40UL /**< Bit mask for USART_TXBL */ #define _USART_STATUS_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_STATUS */ #define USART_STATUS_TXBL_DEFAULT (_USART_STATUS_TXBL_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_STATUS */ #define USART_STATUS_RXDATAV (0x1UL << 7) /**< RX Data Valid */ #define _USART_STATUS_RXDATAV_SHIFT 7 /**< Shift value for USART_RXDATAV */ #define _USART_STATUS_RXDATAV_MASK 0x80UL /**< Bit mask for USART_RXDATAV */ #define _USART_STATUS_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ #define USART_STATUS_RXDATAV_DEFAULT (_USART_STATUS_RXDATAV_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_STATUS */ #define USART_STATUS_RXFULL (0x1UL << 8) /**< RX FIFO Full */ #define _USART_STATUS_RXFULL_SHIFT 8 /**< Shift value for USART_RXFULL */ #define _USART_STATUS_RXFULL_MASK 0x100UL /**< Bit mask for USART_RXFULL */ #define _USART_STATUS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ #define USART_STATUS_RXFULL_DEFAULT (_USART_STATUS_RXFULL_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_STATUS */ #define USART_STATUS_TXBDRIGHT (0x1UL << 9) /**< TX Buffer Expects Double Right Data */ #define _USART_STATUS_TXBDRIGHT_SHIFT 9 /**< Shift value for USART_TXBDRIGHT */ #define _USART_STATUS_TXBDRIGHT_MASK 0x200UL /**< Bit mask for USART_TXBDRIGHT */ #define _USART_STATUS_TXBDRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ #define USART_STATUS_TXBDRIGHT_DEFAULT (_USART_STATUS_TXBDRIGHT_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_STATUS */ #define USART_STATUS_TXBSRIGHT (0x1UL << 10) /**< TX Buffer Expects Single Right Data */ #define _USART_STATUS_TXBSRIGHT_SHIFT 10 /**< Shift value for USART_TXBSRIGHT */ #define _USART_STATUS_TXBSRIGHT_MASK 0x400UL /**< Bit mask for USART_TXBSRIGHT */ #define _USART_STATUS_TXBSRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ #define USART_STATUS_TXBSRIGHT_DEFAULT (_USART_STATUS_TXBSRIGHT_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_STATUS */ #define USART_STATUS_RXDATAVRIGHT (0x1UL << 11) /**< RX Data Right */ #define _USART_STATUS_RXDATAVRIGHT_SHIFT 11 /**< Shift value for USART_RXDATAVRIGHT */ #define _USART_STATUS_RXDATAVRIGHT_MASK 0x800UL /**< Bit mask for USART_RXDATAVRIGHT */ #define _USART_STATUS_RXDATAVRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ #define USART_STATUS_RXDATAVRIGHT_DEFAULT (_USART_STATUS_RXDATAVRIGHT_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_STATUS */ #define USART_STATUS_RXFULLRIGHT (0x1UL << 12) /**< RX Full of Right Data */ #define _USART_STATUS_RXFULLRIGHT_SHIFT 12 /**< Shift value for USART_RXFULLRIGHT */ #define _USART_STATUS_RXFULLRIGHT_MASK 0x1000UL /**< Bit mask for USART_RXFULLRIGHT */ #define _USART_STATUS_RXFULLRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ #define USART_STATUS_RXFULLRIGHT_DEFAULT (_USART_STATUS_RXFULLRIGHT_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_STATUS */ #define USART_STATUS_TXIDLE (0x1UL << 13) /**< TX Idle */ #define _USART_STATUS_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */ #define _USART_STATUS_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */ #define _USART_STATUS_TXIDLE_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_STATUS */ #define USART_STATUS_TXIDLE_DEFAULT (_USART_STATUS_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_STATUS */ #define USART_STATUS_TIMERRESTARTED (0x1UL << 14) /**< The USART Timer Restarted Itself */ #define _USART_STATUS_TIMERRESTARTED_SHIFT 14 /**< Shift value for USART_TIMERRESTARTED */ #define _USART_STATUS_TIMERRESTARTED_MASK 0x4000UL /**< Bit mask for USART_TIMERRESTARTED */ #define _USART_STATUS_TIMERRESTARTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ #define USART_STATUS_TIMERRESTARTED_DEFAULT (_USART_STATUS_TIMERRESTARTED_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_STATUS */ #define _USART_STATUS_TXBUFCNT_SHIFT 16 /**< Shift value for USART_TXBUFCNT */ #define _USART_STATUS_TXBUFCNT_MASK 0x30000UL /**< Bit mask for USART_TXBUFCNT */ #define _USART_STATUS_TXBUFCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ #define USART_STATUS_TXBUFCNT_DEFAULT (_USART_STATUS_TXBUFCNT_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_STATUS */ /* Bit fields for USART CLKDIV */ #define _USART_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for USART_CLKDIV */ #define _USART_CLKDIV_MASK 0x807FFFF8UL /**< Mask for USART_CLKDIV */ #define _USART_CLKDIV_DIV_SHIFT 3 /**< Shift value for USART_DIV */ #define _USART_CLKDIV_DIV_MASK 0x7FFFF8UL /**< Bit mask for USART_DIV */ #define _USART_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CLKDIV */ #define USART_CLKDIV_DIV_DEFAULT (_USART_CLKDIV_DIV_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_CLKDIV */ #define USART_CLKDIV_AUTOBAUDEN (0x1UL << 31) /**< AUTOBAUD Detection Enable */ #define _USART_CLKDIV_AUTOBAUDEN_SHIFT 31 /**< Shift value for USART_AUTOBAUDEN */ #define _USART_CLKDIV_AUTOBAUDEN_MASK 0x80000000UL /**< Bit mask for USART_AUTOBAUDEN */ #define _USART_CLKDIV_AUTOBAUDEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CLKDIV */ #define USART_CLKDIV_AUTOBAUDEN_DEFAULT (_USART_CLKDIV_AUTOBAUDEN_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_CLKDIV */ /* Bit fields for USART RXDATAX */ #define _USART_RXDATAX_RESETVALUE 0x00000000UL /**< Default value for USART_RXDATAX */ #define _USART_RXDATAX_MASK 0x0000C1FFUL /**< Mask for USART_RXDATAX */ #define _USART_RXDATAX_RXDATA_SHIFT 0 /**< Shift value for USART_RXDATA */ #define _USART_RXDATAX_RXDATA_MASK 0x1FFUL /**< Bit mask for USART_RXDATA */ #define _USART_RXDATAX_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAX */ #define USART_RXDATAX_RXDATA_DEFAULT (_USART_RXDATAX_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDATAX */ #define USART_RXDATAX_PERR (0x1UL << 14) /**< Data Parity Error */ #define _USART_RXDATAX_PERR_SHIFT 14 /**< Shift value for USART_PERR */ #define _USART_RXDATAX_PERR_MASK 0x4000UL /**< Bit mask for USART_PERR */ #define _USART_RXDATAX_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAX */ #define USART_RXDATAX_PERR_DEFAULT (_USART_RXDATAX_PERR_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDATAX */ #define USART_RXDATAX_FERR (0x1UL << 15) /**< Data Framing Error */ #define _USART_RXDATAX_FERR_SHIFT 15 /**< Shift value for USART_FERR */ #define _USART_RXDATAX_FERR_MASK 0x8000UL /**< Bit mask for USART_FERR */ #define _USART_RXDATAX_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAX */ #define USART_RXDATAX_FERR_DEFAULT (_USART_RXDATAX_FERR_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDATAX */ /* Bit fields for USART RXDATA */ #define _USART_RXDATA_RESETVALUE 0x00000000UL /**< Default value for USART_RXDATA */ #define _USART_RXDATA_MASK 0x000000FFUL /**< Mask for USART_RXDATA */ #define _USART_RXDATA_RXDATA_SHIFT 0 /**< Shift value for USART_RXDATA */ #define _USART_RXDATA_RXDATA_MASK 0xFFUL /**< Bit mask for USART_RXDATA */ #define _USART_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATA */ #define USART_RXDATA_RXDATA_DEFAULT (_USART_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDATA */ /* Bit fields for USART RXDOUBLEX */ #define _USART_RXDOUBLEX_RESETVALUE 0x00000000UL /**< Default value for USART_RXDOUBLEX */ #define _USART_RXDOUBLEX_MASK 0xC1FFC1FFUL /**< Mask for USART_RXDOUBLEX */ #define _USART_RXDOUBLEX_RXDATA0_SHIFT 0 /**< Shift value for USART_RXDATA0 */ #define _USART_RXDOUBLEX_RXDATA0_MASK 0x1FFUL /**< Bit mask for USART_RXDATA0 */ #define _USART_RXDOUBLEX_RXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ #define USART_RXDOUBLEX_RXDATA0_DEFAULT (_USART_RXDOUBLEX_RXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ #define USART_RXDOUBLEX_PERR0 (0x1UL << 14) /**< Data Parity Error 0 */ #define _USART_RXDOUBLEX_PERR0_SHIFT 14 /**< Shift value for USART_PERR0 */ #define _USART_RXDOUBLEX_PERR0_MASK 0x4000UL /**< Bit mask for USART_PERR0 */ #define _USART_RXDOUBLEX_PERR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ #define USART_RXDOUBLEX_PERR0_DEFAULT (_USART_RXDOUBLEX_PERR0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ #define USART_RXDOUBLEX_FERR0 (0x1UL << 15) /**< Data Framing Error 0 */ #define _USART_RXDOUBLEX_FERR0_SHIFT 15 /**< Shift value for USART_FERR0 */ #define _USART_RXDOUBLEX_FERR0_MASK 0x8000UL /**< Bit mask for USART_FERR0 */ #define _USART_RXDOUBLEX_FERR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ #define USART_RXDOUBLEX_FERR0_DEFAULT (_USART_RXDOUBLEX_FERR0_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ #define _USART_RXDOUBLEX_RXDATA1_SHIFT 16 /**< Shift value for USART_RXDATA1 */ #define _USART_RXDOUBLEX_RXDATA1_MASK 0x1FF0000UL /**< Bit mask for USART_RXDATA1 */ #define _USART_RXDOUBLEX_RXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ #define USART_RXDOUBLEX_RXDATA1_DEFAULT (_USART_RXDOUBLEX_RXDATA1_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ #define USART_RXDOUBLEX_PERR1 (0x1UL << 30) /**< Data Parity Error 1 */ #define _USART_RXDOUBLEX_PERR1_SHIFT 30 /**< Shift value for USART_PERR1 */ #define _USART_RXDOUBLEX_PERR1_MASK 0x40000000UL /**< Bit mask for USART_PERR1 */ #define _USART_RXDOUBLEX_PERR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ #define USART_RXDOUBLEX_PERR1_DEFAULT (_USART_RXDOUBLEX_PERR1_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ #define USART_RXDOUBLEX_FERR1 (0x1UL << 31) /**< Data Framing Error 1 */ #define _USART_RXDOUBLEX_FERR1_SHIFT 31 /**< Shift value for USART_FERR1 */ #define _USART_RXDOUBLEX_FERR1_MASK 0x80000000UL /**< Bit mask for USART_FERR1 */ #define _USART_RXDOUBLEX_FERR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ #define USART_RXDOUBLEX_FERR1_DEFAULT (_USART_RXDOUBLEX_FERR1_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ /* Bit fields for USART RXDOUBLE */ #define _USART_RXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for USART_RXDOUBLE */ #define _USART_RXDOUBLE_MASK 0x0000FFFFUL /**< Mask for USART_RXDOUBLE */ #define _USART_RXDOUBLE_RXDATA0_SHIFT 0 /**< Shift value for USART_RXDATA0 */ #define _USART_RXDOUBLE_RXDATA0_MASK 0xFFUL /**< Bit mask for USART_RXDATA0 */ #define _USART_RXDOUBLE_RXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLE */ #define USART_RXDOUBLE_RXDATA0_DEFAULT (_USART_RXDOUBLE_RXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDOUBLE */ #define _USART_RXDOUBLE_RXDATA1_SHIFT 8 /**< Shift value for USART_RXDATA1 */ #define _USART_RXDOUBLE_RXDATA1_MASK 0xFF00UL /**< Bit mask for USART_RXDATA1 */ #define _USART_RXDOUBLE_RXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLE */ #define USART_RXDOUBLE_RXDATA1_DEFAULT (_USART_RXDOUBLE_RXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_RXDOUBLE */ /* Bit fields for USART RXDATAXP */ #define _USART_RXDATAXP_RESETVALUE 0x00000000UL /**< Default value for USART_RXDATAXP */ #define _USART_RXDATAXP_MASK 0x0000C1FFUL /**< Mask for USART_RXDATAXP */ #define _USART_RXDATAXP_RXDATAP_SHIFT 0 /**< Shift value for USART_RXDATAP */ #define _USART_RXDATAXP_RXDATAP_MASK 0x1FFUL /**< Bit mask for USART_RXDATAP */ #define _USART_RXDATAXP_RXDATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAXP */ #define USART_RXDATAXP_RXDATAP_DEFAULT (_USART_RXDATAXP_RXDATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDATAXP */ #define USART_RXDATAXP_PERRP (0x1UL << 14) /**< Data Parity Error Peek */ #define _USART_RXDATAXP_PERRP_SHIFT 14 /**< Shift value for USART_PERRP */ #define _USART_RXDATAXP_PERRP_MASK 0x4000UL /**< Bit mask for USART_PERRP */ #define _USART_RXDATAXP_PERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAXP */ #define USART_RXDATAXP_PERRP_DEFAULT (_USART_RXDATAXP_PERRP_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDATAXP */ #define USART_RXDATAXP_FERRP (0x1UL << 15) /**< Data Framing Error Peek */ #define _USART_RXDATAXP_FERRP_SHIFT 15 /**< Shift value for USART_FERRP */ #define _USART_RXDATAXP_FERRP_MASK 0x8000UL /**< Bit mask for USART_FERRP */ #define _USART_RXDATAXP_FERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAXP */ #define USART_RXDATAXP_FERRP_DEFAULT (_USART_RXDATAXP_FERRP_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDATAXP */ /* Bit fields for USART RXDOUBLEXP */ #define _USART_RXDOUBLEXP_RESETVALUE 0x00000000UL /**< Default value for USART_RXDOUBLEXP */ #define _USART_RXDOUBLEXP_MASK 0xC1FFC1FFUL /**< Mask for USART_RXDOUBLEXP */ #define _USART_RXDOUBLEXP_RXDATAP0_SHIFT 0 /**< Shift value for USART_RXDATAP0 */ #define _USART_RXDOUBLEXP_RXDATAP0_MASK 0x1FFUL /**< Bit mask for USART_RXDATAP0 */ #define _USART_RXDOUBLEXP_RXDATAP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ #define USART_RXDOUBLEXP_RXDATAP0_DEFAULT (_USART_RXDOUBLEXP_RXDATAP0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ #define USART_RXDOUBLEXP_PERRP0 (0x1UL << 14) /**< Data Parity Error 0 Peek */ #define _USART_RXDOUBLEXP_PERRP0_SHIFT 14 /**< Shift value for USART_PERRP0 */ #define _USART_RXDOUBLEXP_PERRP0_MASK 0x4000UL /**< Bit mask for USART_PERRP0 */ #define _USART_RXDOUBLEXP_PERRP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ #define USART_RXDOUBLEXP_PERRP0_DEFAULT (_USART_RXDOUBLEXP_PERRP0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ #define USART_RXDOUBLEXP_FERRP0 (0x1UL << 15) /**< Data Framing Error 0 Peek */ #define _USART_RXDOUBLEXP_FERRP0_SHIFT 15 /**< Shift value for USART_FERRP0 */ #define _USART_RXDOUBLEXP_FERRP0_MASK 0x8000UL /**< Bit mask for USART_FERRP0 */ #define _USART_RXDOUBLEXP_FERRP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ #define USART_RXDOUBLEXP_FERRP0_DEFAULT (_USART_RXDOUBLEXP_FERRP0_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ #define _USART_RXDOUBLEXP_RXDATAP1_SHIFT 16 /**< Shift value for USART_RXDATAP1 */ #define _USART_RXDOUBLEXP_RXDATAP1_MASK 0x1FF0000UL /**< Bit mask for USART_RXDATAP1 */ #define _USART_RXDOUBLEXP_RXDATAP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ #define USART_RXDOUBLEXP_RXDATAP1_DEFAULT (_USART_RXDOUBLEXP_RXDATAP1_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ #define USART_RXDOUBLEXP_PERRP1 (0x1UL << 30) /**< Data Parity Error 1 Peek */ #define _USART_RXDOUBLEXP_PERRP1_SHIFT 30 /**< Shift value for USART_PERRP1 */ #define _USART_RXDOUBLEXP_PERRP1_MASK 0x40000000UL /**< Bit mask for USART_PERRP1 */ #define _USART_RXDOUBLEXP_PERRP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ #define USART_RXDOUBLEXP_PERRP1_DEFAULT (_USART_RXDOUBLEXP_PERRP1_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ #define USART_RXDOUBLEXP_FERRP1 (0x1UL << 31) /**< Data Framing Error 1 Peek */ #define _USART_RXDOUBLEXP_FERRP1_SHIFT 31 /**< Shift value for USART_FERRP1 */ #define _USART_RXDOUBLEXP_FERRP1_MASK 0x80000000UL /**< Bit mask for USART_FERRP1 */ #define _USART_RXDOUBLEXP_FERRP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ #define USART_RXDOUBLEXP_FERRP1_DEFAULT (_USART_RXDOUBLEXP_FERRP1_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ /* Bit fields for USART TXDATAX */ #define _USART_TXDATAX_RESETVALUE 0x00000000UL /**< Default value for USART_TXDATAX */ #define _USART_TXDATAX_MASK 0x0000F9FFUL /**< Mask for USART_TXDATAX */ #define _USART_TXDATAX_TXDATAX_SHIFT 0 /**< Shift value for USART_TXDATAX */ #define _USART_TXDATAX_TXDATAX_MASK 0x1FFUL /**< Bit mask for USART_TXDATAX */ #define _USART_TXDATAX_TXDATAX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ #define USART_TXDATAX_TXDATAX_DEFAULT (_USART_TXDATAX_TXDATAX_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDATAX */ #define USART_TXDATAX_UBRXAT (0x1UL << 11) /**< Unblock RX After Transmission */ #define _USART_TXDATAX_UBRXAT_SHIFT 11 /**< Shift value for USART_UBRXAT */ #define _USART_TXDATAX_UBRXAT_MASK 0x800UL /**< Bit mask for USART_UBRXAT */ #define _USART_TXDATAX_UBRXAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ #define USART_TXDATAX_UBRXAT_DEFAULT (_USART_TXDATAX_UBRXAT_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_TXDATAX */ #define USART_TXDATAX_TXTRIAT (0x1UL << 12) /**< Set TXTRI After Transmission */ #define _USART_TXDATAX_TXTRIAT_SHIFT 12 /**< Shift value for USART_TXTRIAT */ #define _USART_TXDATAX_TXTRIAT_MASK 0x1000UL /**< Bit mask for USART_TXTRIAT */ #define _USART_TXDATAX_TXTRIAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ #define USART_TXDATAX_TXTRIAT_DEFAULT (_USART_TXDATAX_TXTRIAT_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_TXDATAX */ #define USART_TXDATAX_TXBREAK (0x1UL << 13) /**< Transmit Data as Break */ #define _USART_TXDATAX_TXBREAK_SHIFT 13 /**< Shift value for USART_TXBREAK */ #define _USART_TXDATAX_TXBREAK_MASK 0x2000UL /**< Bit mask for USART_TXBREAK */ #define _USART_TXDATAX_TXBREAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ #define USART_TXDATAX_TXBREAK_DEFAULT (_USART_TXDATAX_TXBREAK_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_TXDATAX */ #define USART_TXDATAX_TXDISAT (0x1UL << 14) /**< Clear TXEN After Transmission */ #define _USART_TXDATAX_TXDISAT_SHIFT 14 /**< Shift value for USART_TXDISAT */ #define _USART_TXDATAX_TXDISAT_MASK 0x4000UL /**< Bit mask for USART_TXDISAT */ #define _USART_TXDATAX_TXDISAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ #define USART_TXDATAX_TXDISAT_DEFAULT (_USART_TXDATAX_TXDISAT_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_TXDATAX */ #define USART_TXDATAX_RXENAT (0x1UL << 15) /**< Enable RX After Transmission */ #define _USART_TXDATAX_RXENAT_SHIFT 15 /**< Shift value for USART_RXENAT */ #define _USART_TXDATAX_RXENAT_MASK 0x8000UL /**< Bit mask for USART_RXENAT */ #define _USART_TXDATAX_RXENAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ #define USART_TXDATAX_RXENAT_DEFAULT (_USART_TXDATAX_RXENAT_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_TXDATAX */ /* Bit fields for USART TXDATA */ #define _USART_TXDATA_RESETVALUE 0x00000000UL /**< Default value for USART_TXDATA */ #define _USART_TXDATA_MASK 0x000000FFUL /**< Mask for USART_TXDATA */ #define _USART_TXDATA_TXDATA_SHIFT 0 /**< Shift value for USART_TXDATA */ #define _USART_TXDATA_TXDATA_MASK 0xFFUL /**< Bit mask for USART_TXDATA */ #define _USART_TXDATA_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATA */ #define USART_TXDATA_TXDATA_DEFAULT (_USART_TXDATA_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDATA */ /* Bit fields for USART TXDOUBLEX */ #define _USART_TXDOUBLEX_RESETVALUE 0x00000000UL /**< Default value for USART_TXDOUBLEX */ #define _USART_TXDOUBLEX_MASK 0xF9FFF9FFUL /**< Mask for USART_TXDOUBLEX */ #define _USART_TXDOUBLEX_TXDATA0_SHIFT 0 /**< Shift value for USART_TXDATA0 */ #define _USART_TXDOUBLEX_TXDATA0_MASK 0x1FFUL /**< Bit mask for USART_TXDATA0 */ #define _USART_TXDOUBLEX_TXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ #define USART_TXDOUBLEX_TXDATA0_DEFAULT (_USART_TXDOUBLEX_TXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ #define USART_TXDOUBLEX_UBRXAT0 (0x1UL << 11) /**< Unblock RX After Transmission */ #define _USART_TXDOUBLEX_UBRXAT0_SHIFT 11 /**< Shift value for USART_UBRXAT0 */ #define _USART_TXDOUBLEX_UBRXAT0_MASK 0x800UL /**< Bit mask for USART_UBRXAT0 */ #define _USART_TXDOUBLEX_UBRXAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ #define USART_TXDOUBLEX_UBRXAT0_DEFAULT (_USART_TXDOUBLEX_UBRXAT0_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ #define USART_TXDOUBLEX_TXTRIAT0 (0x1UL << 12) /**< Set TXTRI After Transmission */ #define _USART_TXDOUBLEX_TXTRIAT0_SHIFT 12 /**< Shift value for USART_TXTRIAT0 */ #define _USART_TXDOUBLEX_TXTRIAT0_MASK 0x1000UL /**< Bit mask for USART_TXTRIAT0 */ #define _USART_TXDOUBLEX_TXTRIAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ #define USART_TXDOUBLEX_TXTRIAT0_DEFAULT (_USART_TXDOUBLEX_TXTRIAT0_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ #define USART_TXDOUBLEX_TXBREAK0 (0x1UL << 13) /**< Transmit Data as Break */ #define _USART_TXDOUBLEX_TXBREAK0_SHIFT 13 /**< Shift value for USART_TXBREAK0 */ #define _USART_TXDOUBLEX_TXBREAK0_MASK 0x2000UL /**< Bit mask for USART_TXBREAK0 */ #define _USART_TXDOUBLEX_TXBREAK0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ #define USART_TXDOUBLEX_TXBREAK0_DEFAULT (_USART_TXDOUBLEX_TXBREAK0_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ #define USART_TXDOUBLEX_TXDISAT0 (0x1UL << 14) /**< Clear TXEN After Transmission */ #define _USART_TXDOUBLEX_TXDISAT0_SHIFT 14 /**< Shift value for USART_TXDISAT0 */ #define _USART_TXDOUBLEX_TXDISAT0_MASK 0x4000UL /**< Bit mask for USART_TXDISAT0 */ #define _USART_TXDOUBLEX_TXDISAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ #define USART_TXDOUBLEX_TXDISAT0_DEFAULT (_USART_TXDOUBLEX_TXDISAT0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ #define USART_TXDOUBLEX_RXENAT0 (0x1UL << 15) /**< Enable RX After Transmission */ #define _USART_TXDOUBLEX_RXENAT0_SHIFT 15 /**< Shift value for USART_RXENAT0 */ #define _USART_TXDOUBLEX_RXENAT0_MASK 0x8000UL /**< Bit mask for USART_RXENAT0 */ #define _USART_TXDOUBLEX_RXENAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ #define USART_TXDOUBLEX_RXENAT0_DEFAULT (_USART_TXDOUBLEX_RXENAT0_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ #define _USART_TXDOUBLEX_TXDATA1_SHIFT 16 /**< Shift value for USART_TXDATA1 */ #define _USART_TXDOUBLEX_TXDATA1_MASK 0x1FF0000UL /**< Bit mask for USART_TXDATA1 */ #define _USART_TXDOUBLEX_TXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ #define USART_TXDOUBLEX_TXDATA1_DEFAULT (_USART_TXDOUBLEX_TXDATA1_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ #define USART_TXDOUBLEX_UBRXAT1 (0x1UL << 27) /**< Unblock RX After Transmission */ #define _USART_TXDOUBLEX_UBRXAT1_SHIFT 27 /**< Shift value for USART_UBRXAT1 */ #define _USART_TXDOUBLEX_UBRXAT1_MASK 0x8000000UL /**< Bit mask for USART_UBRXAT1 */ #define _USART_TXDOUBLEX_UBRXAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ #define USART_TXDOUBLEX_UBRXAT1_DEFAULT (_USART_TXDOUBLEX_UBRXAT1_DEFAULT << 27) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ #define USART_TXDOUBLEX_TXTRIAT1 (0x1UL << 28) /**< Set TXTRI After Transmission */ #define _USART_TXDOUBLEX_TXTRIAT1_SHIFT 28 /**< Shift value for USART_TXTRIAT1 */ #define _USART_TXDOUBLEX_TXTRIAT1_MASK 0x10000000UL /**< Bit mask for USART_TXTRIAT1 */ #define _USART_TXDOUBLEX_TXTRIAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ #define USART_TXDOUBLEX_TXTRIAT1_DEFAULT (_USART_TXDOUBLEX_TXTRIAT1_DEFAULT << 28) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ #define USART_TXDOUBLEX_TXBREAK1 (0x1UL << 29) /**< Transmit Data as Break */ #define _USART_TXDOUBLEX_TXBREAK1_SHIFT 29 /**< Shift value for USART_TXBREAK1 */ #define _USART_TXDOUBLEX_TXBREAK1_MASK 0x20000000UL /**< Bit mask for USART_TXBREAK1 */ #define _USART_TXDOUBLEX_TXBREAK1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ #define USART_TXDOUBLEX_TXBREAK1_DEFAULT (_USART_TXDOUBLEX_TXBREAK1_DEFAULT << 29) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ #define USART_TXDOUBLEX_TXDISAT1 (0x1UL << 30) /**< Clear TXEN After Transmission */ #define _USART_TXDOUBLEX_TXDISAT1_SHIFT 30 /**< Shift value for USART_TXDISAT1 */ #define _USART_TXDOUBLEX_TXDISAT1_MASK 0x40000000UL /**< Bit mask for USART_TXDISAT1 */ #define _USART_TXDOUBLEX_TXDISAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ #define USART_TXDOUBLEX_TXDISAT1_DEFAULT (_USART_TXDOUBLEX_TXDISAT1_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ #define USART_TXDOUBLEX_RXENAT1 (0x1UL << 31) /**< Enable RX After Transmission */ #define _USART_TXDOUBLEX_RXENAT1_SHIFT 31 /**< Shift value for USART_RXENAT1 */ #define _USART_TXDOUBLEX_RXENAT1_MASK 0x80000000UL /**< Bit mask for USART_RXENAT1 */ #define _USART_TXDOUBLEX_RXENAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ #define USART_TXDOUBLEX_RXENAT1_DEFAULT (_USART_TXDOUBLEX_RXENAT1_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ /* Bit fields for USART TXDOUBLE */ #define _USART_TXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for USART_TXDOUBLE */ #define _USART_TXDOUBLE_MASK 0x0000FFFFUL /**< Mask for USART_TXDOUBLE */ #define _USART_TXDOUBLE_TXDATA0_SHIFT 0 /**< Shift value for USART_TXDATA0 */ #define _USART_TXDOUBLE_TXDATA0_MASK 0xFFUL /**< Bit mask for USART_TXDATA0 */ #define _USART_TXDOUBLE_TXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLE */ #define USART_TXDOUBLE_TXDATA0_DEFAULT (_USART_TXDOUBLE_TXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDOUBLE */ #define _USART_TXDOUBLE_TXDATA1_SHIFT 8 /**< Shift value for USART_TXDATA1 */ #define _USART_TXDOUBLE_TXDATA1_MASK 0xFF00UL /**< Bit mask for USART_TXDATA1 */ #define _USART_TXDOUBLE_TXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLE */ #define USART_TXDOUBLE_TXDATA1_DEFAULT (_USART_TXDOUBLE_TXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_TXDOUBLE */ /* Bit fields for USART IF */ #define _USART_IF_RESETVALUE 0x00000002UL /**< Default value for USART_IF */ #define _USART_IF_MASK 0x0001FFFFUL /**< Mask for USART_IF */ #define USART_IF_TXC (0x1UL << 0) /**< TX Complete Interrupt Flag */ #define _USART_IF_TXC_SHIFT 0 /**< Shift value for USART_TXC */ #define _USART_IF_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */ #define _USART_IF_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ #define USART_IF_TXC_DEFAULT (_USART_IF_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IF */ #define USART_IF_TXBL (0x1UL << 1) /**< TX Buffer Level Interrupt Flag */ #define _USART_IF_TXBL_SHIFT 1 /**< Shift value for USART_TXBL */ #define _USART_IF_TXBL_MASK 0x2UL /**< Bit mask for USART_TXBL */ #define _USART_IF_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_IF */ #define USART_IF_TXBL_DEFAULT (_USART_IF_TXBL_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_IF */ #define USART_IF_RXDATAV (0x1UL << 2) /**< RX Data Valid Interrupt Flag */ #define _USART_IF_RXDATAV_SHIFT 2 /**< Shift value for USART_RXDATAV */ #define _USART_IF_RXDATAV_MASK 0x4UL /**< Bit mask for USART_RXDATAV */ #define _USART_IF_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ #define USART_IF_RXDATAV_DEFAULT (_USART_IF_RXDATAV_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_IF */ #define USART_IF_RXFULL (0x1UL << 3) /**< RX Buffer Full Interrupt Flag */ #define _USART_IF_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */ #define _USART_IF_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */ #define _USART_IF_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ #define USART_IF_RXFULL_DEFAULT (_USART_IF_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IF */ #define USART_IF_RXOF (0x1UL << 4) /**< RX Overflow Interrupt Flag */ #define _USART_IF_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */ #define _USART_IF_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */ #define _USART_IF_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ #define USART_IF_RXOF_DEFAULT (_USART_IF_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_IF */ #define USART_IF_RXUF (0x1UL << 5) /**< RX Underflow Interrupt Flag */ #define _USART_IF_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */ #define _USART_IF_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */ #define _USART_IF_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ #define USART_IF_RXUF_DEFAULT (_USART_IF_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_IF */ #define USART_IF_TXOF (0x1UL << 6) /**< TX Overflow Interrupt Flag */ #define _USART_IF_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */ #define _USART_IF_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */ #define _USART_IF_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ #define USART_IF_TXOF_DEFAULT (_USART_IF_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_IF */ #define USART_IF_TXUF (0x1UL << 7) /**< TX Underflow Interrupt Flag */ #define _USART_IF_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */ #define _USART_IF_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */ #define _USART_IF_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ #define USART_IF_TXUF_DEFAULT (_USART_IF_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_IF */ #define USART_IF_PERR (0x1UL << 8) /**< Parity Error Interrupt Flag */ #define _USART_IF_PERR_SHIFT 8 /**< Shift value for USART_PERR */ #define _USART_IF_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */ #define _USART_IF_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ #define USART_IF_PERR_DEFAULT (_USART_IF_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_IF */ #define USART_IF_FERR (0x1UL << 9) /**< Framing Error Interrupt Flag */ #define _USART_IF_FERR_SHIFT 9 /**< Shift value for USART_FERR */ #define _USART_IF_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */ #define _USART_IF_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ #define USART_IF_FERR_DEFAULT (_USART_IF_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_IF */ #define USART_IF_MPAF (0x1UL << 10) /**< Multi-Processor Address Frame Interrupt Flag */ #define _USART_IF_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */ #define _USART_IF_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */ #define _USART_IF_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ #define USART_IF_MPAF_DEFAULT (_USART_IF_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_IF */ #define USART_IF_SSM (0x1UL << 11) /**< Slave-Select in Master Mode Interrupt Flag */ #define _USART_IF_SSM_SHIFT 11 /**< Shift value for USART_SSM */ #define _USART_IF_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */ #define _USART_IF_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ #define USART_IF_SSM_DEFAULT (_USART_IF_SSM_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_IF */ #define USART_IF_CCF (0x1UL << 12) /**< Collision Check Fail Interrupt Flag */ #define _USART_IF_CCF_SHIFT 12 /**< Shift value for USART_CCF */ #define _USART_IF_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */ #define _USART_IF_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ #define USART_IF_CCF_DEFAULT (_USART_IF_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_IF */ #define USART_IF_TXIDLE (0x1UL << 13) /**< TX Idle Interrupt Flag */ #define _USART_IF_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */ #define _USART_IF_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */ #define _USART_IF_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ #define USART_IF_TXIDLE_DEFAULT (_USART_IF_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_IF */ #define USART_IF_TCMP0 (0x1UL << 14) /**< Timer Comparator 0 Interrupt Flag */ #define _USART_IF_TCMP0_SHIFT 14 /**< Shift value for USART_TCMP0 */ #define _USART_IF_TCMP0_MASK 0x4000UL /**< Bit mask for USART_TCMP0 */ #define _USART_IF_TCMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ #define USART_IF_TCMP0_DEFAULT (_USART_IF_TCMP0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_IF */ #define USART_IF_TCMP1 (0x1UL << 15) /**< Timer Comparator 1 Interrupt Flag */ #define _USART_IF_TCMP1_SHIFT 15 /**< Shift value for USART_TCMP1 */ #define _USART_IF_TCMP1_MASK 0x8000UL /**< Bit mask for USART_TCMP1 */ #define _USART_IF_TCMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ #define USART_IF_TCMP1_DEFAULT (_USART_IF_TCMP1_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_IF */ #define USART_IF_TCMP2 (0x1UL << 16) /**< Timer Comparator 2 Interrupt Flag */ #define _USART_IF_TCMP2_SHIFT 16 /**< Shift value for USART_TCMP2 */ #define _USART_IF_TCMP2_MASK 0x10000UL /**< Bit mask for USART_TCMP2 */ #define _USART_IF_TCMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ #define USART_IF_TCMP2_DEFAULT (_USART_IF_TCMP2_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_IF */ /* Bit fields for USART IFS */ #define _USART_IFS_RESETVALUE 0x00000000UL /**< Default value for USART_IFS */ #define _USART_IFS_MASK 0x0001FFF9UL /**< Mask for USART_IFS */ #define USART_IFS_TXC (0x1UL << 0) /**< Set TXC Interrupt Flag */ #define _USART_IFS_TXC_SHIFT 0 /**< Shift value for USART_TXC */ #define _USART_IFS_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */ #define _USART_IFS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ #define USART_IFS_TXC_DEFAULT (_USART_IFS_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IFS */ #define USART_IFS_RXFULL (0x1UL << 3) /**< Set RXFULL Interrupt Flag */ #define _USART_IFS_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */ #define _USART_IFS_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */ #define _USART_IFS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ #define USART_IFS_RXFULL_DEFAULT (_USART_IFS_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IFS */ #define USART_IFS_RXOF (0x1UL << 4) /**< Set RXOF Interrupt Flag */ #define _USART_IFS_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */ #define _USART_IFS_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */ #define _USART_IFS_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ #define USART_IFS_RXOF_DEFAULT (_USART_IFS_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_IFS */ #define USART_IFS_RXUF (0x1UL << 5) /**< Set RXUF Interrupt Flag */ #define _USART_IFS_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */ #define _USART_IFS_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */ #define _USART_IFS_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ #define USART_IFS_RXUF_DEFAULT (_USART_IFS_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_IFS */ #define USART_IFS_TXOF (0x1UL << 6) /**< Set TXOF Interrupt Flag */ #define _USART_IFS_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */ #define _USART_IFS_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */ #define _USART_IFS_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ #define USART_IFS_TXOF_DEFAULT (_USART_IFS_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_IFS */ #define USART_IFS_TXUF (0x1UL << 7) /**< Set TXUF Interrupt Flag */ #define _USART_IFS_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */ #define _USART_IFS_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */ #define _USART_IFS_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ #define USART_IFS_TXUF_DEFAULT (_USART_IFS_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_IFS */ #define USART_IFS_PERR (0x1UL << 8) /**< Set PERR Interrupt Flag */ #define _USART_IFS_PERR_SHIFT 8 /**< Shift value for USART_PERR */ #define _USART_IFS_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */ #define _USART_IFS_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ #define USART_IFS_PERR_DEFAULT (_USART_IFS_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_IFS */ #define USART_IFS_FERR (0x1UL << 9) /**< Set FERR Interrupt Flag */ #define _USART_IFS_FERR_SHIFT 9 /**< Shift value for USART_FERR */ #define _USART_IFS_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */ #define _USART_IFS_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ #define USART_IFS_FERR_DEFAULT (_USART_IFS_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_IFS */ #define USART_IFS_MPAF (0x1UL << 10) /**< Set MPAF Interrupt Flag */ #define _USART_IFS_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */ #define _USART_IFS_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */ #define _USART_IFS_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ #define USART_IFS_MPAF_DEFAULT (_USART_IFS_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_IFS */ #define USART_IFS_SSM (0x1UL << 11) /**< Set SSM Interrupt Flag */ #define _USART_IFS_SSM_SHIFT 11 /**< Shift value for USART_SSM */ #define _USART_IFS_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */ #define _USART_IFS_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ #define USART_IFS_SSM_DEFAULT (_USART_IFS_SSM_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_IFS */ #define USART_IFS_CCF (0x1UL << 12) /**< Set CCF Interrupt Flag */ #define _USART_IFS_CCF_SHIFT 12 /**< Shift value for USART_CCF */ #define _USART_IFS_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */ #define _USART_IFS_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ #define USART_IFS_CCF_DEFAULT (_USART_IFS_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_IFS */ #define USART_IFS_TXIDLE (0x1UL << 13) /**< Set TXIDLE Interrupt Flag */ #define _USART_IFS_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */ #define _USART_IFS_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */ #define _USART_IFS_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ #define USART_IFS_TXIDLE_DEFAULT (_USART_IFS_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_IFS */ #define USART_IFS_TCMP0 (0x1UL << 14) /**< Set TCMP0 Interrupt Flag */ #define _USART_IFS_TCMP0_SHIFT 14 /**< Shift value for USART_TCMP0 */ #define _USART_IFS_TCMP0_MASK 0x4000UL /**< Bit mask for USART_TCMP0 */ #define _USART_IFS_TCMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ #define USART_IFS_TCMP0_DEFAULT (_USART_IFS_TCMP0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_IFS */ #define USART_IFS_TCMP1 (0x1UL << 15) /**< Set TCMP1 Interrupt Flag */ #define _USART_IFS_TCMP1_SHIFT 15 /**< Shift value for USART_TCMP1 */ #define _USART_IFS_TCMP1_MASK 0x8000UL /**< Bit mask for USART_TCMP1 */ #define _USART_IFS_TCMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ #define USART_IFS_TCMP1_DEFAULT (_USART_IFS_TCMP1_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_IFS */ #define USART_IFS_TCMP2 (0x1UL << 16) /**< Set TCMP2 Interrupt Flag */ #define _USART_IFS_TCMP2_SHIFT 16 /**< Shift value for USART_TCMP2 */ #define _USART_IFS_TCMP2_MASK 0x10000UL /**< Bit mask for USART_TCMP2 */ #define _USART_IFS_TCMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ #define USART_IFS_TCMP2_DEFAULT (_USART_IFS_TCMP2_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_IFS */ /* Bit fields for USART IFC */ #define _USART_IFC_RESETVALUE 0x00000000UL /**< Default value for USART_IFC */ #define _USART_IFC_MASK 0x0001FFF9UL /**< Mask for USART_IFC */ #define USART_IFC_TXC (0x1UL << 0) /**< Clear TXC Interrupt Flag */ #define _USART_IFC_TXC_SHIFT 0 /**< Shift value for USART_TXC */ #define _USART_IFC_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */ #define _USART_IFC_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ #define USART_IFC_TXC_DEFAULT (_USART_IFC_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IFC */ #define USART_IFC_RXFULL (0x1UL << 3) /**< Clear RXFULL Interrupt Flag */ #define _USART_IFC_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */ #define _USART_IFC_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */ #define _USART_IFC_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ #define USART_IFC_RXFULL_DEFAULT (_USART_IFC_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IFC */ #define USART_IFC_RXOF (0x1UL << 4) /**< Clear RXOF Interrupt Flag */ #define _USART_IFC_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */ #define _USART_IFC_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */ #define _USART_IFC_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ #define USART_IFC_RXOF_DEFAULT (_USART_IFC_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_IFC */ #define USART_IFC_RXUF (0x1UL << 5) /**< Clear RXUF Interrupt Flag */ #define _USART_IFC_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */ #define _USART_IFC_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */ #define _USART_IFC_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ #define USART_IFC_RXUF_DEFAULT (_USART_IFC_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_IFC */ #define USART_IFC_TXOF (0x1UL << 6) /**< Clear TXOF Interrupt Flag */ #define _USART_IFC_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */ #define _USART_IFC_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */ #define _USART_IFC_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ #define USART_IFC_TXOF_DEFAULT (_USART_IFC_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_IFC */ #define USART_IFC_TXUF (0x1UL << 7) /**< Clear TXUF Interrupt Flag */ #define _USART_IFC_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */ #define _USART_IFC_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */ #define _USART_IFC_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ #define USART_IFC_TXUF_DEFAULT (_USART_IFC_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_IFC */ #define USART_IFC_PERR (0x1UL << 8) /**< Clear PERR Interrupt Flag */ #define _USART_IFC_PERR_SHIFT 8 /**< Shift value for USART_PERR */ #define _USART_IFC_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */ #define _USART_IFC_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ #define USART_IFC_PERR_DEFAULT (_USART_IFC_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_IFC */ #define USART_IFC_FERR (0x1UL << 9) /**< Clear FERR Interrupt Flag */ #define _USART_IFC_FERR_SHIFT 9 /**< Shift value for USART_FERR */ #define _USART_IFC_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */ #define _USART_IFC_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ #define USART_IFC_FERR_DEFAULT (_USART_IFC_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_IFC */ #define USART_IFC_MPAF (0x1UL << 10) /**< Clear MPAF Interrupt Flag */ #define _USART_IFC_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */ #define _USART_IFC_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */ #define _USART_IFC_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ #define USART_IFC_MPAF_DEFAULT (_USART_IFC_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_IFC */ #define USART_IFC_SSM (0x1UL << 11) /**< Clear SSM Interrupt Flag */ #define _USART_IFC_SSM_SHIFT 11 /**< Shift value for USART_SSM */ #define _USART_IFC_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */ #define _USART_IFC_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ #define USART_IFC_SSM_DEFAULT (_USART_IFC_SSM_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_IFC */ #define USART_IFC_CCF (0x1UL << 12) /**< Clear CCF Interrupt Flag */ #define _USART_IFC_CCF_SHIFT 12 /**< Shift value for USART_CCF */ #define _USART_IFC_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */ #define _USART_IFC_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ #define USART_IFC_CCF_DEFAULT (_USART_IFC_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_IFC */ #define USART_IFC_TXIDLE (0x1UL << 13) /**< Clear TXIDLE Interrupt Flag */ #define _USART_IFC_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */ #define _USART_IFC_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */ #define _USART_IFC_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ #define USART_IFC_TXIDLE_DEFAULT (_USART_IFC_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_IFC */ #define USART_IFC_TCMP0 (0x1UL << 14) /**< Clear TCMP0 Interrupt Flag */ #define _USART_IFC_TCMP0_SHIFT 14 /**< Shift value for USART_TCMP0 */ #define _USART_IFC_TCMP0_MASK 0x4000UL /**< Bit mask for USART_TCMP0 */ #define _USART_IFC_TCMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ #define USART_IFC_TCMP0_DEFAULT (_USART_IFC_TCMP0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_IFC */ #define USART_IFC_TCMP1 (0x1UL << 15) /**< Clear TCMP1 Interrupt Flag */ #define _USART_IFC_TCMP1_SHIFT 15 /**< Shift value for USART_TCMP1 */ #define _USART_IFC_TCMP1_MASK 0x8000UL /**< Bit mask for USART_TCMP1 */ #define _USART_IFC_TCMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ #define USART_IFC_TCMP1_DEFAULT (_USART_IFC_TCMP1_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_IFC */ #define USART_IFC_TCMP2 (0x1UL << 16) /**< Clear TCMP2 Interrupt Flag */ #define _USART_IFC_TCMP2_SHIFT 16 /**< Shift value for USART_TCMP2 */ #define _USART_IFC_TCMP2_MASK 0x10000UL /**< Bit mask for USART_TCMP2 */ #define _USART_IFC_TCMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ #define USART_IFC_TCMP2_DEFAULT (_USART_IFC_TCMP2_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_IFC */ /* Bit fields for USART IEN */ #define _USART_IEN_RESETVALUE 0x00000000UL /**< Default value for USART_IEN */ #define _USART_IEN_MASK 0x0001FFFFUL /**< Mask for USART_IEN */ #define USART_IEN_TXC (0x1UL << 0) /**< TXC Interrupt Enable */ #define _USART_IEN_TXC_SHIFT 0 /**< Shift value for USART_TXC */ #define _USART_IEN_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */ #define _USART_IEN_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ #define USART_IEN_TXC_DEFAULT (_USART_IEN_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IEN */ #define USART_IEN_TXBL (0x1UL << 1) /**< TXBL Interrupt Enable */ #define _USART_IEN_TXBL_SHIFT 1 /**< Shift value for USART_TXBL */ #define _USART_IEN_TXBL_MASK 0x2UL /**< Bit mask for USART_TXBL */ #define _USART_IEN_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ #define USART_IEN_TXBL_DEFAULT (_USART_IEN_TXBL_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_IEN */ #define USART_IEN_RXDATAV (0x1UL << 2) /**< RXDATAV Interrupt Enable */ #define _USART_IEN_RXDATAV_SHIFT 2 /**< Shift value for USART_RXDATAV */ #define _USART_IEN_RXDATAV_MASK 0x4UL /**< Bit mask for USART_RXDATAV */ #define _USART_IEN_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ #define USART_IEN_RXDATAV_DEFAULT (_USART_IEN_RXDATAV_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_IEN */ #define USART_IEN_RXFULL (0x1UL << 3) /**< RXFULL Interrupt Enable */ #define _USART_IEN_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */ #define _USART_IEN_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */ #define _USART_IEN_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ #define USART_IEN_RXFULL_DEFAULT (_USART_IEN_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IEN */ #define USART_IEN_RXOF (0x1UL << 4) /**< RXOF Interrupt Enable */ #define _USART_IEN_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */ #define _USART_IEN_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */ #define _USART_IEN_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ #define USART_IEN_RXOF_DEFAULT (_USART_IEN_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_IEN */ #define USART_IEN_RXUF (0x1UL << 5) /**< RXUF Interrupt Enable */ #define _USART_IEN_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */ #define _USART_IEN_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */ #define _USART_IEN_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ #define USART_IEN_RXUF_DEFAULT (_USART_IEN_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_IEN */ #define USART_IEN_TXOF (0x1UL << 6) /**< TXOF Interrupt Enable */ #define _USART_IEN_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */ #define _USART_IEN_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */ #define _USART_IEN_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ #define USART_IEN_TXOF_DEFAULT (_USART_IEN_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_IEN */ #define USART_IEN_TXUF (0x1UL << 7) /**< TXUF Interrupt Enable */ #define _USART_IEN_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */ #define _USART_IEN_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */ #define _USART_IEN_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ #define USART_IEN_TXUF_DEFAULT (_USART_IEN_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_IEN */ #define USART_IEN_PERR (0x1UL << 8) /**< PERR Interrupt Enable */ #define _USART_IEN_PERR_SHIFT 8 /**< Shift value for USART_PERR */ #define _USART_IEN_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */ #define _USART_IEN_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ #define USART_IEN_PERR_DEFAULT (_USART_IEN_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_IEN */ #define USART_IEN_FERR (0x1UL << 9) /**< FERR Interrupt Enable */ #define _USART_IEN_FERR_SHIFT 9 /**< Shift value for USART_FERR */ #define _USART_IEN_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */ #define _USART_IEN_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ #define USART_IEN_FERR_DEFAULT (_USART_IEN_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_IEN */ #define USART_IEN_MPAF (0x1UL << 10) /**< MPAF Interrupt Enable */ #define _USART_IEN_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */ #define _USART_IEN_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */ #define _USART_IEN_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ #define USART_IEN_MPAF_DEFAULT (_USART_IEN_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_IEN */ #define USART_IEN_SSM (0x1UL << 11) /**< SSM Interrupt Enable */ #define _USART_IEN_SSM_SHIFT 11 /**< Shift value for USART_SSM */ #define _USART_IEN_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */ #define _USART_IEN_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ #define USART_IEN_SSM_DEFAULT (_USART_IEN_SSM_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_IEN */ #define USART_IEN_CCF (0x1UL << 12) /**< CCF Interrupt Enable */ #define _USART_IEN_CCF_SHIFT 12 /**< Shift value for USART_CCF */ #define _USART_IEN_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */ #define _USART_IEN_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ #define USART_IEN_CCF_DEFAULT (_USART_IEN_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_IEN */ #define USART_IEN_TXIDLE (0x1UL << 13) /**< TXIDLE Interrupt Enable */ #define _USART_IEN_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */ #define _USART_IEN_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */ #define _USART_IEN_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ #define USART_IEN_TXIDLE_DEFAULT (_USART_IEN_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_IEN */ #define USART_IEN_TCMP0 (0x1UL << 14) /**< TCMP0 Interrupt Enable */ #define _USART_IEN_TCMP0_SHIFT 14 /**< Shift value for USART_TCMP0 */ #define _USART_IEN_TCMP0_MASK 0x4000UL /**< Bit mask for USART_TCMP0 */ #define _USART_IEN_TCMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ #define USART_IEN_TCMP0_DEFAULT (_USART_IEN_TCMP0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_IEN */ #define USART_IEN_TCMP1 (0x1UL << 15) /**< TCMP1 Interrupt Enable */ #define _USART_IEN_TCMP1_SHIFT 15 /**< Shift value for USART_TCMP1 */ #define _USART_IEN_TCMP1_MASK 0x8000UL /**< Bit mask for USART_TCMP1 */ #define _USART_IEN_TCMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ #define USART_IEN_TCMP1_DEFAULT (_USART_IEN_TCMP1_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_IEN */ #define USART_IEN_TCMP2 (0x1UL << 16) /**< TCMP2 Interrupt Enable */ #define _USART_IEN_TCMP2_SHIFT 16 /**< Shift value for USART_TCMP2 */ #define _USART_IEN_TCMP2_MASK 0x10000UL /**< Bit mask for USART_TCMP2 */ #define _USART_IEN_TCMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ #define USART_IEN_TCMP2_DEFAULT (_USART_IEN_TCMP2_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_IEN */ /* Bit fields for USART IRCTRL */ #define _USART_IRCTRL_RESETVALUE 0x00000000UL /**< Default value for USART_IRCTRL */ #define _USART_IRCTRL_MASK 0x00000F8FUL /**< Mask for USART_IRCTRL */ #define USART_IRCTRL_IREN (0x1UL << 0) /**< Enable IrDA Module */ #define _USART_IRCTRL_IREN_SHIFT 0 /**< Shift value for USART_IREN */ #define _USART_IRCTRL_IREN_MASK 0x1UL /**< Bit mask for USART_IREN */ #define _USART_IRCTRL_IREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */ #define USART_IRCTRL_IREN_DEFAULT (_USART_IRCTRL_IREN_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IRCTRL */ #define _USART_IRCTRL_IRPW_SHIFT 1 /**< Shift value for USART_IRPW */ #define _USART_IRCTRL_IRPW_MASK 0x6UL /**< Bit mask for USART_IRPW */ #define _USART_IRCTRL_IRPW_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */ #define _USART_IRCTRL_IRPW_ONE 0x00000000UL /**< Mode ONE for USART_IRCTRL */ #define _USART_IRCTRL_IRPW_TWO 0x00000001UL /**< Mode TWO for USART_IRCTRL */ #define _USART_IRCTRL_IRPW_THREE 0x00000002UL /**< Mode THREE for USART_IRCTRL */ #define _USART_IRCTRL_IRPW_FOUR 0x00000003UL /**< Mode FOUR for USART_IRCTRL */ #define USART_IRCTRL_IRPW_DEFAULT (_USART_IRCTRL_IRPW_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_IRCTRL */ #define USART_IRCTRL_IRPW_ONE (_USART_IRCTRL_IRPW_ONE << 1) /**< Shifted mode ONE for USART_IRCTRL */ #define USART_IRCTRL_IRPW_TWO (_USART_IRCTRL_IRPW_TWO << 1) /**< Shifted mode TWO for USART_IRCTRL */ #define USART_IRCTRL_IRPW_THREE (_USART_IRCTRL_IRPW_THREE << 1) /**< Shifted mode THREE for USART_IRCTRL */ #define USART_IRCTRL_IRPW_FOUR (_USART_IRCTRL_IRPW_FOUR << 1) /**< Shifted mode FOUR for USART_IRCTRL */ #define USART_IRCTRL_IRFILT (0x1UL << 3) /**< IrDA RX Filter */ #define _USART_IRCTRL_IRFILT_SHIFT 3 /**< Shift value for USART_IRFILT */ #define _USART_IRCTRL_IRFILT_MASK 0x8UL /**< Bit mask for USART_IRFILT */ #define _USART_IRCTRL_IRFILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */ #define USART_IRCTRL_IRFILT_DEFAULT (_USART_IRCTRL_IRFILT_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IRCTRL */ #define USART_IRCTRL_IRPRSEN (0x1UL << 7) /**< IrDA PRS Channel Enable */ #define _USART_IRCTRL_IRPRSEN_SHIFT 7 /**< Shift value for USART_IRPRSEN */ #define _USART_IRCTRL_IRPRSEN_MASK 0x80UL /**< Bit mask for USART_IRPRSEN */ #define _USART_IRCTRL_IRPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */ #define USART_IRCTRL_IRPRSEN_DEFAULT (_USART_IRCTRL_IRPRSEN_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_IRCTRL */ #define _USART_IRCTRL_IRPRSSEL_SHIFT 8 /**< Shift value for USART_IRPRSSEL */ #define _USART_IRCTRL_IRPRSSEL_MASK 0xF00UL /**< Bit mask for USART_IRPRSSEL */ #define _USART_IRCTRL_IRPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */ #define _USART_IRCTRL_IRPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for USART_IRCTRL */ #define _USART_IRCTRL_IRPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for USART_IRCTRL */ #define _USART_IRCTRL_IRPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for USART_IRCTRL */ #define _USART_IRCTRL_IRPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for USART_IRCTRL */ #define _USART_IRCTRL_IRPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for USART_IRCTRL */ #define _USART_IRCTRL_IRPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for USART_IRCTRL */ #define _USART_IRCTRL_IRPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for USART_IRCTRL */ #define _USART_IRCTRL_IRPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for USART_IRCTRL */ #define _USART_IRCTRL_IRPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for USART_IRCTRL */ #define _USART_IRCTRL_IRPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for USART_IRCTRL */ #define _USART_IRCTRL_IRPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for USART_IRCTRL */ #define _USART_IRCTRL_IRPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for USART_IRCTRL */ #define USART_IRCTRL_IRPRSSEL_DEFAULT (_USART_IRCTRL_IRPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_IRCTRL */ #define USART_IRCTRL_IRPRSSEL_PRSCH0 (_USART_IRCTRL_IRPRSSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for USART_IRCTRL */ #define USART_IRCTRL_IRPRSSEL_PRSCH1 (_USART_IRCTRL_IRPRSSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for USART_IRCTRL */ #define USART_IRCTRL_IRPRSSEL_PRSCH2 (_USART_IRCTRL_IRPRSSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for USART_IRCTRL */ #define USART_IRCTRL_IRPRSSEL_PRSCH3 (_USART_IRCTRL_IRPRSSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for USART_IRCTRL */ #define USART_IRCTRL_IRPRSSEL_PRSCH4 (_USART_IRCTRL_IRPRSSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for USART_IRCTRL */ #define USART_IRCTRL_IRPRSSEL_PRSCH5 (_USART_IRCTRL_IRPRSSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for USART_IRCTRL */ #define USART_IRCTRL_IRPRSSEL_PRSCH6 (_USART_IRCTRL_IRPRSSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for USART_IRCTRL */ #define USART_IRCTRL_IRPRSSEL_PRSCH7 (_USART_IRCTRL_IRPRSSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for USART_IRCTRL */ #define USART_IRCTRL_IRPRSSEL_PRSCH8 (_USART_IRCTRL_IRPRSSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for USART_IRCTRL */ #define USART_IRCTRL_IRPRSSEL_PRSCH9 (_USART_IRCTRL_IRPRSSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for USART_IRCTRL */ #define USART_IRCTRL_IRPRSSEL_PRSCH10 (_USART_IRCTRL_IRPRSSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for USART_IRCTRL */ #define USART_IRCTRL_IRPRSSEL_PRSCH11 (_USART_IRCTRL_IRPRSSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for USART_IRCTRL */ /* Bit fields for USART INPUT */ #define _USART_INPUT_RESETVALUE 0x00000000UL /**< Default value for USART_INPUT */ #define _USART_INPUT_MASK 0x00008F8FUL /**< Mask for USART_INPUT */ #define _USART_INPUT_RXPRSSEL_SHIFT 0 /**< Shift value for USART_RXPRSSEL */ #define _USART_INPUT_RXPRSSEL_MASK 0xFUL /**< Bit mask for USART_RXPRSSEL */ #define _USART_INPUT_RXPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_INPUT */ #define _USART_INPUT_RXPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for USART_INPUT */ #define _USART_INPUT_RXPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for USART_INPUT */ #define _USART_INPUT_RXPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for USART_INPUT */ #define _USART_INPUT_RXPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for USART_INPUT */ #define _USART_INPUT_RXPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for USART_INPUT */ #define _USART_INPUT_RXPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for USART_INPUT */ #define _USART_INPUT_RXPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for USART_INPUT */ #define _USART_INPUT_RXPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for USART_INPUT */ #define _USART_INPUT_RXPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for USART_INPUT */ #define _USART_INPUT_RXPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for USART_INPUT */ #define _USART_INPUT_RXPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for USART_INPUT */ #define _USART_INPUT_RXPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for USART_INPUT */ #define USART_INPUT_RXPRSSEL_DEFAULT (_USART_INPUT_RXPRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_INPUT */ #define USART_INPUT_RXPRSSEL_PRSCH0 (_USART_INPUT_RXPRSSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for USART_INPUT */ #define USART_INPUT_RXPRSSEL_PRSCH1 (_USART_INPUT_RXPRSSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for USART_INPUT */ #define USART_INPUT_RXPRSSEL_PRSCH2 (_USART_INPUT_RXPRSSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for USART_INPUT */ #define USART_INPUT_RXPRSSEL_PRSCH3 (_USART_INPUT_RXPRSSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for USART_INPUT */ #define USART_INPUT_RXPRSSEL_PRSCH4 (_USART_INPUT_RXPRSSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for USART_INPUT */ #define USART_INPUT_RXPRSSEL_PRSCH5 (_USART_INPUT_RXPRSSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for USART_INPUT */ #define USART_INPUT_RXPRSSEL_PRSCH6 (_USART_INPUT_RXPRSSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for USART_INPUT */ #define USART_INPUT_RXPRSSEL_PRSCH7 (_USART_INPUT_RXPRSSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for USART_INPUT */ #define USART_INPUT_RXPRSSEL_PRSCH8 (_USART_INPUT_RXPRSSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for USART_INPUT */ #define USART_INPUT_RXPRSSEL_PRSCH9 (_USART_INPUT_RXPRSSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for USART_INPUT */ #define USART_INPUT_RXPRSSEL_PRSCH10 (_USART_INPUT_RXPRSSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for USART_INPUT */ #define USART_INPUT_RXPRSSEL_PRSCH11 (_USART_INPUT_RXPRSSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for USART_INPUT */ #define USART_INPUT_RXPRS (0x1UL << 7) /**< PRS RX Enable */ #define _USART_INPUT_RXPRS_SHIFT 7 /**< Shift value for USART_RXPRS */ #define _USART_INPUT_RXPRS_MASK 0x80UL /**< Bit mask for USART_RXPRS */ #define _USART_INPUT_RXPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_INPUT */ #define USART_INPUT_RXPRS_DEFAULT (_USART_INPUT_RXPRS_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_INPUT */ #define _USART_INPUT_CLKPRSSEL_SHIFT 8 /**< Shift value for USART_CLKPRSSEL */ #define _USART_INPUT_CLKPRSSEL_MASK 0xF00UL /**< Bit mask for USART_CLKPRSSEL */ #define _USART_INPUT_CLKPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_INPUT */ #define _USART_INPUT_CLKPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for USART_INPUT */ #define _USART_INPUT_CLKPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for USART_INPUT */ #define _USART_INPUT_CLKPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for USART_INPUT */ #define _USART_INPUT_CLKPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for USART_INPUT */ #define _USART_INPUT_CLKPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for USART_INPUT */ #define _USART_INPUT_CLKPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for USART_INPUT */ #define _USART_INPUT_CLKPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for USART_INPUT */ #define _USART_INPUT_CLKPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for USART_INPUT */ #define _USART_INPUT_CLKPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for USART_INPUT */ #define _USART_INPUT_CLKPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for USART_INPUT */ #define _USART_INPUT_CLKPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for USART_INPUT */ #define _USART_INPUT_CLKPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for USART_INPUT */ #define USART_INPUT_CLKPRSSEL_DEFAULT (_USART_INPUT_CLKPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_INPUT */ #define USART_INPUT_CLKPRSSEL_PRSCH0 (_USART_INPUT_CLKPRSSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for USART_INPUT */ #define USART_INPUT_CLKPRSSEL_PRSCH1 (_USART_INPUT_CLKPRSSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for USART_INPUT */ #define USART_INPUT_CLKPRSSEL_PRSCH2 (_USART_INPUT_CLKPRSSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for USART_INPUT */ #define USART_INPUT_CLKPRSSEL_PRSCH3 (_USART_INPUT_CLKPRSSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for USART_INPUT */ #define USART_INPUT_CLKPRSSEL_PRSCH4 (_USART_INPUT_CLKPRSSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for USART_INPUT */ #define USART_INPUT_CLKPRSSEL_PRSCH5 (_USART_INPUT_CLKPRSSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for USART_INPUT */ #define USART_INPUT_CLKPRSSEL_PRSCH6 (_USART_INPUT_CLKPRSSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for USART_INPUT */ #define USART_INPUT_CLKPRSSEL_PRSCH7 (_USART_INPUT_CLKPRSSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for USART_INPUT */ #define USART_INPUT_CLKPRSSEL_PRSCH8 (_USART_INPUT_CLKPRSSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for USART_INPUT */ #define USART_INPUT_CLKPRSSEL_PRSCH9 (_USART_INPUT_CLKPRSSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for USART_INPUT */ #define USART_INPUT_CLKPRSSEL_PRSCH10 (_USART_INPUT_CLKPRSSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for USART_INPUT */ #define USART_INPUT_CLKPRSSEL_PRSCH11 (_USART_INPUT_CLKPRSSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for USART_INPUT */ #define USART_INPUT_CLKPRS (0x1UL << 15) /**< PRS CLK Enable */ #define _USART_INPUT_CLKPRS_SHIFT 15 /**< Shift value for USART_CLKPRS */ #define _USART_INPUT_CLKPRS_MASK 0x8000UL /**< Bit mask for USART_CLKPRS */ #define _USART_INPUT_CLKPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_INPUT */ #define USART_INPUT_CLKPRS_DEFAULT (_USART_INPUT_CLKPRS_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_INPUT */ /* Bit fields for USART I2SCTRL */ #define _USART_I2SCTRL_RESETVALUE 0x00000000UL /**< Default value for USART_I2SCTRL */ #define _USART_I2SCTRL_MASK 0x0000071FUL /**< Mask for USART_I2SCTRL */ #define USART_I2SCTRL_EN (0x1UL << 0) /**< Enable I2S Mode */ #define _USART_I2SCTRL_EN_SHIFT 0 /**< Shift value for USART_EN */ #define _USART_I2SCTRL_EN_MASK 0x1UL /**< Bit mask for USART_EN */ #define _USART_I2SCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */ #define USART_I2SCTRL_EN_DEFAULT (_USART_I2SCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_I2SCTRL */ #define USART_I2SCTRL_MONO (0x1UL << 1) /**< Stero or Mono */ #define _USART_I2SCTRL_MONO_SHIFT 1 /**< Shift value for USART_MONO */ #define _USART_I2SCTRL_MONO_MASK 0x2UL /**< Bit mask for USART_MONO */ #define _USART_I2SCTRL_MONO_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */ #define USART_I2SCTRL_MONO_DEFAULT (_USART_I2SCTRL_MONO_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_I2SCTRL */ #define USART_I2SCTRL_JUSTIFY (0x1UL << 2) /**< Justification of I2S Data */ #define _USART_I2SCTRL_JUSTIFY_SHIFT 2 /**< Shift value for USART_JUSTIFY */ #define _USART_I2SCTRL_JUSTIFY_MASK 0x4UL /**< Bit mask for USART_JUSTIFY */ #define _USART_I2SCTRL_JUSTIFY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */ #define _USART_I2SCTRL_JUSTIFY_LEFT 0x00000000UL /**< Mode LEFT for USART_I2SCTRL */ #define _USART_I2SCTRL_JUSTIFY_RIGHT 0x00000001UL /**< Mode RIGHT for USART_I2SCTRL */ #define USART_I2SCTRL_JUSTIFY_DEFAULT (_USART_I2SCTRL_JUSTIFY_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_I2SCTRL */ #define USART_I2SCTRL_JUSTIFY_LEFT (_USART_I2SCTRL_JUSTIFY_LEFT << 2) /**< Shifted mode LEFT for USART_I2SCTRL */ #define USART_I2SCTRL_JUSTIFY_RIGHT (_USART_I2SCTRL_JUSTIFY_RIGHT << 2) /**< Shifted mode RIGHT for USART_I2SCTRL */ #define USART_I2SCTRL_DMASPLIT (0x1UL << 3) /**< Separate DMA Request for Left/Right Data */ #define _USART_I2SCTRL_DMASPLIT_SHIFT 3 /**< Shift value for USART_DMASPLIT */ #define _USART_I2SCTRL_DMASPLIT_MASK 0x8UL /**< Bit mask for USART_DMASPLIT */ #define _USART_I2SCTRL_DMASPLIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */ #define USART_I2SCTRL_DMASPLIT_DEFAULT (_USART_I2SCTRL_DMASPLIT_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_I2SCTRL */ #define USART_I2SCTRL_DELAY (0x1UL << 4) /**< Delay on I2S Data */ #define _USART_I2SCTRL_DELAY_SHIFT 4 /**< Shift value for USART_DELAY */ #define _USART_I2SCTRL_DELAY_MASK 0x10UL /**< Bit mask for USART_DELAY */ #define _USART_I2SCTRL_DELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */ #define USART_I2SCTRL_DELAY_DEFAULT (_USART_I2SCTRL_DELAY_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_I2SCTRL */ #define _USART_I2SCTRL_FORMAT_SHIFT 8 /**< Shift value for USART_FORMAT */ #define _USART_I2SCTRL_FORMAT_MASK 0x700UL /**< Bit mask for USART_FORMAT */ #define _USART_I2SCTRL_FORMAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */ #define _USART_I2SCTRL_FORMAT_W32D32 0x00000000UL /**< Mode W32D32 for USART_I2SCTRL */ #define _USART_I2SCTRL_FORMAT_W32D24M 0x00000001UL /**< Mode W32D24M for USART_I2SCTRL */ #define _USART_I2SCTRL_FORMAT_W32D24 0x00000002UL /**< Mode W32D24 for USART_I2SCTRL */ #define _USART_I2SCTRL_FORMAT_W32D16 0x00000003UL /**< Mode W32D16 for USART_I2SCTRL */ #define _USART_I2SCTRL_FORMAT_W32D8 0x00000004UL /**< Mode W32D8 for USART_I2SCTRL */ #define _USART_I2SCTRL_FORMAT_W16D16 0x00000005UL /**< Mode W16D16 for USART_I2SCTRL */ #define _USART_I2SCTRL_FORMAT_W16D8 0x00000006UL /**< Mode W16D8 for USART_I2SCTRL */ #define _USART_I2SCTRL_FORMAT_W8D8 0x00000007UL /**< Mode W8D8 for USART_I2SCTRL */ #define USART_I2SCTRL_FORMAT_DEFAULT (_USART_I2SCTRL_FORMAT_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_I2SCTRL */ #define USART_I2SCTRL_FORMAT_W32D32 (_USART_I2SCTRL_FORMAT_W32D32 << 8) /**< Shifted mode W32D32 for USART_I2SCTRL */ #define USART_I2SCTRL_FORMAT_W32D24M (_USART_I2SCTRL_FORMAT_W32D24M << 8) /**< Shifted mode W32D24M for USART_I2SCTRL */ #define USART_I2SCTRL_FORMAT_W32D24 (_USART_I2SCTRL_FORMAT_W32D24 << 8) /**< Shifted mode W32D24 for USART_I2SCTRL */ #define USART_I2SCTRL_FORMAT_W32D16 (_USART_I2SCTRL_FORMAT_W32D16 << 8) /**< Shifted mode W32D16 for USART_I2SCTRL */ #define USART_I2SCTRL_FORMAT_W32D8 (_USART_I2SCTRL_FORMAT_W32D8 << 8) /**< Shifted mode W32D8 for USART_I2SCTRL */ #define USART_I2SCTRL_FORMAT_W16D16 (_USART_I2SCTRL_FORMAT_W16D16 << 8) /**< Shifted mode W16D16 for USART_I2SCTRL */ #define USART_I2SCTRL_FORMAT_W16D8 (_USART_I2SCTRL_FORMAT_W16D8 << 8) /**< Shifted mode W16D8 for USART_I2SCTRL */ #define USART_I2SCTRL_FORMAT_W8D8 (_USART_I2SCTRL_FORMAT_W8D8 << 8) /**< Shifted mode W8D8 for USART_I2SCTRL */ /* Bit fields for USART TIMING */ #define _USART_TIMING_RESETVALUE 0x00000000UL /**< Default value for USART_TIMING */ #define _USART_TIMING_MASK 0x77770000UL /**< Mask for USART_TIMING */ #define _USART_TIMING_TXDELAY_SHIFT 16 /**< Shift value for USART_TXDELAY */ #define _USART_TIMING_TXDELAY_MASK 0x70000UL /**< Bit mask for USART_TXDELAY */ #define _USART_TIMING_TXDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMING */ #define _USART_TIMING_TXDELAY_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMING */ #define _USART_TIMING_TXDELAY_ONE 0x00000001UL /**< Mode ONE for USART_TIMING */ #define _USART_TIMING_TXDELAY_TWO 0x00000002UL /**< Mode TWO for USART_TIMING */ #define _USART_TIMING_TXDELAY_THREE 0x00000003UL /**< Mode THREE for USART_TIMING */ #define _USART_TIMING_TXDELAY_SEVEN 0x00000004UL /**< Mode SEVEN for USART_TIMING */ #define _USART_TIMING_TXDELAY_TCMP0 0x00000005UL /**< Mode TCMP0 for USART_TIMING */ #define _USART_TIMING_TXDELAY_TCMP1 0x00000006UL /**< Mode TCMP1 for USART_TIMING */ #define _USART_TIMING_TXDELAY_TCMP2 0x00000007UL /**< Mode TCMP2 for USART_TIMING */ #define USART_TIMING_TXDELAY_DEFAULT (_USART_TIMING_TXDELAY_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TIMING */ #define USART_TIMING_TXDELAY_DISABLE (_USART_TIMING_TXDELAY_DISABLE << 16) /**< Shifted mode DISABLE for USART_TIMING */ #define USART_TIMING_TXDELAY_ONE (_USART_TIMING_TXDELAY_ONE << 16) /**< Shifted mode ONE for USART_TIMING */ #define USART_TIMING_TXDELAY_TWO (_USART_TIMING_TXDELAY_TWO << 16) /**< Shifted mode TWO for USART_TIMING */ #define USART_TIMING_TXDELAY_THREE (_USART_TIMING_TXDELAY_THREE << 16) /**< Shifted mode THREE for USART_TIMING */ #define USART_TIMING_TXDELAY_SEVEN (_USART_TIMING_TXDELAY_SEVEN << 16) /**< Shifted mode SEVEN for USART_TIMING */ #define USART_TIMING_TXDELAY_TCMP0 (_USART_TIMING_TXDELAY_TCMP0 << 16) /**< Shifted mode TCMP0 for USART_TIMING */ #define USART_TIMING_TXDELAY_TCMP1 (_USART_TIMING_TXDELAY_TCMP1 << 16) /**< Shifted mode TCMP1 for USART_TIMING */ #define USART_TIMING_TXDELAY_TCMP2 (_USART_TIMING_TXDELAY_TCMP2 << 16) /**< Shifted mode TCMP2 for USART_TIMING */ #define _USART_TIMING_CSSETUP_SHIFT 20 /**< Shift value for USART_CSSETUP */ #define _USART_TIMING_CSSETUP_MASK 0x700000UL /**< Bit mask for USART_CSSETUP */ #define _USART_TIMING_CSSETUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMING */ #define _USART_TIMING_CSSETUP_ZERO 0x00000000UL /**< Mode ZERO for USART_TIMING */ #define _USART_TIMING_CSSETUP_ONE 0x00000001UL /**< Mode ONE for USART_TIMING */ #define _USART_TIMING_CSSETUP_TWO 0x00000002UL /**< Mode TWO for USART_TIMING */ #define _USART_TIMING_CSSETUP_THREE 0x00000003UL /**< Mode THREE for USART_TIMING */ #define _USART_TIMING_CSSETUP_SEVEN 0x00000004UL /**< Mode SEVEN for USART_TIMING */ #define _USART_TIMING_CSSETUP_TCMP0 0x00000005UL /**< Mode TCMP0 for USART_TIMING */ #define _USART_TIMING_CSSETUP_TCMP1 0x00000006UL /**< Mode TCMP1 for USART_TIMING */ #define _USART_TIMING_CSSETUP_TCMP2 0x00000007UL /**< Mode TCMP2 for USART_TIMING */ #define USART_TIMING_CSSETUP_DEFAULT (_USART_TIMING_CSSETUP_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_TIMING */ #define USART_TIMING_CSSETUP_ZERO (_USART_TIMING_CSSETUP_ZERO << 20) /**< Shifted mode ZERO for USART_TIMING */ #define USART_TIMING_CSSETUP_ONE (_USART_TIMING_CSSETUP_ONE << 20) /**< Shifted mode ONE for USART_TIMING */ #define USART_TIMING_CSSETUP_TWO (_USART_TIMING_CSSETUP_TWO << 20) /**< Shifted mode TWO for USART_TIMING */ #define USART_TIMING_CSSETUP_THREE (_USART_TIMING_CSSETUP_THREE << 20) /**< Shifted mode THREE for USART_TIMING */ #define USART_TIMING_CSSETUP_SEVEN (_USART_TIMING_CSSETUP_SEVEN << 20) /**< Shifted mode SEVEN for USART_TIMING */ #define USART_TIMING_CSSETUP_TCMP0 (_USART_TIMING_CSSETUP_TCMP0 << 20) /**< Shifted mode TCMP0 for USART_TIMING */ #define USART_TIMING_CSSETUP_TCMP1 (_USART_TIMING_CSSETUP_TCMP1 << 20) /**< Shifted mode TCMP1 for USART_TIMING */ #define USART_TIMING_CSSETUP_TCMP2 (_USART_TIMING_CSSETUP_TCMP2 << 20) /**< Shifted mode TCMP2 for USART_TIMING */ #define _USART_TIMING_ICS_SHIFT 24 /**< Shift value for USART_ICS */ #define _USART_TIMING_ICS_MASK 0x7000000UL /**< Bit mask for USART_ICS */ #define _USART_TIMING_ICS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMING */ #define _USART_TIMING_ICS_ZERO 0x00000000UL /**< Mode ZERO for USART_TIMING */ #define _USART_TIMING_ICS_ONE 0x00000001UL /**< Mode ONE for USART_TIMING */ #define _USART_TIMING_ICS_TWO 0x00000002UL /**< Mode TWO for USART_TIMING */ #define _USART_TIMING_ICS_THREE 0x00000003UL /**< Mode THREE for USART_TIMING */ #define _USART_TIMING_ICS_SEVEN 0x00000004UL /**< Mode SEVEN for USART_TIMING */ #define _USART_TIMING_ICS_TCMP0 0x00000005UL /**< Mode TCMP0 for USART_TIMING */ #define _USART_TIMING_ICS_TCMP1 0x00000006UL /**< Mode TCMP1 for USART_TIMING */ #define _USART_TIMING_ICS_TCMP2 0x00000007UL /**< Mode TCMP2 for USART_TIMING */ #define USART_TIMING_ICS_DEFAULT (_USART_TIMING_ICS_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_TIMING */ #define USART_TIMING_ICS_ZERO (_USART_TIMING_ICS_ZERO << 24) /**< Shifted mode ZERO for USART_TIMING */ #define USART_TIMING_ICS_ONE (_USART_TIMING_ICS_ONE << 24) /**< Shifted mode ONE for USART_TIMING */ #define USART_TIMING_ICS_TWO (_USART_TIMING_ICS_TWO << 24) /**< Shifted mode TWO for USART_TIMING */ #define USART_TIMING_ICS_THREE (_USART_TIMING_ICS_THREE << 24) /**< Shifted mode THREE for USART_TIMING */ #define USART_TIMING_ICS_SEVEN (_USART_TIMING_ICS_SEVEN << 24) /**< Shifted mode SEVEN for USART_TIMING */ #define USART_TIMING_ICS_TCMP0 (_USART_TIMING_ICS_TCMP0 << 24) /**< Shifted mode TCMP0 for USART_TIMING */ #define USART_TIMING_ICS_TCMP1 (_USART_TIMING_ICS_TCMP1 << 24) /**< Shifted mode TCMP1 for USART_TIMING */ #define USART_TIMING_ICS_TCMP2 (_USART_TIMING_ICS_TCMP2 << 24) /**< Shifted mode TCMP2 for USART_TIMING */ #define _USART_TIMING_CSHOLD_SHIFT 28 /**< Shift value for USART_CSHOLD */ #define _USART_TIMING_CSHOLD_MASK 0x70000000UL /**< Bit mask for USART_CSHOLD */ #define _USART_TIMING_CSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMING */ #define _USART_TIMING_CSHOLD_ZERO 0x00000000UL /**< Mode ZERO for USART_TIMING */ #define _USART_TIMING_CSHOLD_ONE 0x00000001UL /**< Mode ONE for USART_TIMING */ #define _USART_TIMING_CSHOLD_TWO 0x00000002UL /**< Mode TWO for USART_TIMING */ #define _USART_TIMING_CSHOLD_THREE 0x00000003UL /**< Mode THREE for USART_TIMING */ #define _USART_TIMING_CSHOLD_SEVEN 0x00000004UL /**< Mode SEVEN for USART_TIMING */ #define _USART_TIMING_CSHOLD_TCMP0 0x00000005UL /**< Mode TCMP0 for USART_TIMING */ #define _USART_TIMING_CSHOLD_TCMP1 0x00000006UL /**< Mode TCMP1 for USART_TIMING */ #define _USART_TIMING_CSHOLD_TCMP2 0x00000007UL /**< Mode TCMP2 for USART_TIMING */ #define USART_TIMING_CSHOLD_DEFAULT (_USART_TIMING_CSHOLD_DEFAULT << 28) /**< Shifted mode DEFAULT for USART_TIMING */ #define USART_TIMING_CSHOLD_ZERO (_USART_TIMING_CSHOLD_ZERO << 28) /**< Shifted mode ZERO for USART_TIMING */ #define USART_TIMING_CSHOLD_ONE (_USART_TIMING_CSHOLD_ONE << 28) /**< Shifted mode ONE for USART_TIMING */ #define USART_TIMING_CSHOLD_TWO (_USART_TIMING_CSHOLD_TWO << 28) /**< Shifted mode TWO for USART_TIMING */ #define USART_TIMING_CSHOLD_THREE (_USART_TIMING_CSHOLD_THREE << 28) /**< Shifted mode THREE for USART_TIMING */ #define USART_TIMING_CSHOLD_SEVEN (_USART_TIMING_CSHOLD_SEVEN << 28) /**< Shifted mode SEVEN for USART_TIMING */ #define USART_TIMING_CSHOLD_TCMP0 (_USART_TIMING_CSHOLD_TCMP0 << 28) /**< Shifted mode TCMP0 for USART_TIMING */ #define USART_TIMING_CSHOLD_TCMP1 (_USART_TIMING_CSHOLD_TCMP1 << 28) /**< Shifted mode TCMP1 for USART_TIMING */ #define USART_TIMING_CSHOLD_TCMP2 (_USART_TIMING_CSHOLD_TCMP2 << 28) /**< Shifted mode TCMP2 for USART_TIMING */ /* Bit fields for USART CTRLX */ #define _USART_CTRLX_RESETVALUE 0x00000000UL /**< Default value for USART_CTRLX */ #define _USART_CTRLX_MASK 0x0000000FUL /**< Mask for USART_CTRLX */ #define USART_CTRLX_DBGHALT (0x1UL << 0) /**< Debug Halt */ #define _USART_CTRLX_DBGHALT_SHIFT 0 /**< Shift value for USART_DBGHALT */ #define _USART_CTRLX_DBGHALT_MASK 0x1UL /**< Bit mask for USART_DBGHALT */ #define _USART_CTRLX_DBGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */ #define USART_CTRLX_DBGHALT_DEFAULT (_USART_CTRLX_DBGHALT_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_CTRLX */ #define USART_CTRLX_CTSINV (0x1UL << 1) /**< CTS Pin Inversion */ #define _USART_CTRLX_CTSINV_SHIFT 1 /**< Shift value for USART_CTSINV */ #define _USART_CTRLX_CTSINV_MASK 0x2UL /**< Bit mask for USART_CTSINV */ #define _USART_CTRLX_CTSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */ #define USART_CTRLX_CTSINV_DEFAULT (_USART_CTRLX_CTSINV_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_CTRLX */ #define USART_CTRLX_CTSEN (0x1UL << 2) /**< CTS Function Enabled */ #define _USART_CTRLX_CTSEN_SHIFT 2 /**< Shift value for USART_CTSEN */ #define _USART_CTRLX_CTSEN_MASK 0x4UL /**< Bit mask for USART_CTSEN */ #define _USART_CTRLX_CTSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */ #define USART_CTRLX_CTSEN_DEFAULT (_USART_CTRLX_CTSEN_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_CTRLX */ #define USART_CTRLX_RTSINV (0x1UL << 3) /**< RTS Pin Inversion */ #define _USART_CTRLX_RTSINV_SHIFT 3 /**< Shift value for USART_RTSINV */ #define _USART_CTRLX_RTSINV_MASK 0x8UL /**< Bit mask for USART_RTSINV */ #define _USART_CTRLX_RTSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */ #define USART_CTRLX_RTSINV_DEFAULT (_USART_CTRLX_RTSINV_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_CTRLX */ /* Bit fields for USART TIMECMP0 */ #define _USART_TIMECMP0_RESETVALUE 0x00000000UL /**< Default value for USART_TIMECMP0 */ #define _USART_TIMECMP0_MASK 0x017700FFUL /**< Mask for USART_TIMECMP0 */ #define _USART_TIMECMP0_TCMPVAL_SHIFT 0 /**< Shift value for USART_TCMPVAL */ #define _USART_TIMECMP0_TCMPVAL_MASK 0xFFUL /**< Bit mask for USART_TCMPVAL */ #define _USART_TIMECMP0_TCMPVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP0 */ #define USART_TIMECMP0_TCMPVAL_DEFAULT (_USART_TIMECMP0_TCMPVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TIMECMP0 */ #define _USART_TIMECMP0_TSTART_SHIFT 16 /**< Shift value for USART_TSTART */ #define _USART_TIMECMP0_TSTART_MASK 0x70000UL /**< Bit mask for USART_TSTART */ #define _USART_TIMECMP0_TSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP0 */ #define _USART_TIMECMP0_TSTART_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP0 */ #define _USART_TIMECMP0_TSTART_TXEOF 0x00000001UL /**< Mode TXEOF for USART_TIMECMP0 */ #define _USART_TIMECMP0_TSTART_TXC 0x00000002UL /**< Mode TXC for USART_TIMECMP0 */ #define _USART_TIMECMP0_TSTART_RXACT 0x00000003UL /**< Mode RXACT for USART_TIMECMP0 */ #define _USART_TIMECMP0_TSTART_RXEOF 0x00000004UL /**< Mode RXEOF for USART_TIMECMP0 */ #define USART_TIMECMP0_TSTART_DEFAULT (_USART_TIMECMP0_TSTART_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TIMECMP0 */ #define USART_TIMECMP0_TSTART_DISABLE (_USART_TIMECMP0_TSTART_DISABLE << 16) /**< Shifted mode DISABLE for USART_TIMECMP0 */ #define USART_TIMECMP0_TSTART_TXEOF (_USART_TIMECMP0_TSTART_TXEOF << 16) /**< Shifted mode TXEOF for USART_TIMECMP0 */ #define USART_TIMECMP0_TSTART_TXC (_USART_TIMECMP0_TSTART_TXC << 16) /**< Shifted mode TXC for USART_TIMECMP0 */ #define USART_TIMECMP0_TSTART_RXACT (_USART_TIMECMP0_TSTART_RXACT << 16) /**< Shifted mode RXACT for USART_TIMECMP0 */ #define USART_TIMECMP0_TSTART_RXEOF (_USART_TIMECMP0_TSTART_RXEOF << 16) /**< Shifted mode RXEOF for USART_TIMECMP0 */ #define _USART_TIMECMP0_TSTOP_SHIFT 20 /**< Shift value for USART_TSTOP */ #define _USART_TIMECMP0_TSTOP_MASK 0x700000UL /**< Bit mask for USART_TSTOP */ #define _USART_TIMECMP0_TSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP0 */ #define _USART_TIMECMP0_TSTOP_TCMP0 0x00000000UL /**< Mode TCMP0 for USART_TIMECMP0 */ #define _USART_TIMECMP0_TSTOP_TXST 0x00000001UL /**< Mode TXST for USART_TIMECMP0 */ #define _USART_TIMECMP0_TSTOP_RXACT 0x00000002UL /**< Mode RXACT for USART_TIMECMP0 */ #define _USART_TIMECMP0_TSTOP_RXACTN 0x00000003UL /**< Mode RXACTN for USART_TIMECMP0 */ #define USART_TIMECMP0_TSTOP_DEFAULT (_USART_TIMECMP0_TSTOP_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_TIMECMP0 */ #define USART_TIMECMP0_TSTOP_TCMP0 (_USART_TIMECMP0_TSTOP_TCMP0 << 20) /**< Shifted mode TCMP0 for USART_TIMECMP0 */ #define USART_TIMECMP0_TSTOP_TXST (_USART_TIMECMP0_TSTOP_TXST << 20) /**< Shifted mode TXST for USART_TIMECMP0 */ #define USART_TIMECMP0_TSTOP_RXACT (_USART_TIMECMP0_TSTOP_RXACT << 20) /**< Shifted mode RXACT for USART_TIMECMP0 */ #define USART_TIMECMP0_TSTOP_RXACTN (_USART_TIMECMP0_TSTOP_RXACTN << 20) /**< Shifted mode RXACTN for USART_TIMECMP0 */ #define USART_TIMECMP0_RESTARTEN (0x1UL << 24) /**< Restart Timer on TCMP0 */ #define _USART_TIMECMP0_RESTARTEN_SHIFT 24 /**< Shift value for USART_RESTARTEN */ #define _USART_TIMECMP0_RESTARTEN_MASK 0x1000000UL /**< Bit mask for USART_RESTARTEN */ #define _USART_TIMECMP0_RESTARTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP0 */ #define USART_TIMECMP0_RESTARTEN_DEFAULT (_USART_TIMECMP0_RESTARTEN_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_TIMECMP0 */ /* Bit fields for USART TIMECMP1 */ #define _USART_TIMECMP1_RESETVALUE 0x00000000UL /**< Default value for USART_TIMECMP1 */ #define _USART_TIMECMP1_MASK 0x017700FFUL /**< Mask for USART_TIMECMP1 */ #define _USART_TIMECMP1_TCMPVAL_SHIFT 0 /**< Shift value for USART_TCMPVAL */ #define _USART_TIMECMP1_TCMPVAL_MASK 0xFFUL /**< Bit mask for USART_TCMPVAL */ #define _USART_TIMECMP1_TCMPVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP1 */ #define USART_TIMECMP1_TCMPVAL_DEFAULT (_USART_TIMECMP1_TCMPVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TIMECMP1 */ #define _USART_TIMECMP1_TSTART_SHIFT 16 /**< Shift value for USART_TSTART */ #define _USART_TIMECMP1_TSTART_MASK 0x70000UL /**< Bit mask for USART_TSTART */ #define _USART_TIMECMP1_TSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP1 */ #define _USART_TIMECMP1_TSTART_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP1 */ #define _USART_TIMECMP1_TSTART_TXEOF 0x00000001UL /**< Mode TXEOF for USART_TIMECMP1 */ #define _USART_TIMECMP1_TSTART_TXC 0x00000002UL /**< Mode TXC for USART_TIMECMP1 */ #define _USART_TIMECMP1_TSTART_RXACT 0x00000003UL /**< Mode RXACT for USART_TIMECMP1 */ #define _USART_TIMECMP1_TSTART_RXEOF 0x00000004UL /**< Mode RXEOF for USART_TIMECMP1 */ #define USART_TIMECMP1_TSTART_DEFAULT (_USART_TIMECMP1_TSTART_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TIMECMP1 */ #define USART_TIMECMP1_TSTART_DISABLE (_USART_TIMECMP1_TSTART_DISABLE << 16) /**< Shifted mode DISABLE for USART_TIMECMP1 */ #define USART_TIMECMP1_TSTART_TXEOF (_USART_TIMECMP1_TSTART_TXEOF << 16) /**< Shifted mode TXEOF for USART_TIMECMP1 */ #define USART_TIMECMP1_TSTART_TXC (_USART_TIMECMP1_TSTART_TXC << 16) /**< Shifted mode TXC for USART_TIMECMP1 */ #define USART_TIMECMP1_TSTART_RXACT (_USART_TIMECMP1_TSTART_RXACT << 16) /**< Shifted mode RXACT for USART_TIMECMP1 */ #define USART_TIMECMP1_TSTART_RXEOF (_USART_TIMECMP1_TSTART_RXEOF << 16) /**< Shifted mode RXEOF for USART_TIMECMP1 */ #define _USART_TIMECMP1_TSTOP_SHIFT 20 /**< Shift value for USART_TSTOP */ #define _USART_TIMECMP1_TSTOP_MASK 0x700000UL /**< Bit mask for USART_TSTOP */ #define _USART_TIMECMP1_TSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP1 */ #define _USART_TIMECMP1_TSTOP_TCMP1 0x00000000UL /**< Mode TCMP1 for USART_TIMECMP1 */ #define _USART_TIMECMP1_TSTOP_TXST 0x00000001UL /**< Mode TXST for USART_TIMECMP1 */ #define _USART_TIMECMP1_TSTOP_RXACT 0x00000002UL /**< Mode RXACT for USART_TIMECMP1 */ #define _USART_TIMECMP1_TSTOP_RXACTN 0x00000003UL /**< Mode RXACTN for USART_TIMECMP1 */ #define USART_TIMECMP1_TSTOP_DEFAULT (_USART_TIMECMP1_TSTOP_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_TIMECMP1 */ #define USART_TIMECMP1_TSTOP_TCMP1 (_USART_TIMECMP1_TSTOP_TCMP1 << 20) /**< Shifted mode TCMP1 for USART_TIMECMP1 */ #define USART_TIMECMP1_TSTOP_TXST (_USART_TIMECMP1_TSTOP_TXST << 20) /**< Shifted mode TXST for USART_TIMECMP1 */ #define USART_TIMECMP1_TSTOP_RXACT (_USART_TIMECMP1_TSTOP_RXACT << 20) /**< Shifted mode RXACT for USART_TIMECMP1 */ #define USART_TIMECMP1_TSTOP_RXACTN (_USART_TIMECMP1_TSTOP_RXACTN << 20) /**< Shifted mode RXACTN for USART_TIMECMP1 */ #define USART_TIMECMP1_RESTARTEN (0x1UL << 24) /**< Restart Timer on TCMP1 */ #define _USART_TIMECMP1_RESTARTEN_SHIFT 24 /**< Shift value for USART_RESTARTEN */ #define _USART_TIMECMP1_RESTARTEN_MASK 0x1000000UL /**< Bit mask for USART_RESTARTEN */ #define _USART_TIMECMP1_RESTARTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP1 */ #define USART_TIMECMP1_RESTARTEN_DEFAULT (_USART_TIMECMP1_RESTARTEN_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_TIMECMP1 */ /* Bit fields for USART TIMECMP2 */ #define _USART_TIMECMP2_RESETVALUE 0x00000000UL /**< Default value for USART_TIMECMP2 */ #define _USART_TIMECMP2_MASK 0x017700FFUL /**< Mask for USART_TIMECMP2 */ #define _USART_TIMECMP2_TCMPVAL_SHIFT 0 /**< Shift value for USART_TCMPVAL */ #define _USART_TIMECMP2_TCMPVAL_MASK 0xFFUL /**< Bit mask for USART_TCMPVAL */ #define _USART_TIMECMP2_TCMPVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP2 */ #define USART_TIMECMP2_TCMPVAL_DEFAULT (_USART_TIMECMP2_TCMPVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TIMECMP2 */ #define _USART_TIMECMP2_TSTART_SHIFT 16 /**< Shift value for USART_TSTART */ #define _USART_TIMECMP2_TSTART_MASK 0x70000UL /**< Bit mask for USART_TSTART */ #define _USART_TIMECMP2_TSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP2 */ #define _USART_TIMECMP2_TSTART_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP2 */ #define _USART_TIMECMP2_TSTART_TXEOF 0x00000001UL /**< Mode TXEOF for USART_TIMECMP2 */ #define _USART_TIMECMP2_TSTART_TXC 0x00000002UL /**< Mode TXC for USART_TIMECMP2 */ #define _USART_TIMECMP2_TSTART_RXACT 0x00000003UL /**< Mode RXACT for USART_TIMECMP2 */ #define _USART_TIMECMP2_TSTART_RXEOF 0x00000004UL /**< Mode RXEOF for USART_TIMECMP2 */ #define USART_TIMECMP2_TSTART_DEFAULT (_USART_TIMECMP2_TSTART_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TIMECMP2 */ #define USART_TIMECMP2_TSTART_DISABLE (_USART_TIMECMP2_TSTART_DISABLE << 16) /**< Shifted mode DISABLE for USART_TIMECMP2 */ #define USART_TIMECMP2_TSTART_TXEOF (_USART_TIMECMP2_TSTART_TXEOF << 16) /**< Shifted mode TXEOF for USART_TIMECMP2 */ #define USART_TIMECMP2_TSTART_TXC (_USART_TIMECMP2_TSTART_TXC << 16) /**< Shifted mode TXC for USART_TIMECMP2 */ #define USART_TIMECMP2_TSTART_RXACT (_USART_TIMECMP2_TSTART_RXACT << 16) /**< Shifted mode RXACT for USART_TIMECMP2 */ #define USART_TIMECMP2_TSTART_RXEOF (_USART_TIMECMP2_TSTART_RXEOF << 16) /**< Shifted mode RXEOF for USART_TIMECMP2 */ #define _USART_TIMECMP2_TSTOP_SHIFT 20 /**< Shift value for USART_TSTOP */ #define _USART_TIMECMP2_TSTOP_MASK 0x700000UL /**< Bit mask for USART_TSTOP */ #define _USART_TIMECMP2_TSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP2 */ #define _USART_TIMECMP2_TSTOP_TCMP2 0x00000000UL /**< Mode TCMP2 for USART_TIMECMP2 */ #define _USART_TIMECMP2_TSTOP_TXST 0x00000001UL /**< Mode TXST for USART_TIMECMP2 */ #define _USART_TIMECMP2_TSTOP_RXACT 0x00000002UL /**< Mode RXACT for USART_TIMECMP2 */ #define _USART_TIMECMP2_TSTOP_RXACTN 0x00000003UL /**< Mode RXACTN for USART_TIMECMP2 */ #define USART_TIMECMP2_TSTOP_DEFAULT (_USART_TIMECMP2_TSTOP_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_TIMECMP2 */ #define USART_TIMECMP2_TSTOP_TCMP2 (_USART_TIMECMP2_TSTOP_TCMP2 << 20) /**< Shifted mode TCMP2 for USART_TIMECMP2 */ #define USART_TIMECMP2_TSTOP_TXST (_USART_TIMECMP2_TSTOP_TXST << 20) /**< Shifted mode TXST for USART_TIMECMP2 */ #define USART_TIMECMP2_TSTOP_RXACT (_USART_TIMECMP2_TSTOP_RXACT << 20) /**< Shifted mode RXACT for USART_TIMECMP2 */ #define USART_TIMECMP2_TSTOP_RXACTN (_USART_TIMECMP2_TSTOP_RXACTN << 20) /**< Shifted mode RXACTN for USART_TIMECMP2 */ #define USART_TIMECMP2_RESTARTEN (0x1UL << 24) /**< Restart Timer on TCMP2 */ #define _USART_TIMECMP2_RESTARTEN_SHIFT 24 /**< Shift value for USART_RESTARTEN */ #define _USART_TIMECMP2_RESTARTEN_MASK 0x1000000UL /**< Bit mask for USART_RESTARTEN */ #define _USART_TIMECMP2_RESTARTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP2 */ #define USART_TIMECMP2_RESTARTEN_DEFAULT (_USART_TIMECMP2_RESTARTEN_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_TIMECMP2 */ /* Bit fields for USART ROUTEPEN */ #define _USART_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for USART_ROUTEPEN */ #define _USART_ROUTEPEN_MASK 0x0000003FUL /**< Mask for USART_ROUTEPEN */ #define USART_ROUTEPEN_RXPEN (0x1UL << 0) /**< RX Pin Enable */ #define _USART_ROUTEPEN_RXPEN_SHIFT 0 /**< Shift value for USART_RXPEN */ #define _USART_ROUTEPEN_RXPEN_MASK 0x1UL /**< Bit mask for USART_RXPEN */ #define _USART_ROUTEPEN_RXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTEPEN */ #define USART_ROUTEPEN_RXPEN_DEFAULT (_USART_ROUTEPEN_RXPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_ROUTEPEN */ #define USART_ROUTEPEN_TXPEN (0x1UL << 1) /**< TX Pin Enable */ #define _USART_ROUTEPEN_TXPEN_SHIFT 1 /**< Shift value for USART_TXPEN */ #define _USART_ROUTEPEN_TXPEN_MASK 0x2UL /**< Bit mask for USART_TXPEN */ #define _USART_ROUTEPEN_TXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTEPEN */ #define USART_ROUTEPEN_TXPEN_DEFAULT (_USART_ROUTEPEN_TXPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_ROUTEPEN */ #define USART_ROUTEPEN_CSPEN (0x1UL << 2) /**< CS Pin Enable */ #define _USART_ROUTEPEN_CSPEN_SHIFT 2 /**< Shift value for USART_CSPEN */ #define _USART_ROUTEPEN_CSPEN_MASK 0x4UL /**< Bit mask for USART_CSPEN */ #define _USART_ROUTEPEN_CSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTEPEN */ #define USART_ROUTEPEN_CSPEN_DEFAULT (_USART_ROUTEPEN_CSPEN_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_ROUTEPEN */ #define USART_ROUTEPEN_CLKPEN (0x1UL << 3) /**< CLK Pin Enable */ #define _USART_ROUTEPEN_CLKPEN_SHIFT 3 /**< Shift value for USART_CLKPEN */ #define _USART_ROUTEPEN_CLKPEN_MASK 0x8UL /**< Bit mask for USART_CLKPEN */ #define _USART_ROUTEPEN_CLKPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTEPEN */ #define USART_ROUTEPEN_CLKPEN_DEFAULT (_USART_ROUTEPEN_CLKPEN_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_ROUTEPEN */ #define USART_ROUTEPEN_CTSPEN (0x1UL << 4) /**< CTS Pin Enable */ #define _USART_ROUTEPEN_CTSPEN_SHIFT 4 /**< Shift value for USART_CTSPEN */ #define _USART_ROUTEPEN_CTSPEN_MASK 0x10UL /**< Bit mask for USART_CTSPEN */ #define _USART_ROUTEPEN_CTSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTEPEN */ #define USART_ROUTEPEN_CTSPEN_DEFAULT (_USART_ROUTEPEN_CTSPEN_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_ROUTEPEN */ #define USART_ROUTEPEN_RTSPEN (0x1UL << 5) /**< RTS Pin Enable */ #define _USART_ROUTEPEN_RTSPEN_SHIFT 5 /**< Shift value for USART_RTSPEN */ #define _USART_ROUTEPEN_RTSPEN_MASK 0x20UL /**< Bit mask for USART_RTSPEN */ #define _USART_ROUTEPEN_RTSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTEPEN */ #define USART_ROUTEPEN_RTSPEN_DEFAULT (_USART_ROUTEPEN_RTSPEN_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_ROUTEPEN */ /* Bit fields for USART ROUTELOC0 */ #define _USART_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_MASK 0x1F1F1F1FUL /**< Mask for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_RXLOC_SHIFT 0 /**< Shift value for USART_RXLOC */ #define _USART_ROUTELOC0_RXLOC_MASK 0x1FUL /**< Bit mask for USART_RXLOC */ #define _USART_ROUTELOC0_RXLOC_LOC0 0x00000000UL /**< Mode LOC0 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_RXLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_RXLOC_LOC1 0x00000001UL /**< Mode LOC1 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_RXLOC_LOC2 0x00000002UL /**< Mode LOC2 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_RXLOC_LOC3 0x00000003UL /**< Mode LOC3 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_RXLOC_LOC4 0x00000004UL /**< Mode LOC4 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_RXLOC_LOC5 0x00000005UL /**< Mode LOC5 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_RXLOC_LOC6 0x00000006UL /**< Mode LOC6 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_RXLOC_LOC7 0x00000007UL /**< Mode LOC7 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_RXLOC_LOC8 0x00000008UL /**< Mode LOC8 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_RXLOC_LOC9 0x00000009UL /**< Mode LOC9 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_RXLOC_LOC10 0x0000000AUL /**< Mode LOC10 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_RXLOC_LOC11 0x0000000BUL /**< Mode LOC11 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_RXLOC_LOC12 0x0000000CUL /**< Mode LOC12 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_RXLOC_LOC13 0x0000000DUL /**< Mode LOC13 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_RXLOC_LOC14 0x0000000EUL /**< Mode LOC14 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_RXLOC_LOC15 0x0000000FUL /**< Mode LOC15 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_RXLOC_LOC16 0x00000010UL /**< Mode LOC16 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_RXLOC_LOC17 0x00000011UL /**< Mode LOC17 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_RXLOC_LOC18 0x00000012UL /**< Mode LOC18 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_RXLOC_LOC19 0x00000013UL /**< Mode LOC19 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_RXLOC_LOC20 0x00000014UL /**< Mode LOC20 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_RXLOC_LOC21 0x00000015UL /**< Mode LOC21 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_RXLOC_LOC22 0x00000016UL /**< Mode LOC22 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_RXLOC_LOC23 0x00000017UL /**< Mode LOC23 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_RXLOC_LOC24 0x00000018UL /**< Mode LOC24 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_RXLOC_LOC25 0x00000019UL /**< Mode LOC25 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_RXLOC_LOC26 0x0000001AUL /**< Mode LOC26 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_RXLOC_LOC27 0x0000001BUL /**< Mode LOC27 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_RXLOC_LOC28 0x0000001CUL /**< Mode LOC28 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_RXLOC_LOC29 0x0000001DUL /**< Mode LOC29 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_RXLOC_LOC30 0x0000001EUL /**< Mode LOC30 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_RXLOC_LOC31 0x0000001FUL /**< Mode LOC31 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_RXLOC_LOC0 (_USART_ROUTELOC0_RXLOC_LOC0 << 0) /**< Shifted mode LOC0 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_RXLOC_DEFAULT (_USART_ROUTELOC0_RXLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_ROUTELOC0 */ #define USART_ROUTELOC0_RXLOC_LOC1 (_USART_ROUTELOC0_RXLOC_LOC1 << 0) /**< Shifted mode LOC1 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_RXLOC_LOC2 (_USART_ROUTELOC0_RXLOC_LOC2 << 0) /**< Shifted mode LOC2 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_RXLOC_LOC3 (_USART_ROUTELOC0_RXLOC_LOC3 << 0) /**< Shifted mode LOC3 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_RXLOC_LOC4 (_USART_ROUTELOC0_RXLOC_LOC4 << 0) /**< Shifted mode LOC4 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_RXLOC_LOC5 (_USART_ROUTELOC0_RXLOC_LOC5 << 0) /**< Shifted mode LOC5 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_RXLOC_LOC6 (_USART_ROUTELOC0_RXLOC_LOC6 << 0) /**< Shifted mode LOC6 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_RXLOC_LOC7 (_USART_ROUTELOC0_RXLOC_LOC7 << 0) /**< Shifted mode LOC7 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_RXLOC_LOC8 (_USART_ROUTELOC0_RXLOC_LOC8 << 0) /**< Shifted mode LOC8 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_RXLOC_LOC9 (_USART_ROUTELOC0_RXLOC_LOC9 << 0) /**< Shifted mode LOC9 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_RXLOC_LOC10 (_USART_ROUTELOC0_RXLOC_LOC10 << 0) /**< Shifted mode LOC10 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_RXLOC_LOC11 (_USART_ROUTELOC0_RXLOC_LOC11 << 0) /**< Shifted mode LOC11 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_RXLOC_LOC12 (_USART_ROUTELOC0_RXLOC_LOC12 << 0) /**< Shifted mode LOC12 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_RXLOC_LOC13 (_USART_ROUTELOC0_RXLOC_LOC13 << 0) /**< Shifted mode LOC13 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_RXLOC_LOC14 (_USART_ROUTELOC0_RXLOC_LOC14 << 0) /**< Shifted mode LOC14 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_RXLOC_LOC15 (_USART_ROUTELOC0_RXLOC_LOC15 << 0) /**< Shifted mode LOC15 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_RXLOC_LOC16 (_USART_ROUTELOC0_RXLOC_LOC16 << 0) /**< Shifted mode LOC16 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_RXLOC_LOC17 (_USART_ROUTELOC0_RXLOC_LOC17 << 0) /**< Shifted mode LOC17 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_RXLOC_LOC18 (_USART_ROUTELOC0_RXLOC_LOC18 << 0) /**< Shifted mode LOC18 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_RXLOC_LOC19 (_USART_ROUTELOC0_RXLOC_LOC19 << 0) /**< Shifted mode LOC19 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_RXLOC_LOC20 (_USART_ROUTELOC0_RXLOC_LOC20 << 0) /**< Shifted mode LOC20 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_RXLOC_LOC21 (_USART_ROUTELOC0_RXLOC_LOC21 << 0) /**< Shifted mode LOC21 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_RXLOC_LOC22 (_USART_ROUTELOC0_RXLOC_LOC22 << 0) /**< Shifted mode LOC22 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_RXLOC_LOC23 (_USART_ROUTELOC0_RXLOC_LOC23 << 0) /**< Shifted mode LOC23 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_RXLOC_LOC24 (_USART_ROUTELOC0_RXLOC_LOC24 << 0) /**< Shifted mode LOC24 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_RXLOC_LOC25 (_USART_ROUTELOC0_RXLOC_LOC25 << 0) /**< Shifted mode LOC25 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_RXLOC_LOC26 (_USART_ROUTELOC0_RXLOC_LOC26 << 0) /**< Shifted mode LOC26 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_RXLOC_LOC27 (_USART_ROUTELOC0_RXLOC_LOC27 << 0) /**< Shifted mode LOC27 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_RXLOC_LOC28 (_USART_ROUTELOC0_RXLOC_LOC28 << 0) /**< Shifted mode LOC28 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_RXLOC_LOC29 (_USART_ROUTELOC0_RXLOC_LOC29 << 0) /**< Shifted mode LOC29 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_RXLOC_LOC30 (_USART_ROUTELOC0_RXLOC_LOC30 << 0) /**< Shifted mode LOC30 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_RXLOC_LOC31 (_USART_ROUTELOC0_RXLOC_LOC31 << 0) /**< Shifted mode LOC31 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_TXLOC_SHIFT 8 /**< Shift value for USART_TXLOC */ #define _USART_ROUTELOC0_TXLOC_MASK 0x1F00UL /**< Bit mask for USART_TXLOC */ #define _USART_ROUTELOC0_TXLOC_LOC0 0x00000000UL /**< Mode LOC0 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_TXLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_TXLOC_LOC1 0x00000001UL /**< Mode LOC1 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_TXLOC_LOC2 0x00000002UL /**< Mode LOC2 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_TXLOC_LOC3 0x00000003UL /**< Mode LOC3 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_TXLOC_LOC4 0x00000004UL /**< Mode LOC4 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_TXLOC_LOC5 0x00000005UL /**< Mode LOC5 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_TXLOC_LOC6 0x00000006UL /**< Mode LOC6 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_TXLOC_LOC7 0x00000007UL /**< Mode LOC7 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_TXLOC_LOC8 0x00000008UL /**< Mode LOC8 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_TXLOC_LOC9 0x00000009UL /**< Mode LOC9 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_TXLOC_LOC10 0x0000000AUL /**< Mode LOC10 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_TXLOC_LOC11 0x0000000BUL /**< Mode LOC11 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_TXLOC_LOC12 0x0000000CUL /**< Mode LOC12 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_TXLOC_LOC13 0x0000000DUL /**< Mode LOC13 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_TXLOC_LOC14 0x0000000EUL /**< Mode LOC14 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_TXLOC_LOC15 0x0000000FUL /**< Mode LOC15 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_TXLOC_LOC16 0x00000010UL /**< Mode LOC16 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_TXLOC_LOC17 0x00000011UL /**< Mode LOC17 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_TXLOC_LOC18 0x00000012UL /**< Mode LOC18 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_TXLOC_LOC19 0x00000013UL /**< Mode LOC19 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_TXLOC_LOC20 0x00000014UL /**< Mode LOC20 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_TXLOC_LOC21 0x00000015UL /**< Mode LOC21 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_TXLOC_LOC22 0x00000016UL /**< Mode LOC22 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_TXLOC_LOC23 0x00000017UL /**< Mode LOC23 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_TXLOC_LOC24 0x00000018UL /**< Mode LOC24 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_TXLOC_LOC25 0x00000019UL /**< Mode LOC25 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_TXLOC_LOC26 0x0000001AUL /**< Mode LOC26 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_TXLOC_LOC27 0x0000001BUL /**< Mode LOC27 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_TXLOC_LOC28 0x0000001CUL /**< Mode LOC28 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_TXLOC_LOC29 0x0000001DUL /**< Mode LOC29 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_TXLOC_LOC30 0x0000001EUL /**< Mode LOC30 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_TXLOC_LOC31 0x0000001FUL /**< Mode LOC31 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_TXLOC_LOC0 (_USART_ROUTELOC0_TXLOC_LOC0 << 8) /**< Shifted mode LOC0 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_TXLOC_DEFAULT (_USART_ROUTELOC0_TXLOC_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_ROUTELOC0 */ #define USART_ROUTELOC0_TXLOC_LOC1 (_USART_ROUTELOC0_TXLOC_LOC1 << 8) /**< Shifted mode LOC1 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_TXLOC_LOC2 (_USART_ROUTELOC0_TXLOC_LOC2 << 8) /**< Shifted mode LOC2 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_TXLOC_LOC3 (_USART_ROUTELOC0_TXLOC_LOC3 << 8) /**< Shifted mode LOC3 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_TXLOC_LOC4 (_USART_ROUTELOC0_TXLOC_LOC4 << 8) /**< Shifted mode LOC4 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_TXLOC_LOC5 (_USART_ROUTELOC0_TXLOC_LOC5 << 8) /**< Shifted mode LOC5 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_TXLOC_LOC6 (_USART_ROUTELOC0_TXLOC_LOC6 << 8) /**< Shifted mode LOC6 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_TXLOC_LOC7 (_USART_ROUTELOC0_TXLOC_LOC7 << 8) /**< Shifted mode LOC7 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_TXLOC_LOC8 (_USART_ROUTELOC0_TXLOC_LOC8 << 8) /**< Shifted mode LOC8 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_TXLOC_LOC9 (_USART_ROUTELOC0_TXLOC_LOC9 << 8) /**< Shifted mode LOC9 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_TXLOC_LOC10 (_USART_ROUTELOC0_TXLOC_LOC10 << 8) /**< Shifted mode LOC10 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_TXLOC_LOC11 (_USART_ROUTELOC0_TXLOC_LOC11 << 8) /**< Shifted mode LOC11 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_TXLOC_LOC12 (_USART_ROUTELOC0_TXLOC_LOC12 << 8) /**< Shifted mode LOC12 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_TXLOC_LOC13 (_USART_ROUTELOC0_TXLOC_LOC13 << 8) /**< Shifted mode LOC13 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_TXLOC_LOC14 (_USART_ROUTELOC0_TXLOC_LOC14 << 8) /**< Shifted mode LOC14 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_TXLOC_LOC15 (_USART_ROUTELOC0_TXLOC_LOC15 << 8) /**< Shifted mode LOC15 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_TXLOC_LOC16 (_USART_ROUTELOC0_TXLOC_LOC16 << 8) /**< Shifted mode LOC16 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_TXLOC_LOC17 (_USART_ROUTELOC0_TXLOC_LOC17 << 8) /**< Shifted mode LOC17 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_TXLOC_LOC18 (_USART_ROUTELOC0_TXLOC_LOC18 << 8) /**< Shifted mode LOC18 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_TXLOC_LOC19 (_USART_ROUTELOC0_TXLOC_LOC19 << 8) /**< Shifted mode LOC19 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_TXLOC_LOC20 (_USART_ROUTELOC0_TXLOC_LOC20 << 8) /**< Shifted mode LOC20 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_TXLOC_LOC21 (_USART_ROUTELOC0_TXLOC_LOC21 << 8) /**< Shifted mode LOC21 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_TXLOC_LOC22 (_USART_ROUTELOC0_TXLOC_LOC22 << 8) /**< Shifted mode LOC22 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_TXLOC_LOC23 (_USART_ROUTELOC0_TXLOC_LOC23 << 8) /**< Shifted mode LOC23 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_TXLOC_LOC24 (_USART_ROUTELOC0_TXLOC_LOC24 << 8) /**< Shifted mode LOC24 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_TXLOC_LOC25 (_USART_ROUTELOC0_TXLOC_LOC25 << 8) /**< Shifted mode LOC25 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_TXLOC_LOC26 (_USART_ROUTELOC0_TXLOC_LOC26 << 8) /**< Shifted mode LOC26 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_TXLOC_LOC27 (_USART_ROUTELOC0_TXLOC_LOC27 << 8) /**< Shifted mode LOC27 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_TXLOC_LOC28 (_USART_ROUTELOC0_TXLOC_LOC28 << 8) /**< Shifted mode LOC28 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_TXLOC_LOC29 (_USART_ROUTELOC0_TXLOC_LOC29 << 8) /**< Shifted mode LOC29 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_TXLOC_LOC30 (_USART_ROUTELOC0_TXLOC_LOC30 << 8) /**< Shifted mode LOC30 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_TXLOC_LOC31 (_USART_ROUTELOC0_TXLOC_LOC31 << 8) /**< Shifted mode LOC31 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_CSLOC_SHIFT 16 /**< Shift value for USART_CSLOC */ #define _USART_ROUTELOC0_CSLOC_MASK 0x1F0000UL /**< Bit mask for USART_CSLOC */ #define _USART_ROUTELOC0_CSLOC_LOC0 0x00000000UL /**< Mode LOC0 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_CSLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_CSLOC_LOC1 0x00000001UL /**< Mode LOC1 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_CSLOC_LOC2 0x00000002UL /**< Mode LOC2 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_CSLOC_LOC3 0x00000003UL /**< Mode LOC3 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_CSLOC_LOC4 0x00000004UL /**< Mode LOC4 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_CSLOC_LOC5 0x00000005UL /**< Mode LOC5 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_CSLOC_LOC6 0x00000006UL /**< Mode LOC6 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_CSLOC_LOC7 0x00000007UL /**< Mode LOC7 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_CSLOC_LOC8 0x00000008UL /**< Mode LOC8 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_CSLOC_LOC9 0x00000009UL /**< Mode LOC9 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_CSLOC_LOC10 0x0000000AUL /**< Mode LOC10 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_CSLOC_LOC11 0x0000000BUL /**< Mode LOC11 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_CSLOC_LOC12 0x0000000CUL /**< Mode LOC12 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_CSLOC_LOC13 0x0000000DUL /**< Mode LOC13 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_CSLOC_LOC14 0x0000000EUL /**< Mode LOC14 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_CSLOC_LOC15 0x0000000FUL /**< Mode LOC15 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_CSLOC_LOC16 0x00000010UL /**< Mode LOC16 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_CSLOC_LOC17 0x00000011UL /**< Mode LOC17 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_CSLOC_LOC18 0x00000012UL /**< Mode LOC18 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_CSLOC_LOC19 0x00000013UL /**< Mode LOC19 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_CSLOC_LOC20 0x00000014UL /**< Mode LOC20 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_CSLOC_LOC21 0x00000015UL /**< Mode LOC21 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_CSLOC_LOC22 0x00000016UL /**< Mode LOC22 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_CSLOC_LOC23 0x00000017UL /**< Mode LOC23 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_CSLOC_LOC24 0x00000018UL /**< Mode LOC24 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_CSLOC_LOC25 0x00000019UL /**< Mode LOC25 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_CSLOC_LOC26 0x0000001AUL /**< Mode LOC26 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_CSLOC_LOC27 0x0000001BUL /**< Mode LOC27 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_CSLOC_LOC28 0x0000001CUL /**< Mode LOC28 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_CSLOC_LOC29 0x0000001DUL /**< Mode LOC29 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_CSLOC_LOC30 0x0000001EUL /**< Mode LOC30 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_CSLOC_LOC31 0x0000001FUL /**< Mode LOC31 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_CSLOC_LOC0 (_USART_ROUTELOC0_CSLOC_LOC0 << 16) /**< Shifted mode LOC0 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_CSLOC_DEFAULT (_USART_ROUTELOC0_CSLOC_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_ROUTELOC0 */ #define USART_ROUTELOC0_CSLOC_LOC1 (_USART_ROUTELOC0_CSLOC_LOC1 << 16) /**< Shifted mode LOC1 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_CSLOC_LOC2 (_USART_ROUTELOC0_CSLOC_LOC2 << 16) /**< Shifted mode LOC2 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_CSLOC_LOC3 (_USART_ROUTELOC0_CSLOC_LOC3 << 16) /**< Shifted mode LOC3 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_CSLOC_LOC4 (_USART_ROUTELOC0_CSLOC_LOC4 << 16) /**< Shifted mode LOC4 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_CSLOC_LOC5 (_USART_ROUTELOC0_CSLOC_LOC5 << 16) /**< Shifted mode LOC5 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_CSLOC_LOC6 (_USART_ROUTELOC0_CSLOC_LOC6 << 16) /**< Shifted mode LOC6 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_CSLOC_LOC7 (_USART_ROUTELOC0_CSLOC_LOC7 << 16) /**< Shifted mode LOC7 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_CSLOC_LOC8 (_USART_ROUTELOC0_CSLOC_LOC8 << 16) /**< Shifted mode LOC8 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_CSLOC_LOC9 (_USART_ROUTELOC0_CSLOC_LOC9 << 16) /**< Shifted mode LOC9 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_CSLOC_LOC10 (_USART_ROUTELOC0_CSLOC_LOC10 << 16) /**< Shifted mode LOC10 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_CSLOC_LOC11 (_USART_ROUTELOC0_CSLOC_LOC11 << 16) /**< Shifted mode LOC11 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_CSLOC_LOC12 (_USART_ROUTELOC0_CSLOC_LOC12 << 16) /**< Shifted mode LOC12 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_CSLOC_LOC13 (_USART_ROUTELOC0_CSLOC_LOC13 << 16) /**< Shifted mode LOC13 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_CSLOC_LOC14 (_USART_ROUTELOC0_CSLOC_LOC14 << 16) /**< Shifted mode LOC14 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_CSLOC_LOC15 (_USART_ROUTELOC0_CSLOC_LOC15 << 16) /**< Shifted mode LOC15 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_CSLOC_LOC16 (_USART_ROUTELOC0_CSLOC_LOC16 << 16) /**< Shifted mode LOC16 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_CSLOC_LOC17 (_USART_ROUTELOC0_CSLOC_LOC17 << 16) /**< Shifted mode LOC17 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_CSLOC_LOC18 (_USART_ROUTELOC0_CSLOC_LOC18 << 16) /**< Shifted mode LOC18 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_CSLOC_LOC19 (_USART_ROUTELOC0_CSLOC_LOC19 << 16) /**< Shifted mode LOC19 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_CSLOC_LOC20 (_USART_ROUTELOC0_CSLOC_LOC20 << 16) /**< Shifted mode LOC20 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_CSLOC_LOC21 (_USART_ROUTELOC0_CSLOC_LOC21 << 16) /**< Shifted mode LOC21 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_CSLOC_LOC22 (_USART_ROUTELOC0_CSLOC_LOC22 << 16) /**< Shifted mode LOC22 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_CSLOC_LOC23 (_USART_ROUTELOC0_CSLOC_LOC23 << 16) /**< Shifted mode LOC23 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_CSLOC_LOC24 (_USART_ROUTELOC0_CSLOC_LOC24 << 16) /**< Shifted mode LOC24 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_CSLOC_LOC25 (_USART_ROUTELOC0_CSLOC_LOC25 << 16) /**< Shifted mode LOC25 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_CSLOC_LOC26 (_USART_ROUTELOC0_CSLOC_LOC26 << 16) /**< Shifted mode LOC26 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_CSLOC_LOC27 (_USART_ROUTELOC0_CSLOC_LOC27 << 16) /**< Shifted mode LOC27 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_CSLOC_LOC28 (_USART_ROUTELOC0_CSLOC_LOC28 << 16) /**< Shifted mode LOC28 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_CSLOC_LOC29 (_USART_ROUTELOC0_CSLOC_LOC29 << 16) /**< Shifted mode LOC29 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_CSLOC_LOC30 (_USART_ROUTELOC0_CSLOC_LOC30 << 16) /**< Shifted mode LOC30 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_CSLOC_LOC31 (_USART_ROUTELOC0_CSLOC_LOC31 << 16) /**< Shifted mode LOC31 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_CLKLOC_SHIFT 24 /**< Shift value for USART_CLKLOC */ #define _USART_ROUTELOC0_CLKLOC_MASK 0x1F000000UL /**< Bit mask for USART_CLKLOC */ #define _USART_ROUTELOC0_CLKLOC_LOC0 0x00000000UL /**< Mode LOC0 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_CLKLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_CLKLOC_LOC1 0x00000001UL /**< Mode LOC1 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_CLKLOC_LOC2 0x00000002UL /**< Mode LOC2 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_CLKLOC_LOC3 0x00000003UL /**< Mode LOC3 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_CLKLOC_LOC4 0x00000004UL /**< Mode LOC4 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_CLKLOC_LOC5 0x00000005UL /**< Mode LOC5 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_CLKLOC_LOC6 0x00000006UL /**< Mode LOC6 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_CLKLOC_LOC7 0x00000007UL /**< Mode LOC7 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_CLKLOC_LOC8 0x00000008UL /**< Mode LOC8 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_CLKLOC_LOC9 0x00000009UL /**< Mode LOC9 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_CLKLOC_LOC10 0x0000000AUL /**< Mode LOC10 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_CLKLOC_LOC11 0x0000000BUL /**< Mode LOC11 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_CLKLOC_LOC12 0x0000000CUL /**< Mode LOC12 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_CLKLOC_LOC13 0x0000000DUL /**< Mode LOC13 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_CLKLOC_LOC14 0x0000000EUL /**< Mode LOC14 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_CLKLOC_LOC15 0x0000000FUL /**< Mode LOC15 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_CLKLOC_LOC16 0x00000010UL /**< Mode LOC16 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_CLKLOC_LOC17 0x00000011UL /**< Mode LOC17 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_CLKLOC_LOC18 0x00000012UL /**< Mode LOC18 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_CLKLOC_LOC19 0x00000013UL /**< Mode LOC19 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_CLKLOC_LOC20 0x00000014UL /**< Mode LOC20 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_CLKLOC_LOC21 0x00000015UL /**< Mode LOC21 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_CLKLOC_LOC22 0x00000016UL /**< Mode LOC22 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_CLKLOC_LOC23 0x00000017UL /**< Mode LOC23 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_CLKLOC_LOC24 0x00000018UL /**< Mode LOC24 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_CLKLOC_LOC25 0x00000019UL /**< Mode LOC25 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_CLKLOC_LOC26 0x0000001AUL /**< Mode LOC26 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_CLKLOC_LOC27 0x0000001BUL /**< Mode LOC27 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_CLKLOC_LOC28 0x0000001CUL /**< Mode LOC28 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_CLKLOC_LOC29 0x0000001DUL /**< Mode LOC29 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_CLKLOC_LOC30 0x0000001EUL /**< Mode LOC30 for USART_ROUTELOC0 */ #define _USART_ROUTELOC0_CLKLOC_LOC31 0x0000001FUL /**< Mode LOC31 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_CLKLOC_LOC0 (_USART_ROUTELOC0_CLKLOC_LOC0 << 24) /**< Shifted mode LOC0 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_CLKLOC_DEFAULT (_USART_ROUTELOC0_CLKLOC_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_ROUTELOC0 */ #define USART_ROUTELOC0_CLKLOC_LOC1 (_USART_ROUTELOC0_CLKLOC_LOC1 << 24) /**< Shifted mode LOC1 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_CLKLOC_LOC2 (_USART_ROUTELOC0_CLKLOC_LOC2 << 24) /**< Shifted mode LOC2 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_CLKLOC_LOC3 (_USART_ROUTELOC0_CLKLOC_LOC3 << 24) /**< Shifted mode LOC3 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_CLKLOC_LOC4 (_USART_ROUTELOC0_CLKLOC_LOC4 << 24) /**< Shifted mode LOC4 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_CLKLOC_LOC5 (_USART_ROUTELOC0_CLKLOC_LOC5 << 24) /**< Shifted mode LOC5 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_CLKLOC_LOC6 (_USART_ROUTELOC0_CLKLOC_LOC6 << 24) /**< Shifted mode LOC6 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_CLKLOC_LOC7 (_USART_ROUTELOC0_CLKLOC_LOC7 << 24) /**< Shifted mode LOC7 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_CLKLOC_LOC8 (_USART_ROUTELOC0_CLKLOC_LOC8 << 24) /**< Shifted mode LOC8 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_CLKLOC_LOC9 (_USART_ROUTELOC0_CLKLOC_LOC9 << 24) /**< Shifted mode LOC9 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_CLKLOC_LOC10 (_USART_ROUTELOC0_CLKLOC_LOC10 << 24) /**< Shifted mode LOC10 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_CLKLOC_LOC11 (_USART_ROUTELOC0_CLKLOC_LOC11 << 24) /**< Shifted mode LOC11 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_CLKLOC_LOC12 (_USART_ROUTELOC0_CLKLOC_LOC12 << 24) /**< Shifted mode LOC12 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_CLKLOC_LOC13 (_USART_ROUTELOC0_CLKLOC_LOC13 << 24) /**< Shifted mode LOC13 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_CLKLOC_LOC14 (_USART_ROUTELOC0_CLKLOC_LOC14 << 24) /**< Shifted mode LOC14 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_CLKLOC_LOC15 (_USART_ROUTELOC0_CLKLOC_LOC15 << 24) /**< Shifted mode LOC15 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_CLKLOC_LOC16 (_USART_ROUTELOC0_CLKLOC_LOC16 << 24) /**< Shifted mode LOC16 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_CLKLOC_LOC17 (_USART_ROUTELOC0_CLKLOC_LOC17 << 24) /**< Shifted mode LOC17 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_CLKLOC_LOC18 (_USART_ROUTELOC0_CLKLOC_LOC18 << 24) /**< Shifted mode LOC18 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_CLKLOC_LOC19 (_USART_ROUTELOC0_CLKLOC_LOC19 << 24) /**< Shifted mode LOC19 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_CLKLOC_LOC20 (_USART_ROUTELOC0_CLKLOC_LOC20 << 24) /**< Shifted mode LOC20 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_CLKLOC_LOC21 (_USART_ROUTELOC0_CLKLOC_LOC21 << 24) /**< Shifted mode LOC21 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_CLKLOC_LOC22 (_USART_ROUTELOC0_CLKLOC_LOC22 << 24) /**< Shifted mode LOC22 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_CLKLOC_LOC23 (_USART_ROUTELOC0_CLKLOC_LOC23 << 24) /**< Shifted mode LOC23 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_CLKLOC_LOC24 (_USART_ROUTELOC0_CLKLOC_LOC24 << 24) /**< Shifted mode LOC24 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_CLKLOC_LOC25 (_USART_ROUTELOC0_CLKLOC_LOC25 << 24) /**< Shifted mode LOC25 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_CLKLOC_LOC26 (_USART_ROUTELOC0_CLKLOC_LOC26 << 24) /**< Shifted mode LOC26 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_CLKLOC_LOC27 (_USART_ROUTELOC0_CLKLOC_LOC27 << 24) /**< Shifted mode LOC27 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_CLKLOC_LOC28 (_USART_ROUTELOC0_CLKLOC_LOC28 << 24) /**< Shifted mode LOC28 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_CLKLOC_LOC29 (_USART_ROUTELOC0_CLKLOC_LOC29 << 24) /**< Shifted mode LOC29 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_CLKLOC_LOC30 (_USART_ROUTELOC0_CLKLOC_LOC30 << 24) /**< Shifted mode LOC30 for USART_ROUTELOC0 */ #define USART_ROUTELOC0_CLKLOC_LOC31 (_USART_ROUTELOC0_CLKLOC_LOC31 << 24) /**< Shifted mode LOC31 for USART_ROUTELOC0 */ /* Bit fields for USART ROUTELOC1 */ #define _USART_ROUTELOC1_RESETVALUE 0x00000000UL /**< Default value for USART_ROUTELOC1 */ #define _USART_ROUTELOC1_MASK 0x00001F1FUL /**< Mask for USART_ROUTELOC1 */ #define _USART_ROUTELOC1_CTSLOC_SHIFT 0 /**< Shift value for USART_CTSLOC */ #define _USART_ROUTELOC1_CTSLOC_MASK 0x1FUL /**< Bit mask for USART_CTSLOC */ #define _USART_ROUTELOC1_CTSLOC_LOC0 0x00000000UL /**< Mode LOC0 for USART_ROUTELOC1 */ #define _USART_ROUTELOC1_CTSLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTELOC1 */ #define _USART_ROUTELOC1_CTSLOC_LOC1 0x00000001UL /**< Mode LOC1 for USART_ROUTELOC1 */ #define _USART_ROUTELOC1_CTSLOC_LOC2 0x00000002UL /**< Mode LOC2 for USART_ROUTELOC1 */ #define _USART_ROUTELOC1_CTSLOC_LOC3 0x00000003UL /**< Mode LOC3 for USART_ROUTELOC1 */ #define _USART_ROUTELOC1_CTSLOC_LOC4 0x00000004UL /**< Mode LOC4 for USART_ROUTELOC1 */ #define _USART_ROUTELOC1_CTSLOC_LOC5 0x00000005UL /**< Mode LOC5 for USART_ROUTELOC1 */ #define _USART_ROUTELOC1_CTSLOC_LOC6 0x00000006UL /**< Mode LOC6 for USART_ROUTELOC1 */ #define _USART_ROUTELOC1_CTSLOC_LOC7 0x00000007UL /**< Mode LOC7 for USART_ROUTELOC1 */ #define _USART_ROUTELOC1_CTSLOC_LOC8 0x00000008UL /**< Mode LOC8 for USART_ROUTELOC1 */ #define _USART_ROUTELOC1_CTSLOC_LOC9 0x00000009UL /**< Mode LOC9 for USART_ROUTELOC1 */ #define _USART_ROUTELOC1_CTSLOC_LOC10 0x0000000AUL /**< Mode LOC10 for USART_ROUTELOC1 */ #define _USART_ROUTELOC1_CTSLOC_LOC11 0x0000000BUL /**< Mode LOC11 for USART_ROUTELOC1 */ #define _USART_ROUTELOC1_CTSLOC_LOC12 0x0000000CUL /**< Mode LOC12 for USART_ROUTELOC1 */ #define _USART_ROUTELOC1_CTSLOC_LOC13 0x0000000DUL /**< Mode LOC13 for USART_ROUTELOC1 */ #define _USART_ROUTELOC1_CTSLOC_LOC14 0x0000000EUL /**< Mode LOC14 for USART_ROUTELOC1 */ #define _USART_ROUTELOC1_CTSLOC_LOC15 0x0000000FUL /**< Mode LOC15 for USART_ROUTELOC1 */ #define _USART_ROUTELOC1_CTSLOC_LOC16 0x00000010UL /**< Mode LOC16 for USART_ROUTELOC1 */ #define _USART_ROUTELOC1_CTSLOC_LOC17 0x00000011UL /**< Mode LOC17 for USART_ROUTELOC1 */ #define _USART_ROUTELOC1_CTSLOC_LOC18 0x00000012UL /**< Mode LOC18 for USART_ROUTELOC1 */ #define _USART_ROUTELOC1_CTSLOC_LOC19 0x00000013UL /**< Mode LOC19 for USART_ROUTELOC1 */ #define _USART_ROUTELOC1_CTSLOC_LOC20 0x00000014UL /**< Mode LOC20 for USART_ROUTELOC1 */ #define _USART_ROUTELOC1_CTSLOC_LOC21 0x00000015UL /**< Mode LOC21 for USART_ROUTELOC1 */ #define _USART_ROUTELOC1_CTSLOC_LOC22 0x00000016UL /**< Mode LOC22 for USART_ROUTELOC1 */ #define _USART_ROUTELOC1_CTSLOC_LOC23 0x00000017UL /**< Mode LOC23 for USART_ROUTELOC1 */ #define _USART_ROUTELOC1_CTSLOC_LOC24 0x00000018UL /**< Mode LOC24 for USART_ROUTELOC1 */ #define _USART_ROUTELOC1_CTSLOC_LOC25 0x00000019UL /**< Mode LOC25 for USART_ROUTELOC1 */ #define _USART_ROUTELOC1_CTSLOC_LOC26 0x0000001AUL /**< Mode LOC26 for USART_ROUTELOC1 */ #define _USART_ROUTELOC1_CTSLOC_LOC27 0x0000001BUL /**< Mode LOC27 for USART_ROUTELOC1 */ #define _USART_ROUTELOC1_CTSLOC_LOC28 0x0000001CUL /**< Mode LOC28 for USART_ROUTELOC1 */ #define _USART_ROUTELOC1_CTSLOC_LOC29 0x0000001DUL /**< Mode LOC29 for USART_ROUTELOC1 */ #define _USART_ROUTELOC1_CTSLOC_LOC30 0x0000001EUL /**< Mode LOC30 for USART_ROUTELOC1 */ #define _USART_ROUTELOC1_CTSLOC_LOC31 0x0000001FUL /**< Mode LOC31 for USART_ROUTELOC1 */ #define USART_ROUTELOC1_CTSLOC_LOC0 (_USART_ROUTELOC1_CTSLOC_LOC0 << 0) /**< Shifted mode LOC0 for USART_ROUTELOC1 */ #define USART_ROUTELOC1_CTSLOC_DEFAULT (_USART_ROUTELOC1_CTSLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_ROUTELOC1 */ #define USART_ROUTELOC1_CTSLOC_LOC1 (_USART_ROUTELOC1_CTSLOC_LOC1 << 0) /**< Shifted mode LOC1 for USART_ROUTELOC1 */ #define USART_ROUTELOC1_CTSLOC_LOC2 (_USART_ROUTELOC1_CTSLOC_LOC2 << 0) /**< Shifted mode LOC2 for USART_ROUTELOC1 */ #define USART_ROUTELOC1_CTSLOC_LOC3 (_USART_ROUTELOC1_CTSLOC_LOC3 << 0) /**< Shifted mode LOC3 for USART_ROUTELOC1 */ #define USART_ROUTELOC1_CTSLOC_LOC4 (_USART_ROUTELOC1_CTSLOC_LOC4 << 0) /**< Shifted mode LOC4 for USART_ROUTELOC1 */ #define USART_ROUTELOC1_CTSLOC_LOC5 (_USART_ROUTELOC1_CTSLOC_LOC5 << 0) /**< Shifted mode LOC5 for USART_ROUTELOC1 */ #define USART_ROUTELOC1_CTSLOC_LOC6 (_USART_ROUTELOC1_CTSLOC_LOC6 << 0) /**< Shifted mode LOC6 for USART_ROUTELOC1 */ #define USART_ROUTELOC1_CTSLOC_LOC7 (_USART_ROUTELOC1_CTSLOC_LOC7 << 0) /**< Shifted mode LOC7 for USART_ROUTELOC1 */ #define USART_ROUTELOC1_CTSLOC_LOC8 (_USART_ROUTELOC1_CTSLOC_LOC8 << 0) /**< Shifted mode LOC8 for USART_ROUTELOC1 */ #define USART_ROUTELOC1_CTSLOC_LOC9 (_USART_ROUTELOC1_CTSLOC_LOC9 << 0) /**< Shifted mode LOC9 for USART_ROUTELOC1 */ #define USART_ROUTELOC1_CTSLOC_LOC10 (_USART_ROUTELOC1_CTSLOC_LOC10 << 0) /**< Shifted mode LOC10 for USART_ROUTELOC1 */ #define USART_ROUTELOC1_CTSLOC_LOC11 (_USART_ROUTELOC1_CTSLOC_LOC11 << 0) /**< Shifted mode LOC11 for USART_ROUTELOC1 */ #define USART_ROUTELOC1_CTSLOC_LOC12 (_USART_ROUTELOC1_CTSLOC_LOC12 << 0) /**< Shifted mode LOC12 for USART_ROUTELOC1 */ #define USART_ROUTELOC1_CTSLOC_LOC13 (_USART_ROUTELOC1_CTSLOC_LOC13 << 0) /**< Shifted mode LOC13 for USART_ROUTELOC1 */ #define USART_ROUTELOC1_CTSLOC_LOC14 (_USART_ROUTELOC1_CTSLOC_LOC14 << 0) /**< Shifted mode LOC14 for USART_ROUTELOC1 */ #define USART_ROUTELOC1_CTSLOC_LOC15 (_USART_ROUTELOC1_CTSLOC_LOC15 << 0) /**< Shifted mode LOC15 for USART_ROUTELOC1 */ #define USART_ROUTELOC1_CTSLOC_LOC16 (_USART_ROUTELOC1_CTSLOC_LOC16 << 0) /**< Shifted mode LOC16 for USART_ROUTELOC1 */ #define USART_ROUTELOC1_CTSLOC_LOC17 (_USART_ROUTELOC1_CTSLOC_LOC17 << 0) /**< Shifted mode LOC17 for USART_ROUTELOC1 */ #define USART_ROUTELOC1_CTSLOC_LOC18 (_USART_ROUTELOC1_CTSLOC_LOC18 << 0) /**< Shifted mode LOC18 for USART_ROUTELOC1 */ #define USART_ROUTELOC1_CTSLOC_LOC19 (_USART_ROUTELOC1_CTSLOC_LOC19 << 0) /**< Shifted mode LOC19 for USART_ROUTELOC1 */ #define USART_ROUTELOC1_CTSLOC_LOC20 (_USART_ROUTELOC1_CTSLOC_LOC20 << 0) /**< Shifted mode LOC20 for USART_ROUTELOC1 */ #define USART_ROUTELOC1_CTSLOC_LOC21 (_USART_ROUTELOC1_CTSLOC_LOC21 << 0) /**< Shifted mode LOC21 for USART_ROUTELOC1 */ #define USART_ROUTELOC1_CTSLOC_LOC22 (_USART_ROUTELOC1_CTSLOC_LOC22 << 0) /**< Shifted mode LOC22 for USART_ROUTELOC1 */ #define USART_ROUTELOC1_CTSLOC_LOC23 (_USART_ROUTELOC1_CTSLOC_LOC23 << 0) /**< Shifted mode LOC23 for USART_ROUTELOC1 */ #define USART_ROUTELOC1_CTSLOC_LOC24 (_USART_ROUTELOC1_CTSLOC_LOC24 << 0) /**< Shifted mode LOC24 for USART_ROUTELOC1 */ #define USART_ROUTELOC1_CTSLOC_LOC25 (_USART_ROUTELOC1_CTSLOC_LOC25 << 0) /**< Shifted mode LOC25 for USART_ROUTELOC1 */ #define USART_ROUTELOC1_CTSLOC_LOC26 (_USART_ROUTELOC1_CTSLOC_LOC26 << 0) /**< Shifted mode LOC26 for USART_ROUTELOC1 */ #define USART_ROUTELOC1_CTSLOC_LOC27 (_USART_ROUTELOC1_CTSLOC_LOC27 << 0) /**< Shifted mode LOC27 for USART_ROUTELOC1 */ #define USART_ROUTELOC1_CTSLOC_LOC28 (_USART_ROUTELOC1_CTSLOC_LOC28 << 0) /**< Shifted mode LOC28 for USART_ROUTELOC1 */ #define USART_ROUTELOC1_CTSLOC_LOC29 (_USART_ROUTELOC1_CTSLOC_LOC29 << 0) /**< Shifted mode LOC29 for USART_ROUTELOC1 */ #define USART_ROUTELOC1_CTSLOC_LOC30 (_USART_ROUTELOC1_CTSLOC_LOC30 << 0) /**< Shifted mode LOC30 for USART_ROUTELOC1 */ #define USART_ROUTELOC1_CTSLOC_LOC31 (_USART_ROUTELOC1_CTSLOC_LOC31 << 0) /**< Shifted mode LOC31 for USART_ROUTELOC1 */ #define _USART_ROUTELOC1_RTSLOC_SHIFT 8 /**< Shift value for USART_RTSLOC */ #define _USART_ROUTELOC1_RTSLOC_MASK 0x1F00UL /**< Bit mask for USART_RTSLOC */ #define _USART_ROUTELOC1_RTSLOC_LOC0 0x00000000UL /**< Mode LOC0 for USART_ROUTELOC1 */ #define _USART_ROUTELOC1_RTSLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTELOC1 */ #define _USART_ROUTELOC1_RTSLOC_LOC1 0x00000001UL /**< Mode LOC1 for USART_ROUTELOC1 */ #define _USART_ROUTELOC1_RTSLOC_LOC2 0x00000002UL /**< Mode LOC2 for USART_ROUTELOC1 */ #define _USART_ROUTELOC1_RTSLOC_LOC3 0x00000003UL /**< Mode LOC3 for USART_ROUTELOC1 */ #define _USART_ROUTELOC1_RTSLOC_LOC4 0x00000004UL /**< Mode LOC4 for USART_ROUTELOC1 */ #define _USART_ROUTELOC1_RTSLOC_LOC5 0x00000005UL /**< Mode LOC5 for USART_ROUTELOC1 */ #define _USART_ROUTELOC1_RTSLOC_LOC6 0x00000006UL /**< Mode LOC6 for USART_ROUTELOC1 */ #define _USART_ROUTELOC1_RTSLOC_LOC7 0x00000007UL /**< Mode LOC7 for USART_ROUTELOC1 */ #define _USART_ROUTELOC1_RTSLOC_LOC8 0x00000008UL /**< Mode LOC8 for USART_ROUTELOC1 */ #define _USART_ROUTELOC1_RTSLOC_LOC9 0x00000009UL /**< Mode LOC9 for USART_ROUTELOC1 */ #define _USART_ROUTELOC1_RTSLOC_LOC10 0x0000000AUL /**< Mode LOC10 for USART_ROUTELOC1 */ #define _USART_ROUTELOC1_RTSLOC_LOC11 0x0000000BUL /**< Mode LOC11 for USART_ROUTELOC1 */ #define _USART_ROUTELOC1_RTSLOC_LOC12 0x0000000CUL /**< Mode LOC12 for USART_ROUTELOC1 */ #define _USART_ROUTELOC1_RTSLOC_LOC13 0x0000000DUL /**< Mode LOC13 for USART_ROUTELOC1 */ #define _USART_ROUTELOC1_RTSLOC_LOC14 0x0000000EUL /**< Mode LOC14 for USART_ROUTELOC1 */ #define _USART_ROUTELOC1_RTSLOC_LOC15 0x0000000FUL /**< Mode LOC15 for USART_ROUTELOC1 */ #define _USART_ROUTELOC1_RTSLOC_LOC16 0x00000010UL /**< Mode LOC16 for USART_ROUTELOC1 */ #define _USART_ROUTELOC1_RTSLOC_LOC17 0x00000011UL /**< Mode LOC17 for USART_ROUTELOC1 */ #define _USART_ROUTELOC1_RTSLOC_LOC18 0x00000012UL /**< Mode LOC18 for USART_ROUTELOC1 */ #define _USART_ROUTELOC1_RTSLOC_LOC19 0x00000013UL /**< Mode LOC19 for USART_ROUTELOC1 */ #define _USART_ROUTELOC1_RTSLOC_LOC20 0x00000014UL /**< Mode LOC20 for USART_ROUTELOC1 */ #define _USART_ROUTELOC1_RTSLOC_LOC21 0x00000015UL /**< Mode LOC21 for USART_ROUTELOC1 */ #define _USART_ROUTELOC1_RTSLOC_LOC22 0x00000016UL /**< Mode LOC22 for USART_ROUTELOC1 */ #define _USART_ROUTELOC1_RTSLOC_LOC23 0x00000017UL /**< Mode LOC23 for USART_ROUTELOC1 */ #define _USART_ROUTELOC1_RTSLOC_LOC24 0x00000018UL /**< Mode LOC24 for USART_ROUTELOC1 */ #define _USART_ROUTELOC1_RTSLOC_LOC25 0x00000019UL /**< Mode LOC25 for USART_ROUTELOC1 */ #define _USART_ROUTELOC1_RTSLOC_LOC26 0x0000001AUL /**< Mode LOC26 for USART_ROUTELOC1 */ #define _USART_ROUTELOC1_RTSLOC_LOC27 0x0000001BUL /**< Mode LOC27 for USART_ROUTELOC1 */ #define _USART_ROUTELOC1_RTSLOC_LOC28 0x0000001CUL /**< Mode LOC28 for USART_ROUTELOC1 */ #define _USART_ROUTELOC1_RTSLOC_LOC29 0x0000001DUL /**< Mode LOC29 for USART_ROUTELOC1 */ #define _USART_ROUTELOC1_RTSLOC_LOC30 0x0000001EUL /**< Mode LOC30 for USART_ROUTELOC1 */ #define _USART_ROUTELOC1_RTSLOC_LOC31 0x0000001FUL /**< Mode LOC31 for USART_ROUTELOC1 */ #define USART_ROUTELOC1_RTSLOC_LOC0 (_USART_ROUTELOC1_RTSLOC_LOC0 << 8) /**< Shifted mode LOC0 for USART_ROUTELOC1 */ #define USART_ROUTELOC1_RTSLOC_DEFAULT (_USART_ROUTELOC1_RTSLOC_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_ROUTELOC1 */ #define USART_ROUTELOC1_RTSLOC_LOC1 (_USART_ROUTELOC1_RTSLOC_LOC1 << 8) /**< Shifted mode LOC1 for USART_ROUTELOC1 */ #define USART_ROUTELOC1_RTSLOC_LOC2 (_USART_ROUTELOC1_RTSLOC_LOC2 << 8) /**< Shifted mode LOC2 for USART_ROUTELOC1 */ #define USART_ROUTELOC1_RTSLOC_LOC3 (_USART_ROUTELOC1_RTSLOC_LOC3 << 8) /**< Shifted mode LOC3 for USART_ROUTELOC1 */ #define USART_ROUTELOC1_RTSLOC_LOC4 (_USART_ROUTELOC1_RTSLOC_LOC4 << 8) /**< Shifted mode LOC4 for USART_ROUTELOC1 */ #define USART_ROUTELOC1_RTSLOC_LOC5 (_USART_ROUTELOC1_RTSLOC_LOC5 << 8) /**< Shifted mode LOC5 for USART_ROUTELOC1 */ #define USART_ROUTELOC1_RTSLOC_LOC6 (_USART_ROUTELOC1_RTSLOC_LOC6 << 8) /**< Shifted mode LOC6 for USART_ROUTELOC1 */ #define USART_ROUTELOC1_RTSLOC_LOC7 (_USART_ROUTELOC1_RTSLOC_LOC7 << 8) /**< Shifted mode LOC7 for USART_ROUTELOC1 */ #define USART_ROUTELOC1_RTSLOC_LOC8 (_USART_ROUTELOC1_RTSLOC_LOC8 << 8) /**< Shifted mode LOC8 for USART_ROUTELOC1 */ #define USART_ROUTELOC1_RTSLOC_LOC9 (_USART_ROUTELOC1_RTSLOC_LOC9 << 8) /**< Shifted mode LOC9 for USART_ROUTELOC1 */ #define USART_ROUTELOC1_RTSLOC_LOC10 (_USART_ROUTELOC1_RTSLOC_LOC10 << 8) /**< Shifted mode LOC10 for USART_ROUTELOC1 */ #define USART_ROUTELOC1_RTSLOC_LOC11 (_USART_ROUTELOC1_RTSLOC_LOC11 << 8) /**< Shifted mode LOC11 for USART_ROUTELOC1 */ #define USART_ROUTELOC1_RTSLOC_LOC12 (_USART_ROUTELOC1_RTSLOC_LOC12 << 8) /**< Shifted mode LOC12 for USART_ROUTELOC1 */ #define USART_ROUTELOC1_RTSLOC_LOC13 (_USART_ROUTELOC1_RTSLOC_LOC13 << 8) /**< Shifted mode LOC13 for USART_ROUTELOC1 */ #define USART_ROUTELOC1_RTSLOC_LOC14 (_USART_ROUTELOC1_RTSLOC_LOC14 << 8) /**< Shifted mode LOC14 for USART_ROUTELOC1 */ #define USART_ROUTELOC1_RTSLOC_LOC15 (_USART_ROUTELOC1_RTSLOC_LOC15 << 8) /**< Shifted mode LOC15 for USART_ROUTELOC1 */ #define USART_ROUTELOC1_RTSLOC_LOC16 (_USART_ROUTELOC1_RTSLOC_LOC16 << 8) /**< Shifted mode LOC16 for USART_ROUTELOC1 */ #define USART_ROUTELOC1_RTSLOC_LOC17 (_USART_ROUTELOC1_RTSLOC_LOC17 << 8) /**< Shifted mode LOC17 for USART_ROUTELOC1 */ #define USART_ROUTELOC1_RTSLOC_LOC18 (_USART_ROUTELOC1_RTSLOC_LOC18 << 8) /**< Shifted mode LOC18 for USART_ROUTELOC1 */ #define USART_ROUTELOC1_RTSLOC_LOC19 (_USART_ROUTELOC1_RTSLOC_LOC19 << 8) /**< Shifted mode LOC19 for USART_ROUTELOC1 */ #define USART_ROUTELOC1_RTSLOC_LOC20 (_USART_ROUTELOC1_RTSLOC_LOC20 << 8) /**< Shifted mode LOC20 for USART_ROUTELOC1 */ #define USART_ROUTELOC1_RTSLOC_LOC21 (_USART_ROUTELOC1_RTSLOC_LOC21 << 8) /**< Shifted mode LOC21 for USART_ROUTELOC1 */ #define USART_ROUTELOC1_RTSLOC_LOC22 (_USART_ROUTELOC1_RTSLOC_LOC22 << 8) /**< Shifted mode LOC22 for USART_ROUTELOC1 */ #define USART_ROUTELOC1_RTSLOC_LOC23 (_USART_ROUTELOC1_RTSLOC_LOC23 << 8) /**< Shifted mode LOC23 for USART_ROUTELOC1 */ #define USART_ROUTELOC1_RTSLOC_LOC24 (_USART_ROUTELOC1_RTSLOC_LOC24 << 8) /**< Shifted mode LOC24 for USART_ROUTELOC1 */ #define USART_ROUTELOC1_RTSLOC_LOC25 (_USART_ROUTELOC1_RTSLOC_LOC25 << 8) /**< Shifted mode LOC25 for USART_ROUTELOC1 */ #define USART_ROUTELOC1_RTSLOC_LOC26 (_USART_ROUTELOC1_RTSLOC_LOC26 << 8) /**< Shifted mode LOC26 for USART_ROUTELOC1 */ #define USART_ROUTELOC1_RTSLOC_LOC27 (_USART_ROUTELOC1_RTSLOC_LOC27 << 8) /**< Shifted mode LOC27 for USART_ROUTELOC1 */ #define USART_ROUTELOC1_RTSLOC_LOC28 (_USART_ROUTELOC1_RTSLOC_LOC28 << 8) /**< Shifted mode LOC28 for USART_ROUTELOC1 */ #define USART_ROUTELOC1_RTSLOC_LOC29 (_USART_ROUTELOC1_RTSLOC_LOC29 << 8) /**< Shifted mode LOC29 for USART_ROUTELOC1 */ #define USART_ROUTELOC1_RTSLOC_LOC30 (_USART_ROUTELOC1_RTSLOC_LOC30 << 8) /**< Shifted mode LOC30 for USART_ROUTELOC1 */ #define USART_ROUTELOC1_RTSLOC_LOC31 (_USART_ROUTELOC1_RTSLOC_LOC31 << 8) /**< Shifted mode LOC31 for USART_ROUTELOC1 */ /** @} */ /** @} End of group EFR32MG12P_USART */ /** @} End of group Parts */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_vdac.h.
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/***************************************************************************//** * @file * @brief EFR32MG12P_VDAC register and bit field definitions * @version 5.7.0 ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * SPDX-License-Identifier: Zlib * * The licensor of this software is Silicon Laboratories Inc. * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be * appreciated but is not required. * 2. Altered source versions must be plainly marked as such, and must not be * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * ******************************************************************************/ #if defined(__ICCARM__) #pragma system_include /* Treat file as system include file. */ #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang system_header /* Treat file as system include file. */ #endif /***************************************************************************//** * @addtogroup Parts * @{ ******************************************************************************/ /***************************************************************************//** * @defgroup EFR32MG12P_VDAC VDAC * @{ * @brief EFR32MG12P_VDAC Register Declaration ******************************************************************************/ /** VDAC Register Declaration */ typedef struct { __IOM uint32_t CTRL; /**< Control Register */ __IM uint32_t STATUS; /**< Status Register */ __IOM uint32_t CH0CTRL; /**< Channel 0 Control Register */ __IOM uint32_t CH1CTRL; /**< Channel 1 Control Register */ __IOM uint32_t CMD; /**< Command Register */ __IM uint32_t IF; /**< Interrupt Flag Register */ __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ __IOM uint32_t IEN; /**< Interrupt Enable Register */ __IOM uint32_t CH0DATA; /**< Channel 0 Data Register */ __IOM uint32_t CH1DATA; /**< Channel 1 Data Register */ __IOM uint32_t COMBDATA; /**< Combined Data Register */ __IOM uint32_t CAL; /**< Calibration Register */ uint32_t RESERVED0[27U]; /**< Reserved registers */ VDAC_OPA_TypeDef OPA[3U]; /**< OPA Registers */ } VDAC_TypeDef; /** @} */ /***************************************************************************//** * @addtogroup EFR32MG12P_VDAC * @{ * @defgroup EFR32MG12P_VDAC_BitFields VDAC Bit Fields * @{ ******************************************************************************/ /* Bit fields for VDAC CTRL */ #define _VDAC_CTRL_RESETVALUE 0x00000000UL /**< Default value for VDAC_CTRL */ #define _VDAC_CTRL_MASK 0x937F0771UL /**< Mask for VDAC_CTRL */ #define VDAC_CTRL_DIFF (0x1UL << 0) /**< Differential Mode */ #define _VDAC_CTRL_DIFF_SHIFT 0 /**< Shift value for VDAC_DIFF */ #define _VDAC_CTRL_DIFF_MASK 0x1UL /**< Bit mask for VDAC_DIFF */ #define _VDAC_CTRL_DIFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CTRL */ #define VDAC_CTRL_DIFF_DEFAULT (_VDAC_CTRL_DIFF_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CTRL */ #define VDAC_CTRL_SINEMODE (0x1UL << 4) /**< Sine Mode */ #define _VDAC_CTRL_SINEMODE_SHIFT 4 /**< Shift value for VDAC_SINEMODE */ #define _VDAC_CTRL_SINEMODE_MASK 0x10UL /**< Bit mask for VDAC_SINEMODE */ #define _VDAC_CTRL_SINEMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CTRL */ #define VDAC_CTRL_SINEMODE_DEFAULT (_VDAC_CTRL_SINEMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_CTRL */ #define VDAC_CTRL_OUTENPRS (0x1UL << 5) /**< PRS Controlled Output Enable */ #define _VDAC_CTRL_OUTENPRS_SHIFT 5 /**< Shift value for VDAC_OUTENPRS */ #define _VDAC_CTRL_OUTENPRS_MASK 0x20UL /**< Bit mask for VDAC_OUTENPRS */ #define _VDAC_CTRL_OUTENPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CTRL */ #define VDAC_CTRL_OUTENPRS_DEFAULT (_VDAC_CTRL_OUTENPRS_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_CTRL */ #define VDAC_CTRL_CH0PRESCRST (0x1UL << 6) /**< Channel 0 Start Reset Prescaler */ #define _VDAC_CTRL_CH0PRESCRST_SHIFT 6 /**< Shift value for VDAC_CH0PRESCRST */ #define _VDAC_CTRL_CH0PRESCRST_MASK 0x40UL /**< Bit mask for VDAC_CH0PRESCRST */ #define _VDAC_CTRL_CH0PRESCRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CTRL */ #define VDAC_CTRL_CH0PRESCRST_DEFAULT (_VDAC_CTRL_CH0PRESCRST_DEFAULT << 6) /**< Shifted mode DEFAULT for VDAC_CTRL */ #define _VDAC_CTRL_REFSEL_SHIFT 8 /**< Shift value for VDAC_REFSEL */ #define _VDAC_CTRL_REFSEL_MASK 0x700UL /**< Bit mask for VDAC_REFSEL */ #define _VDAC_CTRL_REFSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CTRL */ #define _VDAC_CTRL_REFSEL_1V25LN 0x00000000UL /**< Mode 1V25LN for VDAC_CTRL */ #define _VDAC_CTRL_REFSEL_2V5LN 0x00000001UL /**< Mode 2V5LN for VDAC_CTRL */ #define _VDAC_CTRL_REFSEL_1V25 0x00000002UL /**< Mode 1V25 for VDAC_CTRL */ #define _VDAC_CTRL_REFSEL_2V5 0x00000003UL /**< Mode 2V5 for VDAC_CTRL */ #define _VDAC_CTRL_REFSEL_VDD 0x00000004UL /**< Mode VDD for VDAC_CTRL */ #define _VDAC_CTRL_REFSEL_EXT 0x00000006UL /**< Mode EXT for VDAC_CTRL */ #define VDAC_CTRL_REFSEL_DEFAULT (_VDAC_CTRL_REFSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_CTRL */ #define VDAC_CTRL_REFSEL_1V25LN (_VDAC_CTRL_REFSEL_1V25LN << 8) /**< Shifted mode 1V25LN for VDAC_CTRL */ #define VDAC_CTRL_REFSEL_2V5LN (_VDAC_CTRL_REFSEL_2V5LN << 8) /**< Shifted mode 2V5LN for VDAC_CTRL */ #define VDAC_CTRL_REFSEL_1V25 (_VDAC_CTRL_REFSEL_1V25 << 8) /**< Shifted mode 1V25 for VDAC_CTRL */ #define VDAC_CTRL_REFSEL_2V5 (_VDAC_CTRL_REFSEL_2V5 << 8) /**< Shifted mode 2V5 for VDAC_CTRL */ #define VDAC_CTRL_REFSEL_VDD (_VDAC_CTRL_REFSEL_VDD << 8) /**< Shifted mode VDD for VDAC_CTRL */ #define VDAC_CTRL_REFSEL_EXT (_VDAC_CTRL_REFSEL_EXT << 8) /**< Shifted mode EXT for VDAC_CTRL */ #define _VDAC_CTRL_PRESC_SHIFT 16 /**< Shift value for VDAC_PRESC */ #define _VDAC_CTRL_PRESC_MASK 0x7F0000UL /**< Bit mask for VDAC_PRESC */ #define _VDAC_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CTRL */ #define _VDAC_CTRL_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for VDAC_CTRL */ #define VDAC_CTRL_PRESC_DEFAULT (_VDAC_CTRL_PRESC_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_CTRL */ #define VDAC_CTRL_PRESC_NODIVISION (_VDAC_CTRL_PRESC_NODIVISION << 16) /**< Shifted mode NODIVISION for VDAC_CTRL */ #define _VDAC_CTRL_REFRESHPERIOD_SHIFT 24 /**< Shift value for VDAC_REFRESHPERIOD */ #define _VDAC_CTRL_REFRESHPERIOD_MASK 0x3000000UL /**< Bit mask for VDAC_REFRESHPERIOD */ #define _VDAC_CTRL_REFRESHPERIOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CTRL */ #define _VDAC_CTRL_REFRESHPERIOD_8CYCLES 0x00000000UL /**< Mode 8CYCLES for VDAC_CTRL */ #define _VDAC_CTRL_REFRESHPERIOD_16CYCLES 0x00000001UL /**< Mode 16CYCLES for VDAC_CTRL */ #define _VDAC_CTRL_REFRESHPERIOD_32CYCLES 0x00000002UL /**< Mode 32CYCLES for VDAC_CTRL */ #define _VDAC_CTRL_REFRESHPERIOD_64CYCLES 0x00000003UL /**< Mode 64CYCLES for VDAC_CTRL */ #define VDAC_CTRL_REFRESHPERIOD_DEFAULT (_VDAC_CTRL_REFRESHPERIOD_DEFAULT << 24) /**< Shifted mode DEFAULT for VDAC_CTRL */ #define VDAC_CTRL_REFRESHPERIOD_8CYCLES (_VDAC_CTRL_REFRESHPERIOD_8CYCLES << 24) /**< Shifted mode 8CYCLES for VDAC_CTRL */ #define VDAC_CTRL_REFRESHPERIOD_16CYCLES (_VDAC_CTRL_REFRESHPERIOD_16CYCLES << 24) /**< Shifted mode 16CYCLES for VDAC_CTRL */ #define VDAC_CTRL_REFRESHPERIOD_32CYCLES (_VDAC_CTRL_REFRESHPERIOD_32CYCLES << 24) /**< Shifted mode 32CYCLES for VDAC_CTRL */ #define VDAC_CTRL_REFRESHPERIOD_64CYCLES (_VDAC_CTRL_REFRESHPERIOD_64CYCLES << 24) /**< Shifted mode 64CYCLES for VDAC_CTRL */ #define VDAC_CTRL_WARMUPMODE (0x1UL << 28) /**< Warm-up Mode */ #define _VDAC_CTRL_WARMUPMODE_SHIFT 28 /**< Shift value for VDAC_WARMUPMODE */ #define _VDAC_CTRL_WARMUPMODE_MASK 0x10000000UL /**< Bit mask for VDAC_WARMUPMODE */ #define _VDAC_CTRL_WARMUPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CTRL */ #define _VDAC_CTRL_WARMUPMODE_NORMAL 0x00000000UL /**< Mode NORMAL for VDAC_CTRL */ #define _VDAC_CTRL_WARMUPMODE_KEEPINSTANDBY 0x00000001UL /**< Mode KEEPINSTANDBY for VDAC_CTRL */ #define VDAC_CTRL_WARMUPMODE_DEFAULT (_VDAC_CTRL_WARMUPMODE_DEFAULT << 28) /**< Shifted mode DEFAULT for VDAC_CTRL */ #define VDAC_CTRL_WARMUPMODE_NORMAL (_VDAC_CTRL_WARMUPMODE_NORMAL << 28) /**< Shifted mode NORMAL for VDAC_CTRL */ #define VDAC_CTRL_WARMUPMODE_KEEPINSTANDBY (_VDAC_CTRL_WARMUPMODE_KEEPINSTANDBY << 28) /**< Shifted mode KEEPINSTANDBY for VDAC_CTRL */ #define VDAC_CTRL_DACCLKMODE (0x1UL << 31) /**< Clock Mode */ #define _VDAC_CTRL_DACCLKMODE_SHIFT 31 /**< Shift value for VDAC_DACCLKMODE */ #define _VDAC_CTRL_DACCLKMODE_MASK 0x80000000UL /**< Bit mask for VDAC_DACCLKMODE */ #define _VDAC_CTRL_DACCLKMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CTRL */ #define _VDAC_CTRL_DACCLKMODE_SYNC 0x00000000UL /**< Mode SYNC for VDAC_CTRL */ #define _VDAC_CTRL_DACCLKMODE_ASYNC 0x00000001UL /**< Mode ASYNC for VDAC_CTRL */ #define VDAC_CTRL_DACCLKMODE_DEFAULT (_VDAC_CTRL_DACCLKMODE_DEFAULT << 31) /**< Shifted mode DEFAULT for VDAC_CTRL */ #define VDAC_CTRL_DACCLKMODE_SYNC (_VDAC_CTRL_DACCLKMODE_SYNC << 31) /**< Shifted mode SYNC for VDAC_CTRL */ #define VDAC_CTRL_DACCLKMODE_ASYNC (_VDAC_CTRL_DACCLKMODE_ASYNC << 31) /**< Shifted mode ASYNC for VDAC_CTRL */ /* Bit fields for VDAC STATUS */ #define _VDAC_STATUS_RESETVALUE 0x0000000CUL /**< Default value for VDAC_STATUS */ #define _VDAC_STATUS_MASK 0x7777003FUL /**< Mask for VDAC_STATUS */ #define VDAC_STATUS_CH0ENS (0x1UL << 0) /**< Channel 0 Enabled Status */ #define _VDAC_STATUS_CH0ENS_SHIFT 0 /**< Shift value for VDAC_CH0ENS */ #define _VDAC_STATUS_CH0ENS_MASK 0x1UL /**< Bit mask for VDAC_CH0ENS */ #define _VDAC_STATUS_CH0ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ #define VDAC_STATUS_CH0ENS_DEFAULT (_VDAC_STATUS_CH0ENS_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_STATUS */ #define VDAC_STATUS_CH1ENS (0x1UL << 1) /**< Channel 1 Enabled Status */ #define _VDAC_STATUS_CH1ENS_SHIFT 1 /**< Shift value for VDAC_CH1ENS */ #define _VDAC_STATUS_CH1ENS_MASK 0x2UL /**< Bit mask for VDAC_CH1ENS */ #define _VDAC_STATUS_CH1ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ #define VDAC_STATUS_CH1ENS_DEFAULT (_VDAC_STATUS_CH1ENS_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_STATUS */ #define VDAC_STATUS_CH0BL (0x1UL << 2) /**< Channel 0 Buffer Level */ #define _VDAC_STATUS_CH0BL_SHIFT 2 /**< Shift value for VDAC_CH0BL */ #define _VDAC_STATUS_CH0BL_MASK 0x4UL /**< Bit mask for VDAC_CH0BL */ #define _VDAC_STATUS_CH0BL_DEFAULT 0x00000001UL /**< Mode DEFAULT for VDAC_STATUS */ #define VDAC_STATUS_CH0BL_DEFAULT (_VDAC_STATUS_CH0BL_DEFAULT << 2) /**< Shifted mode DEFAULT for VDAC_STATUS */ #define VDAC_STATUS_CH1BL (0x1UL << 3) /**< Channel 1 Buffer Level */ #define _VDAC_STATUS_CH1BL_SHIFT 3 /**< Shift value for VDAC_CH1BL */ #define _VDAC_STATUS_CH1BL_MASK 0x8UL /**< Bit mask for VDAC_CH1BL */ #define _VDAC_STATUS_CH1BL_DEFAULT 0x00000001UL /**< Mode DEFAULT for VDAC_STATUS */ #define VDAC_STATUS_CH1BL_DEFAULT (_VDAC_STATUS_CH1BL_DEFAULT << 3) /**< Shifted mode DEFAULT for VDAC_STATUS */ #define VDAC_STATUS_CH0WARM (0x1UL << 4) /**< Channel 0 Warm */ #define _VDAC_STATUS_CH0WARM_SHIFT 4 /**< Shift value for VDAC_CH0WARM */ #define _VDAC_STATUS_CH0WARM_MASK 0x10UL /**< Bit mask for VDAC_CH0WARM */ #define _VDAC_STATUS_CH0WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ #define VDAC_STATUS_CH0WARM_DEFAULT (_VDAC_STATUS_CH0WARM_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_STATUS */ #define VDAC_STATUS_CH1WARM (0x1UL << 5) /**< Channel 1 Warm */ #define _VDAC_STATUS_CH1WARM_SHIFT 5 /**< Shift value for VDAC_CH1WARM */ #define _VDAC_STATUS_CH1WARM_MASK 0x20UL /**< Bit mask for VDAC_CH1WARM */ #define _VDAC_STATUS_CH1WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ #define VDAC_STATUS_CH1WARM_DEFAULT (_VDAC_STATUS_CH1WARM_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_STATUS */ #define VDAC_STATUS_OPA0APORTCONFLICT (0x1UL << 16) /**< OPA0 Bus Conflict Output */ #define _VDAC_STATUS_OPA0APORTCONFLICT_SHIFT 16 /**< Shift value for VDAC_OPA0APORTCONFLICT */ #define _VDAC_STATUS_OPA0APORTCONFLICT_MASK 0x10000UL /**< Bit mask for VDAC_OPA0APORTCONFLICT */ #define _VDAC_STATUS_OPA0APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ #define VDAC_STATUS_OPA0APORTCONFLICT_DEFAULT (_VDAC_STATUS_OPA0APORTCONFLICT_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_STATUS */ #define VDAC_STATUS_OPA1APORTCONFLICT (0x1UL << 17) /**< OPA1 Bus Conflict Output */ #define _VDAC_STATUS_OPA1APORTCONFLICT_SHIFT 17 /**< Shift value for VDAC_OPA1APORTCONFLICT */ #define _VDAC_STATUS_OPA1APORTCONFLICT_MASK 0x20000UL /**< Bit mask for VDAC_OPA1APORTCONFLICT */ #define _VDAC_STATUS_OPA1APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ #define VDAC_STATUS_OPA1APORTCONFLICT_DEFAULT (_VDAC_STATUS_OPA1APORTCONFLICT_DEFAULT << 17) /**< Shifted mode DEFAULT for VDAC_STATUS */ #define VDAC_STATUS_OPA2APORTCONFLICT (0x1UL << 18) /**< OPA2 Bus Conflict Output */ #define _VDAC_STATUS_OPA2APORTCONFLICT_SHIFT 18 /**< Shift value for VDAC_OPA2APORTCONFLICT */ #define _VDAC_STATUS_OPA2APORTCONFLICT_MASK 0x40000UL /**< Bit mask for VDAC_OPA2APORTCONFLICT */ #define _VDAC_STATUS_OPA2APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ #define VDAC_STATUS_OPA2APORTCONFLICT_DEFAULT (_VDAC_STATUS_OPA2APORTCONFLICT_DEFAULT << 18) /**< Shifted mode DEFAULT for VDAC_STATUS */ #define VDAC_STATUS_OPA0ENS (0x1UL << 20) /**< OPA0 Enabled Status */ #define _VDAC_STATUS_OPA0ENS_SHIFT 20 /**< Shift value for VDAC_OPA0ENS */ #define _VDAC_STATUS_OPA0ENS_MASK 0x100000UL /**< Bit mask for VDAC_OPA0ENS */ #define _VDAC_STATUS_OPA0ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ #define VDAC_STATUS_OPA0ENS_DEFAULT (_VDAC_STATUS_OPA0ENS_DEFAULT << 20) /**< Shifted mode DEFAULT for VDAC_STATUS */ #define VDAC_STATUS_OPA1ENS (0x1UL << 21) /**< OPA1 Enabled Status */ #define _VDAC_STATUS_OPA1ENS_SHIFT 21 /**< Shift value for VDAC_OPA1ENS */ #define _VDAC_STATUS_OPA1ENS_MASK 0x200000UL /**< Bit mask for VDAC_OPA1ENS */ #define _VDAC_STATUS_OPA1ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ #define VDAC_STATUS_OPA1ENS_DEFAULT (_VDAC_STATUS_OPA1ENS_DEFAULT << 21) /**< Shifted mode DEFAULT for VDAC_STATUS */ #define VDAC_STATUS_OPA2ENS (0x1UL << 22) /**< OPA2 Enabled Status */ #define _VDAC_STATUS_OPA2ENS_SHIFT 22 /**< Shift value for VDAC_OPA2ENS */ #define _VDAC_STATUS_OPA2ENS_MASK 0x400000UL /**< Bit mask for VDAC_OPA2ENS */ #define _VDAC_STATUS_OPA2ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ #define VDAC_STATUS_OPA2ENS_DEFAULT (_VDAC_STATUS_OPA2ENS_DEFAULT << 22) /**< Shifted mode DEFAULT for VDAC_STATUS */ #define VDAC_STATUS_OPA0WARM (0x1UL << 24) /**< OPA0 Warm Status */ #define _VDAC_STATUS_OPA0WARM_SHIFT 24 /**< Shift value for VDAC_OPA0WARM */ #define _VDAC_STATUS_OPA0WARM_MASK 0x1000000UL /**< Bit mask for VDAC_OPA0WARM */ #define _VDAC_STATUS_OPA0WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ #define VDAC_STATUS_OPA0WARM_DEFAULT (_VDAC_STATUS_OPA0WARM_DEFAULT << 24) /**< Shifted mode DEFAULT for VDAC_STATUS */ #define VDAC_STATUS_OPA1WARM (0x1UL << 25) /**< OPA1 Warm Status */ #define _VDAC_STATUS_OPA1WARM_SHIFT 25 /**< Shift value for VDAC_OPA1WARM */ #define _VDAC_STATUS_OPA1WARM_MASK 0x2000000UL /**< Bit mask for VDAC_OPA1WARM */ #define _VDAC_STATUS_OPA1WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ #define VDAC_STATUS_OPA1WARM_DEFAULT (_VDAC_STATUS_OPA1WARM_DEFAULT << 25) /**< Shifted mode DEFAULT for VDAC_STATUS */ #define VDAC_STATUS_OPA2WARM (0x1UL << 26) /**< OPA2 Warm Status */ #define _VDAC_STATUS_OPA2WARM_SHIFT 26 /**< Shift value for VDAC_OPA2WARM */ #define _VDAC_STATUS_OPA2WARM_MASK 0x4000000UL /**< Bit mask for VDAC_OPA2WARM */ #define _VDAC_STATUS_OPA2WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ #define VDAC_STATUS_OPA2WARM_DEFAULT (_VDAC_STATUS_OPA2WARM_DEFAULT << 26) /**< Shifted mode DEFAULT for VDAC_STATUS */ #define VDAC_STATUS_OPA0OUTVALID (0x1UL << 28) /**< OPA0 Output Valid Status */ #define _VDAC_STATUS_OPA0OUTVALID_SHIFT 28 /**< Shift value for VDAC_OPA0OUTVALID */ #define _VDAC_STATUS_OPA0OUTVALID_MASK 0x10000000UL /**< Bit mask for VDAC_OPA0OUTVALID */ #define _VDAC_STATUS_OPA0OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ #define VDAC_STATUS_OPA0OUTVALID_DEFAULT (_VDAC_STATUS_OPA0OUTVALID_DEFAULT << 28) /**< Shifted mode DEFAULT for VDAC_STATUS */ #define VDAC_STATUS_OPA1OUTVALID (0x1UL << 29) /**< OPA1 Output Valid Status */ #define _VDAC_STATUS_OPA1OUTVALID_SHIFT 29 /**< Shift value for VDAC_OPA1OUTVALID */ #define _VDAC_STATUS_OPA1OUTVALID_MASK 0x20000000UL /**< Bit mask for VDAC_OPA1OUTVALID */ #define _VDAC_STATUS_OPA1OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ #define VDAC_STATUS_OPA1OUTVALID_DEFAULT (_VDAC_STATUS_OPA1OUTVALID_DEFAULT << 29) /**< Shifted mode DEFAULT for VDAC_STATUS */ #define VDAC_STATUS_OPA2OUTVALID (0x1UL << 30) /**< OPA2 Output Valid Status */ #define _VDAC_STATUS_OPA2OUTVALID_SHIFT 30 /**< Shift value for VDAC_OPA2OUTVALID */ #define _VDAC_STATUS_OPA2OUTVALID_MASK 0x40000000UL /**< Bit mask for VDAC_OPA2OUTVALID */ #define _VDAC_STATUS_OPA2OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ #define VDAC_STATUS_OPA2OUTVALID_DEFAULT (_VDAC_STATUS_OPA2OUTVALID_DEFAULT << 30) /**< Shifted mode DEFAULT for VDAC_STATUS */ /* Bit fields for VDAC CH0CTRL */ #define _VDAC_CH0CTRL_RESETVALUE 0x00000000UL /**< Default value for VDAC_CH0CTRL */ #define _VDAC_CH0CTRL_MASK 0x0000F171UL /**< Mask for VDAC_CH0CTRL */ #define VDAC_CH0CTRL_CONVMODE (0x1UL << 0) /**< Conversion Mode */ #define _VDAC_CH0CTRL_CONVMODE_SHIFT 0 /**< Shift value for VDAC_CONVMODE */ #define _VDAC_CH0CTRL_CONVMODE_MASK 0x1UL /**< Bit mask for VDAC_CONVMODE */ #define _VDAC_CH0CTRL_CONVMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH0CTRL */ #define _VDAC_CH0CTRL_CONVMODE_CONTINUOUS 0x00000000UL /**< Mode CONTINUOUS for VDAC_CH0CTRL */ #define _VDAC_CH0CTRL_CONVMODE_SAMPLEOFF 0x00000001UL /**< Mode SAMPLEOFF for VDAC_CH0CTRL */ #define VDAC_CH0CTRL_CONVMODE_DEFAULT (_VDAC_CH0CTRL_CONVMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CH0CTRL */ #define VDAC_CH0CTRL_CONVMODE_CONTINUOUS (_VDAC_CH0CTRL_CONVMODE_CONTINUOUS << 0) /**< Shifted mode CONTINUOUS for VDAC_CH0CTRL */ #define VDAC_CH0CTRL_CONVMODE_SAMPLEOFF (_VDAC_CH0CTRL_CONVMODE_SAMPLEOFF << 0) /**< Shifted mode SAMPLEOFF for VDAC_CH0CTRL */ #define _VDAC_CH0CTRL_TRIGMODE_SHIFT 4 /**< Shift value for VDAC_TRIGMODE */ #define _VDAC_CH0CTRL_TRIGMODE_MASK 0x70UL /**< Bit mask for VDAC_TRIGMODE */ #define _VDAC_CH0CTRL_TRIGMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH0CTRL */ #define _VDAC_CH0CTRL_TRIGMODE_SW 0x00000000UL /**< Mode SW for VDAC_CH0CTRL */ #define _VDAC_CH0CTRL_TRIGMODE_PRS 0x00000001UL /**< Mode PRS for VDAC_CH0CTRL */ #define _VDAC_CH0CTRL_TRIGMODE_REFRESH 0x00000002UL /**< Mode REFRESH for VDAC_CH0CTRL */ #define _VDAC_CH0CTRL_TRIGMODE_SWPRS 0x00000003UL /**< Mode SWPRS for VDAC_CH0CTRL */ #define _VDAC_CH0CTRL_TRIGMODE_SWREFRESH 0x00000004UL /**< Mode SWREFRESH for VDAC_CH0CTRL */ #define _VDAC_CH0CTRL_TRIGMODE_LESENSE 0x00000005UL /**< Mode LESENSE for VDAC_CH0CTRL */ #define VDAC_CH0CTRL_TRIGMODE_DEFAULT (_VDAC_CH0CTRL_TRIGMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_CH0CTRL */ #define VDAC_CH0CTRL_TRIGMODE_SW (_VDAC_CH0CTRL_TRIGMODE_SW << 4) /**< Shifted mode SW for VDAC_CH0CTRL */ #define VDAC_CH0CTRL_TRIGMODE_PRS (_VDAC_CH0CTRL_TRIGMODE_PRS << 4) /**< Shifted mode PRS for VDAC_CH0CTRL */ #define VDAC_CH0CTRL_TRIGMODE_REFRESH (_VDAC_CH0CTRL_TRIGMODE_REFRESH << 4) /**< Shifted mode REFRESH for VDAC_CH0CTRL */ #define VDAC_CH0CTRL_TRIGMODE_SWPRS (_VDAC_CH0CTRL_TRIGMODE_SWPRS << 4) /**< Shifted mode SWPRS for VDAC_CH0CTRL */ #define VDAC_CH0CTRL_TRIGMODE_SWREFRESH (_VDAC_CH0CTRL_TRIGMODE_SWREFRESH << 4) /**< Shifted mode SWREFRESH for VDAC_CH0CTRL */ #define VDAC_CH0CTRL_TRIGMODE_LESENSE (_VDAC_CH0CTRL_TRIGMODE_LESENSE << 4) /**< Shifted mode LESENSE for VDAC_CH0CTRL */ #define VDAC_CH0CTRL_PRSASYNC (0x1UL << 8) /**< Channel 0 PRS Asynchronous Enable */ #define _VDAC_CH0CTRL_PRSASYNC_SHIFT 8 /**< Shift value for VDAC_PRSASYNC */ #define _VDAC_CH0CTRL_PRSASYNC_MASK 0x100UL /**< Bit mask for VDAC_PRSASYNC */ #define _VDAC_CH0CTRL_PRSASYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH0CTRL */ #define VDAC_CH0CTRL_PRSASYNC_DEFAULT (_VDAC_CH0CTRL_PRSASYNC_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_CH0CTRL */ #define _VDAC_CH0CTRL_PRSSEL_SHIFT 12 /**< Shift value for VDAC_PRSSEL */ #define _VDAC_CH0CTRL_PRSSEL_MASK 0xF000UL /**< Bit mask for VDAC_PRSSEL */ #define _VDAC_CH0CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH0CTRL */ #define _VDAC_CH0CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for VDAC_CH0CTRL */ #define _VDAC_CH0CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for VDAC_CH0CTRL */ #define _VDAC_CH0CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for VDAC_CH0CTRL */ #define _VDAC_CH0CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for VDAC_CH0CTRL */ #define _VDAC_CH0CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for VDAC_CH0CTRL */ #define _VDAC_CH0CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for VDAC_CH0CTRL */ #define _VDAC_CH0CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for VDAC_CH0CTRL */ #define _VDAC_CH0CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for VDAC_CH0CTRL */ #define _VDAC_CH0CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for VDAC_CH0CTRL */ #define _VDAC_CH0CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for VDAC_CH0CTRL */ #define _VDAC_CH0CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for VDAC_CH0CTRL */ #define _VDAC_CH0CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for VDAC_CH0CTRL */ #define VDAC_CH0CTRL_PRSSEL_DEFAULT (_VDAC_CH0CTRL_PRSSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for VDAC_CH0CTRL */ #define VDAC_CH0CTRL_PRSSEL_PRSCH0 (_VDAC_CH0CTRL_PRSSEL_PRSCH0 << 12) /**< Shifted mode PRSCH0 for VDAC_CH0CTRL */ #define VDAC_CH0CTRL_PRSSEL_PRSCH1 (_VDAC_CH0CTRL_PRSSEL_PRSCH1 << 12) /**< Shifted mode PRSCH1 for VDAC_CH0CTRL */ #define VDAC_CH0CTRL_PRSSEL_PRSCH2 (_VDAC_CH0CTRL_PRSSEL_PRSCH2 << 12) /**< Shifted mode PRSCH2 for VDAC_CH0CTRL */ #define VDAC_CH0CTRL_PRSSEL_PRSCH3 (_VDAC_CH0CTRL_PRSSEL_PRSCH3 << 12) /**< Shifted mode PRSCH3 for VDAC_CH0CTRL */ #define VDAC_CH0CTRL_PRSSEL_PRSCH4 (_VDAC_CH0CTRL_PRSSEL_PRSCH4 << 12) /**< Shifted mode PRSCH4 for VDAC_CH0CTRL */ #define VDAC_CH0CTRL_PRSSEL_PRSCH5 (_VDAC_CH0CTRL_PRSSEL_PRSCH5 << 12) /**< Shifted mode PRSCH5 for VDAC_CH0CTRL */ #define VDAC_CH0CTRL_PRSSEL_PRSCH6 (_VDAC_CH0CTRL_PRSSEL_PRSCH6 << 12) /**< Shifted mode PRSCH6 for VDAC_CH0CTRL */ #define VDAC_CH0CTRL_PRSSEL_PRSCH7 (_VDAC_CH0CTRL_PRSSEL_PRSCH7 << 12) /**< Shifted mode PRSCH7 for VDAC_CH0CTRL */ #define VDAC_CH0CTRL_PRSSEL_PRSCH8 (_VDAC_CH0CTRL_PRSSEL_PRSCH8 << 12) /**< Shifted mode PRSCH8 for VDAC_CH0CTRL */ #define VDAC_CH0CTRL_PRSSEL_PRSCH9 (_VDAC_CH0CTRL_PRSSEL_PRSCH9 << 12) /**< Shifted mode PRSCH9 for VDAC_CH0CTRL */ #define VDAC_CH0CTRL_PRSSEL_PRSCH10 (_VDAC_CH0CTRL_PRSSEL_PRSCH10 << 12) /**< Shifted mode PRSCH10 for VDAC_CH0CTRL */ #define VDAC_CH0CTRL_PRSSEL_PRSCH11 (_VDAC_CH0CTRL_PRSSEL_PRSCH11 << 12) /**< Shifted mode PRSCH11 for VDAC_CH0CTRL */ /* Bit fields for VDAC CH1CTRL */ #define _VDAC_CH1CTRL_RESETVALUE 0x00000000UL /**< Default value for VDAC_CH1CTRL */ #define _VDAC_CH1CTRL_MASK 0x0000F171UL /**< Mask for VDAC_CH1CTRL */ #define VDAC_CH1CTRL_CONVMODE (0x1UL << 0) /**< Conversion Mode */ #define _VDAC_CH1CTRL_CONVMODE_SHIFT 0 /**< Shift value for VDAC_CONVMODE */ #define _VDAC_CH1CTRL_CONVMODE_MASK 0x1UL /**< Bit mask for VDAC_CONVMODE */ #define _VDAC_CH1CTRL_CONVMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH1CTRL */ #define _VDAC_CH1CTRL_CONVMODE_CONTINUOUS 0x00000000UL /**< Mode CONTINUOUS for VDAC_CH1CTRL */ #define _VDAC_CH1CTRL_CONVMODE_SAMPLEOFF 0x00000001UL /**< Mode SAMPLEOFF for VDAC_CH1CTRL */ #define VDAC_CH1CTRL_CONVMODE_DEFAULT (_VDAC_CH1CTRL_CONVMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CH1CTRL */ #define VDAC_CH1CTRL_CONVMODE_CONTINUOUS (_VDAC_CH1CTRL_CONVMODE_CONTINUOUS << 0) /**< Shifted mode CONTINUOUS for VDAC_CH1CTRL */ #define VDAC_CH1CTRL_CONVMODE_SAMPLEOFF (_VDAC_CH1CTRL_CONVMODE_SAMPLEOFF << 0) /**< Shifted mode SAMPLEOFF for VDAC_CH1CTRL */ #define _VDAC_CH1CTRL_TRIGMODE_SHIFT 4 /**< Shift value for VDAC_TRIGMODE */ #define _VDAC_CH1CTRL_TRIGMODE_MASK 0x70UL /**< Bit mask for VDAC_TRIGMODE */ #define _VDAC_CH1CTRL_TRIGMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH1CTRL */ #define _VDAC_CH1CTRL_TRIGMODE_SW 0x00000000UL /**< Mode SW for VDAC_CH1CTRL */ #define _VDAC_CH1CTRL_TRIGMODE_PRS 0x00000001UL /**< Mode PRS for VDAC_CH1CTRL */ #define _VDAC_CH1CTRL_TRIGMODE_REFRESH 0x00000002UL /**< Mode REFRESH for VDAC_CH1CTRL */ #define _VDAC_CH1CTRL_TRIGMODE_SWPRS 0x00000003UL /**< Mode SWPRS for VDAC_CH1CTRL */ #define _VDAC_CH1CTRL_TRIGMODE_SWREFRESH 0x00000004UL /**< Mode SWREFRESH for VDAC_CH1CTRL */ #define _VDAC_CH1CTRL_TRIGMODE_LESENSE 0x00000005UL /**< Mode LESENSE for VDAC_CH1CTRL */ #define VDAC_CH1CTRL_TRIGMODE_DEFAULT (_VDAC_CH1CTRL_TRIGMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_CH1CTRL */ #define VDAC_CH1CTRL_TRIGMODE_SW (_VDAC_CH1CTRL_TRIGMODE_SW << 4) /**< Shifted mode SW for VDAC_CH1CTRL */ #define VDAC_CH1CTRL_TRIGMODE_PRS (_VDAC_CH1CTRL_TRIGMODE_PRS << 4) /**< Shifted mode PRS for VDAC_CH1CTRL */ #define VDAC_CH1CTRL_TRIGMODE_REFRESH (_VDAC_CH1CTRL_TRIGMODE_REFRESH << 4) /**< Shifted mode REFRESH for VDAC_CH1CTRL */ #define VDAC_CH1CTRL_TRIGMODE_SWPRS (_VDAC_CH1CTRL_TRIGMODE_SWPRS << 4) /**< Shifted mode SWPRS for VDAC_CH1CTRL */ #define VDAC_CH1CTRL_TRIGMODE_SWREFRESH (_VDAC_CH1CTRL_TRIGMODE_SWREFRESH << 4) /**< Shifted mode SWREFRESH for VDAC_CH1CTRL */ #define VDAC_CH1CTRL_TRIGMODE_LESENSE (_VDAC_CH1CTRL_TRIGMODE_LESENSE << 4) /**< Shifted mode LESENSE for VDAC_CH1CTRL */ #define VDAC_CH1CTRL_PRSASYNC (0x1UL << 8) /**< Channel 1 PRS Asynchronous Enable */ #define _VDAC_CH1CTRL_PRSASYNC_SHIFT 8 /**< Shift value for VDAC_PRSASYNC */ #define _VDAC_CH1CTRL_PRSASYNC_MASK 0x100UL /**< Bit mask for VDAC_PRSASYNC */ #define _VDAC_CH1CTRL_PRSASYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH1CTRL */ #define VDAC_CH1CTRL_PRSASYNC_DEFAULT (_VDAC_CH1CTRL_PRSASYNC_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_CH1CTRL */ #define _VDAC_CH1CTRL_PRSSEL_SHIFT 12 /**< Shift value for VDAC_PRSSEL */ #define _VDAC_CH1CTRL_PRSSEL_MASK 0xF000UL /**< Bit mask for VDAC_PRSSEL */ #define _VDAC_CH1CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH1CTRL */ #define _VDAC_CH1CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for VDAC_CH1CTRL */ #define _VDAC_CH1CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for VDAC_CH1CTRL */ #define _VDAC_CH1CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for VDAC_CH1CTRL */ #define _VDAC_CH1CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for VDAC_CH1CTRL */ #define _VDAC_CH1CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for VDAC_CH1CTRL */ #define _VDAC_CH1CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for VDAC_CH1CTRL */ #define _VDAC_CH1CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for VDAC_CH1CTRL */ #define _VDAC_CH1CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for VDAC_CH1CTRL */ #define _VDAC_CH1CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for VDAC_CH1CTRL */ #define _VDAC_CH1CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for VDAC_CH1CTRL */ #define _VDAC_CH1CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for VDAC_CH1CTRL */ #define _VDAC_CH1CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for VDAC_CH1CTRL */ #define VDAC_CH1CTRL_PRSSEL_DEFAULT (_VDAC_CH1CTRL_PRSSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for VDAC_CH1CTRL */ #define VDAC_CH1CTRL_PRSSEL_PRSCH0 (_VDAC_CH1CTRL_PRSSEL_PRSCH0 << 12) /**< Shifted mode PRSCH0 for VDAC_CH1CTRL */ #define VDAC_CH1CTRL_PRSSEL_PRSCH1 (_VDAC_CH1CTRL_PRSSEL_PRSCH1 << 12) /**< Shifted mode PRSCH1 for VDAC_CH1CTRL */ #define VDAC_CH1CTRL_PRSSEL_PRSCH2 (_VDAC_CH1CTRL_PRSSEL_PRSCH2 << 12) /**< Shifted mode PRSCH2 for VDAC_CH1CTRL */ #define VDAC_CH1CTRL_PRSSEL_PRSCH3 (_VDAC_CH1CTRL_PRSSEL_PRSCH3 << 12) /**< Shifted mode PRSCH3 for VDAC_CH1CTRL */ #define VDAC_CH1CTRL_PRSSEL_PRSCH4 (_VDAC_CH1CTRL_PRSSEL_PRSCH4 << 12) /**< Shifted mode PRSCH4 for VDAC_CH1CTRL */ #define VDAC_CH1CTRL_PRSSEL_PRSCH5 (_VDAC_CH1CTRL_PRSSEL_PRSCH5 << 12) /**< Shifted mode PRSCH5 for VDAC_CH1CTRL */ #define VDAC_CH1CTRL_PRSSEL_PRSCH6 (_VDAC_CH1CTRL_PRSSEL_PRSCH6 << 12) /**< Shifted mode PRSCH6 for VDAC_CH1CTRL */ #define VDAC_CH1CTRL_PRSSEL_PRSCH7 (_VDAC_CH1CTRL_PRSSEL_PRSCH7 << 12) /**< Shifted mode PRSCH7 for VDAC_CH1CTRL */ #define VDAC_CH1CTRL_PRSSEL_PRSCH8 (_VDAC_CH1CTRL_PRSSEL_PRSCH8 << 12) /**< Shifted mode PRSCH8 for VDAC_CH1CTRL */ #define VDAC_CH1CTRL_PRSSEL_PRSCH9 (_VDAC_CH1CTRL_PRSSEL_PRSCH9 << 12) /**< Shifted mode PRSCH9 for VDAC_CH1CTRL */ #define VDAC_CH1CTRL_PRSSEL_PRSCH10 (_VDAC_CH1CTRL_PRSSEL_PRSCH10 << 12) /**< Shifted mode PRSCH10 for VDAC_CH1CTRL */ #define VDAC_CH1CTRL_PRSSEL_PRSCH11 (_VDAC_CH1CTRL_PRSSEL_PRSCH11 << 12) /**< Shifted mode PRSCH11 for VDAC_CH1CTRL */ /* Bit fields for VDAC CMD */ #define _VDAC_CMD_RESETVALUE 0x00000000UL /**< Default value for VDAC_CMD */ #define _VDAC_CMD_MASK 0x003F000FUL /**< Mask for VDAC_CMD */ #define VDAC_CMD_CH0EN (0x1UL << 0) /**< DAC Channel 0 Enable */ #define _VDAC_CMD_CH0EN_SHIFT 0 /**< Shift value for VDAC_CH0EN */ #define _VDAC_CMD_CH0EN_MASK 0x1UL /**< Bit mask for VDAC_CH0EN */ #define _VDAC_CMD_CH0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ #define VDAC_CMD_CH0EN_DEFAULT (_VDAC_CMD_CH0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CMD */ #define VDAC_CMD_CH0DIS (0x1UL << 1) /**< DAC Channel 0 Disable */ #define _VDAC_CMD_CH0DIS_SHIFT 1 /**< Shift value for VDAC_CH0DIS */ #define _VDAC_CMD_CH0DIS_MASK 0x2UL /**< Bit mask for VDAC_CH0DIS */ #define _VDAC_CMD_CH0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ #define VDAC_CMD_CH0DIS_DEFAULT (_VDAC_CMD_CH0DIS_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_CMD */ #define VDAC_CMD_CH1EN (0x1UL << 2) /**< DAC Channel 1 Enable */ #define _VDAC_CMD_CH1EN_SHIFT 2 /**< Shift value for VDAC_CH1EN */ #define _VDAC_CMD_CH1EN_MASK 0x4UL /**< Bit mask for VDAC_CH1EN */ #define _VDAC_CMD_CH1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ #define VDAC_CMD_CH1EN_DEFAULT (_VDAC_CMD_CH1EN_DEFAULT << 2) /**< Shifted mode DEFAULT for VDAC_CMD */ #define VDAC_CMD_CH1DIS (0x1UL << 3) /**< DAC Channel 1 Disable */ #define _VDAC_CMD_CH1DIS_SHIFT 3 /**< Shift value for VDAC_CH1DIS */ #define _VDAC_CMD_CH1DIS_MASK 0x8UL /**< Bit mask for VDAC_CH1DIS */ #define _VDAC_CMD_CH1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ #define VDAC_CMD_CH1DIS_DEFAULT (_VDAC_CMD_CH1DIS_DEFAULT << 3) /**< Shifted mode DEFAULT for VDAC_CMD */ #define VDAC_CMD_OPA0EN (0x1UL << 16) /**< OPA0 Enable */ #define _VDAC_CMD_OPA0EN_SHIFT 16 /**< Shift value for VDAC_OPA0EN */ #define _VDAC_CMD_OPA0EN_MASK 0x10000UL /**< Bit mask for VDAC_OPA0EN */ #define _VDAC_CMD_OPA0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ #define VDAC_CMD_OPA0EN_DEFAULT (_VDAC_CMD_OPA0EN_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_CMD */ #define VDAC_CMD_OPA0DIS (0x1UL << 17) /**< OPA0 Disable */ #define _VDAC_CMD_OPA0DIS_SHIFT 17 /**< Shift value for VDAC_OPA0DIS */ #define _VDAC_CMD_OPA0DIS_MASK 0x20000UL /**< Bit mask for VDAC_OPA0DIS */ #define _VDAC_CMD_OPA0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ #define VDAC_CMD_OPA0DIS_DEFAULT (_VDAC_CMD_OPA0DIS_DEFAULT << 17) /**< Shifted mode DEFAULT for VDAC_CMD */ #define VDAC_CMD_OPA1EN (0x1UL << 18) /**< OPA1 Enable */ #define _VDAC_CMD_OPA1EN_SHIFT 18 /**< Shift value for VDAC_OPA1EN */ #define _VDAC_CMD_OPA1EN_MASK 0x40000UL /**< Bit mask for VDAC_OPA1EN */ #define _VDAC_CMD_OPA1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ #define VDAC_CMD_OPA1EN_DEFAULT (_VDAC_CMD_OPA1EN_DEFAULT << 18) /**< Shifted mode DEFAULT for VDAC_CMD */ #define VDAC_CMD_OPA1DIS (0x1UL << 19) /**< OPA1 Disable */ #define _VDAC_CMD_OPA1DIS_SHIFT 19 /**< Shift value for VDAC_OPA1DIS */ #define _VDAC_CMD_OPA1DIS_MASK 0x80000UL /**< Bit mask for VDAC_OPA1DIS */ #define _VDAC_CMD_OPA1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ #define VDAC_CMD_OPA1DIS_DEFAULT (_VDAC_CMD_OPA1DIS_DEFAULT << 19) /**< Shifted mode DEFAULT for VDAC_CMD */ #define VDAC_CMD_OPA2EN (0x1UL << 20) /**< OPA2 Enable */ #define _VDAC_CMD_OPA2EN_SHIFT 20 /**< Shift value for VDAC_OPA2EN */ #define _VDAC_CMD_OPA2EN_MASK 0x100000UL /**< Bit mask for VDAC_OPA2EN */ #define _VDAC_CMD_OPA2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ #define VDAC_CMD_OPA2EN_DEFAULT (_VDAC_CMD_OPA2EN_DEFAULT << 20) /**< Shifted mode DEFAULT for VDAC_CMD */ #define VDAC_CMD_OPA2DIS (0x1UL << 21) /**< OPA2 Disable */ #define _VDAC_CMD_OPA2DIS_SHIFT 21 /**< Shift value for VDAC_OPA2DIS */ #define _VDAC_CMD_OPA2DIS_MASK 0x200000UL /**< Bit mask for VDAC_OPA2DIS */ #define _VDAC_CMD_OPA2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ #define VDAC_CMD_OPA2DIS_DEFAULT (_VDAC_CMD_OPA2DIS_DEFAULT << 21) /**< Shifted mode DEFAULT for VDAC_CMD */ /* Bit fields for VDAC IF */ #define _VDAC_IF_RESETVALUE 0x000000C0UL /**< Default value for VDAC_IF */ #define _VDAC_IF_MASK 0x707780FFUL /**< Mask for VDAC_IF */ #define VDAC_IF_CH0CD (0x1UL << 0) /**< Channel 0 Conversion Done Interrupt Flag */ #define _VDAC_IF_CH0CD_SHIFT 0 /**< Shift value for VDAC_CH0CD */ #define _VDAC_IF_CH0CD_MASK 0x1UL /**< Bit mask for VDAC_CH0CD */ #define _VDAC_IF_CH0CD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ #define VDAC_IF_CH0CD_DEFAULT (_VDAC_IF_CH0CD_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_IF */ #define VDAC_IF_CH1CD (0x1UL << 1) /**< Channel 1 Conversion Done Interrupt Flag */ #define _VDAC_IF_CH1CD_SHIFT 1 /**< Shift value for VDAC_CH1CD */ #define _VDAC_IF_CH1CD_MASK 0x2UL /**< Bit mask for VDAC_CH1CD */ #define _VDAC_IF_CH1CD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ #define VDAC_IF_CH1CD_DEFAULT (_VDAC_IF_CH1CD_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_IF */ #define VDAC_IF_CH0OF (0x1UL << 2) /**< Channel 0 Data Overflow Interrupt Flag */ #define _VDAC_IF_CH0OF_SHIFT 2 /**< Shift value for VDAC_CH0OF */ #define _VDAC_IF_CH0OF_MASK 0x4UL /**< Bit mask for VDAC_CH0OF */ #define _VDAC_IF_CH0OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ #define VDAC_IF_CH0OF_DEFAULT (_VDAC_IF_CH0OF_DEFAULT << 2) /**< Shifted mode DEFAULT for VDAC_IF */ #define VDAC_IF_CH1OF (0x1UL << 3) /**< Channel 1 Data Overflow Interrupt Flag */ #define _VDAC_IF_CH1OF_SHIFT 3 /**< Shift value for VDAC_CH1OF */ #define _VDAC_IF_CH1OF_MASK 0x8UL /**< Bit mask for VDAC_CH1OF */ #define _VDAC_IF_CH1OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ #define VDAC_IF_CH1OF_DEFAULT (_VDAC_IF_CH1OF_DEFAULT << 3) /**< Shifted mode DEFAULT for VDAC_IF */ #define VDAC_IF_CH0UF (0x1UL << 4) /**< Channel 0 Data Underflow Interrupt Flag */ #define _VDAC_IF_CH0UF_SHIFT 4 /**< Shift value for VDAC_CH0UF */ #define _VDAC_IF_CH0UF_MASK 0x10UL /**< Bit mask for VDAC_CH0UF */ #define _VDAC_IF_CH0UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ #define VDAC_IF_CH0UF_DEFAULT (_VDAC_IF_CH0UF_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_IF */ #define VDAC_IF_CH1UF (0x1UL << 5) /**< Channel 1 Data Underflow Interrupt Flag */ #define _VDAC_IF_CH1UF_SHIFT 5 /**< Shift value for VDAC_CH1UF */ #define _VDAC_IF_CH1UF_MASK 0x20UL /**< Bit mask for VDAC_CH1UF */ #define _VDAC_IF_CH1UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ #define VDAC_IF_CH1UF_DEFAULT (_VDAC_IF_CH1UF_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_IF */ #define VDAC_IF_CH0BL (0x1UL << 6) /**< Channel 0 Buffer Level Interrupt Flag */ #define _VDAC_IF_CH0BL_SHIFT 6 /**< Shift value for VDAC_CH0BL */ #define _VDAC_IF_CH0BL_MASK 0x40UL /**< Bit mask for VDAC_CH0BL */ #define _VDAC_IF_CH0BL_DEFAULT 0x00000001UL /**< Mode DEFAULT for VDAC_IF */ #define VDAC_IF_CH0BL_DEFAULT (_VDAC_IF_CH0BL_DEFAULT << 6) /**< Shifted mode DEFAULT for VDAC_IF */ #define VDAC_IF_CH1BL (0x1UL << 7) /**< Channel 1 Buffer Level Interrupt Flag */ #define _VDAC_IF_CH1BL_SHIFT 7 /**< Shift value for VDAC_CH1BL */ #define _VDAC_IF_CH1BL_MASK 0x80UL /**< Bit mask for VDAC_CH1BL */ #define _VDAC_IF_CH1BL_DEFAULT 0x00000001UL /**< Mode DEFAULT for VDAC_IF */ #define VDAC_IF_CH1BL_DEFAULT (_VDAC_IF_CH1BL_DEFAULT << 7) /**< Shifted mode DEFAULT for VDAC_IF */ #define VDAC_IF_EM23ERR (0x1UL << 15) /**< EM2/3 Entry Error Flag */ #define _VDAC_IF_EM23ERR_SHIFT 15 /**< Shift value for VDAC_EM23ERR */ #define _VDAC_IF_EM23ERR_MASK 0x8000UL /**< Bit mask for VDAC_EM23ERR */ #define _VDAC_IF_EM23ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ #define VDAC_IF_EM23ERR_DEFAULT (_VDAC_IF_EM23ERR_DEFAULT << 15) /**< Shifted mode DEFAULT for VDAC_IF */ #define VDAC_IF_OPA0APORTCONFLICT (0x1UL << 16) /**< OPA0 Bus Conflict Output Interrupt Flag */ #define _VDAC_IF_OPA0APORTCONFLICT_SHIFT 16 /**< Shift value for VDAC_OPA0APORTCONFLICT */ #define _VDAC_IF_OPA0APORTCONFLICT_MASK 0x10000UL /**< Bit mask for VDAC_OPA0APORTCONFLICT */ #define _VDAC_IF_OPA0APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ #define VDAC_IF_OPA0APORTCONFLICT_DEFAULT (_VDAC_IF_OPA0APORTCONFLICT_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_IF */ #define VDAC_IF_OPA1APORTCONFLICT (0x1UL << 17) /**< OPA1 Bus Conflict Output Interrupt Flag */ #define _VDAC_IF_OPA1APORTCONFLICT_SHIFT 17 /**< Shift value for VDAC_OPA1APORTCONFLICT */ #define _VDAC_IF_OPA1APORTCONFLICT_MASK 0x20000UL /**< Bit mask for VDAC_OPA1APORTCONFLICT */ #define _VDAC_IF_OPA1APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ #define VDAC_IF_OPA1APORTCONFLICT_DEFAULT (_VDAC_IF_OPA1APORTCONFLICT_DEFAULT << 17) /**< Shifted mode DEFAULT for VDAC_IF */ #define VDAC_IF_OPA2APORTCONFLICT (0x1UL << 18) /**< OPA2 Bus Conflict Output Interrupt Flag */ #define _VDAC_IF_OPA2APORTCONFLICT_SHIFT 18 /**< Shift value for VDAC_OPA2APORTCONFLICT */ #define _VDAC_IF_OPA2APORTCONFLICT_MASK 0x40000UL /**< Bit mask for VDAC_OPA2APORTCONFLICT */ #define _VDAC_IF_OPA2APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ #define VDAC_IF_OPA2APORTCONFLICT_DEFAULT (_VDAC_IF_OPA2APORTCONFLICT_DEFAULT << 18) /**< Shifted mode DEFAULT for VDAC_IF */ #define VDAC_IF_OPA0PRSTIMEDERR (0x1UL << 20) /**< OPA0 PRS Trigger Mode Error Interrupt Flag */ #define _VDAC_IF_OPA0PRSTIMEDERR_SHIFT 20 /**< Shift value for VDAC_OPA0PRSTIMEDERR */ #define _VDAC_IF_OPA0PRSTIMEDERR_MASK 0x100000UL /**< Bit mask for VDAC_OPA0PRSTIMEDERR */ #define _VDAC_IF_OPA0PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ #define VDAC_IF_OPA0PRSTIMEDERR_DEFAULT (_VDAC_IF_OPA0PRSTIMEDERR_DEFAULT << 20) /**< Shifted mode DEFAULT for VDAC_IF */ #define VDAC_IF_OPA1PRSTIMEDERR (0x1UL << 21) /**< OPA1 PRS Trigger Mode Error Interrupt Flag */ #define _VDAC_IF_OPA1PRSTIMEDERR_SHIFT 21 /**< Shift value for VDAC_OPA1PRSTIMEDERR */ #define _VDAC_IF_OPA1PRSTIMEDERR_MASK 0x200000UL /**< Bit mask for VDAC_OPA1PRSTIMEDERR */ #define _VDAC_IF_OPA1PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ #define VDAC_IF_OPA1PRSTIMEDERR_DEFAULT (_VDAC_IF_OPA1PRSTIMEDERR_DEFAULT << 21) /**< Shifted mode DEFAULT for VDAC_IF */ #define VDAC_IF_OPA2PRSTIMEDERR (0x1UL << 22) /**< OPA2 PRS Trigger Mode Error Interrupt Flag */ #define _VDAC_IF_OPA2PRSTIMEDERR_SHIFT 22 /**< Shift value for VDAC_OPA2PRSTIMEDERR */ #define _VDAC_IF_OPA2PRSTIMEDERR_MASK 0x400000UL /**< Bit mask for VDAC_OPA2PRSTIMEDERR */ #define _VDAC_IF_OPA2PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ #define VDAC_IF_OPA2PRSTIMEDERR_DEFAULT (_VDAC_IF_OPA2PRSTIMEDERR_DEFAULT << 22) /**< Shifted mode DEFAULT for VDAC_IF */ #define VDAC_IF_OPA0OUTVALID (0x1UL << 28) /**< OPA0 Output Valid Interrupt Flag */ #define _VDAC_IF_OPA0OUTVALID_SHIFT 28 /**< Shift value for VDAC_OPA0OUTVALID */ #define _VDAC_IF_OPA0OUTVALID_MASK 0x10000000UL /**< Bit mask for VDAC_OPA0OUTVALID */ #define _VDAC_IF_OPA0OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ #define VDAC_IF_OPA0OUTVALID_DEFAULT (_VDAC_IF_OPA0OUTVALID_DEFAULT << 28) /**< Shifted mode DEFAULT for VDAC_IF */ #define VDAC_IF_OPA1OUTVALID (0x1UL << 29) /**< OPA1 Output Valid Interrupt Flag */ #define _VDAC_IF_OPA1OUTVALID_SHIFT 29 /**< Shift value for VDAC_OPA1OUTVALID */ #define _VDAC_IF_OPA1OUTVALID_MASK 0x20000000UL /**< Bit mask for VDAC_OPA1OUTVALID */ #define _VDAC_IF_OPA1OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ #define VDAC_IF_OPA1OUTVALID_DEFAULT (_VDAC_IF_OPA1OUTVALID_DEFAULT << 29) /**< Shifted mode DEFAULT for VDAC_IF */ #define VDAC_IF_OPA2OUTVALID (0x1UL << 30) /**< OPA3 Output Valid Interrupt Flag */ #define _VDAC_IF_OPA2OUTVALID_SHIFT 30 /**< Shift value for VDAC_OPA2OUTVALID */ #define _VDAC_IF_OPA2OUTVALID_MASK 0x40000000UL /**< Bit mask for VDAC_OPA2OUTVALID */ #define _VDAC_IF_OPA2OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ #define VDAC_IF_OPA2OUTVALID_DEFAULT (_VDAC_IF_OPA2OUTVALID_DEFAULT << 30) /**< Shifted mode DEFAULT for VDAC_IF */ /* Bit fields for VDAC IFS */ #define _VDAC_IFS_RESETVALUE 0x00000000UL /**< Default value for VDAC_IFS */ #define _VDAC_IFS_MASK 0x7077803FUL /**< Mask for VDAC_IFS */ #define VDAC_IFS_CH0CD (0x1UL << 0) /**< Set CH0CD Interrupt Flag */ #define _VDAC_IFS_CH0CD_SHIFT 0 /**< Shift value for VDAC_CH0CD */ #define _VDAC_IFS_CH0CD_MASK 0x1UL /**< Bit mask for VDAC_CH0CD */ #define _VDAC_IFS_CH0CD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */ #define VDAC_IFS_CH0CD_DEFAULT (_VDAC_IFS_CH0CD_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_IFS */ #define VDAC_IFS_CH1CD (0x1UL << 1) /**< Set CH1CD Interrupt Flag */ #define _VDAC_IFS_CH1CD_SHIFT 1 /**< Shift value for VDAC_CH1CD */ #define _VDAC_IFS_CH1CD_MASK 0x2UL /**< Bit mask for VDAC_CH1CD */ #define _VDAC_IFS_CH1CD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */ #define VDAC_IFS_CH1CD_DEFAULT (_VDAC_IFS_CH1CD_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_IFS */ #define VDAC_IFS_CH0OF (0x1UL << 2) /**< Set CH0OF Interrupt Flag */ #define _VDAC_IFS_CH0OF_SHIFT 2 /**< Shift value for VDAC_CH0OF */ #define _VDAC_IFS_CH0OF_MASK 0x4UL /**< Bit mask for VDAC_CH0OF */ #define _VDAC_IFS_CH0OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */ #define VDAC_IFS_CH0OF_DEFAULT (_VDAC_IFS_CH0OF_DEFAULT << 2) /**< Shifted mode DEFAULT for VDAC_IFS */ #define VDAC_IFS_CH1OF (0x1UL << 3) /**< Set CH1OF Interrupt Flag */ #define _VDAC_IFS_CH1OF_SHIFT 3 /**< Shift value for VDAC_CH1OF */ #define _VDAC_IFS_CH1OF_MASK 0x8UL /**< Bit mask for VDAC_CH1OF */ #define _VDAC_IFS_CH1OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */ #define VDAC_IFS_CH1OF_DEFAULT (_VDAC_IFS_CH1OF_DEFAULT << 3) /**< Shifted mode DEFAULT for VDAC_IFS */ #define VDAC_IFS_CH0UF (0x1UL << 4) /**< Set CH0UF Interrupt Flag */ #define _VDAC_IFS_CH0UF_SHIFT 4 /**< Shift value for VDAC_CH0UF */ #define _VDAC_IFS_CH0UF_MASK 0x10UL /**< Bit mask for VDAC_CH0UF */ #define _VDAC_IFS_CH0UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */ #define VDAC_IFS_CH0UF_DEFAULT (_VDAC_IFS_CH0UF_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_IFS */ #define VDAC_IFS_CH1UF (0x1UL << 5) /**< Set CH1UF Interrupt Flag */ #define _VDAC_IFS_CH1UF_SHIFT 5 /**< Shift value for VDAC_CH1UF */ #define _VDAC_IFS_CH1UF_MASK 0x20UL /**< Bit mask for VDAC_CH1UF */ #define _VDAC_IFS_CH1UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */ #define VDAC_IFS_CH1UF_DEFAULT (_VDAC_IFS_CH1UF_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_IFS */ #define VDAC_IFS_EM23ERR (0x1UL << 15) /**< Set EM23ERR Interrupt Flag */ #define _VDAC_IFS_EM23ERR_SHIFT 15 /**< Shift value for VDAC_EM23ERR */ #define _VDAC_IFS_EM23ERR_MASK 0x8000UL /**< Bit mask for VDAC_EM23ERR */ #define _VDAC_IFS_EM23ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */ #define VDAC_IFS_EM23ERR_DEFAULT (_VDAC_IFS_EM23ERR_DEFAULT << 15) /**< Shifted mode DEFAULT for VDAC_IFS */ #define VDAC_IFS_OPA0APORTCONFLICT (0x1UL << 16) /**< Set OPA0APORTCONFLICT Interrupt Flag */ #define _VDAC_IFS_OPA0APORTCONFLICT_SHIFT 16 /**< Shift value for VDAC_OPA0APORTCONFLICT */ #define _VDAC_IFS_OPA0APORTCONFLICT_MASK 0x10000UL /**< Bit mask for VDAC_OPA0APORTCONFLICT */ #define _VDAC_IFS_OPA0APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */ #define VDAC_IFS_OPA0APORTCONFLICT_DEFAULT (_VDAC_IFS_OPA0APORTCONFLICT_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_IFS */ #define VDAC_IFS_OPA1APORTCONFLICT (0x1UL << 17) /**< Set OPA1APORTCONFLICT Interrupt Flag */ #define _VDAC_IFS_OPA1APORTCONFLICT_SHIFT 17 /**< Shift value for VDAC_OPA1APORTCONFLICT */ #define _VDAC_IFS_OPA1APORTCONFLICT_MASK 0x20000UL /**< Bit mask for VDAC_OPA1APORTCONFLICT */ #define _VDAC_IFS_OPA1APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */ #define VDAC_IFS_OPA1APORTCONFLICT_DEFAULT (_VDAC_IFS_OPA1APORTCONFLICT_DEFAULT << 17) /**< Shifted mode DEFAULT for VDAC_IFS */ #define VDAC_IFS_OPA2APORTCONFLICT (0x1UL << 18) /**< Set OPA2APORTCONFLICT Interrupt Flag */ #define _VDAC_IFS_OPA2APORTCONFLICT_SHIFT 18 /**< Shift value for VDAC_OPA2APORTCONFLICT */ #define _VDAC_IFS_OPA2APORTCONFLICT_MASK 0x40000UL /**< Bit mask for VDAC_OPA2APORTCONFLICT */ #define _VDAC_IFS_OPA2APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */ #define VDAC_IFS_OPA2APORTCONFLICT_DEFAULT (_VDAC_IFS_OPA2APORTCONFLICT_DEFAULT << 18) /**< Shifted mode DEFAULT for VDAC_IFS */ #define VDAC_IFS_OPA0PRSTIMEDERR (0x1UL << 20) /**< Set OPA0PRSTIMEDERR Interrupt Flag */ #define _VDAC_IFS_OPA0PRSTIMEDERR_SHIFT 20 /**< Shift value for VDAC_OPA0PRSTIMEDERR */ #define _VDAC_IFS_OPA0PRSTIMEDERR_MASK 0x100000UL /**< Bit mask for VDAC_OPA0PRSTIMEDERR */ #define _VDAC_IFS_OPA0PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */ #define VDAC_IFS_OPA0PRSTIMEDERR_DEFAULT (_VDAC_IFS_OPA0PRSTIMEDERR_DEFAULT << 20) /**< Shifted mode DEFAULT for VDAC_IFS */ #define VDAC_IFS_OPA1PRSTIMEDERR (0x1UL << 21) /**< Set OPA1PRSTIMEDERR Interrupt Flag */ #define _VDAC_IFS_OPA1PRSTIMEDERR_SHIFT 21 /**< Shift value for VDAC_OPA1PRSTIMEDERR */ #define _VDAC_IFS_OPA1PRSTIMEDERR_MASK 0x200000UL /**< Bit mask for VDAC_OPA1PRSTIMEDERR */ #define _VDAC_IFS_OPA1PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */ #define VDAC_IFS_OPA1PRSTIMEDERR_DEFAULT (_VDAC_IFS_OPA1PRSTIMEDERR_DEFAULT << 21) /**< Shifted mode DEFAULT for VDAC_IFS */ #define VDAC_IFS_OPA2PRSTIMEDERR (0x1UL << 22) /**< Set OPA2PRSTIMEDERR Interrupt Flag */ #define _VDAC_IFS_OPA2PRSTIMEDERR_SHIFT 22 /**< Shift value for VDAC_OPA2PRSTIMEDERR */ #define _VDAC_IFS_OPA2PRSTIMEDERR_MASK 0x400000UL /**< Bit mask for VDAC_OPA2PRSTIMEDERR */ #define _VDAC_IFS_OPA2PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */ #define VDAC_IFS_OPA2PRSTIMEDERR_DEFAULT (_VDAC_IFS_OPA2PRSTIMEDERR_DEFAULT << 22) /**< Shifted mode DEFAULT for VDAC_IFS */ #define VDAC_IFS_OPA0OUTVALID (0x1UL << 28) /**< Set OPA0OUTVALID Interrupt Flag */ #define _VDAC_IFS_OPA0OUTVALID_SHIFT 28 /**< Shift value for VDAC_OPA0OUTVALID */ #define _VDAC_IFS_OPA0OUTVALID_MASK 0x10000000UL /**< Bit mask for VDAC_OPA0OUTVALID */ #define _VDAC_IFS_OPA0OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */ #define VDAC_IFS_OPA0OUTVALID_DEFAULT (_VDAC_IFS_OPA0OUTVALID_DEFAULT << 28) /**< Shifted mode DEFAULT for VDAC_IFS */ #define VDAC_IFS_OPA1OUTVALID (0x1UL << 29) /**< Set OPA1OUTVALID Interrupt Flag */ #define _VDAC_IFS_OPA1OUTVALID_SHIFT 29 /**< Shift value for VDAC_OPA1OUTVALID */ #define _VDAC_IFS_OPA1OUTVALID_MASK 0x20000000UL /**< Bit mask for VDAC_OPA1OUTVALID */ #define _VDAC_IFS_OPA1OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */ #define VDAC_IFS_OPA1OUTVALID_DEFAULT (_VDAC_IFS_OPA1OUTVALID_DEFAULT << 29) /**< Shifted mode DEFAULT for VDAC_IFS */ #define VDAC_IFS_OPA2OUTVALID (0x1UL << 30) /**< Set OPA2OUTVALID Interrupt Flag */ #define _VDAC_IFS_OPA2OUTVALID_SHIFT 30 /**< Shift value for VDAC_OPA2OUTVALID */ #define _VDAC_IFS_OPA2OUTVALID_MASK 0x40000000UL /**< Bit mask for VDAC_OPA2OUTVALID */ #define _VDAC_IFS_OPA2OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */ #define VDAC_IFS_OPA2OUTVALID_DEFAULT (_VDAC_IFS_OPA2OUTVALID_DEFAULT << 30) /**< Shifted mode DEFAULT for VDAC_IFS */ /* Bit fields for VDAC IFC */ #define _VDAC_IFC_RESETVALUE 0x00000000UL /**< Default value for VDAC_IFC */ #define _VDAC_IFC_MASK 0x7077803FUL /**< Mask for VDAC_IFC */ #define VDAC_IFC_CH0CD (0x1UL << 0) /**< Clear CH0CD Interrupt Flag */ #define _VDAC_IFC_CH0CD_SHIFT 0 /**< Shift value for VDAC_CH0CD */ #define _VDAC_IFC_CH0CD_MASK 0x1UL /**< Bit mask for VDAC_CH0CD */ #define _VDAC_IFC_CH0CD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */ #define VDAC_IFC_CH0CD_DEFAULT (_VDAC_IFC_CH0CD_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_IFC */ #define VDAC_IFC_CH1CD (0x1UL << 1) /**< Clear CH1CD Interrupt Flag */ #define _VDAC_IFC_CH1CD_SHIFT 1 /**< Shift value for VDAC_CH1CD */ #define _VDAC_IFC_CH1CD_MASK 0x2UL /**< Bit mask for VDAC_CH1CD */ #define _VDAC_IFC_CH1CD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */ #define VDAC_IFC_CH1CD_DEFAULT (_VDAC_IFC_CH1CD_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_IFC */ #define VDAC_IFC_CH0OF (0x1UL << 2) /**< Clear CH0OF Interrupt Flag */ #define _VDAC_IFC_CH0OF_SHIFT 2 /**< Shift value for VDAC_CH0OF */ #define _VDAC_IFC_CH0OF_MASK 0x4UL /**< Bit mask for VDAC_CH0OF */ #define _VDAC_IFC_CH0OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */ #define VDAC_IFC_CH0OF_DEFAULT (_VDAC_IFC_CH0OF_DEFAULT << 2) /**< Shifted mode DEFAULT for VDAC_IFC */ #define VDAC_IFC_CH1OF (0x1UL << 3) /**< Clear CH1OF Interrupt Flag */ #define _VDAC_IFC_CH1OF_SHIFT 3 /**< Shift value for VDAC_CH1OF */ #define _VDAC_IFC_CH1OF_MASK 0x8UL /**< Bit mask for VDAC_CH1OF */ #define _VDAC_IFC_CH1OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */ #define VDAC_IFC_CH1OF_DEFAULT (_VDAC_IFC_CH1OF_DEFAULT << 3) /**< Shifted mode DEFAULT for VDAC_IFC */ #define VDAC_IFC_CH0UF (0x1UL << 4) /**< Clear CH0UF Interrupt Flag */ #define _VDAC_IFC_CH0UF_SHIFT 4 /**< Shift value for VDAC_CH0UF */ #define _VDAC_IFC_CH0UF_MASK 0x10UL /**< Bit mask for VDAC_CH0UF */ #define _VDAC_IFC_CH0UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */ #define VDAC_IFC_CH0UF_DEFAULT (_VDAC_IFC_CH0UF_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_IFC */ #define VDAC_IFC_CH1UF (0x1UL << 5) /**< Clear CH1UF Interrupt Flag */ #define _VDAC_IFC_CH1UF_SHIFT 5 /**< Shift value for VDAC_CH1UF */ #define _VDAC_IFC_CH1UF_MASK 0x20UL /**< Bit mask for VDAC_CH1UF */ #define _VDAC_IFC_CH1UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */ #define VDAC_IFC_CH1UF_DEFAULT (_VDAC_IFC_CH1UF_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_IFC */ #define VDAC_IFC_EM23ERR (0x1UL << 15) /**< Clear EM23ERR Interrupt Flag */ #define _VDAC_IFC_EM23ERR_SHIFT 15 /**< Shift value for VDAC_EM23ERR */ #define _VDAC_IFC_EM23ERR_MASK 0x8000UL /**< Bit mask for VDAC_EM23ERR */ #define _VDAC_IFC_EM23ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */ #define VDAC_IFC_EM23ERR_DEFAULT (_VDAC_IFC_EM23ERR_DEFAULT << 15) /**< Shifted mode DEFAULT for VDAC_IFC */ #define VDAC_IFC_OPA0APORTCONFLICT (0x1UL << 16) /**< Clear OPA0APORTCONFLICT Interrupt Flag */ #define _VDAC_IFC_OPA0APORTCONFLICT_SHIFT 16 /**< Shift value for VDAC_OPA0APORTCONFLICT */ #define _VDAC_IFC_OPA0APORTCONFLICT_MASK 0x10000UL /**< Bit mask for VDAC_OPA0APORTCONFLICT */ #define _VDAC_IFC_OPA0APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */ #define VDAC_IFC_OPA0APORTCONFLICT_DEFAULT (_VDAC_IFC_OPA0APORTCONFLICT_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_IFC */ #define VDAC_IFC_OPA1APORTCONFLICT (0x1UL << 17) /**< Clear OPA1APORTCONFLICT Interrupt Flag */ #define _VDAC_IFC_OPA1APORTCONFLICT_SHIFT 17 /**< Shift value for VDAC_OPA1APORTCONFLICT */ #define _VDAC_IFC_OPA1APORTCONFLICT_MASK 0x20000UL /**< Bit mask for VDAC_OPA1APORTCONFLICT */ #define _VDAC_IFC_OPA1APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */ #define VDAC_IFC_OPA1APORTCONFLICT_DEFAULT (_VDAC_IFC_OPA1APORTCONFLICT_DEFAULT << 17) /**< Shifted mode DEFAULT for VDAC_IFC */ #define VDAC_IFC_OPA2APORTCONFLICT (0x1UL << 18) /**< Clear OPA2APORTCONFLICT Interrupt Flag */ #define _VDAC_IFC_OPA2APORTCONFLICT_SHIFT 18 /**< Shift value for VDAC_OPA2APORTCONFLICT */ #define _VDAC_IFC_OPA2APORTCONFLICT_MASK 0x40000UL /**< Bit mask for VDAC_OPA2APORTCONFLICT */ #define _VDAC_IFC_OPA2APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */ #define VDAC_IFC_OPA2APORTCONFLICT_DEFAULT (_VDAC_IFC_OPA2APORTCONFLICT_DEFAULT << 18) /**< Shifted mode DEFAULT for VDAC_IFC */ #define VDAC_IFC_OPA0PRSTIMEDERR (0x1UL << 20) /**< Clear OPA0PRSTIMEDERR Interrupt Flag */ #define _VDAC_IFC_OPA0PRSTIMEDERR_SHIFT 20 /**< Shift value for VDAC_OPA0PRSTIMEDERR */ #define _VDAC_IFC_OPA0PRSTIMEDERR_MASK 0x100000UL /**< Bit mask for VDAC_OPA0PRSTIMEDERR */ #define _VDAC_IFC_OPA0PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */ #define VDAC_IFC_OPA0PRSTIMEDERR_DEFAULT (_VDAC_IFC_OPA0PRSTIMEDERR_DEFAULT << 20) /**< Shifted mode DEFAULT for VDAC_IFC */ #define VDAC_IFC_OPA1PRSTIMEDERR (0x1UL << 21) /**< Clear OPA1PRSTIMEDERR Interrupt Flag */ #define _VDAC_IFC_OPA1PRSTIMEDERR_SHIFT 21 /**< Shift value for VDAC_OPA1PRSTIMEDERR */ #define _VDAC_IFC_OPA1PRSTIMEDERR_MASK 0x200000UL /**< Bit mask for VDAC_OPA1PRSTIMEDERR */ #define _VDAC_IFC_OPA1PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */ #define VDAC_IFC_OPA1PRSTIMEDERR_DEFAULT (_VDAC_IFC_OPA1PRSTIMEDERR_DEFAULT << 21) /**< Shifted mode DEFAULT for VDAC_IFC */ #define VDAC_IFC_OPA2PRSTIMEDERR (0x1UL << 22) /**< Clear OPA2PRSTIMEDERR Interrupt Flag */ #define _VDAC_IFC_OPA2PRSTIMEDERR_SHIFT 22 /**< Shift value for VDAC_OPA2PRSTIMEDERR */ #define _VDAC_IFC_OPA2PRSTIMEDERR_MASK 0x400000UL /**< Bit mask for VDAC_OPA2PRSTIMEDERR */ #define _VDAC_IFC_OPA2PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */ #define VDAC_IFC_OPA2PRSTIMEDERR_DEFAULT (_VDAC_IFC_OPA2PRSTIMEDERR_DEFAULT << 22) /**< Shifted mode DEFAULT for VDAC_IFC */ #define VDAC_IFC_OPA0OUTVALID (0x1UL << 28) /**< Clear OPA0OUTVALID Interrupt Flag */ #define _VDAC_IFC_OPA0OUTVALID_SHIFT 28 /**< Shift value for VDAC_OPA0OUTVALID */ #define _VDAC_IFC_OPA0OUTVALID_MASK 0x10000000UL /**< Bit mask for VDAC_OPA0OUTVALID */ #define _VDAC_IFC_OPA0OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */ #define VDAC_IFC_OPA0OUTVALID_DEFAULT (_VDAC_IFC_OPA0OUTVALID_DEFAULT << 28) /**< Shifted mode DEFAULT for VDAC_IFC */ #define VDAC_IFC_OPA1OUTVALID (0x1UL << 29) /**< Clear OPA1OUTVALID Interrupt Flag */ #define _VDAC_IFC_OPA1OUTVALID_SHIFT 29 /**< Shift value for VDAC_OPA1OUTVALID */ #define _VDAC_IFC_OPA1OUTVALID_MASK 0x20000000UL /**< Bit mask for VDAC_OPA1OUTVALID */ #define _VDAC_IFC_OPA1OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */ #define VDAC_IFC_OPA1OUTVALID_DEFAULT (_VDAC_IFC_OPA1OUTVALID_DEFAULT << 29) /**< Shifted mode DEFAULT for VDAC_IFC */ #define VDAC_IFC_OPA2OUTVALID (0x1UL << 30) /**< Clear OPA2OUTVALID Interrupt Flag */ #define _VDAC_IFC_OPA2OUTVALID_SHIFT 30 /**< Shift value for VDAC_OPA2OUTVALID */ #define _VDAC_IFC_OPA2OUTVALID_MASK 0x40000000UL /**< Bit mask for VDAC_OPA2OUTVALID */ #define _VDAC_IFC_OPA2OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */ #define VDAC_IFC_OPA2OUTVALID_DEFAULT (_VDAC_IFC_OPA2OUTVALID_DEFAULT << 30) /**< Shifted mode DEFAULT for VDAC_IFC */ /* Bit fields for VDAC IEN */ #define _VDAC_IEN_RESETVALUE 0x00000000UL /**< Default value for VDAC_IEN */ #define _VDAC_IEN_MASK 0x707780FFUL /**< Mask for VDAC_IEN */ #define VDAC_IEN_CH0CD (0x1UL << 0) /**< CH0CD Interrupt Enable */ #define _VDAC_IEN_CH0CD_SHIFT 0 /**< Shift value for VDAC_CH0CD */ #define _VDAC_IEN_CH0CD_MASK 0x1UL /**< Bit mask for VDAC_CH0CD */ #define _VDAC_IEN_CH0CD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ #define VDAC_IEN_CH0CD_DEFAULT (_VDAC_IEN_CH0CD_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_IEN */ #define VDAC_IEN_CH1CD (0x1UL << 1) /**< CH1CD Interrupt Enable */ #define _VDAC_IEN_CH1CD_SHIFT 1 /**< Shift value for VDAC_CH1CD */ #define _VDAC_IEN_CH1CD_MASK 0x2UL /**< Bit mask for VDAC_CH1CD */ #define _VDAC_IEN_CH1CD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ #define VDAC_IEN_CH1CD_DEFAULT (_VDAC_IEN_CH1CD_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_IEN */ #define VDAC_IEN_CH0OF (0x1UL << 2) /**< CH0OF Interrupt Enable */ #define _VDAC_IEN_CH0OF_SHIFT 2 /**< Shift value for VDAC_CH0OF */ #define _VDAC_IEN_CH0OF_MASK 0x4UL /**< Bit mask for VDAC_CH0OF */ #define _VDAC_IEN_CH0OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ #define VDAC_IEN_CH0OF_DEFAULT (_VDAC_IEN_CH0OF_DEFAULT << 2) /**< Shifted mode DEFAULT for VDAC_IEN */ #define VDAC_IEN_CH1OF (0x1UL << 3) /**< CH1OF Interrupt Enable */ #define _VDAC_IEN_CH1OF_SHIFT 3 /**< Shift value for VDAC_CH1OF */ #define _VDAC_IEN_CH1OF_MASK 0x8UL /**< Bit mask for VDAC_CH1OF */ #define _VDAC_IEN_CH1OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ #define VDAC_IEN_CH1OF_DEFAULT (_VDAC_IEN_CH1OF_DEFAULT << 3) /**< Shifted mode DEFAULT for VDAC_IEN */ #define VDAC_IEN_CH0UF (0x1UL << 4) /**< CH0UF Interrupt Enable */ #define _VDAC_IEN_CH0UF_SHIFT 4 /**< Shift value for VDAC_CH0UF */ #define _VDAC_IEN_CH0UF_MASK 0x10UL /**< Bit mask for VDAC_CH0UF */ #define _VDAC_IEN_CH0UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ #define VDAC_IEN_CH0UF_DEFAULT (_VDAC_IEN_CH0UF_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_IEN */ #define VDAC_IEN_CH1UF (0x1UL << 5) /**< CH1UF Interrupt Enable */ #define _VDAC_IEN_CH1UF_SHIFT 5 /**< Shift value for VDAC_CH1UF */ #define _VDAC_IEN_CH1UF_MASK 0x20UL /**< Bit mask for VDAC_CH1UF */ #define _VDAC_IEN_CH1UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ #define VDAC_IEN_CH1UF_DEFAULT (_VDAC_IEN_CH1UF_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_IEN */ #define VDAC_IEN_CH0BL (0x1UL << 6) /**< CH0BL Interrupt Enable */ #define _VDAC_IEN_CH0BL_SHIFT 6 /**< Shift value for VDAC_CH0BL */ #define _VDAC_IEN_CH0BL_MASK 0x40UL /**< Bit mask for VDAC_CH0BL */ #define _VDAC_IEN_CH0BL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ #define VDAC_IEN_CH0BL_DEFAULT (_VDAC_IEN_CH0BL_DEFAULT << 6) /**< Shifted mode DEFAULT for VDAC_IEN */ #define VDAC_IEN_CH1BL (0x1UL << 7) /**< CH1BL Interrupt Enable */ #define _VDAC_IEN_CH1BL_SHIFT 7 /**< Shift value for VDAC_CH1BL */ #define _VDAC_IEN_CH1BL_MASK 0x80UL /**< Bit mask for VDAC_CH1BL */ #define _VDAC_IEN_CH1BL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ #define VDAC_IEN_CH1BL_DEFAULT (_VDAC_IEN_CH1BL_DEFAULT << 7) /**< Shifted mode DEFAULT for VDAC_IEN */ #define VDAC_IEN_EM23ERR (0x1UL << 15) /**< EM23ERR Interrupt Enable */ #define _VDAC_IEN_EM23ERR_SHIFT 15 /**< Shift value for VDAC_EM23ERR */ #define _VDAC_IEN_EM23ERR_MASK 0x8000UL /**< Bit mask for VDAC_EM23ERR */ #define _VDAC_IEN_EM23ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ #define VDAC_IEN_EM23ERR_DEFAULT (_VDAC_IEN_EM23ERR_DEFAULT << 15) /**< Shifted mode DEFAULT for VDAC_IEN */ #define VDAC_IEN_OPA0APORTCONFLICT (0x1UL << 16) /**< OPA0APORTCONFLICT Interrupt Enable */ #define _VDAC_IEN_OPA0APORTCONFLICT_SHIFT 16 /**< Shift value for VDAC_OPA0APORTCONFLICT */ #define _VDAC_IEN_OPA0APORTCONFLICT_MASK 0x10000UL /**< Bit mask for VDAC_OPA0APORTCONFLICT */ #define _VDAC_IEN_OPA0APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ #define VDAC_IEN_OPA0APORTCONFLICT_DEFAULT (_VDAC_IEN_OPA0APORTCONFLICT_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_IEN */ #define VDAC_IEN_OPA1APORTCONFLICT (0x1UL << 17) /**< OPA1APORTCONFLICT Interrupt Enable */ #define _VDAC_IEN_OPA1APORTCONFLICT_SHIFT 17 /**< Shift value for VDAC_OPA1APORTCONFLICT */ #define _VDAC_IEN_OPA1APORTCONFLICT_MASK 0x20000UL /**< Bit mask for VDAC_OPA1APORTCONFLICT */ #define _VDAC_IEN_OPA1APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ #define VDAC_IEN_OPA1APORTCONFLICT_DEFAULT (_VDAC_IEN_OPA1APORTCONFLICT_DEFAULT << 17) /**< Shifted mode DEFAULT for VDAC_IEN */ #define VDAC_IEN_OPA2APORTCONFLICT (0x1UL << 18) /**< OPA2APORTCONFLICT Interrupt Enable */ #define _VDAC_IEN_OPA2APORTCONFLICT_SHIFT 18 /**< Shift value for VDAC_OPA2APORTCONFLICT */ #define _VDAC_IEN_OPA2APORTCONFLICT_MASK 0x40000UL /**< Bit mask for VDAC_OPA2APORTCONFLICT */ #define _VDAC_IEN_OPA2APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ #define VDAC_IEN_OPA2APORTCONFLICT_DEFAULT (_VDAC_IEN_OPA2APORTCONFLICT_DEFAULT << 18) /**< Shifted mode DEFAULT for VDAC_IEN */ #define VDAC_IEN_OPA0PRSTIMEDERR (0x1UL << 20) /**< OPA0PRSTIMEDERR Interrupt Enable */ #define _VDAC_IEN_OPA0PRSTIMEDERR_SHIFT 20 /**< Shift value for VDAC_OPA0PRSTIMEDERR */ #define _VDAC_IEN_OPA0PRSTIMEDERR_MASK 0x100000UL /**< Bit mask for VDAC_OPA0PRSTIMEDERR */ #define _VDAC_IEN_OPA0PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ #define VDAC_IEN_OPA0PRSTIMEDERR_DEFAULT (_VDAC_IEN_OPA0PRSTIMEDERR_DEFAULT << 20) /**< Shifted mode DEFAULT for VDAC_IEN */ #define VDAC_IEN_OPA1PRSTIMEDERR (0x1UL << 21) /**< OPA1PRSTIMEDERR Interrupt Enable */ #define _VDAC_IEN_OPA1PRSTIMEDERR_SHIFT 21 /**< Shift value for VDAC_OPA1PRSTIMEDERR */ #define _VDAC_IEN_OPA1PRSTIMEDERR_MASK 0x200000UL /**< Bit mask for VDAC_OPA1PRSTIMEDERR */ #define _VDAC_IEN_OPA1PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ #define VDAC_IEN_OPA1PRSTIMEDERR_DEFAULT (_VDAC_IEN_OPA1PRSTIMEDERR_DEFAULT << 21) /**< Shifted mode DEFAULT for VDAC_IEN */ #define VDAC_IEN_OPA2PRSTIMEDERR (0x1UL << 22) /**< OPA2PRSTIMEDERR Interrupt Enable */ #define _VDAC_IEN_OPA2PRSTIMEDERR_SHIFT 22 /**< Shift value for VDAC_OPA2PRSTIMEDERR */ #define _VDAC_IEN_OPA2PRSTIMEDERR_MASK 0x400000UL /**< Bit mask for VDAC_OPA2PRSTIMEDERR */ #define _VDAC_IEN_OPA2PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ #define VDAC_IEN_OPA2PRSTIMEDERR_DEFAULT (_VDAC_IEN_OPA2PRSTIMEDERR_DEFAULT << 22) /**< Shifted mode DEFAULT for VDAC_IEN */ #define VDAC_IEN_OPA0OUTVALID (0x1UL << 28) /**< OPA0OUTVALID Interrupt Enable */ #define _VDAC_IEN_OPA0OUTVALID_SHIFT 28 /**< Shift value for VDAC_OPA0OUTVALID */ #define _VDAC_IEN_OPA0OUTVALID_MASK 0x10000000UL /**< Bit mask for VDAC_OPA0OUTVALID */ #define _VDAC_IEN_OPA0OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ #define VDAC_IEN_OPA0OUTVALID_DEFAULT (_VDAC_IEN_OPA0OUTVALID_DEFAULT << 28) /**< Shifted mode DEFAULT for VDAC_IEN */ #define VDAC_IEN_OPA1OUTVALID (0x1UL << 29) /**< OPA1OUTVALID Interrupt Enable */ #define _VDAC_IEN_OPA1OUTVALID_SHIFT 29 /**< Shift value for VDAC_OPA1OUTVALID */ #define _VDAC_IEN_OPA1OUTVALID_MASK 0x20000000UL /**< Bit mask for VDAC_OPA1OUTVALID */ #define _VDAC_IEN_OPA1OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ #define VDAC_IEN_OPA1OUTVALID_DEFAULT (_VDAC_IEN_OPA1OUTVALID_DEFAULT << 29) /**< Shifted mode DEFAULT for VDAC_IEN */ #define VDAC_IEN_OPA2OUTVALID (0x1UL << 30) /**< OPA2OUTVALID Interrupt Enable */ #define _VDAC_IEN_OPA2OUTVALID_SHIFT 30 /**< Shift value for VDAC_OPA2OUTVALID */ #define _VDAC_IEN_OPA2OUTVALID_MASK 0x40000000UL /**< Bit mask for VDAC_OPA2OUTVALID */ #define _VDAC_IEN_OPA2OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ #define VDAC_IEN_OPA2OUTVALID_DEFAULT (_VDAC_IEN_OPA2OUTVALID_DEFAULT << 30) /**< Shifted mode DEFAULT for VDAC_IEN */ /* Bit fields for VDAC CH0DATA */ #define _VDAC_CH0DATA_RESETVALUE 0x00000800UL /**< Default value for VDAC_CH0DATA */ #define _VDAC_CH0DATA_MASK 0x00000FFFUL /**< Mask for VDAC_CH0DATA */ #define _VDAC_CH0DATA_DATA_SHIFT 0 /**< Shift value for VDAC_DATA */ #define _VDAC_CH0DATA_DATA_MASK 0xFFFUL /**< Bit mask for VDAC_DATA */ #define _VDAC_CH0DATA_DATA_DEFAULT 0x00000800UL /**< Mode DEFAULT for VDAC_CH0DATA */ #define VDAC_CH0DATA_DATA_DEFAULT (_VDAC_CH0DATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CH0DATA */ /* Bit fields for VDAC CH1DATA */ #define _VDAC_CH1DATA_RESETVALUE 0x00000800UL /**< Default value for VDAC_CH1DATA */ #define _VDAC_CH1DATA_MASK 0x00000FFFUL /**< Mask for VDAC_CH1DATA */ #define _VDAC_CH1DATA_DATA_SHIFT 0 /**< Shift value for VDAC_DATA */ #define _VDAC_CH1DATA_DATA_MASK 0xFFFUL /**< Bit mask for VDAC_DATA */ #define _VDAC_CH1DATA_DATA_DEFAULT 0x00000800UL /**< Mode DEFAULT for VDAC_CH1DATA */ #define VDAC_CH1DATA_DATA_DEFAULT (_VDAC_CH1DATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CH1DATA */ /* Bit fields for VDAC COMBDATA */ #define _VDAC_COMBDATA_RESETVALUE 0x08000800UL /**< Default value for VDAC_COMBDATA */ #define _VDAC_COMBDATA_MASK 0x0FFF0FFFUL /**< Mask for VDAC_COMBDATA */ #define _VDAC_COMBDATA_CH0DATA_SHIFT 0 /**< Shift value for VDAC_CH0DATA */ #define _VDAC_COMBDATA_CH0DATA_MASK 0xFFFUL /**< Bit mask for VDAC_CH0DATA */ #define _VDAC_COMBDATA_CH0DATA_DEFAULT 0x00000800UL /**< Mode DEFAULT for VDAC_COMBDATA */ #define VDAC_COMBDATA_CH0DATA_DEFAULT (_VDAC_COMBDATA_CH0DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_COMBDATA */ #define _VDAC_COMBDATA_CH1DATA_SHIFT 16 /**< Shift value for VDAC_CH1DATA */ #define _VDAC_COMBDATA_CH1DATA_MASK 0xFFF0000UL /**< Bit mask for VDAC_CH1DATA */ #define _VDAC_COMBDATA_CH1DATA_DEFAULT 0x00000800UL /**< Mode DEFAULT for VDAC_COMBDATA */ #define VDAC_COMBDATA_CH1DATA_DEFAULT (_VDAC_COMBDATA_CH1DATA_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_COMBDATA */ /* Bit fields for VDAC CAL */ #define _VDAC_CAL_RESETVALUE 0x00082004UL /**< Default value for VDAC_CAL */ #define _VDAC_CAL_MASK 0x000F3F07UL /**< Mask for VDAC_CAL */ #define _VDAC_CAL_OFFSETTRIM_SHIFT 0 /**< Shift value for VDAC_OFFSETTRIM */ #define _VDAC_CAL_OFFSETTRIM_MASK 0x7UL /**< Bit mask for VDAC_OFFSETTRIM */ #define _VDAC_CAL_OFFSETTRIM_DEFAULT 0x00000004UL /**< Mode DEFAULT for VDAC_CAL */ #define VDAC_CAL_OFFSETTRIM_DEFAULT (_VDAC_CAL_OFFSETTRIM_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CAL */ #define _VDAC_CAL_GAINERRTRIM_SHIFT 8 /**< Shift value for VDAC_GAINERRTRIM */ #define _VDAC_CAL_GAINERRTRIM_MASK 0x3F00UL /**< Bit mask for VDAC_GAINERRTRIM */ #define _VDAC_CAL_GAINERRTRIM_DEFAULT 0x00000020UL /**< Mode DEFAULT for VDAC_CAL */ #define VDAC_CAL_GAINERRTRIM_DEFAULT (_VDAC_CAL_GAINERRTRIM_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_CAL */ #define _VDAC_CAL_GAINERRTRIMCH1_SHIFT 16 /**< Shift value for VDAC_GAINERRTRIMCH1 */ #define _VDAC_CAL_GAINERRTRIMCH1_MASK 0xF0000UL /**< Bit mask for VDAC_GAINERRTRIMCH1 */ #define _VDAC_CAL_GAINERRTRIMCH1_DEFAULT 0x00000008UL /**< Mode DEFAULT for VDAC_CAL */ #define VDAC_CAL_GAINERRTRIMCH1_DEFAULT (_VDAC_CAL_GAINERRTRIMCH1_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_CAL */ /* Bit fields for VDAC OPA_APORTREQ */ #define _VDAC_OPA_APORTREQ_RESETVALUE 0x00000000UL /**< Default value for VDAC_OPA_APORTREQ */ #define _VDAC_OPA_APORTREQ_MASK 0x000003FCUL /**< Mask for VDAC_OPA_APORTREQ */ #define VDAC_OPA_APORTREQ_APORT1XREQ (0x1UL << 2) /**< 1 If the Bus Connected to APORT2X is Requested */ #define _VDAC_OPA_APORTREQ_APORT1XREQ_SHIFT 2 /**< Shift value for VDAC_OPAAPORT1XREQ */ #define _VDAC_OPA_APORTREQ_APORT1XREQ_MASK 0x4UL /**< Bit mask for VDAC_OPAAPORT1XREQ */ #define _VDAC_OPA_APORTREQ_APORT1XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTREQ */ #define VDAC_OPA_APORTREQ_APORT1XREQ_DEFAULT (_VDAC_OPA_APORTREQ_APORT1XREQ_DEFAULT << 2) /**< Shifted mode DEFAULT for VDAC_OPA_APORTREQ */ #define VDAC_OPA_APORTREQ_APORT1YREQ (0x1UL << 3) /**< 1 If the Bus Connected to APORT1X is Requested */ #define _VDAC_OPA_APORTREQ_APORT1YREQ_SHIFT 3 /**< Shift value for VDAC_OPAAPORT1YREQ */ #define _VDAC_OPA_APORTREQ_APORT1YREQ_MASK 0x8UL /**< Bit mask for VDAC_OPAAPORT1YREQ */ #define _VDAC_OPA_APORTREQ_APORT1YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTREQ */ #define VDAC_OPA_APORTREQ_APORT1YREQ_DEFAULT (_VDAC_OPA_APORTREQ_APORT1YREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for VDAC_OPA_APORTREQ */ #define VDAC_OPA_APORTREQ_APORT2XREQ (0x1UL << 4) /**< 1 If the Bus Connected to APORT2X is Requested */ #define _VDAC_OPA_APORTREQ_APORT2XREQ_SHIFT 4 /**< Shift value for VDAC_OPAAPORT2XREQ */ #define _VDAC_OPA_APORTREQ_APORT2XREQ_MASK 0x10UL /**< Bit mask for VDAC_OPAAPORT2XREQ */ #define _VDAC_OPA_APORTREQ_APORT2XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTREQ */ #define VDAC_OPA_APORTREQ_APORT2XREQ_DEFAULT (_VDAC_OPA_APORTREQ_APORT2XREQ_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_OPA_APORTREQ */ #define VDAC_OPA_APORTREQ_APORT2YREQ (0x1UL << 5) /**< 1 If the Bus Connected to APORT2Y is Requested */ #define _VDAC_OPA_APORTREQ_APORT2YREQ_SHIFT 5 /**< Shift value for VDAC_OPAAPORT2YREQ */ #define _VDAC_OPA_APORTREQ_APORT2YREQ_MASK 0x20UL /**< Bit mask for VDAC_OPAAPORT2YREQ */ #define _VDAC_OPA_APORTREQ_APORT2YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTREQ */ #define VDAC_OPA_APORTREQ_APORT2YREQ_DEFAULT (_VDAC_OPA_APORTREQ_APORT2YREQ_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_OPA_APORTREQ */ #define VDAC_OPA_APORTREQ_APORT3XREQ (0x1UL << 6) /**< 1 If the Bus Connected to APORT3X is Requested */ #define _VDAC_OPA_APORTREQ_APORT3XREQ_SHIFT 6 /**< Shift value for VDAC_OPAAPORT3XREQ */ #define _VDAC_OPA_APORTREQ_APORT3XREQ_MASK 0x40UL /**< Bit mask for VDAC_OPAAPORT3XREQ */ #define _VDAC_OPA_APORTREQ_APORT3XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTREQ */ #define VDAC_OPA_APORTREQ_APORT3XREQ_DEFAULT (_VDAC_OPA_APORTREQ_APORT3XREQ_DEFAULT << 6) /**< Shifted mode DEFAULT for VDAC_OPA_APORTREQ */ #define VDAC_OPA_APORTREQ_APORT3YREQ (0x1UL << 7) /**< 1 If the Bus Connected to APORT3Y is Requested */ #define _VDAC_OPA_APORTREQ_APORT3YREQ_SHIFT 7 /**< Shift value for VDAC_OPAAPORT3YREQ */ #define _VDAC_OPA_APORTREQ_APORT3YREQ_MASK 0x80UL /**< Bit mask for VDAC_OPAAPORT3YREQ */ #define _VDAC_OPA_APORTREQ_APORT3YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTREQ */ #define VDAC_OPA_APORTREQ_APORT3YREQ_DEFAULT (_VDAC_OPA_APORTREQ_APORT3YREQ_DEFAULT << 7) /**< Shifted mode DEFAULT for VDAC_OPA_APORTREQ */ #define VDAC_OPA_APORTREQ_APORT4XREQ (0x1UL << 8) /**< 1 If the Bus Connected to APORT4X is Requested */ #define _VDAC_OPA_APORTREQ_APORT4XREQ_SHIFT 8 /**< Shift value for VDAC_OPAAPORT4XREQ */ #define _VDAC_OPA_APORTREQ_APORT4XREQ_MASK 0x100UL /**< Bit mask for VDAC_OPAAPORT4XREQ */ #define _VDAC_OPA_APORTREQ_APORT4XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTREQ */ #define VDAC_OPA_APORTREQ_APORT4XREQ_DEFAULT (_VDAC_OPA_APORTREQ_APORT4XREQ_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_OPA_APORTREQ */ #define VDAC_OPA_APORTREQ_APORT4YREQ (0x1UL << 9) /**< 1 If the Bus Connected to APORT4Y is Requested */ #define _VDAC_OPA_APORTREQ_APORT4YREQ_SHIFT 9 /**< Shift value for VDAC_OPAAPORT4YREQ */ #define _VDAC_OPA_APORTREQ_APORT4YREQ_MASK 0x200UL /**< Bit mask for VDAC_OPAAPORT4YREQ */ #define _VDAC_OPA_APORTREQ_APORT4YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTREQ */ #define VDAC_OPA_APORTREQ_APORT4YREQ_DEFAULT (_VDAC_OPA_APORTREQ_APORT4YREQ_DEFAULT << 9) /**< Shifted mode DEFAULT for VDAC_OPA_APORTREQ */ /* Bit fields for VDAC OPA_APORTCONFLICT */ #define _VDAC_OPA_APORTCONFLICT_RESETVALUE 0x00000000UL /**< Default value for VDAC_OPA_APORTCONFLICT */ #define _VDAC_OPA_APORTCONFLICT_MASK 0x000003FCUL /**< Mask for VDAC_OPA_APORTCONFLICT */ #define VDAC_OPA_APORTCONFLICT_APORT1XCONFLICT (0x1UL << 2) /**< 1 If the Bus Connected to APORT1X is in Conflict With Another Peripheral */ #define _VDAC_OPA_APORTCONFLICT_APORT1XCONFLICT_SHIFT 2 /**< Shift value for VDAC_OPAAPORT1XCONFLICT */ #define _VDAC_OPA_APORTCONFLICT_APORT1XCONFLICT_MASK 0x4UL /**< Bit mask for VDAC_OPAAPORT1XCONFLICT */ #define _VDAC_OPA_APORTCONFLICT_APORT1XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTCONFLICT */ #define VDAC_OPA_APORTCONFLICT_APORT1XCONFLICT_DEFAULT (_VDAC_OPA_APORTCONFLICT_APORT1XCONFLICT_DEFAULT << 2) /**< Shifted mode DEFAULT for VDAC_OPA_APORTCONFLICT */ #define VDAC_OPA_APORTCONFLICT_APORT1YCONFLICT (0x1UL << 3) /**< 1 If the Bus Connected to APORT1X is in Conflict With Another Peripheral */ #define _VDAC_OPA_APORTCONFLICT_APORT1YCONFLICT_SHIFT 3 /**< Shift value for VDAC_OPAAPORT1YCONFLICT */ #define _VDAC_OPA_APORTCONFLICT_APORT1YCONFLICT_MASK 0x8UL /**< Bit mask for VDAC_OPAAPORT1YCONFLICT */ #define _VDAC_OPA_APORTCONFLICT_APORT1YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTCONFLICT */ #define VDAC_OPA_APORTCONFLICT_APORT1YCONFLICT_DEFAULT (_VDAC_OPA_APORTCONFLICT_APORT1YCONFLICT_DEFAULT << 3) /**< Shifted mode DEFAULT for VDAC_OPA_APORTCONFLICT */ #define VDAC_OPA_APORTCONFLICT_APORT2XCONFLICT (0x1UL << 4) /**< 1 If the Bus Connected to APORT2X is in Conflict With Another Peripheral */ #define _VDAC_OPA_APORTCONFLICT_APORT2XCONFLICT_SHIFT 4 /**< Shift value for VDAC_OPAAPORT2XCONFLICT */ #define _VDAC_OPA_APORTCONFLICT_APORT2XCONFLICT_MASK 0x10UL /**< Bit mask for VDAC_OPAAPORT2XCONFLICT */ #define _VDAC_OPA_APORTCONFLICT_APORT2XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTCONFLICT */ #define VDAC_OPA_APORTCONFLICT_APORT2XCONFLICT_DEFAULT (_VDAC_OPA_APORTCONFLICT_APORT2XCONFLICT_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_OPA_APORTCONFLICT */ #define VDAC_OPA_APORTCONFLICT_APORT2YCONFLICT (0x1UL << 5) /**< 1 If the Bus Connected to APORT2Y is in Conflict With Another Peripheral */ #define _VDAC_OPA_APORTCONFLICT_APORT2YCONFLICT_SHIFT 5 /**< Shift value for VDAC_OPAAPORT2YCONFLICT */ #define _VDAC_OPA_APORTCONFLICT_APORT2YCONFLICT_MASK 0x20UL /**< Bit mask for VDAC_OPAAPORT2YCONFLICT */ #define _VDAC_OPA_APORTCONFLICT_APORT2YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTCONFLICT */ #define VDAC_OPA_APORTCONFLICT_APORT2YCONFLICT_DEFAULT (_VDAC_OPA_APORTCONFLICT_APORT2YCONFLICT_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_OPA_APORTCONFLICT */ #define VDAC_OPA_APORTCONFLICT_APORT3XCONFLICT (0x1UL << 6) /**< 1 If the Bus Connected to APORT3X is in Conflict With Another Peripheral */ #define _VDAC_OPA_APORTCONFLICT_APORT3XCONFLICT_SHIFT 6 /**< Shift value for VDAC_OPAAPORT3XCONFLICT */ #define _VDAC_OPA_APORTCONFLICT_APORT3XCONFLICT_MASK 0x40UL /**< Bit mask for VDAC_OPAAPORT3XCONFLICT */ #define _VDAC_OPA_APORTCONFLICT_APORT3XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTCONFLICT */ #define VDAC_OPA_APORTCONFLICT_APORT3XCONFLICT_DEFAULT (_VDAC_OPA_APORTCONFLICT_APORT3XCONFLICT_DEFAULT << 6) /**< Shifted mode DEFAULT for VDAC_OPA_APORTCONFLICT */ #define VDAC_OPA_APORTCONFLICT_APORT3YCONFLICT (0x1UL << 7) /**< 1 If the Bus Connected to APORT3Y is in Conflict With Another Peripheral */ #define _VDAC_OPA_APORTCONFLICT_APORT3YCONFLICT_SHIFT 7 /**< Shift value for VDAC_OPAAPORT3YCONFLICT */ #define _VDAC_OPA_APORTCONFLICT_APORT3YCONFLICT_MASK 0x80UL /**< Bit mask for VDAC_OPAAPORT3YCONFLICT */ #define _VDAC_OPA_APORTCONFLICT_APORT3YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTCONFLICT */ #define VDAC_OPA_APORTCONFLICT_APORT3YCONFLICT_DEFAULT (_VDAC_OPA_APORTCONFLICT_APORT3YCONFLICT_DEFAULT << 7) /**< Shifted mode DEFAULT for VDAC_OPA_APORTCONFLICT */ #define VDAC_OPA_APORTCONFLICT_APORT4XCONFLICT (0x1UL << 8) /**< 1 If the Bus Connected to APORT4X is in Conflict With Another Peripheral */ #define _VDAC_OPA_APORTCONFLICT_APORT4XCONFLICT_SHIFT 8 /**< Shift value for VDAC_OPAAPORT4XCONFLICT */ #define _VDAC_OPA_APORTCONFLICT_APORT4XCONFLICT_MASK 0x100UL /**< Bit mask for VDAC_OPAAPORT4XCONFLICT */ #define _VDAC_OPA_APORTCONFLICT_APORT4XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTCONFLICT */ #define VDAC_OPA_APORTCONFLICT_APORT4XCONFLICT_DEFAULT (_VDAC_OPA_APORTCONFLICT_APORT4XCONFLICT_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_OPA_APORTCONFLICT */ #define VDAC_OPA_APORTCONFLICT_APORT4YCONFLICT (0x1UL << 9) /**< 1 If the Bus Connected to APORT4Y is in Conflict With Another Peripheral */ #define _VDAC_OPA_APORTCONFLICT_APORT4YCONFLICT_SHIFT 9 /**< Shift value for VDAC_OPAAPORT4YCONFLICT */ #define _VDAC_OPA_APORTCONFLICT_APORT4YCONFLICT_MASK 0x200UL /**< Bit mask for VDAC_OPAAPORT4YCONFLICT */ #define _VDAC_OPA_APORTCONFLICT_APORT4YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTCONFLICT */ #define VDAC_OPA_APORTCONFLICT_APORT4YCONFLICT_DEFAULT (_VDAC_OPA_APORTCONFLICT_APORT4YCONFLICT_DEFAULT << 9) /**< Shifted mode DEFAULT for VDAC_OPA_APORTCONFLICT */ /* Bit fields for VDAC OPA_CTRL */ #define _VDAC_OPA_CTRL_RESETVALUE 0x0000000EUL /**< Default value for VDAC_OPA_CTRL */ #define _VDAC_OPA_CTRL_MASK 0x00313F1FUL /**< Mask for VDAC_OPA_CTRL */ #define _VDAC_OPA_CTRL_DRIVESTRENGTH_SHIFT 0 /**< Shift value for VDAC_OPADRIVESTRENGTH */ #define _VDAC_OPA_CTRL_DRIVESTRENGTH_MASK 0x3UL /**< Bit mask for VDAC_OPADRIVESTRENGTH */ #define _VDAC_OPA_CTRL_DRIVESTRENGTH_DEFAULT 0x00000002UL /**< Mode DEFAULT for VDAC_OPA_CTRL */ #define VDAC_OPA_CTRL_DRIVESTRENGTH_DEFAULT (_VDAC_OPA_CTRL_DRIVESTRENGTH_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_OPA_CTRL */ #define VDAC_OPA_CTRL_INCBW (0x1UL << 2) /**< OPAx Unity Gain Bandwidth Scale */ #define _VDAC_OPA_CTRL_INCBW_SHIFT 2 /**< Shift value for VDAC_OPAINCBW */ #define _VDAC_OPA_CTRL_INCBW_MASK 0x4UL /**< Bit mask for VDAC_OPAINCBW */ #define _VDAC_OPA_CTRL_INCBW_DEFAULT 0x00000001UL /**< Mode DEFAULT for VDAC_OPA_CTRL */ #define VDAC_OPA_CTRL_INCBW_DEFAULT (_VDAC_OPA_CTRL_INCBW_DEFAULT << 2) /**< Shifted mode DEFAULT for VDAC_OPA_CTRL */ #define VDAC_OPA_CTRL_HCMDIS (0x1UL << 3) /**< High Common Mode Disable */ #define _VDAC_OPA_CTRL_HCMDIS_SHIFT 3 /**< Shift value for VDAC_OPAHCMDIS */ #define _VDAC_OPA_CTRL_HCMDIS_MASK 0x8UL /**< Bit mask for VDAC_OPAHCMDIS */ #define _VDAC_OPA_CTRL_HCMDIS_DEFAULT 0x00000001UL /**< Mode DEFAULT for VDAC_OPA_CTRL */ #define VDAC_OPA_CTRL_HCMDIS_DEFAULT (_VDAC_OPA_CTRL_HCMDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for VDAC_OPA_CTRL */ #define VDAC_OPA_CTRL_OUTSCALE (0x1UL << 4) /**< Scale OPAx Output Driving Strength */ #define _VDAC_OPA_CTRL_OUTSCALE_SHIFT 4 /**< Shift value for VDAC_OPAOUTSCALE */ #define _VDAC_OPA_CTRL_OUTSCALE_MASK 0x10UL /**< Bit mask for VDAC_OPAOUTSCALE */ #define _VDAC_OPA_CTRL_OUTSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_CTRL */ #define _VDAC_OPA_CTRL_OUTSCALE_FULL 0x00000000UL /**< Mode FULL for VDAC_OPA_CTRL */ #define _VDAC_OPA_CTRL_OUTSCALE_HALF 0x00000001UL /**< Mode HALF for VDAC_OPA_CTRL */ #define VDAC_OPA_CTRL_OUTSCALE_DEFAULT (_VDAC_OPA_CTRL_OUTSCALE_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_OPA_CTRL */ #define VDAC_OPA_CTRL_OUTSCALE_FULL (_VDAC_OPA_CTRL_OUTSCALE_FULL << 4) /**< Shifted mode FULL for VDAC_OPA_CTRL */ #define VDAC_OPA_CTRL_OUTSCALE_HALF (_VDAC_OPA_CTRL_OUTSCALE_HALF << 4) /**< Shifted mode HALF for VDAC_OPA_CTRL */ #define VDAC_OPA_CTRL_PRSEN (0x1UL << 8) /**< OPAx PRS Trigger Enable */ #define _VDAC_OPA_CTRL_PRSEN_SHIFT 8 /**< Shift value for VDAC_OPAPRSEN */ #define _VDAC_OPA_CTRL_PRSEN_MASK 0x100UL /**< Bit mask for VDAC_OPAPRSEN */ #define _VDAC_OPA_CTRL_PRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_CTRL */ #define VDAC_OPA_CTRL_PRSEN_DEFAULT (_VDAC_OPA_CTRL_PRSEN_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_OPA_CTRL */ #define VDAC_OPA_CTRL_PRSMODE (0x1UL << 9) /**< OPAx PRS Trigger Mode */ #define _VDAC_OPA_CTRL_PRSMODE_SHIFT 9 /**< Shift value for VDAC_OPAPRSMODE */ #define _VDAC_OPA_CTRL_PRSMODE_MASK 0x200UL /**< Bit mask for VDAC_OPAPRSMODE */ #define _VDAC_OPA_CTRL_PRSMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_CTRL */ #define _VDAC_OPA_CTRL_PRSMODE_PULSED 0x00000000UL /**< Mode PULSED for VDAC_OPA_CTRL */ #define _VDAC_OPA_CTRL_PRSMODE_TIMED 0x00000001UL /**< Mode TIMED for VDAC_OPA_CTRL */ #define VDAC_OPA_CTRL_PRSMODE_DEFAULT (_VDAC_OPA_CTRL_PRSMODE_DEFAULT << 9) /**< Shifted mode DEFAULT for VDAC_OPA_CTRL */ #define VDAC_OPA_CTRL_PRSMODE_PULSED (_VDAC_OPA_CTRL_PRSMODE_PULSED << 9) /**< Shifted mode PULSED for VDAC_OPA_CTRL */ #define VDAC_OPA_CTRL_PRSMODE_TIMED (_VDAC_OPA_CTRL_PRSMODE_TIMED << 9) /**< Shifted mode TIMED for VDAC_OPA_CTRL */ #define _VDAC_OPA_CTRL_PRSSEL_SHIFT 10 /**< Shift value for VDAC_OPAPRSSEL */ #define _VDAC_OPA_CTRL_PRSSEL_MASK 0x3C00UL /**< Bit mask for VDAC_OPAPRSSEL */ #define _VDAC_OPA_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_CTRL */ #define _VDAC_OPA_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for VDAC_OPA_CTRL */ #define _VDAC_OPA_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for VDAC_OPA_CTRL */ #define _VDAC_OPA_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for VDAC_OPA_CTRL */ #define _VDAC_OPA_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for VDAC_OPA_CTRL */ #define _VDAC_OPA_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for VDAC_OPA_CTRL */ #define _VDAC_OPA_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for VDAC_OPA_CTRL */ #define _VDAC_OPA_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for VDAC_OPA_CTRL */ #define _VDAC_OPA_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for VDAC_OPA_CTRL */ #define _VDAC_OPA_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for VDAC_OPA_CTRL */ #define _VDAC_OPA_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for VDAC_OPA_CTRL */ #define _VDAC_OPA_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for VDAC_OPA_CTRL */ #define _VDAC_OPA_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for VDAC_OPA_CTRL */ #define VDAC_OPA_CTRL_PRSSEL_DEFAULT (_VDAC_OPA_CTRL_PRSSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for VDAC_OPA_CTRL */ #define VDAC_OPA_CTRL_PRSSEL_PRSCH0 (_VDAC_OPA_CTRL_PRSSEL_PRSCH0 << 10) /**< Shifted mode PRSCH0 for VDAC_OPA_CTRL */ #define VDAC_OPA_CTRL_PRSSEL_PRSCH1 (_VDAC_OPA_CTRL_PRSSEL_PRSCH1 << 10) /**< Shifted mode PRSCH1 for VDAC_OPA_CTRL */ #define VDAC_OPA_CTRL_PRSSEL_PRSCH2 (_VDAC_OPA_CTRL_PRSSEL_PRSCH2 << 10) /**< Shifted mode PRSCH2 for VDAC_OPA_CTRL */ #define VDAC_OPA_CTRL_PRSSEL_PRSCH3 (_VDAC_OPA_CTRL_PRSSEL_PRSCH3 << 10) /**< Shifted mode PRSCH3 for VDAC_OPA_CTRL */ #define VDAC_OPA_CTRL_PRSSEL_PRSCH4 (_VDAC_OPA_CTRL_PRSSEL_PRSCH4 << 10) /**< Shifted mode PRSCH4 for VDAC_OPA_CTRL */ #define VDAC_OPA_CTRL_PRSSEL_PRSCH5 (_VDAC_OPA_CTRL_PRSSEL_PRSCH5 << 10) /**< Shifted mode PRSCH5 for VDAC_OPA_CTRL */ #define VDAC_OPA_CTRL_PRSSEL_PRSCH6 (_VDAC_OPA_CTRL_PRSSEL_PRSCH6 << 10) /**< Shifted mode PRSCH6 for VDAC_OPA_CTRL */ #define VDAC_OPA_CTRL_PRSSEL_PRSCH7 (_VDAC_OPA_CTRL_PRSSEL_PRSCH7 << 10) /**< Shifted mode PRSCH7 for VDAC_OPA_CTRL */ #define VDAC_OPA_CTRL_PRSSEL_PRSCH8 (_VDAC_OPA_CTRL_PRSSEL_PRSCH8 << 10) /**< Shifted mode PRSCH8 for VDAC_OPA_CTRL */ #define VDAC_OPA_CTRL_PRSSEL_PRSCH9 (_VDAC_OPA_CTRL_PRSSEL_PRSCH9 << 10) /**< Shifted mode PRSCH9 for VDAC_OPA_CTRL */ #define VDAC_OPA_CTRL_PRSSEL_PRSCH10 (_VDAC_OPA_CTRL_PRSSEL_PRSCH10 << 10) /**< Shifted mode PRSCH10 for VDAC_OPA_CTRL */ #define VDAC_OPA_CTRL_PRSSEL_PRSCH11 (_VDAC_OPA_CTRL_PRSSEL_PRSCH11 << 10) /**< Shifted mode PRSCH11 for VDAC_OPA_CTRL */ #define VDAC_OPA_CTRL_PRSOUTMODE (0x1UL << 16) /**< OPAx PRS Output Select */ #define _VDAC_OPA_CTRL_PRSOUTMODE_SHIFT 16 /**< Shift value for VDAC_OPAPRSOUTMODE */ #define _VDAC_OPA_CTRL_PRSOUTMODE_MASK 0x10000UL /**< Bit mask for VDAC_OPAPRSOUTMODE */ #define _VDAC_OPA_CTRL_PRSOUTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_CTRL */ #define _VDAC_OPA_CTRL_PRSOUTMODE_WARM 0x00000000UL /**< Mode WARM for VDAC_OPA_CTRL */ #define _VDAC_OPA_CTRL_PRSOUTMODE_OUTVALID 0x00000001UL /**< Mode OUTVALID for VDAC_OPA_CTRL */ #define VDAC_OPA_CTRL_PRSOUTMODE_DEFAULT (_VDAC_OPA_CTRL_PRSOUTMODE_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_OPA_CTRL */ #define VDAC_OPA_CTRL_PRSOUTMODE_WARM (_VDAC_OPA_CTRL_PRSOUTMODE_WARM << 16) /**< Shifted mode WARM for VDAC_OPA_CTRL */ #define VDAC_OPA_CTRL_PRSOUTMODE_OUTVALID (_VDAC_OPA_CTRL_PRSOUTMODE_OUTVALID << 16) /**< Shifted mode OUTVALID for VDAC_OPA_CTRL */ #define VDAC_OPA_CTRL_APORTXMASTERDIS (0x1UL << 20) /**< APORT Bus Master Disable */ #define _VDAC_OPA_CTRL_APORTXMASTERDIS_SHIFT 20 /**< Shift value for VDAC_OPAAPORTXMASTERDIS */ #define _VDAC_OPA_CTRL_APORTXMASTERDIS_MASK 0x100000UL /**< Bit mask for VDAC_OPAAPORTXMASTERDIS */ #define _VDAC_OPA_CTRL_APORTXMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_CTRL */ #define VDAC_OPA_CTRL_APORTXMASTERDIS_DEFAULT (_VDAC_OPA_CTRL_APORTXMASTERDIS_DEFAULT << 20) /**< Shifted mode DEFAULT for VDAC_OPA_CTRL */ #define VDAC_OPA_CTRL_APORTYMASTERDIS (0x1UL << 21) /**< APORT Bus Master Disable */ #define _VDAC_OPA_CTRL_APORTYMASTERDIS_SHIFT 21 /**< Shift value for VDAC_OPAAPORTYMASTERDIS */ #define _VDAC_OPA_CTRL_APORTYMASTERDIS_MASK 0x200000UL /**< Bit mask for VDAC_OPAAPORTYMASTERDIS */ #define _VDAC_OPA_CTRL_APORTYMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_CTRL */ #define VDAC_OPA_CTRL_APORTYMASTERDIS_DEFAULT (_VDAC_OPA_CTRL_APORTYMASTERDIS_DEFAULT << 21) /**< Shifted mode DEFAULT for VDAC_OPA_CTRL */ /* Bit fields for VDAC OPA_TIMER */ #define _VDAC_OPA_TIMER_RESETVALUE 0x00010700UL /**< Default value for VDAC_OPA_TIMER */ #define _VDAC_OPA_TIMER_MASK 0x03FF7F3FUL /**< Mask for VDAC_OPA_TIMER */ #define _VDAC_OPA_TIMER_STARTUPDLY_SHIFT 0 /**< Shift value for VDAC_OPASTARTUPDLY */ #define _VDAC_OPA_TIMER_STARTUPDLY_MASK 0x3FUL /**< Bit mask for VDAC_OPASTARTUPDLY */ #define _VDAC_OPA_TIMER_STARTUPDLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_TIMER */ #define VDAC_OPA_TIMER_STARTUPDLY_DEFAULT (_VDAC_OPA_TIMER_STARTUPDLY_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_OPA_TIMER */ #define _VDAC_OPA_TIMER_WARMUPTIME_SHIFT 8 /**< Shift value for VDAC_OPAWARMUPTIME */ #define _VDAC_OPA_TIMER_WARMUPTIME_MASK 0x7F00UL /**< Bit mask for VDAC_OPAWARMUPTIME */ #define _VDAC_OPA_TIMER_WARMUPTIME_DEFAULT 0x00000007UL /**< Mode DEFAULT for VDAC_OPA_TIMER */ #define VDAC_OPA_TIMER_WARMUPTIME_DEFAULT (_VDAC_OPA_TIMER_WARMUPTIME_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_OPA_TIMER */ #define _VDAC_OPA_TIMER_SETTLETIME_SHIFT 16 /**< Shift value for VDAC_OPASETTLETIME */ #define _VDAC_OPA_TIMER_SETTLETIME_MASK 0x3FF0000UL /**< Bit mask for VDAC_OPASETTLETIME */ #define _VDAC_OPA_TIMER_SETTLETIME_DEFAULT 0x00000001UL /**< Mode DEFAULT for VDAC_OPA_TIMER */ #define VDAC_OPA_TIMER_SETTLETIME_DEFAULT (_VDAC_OPA_TIMER_SETTLETIME_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_OPA_TIMER */ /* Bit fields for VDAC OPA_MUX */ #define _VDAC_OPA_MUX_RESETVALUE 0x0016F2F1UL /**< Default value for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_MASK 0x0717FFFFUL /**< Mask for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_POSSEL_SHIFT 0 /**< Shift value for VDAC_OPAPOSSEL */ #define _VDAC_OPA_MUX_POSSEL_MASK 0xFFUL /**< Bit mask for VDAC_OPAPOSSEL */ #define _VDAC_OPA_MUX_POSSEL_APORT1XCH0 0x00000020UL /**< Mode APORT1XCH0 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_POSSEL_APORT1XCH2 0x00000021UL /**< Mode APORT1XCH2 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_POSSEL_APORT1XCH4 0x00000022UL /**< Mode APORT1XCH4 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_POSSEL_APORT1XCH6 0x00000023UL /**< Mode APORT1XCH6 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_POSSEL_APORT1XCH8 0x00000024UL /**< Mode APORT1XCH8 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_POSSEL_APORT1XCH10 0x00000025UL /**< Mode APORT1XCH10 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_POSSEL_APORT1XCH12 0x00000026UL /**< Mode APORT1XCH12 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_POSSEL_APORT1XCH14 0x00000027UL /**< Mode APORT1XCH14 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_POSSEL_APORT1XCH16 0x00000028UL /**< Mode APORT1XCH16 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_POSSEL_APORT1XCH18 0x00000029UL /**< Mode APORT1XCH18 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_POSSEL_APORT1XCH20 0x0000002AUL /**< Mode APORT1XCH20 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_POSSEL_APORT1XCH22 0x0000002BUL /**< Mode APORT1XCH22 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_POSSEL_APORT1XCH24 0x0000002CUL /**< Mode APORT1XCH24 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_POSSEL_APORT1XCH26 0x0000002DUL /**< Mode APORT1XCH26 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_POSSEL_APORT1XCH28 0x0000002EUL /**< Mode APORT1XCH28 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_POSSEL_APORT1XCH30 0x0000002FUL /**< Mode APORT1XCH30 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_POSSEL_APORT2XCH1 0x00000040UL /**< Mode APORT2XCH1 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_POSSEL_APORT2XCH3 0x00000041UL /**< Mode APORT2XCH3 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_POSSEL_APORT2XCH5 0x00000042UL /**< Mode APORT2XCH5 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_POSSEL_APORT2XCH7 0x00000043UL /**< Mode APORT2XCH7 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_POSSEL_APORT2XCH9 0x00000044UL /**< Mode APORT2XCH9 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_POSSEL_APORT2XCH11 0x00000045UL /**< Mode APORT2XCH11 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_POSSEL_APORT2XCH13 0x00000046UL /**< Mode APORT2XCH13 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_POSSEL_APORT2XCH15 0x00000047UL /**< Mode APORT2XCH15 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_POSSEL_APORT2XCH17 0x00000048UL /**< Mode APORT2XCH17 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_POSSEL_APORT2XCH19 0x00000049UL /**< Mode APORT2XCH19 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_POSSEL_APORT2XCH21 0x0000004AUL /**< Mode APORT2XCH21 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_POSSEL_APORT2XCH23 0x0000004BUL /**< Mode APORT2XCH23 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_POSSEL_APORT2XCH25 0x0000004CUL /**< Mode APORT2XCH25 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_POSSEL_APORT2XCH27 0x0000004DUL /**< Mode APORT2XCH27 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_POSSEL_APORT2XCH29 0x0000004EUL /**< Mode APORT2XCH29 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_POSSEL_APORT2XCH31 0x0000004FUL /**< Mode APORT2XCH31 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_POSSEL_APORT3XCH0 0x00000060UL /**< Mode APORT3XCH0 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_POSSEL_APORT3XCH2 0x00000061UL /**< Mode APORT3XCH2 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_POSSEL_APORT3XCH4 0x00000062UL /**< Mode APORT3XCH4 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_POSSEL_APORT3XCH6 0x00000063UL /**< Mode APORT3XCH6 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_POSSEL_APORT3XCH8 0x00000064UL /**< Mode APORT3XCH8 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_POSSEL_APORT3XCH10 0x00000065UL /**< Mode APORT3XCH10 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_POSSEL_APORT3XCH12 0x00000066UL /**< Mode APORT3XCH12 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_POSSEL_APORT3XCH14 0x00000067UL /**< Mode APORT3XCH14 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_POSSEL_APORT3XCH16 0x00000068UL /**< Mode APORT3XCH16 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_POSSEL_APORT3XCH18 0x00000069UL /**< Mode APORT3XCH18 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_POSSEL_APORT3XCH20 0x0000006AUL /**< Mode APORT3XCH20 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_POSSEL_APORT3XCH22 0x0000006BUL /**< Mode APORT3XCH22 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_POSSEL_APORT3XCH24 0x0000006CUL /**< Mode APORT3XCH24 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_POSSEL_APORT3XCH26 0x0000006DUL /**< Mode APORT3XCH26 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_POSSEL_APORT3XCH28 0x0000006EUL /**< Mode APORT3XCH28 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_POSSEL_APORT3XCH30 0x0000006FUL /**< Mode APORT3XCH30 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_POSSEL_APORT4XCH1 0x00000080UL /**< Mode APORT4XCH1 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_POSSEL_APORT4XCH3 0x00000081UL /**< Mode APORT4XCH3 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_POSSEL_APORT4XCH5 0x00000082UL /**< Mode APORT4XCH5 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_POSSEL_APORT4XCH7 0x00000083UL /**< Mode APORT4XCH7 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_POSSEL_APORT4XCH9 0x00000084UL /**< Mode APORT4XCH9 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_POSSEL_APORT4XCH11 0x00000085UL /**< Mode APORT4XCH11 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_POSSEL_APORT4XCH13 0x00000086UL /**< Mode APORT4XCH13 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_POSSEL_APORT4XCH15 0x00000087UL /**< Mode APORT4XCH15 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_POSSEL_APORT4XCH17 0x00000088UL /**< Mode APORT4XCH17 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_POSSEL_APORT4XCH19 0x00000089UL /**< Mode APORT4XCH19 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_POSSEL_APORT4XCH21 0x0000008AUL /**< Mode APORT4XCH21 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_POSSEL_APORT4XCH23 0x0000008BUL /**< Mode APORT4XCH23 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_POSSEL_APORT4XCH25 0x0000008CUL /**< Mode APORT4XCH25 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_POSSEL_APORT4XCH27 0x0000008DUL /**< Mode APORT4XCH27 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_POSSEL_APORT4XCH29 0x0000008EUL /**< Mode APORT4XCH29 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_POSSEL_APORT4XCH31 0x0000008FUL /**< Mode APORT4XCH31 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_POSSEL_DISABLE 0x000000F0UL /**< Mode DISABLE for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_POSSEL_DEFAULT 0x000000F1UL /**< Mode DEFAULT for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_POSSEL_DAC 0x000000F1UL /**< Mode DAC for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_POSSEL_POSPAD 0x000000F2UL /**< Mode POSPAD for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_POSSEL_OPANEXT 0x000000F3UL /**< Mode OPANEXT for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_POSSEL_OPATAP 0x000000F4UL /**< Mode OPATAP for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_POSSEL_APORT1XCH0 (_VDAC_OPA_MUX_POSSEL_APORT1XCH0 << 0) /**< Shifted mode APORT1XCH0 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_POSSEL_APORT1XCH2 (_VDAC_OPA_MUX_POSSEL_APORT1XCH2 << 0) /**< Shifted mode APORT1XCH2 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_POSSEL_APORT1XCH4 (_VDAC_OPA_MUX_POSSEL_APORT1XCH4 << 0) /**< Shifted mode APORT1XCH4 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_POSSEL_APORT1XCH6 (_VDAC_OPA_MUX_POSSEL_APORT1XCH6 << 0) /**< Shifted mode APORT1XCH6 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_POSSEL_APORT1XCH8 (_VDAC_OPA_MUX_POSSEL_APORT1XCH8 << 0) /**< Shifted mode APORT1XCH8 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_POSSEL_APORT1XCH10 (_VDAC_OPA_MUX_POSSEL_APORT1XCH10 << 0) /**< Shifted mode APORT1XCH10 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_POSSEL_APORT1XCH12 (_VDAC_OPA_MUX_POSSEL_APORT1XCH12 << 0) /**< Shifted mode APORT1XCH12 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_POSSEL_APORT1XCH14 (_VDAC_OPA_MUX_POSSEL_APORT1XCH14 << 0) /**< Shifted mode APORT1XCH14 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_POSSEL_APORT1XCH16 (_VDAC_OPA_MUX_POSSEL_APORT1XCH16 << 0) /**< Shifted mode APORT1XCH16 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_POSSEL_APORT1XCH18 (_VDAC_OPA_MUX_POSSEL_APORT1XCH18 << 0) /**< Shifted mode APORT1XCH18 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_POSSEL_APORT1XCH20 (_VDAC_OPA_MUX_POSSEL_APORT1XCH20 << 0) /**< Shifted mode APORT1XCH20 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_POSSEL_APORT1XCH22 (_VDAC_OPA_MUX_POSSEL_APORT1XCH22 << 0) /**< Shifted mode APORT1XCH22 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_POSSEL_APORT1XCH24 (_VDAC_OPA_MUX_POSSEL_APORT1XCH24 << 0) /**< Shifted mode APORT1XCH24 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_POSSEL_APORT1XCH26 (_VDAC_OPA_MUX_POSSEL_APORT1XCH26 << 0) /**< Shifted mode APORT1XCH26 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_POSSEL_APORT1XCH28 (_VDAC_OPA_MUX_POSSEL_APORT1XCH28 << 0) /**< Shifted mode APORT1XCH28 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_POSSEL_APORT1XCH30 (_VDAC_OPA_MUX_POSSEL_APORT1XCH30 << 0) /**< Shifted mode APORT1XCH30 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_POSSEL_APORT2XCH1 (_VDAC_OPA_MUX_POSSEL_APORT2XCH1 << 0) /**< Shifted mode APORT2XCH1 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_POSSEL_APORT2XCH3 (_VDAC_OPA_MUX_POSSEL_APORT2XCH3 << 0) /**< Shifted mode APORT2XCH3 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_POSSEL_APORT2XCH5 (_VDAC_OPA_MUX_POSSEL_APORT2XCH5 << 0) /**< Shifted mode APORT2XCH5 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_POSSEL_APORT2XCH7 (_VDAC_OPA_MUX_POSSEL_APORT2XCH7 << 0) /**< Shifted mode APORT2XCH7 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_POSSEL_APORT2XCH9 (_VDAC_OPA_MUX_POSSEL_APORT2XCH9 << 0) /**< Shifted mode APORT2XCH9 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_POSSEL_APORT2XCH11 (_VDAC_OPA_MUX_POSSEL_APORT2XCH11 << 0) /**< Shifted mode APORT2XCH11 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_POSSEL_APORT2XCH13 (_VDAC_OPA_MUX_POSSEL_APORT2XCH13 << 0) /**< Shifted mode APORT2XCH13 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_POSSEL_APORT2XCH15 (_VDAC_OPA_MUX_POSSEL_APORT2XCH15 << 0) /**< Shifted mode APORT2XCH15 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_POSSEL_APORT2XCH17 (_VDAC_OPA_MUX_POSSEL_APORT2XCH17 << 0) /**< Shifted mode APORT2XCH17 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_POSSEL_APORT2XCH19 (_VDAC_OPA_MUX_POSSEL_APORT2XCH19 << 0) /**< Shifted mode APORT2XCH19 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_POSSEL_APORT2XCH21 (_VDAC_OPA_MUX_POSSEL_APORT2XCH21 << 0) /**< Shifted mode APORT2XCH21 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_POSSEL_APORT2XCH23 (_VDAC_OPA_MUX_POSSEL_APORT2XCH23 << 0) /**< Shifted mode APORT2XCH23 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_POSSEL_APORT2XCH25 (_VDAC_OPA_MUX_POSSEL_APORT2XCH25 << 0) /**< Shifted mode APORT2XCH25 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_POSSEL_APORT2XCH27 (_VDAC_OPA_MUX_POSSEL_APORT2XCH27 << 0) /**< Shifted mode APORT2XCH27 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_POSSEL_APORT2XCH29 (_VDAC_OPA_MUX_POSSEL_APORT2XCH29 << 0) /**< Shifted mode APORT2XCH29 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_POSSEL_APORT2XCH31 (_VDAC_OPA_MUX_POSSEL_APORT2XCH31 << 0) /**< Shifted mode APORT2XCH31 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_POSSEL_APORT3XCH0 (_VDAC_OPA_MUX_POSSEL_APORT3XCH0 << 0) /**< Shifted mode APORT3XCH0 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_POSSEL_APORT3XCH2 (_VDAC_OPA_MUX_POSSEL_APORT3XCH2 << 0) /**< Shifted mode APORT3XCH2 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_POSSEL_APORT3XCH4 (_VDAC_OPA_MUX_POSSEL_APORT3XCH4 << 0) /**< Shifted mode APORT3XCH4 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_POSSEL_APORT3XCH6 (_VDAC_OPA_MUX_POSSEL_APORT3XCH6 << 0) /**< Shifted mode APORT3XCH6 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_POSSEL_APORT3XCH8 (_VDAC_OPA_MUX_POSSEL_APORT3XCH8 << 0) /**< Shifted mode APORT3XCH8 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_POSSEL_APORT3XCH10 (_VDAC_OPA_MUX_POSSEL_APORT3XCH10 << 0) /**< Shifted mode APORT3XCH10 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_POSSEL_APORT3XCH12 (_VDAC_OPA_MUX_POSSEL_APORT3XCH12 << 0) /**< Shifted mode APORT3XCH12 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_POSSEL_APORT3XCH14 (_VDAC_OPA_MUX_POSSEL_APORT3XCH14 << 0) /**< Shifted mode APORT3XCH14 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_POSSEL_APORT3XCH16 (_VDAC_OPA_MUX_POSSEL_APORT3XCH16 << 0) /**< Shifted mode APORT3XCH16 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_POSSEL_APORT3XCH18 (_VDAC_OPA_MUX_POSSEL_APORT3XCH18 << 0) /**< Shifted mode APORT3XCH18 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_POSSEL_APORT3XCH20 (_VDAC_OPA_MUX_POSSEL_APORT3XCH20 << 0) /**< Shifted mode APORT3XCH20 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_POSSEL_APORT3XCH22 (_VDAC_OPA_MUX_POSSEL_APORT3XCH22 << 0) /**< Shifted mode APORT3XCH22 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_POSSEL_APORT3XCH24 (_VDAC_OPA_MUX_POSSEL_APORT3XCH24 << 0) /**< Shifted mode APORT3XCH24 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_POSSEL_APORT3XCH26 (_VDAC_OPA_MUX_POSSEL_APORT3XCH26 << 0) /**< Shifted mode APORT3XCH26 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_POSSEL_APORT3XCH28 (_VDAC_OPA_MUX_POSSEL_APORT3XCH28 << 0) /**< Shifted mode APORT3XCH28 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_POSSEL_APORT3XCH30 (_VDAC_OPA_MUX_POSSEL_APORT3XCH30 << 0) /**< Shifted mode APORT3XCH30 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_POSSEL_APORT4XCH1 (_VDAC_OPA_MUX_POSSEL_APORT4XCH1 << 0) /**< Shifted mode APORT4XCH1 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_POSSEL_APORT4XCH3 (_VDAC_OPA_MUX_POSSEL_APORT4XCH3 << 0) /**< Shifted mode APORT4XCH3 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_POSSEL_APORT4XCH5 (_VDAC_OPA_MUX_POSSEL_APORT4XCH5 << 0) /**< Shifted mode APORT4XCH5 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_POSSEL_APORT4XCH7 (_VDAC_OPA_MUX_POSSEL_APORT4XCH7 << 0) /**< Shifted mode APORT4XCH7 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_POSSEL_APORT4XCH9 (_VDAC_OPA_MUX_POSSEL_APORT4XCH9 << 0) /**< Shifted mode APORT4XCH9 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_POSSEL_APORT4XCH11 (_VDAC_OPA_MUX_POSSEL_APORT4XCH11 << 0) /**< Shifted mode APORT4XCH11 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_POSSEL_APORT4XCH13 (_VDAC_OPA_MUX_POSSEL_APORT4XCH13 << 0) /**< Shifted mode APORT4XCH13 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_POSSEL_APORT4XCH15 (_VDAC_OPA_MUX_POSSEL_APORT4XCH15 << 0) /**< Shifted mode APORT4XCH15 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_POSSEL_APORT4XCH17 (_VDAC_OPA_MUX_POSSEL_APORT4XCH17 << 0) /**< Shifted mode APORT4XCH17 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_POSSEL_APORT4XCH19 (_VDAC_OPA_MUX_POSSEL_APORT4XCH19 << 0) /**< Shifted mode APORT4XCH19 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_POSSEL_APORT4XCH21 (_VDAC_OPA_MUX_POSSEL_APORT4XCH21 << 0) /**< Shifted mode APORT4XCH21 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_POSSEL_APORT4XCH23 (_VDAC_OPA_MUX_POSSEL_APORT4XCH23 << 0) /**< Shifted mode APORT4XCH23 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_POSSEL_APORT4XCH25 (_VDAC_OPA_MUX_POSSEL_APORT4XCH25 << 0) /**< Shifted mode APORT4XCH25 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_POSSEL_APORT4XCH27 (_VDAC_OPA_MUX_POSSEL_APORT4XCH27 << 0) /**< Shifted mode APORT4XCH27 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_POSSEL_APORT4XCH29 (_VDAC_OPA_MUX_POSSEL_APORT4XCH29 << 0) /**< Shifted mode APORT4XCH29 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_POSSEL_APORT4XCH31 (_VDAC_OPA_MUX_POSSEL_APORT4XCH31 << 0) /**< Shifted mode APORT4XCH31 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_POSSEL_DISABLE (_VDAC_OPA_MUX_POSSEL_DISABLE << 0) /**< Shifted mode DISABLE for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_POSSEL_DEFAULT (_VDAC_OPA_MUX_POSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_POSSEL_DAC (_VDAC_OPA_MUX_POSSEL_DAC << 0) /**< Shifted mode DAC for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_POSSEL_POSPAD (_VDAC_OPA_MUX_POSSEL_POSPAD << 0) /**< Shifted mode POSPAD for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_POSSEL_OPANEXT (_VDAC_OPA_MUX_POSSEL_OPANEXT << 0) /**< Shifted mode OPANEXT for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_POSSEL_OPATAP (_VDAC_OPA_MUX_POSSEL_OPATAP << 0) /**< Shifted mode OPATAP for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_NEGSEL_SHIFT 8 /**< Shift value for VDAC_OPANEGSEL */ #define _VDAC_OPA_MUX_NEGSEL_MASK 0xFF00UL /**< Bit mask for VDAC_OPANEGSEL */ #define _VDAC_OPA_MUX_NEGSEL_APORT1YCH1 0x00000030UL /**< Mode APORT1YCH1 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_NEGSEL_APORT1YCH3 0x00000031UL /**< Mode APORT1YCH3 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_NEGSEL_APORT1YCH5 0x00000032UL /**< Mode APORT1YCH5 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_NEGSEL_APORT1YCH7 0x00000033UL /**< Mode APORT1YCH7 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_NEGSEL_APORT1YCH9 0x00000034UL /**< Mode APORT1YCH9 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_NEGSEL_APORT1YCH11 0x00000035UL /**< Mode APORT1YCH11 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_NEGSEL_APORT1YCH13 0x00000036UL /**< Mode APORT1YCH13 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_NEGSEL_APORT1YCH15 0x00000037UL /**< Mode APORT1YCH15 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_NEGSEL_APORT1YCH17 0x00000038UL /**< Mode APORT1YCH17 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_NEGSEL_APORT1YCH19 0x00000039UL /**< Mode APORT1YCH19 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_NEGSEL_APORT1YCH21 0x0000003AUL /**< Mode APORT1YCH21 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_NEGSEL_APORT1YCH23 0x0000003BUL /**< Mode APORT1YCH23 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_NEGSEL_APORT1YCH25 0x0000003CUL /**< Mode APORT1YCH25 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_NEGSEL_APORT1YCH27 0x0000003DUL /**< Mode APORT1YCH27 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_NEGSEL_APORT1YCH29 0x0000003EUL /**< Mode APORT1YCH29 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_NEGSEL_APORT1YCH31 0x0000003FUL /**< Mode APORT1YCH31 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_NEGSEL_APORT2YCH0 0x00000050UL /**< Mode APORT2YCH0 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_NEGSEL_APORT2YCH2 0x00000051UL /**< Mode APORT2YCH2 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_NEGSEL_APORT2YCH4 0x00000052UL /**< Mode APORT2YCH4 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_NEGSEL_APORT2YCH6 0x00000053UL /**< Mode APORT2YCH6 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_NEGSEL_APORT2YCH8 0x00000054UL /**< Mode APORT2YCH8 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_NEGSEL_APORT2YCH10 0x00000055UL /**< Mode APORT2YCH10 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_NEGSEL_APORT2YCH12 0x00000056UL /**< Mode APORT2YCH12 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_NEGSEL_APORT2YCH14 0x00000057UL /**< Mode APORT2YCH14 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_NEGSEL_APORT2YCH16 0x00000058UL /**< Mode APORT2YCH16 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_NEGSEL_APORT2YCH18 0x00000059UL /**< Mode APORT2YCH18 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_NEGSEL_APORT2YCH20 0x0000005AUL /**< Mode APORT2YCH20 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_NEGSEL_APORT2YCH22 0x0000005BUL /**< Mode APORT2YCH22 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_NEGSEL_APORT2YCH24 0x0000005CUL /**< Mode APORT2YCH24 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_NEGSEL_APORT2YCH26 0x0000005DUL /**< Mode APORT2YCH26 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_NEGSEL_APORT2YCH28 0x0000005EUL /**< Mode APORT2YCH28 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_NEGSEL_APORT2YCH30 0x0000005FUL /**< Mode APORT2YCH30 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_NEGSEL_APORT3YCH1 0x00000070UL /**< Mode APORT3YCH1 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_NEGSEL_APORT3YCH3 0x00000071UL /**< Mode APORT3YCH3 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_NEGSEL_APORT3YCH5 0x00000072UL /**< Mode APORT3YCH5 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_NEGSEL_APORT3YCH7 0x00000073UL /**< Mode APORT3YCH7 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_NEGSEL_APORT3YCH9 0x00000074UL /**< Mode APORT3YCH9 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_NEGSEL_APORT3YCH11 0x00000075UL /**< Mode APORT3YCH11 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_NEGSEL_APORT3YCH13 0x00000076UL /**< Mode APORT3YCH13 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_NEGSEL_APORT3YCH15 0x00000077UL /**< Mode APORT3YCH15 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_NEGSEL_APORT3YCH17 0x00000078UL /**< Mode APORT3YCH17 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_NEGSEL_APORT3YCH19 0x00000079UL /**< Mode APORT3YCH19 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_NEGSEL_APORT3YCH21 0x0000007AUL /**< Mode APORT3YCH21 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_NEGSEL_APORT3YCH23 0x0000007BUL /**< Mode APORT3YCH23 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_NEGSEL_APORT3YCH25 0x0000007CUL /**< Mode APORT3YCH25 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_NEGSEL_APORT3YCH27 0x0000007DUL /**< Mode APORT3YCH27 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_NEGSEL_APORT3YCH29 0x0000007EUL /**< Mode APORT3YCH29 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_NEGSEL_APORT3YCH31 0x0000007FUL /**< Mode APORT3YCH31 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_NEGSEL_APORT4YCH0 0x00000090UL /**< Mode APORT4YCH0 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_NEGSEL_APORT4YCH2 0x00000091UL /**< Mode APORT4YCH2 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_NEGSEL_APORT4YCH4 0x00000092UL /**< Mode APORT4YCH4 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_NEGSEL_APORT4YCH6 0x00000093UL /**< Mode APORT4YCH6 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_NEGSEL_APORT4YCH8 0x00000094UL /**< Mode APORT4YCH8 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_NEGSEL_APORT4YCH10 0x00000095UL /**< Mode APORT4YCH10 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_NEGSEL_APORT4YCH12 0x00000096UL /**< Mode APORT4YCH12 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_NEGSEL_APORT4YCH14 0x00000097UL /**< Mode APORT4YCH14 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_NEGSEL_APORT4YCH16 0x00000098UL /**< Mode APORT4YCH16 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_NEGSEL_APORT4YCH18 0x00000099UL /**< Mode APORT4YCH18 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_NEGSEL_APORT4YCH20 0x0000009AUL /**< Mode APORT4YCH20 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_NEGSEL_APORT4YCH22 0x0000009BUL /**< Mode APORT4YCH22 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_NEGSEL_APORT4YCH24 0x0000009CUL /**< Mode APORT4YCH24 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_NEGSEL_APORT4YCH26 0x0000009DUL /**< Mode APORT4YCH26 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_NEGSEL_APORT4YCH28 0x0000009EUL /**< Mode APORT4YCH28 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_NEGSEL_APORT4YCH30 0x0000009FUL /**< Mode APORT4YCH30 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_NEGSEL_DISABLE 0x000000F0UL /**< Mode DISABLE for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_NEGSEL_UG 0x000000F1UL /**< Mode UG for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_NEGSEL_DEFAULT 0x000000F2UL /**< Mode DEFAULT for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_NEGSEL_OPATAP 0x000000F2UL /**< Mode OPATAP for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_NEGSEL_NEGPAD 0x000000F3UL /**< Mode NEGPAD for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_NEGSEL_APORT1YCH1 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH1 << 8) /**< Shifted mode APORT1YCH1 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_NEGSEL_APORT1YCH3 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH3 << 8) /**< Shifted mode APORT1YCH3 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_NEGSEL_APORT1YCH5 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH5 << 8) /**< Shifted mode APORT1YCH5 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_NEGSEL_APORT1YCH7 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH7 << 8) /**< Shifted mode APORT1YCH7 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_NEGSEL_APORT1YCH9 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH9 << 8) /**< Shifted mode APORT1YCH9 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_NEGSEL_APORT1YCH11 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH11 << 8) /**< Shifted mode APORT1YCH11 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_NEGSEL_APORT1YCH13 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH13 << 8) /**< Shifted mode APORT1YCH13 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_NEGSEL_APORT1YCH15 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH15 << 8) /**< Shifted mode APORT1YCH15 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_NEGSEL_APORT1YCH17 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH17 << 8) /**< Shifted mode APORT1YCH17 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_NEGSEL_APORT1YCH19 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH19 << 8) /**< Shifted mode APORT1YCH19 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_NEGSEL_APORT1YCH21 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH21 << 8) /**< Shifted mode APORT1YCH21 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_NEGSEL_APORT1YCH23 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH23 << 8) /**< Shifted mode APORT1YCH23 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_NEGSEL_APORT1YCH25 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH25 << 8) /**< Shifted mode APORT1YCH25 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_NEGSEL_APORT1YCH27 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH27 << 8) /**< Shifted mode APORT1YCH27 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_NEGSEL_APORT1YCH29 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH29 << 8) /**< Shifted mode APORT1YCH29 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_NEGSEL_APORT1YCH31 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH31 << 8) /**< Shifted mode APORT1YCH31 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_NEGSEL_APORT2YCH0 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH0 << 8) /**< Shifted mode APORT2YCH0 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_NEGSEL_APORT2YCH2 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH2 << 8) /**< Shifted mode APORT2YCH2 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_NEGSEL_APORT2YCH4 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH4 << 8) /**< Shifted mode APORT2YCH4 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_NEGSEL_APORT2YCH6 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH6 << 8) /**< Shifted mode APORT2YCH6 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_NEGSEL_APORT2YCH8 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH8 << 8) /**< Shifted mode APORT2YCH8 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_NEGSEL_APORT2YCH10 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH10 << 8) /**< Shifted mode APORT2YCH10 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_NEGSEL_APORT2YCH12 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH12 << 8) /**< Shifted mode APORT2YCH12 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_NEGSEL_APORT2YCH14 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH14 << 8) /**< Shifted mode APORT2YCH14 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_NEGSEL_APORT2YCH16 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH16 << 8) /**< Shifted mode APORT2YCH16 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_NEGSEL_APORT2YCH18 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH18 << 8) /**< Shifted mode APORT2YCH18 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_NEGSEL_APORT2YCH20 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH20 << 8) /**< Shifted mode APORT2YCH20 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_NEGSEL_APORT2YCH22 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH22 << 8) /**< Shifted mode APORT2YCH22 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_NEGSEL_APORT2YCH24 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH24 << 8) /**< Shifted mode APORT2YCH24 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_NEGSEL_APORT2YCH26 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH26 << 8) /**< Shifted mode APORT2YCH26 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_NEGSEL_APORT2YCH28 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH28 << 8) /**< Shifted mode APORT2YCH28 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_NEGSEL_APORT2YCH30 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH30 << 8) /**< Shifted mode APORT2YCH30 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_NEGSEL_APORT3YCH1 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH1 << 8) /**< Shifted mode APORT3YCH1 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_NEGSEL_APORT3YCH3 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH3 << 8) /**< Shifted mode APORT3YCH3 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_NEGSEL_APORT3YCH5 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH5 << 8) /**< Shifted mode APORT3YCH5 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_NEGSEL_APORT3YCH7 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH7 << 8) /**< Shifted mode APORT3YCH7 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_NEGSEL_APORT3YCH9 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH9 << 8) /**< Shifted mode APORT3YCH9 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_NEGSEL_APORT3YCH11 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH11 << 8) /**< Shifted mode APORT3YCH11 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_NEGSEL_APORT3YCH13 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH13 << 8) /**< Shifted mode APORT3YCH13 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_NEGSEL_APORT3YCH15 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH15 << 8) /**< Shifted mode APORT3YCH15 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_NEGSEL_APORT3YCH17 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH17 << 8) /**< Shifted mode APORT3YCH17 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_NEGSEL_APORT3YCH19 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH19 << 8) /**< Shifted mode APORT3YCH19 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_NEGSEL_APORT3YCH21 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH21 << 8) /**< Shifted mode APORT3YCH21 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_NEGSEL_APORT3YCH23 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH23 << 8) /**< Shifted mode APORT3YCH23 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_NEGSEL_APORT3YCH25 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH25 << 8) /**< Shifted mode APORT3YCH25 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_NEGSEL_APORT3YCH27 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH27 << 8) /**< Shifted mode APORT3YCH27 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_NEGSEL_APORT3YCH29 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH29 << 8) /**< Shifted mode APORT3YCH29 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_NEGSEL_APORT3YCH31 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH31 << 8) /**< Shifted mode APORT3YCH31 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_NEGSEL_APORT4YCH0 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH0 << 8) /**< Shifted mode APORT4YCH0 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_NEGSEL_APORT4YCH2 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH2 << 8) /**< Shifted mode APORT4YCH2 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_NEGSEL_APORT4YCH4 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH4 << 8) /**< Shifted mode APORT4YCH4 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_NEGSEL_APORT4YCH6 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH6 << 8) /**< Shifted mode APORT4YCH6 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_NEGSEL_APORT4YCH8 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH8 << 8) /**< Shifted mode APORT4YCH8 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_NEGSEL_APORT4YCH10 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH10 << 8) /**< Shifted mode APORT4YCH10 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_NEGSEL_APORT4YCH12 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH12 << 8) /**< Shifted mode APORT4YCH12 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_NEGSEL_APORT4YCH14 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH14 << 8) /**< Shifted mode APORT4YCH14 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_NEGSEL_APORT4YCH16 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH16 << 8) /**< Shifted mode APORT4YCH16 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_NEGSEL_APORT4YCH18 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH18 << 8) /**< Shifted mode APORT4YCH18 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_NEGSEL_APORT4YCH20 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH20 << 8) /**< Shifted mode APORT4YCH20 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_NEGSEL_APORT4YCH22 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH22 << 8) /**< Shifted mode APORT4YCH22 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_NEGSEL_APORT4YCH24 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH24 << 8) /**< Shifted mode APORT4YCH24 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_NEGSEL_APORT4YCH26 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH26 << 8) /**< Shifted mode APORT4YCH26 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_NEGSEL_APORT4YCH28 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH28 << 8) /**< Shifted mode APORT4YCH28 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_NEGSEL_APORT4YCH30 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH30 << 8) /**< Shifted mode APORT4YCH30 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_NEGSEL_DISABLE (_VDAC_OPA_MUX_NEGSEL_DISABLE << 8) /**< Shifted mode DISABLE for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_NEGSEL_UG (_VDAC_OPA_MUX_NEGSEL_UG << 8) /**< Shifted mode UG for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_NEGSEL_DEFAULT (_VDAC_OPA_MUX_NEGSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_NEGSEL_OPATAP (_VDAC_OPA_MUX_NEGSEL_OPATAP << 8) /**< Shifted mode OPATAP for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_NEGSEL_NEGPAD (_VDAC_OPA_MUX_NEGSEL_NEGPAD << 8) /**< Shifted mode NEGPAD for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_RESINMUX_SHIFT 16 /**< Shift value for VDAC_OPARESINMUX */ #define _VDAC_OPA_MUX_RESINMUX_MASK 0x70000UL /**< Bit mask for VDAC_OPARESINMUX */ #define _VDAC_OPA_MUX_RESINMUX_DISABLE 0x00000000UL /**< Mode DISABLE for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_RESINMUX_OPANEXT 0x00000001UL /**< Mode OPANEXT for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_RESINMUX_NEGPAD 0x00000002UL /**< Mode NEGPAD for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_RESINMUX_POSPAD 0x00000003UL /**< Mode POSPAD for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_RESINMUX_COMPAD 0x00000004UL /**< Mode COMPAD for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_RESINMUX_CENTER 0x00000005UL /**< Mode CENTER for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_RESINMUX_DEFAULT 0x00000006UL /**< Mode DEFAULT for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_RESINMUX_VSS 0x00000006UL /**< Mode VSS for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_RESINMUX_DISABLE (_VDAC_OPA_MUX_RESINMUX_DISABLE << 16) /**< Shifted mode DISABLE for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_RESINMUX_OPANEXT (_VDAC_OPA_MUX_RESINMUX_OPANEXT << 16) /**< Shifted mode OPANEXT for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_RESINMUX_NEGPAD (_VDAC_OPA_MUX_RESINMUX_NEGPAD << 16) /**< Shifted mode NEGPAD for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_RESINMUX_POSPAD (_VDAC_OPA_MUX_RESINMUX_POSPAD << 16) /**< Shifted mode POSPAD for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_RESINMUX_COMPAD (_VDAC_OPA_MUX_RESINMUX_COMPAD << 16) /**< Shifted mode COMPAD for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_RESINMUX_CENTER (_VDAC_OPA_MUX_RESINMUX_CENTER << 16) /**< Shifted mode CENTER for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_RESINMUX_DEFAULT (_VDAC_OPA_MUX_RESINMUX_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_RESINMUX_VSS (_VDAC_OPA_MUX_RESINMUX_VSS << 16) /**< Shifted mode VSS for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_GAIN3X (0x1UL << 20) /**< OPAx Dedicated 3x Gain Resistor Ladder */ #define _VDAC_OPA_MUX_GAIN3X_SHIFT 20 /**< Shift value for VDAC_OPAGAIN3X */ #define _VDAC_OPA_MUX_GAIN3X_MASK 0x100000UL /**< Bit mask for VDAC_OPAGAIN3X */ #define _VDAC_OPA_MUX_GAIN3X_DEFAULT 0x00000001UL /**< Mode DEFAULT for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_GAIN3X_DEFAULT (_VDAC_OPA_MUX_GAIN3X_DEFAULT << 20) /**< Shifted mode DEFAULT for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_RESSEL_SHIFT 24 /**< Shift value for VDAC_OPARESSEL */ #define _VDAC_OPA_MUX_RESSEL_MASK 0x7000000UL /**< Bit mask for VDAC_OPARESSEL */ #define _VDAC_OPA_MUX_RESSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_RESSEL_RES0 0x00000000UL /**< Mode RES0 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_RESSEL_RES1 0x00000001UL /**< Mode RES1 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_RESSEL_RES2 0x00000002UL /**< Mode RES2 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_RESSEL_RES3 0x00000003UL /**< Mode RES3 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_RESSEL_RES4 0x00000004UL /**< Mode RES4 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_RESSEL_RES5 0x00000005UL /**< Mode RES5 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_RESSEL_RES6 0x00000006UL /**< Mode RES6 for VDAC_OPA_MUX */ #define _VDAC_OPA_MUX_RESSEL_RES7 0x00000007UL /**< Mode RES7 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_RESSEL_DEFAULT (_VDAC_OPA_MUX_RESSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_RESSEL_RES0 (_VDAC_OPA_MUX_RESSEL_RES0 << 24) /**< Shifted mode RES0 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_RESSEL_RES1 (_VDAC_OPA_MUX_RESSEL_RES1 << 24) /**< Shifted mode RES1 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_RESSEL_RES2 (_VDAC_OPA_MUX_RESSEL_RES2 << 24) /**< Shifted mode RES2 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_RESSEL_RES3 (_VDAC_OPA_MUX_RESSEL_RES3 << 24) /**< Shifted mode RES3 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_RESSEL_RES4 (_VDAC_OPA_MUX_RESSEL_RES4 << 24) /**< Shifted mode RES4 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_RESSEL_RES5 (_VDAC_OPA_MUX_RESSEL_RES5 << 24) /**< Shifted mode RES5 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_RESSEL_RES6 (_VDAC_OPA_MUX_RESSEL_RES6 << 24) /**< Shifted mode RES6 for VDAC_OPA_MUX */ #define VDAC_OPA_MUX_RESSEL_RES7 (_VDAC_OPA_MUX_RESSEL_RES7 << 24) /**< Shifted mode RES7 for VDAC_OPA_MUX */ /* Bit fields for VDAC OPA_OUT */ #define _VDAC_OPA_OUT_RESETVALUE 0x00000001UL /**< Default value for VDAC_OPA_OUT */ #define _VDAC_OPA_OUT_MASK 0x00FF01FFUL /**< Mask for VDAC_OPA_OUT */ #define VDAC_OPA_OUT_MAINOUTEN (0x1UL << 0) /**< OPAx Main Output Enable */ #define _VDAC_OPA_OUT_MAINOUTEN_SHIFT 0 /**< Shift value for VDAC_OPAMAINOUTEN */ #define _VDAC_OPA_OUT_MAINOUTEN_MASK 0x1UL /**< Bit mask for VDAC_OPAMAINOUTEN */ #define _VDAC_OPA_OUT_MAINOUTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for VDAC_OPA_OUT */ #define VDAC_OPA_OUT_MAINOUTEN_DEFAULT (_VDAC_OPA_OUT_MAINOUTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_OPA_OUT */ #define VDAC_OPA_OUT_ALTOUTEN (0x1UL << 1) /**< OPAx Alternative Output Enable */ #define _VDAC_OPA_OUT_ALTOUTEN_SHIFT 1 /**< Shift value for VDAC_OPAALTOUTEN */ #define _VDAC_OPA_OUT_ALTOUTEN_MASK 0x2UL /**< Bit mask for VDAC_OPAALTOUTEN */ #define _VDAC_OPA_OUT_ALTOUTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_OUT */ #define VDAC_OPA_OUT_ALTOUTEN_DEFAULT (_VDAC_OPA_OUT_ALTOUTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_OPA_OUT */ #define VDAC_OPA_OUT_APORTOUTEN (0x1UL << 2) /**< OPAx Aport Output Enable */ #define _VDAC_OPA_OUT_APORTOUTEN_SHIFT 2 /**< Shift value for VDAC_OPAAPORTOUTEN */ #define _VDAC_OPA_OUT_APORTOUTEN_MASK 0x4UL /**< Bit mask for VDAC_OPAAPORTOUTEN */ #define _VDAC_OPA_OUT_APORTOUTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_OUT */ #define VDAC_OPA_OUT_APORTOUTEN_DEFAULT (_VDAC_OPA_OUT_APORTOUTEN_DEFAULT << 2) /**< Shifted mode DEFAULT for VDAC_OPA_OUT */ #define VDAC_OPA_OUT_SHORT (0x1UL << 3) /**< OPAx Main and Alternative Output Short */ #define _VDAC_OPA_OUT_SHORT_SHIFT 3 /**< Shift value for VDAC_OPASHORT */ #define _VDAC_OPA_OUT_SHORT_MASK 0x8UL /**< Bit mask for VDAC_OPASHORT */ #define _VDAC_OPA_OUT_SHORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_OUT */ #define VDAC_OPA_OUT_SHORT_DEFAULT (_VDAC_OPA_OUT_SHORT_DEFAULT << 3) /**< Shifted mode DEFAULT for VDAC_OPA_OUT */ #define _VDAC_OPA_OUT_ALTOUTPADEN_SHIFT 4 /**< Shift value for VDAC_OPAALTOUTPADEN */ #define _VDAC_OPA_OUT_ALTOUTPADEN_MASK 0x1F0UL /**< Bit mask for VDAC_OPAALTOUTPADEN */ #define _VDAC_OPA_OUT_ALTOUTPADEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_OUT */ #define _VDAC_OPA_OUT_ALTOUTPADEN_OUT0 0x00000001UL /**< Mode OUT0 for VDAC_OPA_OUT */ #define _VDAC_OPA_OUT_ALTOUTPADEN_OUT1 0x00000002UL /**< Mode OUT1 for VDAC_OPA_OUT */ #define _VDAC_OPA_OUT_ALTOUTPADEN_OUT2 0x00000004UL /**< Mode OUT2 for VDAC_OPA_OUT */ #define _VDAC_OPA_OUT_ALTOUTPADEN_OUT3 0x00000008UL /**< Mode OUT3 for VDAC_OPA_OUT */ #define _VDAC_OPA_OUT_ALTOUTPADEN_OUT4 0x00000010UL /**< Mode OUT4 for VDAC_OPA_OUT */ #define VDAC_OPA_OUT_ALTOUTPADEN_DEFAULT (_VDAC_OPA_OUT_ALTOUTPADEN_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_OPA_OUT */ #define VDAC_OPA_OUT_ALTOUTPADEN_OUT0 (_VDAC_OPA_OUT_ALTOUTPADEN_OUT0 << 4) /**< Shifted mode OUT0 for VDAC_OPA_OUT */ #define VDAC_OPA_OUT_ALTOUTPADEN_OUT1 (_VDAC_OPA_OUT_ALTOUTPADEN_OUT1 << 4) /**< Shifted mode OUT1 for VDAC_OPA_OUT */ #define VDAC_OPA_OUT_ALTOUTPADEN_OUT2 (_VDAC_OPA_OUT_ALTOUTPADEN_OUT2 << 4) /**< Shifted mode OUT2 for VDAC_OPA_OUT */ #define VDAC_OPA_OUT_ALTOUTPADEN_OUT3 (_VDAC_OPA_OUT_ALTOUTPADEN_OUT3 << 4) /**< Shifted mode OUT3 for VDAC_OPA_OUT */ #define VDAC_OPA_OUT_ALTOUTPADEN_OUT4 (_VDAC_OPA_OUT_ALTOUTPADEN_OUT4 << 4) /**< Shifted mode OUT4 for VDAC_OPA_OUT */ #define _VDAC_OPA_OUT_APORTOUTSEL_SHIFT 16 /**< Shift value for VDAC_OPAAPORTOUTSEL */ #define _VDAC_OPA_OUT_APORTOUTSEL_MASK 0xFF0000UL /**< Bit mask for VDAC_OPAAPORTOUTSEL */ #define _VDAC_OPA_OUT_APORTOUTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_OUT */ #define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH1 0x00000030UL /**< Mode APORT1YCH1 for VDAC_OPA_OUT */ #define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH3 0x00000031UL /**< Mode APORT1YCH3 for VDAC_OPA_OUT */ #define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH5 0x00000032UL /**< Mode APORT1YCH5 for VDAC_OPA_OUT */ #define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH7 0x00000033UL /**< Mode APORT1YCH7 for VDAC_OPA_OUT */ #define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH9 0x00000034UL /**< Mode APORT1YCH9 for VDAC_OPA_OUT */ #define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH11 0x00000035UL /**< Mode APORT1YCH11 for VDAC_OPA_OUT */ #define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH13 0x00000036UL /**< Mode APORT1YCH13 for VDAC_OPA_OUT */ #define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH15 0x00000037UL /**< Mode APORT1YCH15 for VDAC_OPA_OUT */ #define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH17 0x00000038UL /**< Mode APORT1YCH17 for VDAC_OPA_OUT */ #define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH19 0x00000039UL /**< Mode APORT1YCH19 for VDAC_OPA_OUT */ #define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH21 0x0000003AUL /**< Mode APORT1YCH21 for VDAC_OPA_OUT */ #define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH23 0x0000003BUL /**< Mode APORT1YCH23 for VDAC_OPA_OUT */ #define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH25 0x0000003CUL /**< Mode APORT1YCH25 for VDAC_OPA_OUT */ #define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH27 0x0000003DUL /**< Mode APORT1YCH27 for VDAC_OPA_OUT */ #define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH29 0x0000003EUL /**< Mode APORT1YCH29 for VDAC_OPA_OUT */ #define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH31 0x0000003FUL /**< Mode APORT1YCH31 for VDAC_OPA_OUT */ #define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH0 0x00000050UL /**< Mode APORT2YCH0 for VDAC_OPA_OUT */ #define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH2 0x00000051UL /**< Mode APORT2YCH2 for VDAC_OPA_OUT */ #define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH4 0x00000052UL /**< Mode APORT2YCH4 for VDAC_OPA_OUT */ #define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH6 0x00000053UL /**< Mode APORT2YCH6 for VDAC_OPA_OUT */ #define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH8 0x00000054UL /**< Mode APORT2YCH8 for VDAC_OPA_OUT */ #define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH10 0x00000055UL /**< Mode APORT2YCH10 for VDAC_OPA_OUT */ #define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH12 0x00000056UL /**< Mode APORT2YCH12 for VDAC_OPA_OUT */ #define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH14 0x00000057UL /**< Mode APORT2YCH14 for VDAC_OPA_OUT */ #define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH16 0x00000058UL /**< Mode APORT2YCH16 for VDAC_OPA_OUT */ #define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH18 0x00000059UL /**< Mode APORT2YCH18 for VDAC_OPA_OUT */ #define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH20 0x0000005AUL /**< Mode APORT2YCH20 for VDAC_OPA_OUT */ #define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH22 0x0000005BUL /**< Mode APORT2YCH22 for VDAC_OPA_OUT */ #define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH24 0x0000005CUL /**< Mode APORT2YCH24 for VDAC_OPA_OUT */ #define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH26 0x0000005DUL /**< Mode APORT2YCH26 for VDAC_OPA_OUT */ #define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH28 0x0000005EUL /**< Mode APORT2YCH28 for VDAC_OPA_OUT */ #define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH30 0x0000005FUL /**< Mode APORT2YCH30 for VDAC_OPA_OUT */ #define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH1 0x00000070UL /**< Mode APORT3YCH1 for VDAC_OPA_OUT */ #define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH3 0x00000071UL /**< Mode APORT3YCH3 for VDAC_OPA_OUT */ #define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH5 0x00000072UL /**< Mode APORT3YCH5 for VDAC_OPA_OUT */ #define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH7 0x00000073UL /**< Mode APORT3YCH7 for VDAC_OPA_OUT */ #define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH9 0x00000074UL /**< Mode APORT3YCH9 for VDAC_OPA_OUT */ #define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH11 0x00000075UL /**< Mode APORT3YCH11 for VDAC_OPA_OUT */ #define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH13 0x00000076UL /**< Mode APORT3YCH13 for VDAC_OPA_OUT */ #define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH15 0x00000077UL /**< Mode APORT3YCH15 for VDAC_OPA_OUT */ #define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH17 0x00000078UL /**< Mode APORT3YCH17 for VDAC_OPA_OUT */ #define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH19 0x00000079UL /**< Mode APORT3YCH19 for VDAC_OPA_OUT */ #define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH21 0x0000007AUL /**< Mode APORT3YCH21 for VDAC_OPA_OUT */ #define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH23 0x0000007BUL /**< Mode APORT3YCH23 for VDAC_OPA_OUT */ #define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH25 0x0000007CUL /**< Mode APORT3YCH25 for VDAC_OPA_OUT */ #define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH27 0x0000007DUL /**< Mode APORT3YCH27 for VDAC_OPA_OUT */ #define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH29 0x0000007EUL /**< Mode APORT3YCH29 for VDAC_OPA_OUT */ #define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH31 0x0000007FUL /**< Mode APORT3YCH31 for VDAC_OPA_OUT */ #define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH0 0x00000090UL /**< Mode APORT4YCH0 for VDAC_OPA_OUT */ #define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH2 0x00000091UL /**< Mode APORT4YCH2 for VDAC_OPA_OUT */ #define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH4 0x00000092UL /**< Mode APORT4YCH4 for VDAC_OPA_OUT */ #define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH6 0x00000093UL /**< Mode APORT4YCH6 for VDAC_OPA_OUT */ #define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH8 0x00000094UL /**< Mode APORT4YCH8 for VDAC_OPA_OUT */ #define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH10 0x00000095UL /**< Mode APORT4YCH10 for VDAC_OPA_OUT */ #define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH12 0x00000096UL /**< Mode APORT4YCH12 for VDAC_OPA_OUT */ #define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH14 0x00000097UL /**< Mode APORT4YCH14 for VDAC_OPA_OUT */ #define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH16 0x00000098UL /**< Mode APORT4YCH16 for VDAC_OPA_OUT */ #define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH18 0x00000099UL /**< Mode APORT4YCH18 for VDAC_OPA_OUT */ #define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH20 0x0000009AUL /**< Mode APORT4YCH20 for VDAC_OPA_OUT */ #define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH22 0x0000009BUL /**< Mode APORT4YCH22 for VDAC_OPA_OUT */ #define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH24 0x0000009CUL /**< Mode APORT4YCH24 for VDAC_OPA_OUT */ #define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH26 0x0000009DUL /**< Mode APORT4YCH26 for VDAC_OPA_OUT */ #define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH28 0x0000009EUL /**< Mode APORT4YCH28 for VDAC_OPA_OUT */ #define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH30 0x0000009FUL /**< Mode APORT4YCH30 for VDAC_OPA_OUT */ #define VDAC_OPA_OUT_APORTOUTSEL_DEFAULT (_VDAC_OPA_OUT_APORTOUTSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_OPA_OUT */ #define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH1 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH1 << 16) /**< Shifted mode APORT1YCH1 for VDAC_OPA_OUT */ #define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH3 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH3 << 16) /**< Shifted mode APORT1YCH3 for VDAC_OPA_OUT */ #define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH5 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH5 << 16) /**< Shifted mode APORT1YCH5 for VDAC_OPA_OUT */ #define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH7 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH7 << 16) /**< Shifted mode APORT1YCH7 for VDAC_OPA_OUT */ #define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH9 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH9 << 16) /**< Shifted mode APORT1YCH9 for VDAC_OPA_OUT */ #define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH11 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH11 << 16) /**< Shifted mode APORT1YCH11 for VDAC_OPA_OUT */ #define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH13 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH13 << 16) /**< Shifted mode APORT1YCH13 for VDAC_OPA_OUT */ #define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH15 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH15 << 16) /**< Shifted mode APORT1YCH15 for VDAC_OPA_OUT */ #define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH17 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH17 << 16) /**< Shifted mode APORT1YCH17 for VDAC_OPA_OUT */ #define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH19 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH19 << 16) /**< Shifted mode APORT1YCH19 for VDAC_OPA_OUT */ #define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH21 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH21 << 16) /**< Shifted mode APORT1YCH21 for VDAC_OPA_OUT */ #define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH23 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH23 << 16) /**< Shifted mode APORT1YCH23 for VDAC_OPA_OUT */ #define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH25 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH25 << 16) /**< Shifted mode APORT1YCH25 for VDAC_OPA_OUT */ #define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH27 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH27 << 16) /**< Shifted mode APORT1YCH27 for VDAC_OPA_OUT */ #define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH29 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH29 << 16) /**< Shifted mode APORT1YCH29 for VDAC_OPA_OUT */ #define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH31 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH31 << 16) /**< Shifted mode APORT1YCH31 for VDAC_OPA_OUT */ #define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH0 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH0 << 16) /**< Shifted mode APORT2YCH0 for VDAC_OPA_OUT */ #define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH2 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH2 << 16) /**< Shifted mode APORT2YCH2 for VDAC_OPA_OUT */ #define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH4 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH4 << 16) /**< Shifted mode APORT2YCH4 for VDAC_OPA_OUT */ #define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH6 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH6 << 16) /**< Shifted mode APORT2YCH6 for VDAC_OPA_OUT */ #define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH8 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH8 << 16) /**< Shifted mode APORT2YCH8 for VDAC_OPA_OUT */ #define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH10 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH10 << 16) /**< Shifted mode APORT2YCH10 for VDAC_OPA_OUT */ #define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH12 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH12 << 16) /**< Shifted mode APORT2YCH12 for VDAC_OPA_OUT */ #define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH14 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH14 << 16) /**< Shifted mode APORT2YCH14 for VDAC_OPA_OUT */ #define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH16 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH16 << 16) /**< Shifted mode APORT2YCH16 for VDAC_OPA_OUT */ #define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH18 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH18 << 16) /**< Shifted mode APORT2YCH18 for VDAC_OPA_OUT */ #define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH20 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH20 << 16) /**< Shifted mode APORT2YCH20 for VDAC_OPA_OUT */ #define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH22 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH22 << 16) /**< Shifted mode APORT2YCH22 for VDAC_OPA_OUT */ #define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH24 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH24 << 16) /**< Shifted mode APORT2YCH24 for VDAC_OPA_OUT */ #define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH26 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH26 << 16) /**< Shifted mode APORT2YCH26 for VDAC_OPA_OUT */ #define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH28 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH28 << 16) /**< Shifted mode APORT2YCH28 for VDAC_OPA_OUT */ #define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH30 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH30 << 16) /**< Shifted mode APORT2YCH30 for VDAC_OPA_OUT */ #define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH1 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH1 << 16) /**< Shifted mode APORT3YCH1 for VDAC_OPA_OUT */ #define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH3 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH3 << 16) /**< Shifted mode APORT3YCH3 for VDAC_OPA_OUT */ #define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH5 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH5 << 16) /**< Shifted mode APORT3YCH5 for VDAC_OPA_OUT */ #define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH7 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH7 << 16) /**< Shifted mode APORT3YCH7 for VDAC_OPA_OUT */ #define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH9 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH9 << 16) /**< Shifted mode APORT3YCH9 for VDAC_OPA_OUT */ #define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH11 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH11 << 16) /**< Shifted mode APORT3YCH11 for VDAC_OPA_OUT */ #define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH13 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH13 << 16) /**< Shifted mode APORT3YCH13 for VDAC_OPA_OUT */ #define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH15 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH15 << 16) /**< Shifted mode APORT3YCH15 for VDAC_OPA_OUT */ #define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH17 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH17 << 16) /**< Shifted mode APORT3YCH17 for VDAC_OPA_OUT */ #define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH19 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH19 << 16) /**< Shifted mode APORT3YCH19 for VDAC_OPA_OUT */ #define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH21 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH21 << 16) /**< Shifted mode APORT3YCH21 for VDAC_OPA_OUT */ #define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH23 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH23 << 16) /**< Shifted mode APORT3YCH23 for VDAC_OPA_OUT */ #define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH25 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH25 << 16) /**< Shifted mode APORT3YCH25 for VDAC_OPA_OUT */ #define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH27 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH27 << 16) /**< Shifted mode APORT3YCH27 for VDAC_OPA_OUT */ #define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH29 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH29 << 16) /**< Shifted mode APORT3YCH29 for VDAC_OPA_OUT */ #define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH31 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH31 << 16) /**< Shifted mode APORT3YCH31 for VDAC_OPA_OUT */ #define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH0 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH0 << 16) /**< Shifted mode APORT4YCH0 for VDAC_OPA_OUT */ #define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH2 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH2 << 16) /**< Shifted mode APORT4YCH2 for VDAC_OPA_OUT */ #define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH4 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH4 << 16) /**< Shifted mode APORT4YCH4 for VDAC_OPA_OUT */ #define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH6 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH6 << 16) /**< Shifted mode APORT4YCH6 for VDAC_OPA_OUT */ #define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH8 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH8 << 16) /**< Shifted mode APORT4YCH8 for VDAC_OPA_OUT */ #define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH10 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH10 << 16) /**< Shifted mode APORT4YCH10 for VDAC_OPA_OUT */ #define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH12 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH12 << 16) /**< Shifted mode APORT4YCH12 for VDAC_OPA_OUT */ #define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH14 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH14 << 16) /**< Shifted mode APORT4YCH14 for VDAC_OPA_OUT */ #define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH16 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH16 << 16) /**< Shifted mode APORT4YCH16 for VDAC_OPA_OUT */ #define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH18 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH18 << 16) /**< Shifted mode APORT4YCH18 for VDAC_OPA_OUT */ #define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH20 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH20 << 16) /**< Shifted mode APORT4YCH20 for VDAC_OPA_OUT */ #define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH22 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH22 << 16) /**< Shifted mode APORT4YCH22 for VDAC_OPA_OUT */ #define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH24 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH24 << 16) /**< Shifted mode APORT4YCH24 for VDAC_OPA_OUT */ #define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH26 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH26 << 16) /**< Shifted mode APORT4YCH26 for VDAC_OPA_OUT */ #define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH28 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH28 << 16) /**< Shifted mode APORT4YCH28 for VDAC_OPA_OUT */ #define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH30 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH30 << 16) /**< Shifted mode APORT4YCH30 for VDAC_OPA_OUT */ /* Bit fields for VDAC OPA_CAL */ #define _VDAC_OPA_CAL_RESETVALUE 0x000080E7UL /**< Default value for VDAC_OPA_CAL */ #define _VDAC_OPA_CAL_MASK 0x7DF6EDEFUL /**< Mask for VDAC_OPA_CAL */ #define _VDAC_OPA_CAL_CM1_SHIFT 0 /**< Shift value for VDAC_OPACM1 */ #define _VDAC_OPA_CAL_CM1_MASK 0xFUL /**< Bit mask for VDAC_OPACM1 */ #define _VDAC_OPA_CAL_CM1_DEFAULT 0x00000007UL /**< Mode DEFAULT for VDAC_OPA_CAL */ #define VDAC_OPA_CAL_CM1_DEFAULT (_VDAC_OPA_CAL_CM1_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_OPA_CAL */ #define _VDAC_OPA_CAL_CM2_SHIFT 5 /**< Shift value for VDAC_OPACM2 */ #define _VDAC_OPA_CAL_CM2_MASK 0x1E0UL /**< Bit mask for VDAC_OPACM2 */ #define _VDAC_OPA_CAL_CM2_DEFAULT 0x00000007UL /**< Mode DEFAULT for VDAC_OPA_CAL */ #define VDAC_OPA_CAL_CM2_DEFAULT (_VDAC_OPA_CAL_CM2_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_OPA_CAL */ #define _VDAC_OPA_CAL_CM3_SHIFT 10 /**< Shift value for VDAC_OPACM3 */ #define _VDAC_OPA_CAL_CM3_MASK 0xC00UL /**< Bit mask for VDAC_OPACM3 */ #define _VDAC_OPA_CAL_CM3_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_CAL */ #define VDAC_OPA_CAL_CM3_DEFAULT (_VDAC_OPA_CAL_CM3_DEFAULT << 10) /**< Shifted mode DEFAULT for VDAC_OPA_CAL */ #define _VDAC_OPA_CAL_GM_SHIFT 13 /**< Shift value for VDAC_OPAGM */ #define _VDAC_OPA_CAL_GM_MASK 0xE000UL /**< Bit mask for VDAC_OPAGM */ #define _VDAC_OPA_CAL_GM_DEFAULT 0x00000004UL /**< Mode DEFAULT for VDAC_OPA_CAL */ #define VDAC_OPA_CAL_GM_DEFAULT (_VDAC_OPA_CAL_GM_DEFAULT << 13) /**< Shifted mode DEFAULT for VDAC_OPA_CAL */ #define _VDAC_OPA_CAL_GM3_SHIFT 17 /**< Shift value for VDAC_OPAGM3 */ #define _VDAC_OPA_CAL_GM3_MASK 0x60000UL /**< Bit mask for VDAC_OPAGM3 */ #define _VDAC_OPA_CAL_GM3_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_CAL */ #define VDAC_OPA_CAL_GM3_DEFAULT (_VDAC_OPA_CAL_GM3_DEFAULT << 17) /**< Shifted mode DEFAULT for VDAC_OPA_CAL */ #define _VDAC_OPA_CAL_OFFSETP_SHIFT 20 /**< Shift value for VDAC_OPAOFFSETP */ #define _VDAC_OPA_CAL_OFFSETP_MASK 0x1F00000UL /**< Bit mask for VDAC_OPAOFFSETP */ #define _VDAC_OPA_CAL_OFFSETP_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_CAL */ #define VDAC_OPA_CAL_OFFSETP_DEFAULT (_VDAC_OPA_CAL_OFFSETP_DEFAULT << 20) /**< Shifted mode DEFAULT for VDAC_OPA_CAL */ #define _VDAC_OPA_CAL_OFFSETN_SHIFT 26 /**< Shift value for VDAC_OPAOFFSETN */ #define _VDAC_OPA_CAL_OFFSETN_MASK 0x7C000000UL /**< Bit mask for VDAC_OPAOFFSETN */ #define _VDAC_OPA_CAL_OFFSETN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_CAL */ #define VDAC_OPA_CAL_OFFSETN_DEFAULT (_VDAC_OPA_CAL_OFFSETN_DEFAULT << 26) /**< Shifted mode DEFAULT for VDAC_OPA_CAL */ /** @} */ /** @} End of group EFR32MG12P_VDAC */ /** @} End of group Parts */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_vdac_opa.h.
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/***************************************************************************//** * @file * @brief EFR32MG12P_VDAC_OPA register and bit field definitions * @version 5.7.0 ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * SPDX-License-Identifier: Zlib * * The licensor of this software is Silicon Laboratories Inc. * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be * appreciated but is not required. * 2. Altered source versions must be plainly marked as such, and must not be * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * ******************************************************************************/ #if defined(__ICCARM__) #pragma system_include /* Treat file as system include file. */ #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang system_header /* Treat file as system include file. */ #endif /***************************************************************************//** * @addtogroup Parts * @{ ******************************************************************************/ /***************************************************************************//** * @brief VDAC_OPA VDAC OPA Register * @ingroup EFR32MG12P_VDAC ******************************************************************************/ typedef struct { __IM uint32_t APORTREQ; /**< Operational Amplifier APORT Request Status Register */ __IM uint32_t APORTCONFLICT; /**< Operational Amplifier APORT Conflict Status Register */ __IOM uint32_t CTRL; /**< Operational Amplifier Control Register */ __IOM uint32_t TIMER; /**< Operational Amplifier Timer Control Register */ __IOM uint32_t MUX; /**< Operational Amplifier Mux Configuration Register */ __IOM uint32_t OUT; /**< Operational Amplifier Output Configuration Register */ __IOM uint32_t CAL; /**< Operational Amplifier Calibration Register */ uint32_t RESERVED0[1U]; /**< Reserved future */ } VDAC_OPA_TypeDef; /** @} End of group Parts */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_wdog.h.
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/***************************************************************************//** * @file * @brief EFR32MG12P_WDOG register and bit field definitions * @version 5.7.0 ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * SPDX-License-Identifier: Zlib * * The licensor of this software is Silicon Laboratories Inc. * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be * appreciated but is not required. * 2. Altered source versions must be plainly marked as such, and must not be * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * ******************************************************************************/ #if defined(__ICCARM__) #pragma system_include /* Treat file as system include file. */ #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang system_header /* Treat file as system include file. */ #endif /***************************************************************************//** * @addtogroup Parts * @{ ******************************************************************************/ /***************************************************************************//** * @defgroup EFR32MG12P_WDOG WDOG * @{ * @brief EFR32MG12P_WDOG Register Declaration ******************************************************************************/ /** WDOG Register Declaration */ typedef struct { __IOM uint32_t CTRL; /**< Control Register */ __IOM uint32_t CMD; /**< Command Register */ __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ WDOG_PCH_TypeDef PCH[2U]; /**< PCH */ uint32_t RESERVED0[2U]; /**< Reserved for future use **/ __IM uint32_t IF; /**< Watchdog Interrupt Flags */ __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ __IOM uint32_t IEN; /**< Interrupt Enable Register */ } WDOG_TypeDef; /** @} */ /***************************************************************************//** * @addtogroup EFR32MG12P_WDOG * @{ * @defgroup EFR32MG12P_WDOG_BitFields WDOG Bit Fields * @{ ******************************************************************************/ /* Bit fields for WDOG CTRL */ #define _WDOG_CTRL_RESETVALUE 0x00000F00UL /**< Default value for WDOG_CTRL */ #define _WDOG_CTRL_MASK 0xC7033F7FUL /**< Mask for WDOG_CTRL */ #define WDOG_CTRL_EN (0x1UL << 0) /**< Watchdog Timer Enable */ #define _WDOG_CTRL_EN_SHIFT 0 /**< Shift value for WDOG_EN */ #define _WDOG_CTRL_EN_MASK 0x1UL /**< Bit mask for WDOG_EN */ #define _WDOG_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */ #define WDOG_CTRL_EN_DEFAULT (_WDOG_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_CTRL */ #define WDOG_CTRL_DEBUGRUN (0x1UL << 1) /**< Debug Mode Run Enable */ #define _WDOG_CTRL_DEBUGRUN_SHIFT 1 /**< Shift value for WDOG_DEBUGRUN */ #define _WDOG_CTRL_DEBUGRUN_MASK 0x2UL /**< Bit mask for WDOG_DEBUGRUN */ #define _WDOG_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */ #define WDOG_CTRL_DEBUGRUN_DEFAULT (_WDOG_CTRL_DEBUGRUN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_CTRL */ #define WDOG_CTRL_EM2RUN (0x1UL << 2) /**< Energy Mode 2 Run Enable */ #define _WDOG_CTRL_EM2RUN_SHIFT 2 /**< Shift value for WDOG_EM2RUN */ #define _WDOG_CTRL_EM2RUN_MASK 0x4UL /**< Bit mask for WDOG_EM2RUN */ #define _WDOG_CTRL_EM2RUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */ #define WDOG_CTRL_EM2RUN_DEFAULT (_WDOG_CTRL_EM2RUN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_CTRL */ #define WDOG_CTRL_EM3RUN (0x1UL << 3) /**< Energy Mode 3 Run Enable */ #define _WDOG_CTRL_EM3RUN_SHIFT 3 /**< Shift value for WDOG_EM3RUN */ #define _WDOG_CTRL_EM3RUN_MASK 0x8UL /**< Bit mask for WDOG_EM3RUN */ #define _WDOG_CTRL_EM3RUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */ #define WDOG_CTRL_EM3RUN_DEFAULT (_WDOG_CTRL_EM3RUN_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_CTRL */ #define WDOG_CTRL_LOCK (0x1UL << 4) /**< Configuration Lock */ #define _WDOG_CTRL_LOCK_SHIFT 4 /**< Shift value for WDOG_LOCK */ #define _WDOG_CTRL_LOCK_MASK 0x10UL /**< Bit mask for WDOG_LOCK */ #define _WDOG_CTRL_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */ #define WDOG_CTRL_LOCK_DEFAULT (_WDOG_CTRL_LOCK_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_CTRL */ #define WDOG_CTRL_EM4BLOCK (0x1UL << 5) /**< Energy Mode 4 Block */ #define _WDOG_CTRL_EM4BLOCK_SHIFT 5 /**< Shift value for WDOG_EM4BLOCK */ #define _WDOG_CTRL_EM4BLOCK_MASK 0x20UL /**< Bit mask for WDOG_EM4BLOCK */ #define _WDOG_CTRL_EM4BLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */ #define WDOG_CTRL_EM4BLOCK_DEFAULT (_WDOG_CTRL_EM4BLOCK_DEFAULT << 5) /**< Shifted mode DEFAULT for WDOG_CTRL */ #define WDOG_CTRL_SWOSCBLOCK (0x1UL << 6) /**< Software Oscillator Disable Block */ #define _WDOG_CTRL_SWOSCBLOCK_SHIFT 6 /**< Shift value for WDOG_SWOSCBLOCK */ #define _WDOG_CTRL_SWOSCBLOCK_MASK 0x40UL /**< Bit mask for WDOG_SWOSCBLOCK */ #define _WDOG_CTRL_SWOSCBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */ #define WDOG_CTRL_SWOSCBLOCK_DEFAULT (_WDOG_CTRL_SWOSCBLOCK_DEFAULT << 6) /**< Shifted mode DEFAULT for WDOG_CTRL */ #define _WDOG_CTRL_PERSEL_SHIFT 8 /**< Shift value for WDOG_PERSEL */ #define _WDOG_CTRL_PERSEL_MASK 0xF00UL /**< Bit mask for WDOG_PERSEL */ #define _WDOG_CTRL_PERSEL_DEFAULT 0x0000000FUL /**< Mode DEFAULT for WDOG_CTRL */ #define WDOG_CTRL_PERSEL_DEFAULT (_WDOG_CTRL_PERSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WDOG_CTRL */ #define _WDOG_CTRL_CLKSEL_SHIFT 12 /**< Shift value for WDOG_CLKSEL */ #define _WDOG_CTRL_CLKSEL_MASK 0x3000UL /**< Bit mask for WDOG_CLKSEL */ #define _WDOG_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */ #define _WDOG_CTRL_CLKSEL_ULFRCO 0x00000000UL /**< Mode ULFRCO for WDOG_CTRL */ #define _WDOG_CTRL_CLKSEL_LFRCO 0x00000001UL /**< Mode LFRCO for WDOG_CTRL */ #define _WDOG_CTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for WDOG_CTRL */ #define _WDOG_CTRL_CLKSEL_HFCORECLK 0x00000003UL /**< Mode HFCORECLK for WDOG_CTRL */ #define WDOG_CTRL_CLKSEL_DEFAULT (_WDOG_CTRL_CLKSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for WDOG_CTRL */ #define WDOG_CTRL_CLKSEL_ULFRCO (_WDOG_CTRL_CLKSEL_ULFRCO << 12) /**< Shifted mode ULFRCO for WDOG_CTRL */ #define WDOG_CTRL_CLKSEL_LFRCO (_WDOG_CTRL_CLKSEL_LFRCO << 12) /**< Shifted mode LFRCO for WDOG_CTRL */ #define WDOG_CTRL_CLKSEL_LFXO (_WDOG_CTRL_CLKSEL_LFXO << 12) /**< Shifted mode LFXO for WDOG_CTRL */ #define WDOG_CTRL_CLKSEL_HFCORECLK (_WDOG_CTRL_CLKSEL_HFCORECLK << 12) /**< Shifted mode HFCORECLK for WDOG_CTRL */ #define _WDOG_CTRL_WARNSEL_SHIFT 16 /**< Shift value for WDOG_WARNSEL */ #define _WDOG_CTRL_WARNSEL_MASK 0x30000UL /**< Bit mask for WDOG_WARNSEL */ #define _WDOG_CTRL_WARNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */ #define WDOG_CTRL_WARNSEL_DEFAULT (_WDOG_CTRL_WARNSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WDOG_CTRL */ #define _WDOG_CTRL_WINSEL_SHIFT 24 /**< Shift value for WDOG_WINSEL */ #define _WDOG_CTRL_WINSEL_MASK 0x7000000UL /**< Bit mask for WDOG_WINSEL */ #define _WDOG_CTRL_WINSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */ #define WDOG_CTRL_WINSEL_DEFAULT (_WDOG_CTRL_WINSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for WDOG_CTRL */ #define WDOG_CTRL_CLRSRC (0x1UL << 30) /**< Watchdog Clear Source */ #define _WDOG_CTRL_CLRSRC_SHIFT 30 /**< Shift value for WDOG_CLRSRC */ #define _WDOG_CTRL_CLRSRC_MASK 0x40000000UL /**< Bit mask for WDOG_CLRSRC */ #define _WDOG_CTRL_CLRSRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */ #define _WDOG_CTRL_CLRSRC_SW 0x00000000UL /**< Mode SW for WDOG_CTRL */ #define _WDOG_CTRL_CLRSRC_PCH0 0x00000001UL /**< Mode PCH0 for WDOG_CTRL */ #define WDOG_CTRL_CLRSRC_DEFAULT (_WDOG_CTRL_CLRSRC_DEFAULT << 30) /**< Shifted mode DEFAULT for WDOG_CTRL */ #define WDOG_CTRL_CLRSRC_SW (_WDOG_CTRL_CLRSRC_SW << 30) /**< Shifted mode SW for WDOG_CTRL */ #define WDOG_CTRL_CLRSRC_PCH0 (_WDOG_CTRL_CLRSRC_PCH0 << 30) /**< Shifted mode PCH0 for WDOG_CTRL */ #define WDOG_CTRL_WDOGRSTDIS (0x1UL << 31) /**< Watchdog Reset Disable */ #define _WDOG_CTRL_WDOGRSTDIS_SHIFT 31 /**< Shift value for WDOG_WDOGRSTDIS */ #define _WDOG_CTRL_WDOGRSTDIS_MASK 0x80000000UL /**< Bit mask for WDOG_WDOGRSTDIS */ #define _WDOG_CTRL_WDOGRSTDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */ #define _WDOG_CTRL_WDOGRSTDIS_EN 0x00000000UL /**< Mode EN for WDOG_CTRL */ #define _WDOG_CTRL_WDOGRSTDIS_DIS 0x00000001UL /**< Mode DIS for WDOG_CTRL */ #define WDOG_CTRL_WDOGRSTDIS_DEFAULT (_WDOG_CTRL_WDOGRSTDIS_DEFAULT << 31) /**< Shifted mode DEFAULT for WDOG_CTRL */ #define WDOG_CTRL_WDOGRSTDIS_EN (_WDOG_CTRL_WDOGRSTDIS_EN << 31) /**< Shifted mode EN for WDOG_CTRL */ #define WDOG_CTRL_WDOGRSTDIS_DIS (_WDOG_CTRL_WDOGRSTDIS_DIS << 31) /**< Shifted mode DIS for WDOG_CTRL */ /* Bit fields for WDOG CMD */ #define _WDOG_CMD_RESETVALUE 0x00000000UL /**< Default value for WDOG_CMD */ #define _WDOG_CMD_MASK 0x00000001UL /**< Mask for WDOG_CMD */ #define WDOG_CMD_CLEAR (0x1UL << 0) /**< Watchdog Timer Clear */ #define _WDOG_CMD_CLEAR_SHIFT 0 /**< Shift value for WDOG_CLEAR */ #define _WDOG_CMD_CLEAR_MASK 0x1UL /**< Bit mask for WDOG_CLEAR */ #define _WDOG_CMD_CLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CMD */ #define _WDOG_CMD_CLEAR_UNCHANGED 0x00000000UL /**< Mode UNCHANGED for WDOG_CMD */ #define _WDOG_CMD_CLEAR_CLEARED 0x00000001UL /**< Mode CLEARED for WDOG_CMD */ #define WDOG_CMD_CLEAR_DEFAULT (_WDOG_CMD_CLEAR_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_CMD */ #define WDOG_CMD_CLEAR_UNCHANGED (_WDOG_CMD_CLEAR_UNCHANGED << 0) /**< Shifted mode UNCHANGED for WDOG_CMD */ #define WDOG_CMD_CLEAR_CLEARED (_WDOG_CMD_CLEAR_CLEARED << 0) /**< Shifted mode CLEARED for WDOG_CMD */ /* Bit fields for WDOG SYNCBUSY */ #define _WDOG_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for WDOG_SYNCBUSY */ #define _WDOG_SYNCBUSY_MASK 0x0000000FUL /**< Mask for WDOG_SYNCBUSY */ #define WDOG_SYNCBUSY_CTRL (0x1UL << 0) /**< CTRL Register Busy */ #define _WDOG_SYNCBUSY_CTRL_SHIFT 0 /**< Shift value for WDOG_CTRL */ #define _WDOG_SYNCBUSY_CTRL_MASK 0x1UL /**< Bit mask for WDOG_CTRL */ #define _WDOG_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_SYNCBUSY */ #define WDOG_SYNCBUSY_CTRL_DEFAULT (_WDOG_SYNCBUSY_CTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_SYNCBUSY */ #define WDOG_SYNCBUSY_CMD (0x1UL << 1) /**< CMD Register Busy */ #define _WDOG_SYNCBUSY_CMD_SHIFT 1 /**< Shift value for WDOG_CMD */ #define _WDOG_SYNCBUSY_CMD_MASK 0x2UL /**< Bit mask for WDOG_CMD */ #define _WDOG_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_SYNCBUSY */ #define WDOG_SYNCBUSY_CMD_DEFAULT (_WDOG_SYNCBUSY_CMD_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_SYNCBUSY */ #define WDOG_SYNCBUSY_PCH0_PRSCTRL (0x1UL << 2) /**< PCH0_PRSCTRL Register Busy */ #define _WDOG_SYNCBUSY_PCH0_PRSCTRL_SHIFT 2 /**< Shift value for WDOG_PCH0_PRSCTRL */ #define _WDOG_SYNCBUSY_PCH0_PRSCTRL_MASK 0x4UL /**< Bit mask for WDOG_PCH0_PRSCTRL */ #define _WDOG_SYNCBUSY_PCH0_PRSCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_SYNCBUSY */ #define WDOG_SYNCBUSY_PCH0_PRSCTRL_DEFAULT (_WDOG_SYNCBUSY_PCH0_PRSCTRL_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_SYNCBUSY */ #define WDOG_SYNCBUSY_PCH1_PRSCTRL (0x1UL << 3) /**< PCH1_PRSCTRL Register Busy */ #define _WDOG_SYNCBUSY_PCH1_PRSCTRL_SHIFT 3 /**< Shift value for WDOG_PCH1_PRSCTRL */ #define _WDOG_SYNCBUSY_PCH1_PRSCTRL_MASK 0x8UL /**< Bit mask for WDOG_PCH1_PRSCTRL */ #define _WDOG_SYNCBUSY_PCH1_PRSCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_SYNCBUSY */ #define WDOG_SYNCBUSY_PCH1_PRSCTRL_DEFAULT (_WDOG_SYNCBUSY_PCH1_PRSCTRL_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_SYNCBUSY */ /* Bit fields for WDOG PCH_PRSCTRL */ #define _WDOG_PCH_PRSCTRL_RESETVALUE 0x00000000UL /**< Default value for WDOG_PCH_PRSCTRL */ #define _WDOG_PCH_PRSCTRL_MASK 0x0000010FUL /**< Mask for WDOG_PCH_PRSCTRL */ #define _WDOG_PCH_PRSCTRL_PRSSEL_SHIFT 0 /**< Shift value for WDOG_PRSSEL */ #define _WDOG_PCH_PRSCTRL_PRSSEL_MASK 0xFUL /**< Bit mask for WDOG_PRSSEL */ #define _WDOG_PCH_PRSCTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_PCH_PRSCTRL */ #define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WDOG_PCH_PRSCTRL */ #define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WDOG_PCH_PRSCTRL */ #define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WDOG_PCH_PRSCTRL */ #define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WDOG_PCH_PRSCTRL */ #define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WDOG_PCH_PRSCTRL */ #define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WDOG_PCH_PRSCTRL */ #define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WDOG_PCH_PRSCTRL */ #define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WDOG_PCH_PRSCTRL */ #define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WDOG_PCH_PRSCTRL */ #define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WDOG_PCH_PRSCTRL */ #define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WDOG_PCH_PRSCTRL */ #define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WDOG_PCH_PRSCTRL */ #define WDOG_PCH_PRSCTRL_PRSSEL_DEFAULT (_WDOG_PCH_PRSCTRL_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_PCH_PRSCTRL */ #define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH0 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WDOG_PCH_PRSCTRL */ #define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH1 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WDOG_PCH_PRSCTRL */ #define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH2 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WDOG_PCH_PRSCTRL */ #define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH3 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WDOG_PCH_PRSCTRL */ #define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH4 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WDOG_PCH_PRSCTRL */ #define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH5 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WDOG_PCH_PRSCTRL */ #define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH6 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WDOG_PCH_PRSCTRL */ #define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH7 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WDOG_PCH_PRSCTRL */ #define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH8 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WDOG_PCH_PRSCTRL */ #define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH9 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WDOG_PCH_PRSCTRL */ #define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH10 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WDOG_PCH_PRSCTRL */ #define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH11 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WDOG_PCH_PRSCTRL */ #define WDOG_PCH_PRSCTRL_PRSMISSRSTEN (0x1UL << 8) /**< PRS Missing Event Will Trigger a Watchdog Reset */ #define _WDOG_PCH_PRSCTRL_PRSMISSRSTEN_SHIFT 8 /**< Shift value for WDOG_PRSMISSRSTEN */ #define _WDOG_PCH_PRSCTRL_PRSMISSRSTEN_MASK 0x100UL /**< Bit mask for WDOG_PRSMISSRSTEN */ #define _WDOG_PCH_PRSCTRL_PRSMISSRSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_PCH_PRSCTRL */ #define WDOG_PCH_PRSCTRL_PRSMISSRSTEN_DEFAULT (_WDOG_PCH_PRSCTRL_PRSMISSRSTEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WDOG_PCH_PRSCTRL */ /* Bit fields for WDOG IF */ #define _WDOG_IF_RESETVALUE 0x00000000UL /**< Default value for WDOG_IF */ #define _WDOG_IF_MASK 0x0000001FUL /**< Mask for WDOG_IF */ #define WDOG_IF_TOUT (0x1UL << 0) /**< WDOG Timeout Interrupt Flag */ #define _WDOG_IF_TOUT_SHIFT 0 /**< Shift value for WDOG_TOUT */ #define _WDOG_IF_TOUT_MASK 0x1UL /**< Bit mask for WDOG_TOUT */ #define _WDOG_IF_TOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */ #define WDOG_IF_TOUT_DEFAULT (_WDOG_IF_TOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_IF */ #define WDOG_IF_WARN (0x1UL << 1) /**< WDOG Warning Timeout Interrupt Flag */ #define _WDOG_IF_WARN_SHIFT 1 /**< Shift value for WDOG_WARN */ #define _WDOG_IF_WARN_MASK 0x2UL /**< Bit mask for WDOG_WARN */ #define _WDOG_IF_WARN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */ #define WDOG_IF_WARN_DEFAULT (_WDOG_IF_WARN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_IF */ #define WDOG_IF_WIN (0x1UL << 2) /**< WDOG Window Interrupt Flag */ #define _WDOG_IF_WIN_SHIFT 2 /**< Shift value for WDOG_WIN */ #define _WDOG_IF_WIN_MASK 0x4UL /**< Bit mask for WDOG_WIN */ #define _WDOG_IF_WIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */ #define WDOG_IF_WIN_DEFAULT (_WDOG_IF_WIN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_IF */ #define WDOG_IF_PEM0 (0x1UL << 3) /**< PRS Channel Zero Event Missing Interrupt Flag */ #define _WDOG_IF_PEM0_SHIFT 3 /**< Shift value for WDOG_PEM0 */ #define _WDOG_IF_PEM0_MASK 0x8UL /**< Bit mask for WDOG_PEM0 */ #define _WDOG_IF_PEM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */ #define WDOG_IF_PEM0_DEFAULT (_WDOG_IF_PEM0_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_IF */ #define WDOG_IF_PEM1 (0x1UL << 4) /**< PRS Channel One Event Missing Interrupt Flag */ #define _WDOG_IF_PEM1_SHIFT 4 /**< Shift value for WDOG_PEM1 */ #define _WDOG_IF_PEM1_MASK 0x10UL /**< Bit mask for WDOG_PEM1 */ #define _WDOG_IF_PEM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */ #define WDOG_IF_PEM1_DEFAULT (_WDOG_IF_PEM1_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_IF */ /* Bit fields for WDOG IFS */ #define _WDOG_IFS_RESETVALUE 0x00000000UL /**< Default value for WDOG_IFS */ #define _WDOG_IFS_MASK 0x0000001FUL /**< Mask for WDOG_IFS */ #define WDOG_IFS_TOUT (0x1UL << 0) /**< Set TOUT Interrupt Flag */ #define _WDOG_IFS_TOUT_SHIFT 0 /**< Shift value for WDOG_TOUT */ #define _WDOG_IFS_TOUT_MASK 0x1UL /**< Bit mask for WDOG_TOUT */ #define _WDOG_IFS_TOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFS */ #define WDOG_IFS_TOUT_DEFAULT (_WDOG_IFS_TOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_IFS */ #define WDOG_IFS_WARN (0x1UL << 1) /**< Set WARN Interrupt Flag */ #define _WDOG_IFS_WARN_SHIFT 1 /**< Shift value for WDOG_WARN */ #define _WDOG_IFS_WARN_MASK 0x2UL /**< Bit mask for WDOG_WARN */ #define _WDOG_IFS_WARN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFS */ #define WDOG_IFS_WARN_DEFAULT (_WDOG_IFS_WARN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_IFS */ #define WDOG_IFS_WIN (0x1UL << 2) /**< Set WIN Interrupt Flag */ #define _WDOG_IFS_WIN_SHIFT 2 /**< Shift value for WDOG_WIN */ #define _WDOG_IFS_WIN_MASK 0x4UL /**< Bit mask for WDOG_WIN */ #define _WDOG_IFS_WIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFS */ #define WDOG_IFS_WIN_DEFAULT (_WDOG_IFS_WIN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_IFS */ #define WDOG_IFS_PEM0 (0x1UL << 3) /**< Set PEM0 Interrupt Flag */ #define _WDOG_IFS_PEM0_SHIFT 3 /**< Shift value for WDOG_PEM0 */ #define _WDOG_IFS_PEM0_MASK 0x8UL /**< Bit mask for WDOG_PEM0 */ #define _WDOG_IFS_PEM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFS */ #define WDOG_IFS_PEM0_DEFAULT (_WDOG_IFS_PEM0_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_IFS */ #define WDOG_IFS_PEM1 (0x1UL << 4) /**< Set PEM1 Interrupt Flag */ #define _WDOG_IFS_PEM1_SHIFT 4 /**< Shift value for WDOG_PEM1 */ #define _WDOG_IFS_PEM1_MASK 0x10UL /**< Bit mask for WDOG_PEM1 */ #define _WDOG_IFS_PEM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFS */ #define WDOG_IFS_PEM1_DEFAULT (_WDOG_IFS_PEM1_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_IFS */ /* Bit fields for WDOG IFC */ #define _WDOG_IFC_RESETVALUE 0x00000000UL /**< Default value for WDOG_IFC */ #define _WDOG_IFC_MASK 0x0000001FUL /**< Mask for WDOG_IFC */ #define WDOG_IFC_TOUT (0x1UL << 0) /**< Clear TOUT Interrupt Flag */ #define _WDOG_IFC_TOUT_SHIFT 0 /**< Shift value for WDOG_TOUT */ #define _WDOG_IFC_TOUT_MASK 0x1UL /**< Bit mask for WDOG_TOUT */ #define _WDOG_IFC_TOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFC */ #define WDOG_IFC_TOUT_DEFAULT (_WDOG_IFC_TOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_IFC */ #define WDOG_IFC_WARN (0x1UL << 1) /**< Clear WARN Interrupt Flag */ #define _WDOG_IFC_WARN_SHIFT 1 /**< Shift value for WDOG_WARN */ #define _WDOG_IFC_WARN_MASK 0x2UL /**< Bit mask for WDOG_WARN */ #define _WDOG_IFC_WARN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFC */ #define WDOG_IFC_WARN_DEFAULT (_WDOG_IFC_WARN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_IFC */ #define WDOG_IFC_WIN (0x1UL << 2) /**< Clear WIN Interrupt Flag */ #define _WDOG_IFC_WIN_SHIFT 2 /**< Shift value for WDOG_WIN */ #define _WDOG_IFC_WIN_MASK 0x4UL /**< Bit mask for WDOG_WIN */ #define _WDOG_IFC_WIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFC */ #define WDOG_IFC_WIN_DEFAULT (_WDOG_IFC_WIN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_IFC */ #define WDOG_IFC_PEM0 (0x1UL << 3) /**< Clear PEM0 Interrupt Flag */ #define _WDOG_IFC_PEM0_SHIFT 3 /**< Shift value for WDOG_PEM0 */ #define _WDOG_IFC_PEM0_MASK 0x8UL /**< Bit mask for WDOG_PEM0 */ #define _WDOG_IFC_PEM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFC */ #define WDOG_IFC_PEM0_DEFAULT (_WDOG_IFC_PEM0_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_IFC */ #define WDOG_IFC_PEM1 (0x1UL << 4) /**< Clear PEM1 Interrupt Flag */ #define _WDOG_IFC_PEM1_SHIFT 4 /**< Shift value for WDOG_PEM1 */ #define _WDOG_IFC_PEM1_MASK 0x10UL /**< Bit mask for WDOG_PEM1 */ #define _WDOG_IFC_PEM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFC */ #define WDOG_IFC_PEM1_DEFAULT (_WDOG_IFC_PEM1_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_IFC */ /* Bit fields for WDOG IEN */ #define _WDOG_IEN_RESETVALUE 0x00000000UL /**< Default value for WDOG_IEN */ #define _WDOG_IEN_MASK 0x0000001FUL /**< Mask for WDOG_IEN */ #define WDOG_IEN_TOUT (0x1UL << 0) /**< TOUT Interrupt Enable */ #define _WDOG_IEN_TOUT_SHIFT 0 /**< Shift value for WDOG_TOUT */ #define _WDOG_IEN_TOUT_MASK 0x1UL /**< Bit mask for WDOG_TOUT */ #define _WDOG_IEN_TOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */ #define WDOG_IEN_TOUT_DEFAULT (_WDOG_IEN_TOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_IEN */ #define WDOG_IEN_WARN (0x1UL << 1) /**< WARN Interrupt Enable */ #define _WDOG_IEN_WARN_SHIFT 1 /**< Shift value for WDOG_WARN */ #define _WDOG_IEN_WARN_MASK 0x2UL /**< Bit mask for WDOG_WARN */ #define _WDOG_IEN_WARN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */ #define WDOG_IEN_WARN_DEFAULT (_WDOG_IEN_WARN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_IEN */ #define WDOG_IEN_WIN (0x1UL << 2) /**< WIN Interrupt Enable */ #define _WDOG_IEN_WIN_SHIFT 2 /**< Shift value for WDOG_WIN */ #define _WDOG_IEN_WIN_MASK 0x4UL /**< Bit mask for WDOG_WIN */ #define _WDOG_IEN_WIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */ #define WDOG_IEN_WIN_DEFAULT (_WDOG_IEN_WIN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_IEN */ #define WDOG_IEN_PEM0 (0x1UL << 3) /**< PEM0 Interrupt Enable */ #define _WDOG_IEN_PEM0_SHIFT 3 /**< Shift value for WDOG_PEM0 */ #define _WDOG_IEN_PEM0_MASK 0x8UL /**< Bit mask for WDOG_PEM0 */ #define _WDOG_IEN_PEM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */ #define WDOG_IEN_PEM0_DEFAULT (_WDOG_IEN_PEM0_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_IEN */ #define WDOG_IEN_PEM1 (0x1UL << 4) /**< PEM1 Interrupt Enable */ #define _WDOG_IEN_PEM1_SHIFT 4 /**< Shift value for WDOG_PEM1 */ #define _WDOG_IEN_PEM1_MASK 0x10UL /**< Bit mask for WDOG_PEM1 */ #define _WDOG_IEN_PEM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */ #define WDOG_IEN_PEM1_DEFAULT (_WDOG_IEN_PEM1_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_IEN */ /** @} */ /** @} End of group EFR32MG12P_WDOG */ /** @} End of group Parts */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_wdog_pch.h.
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/***************************************************************************//** * @file * @brief EFR32MG12P_WDOG_PCH register and bit field definitions * @version 5.7.0 ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * SPDX-License-Identifier: Zlib * * The licensor of this software is Silicon Laboratories Inc. * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be * appreciated but is not required. * 2. Altered source versions must be plainly marked as such, and must not be * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * ******************************************************************************/ #if defined(__ICCARM__) #pragma system_include /* Treat file as system include file. */ #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang system_header /* Treat file as system include file. */ #endif /***************************************************************************//** * @addtogroup Parts * @{ ******************************************************************************/ /***************************************************************************//** * @brief WDOG_PCH WDOG PCH Register * @ingroup EFR32MG12P_WDOG ******************************************************************************/ typedef struct { __IOM uint32_t PRSCTRL; /**< PRS Control Register */ } WDOG_PCH_TypeDef; /** @} End of group Parts */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/Device/SiliconLabs/EFR32MG12P/Include/em_device.h.
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/***************************************************************************//** * @file * @brief CMSIS Cortex-M Peripheral Access Layer for Silicon Laboratories * microcontroller devices * * This is a convenience header file for defining the part number on the * build command line, instead of specifying the part specific header file. * * @verbatim * Example: Add "-DEFM32G890F128" to your build options, to define part * Add "#include "em_device.h" to your source files * @endverbatim * * @version 5.7.0 ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * SPDX-License-Identifier: Zlib * * The licensor of this software is Silicon Laboratories Inc. * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be * appreciated but is not required. * 2. Altered source versions must be plainly marked as such, and must not be * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * ******************************************************************************/ #ifndef EM_DEVICE_H #define EM_DEVICE_H #if defined(EFR32MG12P132F1024GL125) #include "efr32mg12p132f1024gl125.h" #elif defined(EFR32MG12P132F1024GM48) #include "efr32mg12p132f1024gm48.h" #elif defined(EFR32MG12P132F512GM68) #include "efr32mg12p132f512gm68.h" #elif defined(EFR32MG12P231F1024GM48) #include "efr32mg12p231f1024gm48.h" #elif defined(EFR32MG12P231F1024GM68) #include "efr32mg12p231f1024gm68.h" #elif defined(EFR32MG12P232F1024GL125) #include "efr32mg12p232f1024gl125.h" #elif defined(EFR32MG12P232F1024GM48) #include "efr32mg12p232f1024gm48.h" #elif defined(EFR32MG12P232F1024GM68) #include "efr32mg12p232f1024gm68.h" #elif defined(EFR32MG12P232F512GM68) #include "efr32mg12p232f512gm68.h" #elif defined(EFR32MG12P332F1024GL125) #include "efr32mg12p332f1024gl125.h" #elif defined(EFR32MG12P332F1024GM48) #include "efr32mg12p332f1024gm48.h" #elif defined(EFR32MG12P332F1024IM48) #include "efr32mg12p332f1024im48.h" #elif defined(EFR32MG12P431F1024GM48) #include "efr32mg12p431f1024gm48.h" #elif defined(EFR32MG12P431F1024GM68) #include "efr32mg12p431f1024gm68.h" #elif defined(EFR32MG12P432F1024GL125) #include "efr32mg12p432f1024gl125.h" #elif defined(EFR32MG12P432F1024GM48) #include "efr32mg12p432f1024gm48.h" #elif defined(EFR32MG12P432F1024GM68) #include "efr32mg12p432f1024gm68.h" #elif defined(EFR32MG12P432F1024IM48) #include "efr32mg12p432f1024im48.h" #elif defined(EFR32MG12P433F1024GL125) #include "efr32mg12p433f1024gl125.h" #elif defined(EFR32MG12P433F1024GM48) #include "efr32mg12p433f1024gm48.h" #elif defined(EFR32MG12P433F1024GM68) #include "efr32mg12p433f1024gm68.h" #elif defined(EFR32MG12P433F1024IL125) #include "efr32mg12p433f1024il125.h" #elif defined(EFR32MG12P433F1024IM48) #include "efr32mg12p433f1024im48.h" #else #error "em_device.h: PART NUMBER undefined" #endif #endif /* EM_DEVICE_H */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/Device/SiliconLabs/EFR32MG12P/Include/system_efr32mg12p.h.
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/***************************************************************************//** * @file * @brief CMSIS Cortex-M3/M4 System Layer for EFR32 devices. * @version 5.7.0 ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * SPDX-License-Identifier: Zlib * * The licensor of this software is Silicon Laboratories Inc. * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be * appreciated but is not required. * 2. Altered source versions must be plainly marked as such, and must not be * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * ******************************************************************************/ #ifndef SYSTEM_EFR32_H #define SYSTEM_EFR32_H #ifdef __cplusplus extern "C" { #endif #include <stdint.h> /***************************************************************************//** * @addtogroup Parts * @{ ******************************************************************************/ /***************************************************************************//** * @addtogroup EFR32 EFR32 * @{ ******************************************************************************/ /******************************************************************************* ************************** GLOBAL VARIABLES ******************************* ******************************************************************************/ extern uint32_t SystemCoreClock; /**< System Clock Frequency (Core Clock) */ extern uint32_t SystemHfrcoFreq; /**< System HFRCO frequency */ /******************************************************************************* ***************************** PROTOTYPES ********************************** ******************************************************************************/ void Reset_Handler(void); /**< Reset Handler */ void NMI_Handler(void); /**< NMI Handler */ void HardFault_Handler(void); /**< Hard Fault Handler */ void MemManage_Handler(void); /**< MPU Fault Handler */ void BusFault_Handler(void); /**< Bus Fault Handler */ void UsageFault_Handler(void); /**< Usage Fault Handler */ void SVC_Handler(void); /**< SVCall Handler */ void DebugMon_Handler(void); /**< Debug Monitor Handler */ void PendSV_Handler(void); /**< PendSV Handler */ void SysTick_Handler(void); /**< SysTick Handler */ void EMU_IRQHandler(void); /**< EMU IRQ Handler */ void FRC_PRI_IRQHandler(void); /**< FRC_PRI IRQ Handler */ void WDOG0_IRQHandler(void); /**< WDOG0 IRQ Handler */ void WDOG1_IRQHandler(void); /**< WDOG1 IRQ Handler */ void FRC_IRQHandler(void); /**< FRC IRQ Handler */ void MODEM_IRQHandler(void); /**< MODEM IRQ Handler */ void RAC_SEQ_IRQHandler(void); /**< RAC_SEQ IRQ Handler */ void RAC_RSM_IRQHandler(void); /**< RAC_RSM IRQ Handler */ void BUFC_IRQHandler(void); /**< BUFC IRQ Handler */ void LDMA_IRQHandler(void); /**< LDMA IRQ Handler */ void GPIO_EVEN_IRQHandler(void); /**< GPIO_EVEN IRQ Handler */ void TIMER0_IRQHandler(void); /**< TIMER0 IRQ Handler */ void USART0_RX_IRQHandler(void); /**< USART0_RX IRQ Handler */ void USART0_TX_IRQHandler(void); /**< USART0_TX IRQ Handler */ void ACMP0_IRQHandler(void); /**< ACMP0 IRQ Handler */ void ADC0_IRQHandler(void); /**< ADC0 IRQ Handler */ void IDAC0_IRQHandler(void); /**< IDAC0 IRQ Handler */ void I2C0_IRQHandler(void); /**< I2C0 IRQ Handler */ void GPIO_ODD_IRQHandler(void); /**< GPIO_ODD IRQ Handler */ void TIMER1_IRQHandler(void); /**< TIMER1 IRQ Handler */ void USART1_RX_IRQHandler(void); /**< USART1_RX IRQ Handler */ void USART1_TX_IRQHandler(void); /**< USART1_TX IRQ Handler */ void LEUART0_IRQHandler(void); /**< LEUART0 IRQ Handler */ void PCNT0_IRQHandler(void); /**< PCNT0 IRQ Handler */ void CMU_IRQHandler(void); /**< CMU IRQ Handler */ void MSC_IRQHandler(void); /**< MSC IRQ Handler */ void CRYPTO0_IRQHandler(void); /**< CRYPTO IRQ Handler */ void LETIMER0_IRQHandler(void); /**< LETIMER0 IRQ Handler */ void AGC_IRQHandler(void); /**< AGC IRQ Handler */ void PROTIMER_IRQHandler(void); /**< PROTIMER IRQ Handler */ void RTCC_IRQHandler(void); /**< RTCC IRQ Handler */ void SYNTH_IRQHandler(void); /**< SYNTH IRQ Handler */ void CRYOTIMER_IRQHandler(void); /**< CRYOTIMER IRQ Handler */ void RFSENSE_IRQHandler(void); /**< RFSENSE IRQ Handler */ void FPUEH_IRQHandler(void); /**< FPUEH IRQ Handler */ void SMU_IRQHandler(void); /**< SMU IRQ Handler */ void WTIMER0_IRQHandler(void); /**< WTIMER0 IRQ Handler */ void WTIMER1_IRQHandler(void); /**< WTIMER1 IRQ Handler */ void PCNT1_IRQHandler(void); /**< PCNT1 IRQ Handler */ void PCNT2_IRQHandler(void); /**< PCNT2 IRQ Handler */ void USART2_RX_IRQHandler(void); /**< USART2_RX IRQ Handler */ void USART2_TX_IRQHandler(void); /**< USART2_TX IRQ Handler */ void I2C1_IRQHandler(void); /**< I2C1 IRQ Handler */ void USART3_RX_IRQHandler(void); /**< USART3_RX IRQ Handler */ void USART3_TX_IRQHandler(void); /**< USART3_TX IRQ Handler */ void VDAC0_IRQHandler(void); /**< VDAC0 IRQ Handler */ void CSEN_IRQHandler(void); /**< CSEN IRQ Handler */ void LESENSE_IRQHandler(void); /**< LESENSE IRQ Handler */ void CRYPTO1_IRQHandler(void); /**< CRYPTO1 IRQ Handler */ void TRNG0_IRQHandler(void); /**< TRNG0 IRQ Handler */ void SYSCFG_IRQHandler(void); /**< SYSCFG IRQ Handler */ uint32_t SystemCoreClockGet(void); /***************************************************************************//** * @brief * Update CMSIS SystemCoreClock variable. * * @details * CMSIS defines a global variable SystemCoreClock that shall hold the * core frequency in Hz. If the core frequency is dynamically changed, the * variable must be kept updated in order to be CMSIS compliant. * * Notice that only if changing the core clock frequency through the EFR CMU * API, this variable will be kept updated. This function is only provided * for CMSIS compliance and if a user modifies the the core clock outside * the CMU API. ******************************************************************************/ static __INLINE void SystemCoreClockUpdate(void) { (void)SystemCoreClockGet(); } uint32_t SystemMaxCoreClockGet(void); void SystemInit(void); uint32_t SystemHFClockGet(void); uint32_t SystemHFXOClockGet(void); void SystemHFXOClockSet(uint32_t freq); uint32_t SystemLFRCOClockGet(void); uint32_t SystemULFRCOClockGet(void); uint32_t SystemLFXOClockGet(void); void SystemLFXOClockSet(uint32_t freq); /** @} End of group */ /** @} End of group Parts */ #ifdef __cplusplus } #endif #endif /* SYSTEM_EFR32_H */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/Device/SiliconLabs/EFR32MG12P/Source/GCC/startup_efr32mg12p.c.
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/***************************************************************************//** * @file * @brief CMSIS Compatible EFR32MG12P startup file in C. * Should be used with GCC 'GNU Tools ARM Embedded' * @version 5.7.0 ******************************************************************************* * # License * * The licensor of this software is Silicon Laboratories Inc. Your use of this * software is governed by the terms of Silicon Labs Master Software License * Agreement (MSLA) available at * www.silabs.com/about-us/legal/master-software-license-agreement. This * software is Third Party Software licensed by Silicon Labs from a third party * and is governed by the sections of the MSLA applicable to Third Party * Software and the additional terms set forth below. * ******************************************************************************/ /* * Copyright (c) 2009-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #include <stdint.h> #include <stdbool.h> /*---------------------------------------------------------------------------- * Linker generated Symbols *----------------------------------------------------------------------------*/ extern uint32_t __etext; extern uint32_t __data_start__; extern uint32_t __data_end__; extern uint32_t __copy_table_start__; extern uint32_t __copy_table_end__; extern uint32_t __zero_table_start__; extern uint32_t __zero_table_end__; extern uint32_t __bss_start__; extern uint32_t __bss_end__; extern uint32_t __StackTop; /*---------------------------------------------------------------------------- * Exception / Interrupt Handler Function Prototype *----------------------------------------------------------------------------*/ typedef union { void (*pFunc)(void); void *topOfStack; } tVectorEntry; /*---------------------------------------------------------------------------- * External References *----------------------------------------------------------------------------*/ #ifndef __START extern void _start(void) __attribute__((noreturn)); /* Pre Main (C library entry point) */ #else extern int __START(void) __attribute__((noreturn)); /* main entry point */ #endif #ifndef __NO_SYSTEM_INIT extern void SystemInit(void); /* CMSIS System Initialization */ #endif /*---------------------------------------------------------------------------- * Internal References *----------------------------------------------------------------------------*/ void Default_Handler(void); /* Default empty handler */ void Reset_Handler(void); /* Reset Handler */ /*---------------------------------------------------------------------------- * User Initial Stack & Heap *----------------------------------------------------------------------------*/ #ifndef __STACK_SIZE #define __STACK_SIZE 0x00000400 #endif static uint8_t stack[__STACK_SIZE] __attribute__ ((aligned(8), used, section(".stack"))); #ifndef __HEAP_SIZE #define __HEAP_SIZE 0x00000C00 #endif #if __HEAP_SIZE > 0 static uint8_t heap[__HEAP_SIZE] __attribute__ ((aligned(8), used, section(".heap"))); #endif /*---------------------------------------------------------------------------- * Exception / Interrupt Handler *----------------------------------------------------------------------------*/ /* Cortex-M Processor Exceptions */ void NMI_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); void HardFault_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); void MemManage_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); void BusFault_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); void UsageFault_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); void DebugMon_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); void SVC_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); void PendSV_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); void SysTick_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); /* Part Specific Interrupts */ void EMU_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); void FRC_PRI_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); void WDOG0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); void WDOG1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); void FRC_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); void MODEM_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); void RAC_SEQ_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); void RAC_RSM_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); void BUFC_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); void LDMA_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); void GPIO_EVEN_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); void TIMER0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); void USART0_RX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); void USART0_TX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); void ACMP0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); void ADC0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); void IDAC0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); void I2C0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); void GPIO_ODD_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); void TIMER1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); void USART1_RX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); void USART1_TX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); void LEUART0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); void PCNT0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); void CMU_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); void MSC_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); void CRYPTO0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); void LETIMER0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); void AGC_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); void PROTIMER_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); void RTCC_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); void SYNTH_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); void CRYOTIMER_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); void RFSENSE_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); void FPUEH_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); void SMU_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); void WTIMER0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); void WTIMER1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); void PCNT1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); void PCNT2_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); void USART2_RX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); void USART2_TX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); void I2C1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); void USART3_RX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); void USART3_TX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); void VDAC0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); void CSEN_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); void LESENSE_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); void CRYPTO1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); void TRNG0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /*---------------------------------------------------------------------------- * Exception / Interrupt Vector table *----------------------------------------------------------------------------*/ extern const tVectorEntry __Vectors[]; const tVectorEntry __Vectors[] __attribute__ ((section(".vectors"))) = { /* Cortex-M Exception Handlers */ { .topOfStack = &__StackTop }, /* Initial Stack Pointer */ { Reset_Handler }, /* Reset Handler */ { NMI_Handler }, /* NMI Handler */ { HardFault_Handler }, /* Hard Fault Handler */ { MemManage_Handler }, /* MPU Fault Handler */ { BusFault_Handler }, /* Bus Fault Handler */ { UsageFault_Handler }, /* Usage Fault Handler */ { Default_Handler }, /* Reserved */ { Default_Handler }, /* Reserved */ { Default_Handler }, /* Reserved */ { Default_Handler }, /* Reserved */ { SVC_Handler }, /* SVCall Handler */ { DebugMon_Handler }, /* Debug Monitor Handler */ { Default_Handler }, /* Reserved */ { PendSV_Handler }, /* PendSV Handler */ { SysTick_Handler }, /* SysTick Handler */ /* External interrupts */ { EMU_IRQHandler }, /* 0 */ { FRC_PRI_IRQHandler }, /* 1 */ { WDOG0_IRQHandler }, /* 2 */ { WDOG1_IRQHandler }, /* 3 */ { FRC_IRQHandler }, /* 4 */ { MODEM_IRQHandler }, /* 5 */ { RAC_SEQ_IRQHandler }, /* 6 */ { RAC_RSM_IRQHandler }, /* 7 */ { BUFC_IRQHandler }, /* 8 */ { LDMA_IRQHandler }, /* 9 */ { GPIO_EVEN_IRQHandler }, /* 10 */ { TIMER0_IRQHandler }, /* 11 */ { USART0_RX_IRQHandler }, /* 12 */ { USART0_TX_IRQHandler }, /* 13 */ { ACMP0_IRQHandler }, /* 14 */ { ADC0_IRQHandler }, /* 15 */ { IDAC0_IRQHandler }, /* 16 */ { I2C0_IRQHandler }, /* 17 */ { GPIO_ODD_IRQHandler }, /* 18 */ { TIMER1_IRQHandler }, /* 19 */ { USART1_RX_IRQHandler }, /* 20 */ { USART1_TX_IRQHandler }, /* 21 */ { LEUART0_IRQHandler }, /* 22 */ { PCNT0_IRQHandler }, /* 23 */ { CMU_IRQHandler }, /* 24 */ { MSC_IRQHandler }, /* 25 */ { CRYPTO0_IRQHandler }, /* 26 */ { LETIMER0_IRQHandler }, /* 27 */ { AGC_IRQHandler }, /* 28 */ { PROTIMER_IRQHandler }, /* 29 */ { RTCC_IRQHandler }, /* 30 */ { SYNTH_IRQHandler }, /* 31 */ { CRYOTIMER_IRQHandler }, /* 32 */ { RFSENSE_IRQHandler }, /* 33 */ { FPUEH_IRQHandler }, /* 34 */ { SMU_IRQHandler }, /* 35 */ { WTIMER0_IRQHandler }, /* 36 */ { WTIMER1_IRQHandler }, /* 37 */ { PCNT1_IRQHandler }, /* 38 */ { PCNT2_IRQHandler }, /* 39 */ { USART2_RX_IRQHandler }, /* 40 */ { USART2_TX_IRQHandler }, /* 41 */ { I2C1_IRQHandler }, /* 42 */ { USART3_RX_IRQHandler }, /* 43 */ { USART3_TX_IRQHandler }, /* 44 */ { VDAC0_IRQHandler }, /* 45 */ { CSEN_IRQHandler }, /* 46 */ { LESENSE_IRQHandler }, /* 47 */ { CRYPTO1_IRQHandler }, /* 48 */ { TRNG0_IRQHandler }, /* 49 */ { Default_Handler }, /* 50 - Reserved */ }; /*---------------------------------------------------------------------------- * Reset Handler called on controller reset *----------------------------------------------------------------------------*/ void Reset_Handler(void) { uint32_t *pSrc, *pDest; uint32_t start, end; uint32_t tableStart __attribute__((unused)); uint32_t tableEnd __attribute__((unused)); #ifndef __NO_SYSTEM_INIT SystemInit(); #endif /* Firstly it copies data from read only memory to RAM. There are two schemes * to copy. One can copy more than one sections. Another can only copy * one section. The former scheme needs more instructions and read-only * data to implement than the latter. * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */ #ifdef __STARTUP_COPY_MULTIPLE /* Multiple sections scheme. * * Between symbol address __copy_table_start__ and __copy_table_end__, * there are array of triplets, each of which specify: * offset 0: LMA of start of a section to copy from * offset 4: VMA of start of a section to copy to * offset 8: size of the section to copy. Must be multiply of 4 * * All addresses must be aligned to 4 bytes boundary. */ tableStart = (uint32_t) &__copy_table_start__; tableEnd = (uint32_t) &__copy_table_end__; for (; tableStart < tableEnd; tableStart += 12U) { pSrc = (uint32_t *) (*(uint32_t *) tableStart); start = *(uint32_t *) (tableStart + 4U); end = *(uint32_t *) (tableStart + 8U) + start; pDest = (uint32_t *) start; for (; start < end; start += 4U) { *pDest++ = *pSrc++; } } #else /* Single section scheme. * * The ranges of copy from/to are specified by following symbols * __etext: LMA of start of the section to copy from. Usually end of text * __data_start__: VMA of start of the section to copy to * __data_end__: VMA of end of the section to copy to * * All addresses must be aligned to 4 bytes boundary. */ pSrc = &__etext; pDest = &__data_start__; start = (uint32_t) &__data_start__; end = (uint32_t) &__data_end__; for (; start < end; start += 4U) { *pDest++ = *pSrc++; } #endif /*__STARTUP_COPY_MULTIPLE */ /* This part of work usually is done in C library startup code. Otherwise, * define this macro to enable it in this startup. * * There are two schemes too. One can clear multiple BSS sections. Another * can only clear one section. The former is more size expensive than the * latter. * * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later. */ #ifdef __STARTUP_CLEAR_BSS_MULTIPLE /* Multiple sections scheme. * * Between symbol address __zero_table_start__ and __zero_table_end__, * there are array of tuples specifying: * offset 0: Start of a BSS section * offset 4: Size of this BSS section. Must be multiply of 4 */ tableStart = (uint32_t) &__zero_table_start__; tableEnd = (uint32_t) &__zero_table_end__; for (; tableStart < tableEnd; tableStart += 8U) { start = *(uint32_t *) tableStart; end = *(uint32_t *) (tableStart + 4U) + start; pDest = (uint32_t *) start; for (; start < end; start += 4U) { *pDest++ = 0UL; } } #elif defined (__STARTUP_CLEAR_BSS) /* Single BSS section scheme. * * The BSS section is specified by following symbols * __bss_start__: start of the BSS section. * __bss_end__: end of the BSS section. * * Both addresses must be aligned to 4 bytes boundary. */ pDest = &__bss_start__; start = (uint32_t) &__bss_start__; end = (uint32_t) &__bss_end__; for (; start < end; start += 4U) { *pDest++ = 0UL; } #endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */ #ifndef __START #define __START _start #endif __START(); } /*---------------------------------------------------------------------------- * Default Handler for Exceptions / Interrupts *----------------------------------------------------------------------------*/ void Default_Handler(void) { while (true) { } } |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/Device/SiliconLabs/EFR32MG12P/Source/system_efr32mg12p.c.
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/***************************************************************************//** * @file * @brief CMSIS Cortex-M3/M4 System Layer for EFR32 devices. * @version 5.7.0 ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * SPDX-License-Identifier: Zlib * * The licensor of this software is Silicon Laboratories Inc. * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be * appreciated but is not required. * 2. Altered source versions must be plainly marked as such, and must not be * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * ******************************************************************************/ #include <stdint.h> #include "em_device.h" /******************************************************************************* ****************************** DEFINES ************************************ ******************************************************************************/ /** LFRCO frequency, tuned to below frequency during manufacturing. */ #define EFR32_LFRCO_FREQ (32768UL) /** ULFRCO frequency */ #define EFR32_ULFRCO_FREQ (1000UL) /******************************************************************************* ************************** LOCAL VARIABLES ******************************** ******************************************************************************/ /* System oscillator frequencies. These frequencies are normally constant */ /* for a target, but they are made configurable in order to allow run-time */ /* handling of different boards. The crystal oscillator clocks can be set */ /* compile time to a non-default value by defining respective EFR32_nFXO_FREQ */ /* values according to board design. By defining the EFR32_nFXO_FREQ to 0, */ /* one indicates that the oscillator is not present, in order to save some */ /* SW footprint. */ #ifndef EFR32_HFRCO_MAX_FREQ /** Maximum HFRCO frequency */ #define EFR32_HFRCO_MAX_FREQ (38000000UL) #endif #ifndef EFR32_HFXO_FREQ /** HFXO frequency */ #define EFR32_HFXO_FREQ (38400000UL) #endif #ifndef EFR32_HFRCO_STARTUP_FREQ /** HFRCO startup frequency */ #define EFR32_HFRCO_STARTUP_FREQ (19000000UL) #endif /* Do not define variable if HF crystal oscillator not present */ #if (EFR32_HFXO_FREQ > 0U) /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ /** System HFXO clock. */ static uint32_t SystemHFXOClock = EFR32_HFXO_FREQ; /** @endcond (DO_NOT_INCLUDE_WITH_DOXYGEN) */ #endif #ifndef EFR32_LFXO_FREQ /** LFXO frequency */ #define EFR32_LFXO_FREQ (EFR32_LFRCO_FREQ) #endif /* Do not define variable if LF crystal oscillator not present */ #if (EFR32_LFXO_FREQ > 0U) /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ /** System LFXO clock. */ static uint32_t SystemLFXOClock = EFR32_LFXO_FREQ; /** @endcond (DO_NOT_INCLUDE_WITH_DOXYGEN) */ #endif /******************************************************************************* ************************** GLOBAL VARIABLES ******************************* ******************************************************************************/ /** * @brief * System System Clock Frequency (Core Clock). * * @details * Required CMSIS global variable that must be kept up-to-date. */ uint32_t SystemCoreClock = EFR32_HFRCO_STARTUP_FREQ; /** * @brief * System HFRCO frequency * * @note * This is an EFR32 proprietary variable, not part of the CMSIS definition. * * @details * Frequency of the system HFRCO oscillator */ uint32_t SystemHfrcoFreq = EFR32_HFRCO_STARTUP_FREQ; /******************************************************************************* ************************** GLOBAL FUNCTIONS ******************************* ******************************************************************************/ #if defined(__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) #if defined(__ICCARM__) /* IAR requires the __vector_table symbol */ #define __Vectors __vector_table #endif extern uint32_t __Vectors; #endif /***************************************************************************//** * @brief * Get the current core clock frequency. * * @details * Calculate and get the current core clock frequency based on the current * configuration. Assuming that the SystemCoreClock global variable is * maintained, the core clock frequency is stored in that variable as well. * This function will however calculate the core clock based on actual HW * configuration. It will also update the SystemCoreClock global variable. * * @note * This is an EFR32 proprietary function, not part of the CMSIS definition. * * @return * The current core clock frequency in Hz. ******************************************************************************/ uint32_t SystemCoreClockGet(void) { uint32_t ret; uint32_t presc; ret = SystemHFClockGet(); presc = (CMU->HFCOREPRESC & _CMU_HFCOREPRESC_PRESC_MASK) >> _CMU_HFCOREPRESC_PRESC_SHIFT; ret /= presc + 1U; /* Keep CMSIS system clock variable up-to-date */ SystemCoreClock = ret; return ret; } /***************************************************************************//** * @brief * Get the maximum core clock frequency. * * @note * This is an EFR32 proprietary function, not part of the CMSIS definition. * * @return * The maximum core clock frequency in Hz. ******************************************************************************/ uint32_t SystemMaxCoreClockGet(void) { #if (EFR32_HFRCO_MAX_FREQ > EFR32_HFXO_FREQ) return EFR32_HFRCO_MAX_FREQ; #else return EFR32_HFXO_FREQ; #endif } /***************************************************************************//** * @brief * Get the current HFCLK frequency. * * @note * This is an EFR proprietary function, not part of the CMSIS definition. * * @return * The current HFCLK frequency in Hz. ******************************************************************************/ uint32_t SystemHFClockGet(void) { uint32_t ret; switch (CMU->HFCLKSTATUS & _CMU_HFCLKSTATUS_SELECTED_MASK) { case CMU_HFCLKSTATUS_SELECTED_LFXO: #if (EFR32_LFXO_FREQ > 0U) ret = SystemLFXOClock; #else /* We should not get here, since core should not be clocked. May */ /* be caused by a misconfiguration though. */ ret = 0U; #endif break; case CMU_HFCLKSTATUS_SELECTED_LFRCO: ret = EFR32_LFRCO_FREQ; break; case CMU_HFCLKSTATUS_SELECTED_HFXO: #if (EFR32_HFXO_FREQ > 0U) ret = SystemHFXOClock; #else /* We should not get here, since core should not be clocked. May */ /* be caused by a misconfiguration though. */ ret = 0U; #endif break; default: /* CMU_HFCLKSTATUS_SELECTED_HFRCO */ ret = SystemHfrcoFreq; break; } return ret / (1U + ((CMU->HFPRESC & _CMU_HFPRESC_PRESC_MASK) >> _CMU_HFPRESC_PRESC_SHIFT)); } /***************************************************************************//** * @brief * Get high frequency crystal oscillator clock frequency for target system. * * @note * This is an EFR proprietary function, not part of the CMSIS definition. * * @return * HFXO frequency in Hz. ******************************************************************************/ uint32_t SystemHFXOClockGet(void) { /* External crystal oscillator present? */ #if (EFR32_HFXO_FREQ > 0U) return SystemHFXOClock; #else return 0U; #endif } /***************************************************************************//** * @brief * Set high frequency crystal oscillator clock frequency for target system. * * @note * This function is mainly provided for being able to handle target systems * with different HF crystal oscillator frequencies run-time. If used, it * should probably only be used once during system startup. * * @note * This is an EFR proprietary function, not part of the CMSIS definition. * * @param[in] freq * HFXO frequency in Hz used for target. ******************************************************************************/ void SystemHFXOClockSet(uint32_t freq) { /* External crystal oscillator present? */ #if (EFR32_HFXO_FREQ > 0U) SystemHFXOClock = freq; /* Update core clock frequency if HFXO is used to clock core */ if ((CMU->HFCLKSTATUS & _CMU_HFCLKSTATUS_SELECTED_MASK) == CMU_HFCLKSTATUS_SELECTED_HFXO) { /* The function will update the global variable */ (void)SystemCoreClockGet(); } #else (void)freq; /* Unused parameter */ #endif } /***************************************************************************//** * @brief * Initialize the system. * * @details * Do required generic HW system init. * * @note * This function is invoked during system init, before the main() routine * and any data has been initialized. For this reason, it cannot do any * initialization of variables etc. ******************************************************************************/ void SystemInit(void) { #if defined(__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) SCB->VTOR = (uint32_t)&__Vectors; #endif #if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) /* Set floating point coprosessor access mode. */ SCB->CPACR |= ((3UL << 10 * 2) /* set CP10 Full Access */ | (3UL << 11 * 2)); /* set CP11 Full Access */ #endif #if defined(UNALIGNED_SUPPORT_DISABLE) SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; #endif } /***************************************************************************//** * @brief * Get low frequency RC oscillator clock frequency for target system. * * @note * This is an EFR proprietary function, not part of the CMSIS definition. * * @return * LFRCO frequency in Hz. ******************************************************************************/ uint32_t SystemLFRCOClockGet(void) { /* Currently we assume that this frequency is properly tuned during */ /* manufacturing and is not changed after reset. If future requirements */ /* for re-tuning by user, we can add support for that. */ return EFR32_LFRCO_FREQ; } /***************************************************************************//** * @brief * Get ultra low frequency RC oscillator clock frequency for target system. * * @note * This is an EFR proprietary function, not part of the CMSIS definition. * * @return * ULFRCO frequency in Hz. ******************************************************************************/ uint32_t SystemULFRCOClockGet(void) { /* The ULFRCO frequency is not tuned, and can be very inaccurate */ return EFR32_ULFRCO_FREQ; } /***************************************************************************//** * @brief * Get low frequency crystal oscillator clock frequency for target system. * * @note * This is an EFR proprietary function, not part of the CMSIS definition. * * @return * LFXO frequency in Hz. ******************************************************************************/ uint32_t SystemLFXOClockGet(void) { /* External crystal oscillator present? */ #if (EFR32_LFXO_FREQ > 0U) return SystemLFXOClock; #else return 0U; #endif } /***************************************************************************//** * @brief * Set low frequency crystal oscillator clock frequency for target system. * * @note * This function is mainly provided for being able to handle target systems * with different HF crystal oscillator frequencies run-time. If used, it * should probably only be used once during system startup. * * @note * This is an EFR proprietary function, not part of the CMSIS definition. * * @param[in] freq * LFXO frequency in Hz used for target. ******************************************************************************/ void SystemLFXOClockSet(uint32_t freq) { /* External crystal oscillator present? */ #if (EFR32_LFXO_FREQ > 0U) SystemLFXOClock = freq; /* Update core clock frequency if LFXO is used to clock core */ if ((CMU->HFCLKSTATUS & _CMU_HFCLKSTATUS_SELECTED_MASK) == CMU_HFCLKSTATUS_SELECTED_LFXO) { /* The function will update the global variable */ (void)SystemCoreClockGet(); } #else (void)freq; /* Unused parameter */ #endif } |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/bootloader/api/application_properties.h.
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/***************************************************************************//** * @file * @brief Representation of Application Properties ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * The licensor of this software is Silicon Laboratories Inc. Your use of this * software is governed by the terms of Silicon Labs Master Software License * Agreement (MSLA) available at * www.silabs.com/about-us/legal/master-software-license-agreement. This * software is distributed to you in Source Code format and is governed by the * sections of the MSLA applicable to Source Code. * ******************************************************************************/ #ifndef APPLICATION_PROPERTIES_H #define APPLICATION_PROPERTIES_H #include <stdint.h> /***************************************************************************//** * @addtogroup Interface * @{ * @addtogroup ApplicationProperties Application Properties * @brief Properties of the application that can be accessed by the bootloader * @details * Applications must contain an @ref ApplicationProperties_t struct declaring * the application version and capabilities, etc. The metadata contained in * this struct will be extracted from the application by the Simplicity * Commander tool and placed in the EBL upgrade file. If such a struct is not * present in the application image, it will be added to the EBL file by the * Simplicity Commander. * * The struct is also used to declare whether the application image is signed, * and what type of signature is used. If no @ref ApplicationProperties_t * struct is present, the bootloader will assume that the application image * is signed using @ref APPLICATION_SIGNATURE_ECDSA_P256. * * In order for the bootloader to easily locate the ApplicationProperties_t * struct, if not already done by the linker, Simplicity Commander will modify * word 13 of the application to insert a pointer to the * ApplicationProperties_t struct. * @{ ******************************************************************************/ /// Magic value declaring the existence of an ApplicationProperties_t struct #define APPLICATION_PROPERTIES_MAGIC { \ 0x13, 0xb7, 0x79, 0xfa, \ 0xc9, 0x25, 0xdd, 0xb7, \ 0xad, 0xf3, 0xcf, 0xe0, \ 0xf1, 0xb6, 0x14, 0xb8 \ } /// Byte-reversed version of ::APPLICATION_PROPERTIES_MAGIC #define APPLICATION_PROPERTIES_REVERSED { \ 0xb8, 0x14, 0xb6, 0xf1, \ 0xe0, 0xcf, 0xf3, 0xad, \ 0xb7, 0xdd, 0x25, 0xc9, \ 0xfa, 0x79, 0xb7, 0x13 \ } /// Version number of the AppliationProperties_t struct #define APPLICATION_PROPERTIES_VERSION 0x00000101 /// The application is not signed #define APPLICATION_SIGNATURE_NONE (0UL) /// @brief The SHA-256 digest of the application is signed using ECDSA with the /// NIST P-256 curve #define APPLICATION_SIGNATURE_ECDSA_P256 (1UL << 0UL) /// @brief The application is not signed, but has a CRC-32 checksum #define APPLICATION_SIGNATURE_CRC32 (1UL << 1UL) /// The application contains a Zigbee wireless stack #define APPLICATION_TYPE_ZIGBEE (1UL << 0UL) /// The application contains a Thread wireless stack #define APPLICATION_TYPE_THREAD (1UL << 1UL) /// The application contains a Flex wireless stack #define APPLICATION_TYPE_FLEX (1UL << 2UL) /// The application contains a Bluetooth wireless stack #define APPLICATION_TYPE_BLUETOOTH (1UL << 3UL) /// The application is an MCU application #define APPLICATION_TYPE_MCU (1UL << 4UL) /// The application contains a Bluetooth application #define APPLICATION_TYPE_BLUETOOTH_APP (1UL << 5UL) /// The application contains a bootloader #define APPLICATION_TYPE_BOOTLOADER (1UL << 6UL) /// Application Data typedef struct ApplicationData { /// @brief Bitfield representing type of application, e.g. /// @ref APPLICATION_TYPE_ZIGBEE uint32_t type; /// Version number for this application uint32_t version; /// Capabilities of this application uint32_t capabilities; /// Unique ID (UUID or GUID) for the product this application is built for uint8_t productId[16]; } ApplicationData_t; /// Application Certificate typedef struct ApplicationCertificate { /// Version of the certificate structure uint8_t structVersion; /// Reserved flags uint8_t flags[3]; /// Public key uint8_t key[64]; /// The version number of this certificate uint32_t version; /// Signature of the certificate uint8_t signature[64]; } ApplicationCertificate_t; /// Application Properties struct typedef struct { /// @brief Magic value indicating this is an ApplicationProperties_t struct. /// Must equal @ref APPLICATION_PROPERTIES_MAGIC uint8_t magic[16]; /// Version number of this struct uint32_t structVersion; /// Type of signature this application is signed with uint32_t signatureType; /// Location of the signature. Typically points to the end of the application uint32_t signatureLocation; /// Information about the application ApplicationData_t app; /// Pointer to information about the certificate ApplicationCertificate_t *cert; /// Pointer to Long Token Data Section uint8_t *longTokenSectionAddress; } ApplicationProperties_t; /** @} // addtogroup ApplicationProperties */ /** @} // addtogroup Interface */ #endif // APPLICATION_PROPERTIES_H |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/emdrv/common/inc/ecode.h.
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/***************************************************************************//** * @file * @brief Energy Aware drivers error code definitions. ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * The licensor of this software is Silicon Laboratories Inc. Your use of this * software is governed by the terms of Silicon Labs Master Software License * Agreement (MSLA) available at * www.silabs.com/about-us/legal/master-software-license-agreement. This * software is distributed to you in Source Code format and is governed by the * sections of the MSLA applicable to Source Code. * ******************************************************************************/ #ifndef __SILICON_LABS_ECODE_H__ #define __SILICON_LABS_ECODE_H__ #include <stdint.h> /***************************************************************************//** * @defgroup emdrv EMDRV * @brief Gecko Platform driver library * @details * * EMDRV is a set of function specific high performance drivers for EFM32, EZR32 * and EFR32 on-chip peripherals. Drivers are typically DMA based and are using * all available low-energy features. For most drivers, the API offers both * synchronous and asynchronous functions. The APIs are fully reentrant and * callback based. * * Most drivers are compile-time configurable to allow the highest possible * code size optimization for the application. Compile-time configuration is * defined in *_config.h files. Templates for the configuration files can be * found in emdrv\\<driver>\\config. * * @note * EMDRV APIs use @ref Ecode_t to return status. * @n @n * With the exception of ezradiodrv, EMDRV does not implement RF support. * Please refer to stack documentation for more information. * * @{ ******************************************************************************/ /***************************************************************************//** * @brief Typedef for API function error code return values. * * @details * Bit 24-31: Component, for example @ref emdrv @n * Bit 16-23: Module, for example @ref UARTDRV or @ref RTCDRV @n * Bit 0-15: Error code ******************************************************************************/ typedef uint32_t Ecode_t; #define ECODE_EMDRV_BASE (0xF0000000U) ///< Base value for all EMDRV errorcodes. #define ECODE_OK (0U) ///< Generic success return value. #define ECODE_EMDRV_RTCDRV_BASE (ECODE_EMDRV_BASE | 0x00001000U) ///< Base value for RTCDRV error codes. #define ECODE_EMDRV_SPIDRV_BASE (ECODE_EMDRV_BASE | 0x00002000U) ///< Base value for SPIDRV error codes. #define ECODE_EMDRV_NVM_BASE (ECODE_EMDRV_BASE | 0x00003000U) ///< Base value for NVM error codes. #define ECODE_EMDRV_USTIMER_BASE (ECODE_EMDRV_BASE | 0x00004000U) ///< Base value for USTIMER error codes. #define ECODE_EMDRV_UARTDRV_BASE (ECODE_EMDRV_BASE | 0x00007000U) ///< Base value for UARTDRV error codes. #define ECODE_EMDRV_DMADRV_BASE (ECODE_EMDRV_BASE | 0x00008000U) ///< Base value for DMADRV error codes. #define ECODE_EMDRV_EZRADIODRV_BASE (ECODE_EMDRV_BASE | 0x00009000U) ///< Base value for EZRADIODRV error codes. #define ECODE_EMDRV_TEMPDRV_BASE (ECODE_EMDRV_BASE | 0x0000D000U) ///< Base value for TEMPDRV error codes. #define ECODE_EMDRV_NVM3_BASE (ECODE_EMDRV_BASE | 0x0000E000U) ///< Base value for NVM3 error codes. /** @} (end addtogroup emdrv) */ #endif // __SILICON_LABS_ECODE_H__ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/emdrv/dmadrv/inc/dmadrv.h.
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/***************************************************************************//** * @file * @brief DMADRV API definition. ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * The licensor of this software is Silicon Laboratories Inc. Your use of this * software is governed by the terms of Silicon Labs Master Software License * Agreement (MSLA) available at * www.silabs.com/about-us/legal/master-software-license-agreement. This * software is distributed to you in Source Code format and is governed by the * sections of the MSLA applicable to Source Code. * ******************************************************************************/ #ifndef __SILICON_LABS_DMADRV_H__ #define __SILICON_LABS_DMADRV_H__ #include "em_device.h" #include "ecode.h" #if defined(DMA_PRESENT) && (DMA_COUNT == 1) #define EMDRV_DMADRV_UDMA #define EMDRV_DMADRV_DMA_PRESENT #include "em_dma.h" #elif defined(LDMA_PRESENT) && (LDMA_COUNT == 1) #define EMDRV_DMADRV_LDMA #define EMDRV_DMADRV_DMA_PRESENT #include "em_ldma.h" #else #error "No valid DMA engine defined." #endif #include "dmadrv_config.h" #ifdef __cplusplus extern "C" { #endif /***************************************************************************//** * @addtogroup emdrv * @{ ******************************************************************************/ /***************************************************************************//** * @addtogroup DMADRV * @{ ******************************************************************************/ #define ECODE_EMDRV_DMADRV_OK (ECODE_OK) ///< A successful return value. #define ECODE_EMDRV_DMADRV_PARAM_ERROR (ECODE_EMDRV_DMADRV_BASE | 0x00000001) ///< An illegal input parameter. #define ECODE_EMDRV_DMADRV_NOT_INITIALIZED (ECODE_EMDRV_DMADRV_BASE | 0x00000002) ///< DMA is not initialized. #define ECODE_EMDRV_DMADRV_ALREADY_INITIALIZED (ECODE_EMDRV_DMADRV_BASE | 0x00000003) ///< DMA has already been initialized. #define ECODE_EMDRV_DMADRV_CHANNELS_EXHAUSTED (ECODE_EMDRV_DMADRV_BASE | 0x00000004) ///< No DMA channels available. #define ECODE_EMDRV_DMADRV_IN_USE (ECODE_EMDRV_DMADRV_BASE | 0x00000005) ///< DMA is in use. #define ECODE_EMDRV_DMADRV_ALREADY_FREED (ECODE_EMDRV_DMADRV_BASE | 0x00000006) ///< A DMA channel was free. #define ECODE_EMDRV_DMADRV_CH_NOT_ALLOCATED (ECODE_EMDRV_DMADRV_BASE | 0x00000007) ///< A channel is not reserved. /***************************************************************************//** * @brief * DMADRV transfer completion callback function. * * @details * The callback function is called when a transfer is complete. * * @param[in] channel * The DMA channel number. * * @param[in] sequenceNo * The number of times the callback was called. Useful on long chains of * linked transfers or on endless ping-pong type transfers. * * @param[in] userParam * Optional user parameter supplied on DMA invocation. * * @return * When doing ping-pong transfers, return true to continue or false to * stop transfers. ******************************************************************************/ typedef bool (*DMADRV_Callback_t)(unsigned int channel, unsigned int sequenceNo, void *userParam); #if defined(DMA_PRESENT) && (DMA_COUNT == 1) /// Maximum length of one DMA transfer. #define DMADRV_MAX_XFER_COUNT ((int)((_DMA_CTRL_N_MINUS_1_MASK >> _DMA_CTRL_N_MINUS_1_SHIFT) + 1)) /// Peripherals that can trigger UDMA transfers. typedef enum { dmadrvPeripheralSignal_NONE = 0, ///< No peripheral selected for DMA triggering. #if defined(DMAREQ_ADC0_SCAN) dmadrvPeripheralSignal_ADC0_SCAN = DMAREQ_ADC0_SCAN, ///< Trig on ADC0_SCAN. #endif #if defined(DMAREQ_ADC0_SINGLE) dmadrvPeripheralSignal_ADC0_SINGLE = DMAREQ_ADC0_SINGLE, ///< Trig on ADC0_SINGLE. #endif #if defined(DMAREQ_AES_DATARD) dmadrvPeripheralSignal_AES_DATARD = DMAREQ_AES_DATARD, ///< Trig on AES_DATARD. #endif #if defined(DMAREQ_AES_DATAWR) dmadrvPeripheralSignal_AES_DATAWR = DMAREQ_AES_DATAWR, ///< Trig on AES_DATAWR. #endif #if defined(DMAREQ_AES_KEYWR) dmadrvPeripheralSignal_AES_KEYWR = DMAREQ_AES_KEYWR, ///< Trig on AES_KEYWR. #endif #if defined(DMAREQ_AES_XORDATAWR) dmadrvPeripheralSignal_AES_XORDATAWR = DMAREQ_AES_XORDATAWR, ///< Trig on AES_XORDATAWR. #endif #if defined(DMAREQ_DAC0_CH0) dmadrvPeripheralSignal_DAC0_CH0 = DMAREQ_DAC0_CH0, ///< Trig on DAC0_CH0. #endif #if defined(DMAREQ_DAC0_CH1) dmadrvPeripheralSignal_DAC0_CH1 = DMAREQ_DAC0_CH1, ///< Trig on DAC0_CH1. #endif #if defined(DMAREQ_EBI_DDEMPTY) dmadrvPeripheralSignal_EBI_DDEMPTY = DMAREQ_EBI_DDEMPTY, ///< Trig on EBI_DDEMPTY. #endif #if defined(DMAREQ_EBI_PXL0EMPTY) dmadrvPeripheralSignal_EBI_PXL0EMPTY = DMAREQ_EBI_PXL0EMPTY, ///< Trig on EBI_PXL0EMPTY. #endif #if defined(DMAREQ_EBI_PXL1EMPTY) dmadrvPeripheralSignal_EBI_PXL1EMPTY = DMAREQ_EBI_PXL1EMPTY, ///< Trig on EBI_PXL1EMPTY. #endif #if defined(DMAREQ_EBI_PXLFULL) dmadrvPeripheralSignal_EBI_PXLFULL = DMAREQ_EBI_PXLFULL, ///< Trig on EBI_PXLFULL. #endif #if defined(DMAREQ_I2C0_RXDATAV) dmadrvPeripheralSignal_I2C0_RXDATAV = DMAREQ_I2C0_RXDATAV, ///< Trig on I2C0_RXDATAV. #endif #if defined(DMAREQ_I2C0_TXBL) dmadrvPeripheralSignal_I2C0_TXBL = DMAREQ_I2C0_TXBL, ///< Trig on I2C0_TXBL. #endif #if defined(DMAREQ_I2C1_RXDATAV) dmadrvPeripheralSignal_I2C1_RXDATAV = DMAREQ_I2C1_RXDATAV, ///< Trig on I2C1_RXDATAV. #endif #if defined(DMAREQ_I2C1_TXBL) dmadrvPeripheralSignal_I2C1_TXBL = DMAREQ_I2C1_TXBL, ///< Trig on I2C1_TXBL. #endif #if defined(DMAREQ_LESENSE_BUFDATAV) dmadrvPeripheralSignal_LESENSE_BUFDATAV = DMAREQ_LESENSE_BUFDATAV, ///< Trig on LESENSE_BUFDATAV. #endif #if defined(DMAREQ_LEUART0_RXDATAV) dmadrvPeripheralSignal_LEUART0_RXDATAV = DMAREQ_LEUART0_RXDATAV, ///< Trig on LEUART0_RXDATAV. #endif #if defined(DMAREQ_LEUART0_TXBL) dmadrvPeripheralSignal_LEUART0_TXBL = DMAREQ_LEUART0_TXBL, ///< Trig on LEUART0_TXBL. #endif #if defined(DMAREQ_LEUART0_TXEMPTY) dmadrvPeripheralSignal_LEUART0_TXEMPTY = DMAREQ_LEUART0_TXEMPTY, ///< Trig on LEUART0_TXEMPTY. #endif #if defined(DMAREQ_LEUART1_RXDATAV) dmadrvPeripheralSignal_LEUART1_RXDATAV = DMAREQ_LEUART1_RXDATAV, ///< Trig on LEUART1_RXDATAV. #endif #if defined(DMAREQ_LEUART1_TXBL) dmadrvPeripheralSignal_LEUART1_TXBL = DMAREQ_LEUART1_TXBL, ///< Trig on LEUART1_TXBL. #endif #if defined(DMAREQ_LEUART1_TXEMPTY) dmadrvPeripheralSignal_LEUART1_TXEMPTY = DMAREQ_LEUART1_TXEMPTY, ///< Trig on LEUART1_TXEMPTY. #endif #if defined(DMAREQ_MSC_WDATA) dmadrvPeripheralSignal_MSC_WDATA = DMAREQ_MSC_WDATA, ///< Trig on MSC_WDATA. #endif #if defined(DMAREQ_TIMER0_CC0) dmadrvPeripheralSignal_TIMER0_CC0 = DMAREQ_TIMER0_CC0, ///< Trig on TIMER0_CC0. #endif #if defined(DMAREQ_TIMER0_CC1) dmadrvPeripheralSignal_TIMER0_CC1 = DMAREQ_TIMER0_CC1, ///< Trig on TIMER0_CC1. #endif #if defined(DMAREQ_TIMER0_CC2) dmadrvPeripheralSignal_TIMER0_CC2 = DMAREQ_TIMER0_CC2, ///< Trig on TIMER0_CC2. #endif #if defined(DMAREQ_TIMER0_UFOF) dmadrvPeripheralSignal_TIMER0_UFOF = DMAREQ_TIMER0_UFOF, ///< Trig on TIMER0_UFOF. #endif #if defined(DMAREQ_TIMER1_CC0) dmadrvPeripheralSignal_TIMER1_CC0 = DMAREQ_TIMER1_CC0, ///< Trig on TIMER1_CC0. #endif #if defined(DMAREQ_TIMER1_CC1) dmadrvPeripheralSignal_TIMER1_CC1 = DMAREQ_TIMER1_CC1, ///< Trig on TIMER1_CC1. #endif #if defined(DMAREQ_TIMER1_CC2) dmadrvPeripheralSignal_TIMER1_CC2 = DMAREQ_TIMER1_CC2, ///< Trig on TIMER1_CC2. #endif #if defined(DMAREQ_TIMER1_UFOF) dmadrvPeripheralSignal_TIMER1_UFOF = DMAREQ_TIMER1_UFOF, ///< Trig on TIMER1_UFOF. #endif #if defined(DMAREQ_TIMER2_CC0) dmadrvPeripheralSignal_TIMER2_CC0 = DMAREQ_TIMER2_CC0, ///< Trig on TIMER2_CC0. #endif #if defined(DMAREQ_TIMER2_CC1) dmadrvPeripheralSignal_TIMER2_CC1 = DMAREQ_TIMER2_CC1, ///< Trig on TIMER2_CC1. #endif #if defined(DMAREQ_TIMER2_CC2) dmadrvPeripheralSignal_TIMER2_CC2 = DMAREQ_TIMER2_CC2, ///< Trig on TIMER2_CC2. #endif #if defined(DMAREQ_TIMER2_UFOF) dmadrvPeripheralSignal_TIMER2_UFOF = DMAREQ_TIMER2_UFOF, ///< Trig on TIMER2_UFOF. #endif #if defined(DMAREQ_TIMER3_CC0) dmadrvPeripheralSignal_TIMER3_CC0 = DMAREQ_TIMER3_CC0, ///< Trig on TIMER3_CC0. #endif #if defined(DMAREQ_TIMER3_CC1) dmadrvPeripheralSignal_TIMER3_CC1 = DMAREQ_TIMER3_CC1, ///< Trig on TIMER3_CC1. #endif #if defined(DMAREQ_TIMER3_CC2) dmadrvPeripheralSignal_TIMER3_CC2 = DMAREQ_TIMER3_CC2, ///< Trig on TIMER3_CC2. #endif #if defined(DMAREQ_TIMER3_UFOF) dmadrvPeripheralSignal_TIMER3_UFOF = DMAREQ_TIMER3_UFOF, ///< Trig on TIMER3_UFOF. #endif #if defined(DMAREQ_UART0_RXDATAV) dmadrvPeripheralSignal_UART0_RXDATAV = DMAREQ_UART0_RXDATAV, ///< Trig on UART0_RXDATAV. #endif #if defined(DMAREQ_UART0_TXBL) dmadrvPeripheralSignal_UART0_TXBL = DMAREQ_UART0_TXBL, ///< Trig on UART0_TXBL. #endif #if defined(DMAREQ_UART0_TXEMPTY) dmadrvPeripheralSignal_UART0_TXEMPTY = DMAREQ_UART0_TXEMPTY, ///< Trig on UART0_TXEMPTY. #endif #if defined(DMAREQ_UART1_RXDATAV) dmadrvPeripheralSignal_UART1_RXDATAV = DMAREQ_UART1_RXDATAV, ///< Trig on UART1_RXDATAV. #endif #if defined(DMAREQ_UART1_TXBL) dmadrvPeripheralSignal_UART1_TXBL = DMAREQ_UART1_TXBL, ///< Trig on UART1_TXBL. #endif #if defined(DMAREQ_UART1_TXEMPTY) dmadrvPeripheralSignal_UART1_TXEMPTY = DMAREQ_UART1_TXEMPTY, ///< Trig on UART1_TXEMPTY. #endif #if defined(DMAREQ_USART0_RXDATAV) dmadrvPeripheralSignal_USART0_RXDATAV = DMAREQ_USART0_RXDATAV, ///< Trig on USART0_RXDATAV. #endif #if defined(DMAREQ_USART0_TXBL) dmadrvPeripheralSignal_USART0_TXBL = DMAREQ_USART0_TXBL, ///< Trig on USART0_TXBL. #endif #if defined(DMAREQ_USART0_TXEMPTY) dmadrvPeripheralSignal_USART0_TXEMPTY = DMAREQ_USART0_TXEMPTY, ///< Trig on USART0_TXEMPTY. #endif #if defined(DMAREQ_USARTRF0_RXDATAV) dmadrvPeripheralSignal_USARTRF0_RXDATAV = DMAREQ_USARTRF0_RXDATAV, ///< Trig on USARTRF0_RXDATAV. #endif #if defined(DMAREQ_USARTRF0_TXBL) dmadrvPeripheralSignal_USARTRF0_TXBL = DMAREQ_USARTRF0_TXBL, ///< Trig on USARTRF0_TXBL. #endif #if defined(DMAREQ_USARTRF0_TXEMPTY) dmadrvPeripheralSignal_USARTRF0_TXEMPTY = DMAREQ_USARTRF0_TXEMPTY, ///< Trig on USARTRF0_TXEMPTY. #endif #if defined(DMAREQ_USARTRF1_RXDATAV) dmadrvPeripheralSignal_USARTRF1_RXDATAV = DMAREQ_USARTRF1_RXDATAV, ///< Trig on USARTRF1_RXDATAV. #endif #if defined(DMAREQ_USARTRF1_TXBL) dmadrvPeripheralSignal_USARTRF1_TXBL = DMAREQ_USARTRF1_TXBL, ///< Trig on USARTRF1_TXBL. #endif #if defined(DMAREQ_USARTRF1_TXEMPTY) dmadrvPeripheralSignal_USARTRF1_TXEMPTY = DMAREQ_USARTRF1_TXEMPTY, ///< Trig on USARTRF1_TXEMPTY. #endif #if defined(DMAREQ_USART1_RXDATAV) dmadrvPeripheralSignal_USART1_RXDATAV = DMAREQ_USART1_RXDATAV, ///< Trig on USART1_RXDATAV. #endif #if defined(DMAREQ_USART1_RXDATAVRIGHT) dmadrvPeripheralSignal_USART1_RXDATAVRIGHT = DMAREQ_USART1_RXDATAVRIGHT,///< Trig on USART1_RXDATAVRIGHT. #endif #if defined(DMAREQ_USART1_TXBL) dmadrvPeripheralSignal_USART1_TXBL = DMAREQ_USART1_TXBL, ///< Trig on USART1_TXBL. #endif #if defined(DMAREQ_USART1_TXBLRIGHT) dmadrvPeripheralSignal_USART1_TXBLRIGHT = DMAREQ_USART1_TXBLRIGHT, ///< Trig on USART1_TXBLRIGHT. #endif #if defined(DMAREQ_USART1_TXEMPTY) dmadrvPeripheralSignal_USART1_TXEMPTY = DMAREQ_USART1_TXEMPTY, ///< Trig on USART1_TXEMPTY. #endif #if defined(DMAREQ_USART2_RXDATAV) dmadrvPeripheralSignal_USART2_RXDATAV = DMAREQ_USART2_RXDATAV, ///< Trig on USART2_RXDATAV. #endif #if defined(DMAREQ_USART2_RXDATAVRIGHT) dmadrvPeripheralSignal_USART2_RXDATAVRIGHT = DMAREQ_USART2_RXDATAVRIGHT,///< Trig on USART2_RXDATAVRIGHT. #endif #if defined(DMAREQ_USART2_TXBL) dmadrvPeripheralSignal_USART2_TXBL = DMAREQ_USART2_TXBL, ///< Trig on USART2_TXBL. #endif #if defined(DMAREQ_USART2_TXBLRIGHT) dmadrvPeripheralSignal_USART2_TXBLRIGHT = DMAREQ_USART2_TXBLRIGHT, ///< Trig on USART2_TXBLRIGHT. #endif #if defined(DMAREQ_USART2_TXEMPTY) dmadrvPeripheralSignal_USART2_TXEMPTY = DMAREQ_USART2_TXEMPTY, ///< Trig on USART2_TXEMPTY. #endif #ifdef DOXY_DOC_ONLY } DMADRV_Peripheralsignal_t; #else } DMADRV_PeripheralSignal_t; #endif /// Data size of one UDMA transfer item. typedef enum { dmadrvDataSize1 = dmaDataSize1, ///< Byte dmadrvDataSize2 = dmaDataSize2, ///< Halfword dmadrvDataSize4 = dmaDataSize4 ///< Word #ifdef DOXY_DOC_ONLY } DMADRV_Datasize_t; #else } DMADRV_DataSize_t; #endif #endif // defined( DMA_PRESENT ) && ( DMA_COUNT == 1 ) #if defined(LDMA_PRESENT) && (LDMA_COUNT == 1) /// Maximum length of one DMA transfer. #define DMADRV_MAX_XFER_COUNT ((int)((_LDMA_CH_CTRL_XFERCNT_MASK >> _LDMA_CH_CTRL_XFERCNT_SHIFT) + 1)) #if defined(LDMAXBAR_COUNT) && (LDMAXBAR_COUNT > 0) /// Peripherals that can trigger LDMA transfers. typedef enum { dmadrvPeripheralSignal_NONE = LDMAXBAR_CH_REQSEL_SOURCESEL_NONE, ///< No peripheral selected for DMA triggering. #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC0 dmadrvPeripheralSignal_TIMER0_CC0 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC0 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER0, #endif #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC1 dmadrvPeripheralSignal_TIMER0_CC1 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC1 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER0, #endif #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC2 dmadrvPeripheralSignal_TIMER0_CC2 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC2 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER0, #endif #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0UFOF dmadrvPeripheralSignal_TIMER0_UFOF = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0UFOF | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER0, #endif #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC0 dmadrvPeripheralSignal_TIMER1_CC0 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC0 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER1, #endif #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC1 dmadrvPeripheralSignal_TIMER1_CC1 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC1 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER1, #endif #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC2 dmadrvPeripheralSignal_TIMER1_CC2 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC2 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER1, #endif #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1UFOF dmadrvPeripheralSignal_TIMER1_UFOF = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1UFOF | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER1, #endif #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAV dmadrvPeripheralSignal_USART0_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAV | LDMAXBAR_CH_REQSEL_SOURCESEL_USART0, #endif #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAVRIGHT dmadrvPeripheralSignal_USART0_RXDATAVRIGHT = LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAVRIGHT | LDMAXBAR_CH_REQSEL_SOURCESEL_USART0, #endif #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBL dmadrvPeripheralSignal_USART0_TXBL = LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBL | LDMAXBAR_CH_REQSEL_SOURCESEL_USART0, #endif #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBLRIGHT dmadrvPeripheralSignal_USART0_TXBLRIGHT = LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBLRIGHT | LDMAXBAR_CH_REQSEL_SOURCESEL_USART0, #endif #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXEMPTY dmadrvPeripheralSignal_USART0_TXEMPTY = LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXEMPTY | LDMAXBAR_CH_REQSEL_SOURCESEL_USART0, #endif #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART1RXDATAV dmadrvPeripheralSignal_USART1_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_USART1RXDATAV | LDMAXBAR_CH_REQSEL_SOURCESEL_USART1, #endif #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT dmadrvPeripheralSignal_USART1_RXDATAVRIGHT = LDMAXBAR_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT | LDMAXBAR_CH_REQSEL_SOURCESEL_USART1, #endif #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXBL dmadrvPeripheralSignal_USART1_TXBL = LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXBL | LDMAXBAR_CH_REQSEL_SOURCESEL_USART1, #endif #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXBLRIGHT dmadrvPeripheralSignal_USART1_TXBLRIGHT = LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXBLRIGHT | LDMAXBAR_CH_REQSEL_SOURCESEL_USART1, #endif #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXEMPTY dmadrvPeripheralSignal_USART1_TXEMPTY = LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXEMPTY | LDMAXBAR_CH_REQSEL_SOURCESEL_USART1, #endif #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART2RXDATAV dmadrvPeripheralSignal_USART2_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_USART2RXDATAV | LDMAXBAR_CH_REQSEL_SOURCESEL_USART2, #endif #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART2RXDATAVRIGHT dmadrvPeripheralSignal_USART2_RXDATAVRIGHT = LDMAXBAR_CH_REQSEL_SIGSEL_USART2RXDATAVRIGHT | LDMAXBAR_CH_REQSEL_SOURCESEL_USART2, #endif #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART2TXBL dmadrvPeripheralSignal_USART2_TXBL = LDMAXBAR_CH_REQSEL_SIGSEL_USART2TXBL | LDMAXBAR_CH_REQSEL_SOURCESEL_USART2, #endif #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART2TXBLRIGHT dmadrvPeripheralSignal_USART2_TXBLRIGHT = LDMAXBAR_CH_REQSEL_SIGSEL_USART2TXBLRIGHT | LDMAXBAR_CH_REQSEL_SOURCESEL_USART2, #endif #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART2TXEMPTY dmadrvPeripheralSignal_USART2_TXEMPTY = LDMAXBAR_CH_REQSEL_SIGSEL_USART2TXEMPTY | LDMAXBAR_CH_REQSEL_SOURCESEL_USART2, #endif #if defined LDMAXBAR_CH_REQSEL_SIGSEL_I2C0RXDATAV dmadrvPeripheralSignal_I2C0_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_I2C0RXDATAV | LDMAXBAR_CH_REQSEL_SOURCESEL_I2C0, #endif #if defined LDMAXBAR_CH_REQSEL_SIGSEL_I2C0TXBL dmadrvPeripheralSignal_I2C0_TXBL = LDMAXBAR_CH_REQSEL_SIGSEL_I2C0TXBL | LDMAXBAR_CH_REQSEL_SOURCESEL_I2C0, #endif #if defined LDMAXBAR_CH_REQSEL_SIGSEL_I2C1RXDATAV dmadrvPeripheralSignal_I2C1_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_I2C1RXDATAV | LDMAXBAR_CH_REQSEL_SOURCESEL_I2C1, #endif #if defined LDMAXBAR_CH_REQSEL_SIGSEL_I2C1TXBL dmadrvPeripheralSignal_I2C1_TXBL = LDMAXBAR_CH_REQSEL_SIGSEL_I2C1TXBL | LDMAXBAR_CH_REQSEL_SOURCESEL_I2C1, #endif #if defined LDMAXBAR_CH_REQSEL_SIGSEL_AGCRSSI dmadrvPeripheralSignal_AGC_RSSI = LDMAXBAR_CH_REQSEL_SIGSEL_AGCRSSI | LDMAXBAR_CH_REQSEL_SOURCESEL_AGC, #endif #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERBOF dmadrvPeripheralSignal_PROTIMER_BOF = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERBOF | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER, #endif #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC0 dmadrvPeripheralSignal_PROTIMER_CC0 = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC0 | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER, #endif #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC1 dmadrvPeripheralSignal_PROTIMER_CC1 = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC1 | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER, #endif #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC2 dmadrvPeripheralSignal_PROTIMER_CC2 = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC2 | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER, #endif #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC3 dmadrvPeripheralSignal_PROTIMER_CC3 = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC3 | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER, #endif #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC4 dmadrvPeripheralSignal_PROTIMER_CC4 = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC4 | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER, #endif #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERPOF dmadrvPeripheralSignal_PROTIMER_POF = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERPOF | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER, #endif #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERWOF dmadrvPeripheralSignal_PROTIMER_WOF = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERWOF | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER, #endif #if defined LDMAXBAR_CH_REQSEL_SIGSEL_MODEMDEBUG dmadrvPeripheralSignal_MODEM_DEBUG = LDMAXBAR_CH_REQSEL_SIGSEL_MODEMDEBUG | LDMAXBAR_CH_REQSEL_SOURCESEL_MODEM, #endif #if defined LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SCAN dmadrvPeripheralSignal_IADC0_IADC_SCAN = LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SCAN | LDMAXBAR_CH_REQSEL_SOURCESEL_IADC0, #endif #if defined LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SINGLE dmadrvPeripheralSignal_IADC0_IADC_SINGLE = LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SINGLE | LDMAXBAR_CH_REQSEL_SOURCESEL_IADC0, #endif #if defined LDMAXBAR_CH_REQSEL_SIGSEL_IMEMWDATA dmadrvPeripheralSignal_IMEM_WDATA = LDMAXBAR_CH_REQSEL_SIGSEL_IMEMWDATA | LDMAXBAR_CH_REQSEL_SOURCESEL_IMEM, #endif #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC0 dmadrvPeripheralSignal_TIMER2_CC0 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC0 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER2, #endif #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC1 dmadrvPeripheralSignal_TIMER2_CC1 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC1 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER2, #endif #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC2 dmadrvPeripheralSignal_TIMER2_CC2 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC2 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER2, #endif #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2UFOF dmadrvPeripheralSignal_TIMER2_UFOF = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2UFOF | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER2, #endif #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC0 dmadrvPeripheralSignal_TIMER3_CC0 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC0 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER3, #endif #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC1 dmadrvPeripheralSignal_TIMER3_CC1 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC1 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER3, #endif #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC2 dmadrvPeripheralSignal_TIMER3_CC2 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC2 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER3, #endif #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3UFOF dmadrvPeripheralSignal_TIMER3_UFOF = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3UFOF | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER3, #endif } DMADRV_PeripheralSignal_t; #else /// Peripherals that can trigger LDMA transfers. typedef enum { dmadrvPeripheralSignal_NONE = LDMA_CH_REQSEL_SOURCESEL_NONE, ///< No peripheral selected for DMA triggering. #if defined(LDMA_CH_REQSEL_SIGSEL_ADC0SCAN) dmadrvPeripheralSignal_ADC0_SCAN = LDMA_CH_REQSEL_SIGSEL_ADC0SCAN | LDMA_CH_REQSEL_SOURCESEL_ADC0, ///< Trig on ADC0_SCAN. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_ADC0SINGLE) dmadrvPeripheralSignal_ADC0_SINGLE = LDMA_CH_REQSEL_SIGSEL_ADC0SINGLE | LDMA_CH_REQSEL_SOURCESEL_ADC0, ///< Trig on ADC0_SINGLE. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_ADC1SCAN) dmadrvPeripheralSignal_ADC1_SCAN = LDMA_CH_REQSEL_SIGSEL_ADC1SCAN | LDMA_CH_REQSEL_SOURCESEL_ADC1, ///< Trig on ADC1_SCAN. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_ADC1SINGLE) dmadrvPeripheralSignal_ADC1_SINGLE = LDMA_CH_REQSEL_SIGSEL_ADC1SINGLE | LDMA_CH_REQSEL_SOURCESEL_ADC1, ///< Trig on ADC1_SINGLE. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_VDAC0CH0) dmadrvPeripheralSignal_VDAC0_CH0 = LDMA_CH_REQSEL_SIGSEL_VDAC0CH0 | LDMA_CH_REQSEL_SOURCESEL_VDAC0, ///< Trig on VDAC0_CH0 #endif #if defined(LDMA_CH_REQSEL_SIGSEL_VDAC0CH1) dmadrvPeripheralSignal_VDAC0_CH1 = LDMA_CH_REQSEL_SIGSEL_VDAC0CH1 | LDMA_CH_REQSEL_SOURCESEL_VDAC0, ///< Trig on VDAC0_CH1 #endif #if defined(LDMA_CH_REQSEL_SIGSEL_AGCRSSI) dmadrvPeripheralSignal_AGC_RSSI = LDMA_CH_REQSEL_SIGSEL_AGCRSSI | LDMA_CH_REQSEL_SOURCESEL_AGC, ///< Trig on AGC_RSSI. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0RD) dmadrvPeripheralSignal_CRYPTO_DATA0RD = LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO, ///< Trig on CRYPTO_DATA0RD. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0WR) dmadrvPeripheralSignal_CRYPTO_DATA0WR = LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0WR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO, ///< Trig on CRYPTO_DATA0WR. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0XWR) dmadrvPeripheralSignal_CRYPTO_DATA0XWR = LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0XWR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO, ///< Trig on CRYPTO_DATA0XWR. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1RD) dmadrvPeripheralSignal_CRYPTO_DATA1RD = LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO, ///< Trig on CRYPTO_DATA1RD. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1WR) dmadrvPeripheralSignal_CRYPTO_DATA1WR = LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1WR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO, ///< Trig on CRYPTO_DATA1WR. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0RD) dmadrvPeripheralSignal_CRYPTO0_DATA0RD = LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO0, ///< Trig on CRYPTO0_DATA0RD. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0WR) dmadrvPeripheralSignal_CRYPTO0_DATA0WR = LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0WR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO0, ///< Trig on CRYPTO0_DATA0WR. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0XWR) dmadrvPeripheralSignal_CRYPTO0_DATA0XWR = LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0XWR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO0, ///< Trig on CRYPTO0_DATA0XWR. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1RD) dmadrvPeripheralSignal_CRYPTO0_DATA1RD = LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO0, ///< Trig on CRYPTO0_DATA1RD. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1WR) dmadrvPeripheralSignal_CRYPTO0_DATA1WR = LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1WR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO0, ///< Trig on CRYPTO0_DATA1WR. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0RD) dmadrvPeripheralSignal_CRYPTO1_DATA0RD = LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO1, ///< Trig on CRYPTO1_DATA0RD. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0WR) dmadrvPeripheralSignal_CRYPTO1_DATA0WR = LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0WR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO1, ///< Trig on CRYPTO1_DATA0WR. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0XWR) dmadrvPeripheralSignal_CRYPTO1_DATA0XWR = LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0XWR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO1, ///< Trig on CRYPTO1_DATA0XWR. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA1RD) dmadrvPeripheralSignal_CRYPTO1_DATA1RD = LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA1RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO1, ///< Trig on CRYPTO1_DATA1RD. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA1WR) dmadrvPeripheralSignal_CRYPTO1_DATA1WR = LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA1WR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO1, ///< Trig on CRYPTO1_DATA1WR. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_EBIPXL0EMPTY) dmadrvPeripheralSignal_EBI_PXL0EMPTY = LDMA_CH_REQSEL_SIGSEL_EBIPXL0EMPTY | LDMA_CH_REQSEL_SOURCESEL_EBI, ///< Trig on EBI_PXL0EMPTY. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_EBIPXL1EMPTY) dmadrvPeripheralSignal_EBI_PXL1EMPTY = LDMA_CH_REQSEL_SIGSEL_EBIPXL1EMPTY | LDMA_CH_REQSEL_SOURCESEL_EBI, ///< Trig on EBI_PXL1EMPTY. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_EBIPXLFULL) dmadrvPeripheralSignal_EBI_PXLFULL = LDMA_CH_REQSEL_SIGSEL_EBIPXLFULL | LDMA_CH_REQSEL_SOURCESEL_EBI, ///< Trig on EBI_PXLFULL. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_EBIDDEMPTY) dmadrvPeripheralSignal_EBI_DDEMPTY = LDMA_CH_REQSEL_SIGSEL_EBIDDEMPTY | LDMA_CH_REQSEL_SOURCESEL_EBI, ///< Trig on EBI_DDEMPTY. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_EBIVSYNC) dmadrvPeripheralSignal_EBI_VSYNC = LDMA_CH_REQSEL_SIGSEL_EBIVSYNC | LDMA_CH_REQSEL_SOURCESEL_EBI, ///< Trig on EBI_VSYNC. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_EBIHSYNC) dmadrvPeripheralSignal_EBI_HSYNC = LDMA_CH_REQSEL_SIGSEL_EBIHSYNC | LDMA_CH_REQSEL_SOURCESEL_EBI, ///< Trig on EBI_HSYNC. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_CSENDATA) dmadrvPeripheralSignal_CSEN_DATA = LDMA_CH_REQSEL_SIGSEL_CSENDATA | LDMA_CH_REQSEL_SOURCESEL_CSEN, ///< Trig on CSEN_DATA. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_CSENBSLN) dmadrvPeripheralSignal_CSEN_BSLN = LDMA_CH_REQSEL_SIGSEL_CSENBSLN | LDMA_CH_REQSEL_SOURCESEL_CSEN, ///< Trig on CSEN_BSLN. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_LSENSEBUFDATAV) dmadrvPeripheralSignal_LESENSE_BUFDATAV = LDMA_CH_REQSEL_SIGSEL_LSENSEBUFDATAV | LDMA_CH_REQSEL_SOURCESEL_LESENSE, ///< Trig on LESENSE_BUFDATAV. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_I2C0RXDATAV) dmadrvPeripheralSignal_I2C0_RXDATAV = LDMA_CH_REQSEL_SIGSEL_I2C0RXDATAV | LDMA_CH_REQSEL_SOURCESEL_I2C0, ///< Trig on I2C0_RXDATAV. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_I2C0TXBL) dmadrvPeripheralSignal_I2C0_TXBL = LDMA_CH_REQSEL_SIGSEL_I2C0TXBL | LDMA_CH_REQSEL_SOURCESEL_I2C0, ///< Trig on I2C0_TXBL. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_I2C1RXDATAV) dmadrvPeripheralSignal_I2C1_RXDATAV = LDMA_CH_REQSEL_SIGSEL_I2C1RXDATAV | LDMA_CH_REQSEL_SOURCESEL_I2C1, ///< Trig on I2C1_RXDATAV. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_I2C1TXBL) dmadrvPeripheralSignal_I2C1_TXBL = LDMA_CH_REQSEL_SIGSEL_I2C1TXBL | LDMA_CH_REQSEL_SOURCESEL_I2C1, ///< Trig on I2C1_TXBL. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_I2C2RXDATAV) dmadrvPeripheralSignal_I2C2_RXDATAV = LDMA_CH_REQSEL_SIGSEL_I2C2RXDATAV | LDMA_CH_REQSEL_SOURCESEL_I2C2, ///< Trig on I2C2_RXDATAV. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_I2C2TXBL) dmadrvPeripheralSignal_I2C2_TXBL = LDMA_CH_REQSEL_SIGSEL_I2C2TXBL | LDMA_CH_REQSEL_SOURCESEL_I2C2, ///< Trig on I2C2_TXBL. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_LEUART0RXDATAV) dmadrvPeripheralSignal_LEUART0_RXDATAV = LDMA_CH_REQSEL_SIGSEL_LEUART0RXDATAV | LDMA_CH_REQSEL_SOURCESEL_LEUART0, ///< Trig on LEUART0_RXDATAV. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_LEUART0TXBL) dmadrvPeripheralSignal_LEUART0_TXBL = LDMA_CH_REQSEL_SIGSEL_LEUART0TXBL | LDMA_CH_REQSEL_SOURCESEL_LEUART0, ///< Trig on LEUART0_TXBL. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_LEUART0TXEMPTY) dmadrvPeripheralSignal_LEUART0_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_LEUART0TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_LEUART0, ///< Trig on LEUART0_TXEMPTY. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_LEUART1RXDATAV) dmadrvPeripheralSignal_LEUART1_RXDATAV = LDMA_CH_REQSEL_SIGSEL_LEUART1RXDATAV | LDMA_CH_REQSEL_SOURCESEL_LEUART1, ///< Trig on LEUART1_RXDATAV. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_LEUART1TXBL) dmadrvPeripheralSignal_LEUART1_TXBL = LDMA_CH_REQSEL_SIGSEL_LEUART1TXBL | LDMA_CH_REQSEL_SOURCESEL_LEUART1, ///< Trig on LEUART1_TXBL. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_LEUART1TXEMPTY) dmadrvPeripheralSignal_LEUART1_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_LEUART1TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_LEUART1, ///< Trig on LEUART1_TXEMPTY. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_MODEMDEBUG) dmadrvPeripheralSignal_MODEM_DEBUG = LDMA_CH_REQSEL_SIGSEL_MODEMDEBUG | LDMA_CH_REQSEL_SOURCESEL_MODEM, ///< Trig on MODEM_DEBUG. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_MSCWDATA) dmadrvPeripheralSignal_MSC_WDATA = LDMA_CH_REQSEL_SIGSEL_MSCWDATA | LDMA_CH_REQSEL_SOURCESEL_MSC, ///< Trig on MSC_WDATA. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_PROTIMERBOF) dmadrvPeripheralSignal_PROTIMER_BOF = LDMA_CH_REQSEL_SIGSEL_PROTIMERBOF | LDMA_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trig on PROTIMER_BOF. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_PROTIMERCC0) dmadrvPeripheralSignal_PROTIMER_CC0 = LDMA_CH_REQSEL_SIGSEL_PROTIMERCC0 | LDMA_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trig on PROTIMER_CC0. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_PROTIMERCC1) dmadrvPeripheralSignal_PROTIMER_CC1 = LDMA_CH_REQSEL_SIGSEL_PROTIMERCC1 | LDMA_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trig on PROTIMER_CC1. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_PROTIMERCC2) dmadrvPeripheralSignal_PROTIMER_CC2 = LDMA_CH_REQSEL_SIGSEL_PROTIMERCC2 | LDMA_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trig on PROTIMER_CC2. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_PROTIMERCC3) dmadrvPeripheralSignal_PROTIMER_CC3 = LDMA_CH_REQSEL_SIGSEL_PROTIMERCC3 | LDMA_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trig on PROTIMER_CC3. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_PROTIMERCC4) dmadrvPeripheralSignal_PROTIMER_CC4 = LDMA_CH_REQSEL_SIGSEL_PROTIMERCC4 | LDMA_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trig on PROTIMER_CC4. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_PROTIMERPOF) dmadrvPeripheralSignal_PROTIMER_POF = LDMA_CH_REQSEL_SIGSEL_PROTIMERPOF | LDMA_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trig on PROTIMER_POF. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_PROTIMERWOF) dmadrvPeripheralSignal_PROTIMER_WOF = LDMA_CH_REQSEL_SIGSEL_PROTIMERWOF | LDMA_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trig on PROTIMER_WOF. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_PRSREQ0) dmadrvPeripheralSignal_PRS_REQ0 = LDMA_CH_REQSEL_SIGSEL_PRSREQ0 | LDMA_CH_REQSEL_SOURCESEL_PRS, ///< Trig on PRS_REQ0. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_PRSREQ1) dmadrvPeripheralSignal_PRS_REQ1 = LDMA_CH_REQSEL_SIGSEL_PRSREQ1 | LDMA_CH_REQSEL_SOURCESEL_PRS, ///< Trig on PRS_REQ1. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER0CC0) dmadrvPeripheralSignal_TIMER0_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER0CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER0, ///< Trig on TIMER0_CC0. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER0CC1) dmadrvPeripheralSignal_TIMER0_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER0CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER0, ///< Trig on TIMER0_CC1. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER0CC2) dmadrvPeripheralSignal_TIMER0_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER0CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER0, ///< Trig on TIMER0_CC2. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER0CC3) dmadrvPeripheralSignal_TIMER0_CC3 = LDMA_CH_REQSEL_SIGSEL_TIMER0CC3 | LDMA_CH_REQSEL_SOURCESEL_TIMER0, ///< Trig on TIMER0_CC3. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER0UFOF) dmadrvPeripheralSignal_TIMER0_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER0UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER0, ///< Trig on TIMER0_UFOF. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER1CC0) dmadrvPeripheralSignal_TIMER1_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER1CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER1, ///< Trig on TIMER1_CC0. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER1CC1) dmadrvPeripheralSignal_TIMER1_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER1CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER1, ///< Trig on TIMER1_CC1. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER1CC2) dmadrvPeripheralSignal_TIMER1_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER1CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER1, ///< Trig on TIMER1_CC2. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER1CC3) dmadrvPeripheralSignal_TIMER1_CC3 = LDMA_CH_REQSEL_SIGSEL_TIMER1CC3 | LDMA_CH_REQSEL_SOURCESEL_TIMER1, ///< Trig on TIMER1_CC3. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER1UFOF) dmadrvPeripheralSignal_TIMER1_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER1UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER1, ///< Trig on TIMER1_UFOF. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER2CC0) dmadrvPeripheralSignal_TIMER2_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER2CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER2, ///< Trig on TIMER2_CC0. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER2CC1) dmadrvPeripheralSignal_TIMER2_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER2CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER2, ///< Trig on TIMER2_CC1. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER2CC2) dmadrvPeripheralSignal_TIMER2_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER2CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER2, ///< Trig on TIMER2_CC2. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER2CC3) dmadrvPeripheralSignal_TIMER2_CC3 = LDMA_CH_REQSEL_SIGSEL_TIMER2CC3 | LDMA_CH_REQSEL_SOURCESEL_TIMER2, ///< Trig on TIMER2_CC3. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER2UFOF) dmadrvPeripheralSignal_TIMER2_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER2UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER2, ///< Trig on TIMER2_UFOF. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER3CC0) dmadrvPeripheralSignal_TIMER3_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER3CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER3, ///< Trig on TIMER3_CC0. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER3CC1) dmadrvPeripheralSignal_TIMER3_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER3CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER3, ///< Trig on TIMER3_CC1. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER3CC2) dmadrvPeripheralSignal_TIMER3_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER3CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER3, ///< Trig on TIMER3_CC2. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER3CC3) dmadrvPeripheralSignal_TIMER3_CC3 = LDMA_CH_REQSEL_SIGSEL_TIMER3CC3 | LDMA_CH_REQSEL_SOURCESEL_TIMER3, ///< Trig on TIMER3_CC3. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER3UFOF) dmadrvPeripheralSignal_TIMER3_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER3UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER3, ///< Trig on TIMER3_UFOF. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER4CC0) dmadrvPeripheralSignal_TIMER4_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER4CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER4, ///< Trig on TIMER4_CC0. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER4CC1) dmadrvPeripheralSignal_TIMER4_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER4CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER4, ///< Trig on TIMER4_CC1. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER4CC2) dmadrvPeripheralSignal_TIMER4_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER4CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER4, ///< Trig on TIMER4_CC2. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER4CC3) dmadrvPeripheralSignal_TIMER4_CC3 = LDMA_CH_REQSEL_SIGSEL_TIMER4CC3 | LDMA_CH_REQSEL_SOURCESEL_TIMER4, ///< Trig on TIMER4_CC3. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER4UFOF) dmadrvPeripheralSignal_TIMER4_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER4UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER4, ///< Trig on TIMER4_UFOF. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER5CC0) dmadrvPeripheralSignal_TIMER5_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER5CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER5, ///< Trig on TIMER5_CC0. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER5CC1) dmadrvPeripheralSignal_TIMER5_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER5CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER5, ///< Trig on TIMER5_CC1. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER5CC2) dmadrvPeripheralSignal_TIMER5_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER5CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER5, ///< Trig on TIMER5_CC2. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER5CC3) dmadrvPeripheralSignal_TIMER5_CC3 = LDMA_CH_REQSEL_SIGSEL_TIMER5CC3 | LDMA_CH_REQSEL_SOURCESEL_TIMER5, ///< Trig on TIMER5_CC3. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER5UFOF) dmadrvPeripheralSignal_TIMER5_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER5UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER5, ///< Trig on TIMER5_UFOF. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER6CC0) dmadrvPeripheralSignal_TIMER6_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER6CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER6, ///< Trig on TIMER6_CC0. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER6CC1) dmadrvPeripheralSignal_TIMER6_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER6CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER6, ///< Trig on TIMER6_CC1. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER6CC2) dmadrvPeripheralSignal_TIMER6_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER6CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER6, ///< Trig on TIMER6_CC2. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER6CC3) dmadrvPeripheralSignal_TIMER6_CC3 = LDMA_CH_REQSEL_SIGSEL_TIMER6CC3 | LDMA_CH_REQSEL_SOURCESEL_TIMER6, ///< Trig on TIMER6_CC3. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER6UFOF) dmadrvPeripheralSignal_TIMER6_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER6UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER6, ///< Trig on TIMER6_UFOF. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER0CC0) dmadrvPeripheralSignal_WTIMER0_CC0 = LDMA_CH_REQSEL_SIGSEL_WTIMER0CC0 | LDMA_CH_REQSEL_SOURCESEL_WTIMER0, ///< Trig on WTIMER0_CC0. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER0CC1) dmadrvPeripheralSignal_WTIMER0_CC1 = LDMA_CH_REQSEL_SIGSEL_WTIMER0CC1 | LDMA_CH_REQSEL_SOURCESEL_WTIMER0, ///< Trig on WTIMER0_CC1. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER0CC2) dmadrvPeripheralSignal_WTIMER0_CC2 = LDMA_CH_REQSEL_SIGSEL_WTIMER0CC2 | LDMA_CH_REQSEL_SOURCESEL_WTIMER0, ///< Trig on WTIMER0_CC2. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER0CC3) dmadrvPeripheralSignal_WTIMER0_CC3 = LDMA_CH_REQSEL_SIGSEL_WTIMER0CC3 | LDMA_CH_REQSEL_SOURCESEL_WTIMER0, ///< Trig on WTIMER0_CC3. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER0UFOF) dmadrvPeripheralSignal_WTIMER0_UFOF = LDMA_CH_REQSEL_SIGSEL_WTIMER0UFOF | LDMA_CH_REQSEL_SOURCESEL_WTIMER0, ///< Trig on WTIMER0_UFOF. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER1CC0) dmadrvPeripheralSignal_WTIMER1_CC0 = LDMA_CH_REQSEL_SIGSEL_WTIMER1CC0 | LDMA_CH_REQSEL_SOURCESEL_WTIMER1, ///< Trig on WTIMER1_CC0. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER1CC1) dmadrvPeripheralSignal_WTIMER1_CC1 = LDMA_CH_REQSEL_SIGSEL_WTIMER1CC1 | LDMA_CH_REQSEL_SOURCESEL_WTIMER1, ///< Trig on WTIMER1_CC1. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER1CC2) dmadrvPeripheralSignal_WTIMER1_CC2 = LDMA_CH_REQSEL_SIGSEL_WTIMER1CC2 | LDMA_CH_REQSEL_SOURCESEL_WTIMER1, ///< Trig on WTIMER1_CC2. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER1CC3) dmadrvPeripheralSignal_WTIMER1_CC3 = LDMA_CH_REQSEL_SIGSEL_WTIMER1CC3 | LDMA_CH_REQSEL_SOURCESEL_WTIMER1, ///< Trig on WTIMER1_CC3. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER1UFOF) dmadrvPeripheralSignal_WTIMER1_UFOF = LDMA_CH_REQSEL_SIGSEL_WTIMER1UFOF | LDMA_CH_REQSEL_SOURCESEL_WTIMER1, ///< Trig on WTIMER1_UFOF. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER2CC0) dmadrvPeripheralSignal_WTIMER2_CC0 = LDMA_CH_REQSEL_SIGSEL_WTIMER2CC0 | LDMA_CH_REQSEL_SOURCESEL_WTIMER2, ///< Trig on WTIMER2_CC0. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER2CC1) dmadrvPeripheralSignal_WTIMER2_CC1 = LDMA_CH_REQSEL_SIGSEL_WTIMER2CC1 | LDMA_CH_REQSEL_SOURCESEL_WTIMER2, ///< Trig on WTIMER2_CC1. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER2CC2) dmadrvPeripheralSignal_WTIMER2_CC2 = LDMA_CH_REQSEL_SIGSEL_WTIMER2CC2 | LDMA_CH_REQSEL_SOURCESEL_WTIMER2, ///< Trig on WTIMER2_CC2. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER2CC3) dmadrvPeripheralSignal_WTIMER2_CC3 = LDMA_CH_REQSEL_SIGSEL_WTIMER2CC3 | LDMA_CH_REQSEL_SOURCESEL_WTIMER2, ///< Trig on WTIMER2_CC3. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER2UFOF) dmadrvPeripheralSignal_WTIMER2_UFOF = LDMA_CH_REQSEL_SIGSEL_WTIMER2UFOF | LDMA_CH_REQSEL_SOURCESEL_WTIMER2, ///< Trig on WTIMER2_UFOF. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER3CC0) dmadrvPeripheralSignal_WTIMER3_CC0 = LDMA_CH_REQSEL_SIGSEL_WTIMER3CC0 | LDMA_CH_REQSEL_SOURCESEL_WTIMER3, ///< Trig on WTIMER3_CC0. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER3CC1) dmadrvPeripheralSignal_WTIMER3_CC1 = LDMA_CH_REQSEL_SIGSEL_WTIMER3CC1 | LDMA_CH_REQSEL_SOURCESEL_WTIMER3, ///< Trig on WTIMER3_CC1. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER3CC2) dmadrvPeripheralSignal_WTIMER3_CC2 = LDMA_CH_REQSEL_SIGSEL_WTIMER3CC2 | LDMA_CH_REQSEL_SOURCESEL_WTIMER3, ///< Trig on WTIMER3_CC2. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER3CC3) dmadrvPeripheralSignal_WTIMER3_CC3 = LDMA_CH_REQSEL_SIGSEL_WTIMER3CC3 | LDMA_CH_REQSEL_SOURCESEL_WTIMER3, ///< Trig on WTIMER3_CC3. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER3UFOF) dmadrvPeripheralSignal_WTIMER3_UFOF = LDMA_CH_REQSEL_SIGSEL_WTIMER3UFOF | LDMA_CH_REQSEL_SOURCESEL_WTIMER3, ///< Trig on WTIMER3_UFOF. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_USART0RXDATAV) dmadrvPeripheralSignal_USART0_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART0RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART0, ///< Trig on USART0_RXDATAV. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_USART0TXBL) dmadrvPeripheralSignal_USART0_TXBL = LDMA_CH_REQSEL_SIGSEL_USART0TXBL | LDMA_CH_REQSEL_SOURCESEL_USART0, ///< Trig on USART0_TXBL. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_USART0TXEMPTY) dmadrvPeripheralSignal_USART0_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART0TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART0, ///< Trig on USART0_TXEMPTY. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_USART1RXDATAV) dmadrvPeripheralSignal_USART1_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART1RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART1, ///< Trig on USART1_RXDATAV. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT) dmadrvPeripheralSignal_USART1_RXDATAVRIGHT = LDMA_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART1, ///< Trig on USART1_RXDATAVRIGHT. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_USART1TXBL) dmadrvPeripheralSignal_USART1_TXBL = LDMA_CH_REQSEL_SIGSEL_USART1TXBL | LDMA_CH_REQSEL_SOURCESEL_USART1, ///< Trig on USART1_TXBL. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_USART1TXBLRIGHT) dmadrvPeripheralSignal_USART1_TXBLRIGHT = LDMA_CH_REQSEL_SIGSEL_USART1TXBLRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART1, ///< Trig on USART1_TXBLRIGHT. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_USART1TXEMPTY) dmadrvPeripheralSignal_USART1_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART1TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART1, ///< Trig on USART1_TXEMPTY. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_USART2RXDATAV) dmadrvPeripheralSignal_USART2_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART2RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART2, ///< Trig on USART2_RXDATAV. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_USART2RXDATAVRIGHT) dmadrvPeripheralSignal_USART2_RXDATAVRIGHT = LDMA_CH_REQSEL_SIGSEL_USART2RXDATAVRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART2, ///< Trig on USART2_RXDATAVRIGHT. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_USART2TXBL) dmadrvPeripheralSignal_USART2_TXBL = LDMA_CH_REQSEL_SIGSEL_USART2TXBL | LDMA_CH_REQSEL_SOURCESEL_USART2, ///< Trig on USART2_TXBL. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_USART2TXBLRIGHT) dmadrvPeripheralSignal_USART2_TXBLRIGHT = LDMA_CH_REQSEL_SIGSEL_USART2TXBLRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART2, ///< Trig on USART2_TXBLRIGHT. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_USART2TXEMPTY) dmadrvPeripheralSignal_USART2_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART2TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART2, ///< Trig on USART2_TXEMPTY. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_USART3RXDATAV) dmadrvPeripheralSignal_USART3_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART3RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART3, ///< Trig on USART3_RXDATAV. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_USART3RXDATAVRIGHT) dmadrvPeripheralSignal_USART3_RXDATAVRIGHT = LDMA_CH_REQSEL_SIGSEL_USART3RXDATAVRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART3, ///< Trig on USART3_RXDATAVRIGHT. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_USART3TXBL) dmadrvPeripheralSignal_USART3_TXBL = LDMA_CH_REQSEL_SIGSEL_USART3TXBL | LDMA_CH_REQSEL_SOURCESEL_USART3, ///< Trig on USART3_TXBL. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_USART3TXBLRIGHT) dmadrvPeripheralSignal_USART3_TXBLRIGHT = LDMA_CH_REQSEL_SIGSEL_USART3TXBLRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART3, ///< Trig on USART3_TXBLRIGHT. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_USART3TXEMPTY) dmadrvPeripheralSignal_USART3_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART3TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART3, ///< Trig on USART3_TXEMPTY. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_USART4RXDATAV) dmadrvPeripheralSignal_USART4_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART4RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART4, ///< Trig on USART4_RXDATAV. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_USART4RXDATAVRIGHT) dmadrvPeripheralSignal_USART4_RXDATAVRIGHT = LDMA_CH_REQSEL_SIGSEL_USART4RXDATAVRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART4, ///< Trig on USART4_RXDATAVRIGHT. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_USART4TXBL) dmadrvPeripheralSignal_USART4_TXBL = LDMA_CH_REQSEL_SIGSEL_USART4TXBL | LDMA_CH_REQSEL_SOURCESEL_USART4, ///< Trig on USART4_TXBL. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_USART4TXBLRIGHT) dmadrvPeripheralSignal_USART4_TXBLRIGHT = LDMA_CH_REQSEL_SIGSEL_USART4TXBLRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART4, ///< Trig on USART4_TXBLRIGHT. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_USART4TXEMPTY) dmadrvPeripheralSignal_USART4_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART4TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART4, ///< Trig on USART4_TXEMPTY. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_USART5RXDATAV) dmadrvPeripheralSignal_USART5_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART5RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART5, ///< Trig on USART5_RXDATAV. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_USART5RXDATAVRIGHT) dmadrvPeripheralSignal_USART5_RXDATAVRIGHT = LDMA_CH_REQSEL_SIGSEL_USART5RXDATAVRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART5, ///< Trig on USART5_RXDATAVRIGHT. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_USART5TXBL) dmadrvPeripheralSignal_USART5_TXBL = LDMA_CH_REQSEL_SIGSEL_USART5TXBL | LDMA_CH_REQSEL_SOURCESEL_USART5, ///< Trig on USART5_TXBL. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_USART5TXBLRIGHT) dmadrvPeripheralSignal_USART5_TXBLRIGHT = LDMA_CH_REQSEL_SIGSEL_USART5TXBLRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART5, ///< Trig on USART5_TXBLRIGHT. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_USART5TXEMPTY) dmadrvPeripheralSignal_USART5_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART5TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART5, ///< Trig on USART5_TXEMPTY. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_UART0RXDATAV) dmadrvPeripheralSignal_UART0_RXDATAV = LDMA_CH_REQSEL_SIGSEL_UART0RXDATAV | LDMA_CH_REQSEL_SOURCESEL_UART0, ///< Trig on UART0_RXDATAV. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_UART0TXBL) dmadrvPeripheralSignal_UART0_TXBL = LDMA_CH_REQSEL_SIGSEL_UART0TXBL | LDMA_CH_REQSEL_SOURCESEL_UART0, ///< Trig on UART0_TXBL. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_UART0TXEMPTY) dmadrvPeripheralSignal_UART0_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_UART0TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_UART0, ///< Trig on UART0_TXEMPTY. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_UART1RXDATAV) dmadrvPeripheralSignal_UART1_RXDATAV = LDMA_CH_REQSEL_SIGSEL_UART1RXDATAV | LDMA_CH_REQSEL_SOURCESEL_UART1, ///< Trig on UART1_RXDATAV. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_UART1TXBL) dmadrvPeripheralSignal_UART1_TXBL = LDMA_CH_REQSEL_SIGSEL_UART1TXBL | LDMA_CH_REQSEL_SOURCESEL_UART1, ///< Trig on UART1_TXBL. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_UART1TXEMPTY) dmadrvPeripheralSignal_UART1_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_UART1TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_UART1 ///< Trig on UART1_TXEMPTY. #endif } DMADRV_PeripheralSignal_t; #endif /// Data size of one LDMA transfer item. typedef enum { dmadrvDataSize1 = ldmaCtrlSizeByte, ///< Byte dmadrvDataSize2 = ldmaCtrlSizeHalf, ///< Halfword dmadrvDataSize4 = ldmaCtrlSizeWord ///< Word } DMADRV_DataSize_t; #endif /* defined( LDMA_PRESENT ) && ( LDMA_COUNT == 1 ) */ Ecode_t DMADRV_AllocateChannel(unsigned int *channelId, void *capabilities); Ecode_t DMADRV_DeInit(void); Ecode_t DMADRV_FreeChannel(unsigned int channelId); Ecode_t DMADRV_Init(void); #if !defined(EMDRV_DMADRV_USE_NATIVE_API) || defined(DOXY_DOC_ONLY) Ecode_t DMADRV_MemoryPeripheral(unsigned int channelId, DMADRV_PeripheralSignal_t peripheralSignal, void *dst, void *src, bool srcInc, int len, DMADRV_DataSize_t size, DMADRV_Callback_t callback, void *cbUserParam); Ecode_t DMADRV_PeripheralMemory(unsigned int channelId, DMADRV_PeripheralSignal_t peripheralSignal, void *dst, void *src, bool dstInc, int len, DMADRV_DataSize_t size, DMADRV_Callback_t callback, void *cbUserParam); Ecode_t DMADRV_MemoryPeripheralPingPong(unsigned int channelId, DMADRV_PeripheralSignal_t peripheralSignal, void *dst, void *src0, void *src1, bool srcInc, int len, DMADRV_DataSize_t size, DMADRV_Callback_t callback, void *cbUserParam); Ecode_t DMADRV_PeripheralMemoryPingPong(unsigned int channelId, DMADRV_PeripheralSignal_t peripheralSignal, void *dst0, void *dst1, void *src, bool dstInc, int len, DMADRV_DataSize_t size, DMADRV_Callback_t callback, void *cbUserParam); #endif #if defined(EMDRV_DMADRV_LDMA) && defined(EMDRV_DMADRV_USE_NATIVE_API) Ecode_t DMADRV_LdmaStartTransfer( int channelId, LDMA_TransferCfg_t *transfer, LDMA_Descriptor_t *descriptor, DMADRV_Callback_t callback, void *cbUserParam); #endif /* !defined( EMDRV_DMADRV_USE_NATIVE_API ) */ Ecode_t DMADRV_PauseTransfer(unsigned int channelId); Ecode_t DMADRV_ResumeTransfer(unsigned int channelId); Ecode_t DMADRV_StopTransfer(unsigned int channelId); Ecode_t DMADRV_TransferActive(unsigned int channelId, bool *active); Ecode_t DMADRV_TransferCompletePending(unsigned int channelId, bool *pending); Ecode_t DMADRV_TransferDone(unsigned int channelId, bool *done); Ecode_t DMADRV_TransferRemainingCount(unsigned int channelId, int *remaining); /** @} (end addtogroup DMADRV) */ /** @} (end addtogroup emdrv) */ #ifdef __cplusplus } #endif #endif /* __SILICON_LABS_DMADRV_H__ */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/emdrv/dmadrv/src/dmadrv.c.
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/***************************************************************************//** * @file * @brief DMADRV API implementation. ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * The licensor of this software is Silicon Laboratories Inc. Your use of this * software is governed by the terms of Silicon Labs Master Software License * Agreement (MSLA) available at * www.silabs.com/about-us/legal/master-software-license-agreement. This * software is distributed to you in Source Code format and is governed by the * sections of the MSLA applicable to Source Code. * ******************************************************************************/ #include <stdbool.h> #include <stddef.h> #include "em_device.h" #include "em_cmu.h" #include "em_core.h" #include "dmadrv.h" #if defined(EMDRV_DMADRV_UDMA) #include "dmactrl.h" #endif /// @cond DO_NOT_INCLUDE_WITH_DOXYGEN #if !defined(EMDRV_DMADRV_DMA_CH_COUNT) \ || (EMDRV_DMADRV_DMA_CH_COUNT > DMA_CHAN_COUNT) #define EMDRV_DMADRV_DMA_CH_COUNT DMA_CHAN_COUNT #endif typedef enum { dmaDirectionMemToPeripheral, dmaDirectionPeripheralToMem } DmaDirection_t; typedef enum { dmaModeBasic, dmaModePingPong } DmaMode_t; #if defined(EMDRV_DMADRV_USE_NATIVE_API) && defined(EMDRV_DMADRV_UDMA) typedef struct { bool allocated; } ChTable_t; #elif defined(EMDRV_DMADRV_USE_NATIVE_API) && defined(EMDRV_DMADRV_LDMA) typedef struct { DMADRV_Callback_t callback; void *userParam; unsigned int callbackCount; bool allocated; } ChTable_t; #else typedef struct { DMADRV_Callback_t callback; void *userParam; unsigned int callbackCount; #if defined(EMDRV_DMADRV_UDMA) int length; #endif bool allocated; #if defined(EMDRV_DMADRV_LDMA) DmaMode_t mode; #endif } ChTable_t; #endif static bool initialized = false; static ChTable_t chTable[EMDRV_DMADRV_DMA_CH_COUNT]; #if defined(EMDRV_DMADRV_UDMA) && !defined(EMDRV_DMADRV_USE_NATIVE_API) static DMA_CB_TypeDef dmaCallBack[EMDRV_DMADRV_DMA_CH_COUNT]; #endif #if defined(EMDRV_DMADRV_LDMA) && !defined(EMDRV_DMADRV_USE_NATIVE_API) const LDMA_TransferCfg_t xferCfg = LDMA_TRANSFER_CFG_PERIPHERAL(0); const LDMA_Descriptor_t m2p = LDMA_DESCRIPTOR_SINGLE_M2P_BYTE(NULL, NULL, 1UL); const LDMA_Descriptor_t p2m = LDMA_DESCRIPTOR_SINGLE_P2M_BYTE(NULL, NULL, 1UL); typedef struct { LDMA_Descriptor_t desc[2]; } DmaXfer_t; static DmaXfer_t dmaXfer[EMDRV_DMADRV_DMA_CH_COUNT]; #endif #if !defined(EMDRV_DMADRV_USE_NATIVE_API) static Ecode_t StartTransfer(DmaMode_t mode, DmaDirection_t direction, unsigned int channelId, DMADRV_PeripheralSignal_t peripheralSignal, void *buf0, void *buf1, void *buf2, bool bufInc, int len, DMADRV_DataSize_t size, DMADRV_Callback_t callback, void *cbUserParam); #endif /// @endcond /***************************************************************************//** * @brief * Allocate (reserve) a DMA channel. * * @param[out] channelId * The channel ID assigned by DMADRV. * * @param[in] capabilities * Not used. * * @return * @ref ECODE_EMDRV_DMADRV_OK on success. On failure, an appropriate * DMADRV @ref Ecode_t is returned. ******************************************************************************/ Ecode_t DMADRV_AllocateChannel(unsigned int *channelId, void *capabilities) { int i; (void)capabilities; CORE_DECLARE_IRQ_STATE; if ( !initialized ) { return ECODE_EMDRV_DMADRV_NOT_INITIALIZED; } if ( channelId == NULL ) { return ECODE_EMDRV_DMADRV_PARAM_ERROR; } CORE_ENTER_ATOMIC(); for ( i = 0; i < (int)EMDRV_DMADRV_DMA_CH_COUNT; i++ ) { if ( !chTable[i].allocated ) { *channelId = i; chTable[i].allocated = true; #if !defined(EMDRV_DMADRV_USE_NATIVE_API) || defined(EMDRV_DMADRV_LDMA) chTable[i].callback = NULL; #endif CORE_EXIT_ATOMIC(); return ECODE_EMDRV_DMADRV_OK; } } CORE_EXIT_ATOMIC(); return ECODE_EMDRV_DMADRV_CHANNELS_EXHAUSTED; } /***************************************************************************//** * @brief * Deinitialize DMADRV. * * @details * If DMA channels are not currently allocated, it will disable DMA hardware * and mask associated interrupts. * * @return * @ref ECODE_EMDRV_DMADRV_OK on success. On failure, an appropriate * DMADRV @ref Ecode_t is returned. ******************************************************************************/ Ecode_t DMADRV_DeInit(void) { int i; bool inUse; CORE_DECLARE_IRQ_STATE; inUse = false; CORE_ENTER_ATOMIC(); for ( i = 0; i < (int)EMDRV_DMADRV_DMA_CH_COUNT; i++ ) { if ( chTable[i].allocated ) { inUse = true; break; } } if ( !inUse ) { #if defined(EMDRV_DMADRV_UDMA) NVIC_DisableIRQ(DMA_IRQn); DMA->IEN = _DMA_IEN_RESETVALUE; DMA->CONFIG = _DMA_CONFIG_RESETVALUE; CMU_ClockEnable(cmuClock_DMA, false); #elif defined(EMDRV_DMADRV_LDMA) LDMA_DeInit(); #endif initialized = false; CORE_EXIT_ATOMIC(); return ECODE_EMDRV_DMADRV_OK; } CORE_EXIT_ATOMIC(); return ECODE_EMDRV_DMADRV_IN_USE; } /***************************************************************************//** * @brief * Free an allocated (reserved) DMA channel. * * @param[in] channelId * The channel ID to free. * * @return * @ref ECODE_EMDRV_DMADRV_OK on success. On failure, an appropriate * DMADRV @ref Ecode_t is returned. ******************************************************************************/ Ecode_t DMADRV_FreeChannel(unsigned int channelId) { CORE_DECLARE_IRQ_STATE; if ( !initialized ) { return ECODE_EMDRV_DMADRV_NOT_INITIALIZED; } if ( channelId >= EMDRV_DMADRV_DMA_CH_COUNT ) { return ECODE_EMDRV_DMADRV_PARAM_ERROR; } CORE_ENTER_ATOMIC(); if ( chTable[channelId].allocated ) { chTable[channelId].allocated = false; CORE_EXIT_ATOMIC(); return ECODE_EMDRV_DMADRV_OK; } CORE_EXIT_ATOMIC(); return ECODE_EMDRV_DMADRV_ALREADY_FREED; } /***************************************************************************//** * @brief * Initialize DMADRV. * * @details * The DMA hardware is initialized. * * @return * @ref ECODE_EMDRV_DMADRV_OK on success. On failure, an appropriate * DMADRV @ref Ecode_t is returned. ******************************************************************************/ Ecode_t DMADRV_Init(void) { int i; CORE_DECLARE_IRQ_STATE; #if defined(EMDRV_DMADRV_UDMA) DMA_Init_TypeDef dmaInit; #elif defined(EMDRV_DMADRV_LDMA) LDMA_Init_t dmaInit = LDMA_INIT_DEFAULT; dmaInit.ldmaInitCtrlNumFixed = EMDRV_DMADRV_DMA_CH_PRIORITY; #endif CORE_ENTER_ATOMIC(); if ( initialized ) { CORE_EXIT_ATOMIC(); return ECODE_EMDRV_DMADRV_ALREADY_INITIALIZED; } initialized = true; CORE_EXIT_ATOMIC(); if ( EMDRV_DMADRV_DMA_IRQ_PRIORITY > 7 ) { return ECODE_EMDRV_DMADRV_PARAM_ERROR; } for ( i = 0; i < (int)EMDRV_DMADRV_DMA_CH_COUNT; i++ ) { chTable[i].allocated = false; } #if defined(EMDRV_DMADRV_UDMA) NVIC_SetPriority(DMA_IRQn, EMDRV_DMADRV_DMA_IRQ_PRIORITY); dmaInit.hprot = 0; dmaInit.controlBlock = dmaControlBlock; DMA_Init(&dmaInit); #elif defined(EMDRV_DMADRV_LDMA) dmaInit.ldmaInitIrqPriority = EMDRV_DMADRV_DMA_IRQ_PRIORITY; LDMA_Init(&dmaInit); #endif return ECODE_EMDRV_DMADRV_OK; } #if defined(EMDRV_DMADRV_LDMA) && defined(EMDRV_DMADRV_USE_NATIVE_API) /***************************************************************************//** * @brief * Start an LDMA transfer. * * @details * This function can only be used on LDMA when @ref EMDRV_DMADRV_USE_NATIVE_API * is defined. It is a wrapper similar to emlib LDMA function. * * @param[in] channelId * The channel ID to use. * * @param[in] transfer * A DMA transfer configuration data structure. * * @param[in] descriptor * A DMA transfer descriptor, can be an array of descriptors linked together. * * @param[in] callback * An optional callback function for signalling completion. May be NULL if not * needed. * * @param[in] cbUserParam * An optional user parameter to feed to the callback function. May be NULL if * not needed. * * @return * @ref ECODE_EMDRV_DMADRV_OK on success. On failure, an appropriate * DMADRV @ref Ecode_t is returned. ******************************************************************************/ Ecode_t DMADRV_LdmaStartTransfer(int channelId, LDMA_TransferCfg_t *transfer, LDMA_Descriptor_t *descriptor, DMADRV_Callback_t callback, void *cbUserParam) { ChTable_t *ch; if ( !initialized ) { return ECODE_EMDRV_DMADRV_NOT_INITIALIZED; } if ( channelId >= (int)EMDRV_DMADRV_DMA_CH_COUNT ) { return ECODE_EMDRV_DMADRV_PARAM_ERROR; } ch = &chTable[channelId]; if ( ch->allocated == false ) { return ECODE_EMDRV_DMADRV_CH_NOT_ALLOCATED; } ch->callback = callback; ch->userParam = cbUserParam; ch->callbackCount = 0; LDMA_StartTransfer(channelId, transfer, descriptor); return ECODE_EMDRV_DMADRV_OK; } #endif #if !defined(EMDRV_DMADRV_USE_NATIVE_API) || defined(DOXY_DOC_ONLY) /***************************************************************************//** * @brief * Start a memory to a peripheral DMA transfer. * * @param[in] channelId * The channel ID to use for the transfer. * * @param[in] peripheralSignal * Selects which peripheral/peripheralsignal to use. * * @param[in] dst * A destination (peripheral register) memory address. * * @param[in] src * A source memory address. * * @param[in] srcInc * Set to true to enable source address increment (increments according to * @a size parameter). * * @param[in] len * A number of items (of @a size size) to transfer. * * @param[in] size * An item size, byte, halfword or word. * * @param[in] callback * A function to call on DMA completion, use NULL if not needed. * * @param[in] cbUserParam * An optional user parameter to feed to the callback function. Use NULL if * not needed. * * @return * @ref ECODE_EMDRV_DMADRV_OK on success. On failure, an appropriate * DMADRV @ref Ecode_t is returned. ******************************************************************************/ Ecode_t DMADRV_MemoryPeripheral(unsigned int channelId, DMADRV_PeripheralSignal_t peripheralSignal, void *dst, void *src, bool srcInc, int len, DMADRV_DataSize_t size, DMADRV_Callback_t callback, void *cbUserParam) { return StartTransfer(dmaModeBasic, dmaDirectionMemToPeripheral, channelId, peripheralSignal, dst, src, NULL, srcInc, len, size, callback, cbUserParam); } #endif #if !defined(EMDRV_DMADRV_USE_NATIVE_API) || defined(DOXY_DOC_ONLY) /***************************************************************************//** * @brief * Start a memory to a peripheral ping-pong DMA transfer. * * @param[in] channelId * The channel ID to use for the transfer. * * @param[in] peripheralSignal * Selects which peripheral/peripheralsignal to use. * * @param[in] dst * A destination (peripheral register) memory address. * * @param[in] src0 * A source memory address of the first (ping) buffer. * * @param[in] src1 * A source memory address of the second (pong) buffer. * * @param[in] srcInc * Set to true to enable source address increment (increments according to * @a size parameter). * * @param[in] len * A number of items (of @a size size) to transfer. * * @param[in] size * An item size, byte, halfword or word. * * @param[in] callback * A function to call on DMA completion, use NULL if not needed. * * @param[in] cbUserParam * An optional user parameter to feed to the callback function. Use NULL if * not needed. * * @return * @ref ECODE_EMDRV_DMADRV_OK on success. On failure, an appropriate * DMADRV @ref Ecode_t is returned. ******************************************************************************/ Ecode_t DMADRV_MemoryPeripheralPingPong( unsigned int channelId, DMADRV_PeripheralSignal_t peripheralSignal, void *dst, void *src0, void *src1, bool srcInc, int len, DMADRV_DataSize_t size, DMADRV_Callback_t callback, void *cbUserParam) { return StartTransfer(dmaModePingPong, dmaDirectionMemToPeripheral, channelId, peripheralSignal, dst, src0, src1, srcInc, len, size, callback, cbUserParam); } #endif #if !defined(EMDRV_DMADRV_USE_NATIVE_API) || defined(DOXY_DOC_ONLY) /***************************************************************************//** * @brief * Start a peripheral to memory DMA transfer. * * @param[in] channelId * The channel ID to use for the transfer. * * @param[in] peripheralSignal * Selects which peripheral/peripheralsignal to use. * * @param[in] dst * A destination memory address. * * @param[in] src * A source memory (peripheral register) address. * * @param[in] dstInc * Set to true to enable destination address increment (increments according * to @a size parameter). * * @param[in] len * A number of items (of @a size size) to transfer. * * @param[in] size * An item size, byte, halfword or word. * * @param[in] callback * A function to call on DMA completion, use NULL if not needed. * * @param[in] cbUserParam * An optional user parameter to feed to the callback function. Use NULL if * not needed. * * @return * @ref ECODE_EMDRV_DMADRV_OK on success. On failure, an appropriate * DMADRV @ref Ecode_t is returned. ******************************************************************************/ Ecode_t DMADRV_PeripheralMemory(unsigned int channelId, DMADRV_PeripheralSignal_t peripheralSignal, void *dst, void *src, bool dstInc, int len, DMADRV_DataSize_t size, DMADRV_Callback_t callback, void *cbUserParam) { return StartTransfer(dmaModeBasic, dmaDirectionPeripheralToMem, channelId, peripheralSignal, dst, src, NULL, dstInc, len, size, callback, cbUserParam); } #endif #if !defined(EMDRV_DMADRV_USE_NATIVE_API) || defined(DOXY_DOC_ONLY) /***************************************************************************//** * @brief * Start a peripheral to memory ping-pong DMA transfer. * * @param[in] channelId * The channel ID to use for the transfer. * * @param[in] peripheralSignal * Selects which peripheral/peripheralsignal to use. * * @param[in] dst0 * A destination memory address of the first (ping) buffer. * * @param[in] dst1 * A destination memory address of the second (pong) buffer. * * @param[in] src * A source memory (peripheral register) address. * * @param[in] dstInc * Set to true to enable destination address increment (increments according * to @a size parameter). * * @param[in] len * A number of items (of @a size size) to transfer. * * @param[in] size * An item size, byte, halfword or word. * * @param[in] callback * A function to call on DMA completion, use NULL if not needed. * * @param[in] cbUserParam * An optional user parameter to feed to the callback function. Use NULL if * not needed. * * @return * @ref ECODE_EMDRV_DMADRV_OK on success. On failure, an appropriate * DMADRV @ref Ecode_t is returned. ******************************************************************************/ Ecode_t DMADRV_PeripheralMemoryPingPong( unsigned int channelId, DMADRV_PeripheralSignal_t peripheralSignal, void *dst0, void *dst1, void *src, bool dstInc, int len, DMADRV_DataSize_t size, DMADRV_Callback_t callback, void *cbUserParam) { return StartTransfer(dmaModePingPong, dmaDirectionPeripheralToMem, channelId, peripheralSignal, dst0, dst1, src, dstInc, len, size, callback, cbUserParam); } #endif /* !defined( EMDRV_DMADRV_USE_NATIVE_API ) */ /***************************************************************************//** * @brief * Pause an ongoing DMA transfer. * * @param[in] channelId * The channel ID of the transfer to pause. * * @return * @ref ECODE_EMDRV_DMADRV_OK on success. On failure, an appropriate * DMADRV @ref Ecode_t is returned. ******************************************************************************/ Ecode_t DMADRV_PauseTransfer(unsigned int channelId) { if ( !initialized ) { return ECODE_EMDRV_DMADRV_NOT_INITIALIZED; } if ( channelId >= EMDRV_DMADRV_DMA_CH_COUNT ) { return ECODE_EMDRV_DMADRV_PARAM_ERROR; } if ( chTable[channelId].allocated == false ) { return ECODE_EMDRV_DMADRV_CH_NOT_ALLOCATED; } #if defined(EMDRV_DMADRV_UDMA) DMA_ChannelRequestEnable(channelId, false); #elif defined(EMDRV_DMADRV_LDMA) LDMA_EnableChannelRequest(channelId, false); #endif return ECODE_EMDRV_DMADRV_OK; } /***************************************************************************//** * @brief * Resume an ongoing DMA transfer. * * @param[in] channelId * The channel ID of the transfer to resume. * * @return * @ref ECODE_EMDRV_DMADRV_OK on success. On failure, an appropriate * DMADRV @ref Ecode_t is returned. ******************************************************************************/ Ecode_t DMADRV_ResumeTransfer(unsigned int channelId) { if ( !initialized ) { return ECODE_EMDRV_DMADRV_NOT_INITIALIZED; } if ( channelId >= EMDRV_DMADRV_DMA_CH_COUNT ) { return ECODE_EMDRV_DMADRV_PARAM_ERROR; } if ( chTable[channelId].allocated == false ) { return ECODE_EMDRV_DMADRV_CH_NOT_ALLOCATED; } #if defined(EMDRV_DMADRV_UDMA) DMA_ChannelRequestEnable(channelId, true); #elif defined(EMDRV_DMADRV_LDMA) LDMA_EnableChannelRequest(channelId, true); #endif return ECODE_EMDRV_DMADRV_OK; } /***************************************************************************//** * @brief * Stop an ongoing DMA transfer. * * @param[in] channelId * The channel ID of the transfer to stop. * * @return * @ref ECODE_EMDRV_DMADRV_OK on success. On failure, an appropriate * DMADRV @ref Ecode_t is returned. ******************************************************************************/ Ecode_t DMADRV_StopTransfer(unsigned int channelId) { if ( !initialized ) { return ECODE_EMDRV_DMADRV_NOT_INITIALIZED; } if ( channelId >= EMDRV_DMADRV_DMA_CH_COUNT ) { return ECODE_EMDRV_DMADRV_PARAM_ERROR; } if ( chTable[channelId].allocated == false ) { return ECODE_EMDRV_DMADRV_CH_NOT_ALLOCATED; } #if defined(EMDRV_DMADRV_UDMA) DMA_ChannelEnable(channelId, false); #elif defined(EMDRV_DMADRV_LDMA) LDMA_StopTransfer(channelId); #endif return ECODE_EMDRV_DMADRV_OK; } /***************************************************************************//** * @brief * Check if a transfer is running. * * @param[in] channelId * The channel ID of the transfer to check. * * @param[out] active * True if transfer is running, false otherwise. * * @return * @ref ECODE_EMDRV_DMADRV_OK on success. On failure, an appropriate * DMADRV @ref Ecode_t is returned. ******************************************************************************/ Ecode_t DMADRV_TransferActive(unsigned int channelId, bool *active) { if ( !initialized ) { return ECODE_EMDRV_DMADRV_NOT_INITIALIZED; } if ( (channelId >= EMDRV_DMADRV_DMA_CH_COUNT) || (active == NULL) ) { return ECODE_EMDRV_DMADRV_PARAM_ERROR; } if ( chTable[channelId].allocated == false ) { return ECODE_EMDRV_DMADRV_CH_NOT_ALLOCATED; } #if defined(EMDRV_DMADRV_UDMA) if ( DMA_ChannelEnabled(channelId) ) #elif defined(EMDRV_DMADRV_LDMA) if ( LDMA_ChannelEnabled(channelId) ) #endif { *active = true; } else { *active = false; } return ECODE_EMDRV_DMADRV_OK; } /***************************************************************************//** * @brief * Check if a transfer complete is pending. * * @details * Will check the channel interrupt flag. This assumes that the DMA is configured * to give a completion interrupt. * * @param[in] channelId * The channel ID of the transfer to check. * * @param[out] pending * True if a transfer complete is pending, false otherwise. * * @return * @ref ECODE_EMDRV_DMADRV_OK on success. On failure, an appropriate * DMADRV @ref Ecode_t is returned. ******************************************************************************/ Ecode_t DMADRV_TransferCompletePending(unsigned int channelId, bool *pending) { if ( !initialized ) { return ECODE_EMDRV_DMADRV_NOT_INITIALIZED; } if ( (channelId >= EMDRV_DMADRV_DMA_CH_COUNT) || (pending == NULL) ) { return ECODE_EMDRV_DMADRV_PARAM_ERROR; } if ( chTable[channelId].allocated == false ) { return ECODE_EMDRV_DMADRV_CH_NOT_ALLOCATED; } #if defined(EMDRV_DMADRV_UDMA) if ( DMA->IF & (1 << channelId) ) #elif defined(EMDRV_DMADRV_LDMA) if ( LDMA->IF & (1 << channelId) ) #endif { *pending = true; } else { *pending = false; } return ECODE_EMDRV_DMADRV_OK; } /***************************************************************************//** * @brief * Check if a transfer has completed. * * @note * This function should be used in a polled environment. * Will only work reliably for transfers NOT using the completion interrupt. * On UDMA, it will only work on basic transfers on the primary channel. * * @param[in] channelId * The channel ID of the transfer to check. * * @param[out] done * True if a transfer has completed, false otherwise. * * @return * @ref ECODE_EMDRV_DMADRV_OK on success. On failure, an appropriate * DMADRV @ref Ecode_t is returned. ******************************************************************************/ Ecode_t DMADRV_TransferDone(unsigned int channelId, bool *done) { #if defined(EMDRV_DMADRV_UDMA) uint32_t remaining, iflag; #endif if ( !initialized ) { return ECODE_EMDRV_DMADRV_NOT_INITIALIZED; } if ( (channelId >= EMDRV_DMADRV_DMA_CH_COUNT) || (done == NULL) ) { return ECODE_EMDRV_DMADRV_PARAM_ERROR; } if ( chTable[channelId].allocated == false ) { return ECODE_EMDRV_DMADRV_CH_NOT_ALLOCATED; } #if defined(EMDRV_DMADRV_UDMA) CORE_ATOMIC_SECTION( /* This works for primary channel only ! */ remaining = (dmaControlBlock[channelId].CTRL & _DMA_CTRL_N_MINUS_1_MASK) >> _DMA_CTRL_N_MINUS_1_SHIFT; iflag = DMA->IF; ) if ( (remaining == 0) && (iflag & (1 << channelId)) ) { *done = true; } else { *done = false; } #elif defined(EMDRV_DMADRV_LDMA) *done = LDMA_TransferDone(channelId); #endif return ECODE_EMDRV_DMADRV_OK; } /***************************************************************************//** * @brief * Get number of items remaining in a transfer. * * @note * This function does not take into account that a DMA transfer with * a chain of linked transfers might be ongoing. It will only check the * count for the current transfer. * On UDMA, it will only work on the primary channel. * * @param[in] channelId * The channel ID of the transfer to check. * * @param[out] remaining * A number of items remaining in the transfer. * * @return * @ref ECODE_EMDRV_DMADRV_OK on success. On failure, an appropriate * DMADRV @ref Ecode_t is returned. ******************************************************************************/ Ecode_t DMADRV_TransferRemainingCount(unsigned int channelId, int *remaining) { #if defined(EMDRV_DMADRV_UDMA) uint32_t remain, iflag; #endif if ( !initialized ) { return ECODE_EMDRV_DMADRV_NOT_INITIALIZED; } if ( (channelId >= EMDRV_DMADRV_DMA_CH_COUNT) || (remaining == NULL) ) { return ECODE_EMDRV_DMADRV_PARAM_ERROR; } if ( chTable[channelId].allocated == false ) { return ECODE_EMDRV_DMADRV_CH_NOT_ALLOCATED; } #if defined(EMDRV_DMADRV_UDMA) CORE_ATOMIC_SECTION( /* This works for the primary channel only ! */ remain = (dmaControlBlock[channelId].CTRL & _DMA_CTRL_N_MINUS_1_MASK) >> _DMA_CTRL_N_MINUS_1_SHIFT; iflag = DMA->IF; ) if ( (remain == 0) && (iflag & (1 << channelId)) ) { *remaining = 0; } else { *remaining = 1 + remain; } #elif defined(EMDRV_DMADRV_LDMA) *remaining = LDMA_TransferRemainingCount(channelId); #endif return ECODE_EMDRV_DMADRV_OK; } /// @cond DO_NOT_INCLUDE_WITH_DOXYGEN #if defined(EMDRV_DMADRV_LDMA) /***************************************************************************//** * @brief * An interrupt handler for LDMA. ******************************************************************************/ void LDMA_IRQHandler(void) { #if !defined(EMDRV_DMADRV_USE_NATIVE_API) bool stop; #endif ChTable_t *ch; uint32_t pending, chnum, chmask; /* Get all pending and enabled interrupts. */ pending = LDMA->IF; pending &= LDMA->IEN; /* Check for LDMA error. */ if ( pending & LDMA_IF_ERROR ) { /* Loop to enable debugger to see what has happened. */ while (true) { /* Wait forever. */ } } /* Iterate over all LDMA channels. */ for ( chnum = 0, chmask = 1; chnum < EMDRV_DMADRV_DMA_CH_COUNT; chnum++, chmask <<= 1 ) { if ( pending & chmask ) { /* Clear the interrupt flag. */ #if defined (LDMA_HAS_SET_CLEAR) LDMA->IF_CLR = chmask; #else LDMA->IFC = chmask; #endif ch = &chTable[chnum]; if ( ch->callback != NULL ) { ch->callbackCount++; #if defined(EMDRV_DMADRV_USE_NATIVE_API) ch->callback(chnum, ch->callbackCount, ch->userParam); #else stop = !ch->callback(chnum, ch->callbackCount, ch->userParam); if ( (ch->mode == dmaModePingPong) && stop ) { dmaXfer[chnum].desc[0].xfer.link = 0; dmaXfer[chnum].desc[1].xfer.link = 0; } #endif } } } } #endif /* defined( EMDRV_DMADRV_LDMA ) */ #if defined(EMDRV_DMADRV_UDMA) && !defined(EMDRV_DMADRV_USE_NATIVE_API) /***************************************************************************//** * @brief * A callback function for UDMA basic transfers. ******************************************************************************/ static void DmaBasicCallback(unsigned int channel, bool primary, void *user) { ChTable_t *ch = &chTable[channel]; (void)user; (void)primary; if ( ch->callback != NULL ) { ch->callbackCount++; ch->callback(channel, ch->callbackCount, ch->userParam); } } #endif #if defined(EMDRV_DMADRV_UDMA) && !defined(EMDRV_DMADRV_USE_NATIVE_API) /***************************************************************************//** * @brief * A callback function for UDMA ping-pong transfers. ******************************************************************************/ static void DmaPingPongCallback(unsigned int channel, bool primary, void *user) { bool stop = true; ChTable_t *ch = &chTable[channel]; (void)user; if ( ch->callback != NULL ) { ch->callbackCount++; stop = !ch->callback(channel, ch->callbackCount, ch->userParam); } DMA_RefreshPingPong(channel, primary, false, NULL, NULL, ch->length - 1, stop); } #endif #if defined(EMDRV_DMADRV_UDMA) && !defined(EMDRV_DMADRV_USE_NATIVE_API) /***************************************************************************//** * @brief * Start a UDMA transfer. ******************************************************************************/ static Ecode_t StartTransfer(DmaMode_t mode, DmaDirection_t direction, unsigned int channelId, DMADRV_PeripheralSignal_t peripheralSignal, void *buf0, void *buf1, void *buf2, bool bufInc, int len, DMADRV_DataSize_t size, DMADRV_Callback_t callback, void *cbUserParam) { ChTable_t *ch; DMA_CfgChannel_TypeDef chCfg; DMA_CfgDescr_TypeDef descrCfg; if ( !initialized ) { return ECODE_EMDRV_DMADRV_NOT_INITIALIZED; } if ( (channelId >= EMDRV_DMADRV_DMA_CH_COUNT) || (buf0 == NULL) || (buf1 == NULL) || (len > DMADRV_MAX_XFER_COUNT) || ((mode == dmaModePingPong) && (buf2 == NULL)) ) { return ECODE_EMDRV_DMADRV_PARAM_ERROR; } ch = &chTable[channelId]; if ( ch->allocated == false ) { return ECODE_EMDRV_DMADRV_CH_NOT_ALLOCATED; } /* Se tup the interrupt callback routine. */ if ( mode == dmaModeBasic ) { dmaCallBack[channelId].cbFunc = DmaBasicCallback; } else { dmaCallBack[channelId].cbFunc = DmaPingPongCallback; } dmaCallBack[channelId].userPtr = NULL; /* Set up the channel */ chCfg.highPri = false; /* Can't use hi pri with peripherals. */ /* Whether the interrupt is needed. */ if ( (callback != NULL) || (mode == dmaModePingPong) ) { chCfg.enableInt = true; } else { chCfg.enableInt = false; } chCfg.select = peripheralSignal; chCfg.cb = &dmaCallBack[channelId]; DMA_CfgChannel(channelId, &chCfg); /* Set up the channel descriptor. */ if ( direction == dmaDirectionMemToPeripheral ) { if ( bufInc ) { if ( size == dmadrvDataSize1 ) { descrCfg.srcInc = dmaDataInc1; } else if ( size == dmadrvDataSize2 ) { descrCfg.srcInc = dmaDataInc2; } else { /* dmadrvDataSize4 */ descrCfg.srcInc = dmaDataInc4; } } else { descrCfg.srcInc = dmaDataIncNone; } descrCfg.dstInc = dmaDataIncNone; } else { if ( bufInc ) { if ( size == dmadrvDataSize1 ) { descrCfg.dstInc = dmaDataInc1; } else if ( size == dmadrvDataSize2 ) { descrCfg.dstInc = dmaDataInc2; } else { /* dmadrvDataSize4 */ descrCfg.dstInc = dmaDataInc4; } } else { descrCfg.dstInc = dmaDataIncNone; } descrCfg.srcInc = dmaDataIncNone; } descrCfg.size = (DMA_DataSize_TypeDef)size; descrCfg.arbRate = dmaArbitrate1; descrCfg.hprot = 0; DMA_CfgDescr(channelId, true, &descrCfg); if ( mode == dmaModePingPong ) { DMA_CfgDescr(channelId, false, &descrCfg); } ch->callback = callback; ch->userParam = cbUserParam; ch->callbackCount = 0; ch->length = len; DMA->IFC = 1 << channelId; /* Start the DMA cycle. */ if ( mode == dmaModeBasic ) { DMA_ActivateBasic(channelId, true, false, buf0, buf1, len - 1); } else { if ( direction == dmaDirectionMemToPeripheral ) { DMA_ActivatePingPong(channelId, false, buf0, /* dest */ buf1, /* src */ len - 1, buf0, /* dest */ buf2, /* src */ len - 1); } else { DMA_ActivatePingPong(channelId, false, buf0, /* dest */ buf2, /* src */ len - 1, buf1, /* dest */ buf2, /* src */ len - 1); } } return ECODE_EMDRV_DMADRV_OK; } #endif /* defined( EMDRV_DMADRV_UDMA ) && !defined( EMDRV_DMADRV_USE_NATIVE_API ) */ #if defined(EMDRV_DMADRV_LDMA) && !defined(EMDRV_DMADRV_USE_NATIVE_API) /***************************************************************************//** * @brief * Start an LDMA transfer. ******************************************************************************/ static Ecode_t StartTransfer(DmaMode_t mode, DmaDirection_t direction, unsigned int channelId, DMADRV_PeripheralSignal_t peripheralSignal, void *buf0, void *buf1, void *buf2, bool bufInc, int len, DMADRV_DataSize_t size, DMADRV_Callback_t callback, void *cbUserParam) { ChTable_t *ch; LDMA_TransferCfg_t xfer; LDMA_Descriptor_t *desc; if ( !initialized ) { return ECODE_EMDRV_DMADRV_NOT_INITIALIZED; } if ( (channelId >= EMDRV_DMADRV_DMA_CH_COUNT) || (buf0 == NULL) || (buf1 == NULL) || (len > DMADRV_MAX_XFER_COUNT) || ((mode == dmaModePingPong) && (buf2 == NULL)) ) { return ECODE_EMDRV_DMADRV_PARAM_ERROR; } ch = &chTable[channelId]; if ( ch->allocated == false ) { return ECODE_EMDRV_DMADRV_CH_NOT_ALLOCATED; } xfer = xferCfg; desc = &dmaXfer[channelId].desc[0]; if ( direction == dmaDirectionMemToPeripheral ) { *desc = m2p; if ( !bufInc ) { desc->xfer.srcInc = ldmaCtrlSrcIncNone; } } else { *desc = p2m; if ( !bufInc ) { desc->xfer.dstInc = ldmaCtrlDstIncNone; } } xfer.ldmaReqSel = peripheralSignal; desc->xfer.xferCnt = len - 1; desc->xfer.dstAddr = (uint32_t)(uint8_t *)buf0; desc->xfer.srcAddr = (uint32_t)(uint8_t *)buf1; desc->xfer.size = size; if ( mode == dmaModePingPong ) { desc->xfer.linkMode = ldmaLinkModeRel; desc->xfer.link = 1; desc->xfer.linkAddr = 4; /* Refer to the "pong" descriptor. */ /* Set the "pong" descriptor equal to the "ping" descriptor. */ dmaXfer[channelId].desc[1] = *desc; /* Refer to the "ping" descriptor. */ dmaXfer[channelId].desc[1].xfer.linkAddr = -4; dmaXfer[channelId].desc[1].xfer.srcAddr = (uint32_t)(uint8_t *)buf2; if ( direction == dmaDirectionPeripheralToMem ) { dmaXfer[channelId].desc[1].xfer.dstAddr = (uint32_t)(uint8_t *)buf1; desc->xfer.srcAddr = (uint32_t)(uint8_t *)buf2; } } /* Whether an interrupt is needed. */ if ( (callback == NULL) && (mode == dmaModeBasic) ) { desc->xfer.doneIfs = 0; } ch->callback = callback; ch->userParam = cbUserParam; ch->callbackCount = 0; ch->mode = mode; LDMA_StartTransfer(channelId, &xfer, desc); return ECODE_EMDRV_DMADRV_OK; } #endif /* defined( EMDRV_DMADRV_LDMA ) && !defined( EMDRV_DMADRV_USE_NATIVE_API ) */ /// @endcond /******** THE REST OF THE FILE IS DOCUMENTATION ONLY !**********************//** * @addtogroup emdrv * @{ * @addtogroup DMADRV * @brief DMADRV Direct Memory Access Driver * @{ @details @li @ref dmadrv_intro @li @ref dmadrv_conf @li @ref dmadrv_api @li @ref dmadrv_example @n @section dmadrv_intro Introduction The DMADRV driver supports writing code using DMA which will work regardless of the type of the DMA controller on the underlying microcontroller. Additionally, DMA can be used in several modules that are completely unaware of each other. The driver does not preclude use of the native emlib API of the underlying DMA controller. On the contrary, it will often result in more efficient code and is necessary for complex DMA operations. The housekeeping functions of this driver are valuable even in this use-case. The dmadrv.c and dmadrv.h source files are in the emdrv/dmadrv folder. @note DMA transfer completion callback functions are called from within the DMA interrupt handler. @n @section dmadrv_conf Configuration Options Some properties of the DMADRV driver are compile-time configurable. These properties are stored in a file named @ref dmadrv_config.h. A template for this file, containing default values, is in the emdrv/config folder. Currently the configuration options are as follows: @li The interrupt priority of the DMA peripheral. @li A number of DMA channels to support. @li Use the native emlib API belonging to the underlying DMA hardware in combination with the DMADRV API. Both configuration options will help reduce the driver's RAM footprint. To configure DMADRV, provide a custom configuration file. This is an example @ref dmadrv_config.h file: @verbatim #ifndef __SILICON_LABS_DMADRV_CONFIG_H__ #define __SILICON_LABS_DMADRV_CONFIG_H__ // DMADRV DMA interrupt priority configuration option. // Set DMA interrupt priority. Range is 0..7, 0 is the highest priority. #define EMDRV_DMADRV_DMA_IRQ_PRIORITY 4 // DMADRV channel count configuration option. // A number of DMA channels to support. A lower DMA channel count will reduce // RAM footprint. #define EMDRV_DMADRV_DMA_CH_COUNT 4 // DMADRV native API configuration option. // Use the native emlib API of the DMA controller in addition to DMADRV // housekeeping functions, such as AllocateChannel/FreeChannel, and so on. #define EMDRV_DMADRV_USE_NATIVE_API #endif @endverbatim @n @section dmadrv_api The API This section contains brief descriptions of the API functions. For more information about input and output parameters and return values, click on the hyperlinked function names. Most functions return an error code, @ref ECODE_EMDRV_DMADRV_OK is returned on success, see @ref ecode.h and @ref dmadrv.h for other error codes. The application code must include @em dmadrv.h header file. @ref DMADRV_Init(), @ref DMADRV_DeInit() @n These functions initialize or deinitialize the DMADRV driver. Typically, @htmlonly DMADRV_Init() @endhtmlonly is called once in the startup code. @ref DMADRV_AllocateChannel(), @ref DMADRV_FreeChannel() @n DMA channel reserve and release functions. It is recommended that application code check that @htmlonly DMADRV_AllocateChannel() @endhtmlonly returns @htmlonly ECODE_EMDRV_DMADRV_OK @endhtmlonly before starting a DMA transfer. @ref DMADRV_MemoryPeripheral() @n Start a DMA transfer from memory to a peripheral. @ref DMADRV_PeripheralMemory() @n Start a DMA transfer from a peripheral to memory. @ref DMADRV_MemoryPeripheralPingPong() @n Start a DMA ping-pong transfer from memory to a peripheral. @ref DMADRV_PeripheralMemoryPingPong() @n Start a DMA ping-pong transfer from a peripheral to memory. @ref DMADRV_LdmaStartTransfer() @n Start a DMA transfer on an LDMA controller. This function can only be used when configuration option @ref EMDRV_DMADRV_USE_NATIVE_API is defined. It is a wrapper similar to the emlib LDMA function, but adds support for completion callback and user-defined callback function parameter. @ref DMADRV_StopTransfer() @n Stop an ongoing DMA transfer. @ref DMADRV_TransferActive() @n Check if a transfer is ongoing. @ref DMADRV_TransferCompletePending() @n Check if a transfer completion is pending. @ref DMADRV_TransferDone() @n Check if a transfer has completed. @ref DMADRV_TransferRemainingCount() @n Get number of items remaining in a transfer. @n @section dmadrv_example Example Transfer a text string to USART1. @verbatim #include "dmadrv.h" char str[] = "Hello DMA !"; unsigned int channel; int main( void ) { // Initialize DMA. DMADRV_Init(); // Request a DMA channel. DMADRV_AllocateChannel( &channel, NULL ); // Start the DMA transfer. DMADRV_MemoryPeripheral( channel, dmadrvPeripheralSignal_USART1_TXBL, (void*)&(USART1->TXDATA), str, true, sizeof( str ), dmadrvDataSize1, NULL, NULL ); return 0; } @endverbatim * @} end group DMADRV ******************************************************** * @} end group emdrv ****************************************************/ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/emdrv/gpiointerrupt/inc/gpiointerrupt.h.
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/***************************************************************************//** * @file * @brief GPIOINT API definition ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * The licensor of this software is Silicon Laboratories Inc. Your use of this * software is governed by the terms of Silicon Labs Master Software License * Agreement (MSLA) available at * www.silabs.com/about-us/legal/master-software-license-agreement. This * software is distributed to you in Source Code format and is governed by the * sections of the MSLA applicable to Source Code. * ******************************************************************************/ #ifndef GPIOINTERRUPT_H #define GPIOINTERRUPT_H #include "em_device.h" #ifdef __cplusplus extern "C" { #endif /***************************************************************************//** * @addtogroup emdrv * @{ ******************************************************************************/ /***************************************************************************//** * @addtogroup GPIOINT * @{ ******************************************************************************/ /******************************************************************************* ******************************* TYPEDEFS ********************************** ******************************************************************************/ /** * @brief * GPIO interrupt callback function pointer. * @details * Parameters: * @li intNo - The pin interrupt number the callback function is invoked for. */ typedef void (*GPIOINT_IrqCallbackPtr_t)(uint8_t intNo); /******************************************************************************* ****************************** PROTOTYPES ********************************* ******************************************************************************/ void GPIOINT_Init(void); void GPIOINT_CallbackRegister(uint8_t intNo, GPIOINT_IrqCallbackPtr_t callbackPtr); static __INLINE void GPIOINT_CallbackUnRegister(uint8_t intNo); /***************************************************************************//** * @brief * Unregisters user callback for given pin interrupt number. * * @details * Use this function to unregister a callback. * * @param[in] intNo * Pin interrupt number for the callback. * ******************************************************************************/ static __INLINE void GPIOINT_CallbackUnRegister(uint8_t intNo) { GPIOINT_CallbackRegister(intNo, 0); } /** @} (end addtogroup GPIOINT */ /** @} (end addtogroup emdrv) */ #ifdef __cplusplus } #endif #endif /* GPIOINTERRUPT_H */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/emdrv/gpiointerrupt/src/gpiointerrupt.c.
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/***************************************************************************//** * @file * @brief GPIOINT API implementation ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * The licensor of this software is Silicon Laboratories Inc. Your use of this * software is governed by the terms of Silicon Labs Master Software License * Agreement (MSLA) available at * www.silabs.com/about-us/legal/master-software-license-agreement. This * software is distributed to you in Source Code format and is governed by the * sections of the MSLA applicable to Source Code. * ******************************************************************************/ #include "em_gpio.h" #include "em_core.h" #include "gpiointerrupt.h" #include "em_assert.h" #include "em_common.h" /******************************************************************************* ******************************** MACROS *********************************** ******************************************************************************/ /******************************************************************************* ******************************* STRUCTS *********************************** ******************************************************************************/ /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ typedef struct { /* Pin interrupt number in range of 0 to 15 */ uint32_t intNo; /* Pointer to the callback function */ GPIOINT_IrqCallbackPtr_t callback; } GPIOINT_CallbackDesc_t; /******************************************************************************* ******************************** GLOBALS ********************************** ******************************************************************************/ /* Array of user callbacks. One for each pin interrupt number. */ static GPIOINT_IrqCallbackPtr_t gpioCallbacks[16] = { 0 }; /******************************************************************************* ****************************** PROTOTYPES ********************************* ******************************************************************************/ static void GPIOINT_IRQDispatcher(uint32_t iflags); /** @endcond */ /******************************************************************************* *************************** GLOBAL FUNCTIONS ****************************** ******************************************************************************/ /***************************************************************************//** * @brief * Initialization of GPIOINT module. * ******************************************************************************/ void GPIOINT_Init(void) { NVIC_ClearPendingIRQ(GPIO_ODD_IRQn); NVIC_EnableIRQ(GPIO_ODD_IRQn); NVIC_ClearPendingIRQ(GPIO_EVEN_IRQn); NVIC_EnableIRQ(GPIO_EVEN_IRQn); } /***************************************************************************//** * @brief * Registers user callback for given pin interrupt number. * * @details * Use this function to register a callback which shall be called upon * interrupt generated for a given pin interrupt number. * Interrupt itself must be configured externally. Function overwrites previously * registered callback. * * @param[in] pin * Pin number for the callback. * @param[in] callbackPtr * A pointer to callback function. ******************************************************************************/ void GPIOINT_CallbackRegister(uint8_t intNo, GPIOINT_IrqCallbackPtr_t callbackPtr) { CORE_ATOMIC_SECTION( /* Dispatcher is used */ gpioCallbacks[intNo] = callbackPtr; ) } /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ /***************************************************************************//** * @brief * Function calls users callback for registered pin interrupts. * * @details * This function is called when GPIO interrupts are handled by the dispatcher. * Function gets even or odd interrupt flags and calls user callback * registered for that pin. Function iterates on flags starting from MSB. * * @param iflags * Interrupt flags which shall be handled by the dispatcher. * ******************************************************************************/ static void GPIOINT_IRQDispatcher(uint32_t iflags) { uint32_t irqIdx; GPIOINT_IrqCallbackPtr_t callback; /* check for all flags set in IF register */ while (iflags != 0U) { irqIdx = SL_CTZ(iflags); /* clear flag*/ iflags &= ~(1 << irqIdx); callback = gpioCallbacks[irqIdx]; if (callback) { /* call user callback */ callback(irqIdx); } } } /***************************************************************************//** * @brief * GPIO EVEN interrupt handler. Interrupt handler clears all IF even flags and * call the dispatcher passing the flags which triggered the interrupt. * ******************************************************************************/ void GPIO_EVEN_IRQHandler(void) { uint32_t iflags; /* Get all even interrupts. */ iflags = GPIO_IntGetEnabled() & 0x00005555; /* Clean only even interrupts. */ GPIO_IntClear(iflags); GPIOINT_IRQDispatcher(iflags); } /***************************************************************************//** * @brief * GPIO ODD interrupt handler. Interrupt handler clears all IF odd flags and * call the dispatcher passing the flags which triggered the interrupt. * ******************************************************************************/ void GPIO_ODD_IRQHandler(void) { uint32_t iflags; /* Get all odd interrupts. */ iflags = GPIO_IntGetEnabled() & 0x0000AAAA; /* Clean only odd interrupts. */ GPIO_IntClear(iflags); GPIOINT_IRQDispatcher(iflags); } /** @endcond */ /** @} (end addtogroup GPIOINT */ /** @} (end addtogroup emdrv) */ /* *INDENT-OFF* */ /******** THE REST OF THE FILE IS DOCUMENTATION ONLY !**********************//** * @addtogroup emdrv * @{ * @addtogroup GPIOINT * @brief GPIOINT General Purpose Input/Output Interrupt dispatcher * @{ @details The source files for the GPIO interrupt dispatcher library resides in the emdrv/gpiointerrupt folder, and are named gpiointerrupt.c and gpiointerrupt.h. @li @ref gpioint_intro @li @ref gpioint_api @li @ref gpioint_example @n @section gpioint_intro Introduction * EFM32/EZR32/EFR32 has two GPIO interrupts lines, Odd and Even. If more * than two interrupts are used then interrupt routine must dispatch from a callback * register. This module provides small dispatcher for both GPIO interrupts enabling * handling of up to 16 GPIO pin interrupts. * * It is up to the user to configure and enable interrupt on given pin. This can be done * using the GPIO library (emlib). This module handles the dispatch register and clearing of * interrupt flags. * * In order to use this dispatcher, it has to be initialized first by * calling GPIOINT_Init(). Then each pin interrupt number must be configured by first * registering the callback function for given interrupt number and then configure and * enabling the interrupt number in the GPIO module. @n @section gpioint_api The API This section contain brief descriptions of the functions in the API. You will find detailed information on parameters by clicking on the hyperlinked function names. Your application code must include one header file: @em gpiointerrupt.h. @ref GPIOINT_Init() @n This functions initializes the dispatcher register. Typically @htmlonly GPIOINT_Init() @endhtmlonly is called once in your startup code. @ref GPIOINT_CallbackRegister() @n Register a callback function on a pin interrupt number. @ref GPIOINT_CallbackUnRegister() @n Un-register a callback function on a pin interrupt number. @n @section gpioint_example Example @verbatim #include "em_gpio.h" #include "em_int.h" #include "gpiointerrupt.h" int main(void) { CHIP_Init(); // Enable clock for GPIO module, initialize GPIOINT CMU_ClockEnable(cmuClock_GPIO, true); GPIOINT_Init(); // Register callback functions and enable interrupts GPIOINT_CallbackRegister(1, gpioCallback1); GPIOINT_CallbackRegister(3, gpioCallback3); GPIOINT_CallbackRegister(8, gpioCallback8); GPIO_IntEnable(1<<1 | 1<<3 | 1<<8); while(true); } @endverbatim * @} end group GPIOINT ******************************************************* * @} end group emdrv ****************************************************/ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/emdrv/sleep/inc/sleep.h.
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/***************************************************************************//** * @file * @brief Energy Modes management driver ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * The licensor of this software is Silicon Laboratories Inc. Your use of this * software is governed by the terms of Silicon Labs Master Software License * Agreement (MSLA) available at * www.silabs.com/about-us/legal/master-software-license-agreement. This * software is distributed to you in Source Code format and is governed by the * sections of the MSLA applicable to Source Code. * ******************************************************************************/ #ifndef SLEEP_H #define SLEEP_H #include <stdint.h> #include <stdbool.h> /* Device specific header file(s). */ #include "em_device.h" #ifdef __cplusplus extern "C" { #endif /***************************************************************************//** * @addtogroup emdrv * @{ ******************************************************************************/ /***************************************************************************//** * @addtogroup SLEEP * @brief * Sleep Management Driver. * * @details * * @n @section sleepdrv_intro Introduction * This is a sleep management module consisting of sleep.c and sleep.h * source files. The main purpose of the module is to make it easy for an * application to always enter the lowest possible energy mode using a simple * API. * * The module works by providing an API for defining "sleep blocks" in the * application code. A "sleep block" will block the MCU from entering a certain * energy mode. A "sleep block" can for instance block EM2 entry because an * EM1 only peripheral is in use. These "sleep blocks" are created by the calls to * @ref SLEEP_SleepBlockBegin() and end with @ref SLEEP_SleepBlockEnd(). * * When an application wants to enter a low energy mode it can call * @ref SLEEP_Sleep() to enter the lowest possible energy mode. This module * will use the "sleep blocks" to figure out the lowest possible energy mode. * * Here is an example of how the sleep driver is initialized and how it can * be used to enter EM2. * * @code * SLEEP_Init_t sleepConfig = {0}; * SLEEP_InitEx(&sleepConfig); * SLEEP_SleepBlockBegin(sleepEM3); // Block EM3 entry * SLEEP_Sleep(); * SLEEP_SleepBlockEnd(sleepEM3); * @endcode * * @n @section sleepdrv_callbacks Sleep and Wakeup Events/Callbacks * * This module also provides a way to add application callbacks to notify * the application that the MCU is entering sleep, or waking up from sleep. * These callbacks can be provided to the driver when calling * @ref SLEEP_InitEx(). * * The sleepCallback function is called before entering sleep and the * wakeupCallback is called after waking up from sleep. The sleepCallback * function has a bool return value. This return value can be used to control * if the MCU should really go to sleep or not. Returning true will make * the MCU enter the selected energy mode, while returning false will force * the sleep driver to return without entering a sleep. * * Here is an example of how the sleep and wakeup callbacks are used. * * @code * static bool beforeSleep(SLEEP_EnergyMode_t mode) * { * printf("sleep\n"); * return true; * } * * static void afterWakeup(SLEEP_EnergyMode_t mode) * { * printf("wakeup\n"); * (void) mode; * } * * void main(void) * { * SLEEP_Init_t sleepConfig = { * .sleepCallback = beforeSleep, * .wakeupCallback = afterWakeup * }; * SLEEP_InitEx(&sleepConfig); * SLEEP_SleepBlockBegin(sleepEM3); // Block EM3 entry * while (true) { * SLEEP_Sleep(); * } * SLEEP_SleepBlockEnd(sleepEM3); * } * @endcode * * @{ ******************************************************************************/ /******************************************************************************* ******************************* MACROS ************************************ ******************************************************************************/ /** * This flag can be returned from the @ref restoreCallback function in order to * signal that the sleep driver should continue as normal. */ #define SLEEP_FLAG_NONE 0x0 /** * This flag can be returned from the @ref restoreCallback function in order to * signal to the sleep driver that HF clocks should not be restored and that * the sleep driver should go right back to sleep again. */ #define SLEEP_FLAG_NO_CLOCK_RESTORE 0x1u /******************************************************************************* **************************** CONFIGURATION ******************************** ******************************************************************************/ /** Enable/disable the HW block for protecting accidental setting of low energy * modes. Note that some devices do not support blocking energy mode entry in * hardware, on these devices SLEEP_HW_LOW_ENERGY_BLOCK_ENABLED will have no * effect. */ #ifndef SLEEP_HW_LOW_ENERGY_BLOCK_ENABLED #define SLEEP_HW_LOW_ENERGY_BLOCK_ENABLED false #endif /** Enable/disable calling wakeup callback after EM4 reset. */ #ifndef SLEEP_EM4_WAKEUP_CALLBACK_ENABLED #define SLEEP_EM4_WAKEUP_CALLBACK_ENABLED true #endif /** Configure default lowest energy mode that the system can be set to. * Possible values: * @li sleepEM2 - EM2, CPU core is turned off, all HF clocks are turned off, * LF clocks are on. * @li sleepEM3 - EM3, like EM2 + LF clocks are off, RAM retention, GPIO and ACMP * interrupt is on. */ #ifndef SLEEP_LOWEST_ENERGY_MODE_DEFAULT #define SLEEP_LOWEST_ENERGY_MODE_DEFAULT sleepEM3 #endif /******************************************************************************* ****************************** TYPEDEFS *********************************** ******************************************************************************/ /** Status value used for showing the Energy Mode the device is currently in. */ typedef enum { /** Status value for EM0. */ sleepEM0 = 0, /** Status value for EM1. */ sleepEM1 = 1, /** Status value for EM2. */ sleepEM2 = 2, /** Status value for EM3. */ sleepEM3 = 3, /** Status value for EM4. */ sleepEM4 = 4 } SLEEP_EnergyMode_t; /** Callback function pointer type. */ typedef void (*SLEEP_CbFuncPtr_t)(SLEEP_EnergyMode_t); /** * Initialization structure for the sleep driver. This includes optional * callback functions that can be used by the application to get notified * about sleep related events and that can be used to control the MCU * behavior when waking up from sleep. */ typedef struct { /** * Pointer to the callback function that is being called before the device * is going to sleep. This function is optional, if no sleep callback is * needed by the application then this field must be set to NULL. * * This callback function has a return value that can be used to force the * sleep driver to not enter a sleep mode. This can be used in applications * where for instance timing of events will make it inefficient to enter * sleep at a certain point in time. */ bool (*sleepCallback)(SLEEP_EnergyMode_t emode); /** * Pointer to the callback function that is being called after wake up. This * function is optional, if no wake up callback is needed by the application * then this field must be set to NULL. */ void (*wakeupCallback)(SLEEP_EnergyMode_t emode); /** * Pointer to the callback function that is being called after wake up and * before the HF clock is restored. This function can be used by the * application to signal that the sleep driver should wakeup normally or if * it should skip restoring the HF clock and go back to sleep. Delaying HF * clock restore is an advanced functionality that can be used to save * power in a system with frequent interrupts. * * These are the supported flags that can be returned from the callback * function. * * @ref SLEEP_FLAG_NONE * @ref SLEEP_FLAG_NO_CLOCK_RESTORE */ uint32_t (*restoreCallback)(SLEEP_EnergyMode_t emode); } SLEEP_Init_t; /******************************************************************************* ****************************** PROTOTYPES ********************************* ******************************************************************************/ void SLEEP_Init(SLEEP_CbFuncPtr_t pSleepCb, SLEEP_CbFuncPtr_t pWakeUpCb); void SLEEP_InitEx(const SLEEP_Init_t * init); SLEEP_EnergyMode_t SLEEP_LowestEnergyModeGet(void); SLEEP_EnergyMode_t SLEEP_Sleep(void); void SLEEP_ForceSleepInEM4(void); void SLEEP_SleepBlockBegin(SLEEP_EnergyMode_t eMode); void SLEEP_SleepBlockEnd(SLEEP_EnergyMode_t eMode); /** @} (end addtogroup SLEEP) */ /** @} (end addtogroup emdrv) */ #ifdef __cplusplus } #endif #endif /* SLEEP_H */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/emdrv/sleep/src/sleep.c.
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/***************************************************************************//** * @file * @brief Energy Modes management driver ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * The licensor of this software is Silicon Laboratories Inc. Your use of this * software is governed by the terms of Silicon Labs Master Software License * Agreement (MSLA) available at * www.silabs.com/about-us/legal/master-software-license-agreement. This * software is distributed to you in Source Code format and is governed by the * sections of the MSLA applicable to Source Code. * ******************************************************************************/ /* Chip specific header file(s). */ #include "em_device.h" #include "em_assert.h" #include "em_core.h" #include "em_rmu.h" #include "em_emu.h" /* Module header file(s). */ #include "sleep.h" /* stdlib is needed for NULL definition */ #include <stdlib.h> /***************************************************************************//** * @addtogroup emdrv * @{ ******************************************************************************/ /***************************************************************************//** * @addtogroup SLEEP * @{ ******************************************************************************/ /******************************************************************************* ******************************* MACROS ************************************ ******************************************************************************/ /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ /* Number of low energy modes (EM2 and EM3). Note: EM4 sleep/wakeup is handled * differently therefore it is not part of the list! */ #define SLEEP_NUMOF_LOW_ENERGY_MODES 2U #if defined(RMU_RSTCAUSE_EM4WURST) #define EM4_RESET_FLAG RMU_RSTCAUSE_EM4WURST #elif defined(RMU_RSTCAUSE_EM4RST) #define EM4_RESET_FLAG RMU_RSTCAUSE_EM4RST #elif defined(EMU_RSTCAUSE_EM4) #define EM4_RESET_FLAG EMU_RSTCAUSE_EM4 #endif /******************************************************************************* ******************************* STATICS *********************************** ******************************************************************************/ /* This is the internal context of the sleep driver. */ static SLEEP_Init_t sleepContext = { 0 }; /* Callback functions to call before and after sleep. This is only used to * preserve backwards compatibility when using SLEEP_Init. When using * SLEEP_InitEx this is no longer needed. */ static SLEEP_CbFuncPtr_t sleepCallback = NULL; /* Sleep block counter array representing the nested sleep blocks for the low * energy modes (EM2/EM3). Array index 0 corresponds to EM2 and index 1 * to EM3. * * Note: * - EM4 sleep/wakeup is handled differently therefore it is not part of the * list! * - Max. number of sleep block nesting is 255. */ static uint8_t sleepBlockCnt[SLEEP_NUMOF_LOW_ENERGY_MODES]; /** * @brief * This function is only used to keep the interface backwards compatible. * * @details * Previous version of the sleep driver had a sleep callback but it did not * have a return value. */ static bool sleepCallbackWrapper(SLEEP_EnergyMode_t emode) { if (NULL != sleepCallback) { sleepCallback(emode); } return true; } /******************************************************************************* ****************************** PROTOTYPES ********************************* ******************************************************************************/ static SLEEP_EnergyMode_t enterEMx(SLEEP_EnergyMode_t eMode); /** @endcond */ /******************************************************************************* *************************** GLOBAL FUNCTIONS ****************************** ******************************************************************************/ /***************************************************************************//** * @brief * Initialize the Sleep module. * * @details * Use this function to initialize the Sleep module, should be called * only once! Pointers to sleep and wake-up callback functions shall be * provided when calling this function. * If SLEEP_EM4_WAKEUP_CALLBACK_ENABLED is set to true, this function checks * for the cause of the reset that implicitly called it and calls the wakeup * callback if the reset was a wakeup from EM4 (does not work on Gecko MCU). * * @param[in] pSleepCb * Pointer to the callback function that is being called before the device is * going to sleep. * * @param[in] pWakeUpCb * Pointer to the callback function that is being called after wake up. * * @deprecated New code should use the @ref SLEEP_InitEx function for * initializing the sleep module. ******************************************************************************/ void SLEEP_Init(SLEEP_CbFuncPtr_t pSleepCb, SLEEP_CbFuncPtr_t pWakeUpCb) { /* Initialize callback functions. */ sleepCallback = pSleepCb; sleepContext.sleepCallback = sleepCallbackWrapper; sleepContext.wakeupCallback = pWakeUpCb; /* Reset sleep block counters. Note: not using for() saves code! */ sleepBlockCnt[0U] = 0U; sleepBlockCnt[1U] = 0U; #if (SLEEP_EM4_WAKEUP_CALLBACK_ENABLED == true) && !defined(_EFM32_GECKO_FAMILY) /* Check if the Init() happened after an EM4 reset. */ if (RMU_ResetCauseGet() & EM4_RESET_FLAG) { /* Clear the cause of the reset. */ RMU_ResetCauseClear(); /* Call wakeup callback with EM4 parameter. */ if (NULL != sleepContext.wakeupCallback) { sleepContext.wakeupCallback(sleepEM4); } } #endif } /***************************************************************************//** * @brief * Initialize the Sleep module. * * @details * Use this function to initialize the Sleep module. * * @param[in] init * Pointer to the sleep module init structure containing callback function * and configuration parameters. ******************************************************************************/ void SLEEP_InitEx(const SLEEP_Init_t * init) { SLEEP_Init(NULL, init->wakeupCallback); sleepContext.sleepCallback = init->sleepCallback; sleepContext.restoreCallback = init->restoreCallback; sleepContext.wakeupCallback = init->wakeupCallback; } /***************************************************************************//** * @brief * Sets the system to sleep into the lowest possible energy mode. * * @details * This function takes care of the system states protected by the sleep block * provided by SLEEP_SleepBlockBegin() / SLEEP_SleepBlockEnd(). It allows * the system to go into the lowest possible energy mode that the device can * be set into at the time of the call of this function. * This function will not go lower than EM3 because leaving EM4 requires * resetting MCU. To enter into EM4 call SLEEP_ForceSleepInEM4(). * * @return * Energy Mode that was entered. Possible values: * @li sleepEM0 * @li sleepEM1 * @li sleepEM2 * @li sleepEM3 ******************************************************************************/ SLEEP_EnergyMode_t SLEEP_Sleep(void) { CORE_DECLARE_IRQ_STATE; SLEEP_EnergyMode_t allowedEM; SLEEP_EnergyMode_t modeEntered = sleepEM0; uint32_t flags = 0; /* Critical section to allow sleep blocks in ISRs. */ CORE_ENTER_CRITICAL(); allowedEM = SLEEP_LowestEnergyModeGet(); if (allowedEM == sleepEM2 || allowedEM == sleepEM3) { EMU_Save(); } do { allowedEM = SLEEP_LowestEnergyModeGet(); if ((allowedEM >= sleepEM1) && (allowedEM <= sleepEM3)) { modeEntered = enterEMx(allowedEM); } if (NULL != sleepContext.restoreCallback) { flags = sleepContext.restoreCallback(modeEntered); } } while ((flags & SLEEP_FLAG_NO_CLOCK_RESTORE) > 0u); if (modeEntered == sleepEM2 || modeEntered == sleepEM3) { EMU_Restore(); } CORE_EXIT_CRITICAL(); return modeEntered; } /***************************************************************************//** * @brief * Force the device to go to EM4 without doing any checks. * * @details * This function unblocks the low energy sleep block then goes to EM4. * * @note * Regular RAM is not retained in EM4 and the wake up causes a reset. * If the configuration option SLEEP_EM4_WAKEUP_CALLBACK_ENABLED is set to * true, the SLEEP_Init() function checks for the reset cause and calls the * EM4 wakeup callback. ******************************************************************************/ void SLEEP_ForceSleepInEM4(void) { #if (SLEEP_HW_LOW_ENERGY_BLOCK_ENABLED == true) /* Unblock the EM2/EM3/EM4 block in the EMU. */ EMU_EM2UnBlock(); #endif /* Request entering to EM4. */ enterEMx(sleepEM4); } /***************************************************************************//** * @brief * Begin sleep block in the requested energy mode. * * @details * Blocking a critical system state from a certain energy mode makes sure that * the system is not set to that energy mode while the block is not being * released. * Every SLEEP_SleepBlockBegin() increases the corresponding counter and * every SLEEP_SleepBlockEnd() decreases it. * * Example:\code * SLEEP_SleepBlockBegin(sleepEM2); // do not allow EM2 or higher * // do some stuff that requires EM1 at least, like ADC sampling * SLEEP_SleepBlockEnd(sleepEM2); // remove restriction for EM2\endcode * * @note * Be aware that there is limit of maximum blocks nesting to 255. * * @param[in] eMode * Energy mode to begin to block. Possible values: * @li sleepEM2 - Begin to block the system from being set to EM2/EM3/EM4. * @li sleepEM3 - Begin to block the system from being set to EM3/EM4. ******************************************************************************/ void SLEEP_SleepBlockBegin(SLEEP_EnergyMode_t eMode) { EFM_ASSERT((eMode >= sleepEM2) && (eMode < sleepEM4)); EFM_ASSERT((sleepBlockCnt[eMode - 2U]) < 255U); if ((eMode == sleepEM2) || (eMode == sleepEM3)) { /* Increase the sleep block counter of the selected energy mode. */ sleepBlockCnt[eMode - 2U]++; #if (SLEEP_HW_LOW_ENERGY_BLOCK_ENABLED == true) && defined(_EMU_CTRL_EM2BLOCK_MASK) /* Block EM2/EM3 sleep if the EM2 block begins. */ if (eMode == sleepEM2) { EMU_EM2Block(); } #endif } } /***************************************************************************//** * @brief * End sleep block in the requested energy mode. * * @details * Release restriction for entering certain energy mode. Every call of this * function reduce blocking counter by 1. Once the counter for specific energy * mode is 0 and all counters for lower energy modes are 0 as well, using * particular energy mode is allowed. * Every SLEEP_SleepBlockBegin() increases the corresponding counter and * every SLEEP_SleepBlockEnd() decreases it. * * Example:\code * // at start all energy modes are allowed * SLEEP_SleepBlockBegin(sleepEM3); // EM3 and EM4 are blocked * SLEEP_SleepBlockBegin(sleepEM2); // EM2, EM3 and EM4 are blocked * SLEEP_SleepBlockBegin(sleepEM2); // EM2, EM3 and EM4 are blocked * SLEEP_SleepBlockEnd(sleepEM3); // EM2, EM3 and EM4 are still blocked * SLEEP_SleepBlockEnd(sleepEM2); // EM2, EM3 and EM4 are still blocked * SLEEP_SleepBlockEnd(sleepEM2); // all energy modes are allowed now\endcode * * @param[in] eMode * Energy mode to end to block. Possible values: * @li sleepEM2 - End to block the system from being set to EM2/EM3/EM4. * @li sleepEM3 - End to block the system from being set to EM3/EM4. ******************************************************************************/ void SLEEP_SleepBlockEnd(SLEEP_EnergyMode_t eMode) { EFM_ASSERT((eMode >= sleepEM2) && (eMode < sleepEM4)); if ((eMode == sleepEM2) || (eMode == sleepEM3)) { /* Decrease the sleep block counter of the selected energy mode. */ if (sleepBlockCnt[eMode - 2U] > 0U) { sleepBlockCnt[eMode - 2U]--; } #if (SLEEP_HW_LOW_ENERGY_BLOCK_ENABLED == true) && defined(_EMU_CTRL_EM2BLOCK_MASK) /* Check if the EM2/EM3 block should be unblocked in the EMU. */ if (0U == sleepBlockCnt[sleepEM2 - 2U]) { EMU_EM2UnBlock(); } #endif } } /***************************************************************************//** * @brief * Gets the lowest energy mode that the system is allowed to be set to. * * @details * This function uses the low energy mode block counters to determine the * lowest possible that the system is allowed to be set to. * * @return * Lowest energy mode that the system can be set to. Possible values: * @li sleepEM1 * @li sleepEM2 * @li sleepEM3 ******************************************************************************/ SLEEP_EnergyMode_t SLEEP_LowestEnergyModeGet(void) { SLEEP_EnergyMode_t tmpLowestEM = sleepEM1; /* Check which is the lowest energy mode that the system can be set to. */ if (0U == sleepBlockCnt[sleepEM2 - 2U]) { tmpLowestEM = sleepEM2; if (0U == sleepBlockCnt[sleepEM3 - 2U]) { tmpLowestEM = sleepEM3; } } /* Compare with the default lowest energy mode setting. */ if (SLEEP_LOWEST_ENERGY_MODE_DEFAULT < tmpLowestEM) { tmpLowestEM = SLEEP_LOWEST_ENERGY_MODE_DEFAULT; } return tmpLowestEM; } /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ /***************************************************************************//** * @brief * Call the callbacks and enter the requested energy mode. * * @details * This function is not part of the API, therefore it shall not be called by * the user directly as it doesn not have any checks if the system is ready * for sleep! * * @note * The EM4 wakeup callback is not being called from this function because * waking up from EM4 causes a reset. * If SLEEP_EM4_WAKEUP_CALLBACK_ENABLED is set to true, SLEEP_Init() function * checks for the cause of the reset and calls the wakeup callback if the * reset was a wakeup from EM4. ******************************************************************************/ static SLEEP_EnergyMode_t enterEMx(SLEEP_EnergyMode_t eMode) { bool enterSleep = true; EFM_ASSERT((eMode > sleepEM0) && (eMode <= sleepEM4)); /* Call sleepCallback() before going to sleep. */ if (NULL != sleepContext.sleepCallback) { /* Call the callback before going to sleep. */ enterSleep = sleepContext.sleepCallback(eMode); } if (!enterSleep) { return sleepEM0; } /* Enter the requested energy mode. */ switch (eMode) { case sleepEM1: EMU_EnterEM1(); break; case sleepEM2: EMU_EnterEM2(false); break; case sleepEM3: EMU_EnterEM3(false); break; case sleepEM4: EMU_EnterEM4(); break; default: /* Don't do anything, stay in EM0. */ break; } /* Call the callback after waking up from sleep. */ if (NULL != sleepContext.wakeupCallback) { sleepContext.wakeupCallback(eMode); } return eMode; } /** @endcond */ /** @} (end addtogroup SLEEP */ /** @} (end addtogroup emdrv) */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/emdrv/uartdrv/inc/uartdrv.h.
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/***************************************************************************//** * @file * @brief UARTDRV API definition. ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * The licensor of this software is Silicon Laboratories Inc. Your use of this * software is governed by the terms of Silicon Labs Master Software License * Agreement (MSLA) available at * www.silabs.com/about-us/legal/master-software-license-agreement. This * software is distributed to you in Source Code format and is governed by the * sections of the MSLA applicable to Source Code. * ******************************************************************************/ #ifndef UARTDRV_H #define UARTDRV_H #include "em_device.h" #include "em_usart.h" #include "em_leuart.h" #include "em_gpio.h" #include "em_cmu.h" #include "ecode.h" #include "uartdrv_config.h" #include "dmadrv.h" #ifdef __cplusplus extern "C" { #endif /***************************************************************************//** * @addtogroup emdrv * @{ ******************************************************************************/ /***************************************************************************//** * @addtogroup UARTDRV * @{ ******************************************************************************/ #define ECODE_EMDRV_UARTDRV_OK (ECODE_OK) ///< A successful return value. #define ECODE_EMDRV_UARTDRV_WAITING (ECODE_EMDRV_UARTDRV_BASE | 0x00000001) ///< An operation is waiting in queue. #define ECODE_EMDRV_UARTDRV_ILLEGAL_HANDLE (ECODE_EMDRV_UARTDRV_BASE | 0x00000002) ///< An illegal UART handle. #define ECODE_EMDRV_UARTDRV_PARAM_ERROR (ECODE_EMDRV_UARTDRV_BASE | 0x00000003) ///< An illegal input parameter. #define ECODE_EMDRV_UARTDRV_BUSY (ECODE_EMDRV_UARTDRV_BASE | 0x00000004) ///< The UART port is busy. #define ECODE_EMDRV_UARTDRV_ILLEGAL_OPERATION (ECODE_EMDRV_UARTDRV_BASE | 0x00000005) ///< An illegal operation on the UART port. #define ECODE_EMDRV_UARTDRV_IDLE (ECODE_EMDRV_UARTDRV_BASE | 0x00000008) ///< No UART transfer is in progress. #define ECODE_EMDRV_UARTDRV_ABORTED (ECODE_EMDRV_UARTDRV_BASE | 0x00000009) ///< A UART transfer has been aborted. #define ECODE_EMDRV_UARTDRV_QUEUE_FULL (ECODE_EMDRV_UARTDRV_BASE | 0x0000000A) ///< A UART operation queue is full. #define ECODE_EMDRV_UARTDRV_QUEUE_EMPTY (ECODE_EMDRV_UARTDRV_BASE | 0x0000000B) ///< A UART operation queue is empty. #define ECODE_EMDRV_UARTDRV_PARITY_ERROR (ECODE_EMDRV_UARTDRV_BASE | 0x0000000C) ///< A UART parity error frame. Data is ignored. #define ECODE_EMDRV_UARTDRV_FRAME_ERROR (ECODE_EMDRV_UARTDRV_BASE | 0x0000000D) ///< A UART frame error. Data is ignored. #define ECODE_EMDRV_UARTDRV_DMA_ALLOC_ERROR (ECODE_EMDRV_UARTDRV_BASE | 0x0000000E) ///< Unable to allocate DMA channels. #define ECODE_EMDRV_UARTDRV_CLOCK_ERROR (ECODE_EMDRV_UARTDRV_BASE | 0x0000000F) ///< Unable to set a desired baudrate. // UARTDRV status codes #define UARTDRV_STATUS_RXEN (1 << 0) ///< The receiver is enabled. #define UARTDRV_STATUS_TXEN (1 << 1) ///< The transmitter is enabled. #define UARTDRV_STATUS_RXBLOCK (1 << 3) ///< The receiver is blocked; incoming frames will be discarded. #define UARTDRV_STATUS_TXTRI (1 << 4) ///< The transmitter is tristated. #define UARTDRV_STATUS_TXC (1 << 5) ///< A transmit operation is complete. No more data is available in the transmit buffer and shift register. #define UARTDRV_STATUS_TXBL (1 << 6) ///< The transmit buffer is empty. #define UARTDRV_STATUS_RXDATAV (1 << 7) ///< Data is available in the receive buffer. #define UARTDRV_STATUS_RXFULL (1 << 8) ///< The receive buffer is full. #define UARTDRV_STATUS_TXIDLE (1 << 13) ///< The transmitter is idle. typedef uint32_t UARTDRV_Count_t; ///< A UART transfer count typedef uint32_t UARTDRV_Status_t; ///< A UART status return type. Bitfield of UARTDRV_STATUS_* values. /// Flow Control method typedef enum UARTDRV_FlowControlType{ uartdrvFlowControlNone = 0, ///< None uartdrvFlowControlSw = 1, ///< Software XON/XOFF uartdrvFlowControlHw = 2, ///< nRTS/nCTS hardware handshake uartdrvFlowControlHwUart = 3 ///< UART peripheral controls nRTS/nCTS } UARTDRV_FlowControlType_t; /// Flow Control state typedef enum UARTDRV_FlowControlState{ uartdrvFlowControlOn = 0, ///< XON or nRTS/nCTS low uartdrvFlowControlOff = 1, ///< XOFF or nRTS/nCTS high uartdrvFlowControlAuto = 2 ///< This driver controls the state. } UARTDRV_FlowControlState_t; /// Transfer abort type typedef enum UARTDRV_AbortType{ uartdrvAbortTransmit = 1, ///< Abort current and queued transmit operations uartdrvAbortReceive = 2, ///< Abort current and queued receive operations uartdrvAbortAll = 3 ///< Abort all current and queued operations } UARTDRV_AbortType_t; /// @cond DO_NOT_INCLUDE_WITH_DOXYGEN /// Type of a UART peripheral typedef enum UARTDRV_UartType{ uartdrvUartTypeUart = 0, ///< USART/UART peripheral #if defined(LEUART_COUNT) && (LEUART_COUNT > 0) uartdrvUartTypeLeuart = 1 ///< LEUART peripheral #endif } UARTDRV_UartType_t; /// @endcond struct UARTDRV_HandleData; /***************************************************************************//** * @brief * UARTDRV transfer completion callback function. * * @details * Called when a transfer is complete. An * application should check the transferStatus and itemsTransferred values. * * @param[in] handle * The UARTDRV device handle used to start the transfer. * * @param[in] transferStatus * Completion status of the transfer operation. * * @param[in] data * A pointer to the transfer data buffer. * * @param[in] transferCount * A number of bytes transferred. ******************************************************************************/ typedef void (*UARTDRV_Callback_t)(struct UARTDRV_HandleData *handle, Ecode_t transferStatus, uint8_t *data, UARTDRV_Count_t transferCount); /// UART transfer buffer typedef struct { uint8_t *data; ///< Transfer data buffer UARTDRV_Count_t transferCount; ///< Transfer item count volatile UARTDRV_Count_t itemsRemaining; ///< Transfer items remaining UARTDRV_Callback_t callback; ///< Completion callback Ecode_t transferStatus; ///< Completion status of the transfer operation } UARTDRV_Buffer_t; /// Transfer operation FIFO queue typedef typedef struct { volatile uint16_t head; ///< An index of the next byte to send. volatile uint16_t tail; ///< An index of the location to enqueue the next message. volatile uint16_t used; ///< A number of bytes queued. const uint16_t size; ///< FIFO size. UARTDRV_Buffer_t fifo[]; ///< FIFO of queued data. } UARTDRV_Buffer_FifoQueue_t; /// Macros to define FIFO and buffer queues. typedef can't be used becuase the size /// of the FIFO array in the queues can change. #define DEFINE_BUF_QUEUE(qSize, qName) \ typedef struct { \ uint16_t head; \ uint16_t tail; \ volatile uint16_t used; \ const uint16_t size; \ UARTDRV_Buffer_t fifo[qSize]; \ } _##qName; \ static volatile _##qName qName = \ { \ .head = 0, \ .tail = 0, \ .used = 0, \ .size = qSize, \ } /// A UART driver instance initialization structure. /// Contains a number of UARTDRV configuration options. /// It is required for driver instance initialization. /// This structure is passed to @ref UARTDRV_Init() when initializing a UARTDRV /// instance. typedef struct { USART_TypeDef *port; ///< The peripheral used for UART uint32_t baudRate; ///< UART baud rate #if defined(_USART_ROUTELOC0_MASK) uint8_t portLocationTx; ///< A location number for UART Tx pin. uint8_t portLocationRx; ///< A location number for UART Rx pin. #elif defined(_USART_ROUTE_MASK) uint8_t portLocation; ///< A location number for UART pins. #elif defined(_GPIO_USART_ROUTEEN_MASK) GPIO_Port_TypeDef txPort; ///< Port for UART Tx pin. GPIO_Port_TypeDef rxPort; ///< Port for UART Rx pin. uint8_t txPin; ///< Pin number for UART Tx. uint8_t rxPin; ///< Pin number for UART Rx. uint8_t uartNum; ///< UART instance number. #endif USART_Stopbits_TypeDef stopBits; ///< A number of stop bits. USART_Parity_TypeDef parity; ///< Parity configuration. USART_OVS_TypeDef oversampling; ///< Oversampling mode. #if defined(USART_CTRL_MVDIS) bool mvdis; ///< Majority Vote Disable for 16x, 8x and 6x oversampling modes. #endif UARTDRV_FlowControlType_t fcType; ///< Flow control mode. GPIO_Port_TypeDef ctsPort; ///< A CTS pin port number. uint8_t ctsPin; ///< A CTS pin number. GPIO_Port_TypeDef rtsPort; ///< An RTS pin port number. uint8_t rtsPin; ///< An RTS pin number. UARTDRV_Buffer_FifoQueue_t *rxQueue; ///< A receive operation queue. UARTDRV_Buffer_FifoQueue_t *txQueue; ///< T transmit operation queue. #if defined(_USART_ROUTELOC1_MASK) uint8_t portLocationCts; ///< A location number for the UART CTS pin. uint8_t portLocationRts; ///< A location number for the UART RTS pin. #endif } UARTDRV_InitUart_t; /// @cond DO_NOT_INCLUDE_WITH_DOXYGEN /// Deprecated UART driver instance initialization structure alias. /// @deprecated This structure is deprecated. Use UARTDRV_InitUart_t instead. typedef UARTDRV_InitUart_t UARTDRV_Init_t; /// @endcond #if defined(LEUART_COUNT) && (LEUART_COUNT > 0) /// LEUART driver instance initialization structure. /// Contains a number of UARTDRV configuration options. /// It is required to initialize a driver instance. /// This structure is passed to @ref UARTDRV_InitLeuart() when initializing a UARTDRV /// instance. typedef struct { LEUART_TypeDef *port; ///< The peripheral used for LEUART uint32_t baudRate; ///< UART baud rate #if defined(_LEUART_ROUTELOC0_MASK) uint8_t portLocationTx; ///< Location number for LEUART Tx pin. uint8_t portLocationRx; ///< Location number for LEUART Rx pin. #else uint8_t portLocation; ///< Location number for LEUART pins #endif LEUART_Stopbits_TypeDef stopBits; ///< Number of stop bits LEUART_Parity_TypeDef parity; ///< Parity configuration UARTDRV_FlowControlType_t fcType; ///< Flow control mode GPIO_Port_TypeDef ctsPort; ///< CTS pin port number uint8_t ctsPin; ///< CTS pin number GPIO_Port_TypeDef rtsPort; ///< RTS pin port number uint8_t rtsPin; ///< RTS pin number UARTDRV_Buffer_FifoQueue_t *rxQueue; ///< Receive operation queue UARTDRV_Buffer_FifoQueue_t *txQueue; ///< Transmit operation queue } UARTDRV_InitLeuart_t; #endif /// A UART driver instance handle data structure. /// Allocated by the application using UARTDRV. /// Several concurrent driver instances may exist in an application. The application must /// not modify the contents of this handle and should not depend on its values. typedef struct UARTDRV_HandleData{ /// @cond DO_NOT_INCLUDE_WITH_DOXYGEN union { USART_TypeDef * uart; #if defined(LEUART_COUNT) && (LEUART_COUNT > 0) LEUART_TypeDef * leuart; #endif } peripheral; #if defined(_GPIO_USART_ROUTEEN_MASK) uint8_t uartNum; // UART instance number #endif unsigned int txDmaCh; // A DMA ch assigned to Tx unsigned int rxDmaCh; // A DMA ch assigned to Rx DMADRV_PeripheralSignal_t txDmaSignal; // A DMA Tx trigger source signal DMADRV_PeripheralSignal_t rxDmaSignal; // A DMA Rx trigger source signal UARTDRV_FlowControlState_t fcSelfState; // A current self flow control state UARTDRV_FlowControlState_t fcSelfCfg; // A self flow control override configuration UARTDRV_FlowControlState_t fcPeerState; // A current peer flow control state GPIO_Port_TypeDef txPort; // A Tx pin port number GPIO_Port_TypeDef rxPort; // An Rx pin port number GPIO_Port_TypeDef ctsPort; // A CTS pin port number GPIO_Port_TypeDef rtsPort; // An RTS pin port number uint8_t txPin; // A Tx pin number uint8_t rxPin; // An Tx pin number uint8_t ctsPin; // A CTS pin number uint8_t rtsPin; // An RTS pin number CMU_Clock_TypeDef uartClock; // A clock source select UARTDRV_Buffer_FifoQueue_t *rxQueue; // A receive operation queue UARTDRV_Buffer_FifoQueue_t *txQueue; // A transmit operation queue volatile bool rxDmaActive; // A receive DMA is currently active volatile bool txDmaActive; // A transmit DMA is currently active volatile uint8_t txDmaPaused; // A transmit DMA pause counter bool IgnoreRestrain; // A transmit does not respect uartdrvFlowControlOff bool hasTransmitted; // Indicates whether the handle has transmitted data UARTDRV_FlowControlType_t fcType; // A flow control mode UARTDRV_UartType_t type; // A type of UART /// @endcond } UARTDRV_HandleData_t; /// Handle pointer typedef UARTDRV_HandleData_t * UARTDRV_Handle_t; Ecode_t UARTDRV_InitUart(UARTDRV_Handle_t handle, const UARTDRV_InitUart_t * initData); #if defined(LEUART_COUNT) && (LEUART_COUNT > 0) Ecode_t UARTDRV_InitLeuart(UARTDRV_Handle_t handle, const UARTDRV_InitLeuart_t * initData); #endif Ecode_t UARTDRV_DeInit(UARTDRV_Handle_t handle); UARTDRV_Status_t UARTDRV_GetPeripheralStatus(UARTDRV_Handle_t handle); UARTDRV_Status_t UARTDRV_GetReceiveStatus(UARTDRV_Handle_t handle, uint8_t **buffer, UARTDRV_Count_t *bytesReceived, UARTDRV_Count_t *bytesRemaining); UARTDRV_Status_t UARTDRV_GetTransmitStatus(UARTDRV_Handle_t handle, uint8_t **buffer, UARTDRV_Count_t *bytesSent, UARTDRV_Count_t *bytesRemaining); uint8_t UARTDRV_GetReceiveDepth(UARTDRV_Handle_t handle); uint8_t UARTDRV_GetTransmitDepth(UARTDRV_Handle_t handle); Ecode_t UARTDRV_Transmit(UARTDRV_Handle_t handle, uint8_t *data, UARTDRV_Count_t count, UARTDRV_Callback_t callback); Ecode_t UARTDRV_Receive(UARTDRV_Handle_t handle, uint8_t *data, UARTDRV_Count_t count, UARTDRV_Callback_t callback); Ecode_t UARTDRV_TransmitB(UARTDRV_Handle_t handle, uint8_t *data, UARTDRV_Count_t count); Ecode_t UARTDRV_ReceiveB(UARTDRV_Handle_t handle, uint8_t *data, UARTDRV_Count_t count); Ecode_t UARTDRV_ForceTransmit(UARTDRV_Handle_t handle, uint8_t *data, UARTDRV_Count_t count); UARTDRV_Count_t UARTDRV_ForceReceive(UARTDRV_Handle_t handle, uint8_t *data, UARTDRV_Count_t maxLength); Ecode_t UARTDRV_Abort(UARTDRV_Handle_t handle, UARTDRV_AbortType_t type); Ecode_t UARTDRV_PauseTransmit(UARTDRV_Handle_t handle); Ecode_t UARTDRV_ResumeTransmit(UARTDRV_Handle_t handle); UARTDRV_FlowControlState_t UARTDRV_FlowControlGetSelfStatus(UARTDRV_Handle_t handle); UARTDRV_FlowControlState_t UARTDRV_FlowControlGetPeerStatus(UARTDRV_Handle_t handle); Ecode_t UARTDRV_FlowControlSet(UARTDRV_Handle_t handle, UARTDRV_FlowControlState_t state); Ecode_t UARTDRV_FlowControlSetPeerStatus(UARTDRV_Handle_t handle, UARTDRV_FlowControlState_t state); Ecode_t UARTDRV_FlowControlIgnoreRestrain(UARTDRV_Handle_t handle); // -------------------------------- // Deprecated items /***************************************************************************//** * @brief * Initialize a U(S)ART driver instance. * * @deprecated * Deprecated; Use @ref UARTDRV_InitUart() instead. * * @param[out] handle A pointer to a UARTDRV handle, refer to @ref * UARTDRV_Handle_t. * * @param[in] initData A pointer to an initialization data structure, * refer to @ref UARTDRV_InitUart_t. * * @return * @ref ECODE_EMDRV_UARTDRV_OK on success. On failure, an appropriate * UARTDRV @ref Ecode_t is returned. ******************************************************************************/ __STATIC_INLINE Ecode_t UARTDRV_Init(UARTDRV_Handle_t handle, UARTDRV_InitUart_t *initData) { return UARTDRV_InitUart(handle, initData); } /// Set to 1 to include flow control support. /// @deprecated EMDRV_UARTDRV_HW_FLOW_CONTROL_ENABLE changed to /// to EMDRV_UARTDRV_FLOW_CONTROL_ENABLE. /// Translate to new name if old name is in use. #if defined(EMDRV_UARTDRV_HW_FLOW_CONTROL_ENABLE) #undef EMDRV_UARTDRV_FLOW_CONTROL_ENABLE #define EMDRV_UARTDRV_FLOW_CONTROL_ENABLE EMDRV_UARTDRV_HW_FLOW_CONTROL_ENABLE #endif /** @} (end addtogroup UARTDRV) */ /** @} (end addtogroup emdrv) */ #ifdef __cplusplus } #endif #endif // UARTDRV_H |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/emlib/inc/em_adc.h.
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/***************************************************************************//** * @file * @brief Analog to Digital Converter (ADC) peripheral API * @version 5.7.0 ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * SPDX-License-Identifier: Zlib * * The licensor of this software is Silicon Laboratories Inc. * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be * appreciated but is not required. * 2. Altered source versions must be plainly marked as such, and must not be * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * ******************************************************************************/ #ifndef EM_ADC_H #define EM_ADC_H #include "em_device.h" #if defined(ADC_COUNT) && (ADC_COUNT > 0) #include <stdbool.h> #ifdef __cplusplus extern "C" { #endif /***************************************************************************//** * @addtogroup emlib * @{ ******************************************************************************/ /***************************************************************************//** * @addtogroup ADC * @{ ******************************************************************************/ /******************************************************************************* ******************************** ENUMS ************************************ ******************************************************************************/ /** Acquisition time (in ADC clock cycles). */ typedef enum { adcAcqTime1 = _ADC_SINGLECTRL_AT_1CYCLE, /**< 1 clock cycle. */ adcAcqTime2 = _ADC_SINGLECTRL_AT_2CYCLES, /**< 2 clock cycles. */ adcAcqTime4 = _ADC_SINGLECTRL_AT_4CYCLES, /**< 4 clock cycles. */ adcAcqTime8 = _ADC_SINGLECTRL_AT_8CYCLES, /**< 8 clock cycles. */ adcAcqTime16 = _ADC_SINGLECTRL_AT_16CYCLES, /**< 16 clock cycles. */ adcAcqTime32 = _ADC_SINGLECTRL_AT_32CYCLES, /**< 32 clock cycles. */ adcAcqTime64 = _ADC_SINGLECTRL_AT_64CYCLES, /**< 64 clock cycles. */ adcAcqTime128 = _ADC_SINGLECTRL_AT_128CYCLES, /**< 128 clock cycles. */ adcAcqTime256 = _ADC_SINGLECTRL_AT_256CYCLES /**< 256 clock cycles. */ } ADC_AcqTime_TypeDef; #if defined(_ADC_CTRL_LPFMODE_MASK) /** Lowpass filter mode. */ typedef enum { /** No filter or decoupling capacitor. */ adcLPFilterBypass = _ADC_CTRL_LPFMODE_BYPASS, /** On-chip RC filter. */ adcLPFilterRC = _ADC_CTRL_LPFMODE_RCFILT, /** On-chip decoupling capacitor. */ adcLPFilterDeCap = _ADC_CTRL_LPFMODE_DECAP } ADC_LPFilter_TypeDef; #endif /** Oversample rate select. */ typedef enum { /** 2 samples per conversion result. */ adcOvsRateSel2 = _ADC_CTRL_OVSRSEL_X2, /** 4 samples per conversion result. */ adcOvsRateSel4 = _ADC_CTRL_OVSRSEL_X4, /** 8 samples per conversion result. */ adcOvsRateSel8 = _ADC_CTRL_OVSRSEL_X8, /** 16 samples per conversion result. */ adcOvsRateSel16 = _ADC_CTRL_OVSRSEL_X16, /** 32 samples per conversion result. */ adcOvsRateSel32 = _ADC_CTRL_OVSRSEL_X32, /** 64 samples per conversion result. */ adcOvsRateSel64 = _ADC_CTRL_OVSRSEL_X64, /** 128 samples per conversion result. */ adcOvsRateSel128 = _ADC_CTRL_OVSRSEL_X128, /** 256 samples per conversion result. */ adcOvsRateSel256 = _ADC_CTRL_OVSRSEL_X256, /** 512 samples per conversion result. */ adcOvsRateSel512 = _ADC_CTRL_OVSRSEL_X512, /** 1024 samples per conversion result. */ adcOvsRateSel1024 = _ADC_CTRL_OVSRSEL_X1024, /** 2048 samples per conversion result. */ adcOvsRateSel2048 = _ADC_CTRL_OVSRSEL_X2048, /** 4096 samples per conversion result. */ adcOvsRateSel4096 = _ADC_CTRL_OVSRSEL_X4096 } ADC_OvsRateSel_TypeDef; /** Peripheral Reflex System signal used to trigger a single sample. */ typedef enum { #if defined(_ADC_SINGLECTRL_PRSSEL_MASK) adcPRSSELCh0 = _ADC_SINGLECTRL_PRSSEL_PRSCH0, /**< PRS channel 0. */ adcPRSSELCh1 = _ADC_SINGLECTRL_PRSSEL_PRSCH1, /**< PRS channel 1. */ adcPRSSELCh2 = _ADC_SINGLECTRL_PRSSEL_PRSCH2, /**< PRS channel 2. */ adcPRSSELCh3 = _ADC_SINGLECTRL_PRSSEL_PRSCH3, /**< PRS channel 3. */ #if defined(_ADC_SINGLECTRL_PRSSEL_PRSCH4) adcPRSSELCh4 = _ADC_SINGLECTRL_PRSSEL_PRSCH4, /**< PRS channel 4. */ #endif #if defined(_ADC_SINGLECTRL_PRSSEL_PRSCH5) adcPRSSELCh5 = _ADC_SINGLECTRL_PRSSEL_PRSCH5, /**< PRS channel 5. */ #endif #if defined(_ADC_SINGLECTRL_PRSSEL_PRSCH6) adcPRSSELCh6 = _ADC_SINGLECTRL_PRSSEL_PRSCH6, /**< PRS channel 6. */ #endif #if defined(_ADC_SINGLECTRL_PRSSEL_PRSCH7) adcPRSSELCh7 = _ADC_SINGLECTRL_PRSSEL_PRSCH7, /**< PRS channel 7. */ #endif #if defined(_ADC_SINGLECTRL_PRSSEL_PRSCH8) adcPRSSELCh8 = _ADC_SINGLECTRL_PRSSEL_PRSCH8, /**< PRS channel 8. */ #endif #if defined(_ADC_SINGLECTRL_PRSSEL_PRSCH9) adcPRSSELCh9 = _ADC_SINGLECTRL_PRSSEL_PRSCH9, /**< PRS channel 9. */ #endif #if defined(_ADC_SINGLECTRL_PRSSEL_PRSCH10) adcPRSSELCh10 = _ADC_SINGLECTRL_PRSSEL_PRSCH10, /**< PRS channel 10. */ #endif #if defined(_ADC_SINGLECTRL_PRSSEL_PRSCH11) adcPRSSELCh11 = _ADC_SINGLECTRL_PRSSEL_PRSCH11, /**< PRS channel 11. */ #endif #elif defined(_ADC_SINGLECTRLX_PRSSEL_MASK) adcPRSSELCh0 = _ADC_SINGLECTRLX_PRSSEL_PRSCH0, /**< PRS channel 0. */ adcPRSSELCh1 = _ADC_SINGLECTRLX_PRSSEL_PRSCH1, /**< PRS channel 1. */ adcPRSSELCh2 = _ADC_SINGLECTRLX_PRSSEL_PRSCH2, /**< PRS channel 2. */ adcPRSSELCh3 = _ADC_SINGLECTRLX_PRSSEL_PRSCH3, /**< PRS channel 3. */ adcPRSSELCh4 = _ADC_SINGLECTRLX_PRSSEL_PRSCH4, /**< PRS channel 4. */ adcPRSSELCh5 = _ADC_SINGLECTRLX_PRSSEL_PRSCH5, /**< PRS channel 5. */ adcPRSSELCh6 = _ADC_SINGLECTRLX_PRSSEL_PRSCH6, /**< PRS channel 6. */ adcPRSSELCh7 = _ADC_SINGLECTRLX_PRSSEL_PRSCH7, /**< PRS channel 7. */ #if defined(_ADC_SINGLECTRLX_PRSSEL_PRSCH8) adcPRSSELCh8 = _ADC_SINGLECTRLX_PRSSEL_PRSCH8, /**< PRS channel 8. */ #endif #if defined(_ADC_SINGLECTRLX_PRSSEL_PRSCH9) adcPRSSELCh9 = _ADC_SINGLECTRLX_PRSSEL_PRSCH9, /**< PRS channel 9. */ #endif #if defined(_ADC_SINGLECTRLX_PRSSEL_PRSCH10) adcPRSSELCh10 = _ADC_SINGLECTRLX_PRSSEL_PRSCH10, /**< PRS channel 10. */ #endif #if defined(_ADC_SINGLECTRLX_PRSSEL_PRSCH11) adcPRSSELCh11 = _ADC_SINGLECTRLX_PRSSEL_PRSCH11, /**< PRS channel 11. */ #endif #if defined(_ADC_SINGLECTRLX_PRSSEL_PRSCH12) adcPRSSELCh12 = _ADC_SINGLECTRLX_PRSSEL_PRSCH12, /**< PRS channel 12. */ adcPRSSELCh13 = _ADC_SINGLECTRLX_PRSSEL_PRSCH13, /**< PRS channel 13. */ adcPRSSELCh14 = _ADC_SINGLECTRLX_PRSSEL_PRSCH14, /**< PRS channel 14. */ adcPRSSELCh15 = _ADC_SINGLECTRLX_PRSSEL_PRSCH15, /**< PRS channel 15. */ #endif #endif } ADC_PRSSEL_TypeDef; /** Single and scan mode voltage references. Using unshifted enumerations and or in ADC_CTRLX_VREFSEL_REG to select the extension register CTRLX_VREFSEL. */ #if defined(_ADC_SCANCTRLX_VREFSEL_MASK) #define ADC_CTRLX_VREFSEL_REG 0x80UL #endif typedef enum { /** Internal 1.25 V reference. */ adcRef1V25 = _ADC_SINGLECTRL_REF_1V25, /** Internal 2.5 V reference. */ adcRef2V5 = _ADC_SINGLECTRL_REF_2V5, /** Buffered VDD. */ adcRefVDD = _ADC_SINGLECTRL_REF_VDD, #if defined(_ADC_SINGLECTRL_REF_5VDIFF) /** Internal differential 5 V reference. */ adcRef5VDIFF = _ADC_SINGLECTRL_REF_5VDIFF, #endif #if defined(_ADC_SINGLECTRL_REF_5V) /** Internal 5 V reference. */ adcRef5V = _ADC_SINGLECTRL_REF_5V, #endif /** Single-ended external reference from pin 6. */ adcRefExtSingle = _ADC_SINGLECTRL_REF_EXTSINGLE, /** Differential external reference from pin 6 and 7. */ adcRef2xExtDiff = _ADC_SINGLECTRL_REF_2XEXTDIFF, /** Unbuffered 2xVDD. */ adcRef2xVDD = _ADC_SINGLECTRL_REF_2XVDD, #if defined(_ADC_SINGLECTRLX_VREFSEL_VBGR) /** Custom VFS: Internal Bandgap reference. */ adcRefVBGR = _ADC_SINGLECTRLX_VREFSEL_VBGR | ADC_CTRLX_VREFSEL_REG, #endif #if defined(_ADC_SINGLECTRLX_VREFSEL_VDDXWATT) /** Custom VFS: Scaled AVDD: AVDD * VREFATT. */ adcRefVddxAtt = _ADC_SINGLECTRLX_VREFSEL_VDDXWATT | ADC_CTRLX_VREFSEL_REG, #endif #if defined(_ADC_SINGLECTRLX_VREFSEL_VREFPWATT) /** Custom VFS: Scaled singled ended external reference from pin 6: VREFP * VREFATT. */ adcRefVPxAtt = _ADC_SINGLECTRLX_VREFSEL_VREFPWATT | ADC_CTRLX_VREFSEL_REG, #endif #if defined(_ADC_SINGLECTRLX_VREFSEL_VREFP) /** Custom VFS: Raw single-ended external reference from pin 6. */ adcRefP = _ADC_SINGLECTRLX_VREFSEL_VREFP | ADC_CTRLX_VREFSEL_REG, #endif #if defined(_ADC_SINGLECTRLX_VREFSEL_VENTROPY) /** Custom VFS: Special mode for entropy generation */ adcRefVEntropy = _ADC_SINGLECTRLX_VREFSEL_VENTROPY | ADC_CTRLX_VREFSEL_REG, #endif #if defined(_ADC_SINGLECTRLX_VREFSEL_VREFPNWATT) /** Custom VFS: Scaled differential external Vref from pin 6 and 7: (VREFP - VREFN) * VREFATT. */ adcRefVPNxAtt = _ADC_SINGLECTRLX_VREFSEL_VREFPNWATT | ADC_CTRLX_VREFSEL_REG, #endif #if defined(_ADC_SINGLECTRLX_VREFSEL_VREFPN) /** Custom VFS: Raw differential external Vref from pin 6 and 7: VREFP - VREFN. */ adcRefPN = _ADC_SINGLECTRLX_VREFSEL_VREFPN | ADC_CTRLX_VREFSEL_REG, #endif } ADC_Ref_TypeDef; /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ /* Deprecated enum names */ #if !defined(_ADC_SINGLECTRL_REF_5VDIFF) #define adcRef5VDIFF adcRef5V #endif /** @endcond */ /** Sample resolution. */ typedef enum { adcRes12Bit = _ADC_SINGLECTRL_RES_12BIT, /**< 12 bit sampling. */ adcRes8Bit = _ADC_SINGLECTRL_RES_8BIT, /**< 8 bit sampling. */ adcRes6Bit = _ADC_SINGLECTRL_RES_6BIT, /**< 6 bit sampling. */ adcResOVS = _ADC_SINGLECTRL_RES_OVS /**< Oversampling. */ } ADC_Res_TypeDef; #if defined(_ADC_SINGLECTRL_INPUTSEL_MASK) /** Single sample input selection. */ typedef enum { /* Differential mode disabled */ adcSingleInputCh0 = _ADC_SINGLECTRL_INPUTSEL_CH0, /**< Channel 0. */ adcSingleInputCh1 = _ADC_SINGLECTRL_INPUTSEL_CH1, /**< Channel 1. */ adcSingleInputCh2 = _ADC_SINGLECTRL_INPUTSEL_CH2, /**< Channel 2. */ adcSingleInputCh3 = _ADC_SINGLECTRL_INPUTSEL_CH3, /**< Channel 3. */ adcSingleInputCh4 = _ADC_SINGLECTRL_INPUTSEL_CH4, /**< Channel 4. */ adcSingleInputCh5 = _ADC_SINGLECTRL_INPUTSEL_CH5, /**< Channel 5. */ adcSingleInputCh6 = _ADC_SINGLECTRL_INPUTSEL_CH6, /**< Channel 6. */ adcSingleInputCh7 = _ADC_SINGLECTRL_INPUTSEL_CH7, /**< Channel 7. */ adcSingleInputTemp = _ADC_SINGLECTRL_INPUTSEL_TEMP, /**< Temperature reference. */ adcSingleInputVDDDiv3 = _ADC_SINGLECTRL_INPUTSEL_VDDDIV3, /**< VDD divided by 3. */ adcSingleInputVDD = _ADC_SINGLECTRL_INPUTSEL_VDD, /**< VDD. */ adcSingleInputVSS = _ADC_SINGLECTRL_INPUTSEL_VSS, /**< VSS. */ adcSingleInputVrefDiv2 = _ADC_SINGLECTRL_INPUTSEL_VREFDIV2, /**< Vref divided by 2. */ adcSingleInputDACOut0 = _ADC_SINGLECTRL_INPUTSEL_DAC0OUT0, /**< DAC output 0. */ adcSingleInputDACOut1 = _ADC_SINGLECTRL_INPUTSEL_DAC0OUT1, /**< DAC output 1. */ adcSingleInputATEST = 15, /**< ATEST. */ /* Differential mode enabled */ adcSingleInputCh0Ch1 = _ADC_SINGLECTRL_INPUTSEL_CH0CH1, /**< Positive Ch0, negative Ch1. */ adcSingleInputCh2Ch3 = _ADC_SINGLECTRL_INPUTSEL_CH2CH3, /**< Positive Ch2, negative Ch3. */ adcSingleInputCh4Ch5 = _ADC_SINGLECTRL_INPUTSEL_CH4CH5, /**< Positive Ch4, negative Ch5. */ adcSingleInputCh6Ch7 = _ADC_SINGLECTRL_INPUTSEL_CH6CH7, /**< Positive Ch6, negative Ch7. */ adcSingleInputDiff0 = 4 /**< Differential 0. */ } ADC_SingleInput_TypeDef; /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ /* Deprecated enum names */ #define adcSingleInpCh0 adcSingleInputCh0 #define adcSingleInpCh1 adcSingleInputCh1 #define adcSingleInpCh2 adcSingleInputCh2 #define adcSingleInpCh3 adcSingleInputCh3 #define adcSingleInpCh4 adcSingleInputCh4 #define adcSingleInpCh5 adcSingleInputCh5 #define adcSingleInpCh6 adcSingleInputCh6 #define adcSingleInpCh7 adcSingleInputCh7 #define adcSingleInpTemp adcSingleInputTemp #define adcSingleInpVDDDiv3 adcSingleInputVDDDiv3 #define adcSingleInpVDD adcSingleInputVDD #define adcSingleInpVSS adcSingleInputVSS #define adcSingleInpVrefDiv2 adcSingleInputVrefDiv2 #define adcSingleInpDACOut0 adcSingleInputDACOut0 #define adcSingleInpDACOut1 adcSingleInputDACOut1 #define adcSingleInpATEST adcSingleInputATEST #define adcSingleInpCh0Ch1 adcSingleInputCh0Ch1 #define adcSingleInpCh2Ch3 adcSingleInputCh2Ch3 #define adcSingleInpCh4Ch5 adcSingleInputCh4Ch5 #define adcSingleInpCh6Ch7 adcSingleInputCh6Ch7 #define adcSingleInpDiff0 adcSingleInputDiff0 /** @endcond */ #endif #if defined(_ADC_SINGLECTRL_POSSEL_MASK) /** Positive input selection for single and scan coversion. */ typedef enum { adcPosSelAPORT0XCH0 = _ADC_SINGLECTRL_POSSEL_APORT0XCH0, adcPosSelAPORT0XCH1 = _ADC_SINGLECTRL_POSSEL_APORT0XCH1, adcPosSelAPORT0XCH2 = _ADC_SINGLECTRL_POSSEL_APORT0XCH2, adcPosSelAPORT0XCH3 = _ADC_SINGLECTRL_POSSEL_APORT0XCH3, adcPosSelAPORT0XCH4 = _ADC_SINGLECTRL_POSSEL_APORT0XCH4, adcPosSelAPORT0XCH5 = _ADC_SINGLECTRL_POSSEL_APORT0XCH5, adcPosSelAPORT0XCH6 = _ADC_SINGLECTRL_POSSEL_APORT0XCH6, adcPosSelAPORT0XCH7 = _ADC_SINGLECTRL_POSSEL_APORT0XCH7, adcPosSelAPORT0XCH8 = _ADC_SINGLECTRL_POSSEL_APORT0XCH8, adcPosSelAPORT0XCH9 = _ADC_SINGLECTRL_POSSEL_APORT0XCH9, adcPosSelAPORT0XCH10 = _ADC_SINGLECTRL_POSSEL_APORT0XCH10, adcPosSelAPORT0XCH11 = _ADC_SINGLECTRL_POSSEL_APORT0XCH11, adcPosSelAPORT0XCH12 = _ADC_SINGLECTRL_POSSEL_APORT0XCH12, adcPosSelAPORT0XCH13 = _ADC_SINGLECTRL_POSSEL_APORT0XCH13, adcPosSelAPORT0XCH14 = _ADC_SINGLECTRL_POSSEL_APORT0XCH14, adcPosSelAPORT0XCH15 = _ADC_SINGLECTRL_POSSEL_APORT0XCH15, adcPosSelAPORT0YCH0 = _ADC_SINGLECTRL_POSSEL_APORT0YCH0, adcPosSelAPORT0YCH1 = _ADC_SINGLECTRL_POSSEL_APORT0YCH1, adcPosSelAPORT0YCH2 = _ADC_SINGLECTRL_POSSEL_APORT0YCH2, adcPosSelAPORT0YCH3 = _ADC_SINGLECTRL_POSSEL_APORT0YCH3, adcPosSelAPORT0YCH4 = _ADC_SINGLECTRL_POSSEL_APORT0YCH4, adcPosSelAPORT0YCH5 = _ADC_SINGLECTRL_POSSEL_APORT0YCH5, adcPosSelAPORT0YCH6 = _ADC_SINGLECTRL_POSSEL_APORT0YCH6, adcPosSelAPORT0YCH7 = _ADC_SINGLECTRL_POSSEL_APORT0YCH7, adcPosSelAPORT0YCH8 = _ADC_SINGLECTRL_POSSEL_APORT0YCH8, adcPosSelAPORT0YCH9 = _ADC_SINGLECTRL_POSSEL_APORT0YCH9, adcPosSelAPORT0YCH10 = _ADC_SINGLECTRL_POSSEL_APORT0YCH10, adcPosSelAPORT0YCH11 = _ADC_SINGLECTRL_POSSEL_APORT0YCH11, adcPosSelAPORT0YCH12 = _ADC_SINGLECTRL_POSSEL_APORT0YCH12, adcPosSelAPORT0YCH13 = _ADC_SINGLECTRL_POSSEL_APORT0YCH13, adcPosSelAPORT0YCH14 = _ADC_SINGLECTRL_POSSEL_APORT0YCH14, adcPosSelAPORT0YCH15 = _ADC_SINGLECTRL_POSSEL_APORT0YCH15, adcPosSelAPORT1XCH0 = _ADC_SINGLECTRL_POSSEL_APORT1XCH0, adcPosSelAPORT1YCH1 = _ADC_SINGLECTRL_POSSEL_APORT1YCH1, adcPosSelAPORT1XCH2 = _ADC_SINGLECTRL_POSSEL_APORT1XCH2, adcPosSelAPORT1YCH3 = _ADC_SINGLECTRL_POSSEL_APORT1YCH3, adcPosSelAPORT1XCH4 = _ADC_SINGLECTRL_POSSEL_APORT1XCH4, adcPosSelAPORT1YCH5 = _ADC_SINGLECTRL_POSSEL_APORT1YCH5, adcPosSelAPORT1XCH6 = _ADC_SINGLECTRL_POSSEL_APORT1XCH6, adcPosSelAPORT1YCH7 = _ADC_SINGLECTRL_POSSEL_APORT1YCH7, adcPosSelAPORT1XCH8 = _ADC_SINGLECTRL_POSSEL_APORT1XCH8, adcPosSelAPORT1YCH9 = _ADC_SINGLECTRL_POSSEL_APORT1YCH9, adcPosSelAPORT1XCH10 = _ADC_SINGLECTRL_POSSEL_APORT1XCH10, adcPosSelAPORT1YCH11 = _ADC_SINGLECTRL_POSSEL_APORT1YCH11, adcPosSelAPORT1XCH12 = _ADC_SINGLECTRL_POSSEL_APORT1XCH12, adcPosSelAPORT1YCH13 = _ADC_SINGLECTRL_POSSEL_APORT1YCH13, adcPosSelAPORT1XCH14 = _ADC_SINGLECTRL_POSSEL_APORT1XCH14, adcPosSelAPORT1YCH15 = _ADC_SINGLECTRL_POSSEL_APORT1YCH15, adcPosSelAPORT1XCH16 = _ADC_SINGLECTRL_POSSEL_APORT1XCH16, adcPosSelAPORT1YCH17 = _ADC_SINGLECTRL_POSSEL_APORT1YCH17, adcPosSelAPORT1XCH18 = _ADC_SINGLECTRL_POSSEL_APORT1XCH18, adcPosSelAPORT1YCH19 = _ADC_SINGLECTRL_POSSEL_APORT1YCH19, adcPosSelAPORT1XCH20 = _ADC_SINGLECTRL_POSSEL_APORT1XCH20, adcPosSelAPORT1YCH21 = _ADC_SINGLECTRL_POSSEL_APORT1YCH21, adcPosSelAPORT1XCH22 = _ADC_SINGLECTRL_POSSEL_APORT1XCH22, adcPosSelAPORT1YCH23 = _ADC_SINGLECTRL_POSSEL_APORT1YCH23, adcPosSelAPORT1XCH24 = _ADC_SINGLECTRL_POSSEL_APORT1XCH24, adcPosSelAPORT1YCH25 = _ADC_SINGLECTRL_POSSEL_APORT1YCH25, adcPosSelAPORT1XCH26 = _ADC_SINGLECTRL_POSSEL_APORT1XCH26, adcPosSelAPORT1YCH27 = _ADC_SINGLECTRL_POSSEL_APORT1YCH27, adcPosSelAPORT1XCH28 = _ADC_SINGLECTRL_POSSEL_APORT1XCH28, adcPosSelAPORT1YCH29 = _ADC_SINGLECTRL_POSSEL_APORT1YCH29, adcPosSelAPORT1XCH30 = _ADC_SINGLECTRL_POSSEL_APORT1XCH30, adcPosSelAPORT1YCH31 = _ADC_SINGLECTRL_POSSEL_APORT1YCH31, adcPosSelAPORT2YCH0 = _ADC_SINGLECTRL_POSSEL_APORT2YCH0, adcPosSelAPORT2XCH1 = _ADC_SINGLECTRL_POSSEL_APORT2XCH1, adcPosSelAPORT2YCH2 = _ADC_SINGLECTRL_POSSEL_APORT2YCH2, adcPosSelAPORT2XCH3 = _ADC_SINGLECTRL_POSSEL_APORT2XCH3, adcPosSelAPORT2YCH4 = _ADC_SINGLECTRL_POSSEL_APORT2YCH4, adcPosSelAPORT2XCH5 = _ADC_SINGLECTRL_POSSEL_APORT2XCH5, adcPosSelAPORT2YCH6 = _ADC_SINGLECTRL_POSSEL_APORT2YCH6, adcPosSelAPORT2XCH7 = _ADC_SINGLECTRL_POSSEL_APORT2XCH7, adcPosSelAPORT2YCH8 = _ADC_SINGLECTRL_POSSEL_APORT2YCH8, adcPosSelAPORT2XCH9 = _ADC_SINGLECTRL_POSSEL_APORT2XCH9, adcPosSelAPORT2YCH10 = _ADC_SINGLECTRL_POSSEL_APORT2YCH10, adcPosSelAPORT2XCH11 = _ADC_SINGLECTRL_POSSEL_APORT2XCH11, adcPosSelAPORT2YCH12 = _ADC_SINGLECTRL_POSSEL_APORT2YCH12, adcPosSelAPORT2XCH13 = _ADC_SINGLECTRL_POSSEL_APORT2XCH13, adcPosSelAPORT2YCH14 = _ADC_SINGLECTRL_POSSEL_APORT2YCH14, adcPosSelAPORT2XCH15 = _ADC_SINGLECTRL_POSSEL_APORT2XCH15, adcPosSelAPORT2YCH16 = _ADC_SINGLECTRL_POSSEL_APORT2YCH16, adcPosSelAPORT2XCH17 = _ADC_SINGLECTRL_POSSEL_APORT2XCH17, adcPosSelAPORT2YCH18 = _ADC_SINGLECTRL_POSSEL_APORT2YCH18, adcPosSelAPORT2XCH19 = _ADC_SINGLECTRL_POSSEL_APORT2XCH19, adcPosSelAPORT2YCH20 = _ADC_SINGLECTRL_POSSEL_APORT2YCH20, adcPosSelAPORT2XCH21 = _ADC_SINGLECTRL_POSSEL_APORT2XCH21, adcPosSelAPORT2YCH22 = _ADC_SINGLECTRL_POSSEL_APORT2YCH22, adcPosSelAPORT2XCH23 = _ADC_SINGLECTRL_POSSEL_APORT2XCH23, adcPosSelAPORT2YCH24 = _ADC_SINGLECTRL_POSSEL_APORT2YCH24, adcPosSelAPORT2XCH25 = _ADC_SINGLECTRL_POSSEL_APORT2XCH25, adcPosSelAPORT2YCH26 = _ADC_SINGLECTRL_POSSEL_APORT2YCH26, adcPosSelAPORT2XCH27 = _ADC_SINGLECTRL_POSSEL_APORT2XCH27, adcPosSelAPORT2YCH28 = _ADC_SINGLECTRL_POSSEL_APORT2YCH28, adcPosSelAPORT2XCH29 = _ADC_SINGLECTRL_POSSEL_APORT2XCH29, adcPosSelAPORT2YCH30 = _ADC_SINGLECTRL_POSSEL_APORT2YCH30, adcPosSelAPORT2XCH31 = _ADC_SINGLECTRL_POSSEL_APORT2XCH31, adcPosSelAPORT3XCH0 = _ADC_SINGLECTRL_POSSEL_APORT3XCH0, adcPosSelAPORT3YCH1 = _ADC_SINGLECTRL_POSSEL_APORT3YCH1, adcPosSelAPORT3XCH2 = _ADC_SINGLECTRL_POSSEL_APORT3XCH2, adcPosSelAPORT3YCH3 = _ADC_SINGLECTRL_POSSEL_APORT3YCH3, adcPosSelAPORT3XCH4 = _ADC_SINGLECTRL_POSSEL_APORT3XCH4, adcPosSelAPORT3YCH5 = _ADC_SINGLECTRL_POSSEL_APORT3YCH5, adcPosSelAPORT3XCH6 = _ADC_SINGLECTRL_POSSEL_APORT3XCH6, adcPosSelAPORT3YCH7 = _ADC_SINGLECTRL_POSSEL_APORT3YCH7, adcPosSelAPORT3XCH8 = _ADC_SINGLECTRL_POSSEL_APORT3XCH8, adcPosSelAPORT3YCH9 = _ADC_SINGLECTRL_POSSEL_APORT3YCH9, adcPosSelAPORT3XCH10 = _ADC_SINGLECTRL_POSSEL_APORT3XCH10, adcPosSelAPORT3YCH11 = _ADC_SINGLECTRL_POSSEL_APORT3YCH11, adcPosSelAPORT3XCH12 = _ADC_SINGLECTRL_POSSEL_APORT3XCH12, adcPosSelAPORT3YCH13 = _ADC_SINGLECTRL_POSSEL_APORT3YCH13, adcPosSelAPORT3XCH14 = _ADC_SINGLECTRL_POSSEL_APORT3XCH14, adcPosSelAPORT3YCH15 = _ADC_SINGLECTRL_POSSEL_APORT3YCH15, adcPosSelAPORT3XCH16 = _ADC_SINGLECTRL_POSSEL_APORT3XCH16, adcPosSelAPORT3YCH17 = _ADC_SINGLECTRL_POSSEL_APORT3YCH17, adcPosSelAPORT3XCH18 = _ADC_SINGLECTRL_POSSEL_APORT3XCH18, adcPosSelAPORT3YCH19 = _ADC_SINGLECTRL_POSSEL_APORT3YCH19, adcPosSelAPORT3XCH20 = _ADC_SINGLECTRL_POSSEL_APORT3XCH20, adcPosSelAPORT3YCH21 = _ADC_SINGLECTRL_POSSEL_APORT3YCH21, adcPosSelAPORT3XCH22 = _ADC_SINGLECTRL_POSSEL_APORT3XCH22, adcPosSelAPORT3YCH23 = _ADC_SINGLECTRL_POSSEL_APORT3YCH23, adcPosSelAPORT3XCH24 = _ADC_SINGLECTRL_POSSEL_APORT3XCH24, adcPosSelAPORT3YCH25 = _ADC_SINGLECTRL_POSSEL_APORT3YCH25, adcPosSelAPORT3XCH26 = _ADC_SINGLECTRL_POSSEL_APORT3XCH26, adcPosSelAPORT3YCH27 = _ADC_SINGLECTRL_POSSEL_APORT3YCH27, adcPosSelAPORT3XCH28 = _ADC_SINGLECTRL_POSSEL_APORT3XCH28, adcPosSelAPORT3YCH29 = _ADC_SINGLECTRL_POSSEL_APORT3YCH29, adcPosSelAPORT3XCH30 = _ADC_SINGLECTRL_POSSEL_APORT3XCH30, adcPosSelAPORT3YCH31 = _ADC_SINGLECTRL_POSSEL_APORT3YCH31, adcPosSelAPORT4YCH0 = _ADC_SINGLECTRL_POSSEL_APORT4YCH0, adcPosSelAPORT4XCH1 = _ADC_SINGLECTRL_POSSEL_APORT4XCH1, adcPosSelAPORT4YCH2 = _ADC_SINGLECTRL_POSSEL_APORT4YCH2, adcPosSelAPORT4XCH3 = _ADC_SINGLECTRL_POSSEL_APORT4XCH3, adcPosSelAPORT4YCH4 = _ADC_SINGLECTRL_POSSEL_APORT4YCH4, adcPosSelAPORT4XCH5 = _ADC_SINGLECTRL_POSSEL_APORT4XCH5, adcPosSelAPORT4YCH6 = _ADC_SINGLECTRL_POSSEL_APORT4YCH6, adcPosSelAPORT4XCH7 = _ADC_SINGLECTRL_POSSEL_APORT4XCH7, adcPosSelAPORT4YCH8 = _ADC_SINGLECTRL_POSSEL_APORT4YCH8, adcPosSelAPORT4XCH9 = _ADC_SINGLECTRL_POSSEL_APORT4XCH9, adcPosSelAPORT4YCH10 = _ADC_SINGLECTRL_POSSEL_APORT4YCH10, adcPosSelAPORT4XCH11 = _ADC_SINGLECTRL_POSSEL_APORT4XCH11, adcPosSelAPORT4YCH12 = _ADC_SINGLECTRL_POSSEL_APORT4YCH12, adcPosSelAPORT4XCH13 = _ADC_SINGLECTRL_POSSEL_APORT4XCH13, adcPosSelAPORT4YCH14 = _ADC_SINGLECTRL_POSSEL_APORT4YCH14, adcPosSelAPORT4XCH15 = _ADC_SINGLECTRL_POSSEL_APORT4XCH15, adcPosSelAPORT4YCH16 = _ADC_SINGLECTRL_POSSEL_APORT4YCH16, adcPosSelAPORT4XCH17 = _ADC_SINGLECTRL_POSSEL_APORT4XCH17, adcPosSelAPORT4YCH18 = _ADC_SINGLECTRL_POSSEL_APORT4YCH18, adcPosSelAPORT4XCH19 = _ADC_SINGLECTRL_POSSEL_APORT4XCH19, adcPosSelAPORT4YCH20 = _ADC_SINGLECTRL_POSSEL_APORT4YCH20, adcPosSelAPORT4XCH21 = _ADC_SINGLECTRL_POSSEL_APORT4XCH21, adcPosSelAPORT4YCH22 = _ADC_SINGLECTRL_POSSEL_APORT4YCH22, adcPosSelAPORT4XCH23 = _ADC_SINGLECTRL_POSSEL_APORT4XCH23, adcPosSelAPORT4YCH24 = _ADC_SINGLECTRL_POSSEL_APORT4YCH24, adcPosSelAPORT4XCH25 = _ADC_SINGLECTRL_POSSEL_APORT4XCH25, adcPosSelAPORT4YCH26 = _ADC_SINGLECTRL_POSSEL_APORT4YCH26, adcPosSelAPORT4XCH27 = _ADC_SINGLECTRL_POSSEL_APORT4XCH27, adcPosSelAPORT4YCH28 = _ADC_SINGLECTRL_POSSEL_APORT4YCH28, adcPosSelAPORT4XCH29 = _ADC_SINGLECTRL_POSSEL_APORT4XCH29, adcPosSelAPORT4YCH30 = _ADC_SINGLECTRL_POSSEL_APORT4YCH30, adcPosSelAPORT4XCH31 = _ADC_SINGLECTRL_POSSEL_APORT4XCH31, adcPosSelAVDD = _ADC_SINGLECTRL_POSSEL_AVDD, adcPosSelBUVDD = _ADC_SINGLECTRL_POSSEL_BUVDD, adcPosSelDVDD = _ADC_SINGLECTRL_POSSEL_DVDD, adcPosSelPAVDD = _ADC_SINGLECTRL_POSSEL_PAVDD, adcPosSelDECOUPLE = _ADC_SINGLECTRL_POSSEL_DECOUPLE, adcPosSelIOVDD = _ADC_SINGLECTRL_POSSEL_IOVDD, adcPosSelIOVDD1 = _ADC_SINGLECTRL_POSSEL_IOVDD1, adcPosSelVSP = _ADC_SINGLECTRL_POSSEL_VSP, adcPosSelOPA2 = _ADC_SINGLECTRL_POSSEL_OPA2, adcPosSelTEMP = _ADC_SINGLECTRL_POSSEL_TEMP, adcPosSelDAC0OUT0 = _ADC_SINGLECTRL_POSSEL_DAC0OUT0, adcPosSelR5VOUT = _ADC_SINGLECTRL_POSSEL_R5VOUT, adcPosSelSP1 = _ADC_SINGLECTRL_POSSEL_SP1, adcPosSelSP2 = _ADC_SINGLECTRL_POSSEL_SP2, adcPosSelDAC0OUT1 = _ADC_SINGLECTRL_POSSEL_DAC0OUT1, adcPosSelSUBLSB = _ADC_SINGLECTRL_POSSEL_SUBLSB, adcPosSelOPA3 = _ADC_SINGLECTRL_POSSEL_OPA3, adcPosSelDEFAULT = _ADC_SINGLECTRL_POSSEL_DEFAULT, adcPosSelVSS = _ADC_SINGLECTRL_POSSEL_VSS } ADC_PosSel_TypeDef; /* Map legacy or incorrectly named select enums to correct enums. */ #define adcPosSelIO0 adcPosSelIOVDD #define adcPosSelVREGOUTPA adcPosSelPAVDD #define adcPosSelAREG adcPosSelDVDD #define adcPosSelPDBU adcPosSelDECOUPLE #endif #if defined(_ADC_SINGLECTRL_NEGSEL_MASK) /** Negative input selection for single and scan conversion. */ typedef enum { adcNegSelAPORT0XCH0 = _ADC_SINGLECTRL_NEGSEL_APORT0XCH0, adcNegSelAPORT0XCH1 = _ADC_SINGLECTRL_NEGSEL_APORT0XCH1, adcNegSelAPORT0XCH2 = _ADC_SINGLECTRL_NEGSEL_APORT0XCH2, adcNegSelAPORT0XCH3 = _ADC_SINGLECTRL_NEGSEL_APORT0XCH3, adcNegSelAPORT0XCH4 = _ADC_SINGLECTRL_NEGSEL_APORT0XCH4, adcNegSelAPORT0XCH5 = _ADC_SINGLECTRL_NEGSEL_APORT0XCH5, adcNegSelAPORT0XCH6 = _ADC_SINGLECTRL_NEGSEL_APORT0XCH6, adcNegSelAPORT0XCH7 = _ADC_SINGLECTRL_NEGSEL_APORT0XCH7, adcNegSelAPORT0XCH8 = _ADC_SINGLECTRL_NEGSEL_APORT0XCH8, adcNegSelAPORT0XCH9 = _ADC_SINGLECTRL_NEGSEL_APORT0XCH9, adcNegSelAPORT0XCH10 = _ADC_SINGLECTRL_NEGSEL_APORT0XCH10, adcNegSelAPORT0XCH11 = _ADC_SINGLECTRL_NEGSEL_APORT0XCH11, adcNegSelAPORT0XCH12 = _ADC_SINGLECTRL_NEGSEL_APORT0XCH12, adcNegSelAPORT0XCH13 = _ADC_SINGLECTRL_NEGSEL_APORT0XCH13, adcNegSelAPORT0XCH14 = _ADC_SINGLECTRL_NEGSEL_APORT0XCH14, adcNegSelAPORT0XCH15 = _ADC_SINGLECTRL_NEGSEL_APORT0XCH15, adcNegSelAPORT0YCH0 = _ADC_SINGLECTRL_NEGSEL_APORT0YCH0, adcNegSelAPORT0YCH1 = _ADC_SINGLECTRL_NEGSEL_APORT0YCH1, adcNegSelAPORT0YCH2 = _ADC_SINGLECTRL_NEGSEL_APORT0YCH2, adcNegSelAPORT0YCH3 = _ADC_SINGLECTRL_NEGSEL_APORT0YCH3, adcNegSelAPORT0YCH4 = _ADC_SINGLECTRL_NEGSEL_APORT0YCH4, adcNegSelAPORT0YCH5 = _ADC_SINGLECTRL_NEGSEL_APORT0YCH5, adcNegSelAPORT0YCH6 = _ADC_SINGLECTRL_NEGSEL_APORT0YCH6, adcNegSelAPORT0YCH7 = _ADC_SINGLECTRL_NEGSEL_APORT0YCH7, adcNegSelAPORT0YCH8 = _ADC_SINGLECTRL_NEGSEL_APORT0YCH8, adcNegSelAPORT0YCH9 = _ADC_SINGLECTRL_NEGSEL_APORT0YCH9, adcNegSelAPORT0YCH10 = _ADC_SINGLECTRL_NEGSEL_APORT0YCH10, adcNegSelAPORT0YCH11 = _ADC_SINGLECTRL_NEGSEL_APORT0YCH11, adcNegSelAPORT0YCH12 = _ADC_SINGLECTRL_NEGSEL_APORT0YCH12, adcNegSelAPORT0YCH13 = _ADC_SINGLECTRL_NEGSEL_APORT0YCH13, adcNegSelAPORT0YCH14 = _ADC_SINGLECTRL_NEGSEL_APORT0YCH14, adcNegSelAPORT0YCH15 = _ADC_SINGLECTRL_NEGSEL_APORT0YCH15, adcNegSelAPORT1XCH0 = _ADC_SINGLECTRL_NEGSEL_APORT1XCH0, adcNegSelAPORT1YCH1 = _ADC_SINGLECTRL_NEGSEL_APORT1YCH1, adcNegSelAPORT1XCH2 = _ADC_SINGLECTRL_NEGSEL_APORT1XCH2, adcNegSelAPORT1YCH3 = _ADC_SINGLECTRL_NEGSEL_APORT1YCH3, adcNegSelAPORT1XCH4 = _ADC_SINGLECTRL_NEGSEL_APORT1XCH4, adcNegSelAPORT1YCH5 = _ADC_SINGLECTRL_NEGSEL_APORT1YCH5, adcNegSelAPORT1XCH6 = _ADC_SINGLECTRL_NEGSEL_APORT1XCH6, adcNegSelAPORT1YCH7 = _ADC_SINGLECTRL_NEGSEL_APORT1YCH7, adcNegSelAPORT1XCH8 = _ADC_SINGLECTRL_NEGSEL_APORT1XCH8, adcNegSelAPORT1YCH9 = _ADC_SINGLECTRL_NEGSEL_APORT1YCH9, adcNegSelAPORT1XCH10 = _ADC_SINGLECTRL_NEGSEL_APORT1XCH10, adcNegSelAPORT1YCH11 = _ADC_SINGLECTRL_NEGSEL_APORT1YCH11, adcNegSelAPORT1XCH12 = _ADC_SINGLECTRL_NEGSEL_APORT1XCH12, adcNegSelAPORT1YCH13 = _ADC_SINGLECTRL_NEGSEL_APORT1YCH13, adcNegSelAPORT1XCH14 = _ADC_SINGLECTRL_NEGSEL_APORT1XCH14, adcNegSelAPORT1YCH15 = _ADC_SINGLECTRL_NEGSEL_APORT1YCH15, adcNegSelAPORT1XCH16 = _ADC_SINGLECTRL_NEGSEL_APORT1XCH16, adcNegSelAPORT1YCH17 = _ADC_SINGLECTRL_NEGSEL_APORT1YCH17, adcNegSelAPORT1XCH18 = _ADC_SINGLECTRL_NEGSEL_APORT1XCH18, adcNegSelAPORT1YCH19 = _ADC_SINGLECTRL_NEGSEL_APORT1YCH19, adcNegSelAPORT1XCH20 = _ADC_SINGLECTRL_NEGSEL_APORT1XCH20, adcNegSelAPORT1YCH21 = _ADC_SINGLECTRL_NEGSEL_APORT1YCH21, adcNegSelAPORT1XCH22 = _ADC_SINGLECTRL_NEGSEL_APORT1XCH22, adcNegSelAPORT1YCH23 = _ADC_SINGLECTRL_NEGSEL_APORT1YCH23, adcNegSelAPORT1XCH24 = _ADC_SINGLECTRL_NEGSEL_APORT1XCH24, adcNegSelAPORT1YCH25 = _ADC_SINGLECTRL_NEGSEL_APORT1YCH25, adcNegSelAPORT1XCH26 = _ADC_SINGLECTRL_NEGSEL_APORT1XCH26, adcNegSelAPORT1YCH27 = _ADC_SINGLECTRL_NEGSEL_APORT1YCH27, adcNegSelAPORT1XCH28 = _ADC_SINGLECTRL_NEGSEL_APORT1XCH28, adcNegSelAPORT1YCH29 = _ADC_SINGLECTRL_NEGSEL_APORT1YCH29, adcNegSelAPORT1XCH30 = _ADC_SINGLECTRL_NEGSEL_APORT1XCH30, adcNegSelAPORT1YCH31 = _ADC_SINGLECTRL_NEGSEL_APORT1YCH31, adcNegSelAPORT2YCH0 = _ADC_SINGLECTRL_NEGSEL_APORT2YCH0, adcNegSelAPORT2XCH1 = _ADC_SINGLECTRL_NEGSEL_APORT2XCH1, adcNegSelAPORT2YCH2 = _ADC_SINGLECTRL_NEGSEL_APORT2YCH2, adcNegSelAPORT2XCH3 = _ADC_SINGLECTRL_NEGSEL_APORT2XCH3, adcNegSelAPORT2YCH4 = _ADC_SINGLECTRL_NEGSEL_APORT2YCH4, adcNegSelAPORT2XCH5 = _ADC_SINGLECTRL_NEGSEL_APORT2XCH5, adcNegSelAPORT2YCH6 = _ADC_SINGLECTRL_NEGSEL_APORT2YCH6, adcNegSelAPORT2XCH7 = _ADC_SINGLECTRL_NEGSEL_APORT2XCH7, adcNegSelAPORT2YCH8 = _ADC_SINGLECTRL_NEGSEL_APORT2YCH8, adcNegSelAPORT2XCH9 = _ADC_SINGLECTRL_NEGSEL_APORT2XCH9, adcNegSelAPORT2YCH10 = _ADC_SINGLECTRL_NEGSEL_APORT2YCH10, adcNegSelAPORT2XCH11 = _ADC_SINGLECTRL_NEGSEL_APORT2XCH11, adcNegSelAPORT2YCH12 = _ADC_SINGLECTRL_NEGSEL_APORT2YCH12, adcNegSelAPORT2XCH13 = _ADC_SINGLECTRL_NEGSEL_APORT2XCH13, adcNegSelAPORT2YCH14 = _ADC_SINGLECTRL_NEGSEL_APORT2YCH14, adcNegSelAPORT2XCH15 = _ADC_SINGLECTRL_NEGSEL_APORT2XCH15, adcNegSelAPORT2YCH16 = _ADC_SINGLECTRL_NEGSEL_APORT2YCH16, adcNegSelAPORT2XCH17 = _ADC_SINGLECTRL_NEGSEL_APORT2XCH17, adcNegSelAPORT2YCH18 = _ADC_SINGLECTRL_NEGSEL_APORT2YCH18, adcNegSelAPORT2XCH19 = _ADC_SINGLECTRL_NEGSEL_APORT2XCH19, adcNegSelAPORT2YCH20 = _ADC_SINGLECTRL_NEGSEL_APORT2YCH20, adcNegSelAPORT2XCH21 = _ADC_SINGLECTRL_NEGSEL_APORT2XCH21, adcNegSelAPORT2YCH22 = _ADC_SINGLECTRL_NEGSEL_APORT2YCH22, adcNegSelAPORT2XCH23 = _ADC_SINGLECTRL_NEGSEL_APORT2XCH23, adcNegSelAPORT2YCH24 = _ADC_SINGLECTRL_NEGSEL_APORT2YCH24, adcNegSelAPORT2XCH25 = _ADC_SINGLECTRL_NEGSEL_APORT2XCH25, adcNegSelAPORT2YCH26 = _ADC_SINGLECTRL_NEGSEL_APORT2YCH26, adcNegSelAPORT2XCH27 = _ADC_SINGLECTRL_NEGSEL_APORT2XCH27, adcNegSelAPORT2YCH28 = _ADC_SINGLECTRL_NEGSEL_APORT2YCH28, adcNegSelAPORT2XCH29 = _ADC_SINGLECTRL_NEGSEL_APORT2XCH29, adcNegSelAPORT2YCH30 = _ADC_SINGLECTRL_NEGSEL_APORT2YCH30, adcNegSelAPORT2XCH31 = _ADC_SINGLECTRL_NEGSEL_APORT2XCH31, adcNegSelAPORT3XCH0 = _ADC_SINGLECTRL_NEGSEL_APORT3XCH0, adcNegSelAPORT3YCH1 = _ADC_SINGLECTRL_NEGSEL_APORT3YCH1, adcNegSelAPORT3XCH2 = _ADC_SINGLECTRL_NEGSEL_APORT3XCH2, adcNegSelAPORT3YCH3 = _ADC_SINGLECTRL_NEGSEL_APORT3YCH3, adcNegSelAPORT3XCH4 = _ADC_SINGLECTRL_NEGSEL_APORT3XCH4, adcNegSelAPORT3YCH5 = _ADC_SINGLECTRL_NEGSEL_APORT3YCH5, adcNegSelAPORT3XCH6 = _ADC_SINGLECTRL_NEGSEL_APORT3XCH6, adcNegSelAPORT3YCH7 = _ADC_SINGLECTRL_NEGSEL_APORT3YCH7, adcNegSelAPORT3XCH8 = _ADC_SINGLECTRL_NEGSEL_APORT3XCH8, adcNegSelAPORT3YCH9 = _ADC_SINGLECTRL_NEGSEL_APORT3YCH9, adcNegSelAPORT3XCH10 = _ADC_SINGLECTRL_NEGSEL_APORT3XCH10, adcNegSelAPORT3YCH11 = _ADC_SINGLECTRL_NEGSEL_APORT3YCH11, adcNegSelAPORT3XCH12 = _ADC_SINGLECTRL_NEGSEL_APORT3XCH12, adcNegSelAPORT3YCH13 = _ADC_SINGLECTRL_NEGSEL_APORT3YCH13, adcNegSelAPORT3XCH14 = _ADC_SINGLECTRL_NEGSEL_APORT3XCH14, adcNegSelAPORT3YCH15 = _ADC_SINGLECTRL_NEGSEL_APORT3YCH15, adcNegSelAPORT3XCH16 = _ADC_SINGLECTRL_NEGSEL_APORT3XCH16, adcNegSelAPORT3YCH17 = _ADC_SINGLECTRL_NEGSEL_APORT3YCH17, adcNegSelAPORT3XCH18 = _ADC_SINGLECTRL_NEGSEL_APORT3XCH18, adcNegSelAPORT3YCH19 = _ADC_SINGLECTRL_NEGSEL_APORT3YCH19, adcNegSelAPORT3XCH20 = _ADC_SINGLECTRL_NEGSEL_APORT3XCH20, adcNegSelAPORT3YCH21 = _ADC_SINGLECTRL_NEGSEL_APORT3YCH21, adcNegSelAPORT3XCH22 = _ADC_SINGLECTRL_NEGSEL_APORT3XCH22, adcNegSelAPORT3YCH23 = _ADC_SINGLECTRL_NEGSEL_APORT3YCH23, adcNegSelAPORT3XCH24 = _ADC_SINGLECTRL_NEGSEL_APORT3XCH24, adcNegSelAPORT3YCH25 = _ADC_SINGLECTRL_NEGSEL_APORT3YCH25, adcNegSelAPORT3XCH26 = _ADC_SINGLECTRL_NEGSEL_APORT3XCH26, adcNegSelAPORT3YCH27 = _ADC_SINGLECTRL_NEGSEL_APORT3YCH27, adcNegSelAPORT3XCH28 = _ADC_SINGLECTRL_NEGSEL_APORT3XCH28, adcNegSelAPORT3YCH29 = _ADC_SINGLECTRL_NEGSEL_APORT3YCH29, adcNegSelAPORT3XCH30 = _ADC_SINGLECTRL_NEGSEL_APORT3XCH30, adcNegSelAPORT3YCH31 = _ADC_SINGLECTRL_NEGSEL_APORT3YCH31, adcNegSelAPORT4YCH0 = _ADC_SINGLECTRL_NEGSEL_APORT4YCH0, adcNegSelAPORT4XCH1 = _ADC_SINGLECTRL_NEGSEL_APORT4XCH1, adcNegSelAPORT4YCH2 = _ADC_SINGLECTRL_NEGSEL_APORT4YCH2, adcNegSelAPORT4XCH3 = _ADC_SINGLECTRL_NEGSEL_APORT4XCH3, adcNegSelAPORT4YCH4 = _ADC_SINGLECTRL_NEGSEL_APORT4YCH4, adcNegSelAPORT4XCH5 = _ADC_SINGLECTRL_NEGSEL_APORT4XCH5, adcNegSelAPORT4YCH6 = _ADC_SINGLECTRL_NEGSEL_APORT4YCH6, adcNegSelAPORT4XCH7 = _ADC_SINGLECTRL_NEGSEL_APORT4XCH7, adcNegSelAPORT4YCH8 = _ADC_SINGLECTRL_NEGSEL_APORT4YCH8, adcNegSelAPORT4XCH9 = _ADC_SINGLECTRL_NEGSEL_APORT4XCH9, adcNegSelAPORT4YCH10 = _ADC_SINGLECTRL_NEGSEL_APORT4YCH10, adcNegSelAPORT4XCH11 = _ADC_SINGLECTRL_NEGSEL_APORT4XCH11, adcNegSelAPORT4YCH12 = _ADC_SINGLECTRL_NEGSEL_APORT4YCH12, adcNegSelAPORT4XCH13 = _ADC_SINGLECTRL_NEGSEL_APORT4XCH13, adcNegSelAPORT4YCH14 = _ADC_SINGLECTRL_NEGSEL_APORT4YCH14, adcNegSelAPORT4XCH15 = _ADC_SINGLECTRL_NEGSEL_APORT4XCH15, adcNegSelAPORT4YCH16 = _ADC_SINGLECTRL_NEGSEL_APORT4YCH16, adcNegSelAPORT4XCH17 = _ADC_SINGLECTRL_NEGSEL_APORT4XCH17, adcNegSelAPORT4YCH18 = _ADC_SINGLECTRL_NEGSEL_APORT4YCH18, adcNegSelAPORT4XCH19 = _ADC_SINGLECTRL_NEGSEL_APORT4XCH19, adcNegSelAPORT4YCH20 = _ADC_SINGLECTRL_NEGSEL_APORT4YCH20, adcNegSelAPORT4XCH21 = _ADC_SINGLECTRL_NEGSEL_APORT4XCH21, adcNegSelAPORT4YCH22 = _ADC_SINGLECTRL_NEGSEL_APORT4YCH22, adcNegSelAPORT4XCH23 = _ADC_SINGLECTRL_NEGSEL_APORT4XCH23, adcNegSelAPORT4YCH24 = _ADC_SINGLECTRL_NEGSEL_APORT4YCH24, adcNegSelAPORT4XCH25 = _ADC_SINGLECTRL_NEGSEL_APORT4XCH25, adcNegSelAPORT4YCH26 = _ADC_SINGLECTRL_NEGSEL_APORT4YCH26, adcNegSelAPORT4XCH27 = _ADC_SINGLECTRL_NEGSEL_APORT4XCH27, adcNegSelAPORT4YCH28 = _ADC_SINGLECTRL_NEGSEL_APORT4YCH28, adcNegSelAPORT4XCH29 = _ADC_SINGLECTRL_NEGSEL_APORT4XCH29, adcNegSelAPORT4YCH30 = _ADC_SINGLECTRL_NEGSEL_APORT4YCH30, adcNegSelAPORT4XCH31 = _ADC_SINGLECTRL_NEGSEL_APORT4XCH31, adcNegSelTESTN = _ADC_SINGLECTRL_NEGSEL_TESTN, adcNegSelDEFAULT = _ADC_SINGLECTRL_NEGSEL_DEFAULT, adcNegSelVSS = _ADC_SINGLECTRL_NEGSEL_VSS } ADC_NegSel_TypeDef; #endif #if defined(_ADC_SCANINPUTSEL_MASK) /* ADC scan input groups. */ typedef enum { adcScanInputGroup0 = 0, adcScanInputGroup1 = 1, adcScanInputGroup2 = 2, adcScanInputGroup3 = 3, } ADC_ScanInputGroup_TypeDef; /* Define none selected for ADC_SCANINPUTSEL. */ #define ADC_SCANINPUTSEL_GROUP_NONE 0xFFU #define ADC_SCANINPUTSEL_NONE ((ADC_SCANINPUTSEL_GROUP_NONE \ << _ADC_SCANINPUTSEL_INPUT0TO7SEL_SHIFT) \ | (ADC_SCANINPUTSEL_GROUP_NONE \ << _ADC_SCANINPUTSEL_INPUT8TO15SEL_SHIFT) \ | (ADC_SCANINPUTSEL_GROUP_NONE \ << _ADC_SCANINPUTSEL_INPUT16TO23SEL_SHIFT) \ | (ADC_SCANINPUTSEL_GROUP_NONE \ << _ADC_SCANINPUTSEL_INPUT24TO31SEL_SHIFT)) /* ADC scan alternative negative inputs. */ typedef enum { adcScanNegInput1 = 1, adcScanNegInput3 = 3, adcScanNegInput5 = 5, adcScanNegInput7 = 7, adcScanNegInput8 = 8, adcScanNegInput10 = 10, adcScanNegInput12 = 12, adcScanNegInput14 = 14, adcScanNegInputDefault = 0xFF, } ADC_ScanNegInput_TypeDef; #endif /** ADC start command. */ typedef enum { /** Start a single conversion. */ adcStartSingle = ADC_CMD_SINGLESTART, /** Start a scan sequence. */ adcStartScan = ADC_CMD_SCANSTART, /** * Start a scan sequence and single conversion, typically used when tailgating * a single conversion after a scan sequence. */ adcStartScanAndSingle = ADC_CMD_SCANSTART | ADC_CMD_SINGLESTART } ADC_Start_TypeDef; /** Warm-up mode. */ typedef enum { /** ADC shutdown after each conversion. */ adcWarmupNormal = _ADC_CTRL_WARMUPMODE_NORMAL, #if defined(_ADC_CTRL_WARMUPMODE_FASTBG) /** Do not warm up bandgap references. */ adcWarmupFastBG = _ADC_CTRL_WARMUPMODE_FASTBG, #endif #if defined(_ADC_CTRL_WARMUPMODE_KEEPSCANREFWARM) /** Reference selected for scan mode kept warm.*/ adcWarmupKeepScanRefWarm = _ADC_CTRL_WARMUPMODE_KEEPSCANREFWARM, #endif #if defined(_ADC_CTRL_WARMUPMODE_KEEPINSTANDBY) /** ADC is kept in standby mode between conversions. 1 us warmup time needed before the next conversion. */ adcWarmupKeepInStandby = _ADC_CTRL_WARMUPMODE_KEEPINSTANDBY, #endif #if defined(_ADC_CTRL_WARMUPMODE_KEEPINSLOWACC) /** ADC is kept in slow acquisition mode between conversions. 1 us warmup time needed before the next conversion. */ adcWarmupKeepInSlowAcq = _ADC_CTRL_WARMUPMODE_KEEPINSLOWACC, #endif /** ADC and reference selected for scan mode kept at warmup allowing continuous conversion. */ adcWarmupKeepADCWarm = _ADC_CTRL_WARMUPMODE_KEEPADCWARM, } ADC_Warmup_TypeDef; #if defined(_ADC_CTRL_ADCCLKMODE_MASK) /** ADC EM2 clock configuration. */ typedef enum { adcEm2Disabled = 0, adcEm2ClockOnDemand = ADC_CTRL_ADCCLKMODE_ASYNC | ADC_CTRL_ASYNCCLKEN_ASNEEDED, adcEm2ClockAlwaysOn = ADC_CTRL_ADCCLKMODE_ASYNC | ADC_CTRL_ASYNCCLKEN_ALWAYSON, } ADC_EM2ClockConfig_TypeDef; #endif /******************************************************************************* ******************************* STRUCTS *********************************** ******************************************************************************/ /** ADC initialization structure, common for single conversion and scan sequence. */ typedef struct { /** * Oversampling rate select. To have any effect, oversampling must * be enabled for single/scan mode. */ ADC_OvsRateSel_TypeDef ovsRateSel; #if defined(_ADC_CTRL_LPFMODE_MASK) /** Lowpass or decoupling capacitor filter. */ ADC_LPFilter_TypeDef lpfMode; #endif /** ADC Warm-up mode. */ ADC_Warmup_TypeDef warmUpMode; /** * Timebase for ADC warm up. Select N to give (N+1) HFPERCLK / HFPERCCLK cycles. * (Additional delay is added for bandgap references. See the * reference manual for more information.) Normally, N should be selected so that the timebase * is at least 1 us. See ADC_TimebaseCalc() to obtain * a suggested timebase of, at least, 1 us. */ uint8_t timebase; /** Clock division factor N, ADC clock = (HFPERCLK or HFPERCCLK) / (N + 1). */ uint8_t prescale; /** Enable/disable conversion tailgating. */ bool tailgate; /** ADC EM2 clock configuration */ #if defined(_ADC_CTRL_ADCCLKMODE_MASK) ADC_EM2ClockConfig_TypeDef em2ClockConfig; #endif } ADC_Init_TypeDef; /** Default configuration for ADC initialization structure. */ #if defined(_ADC_CTRL_LPFMODE_MASK) && (!defined(_ADC_CTRL_ADCCLKMODE_MASK)) #define ADC_INIT_DEFAULT \ { \ adcOvsRateSel2, /* 2x oversampling (if enabled). */ \ adcLPFilterBypass, /* No input filter selected. */ \ adcWarmupNormal, /* ADC shutdown after each conversion. */ \ _ADC_CTRL_TIMEBASE_DEFAULT, /* Use hardware default value. */ \ _ADC_CTRL_PRESC_DEFAULT, /* Use hardware default value. */ \ false /* Do not use tailgate. */ \ } #elif (!defined(_ADC_CTRL_LPFMODE_MASK)) && (!defined(_ADC_CTRL_ADCCLKMODE_MASK)) #define ADC_INIT_DEFAULT \ { \ adcOvsRateSel2, /* 2x oversampling (if enabled). */ \ adcWarmupNormal, /* ADC shutdown after each conversion. */ \ _ADC_CTRL_TIMEBASE_DEFAULT, /* Use hardware default value. */ \ _ADC_CTRL_PRESC_DEFAULT, /* Use hardware default value. */ \ false /* Do not use tailgate. */ \ } #elif (!defined(_ADC_CTRL_LPFMODE_MASK)) && defined(_ADC_CTRL_ADCCLKMODE_MASK) #define ADC_INIT_DEFAULT \ { \ adcOvsRateSel2, /* 2x oversampling (if enabled). */ \ adcWarmupNormal, /* ADC shutdown after each conversion. */ \ _ADC_CTRL_TIMEBASE_DEFAULT, /* Use hardware default value. */ \ _ADC_CTRL_PRESC_DEFAULT, /* Use hardware default value. */ \ false, /* Do not use tailgate. */ \ adcEm2Disabled /* ADC disabled in EM2. */ \ } #endif /** Scan input configuration. */ typedef struct { /** Input range select to be applied to ADC_SCANINPUTSEL. */ uint32_t scanInputSel; /** Input enable mask. */ uint32_t scanInputEn; /** Alternative negative input. */ uint32_t scanNegSel; } ADC_InitScanInput_TypeDef; /** Scan sequence initialization structure. */ typedef struct { /** * Peripheral reflex system trigger selection. Only applicable if @p prsEnable * is enabled. */ ADC_PRSSEL_TypeDef prsSel; /** Acquisition time (in ADC clock cycles). */ ADC_AcqTime_TypeDef acqTime; /** * Sample reference selection. Note that, for external references, the * ADC calibration register must be set explicitly. */ ADC_Ref_TypeDef reference; /** Sample resolution. */ ADC_Res_TypeDef resolution; #if defined(_ADC_SCANCTRL_INPUTMASK_MASK) /** * Scan input selection. If single ended (@p diff is false), use logical * combination of ADC_SCANCTRL_INPUTMASK_CHx defines. If differential input * (@p diff is true), use logical combination of ADC_SCANCTRL_INPUTMASK_CHxCHy * defines. (Notice underscore prefix for defines used.) */ uint32_t input; #endif #if defined(_ADC_SCANINPUTSEL_MASK) /** * Scan input configuration. @ref Use ADC_ScanInputClear(), @ref ADC_ScanSingleEndedInputAdd() * or @ref ADC_ScanDifferentialInputAdd() to update this structure. */ ADC_InitScanInput_TypeDef scanInputConfig; #endif /** Select if single-ended or differential input. */ bool diff; /** Peripheral reflex system trigger enable. */ bool prsEnable; /** Select if left adjustment should be done. */ bool leftAdjust; /** Select if continuous conversion until explicit stop. */ bool rep; /** When true, DMA is available in EM2 for scan conversion */ #if defined(_ADC_CTRL_SCANDMAWU_MASK) bool scanDmaEm2Wu; #endif #if defined(_ADC_SCANCTRLX_FIFOOFACT_MASK) /** When true, FIFO overwrites old data when full. If false, FIFO discards new data. The SINGLEOF IRQ is triggered in both cases. */ bool fifoOverwrite; #endif } ADC_InitScan_TypeDef; /** Default configuration for ADC scan initialization structure. */ #if defined(_ADC_SCANCTRL_INPUTMASK_MASK) #define ADC_INITSCAN_DEFAULT \ { \ adcPRSSELCh0, /* PRS ch0 (if enabled). */ \ adcAcqTime1, /* 1 ADC_CLK cycle acquisition time. */ \ adcRef1V25, /* 1.25 V internal reference. */ \ adcRes12Bit, /* 12 bit resolution. */ \ 0, /* No input selected. */ \ false, /* Single-ended input. */ \ false, /* PRS disabled. */ \ false, /* Right adjust. */ \ false, /* Deactivate conversion after one scan sequence. */ \ } #endif #if defined(_ADC_SCANINPUTSEL_MASK) #define ADC_INITSCAN_DEFAULT \ { \ adcPRSSELCh0, /* PRS ch0 (if enabled). */ \ adcAcqTime1, /* 1 ADC_CLK cycle acquisition time. */ \ adcRef1V25, /* 1.25 V internal reference. */ \ adcRes12Bit, /* 12 bit resolution. */ \ { \ /* Initialization should match values set by @ref ADC_ScanInputClear(). */ \ ADC_SCANINPUTSEL_NONE, /* Default ADC inputs. */ \ 0, /* Default input mask (all off). */ \ _ADC_SCANNEGSEL_RESETVALUE,/* Default negative select for positive terminal. */ \ }, \ false, /* Single-ended input. */ \ false, /* PRS disabled. */ \ false, /* Right adjust. */ \ false, /* Deactivate conversion after one scan sequence. */ \ false, /* No EM2 DMA wakeup from scan FIFO DVL. */ \ false /* Discard new data on full FIFO. */ \ } #endif /** Single conversion initialization structure. */ typedef struct { /** * Peripheral reflex system trigger selection. Only applicable if @p prsEnable * is enabled. */ ADC_PRSSEL_TypeDef prsSel; /** Acquisition time (in ADC clock cycles). */ ADC_AcqTime_TypeDef acqTime; /** * Sample reference selection. Note that, for external references, the * ADC calibration register must be set explicitly. */ ADC_Ref_TypeDef reference; /** Sample resolution. */ ADC_Res_TypeDef resolution; #if defined(_ADC_SINGLECTRL_INPUTSEL_MASK) /** * Sample input selection, use single-ended or differential input according * to setting of @p diff. */ ADC_SingleInput_TypeDef input; #endif #if defined(_ADC_SINGLECTRL_POSSEL_MASK) /** Select positive input for single channel conversion mode. */ ADC_PosSel_TypeDef posSel; #endif #if defined(_ADC_SINGLECTRL_NEGSEL_MASK) /** Select negative input for single channel conversion mode. Negative input is grounded for single-ended (non-differential) converison. */ ADC_NegSel_TypeDef negSel; #endif /** Select if single-ended or differential input. */ bool diff; /** Peripheral reflex system trigger enable. */ bool prsEnable; /** Select if left adjustment should be done. */ bool leftAdjust; /** Select if continuous conversion until explicit stop. */ bool rep; #if defined(_ADC_CTRL_SINGLEDMAWU_MASK) /** When true, DMA is available in EM2 for single conversion */ bool singleDmaEm2Wu; #endif #if defined(_ADC_SINGLECTRLX_FIFOOFACT_MASK) /** When true, FIFO overwrites old data when full. If false, FIFO discards new data. The SCANOF IRQ is triggered in both cases. */ bool fifoOverwrite; #endif } ADC_InitSingle_TypeDef; /** Default configuration for ADC single conversion initialization structure. */ #if defined(_ADC_SINGLECTRL_INPUTSEL_MASK) #define ADC_INITSINGLE_DEFAULT \ { \ adcPRSSELCh0, /* PRS ch0 (if enabled). */ \ adcAcqTime1, /* 1 ADC_CLK cycle acquisition time. */ \ adcRef1V25, /* 1.25 V internal reference. */ \ adcRes12Bit, /* 12 bit resolution. */ \ adcSingleInpCh0, /* CH0 input selected. */ \ false, /* Single-ended input. */ \ false, /* PRS disabled. */ \ false, /* Right adjust. */ \ false /* Deactivate conversion after one scan sequence. */ \ } #else #define ADC_INITSINGLE_DEFAULT \ { \ adcPRSSELCh0, /* PRS ch0 (if enabled). */ \ adcAcqTime1, /* 1 ADC_CLK cycle acquisition time. */ \ adcRef1V25, /* 1.25 V internal reference. */ \ adcRes12Bit, /* 12 bit resolution. */ \ adcPosSelAPORT0XCH0, /* Select node BUS0XCH0 as posSel */ \ adcNegSelVSS, /* Select VSS as negSel */ \ false, /* Single-ended input. */ \ false, /* PRS disabled. */ \ false, /* Right adjust. */ \ false, /* Deactivate conversion after one scan sequence. */ \ false, /* No EM2 DMA wakeup from single FIFO DVL */ \ false /* Discard new data on full FIFO. */ \ } #endif /******************************************************************************* ***************************** PROTOTYPES ********************************** ******************************************************************************/ /***************************************************************************//** * @brief * Get a single conversion result. * * @note * Check data valid flag before calling this function. * * @param[in] adc * A pointer to the ADC peripheral register block. * * @return * Single conversion data. ******************************************************************************/ __STATIC_INLINE uint32_t ADC_DataSingleGet(ADC_TypeDef *adc) { return adc->SINGLEDATA; } /***************************************************************************//** * @brief * Peek single conversion result. * * @note * Check data valid flag before calling this function. * * @param[in] adc * A pointer to the ADC peripheral register block. * * @return * Single conversion data. ******************************************************************************/ __STATIC_INLINE uint32_t ADC_DataSinglePeek(ADC_TypeDef *adc) { return adc->SINGLEDATAP; } /***************************************************************************//** * @brief * Get a scan result. * * @note * Check data valid flag before calling this function. * * @param[in] adc * A pointer to the ADC peripheral register block. * * @return * Scan conversion data. ******************************************************************************/ __STATIC_INLINE uint32_t ADC_DataScanGet(ADC_TypeDef *adc) { return adc->SCANDATA; } /***************************************************************************//** * @brief * Peek scan result. * * @note * Check data valid flag before calling this function. * * @param[in] adc * A pointer to the ADC peripheral register block. * * @return * Scan conversion data. ******************************************************************************/ __STATIC_INLINE uint32_t ADC_DataScanPeek(ADC_TypeDef *adc) { return adc->SCANDATAP; } #if defined(_ADC_SCANDATAX_MASK) uint32_t ADC_DataIdScanGet(ADC_TypeDef *adc, uint32_t *scanId); #endif void ADC_Init(ADC_TypeDef *adc, const ADC_Init_TypeDef *init); void ADC_Reset(ADC_TypeDef *adc); void ADC_InitScan(ADC_TypeDef *adc, const ADC_InitScan_TypeDef *init); #if defined(_ADC_SCANINPUTSEL_MASK) void ADC_ScanInputClear(ADC_InitScan_TypeDef *scanInit); uint32_t ADC_ScanSingleEndedInputAdd(ADC_InitScan_TypeDef *scanInit, ADC_ScanInputGroup_TypeDef inputGroup, ADC_PosSel_TypeDef singleEndedSel); uint32_t ADC_ScanDifferentialInputAdd(ADC_InitScan_TypeDef *scanInit, ADC_ScanInputGroup_TypeDef inputGroup, ADC_PosSel_TypeDef posSel, ADC_ScanNegInput_TypeDef negInput); #endif void ADC_InitSingle(ADC_TypeDef *adc, const ADC_InitSingle_TypeDef *init); uint8_t ADC_TimebaseCalc(uint32_t hfperFreq); uint8_t ADC_PrescaleCalc(uint32_t adcFreq, uint32_t hfperFreq); /***************************************************************************//** * @brief * Clear one or more pending ADC interrupts. * * @param[in] adc * A pointer to the ADC peripheral register block. * * @param[in] flags * Pending ADC interrupt source to clear. Use a bitwise logic OR combination * of valid interrupt flags for the ADC module (ADC_IF_nnn). ******************************************************************************/ __STATIC_INLINE void ADC_IntClear(ADC_TypeDef *adc, uint32_t flags) { adc->IFC = flags; } /***************************************************************************//** * @brief * Disable one or more ADC interrupts. * * @param[in] adc * A pointer to the ADC peripheral register block. * * @param[in] flags * ADC interrupt sources to disable. Use a bitwise logic OR combination of * valid interrupt flags for the ADC module (ADC_IF_nnn). ******************************************************************************/ __STATIC_INLINE void ADC_IntDisable(ADC_TypeDef *adc, uint32_t flags) { adc->IEN &= ~flags; } /***************************************************************************//** * @brief * Enable one or more ADC interrupts. * * @note * Depending on use, a pending interrupt may already be set prior to * enabling the interrupt. Consider using ADC_IntClear() prior to enabling * if the pending interrupt should be ignored. * * @param[in] adc * A pointer to the ADC peripheral register block. * * @param[in] flags * ADC interrupt sources to enable. Use a bitwise logic OR combination of * valid interrupt flags for the ADC module (ADC_IF_nnn). ******************************************************************************/ __STATIC_INLINE void ADC_IntEnable(ADC_TypeDef *adc, uint32_t flags) { adc->IEN |= flags; } /***************************************************************************//** * @brief * Get pending ADC interrupt flags. * * @note * This function does not clear event bits. * * @param[in] adc * A pointer to the ADC peripheral register block. * * @return * ADC interrupt sources pending. A bitwise logic OR combination of valid * interrupt flags for the ADC module (ADC_IF_nnn). ******************************************************************************/ __STATIC_INLINE uint32_t ADC_IntGet(ADC_TypeDef *adc) { return adc->IF; } /***************************************************************************//** * @brief * Get enabled and pending ADC interrupt flags. * Useful for handling more interrupt sources in the same interrupt handler. * * @param[in] adc * A pointer to the ADC peripheral register block. * * @note * This function does not clear interrupt flags. * * @return * Pending and enabled ADC interrupt sources. * The return value is the bitwise AND combination of * - the OR combination of enabled interrupt sources in ADCx_IEN_nnn * register (ADCx_IEN_nnn) and * - the OR combination of valid interrupt flags of the ADC module * (ADCx_IF_nnn). ******************************************************************************/ __STATIC_INLINE uint32_t ADC_IntGetEnabled(ADC_TypeDef *adc) { uint32_t ien; /* Store ADCx->IEN in a temporary variable to define the explicit order * of volatile accesses. */ ien = adc->IEN; /* Bitwise AND of pending and enabled interrupts */ return adc->IF & ien; } /***************************************************************************//** * @brief * Set one or more pending ADC interrupts from software. * * @param[in] adc * A pointer to the ADC peripheral register block. * * @param[in] flags * ADC interrupt sources to set to pending. Use a bitwise logic OR combination * of valid interrupt flags for the ADC module (ADC_IF_nnn). ******************************************************************************/ __STATIC_INLINE void ADC_IntSet(ADC_TypeDef *adc, uint32_t flags) { adc->IFS = flags; } /***************************************************************************//** * @brief * Start scan sequence and/or single conversion. * * @param[in] adc * A pointer to the ADC peripheral register block. * * @param[in] cmd * A command indicating which type of sampling to start. ******************************************************************************/ __STATIC_INLINE void ADC_Start(ADC_TypeDef *adc, ADC_Start_TypeDef cmd) { adc->CMD = (uint32_t)cmd; } /** @} (end addtogroup ADC) */ /** @} (end addtogroup emlib) */ #ifdef __cplusplus } #endif #endif /* defined(ADC_COUNT) && (ADC_COUNT > 0) */ #endif /* EM_ADC_H */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/emlib/inc/em_assert.h.
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/***************************************************************************//** * @file * @brief Emlib peripheral API "assert" implementation. * @version 5.7.0 ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * SPDX-License-Identifier: Zlib * * The licensor of this software is Silicon Laboratories Inc. * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be * appreciated but is not required. * 2. Altered source versions must be plainly marked as such, and must not be * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * ******************************************************************************/ #ifndef EM_ASSERT_H #define EM_ASSERT_H #ifdef __cplusplus extern "C" { #endif /***************************************************************************//** * @addtogroup emlib * @{ ******************************************************************************/ #if defined(DOXY_DOC_ONLY) /** @brief Included for documentation purposes only. This define is not present by default. * @ref DEBUG_EFM should be defined from the compiler to enable the default internal * assert handler. */ #define DEBUG_EFM /** @endcond */ #endif #if defined(DEBUG_EFM) || defined(DEBUG_EFM_USER) /***************************************************************************//** * @addtogroup ASSERT * @brief Error checking module. * @details * By default, EMLIB library assert usage is not included to reduce * footprint and processing overhead. Further, EMLIB assert usage is decoupled * from ISO C assert handling (NDEBUG usage) to allow using ISO C * assert without including EMLIB assert statements. * * Below are available defines for controlling EMLIB assert inclusion. The defines * are typically for a project to be used by the preprocessor. * * @li If @ref DEBUG_EFM is defined, the internal EMLIB library assert handling will * be used. This is implemented as a simple while(true) loop. @ref DEBUG_EFM is not * defined by default. * * @li If DEBUG_EFM_USER is defined, the user must provide custom * implementation of the assertEFM() function. * * @li If both @ref DEBUG_EFM and DEBUG_EFM_USER are undefined, all EFM_ASSERT() * statements are not operational. * * @note * The internal EMLIB assert is documented because @ref DEBUG_EFM is defined in * the doxygen configuration. * @{ ******************************************************************************/ /* Due to footprint considerations, we only pass file name and line number, */ /* not the assert expression (nor function name (C99)) */ void assertEFM(const char *file, int line); #define EFM_ASSERT(expr) ((expr) ? ((void)0) : assertEFM(__FILE__, __LINE__)) #else /** Default assertion is not operational */ #define EFM_ASSERT(expr) ((void)(expr)) #endif /* defined(DEBUG_EFM) || defined(DEBUG_EFM_USER) */ /** @} (end addtogroup ASSERT) */ /** @} (end addtogroup emlib) */ #ifdef __cplusplus } #endif #endif /* EM_ASSERT_H */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/emlib/inc/em_burtc.h.
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/***************************************************************************//** * @file * @brief Backup Real Time Counter (BURTC) peripheral API * @version 5.7.0 ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * SPDX-License-Identifier: Zlib * * The licensor of this software is Silicon Laboratories Inc. * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be * appreciated but is not required. * 2. Altered source versions must be plainly marked as such, and must not be * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * ******************************************************************************/ #ifndef EM_BURTC_H #define EM_BURTC_H #include "em_device.h" #if defined(BURTC_PRESENT) #include <stdbool.h> #include "em_assert.h" #include "em_bus.h" #ifdef __cplusplus extern "C" { #endif /***************************************************************************//** * @addtogroup emlib * @{ ******************************************************************************/ /***************************************************************************//** * @addtogroup BURTC * @{ ******************************************************************************/ /******************************************************************************* ******************************* DEFINES *********************************** ******************************************************************************/ /** BURTC clock divisors. These values are valid for the BURTC prescaler. */ #define burtcClkDiv_1 1 /**< Divide clock by 1. */ #define burtcClkDiv_2 2 /**< Divide clock by 2. */ #define burtcClkDiv_4 4 /**< Divide clock by 4. */ #define burtcClkDiv_8 8 /**< Divide clock by 8. */ #define burtcClkDiv_16 16 /**< Divide clock by 16. */ #define burtcClkDiv_32 32 /**< Divide clock by 32. */ #define burtcClkDiv_64 64 /**< Divide clock by 64. */ #define burtcClkDiv_128 128 /**< Divide clock by 128. */ /******************************************************************************* ******************************** ENUMS ************************************ ******************************************************************************/ #if defined(_SILICON_LABS_32B_SERIES_0) /** BURTC clock selection. */ typedef enum { /** Ultra low frequency (1 kHz) clock. */ burtcClkSelULFRCO = BURTC_CTRL_CLKSEL_ULFRCO, /** Low frequency RC oscillator. */ burtcClkSelLFRCO = BURTC_CTRL_CLKSEL_LFRCO, /** Low frequency crystal osciallator. */ burtcClkSelLFXO = BURTC_CTRL_CLKSEL_LFXO } BURTC_ClkSel_TypeDef; /** BURTC mode of operation. */ typedef enum { /** Disable BURTC */ burtcModeDisable = BURTC_CTRL_MODE_DISABLE, /** Enable and start BURTC counter in EM0 to EM2. */ burtcModeEM2 = BURTC_CTRL_MODE_EM2EN, /** Enable and start BURTC counter in EM0 to EM3. */ burtcModeEM3 = BURTC_CTRL_MODE_EM3EN, /** Enable and start BURTC counter in EM0 to EM4. */ burtcModeEM4 = BURTC_CTRL_MODE_EM4EN, } BURTC_Mode_TypeDef; /** BURTC low power mode. */ typedef enum { /** Low Power Mode is disabled. */ burtcLPDisable = BURTC_LPMODE_LPMODE_DISABLE, /** Low Power Mode is always enabled. */ burtcLPEnable = BURTC_LPMODE_LPMODE_ENABLE, /** Low Power Mode when system enters backup mode. */ burtcLPBU = BURTC_LPMODE_LPMODE_BUEN } BURTC_LP_TypeDef; #endif /******************************************************************************* ******************************* STRUCTS *********************************** ******************************************************************************/ #if defined(_SILICON_LABS_32B_SERIES_0) /** BURTC initialization structure for Series 0 devices. */ typedef struct { bool enable; /**< Enable BURTC after initialization (starts counter). */ BURTC_Mode_TypeDef mode; /**< Configure energy mode operation. */ bool debugRun; /**< If true, counter will keep running under debug halt. */ BURTC_ClkSel_TypeDef clkSel; /**< Select clock source. */ uint32_t clkDiv; /**< Clock divider; for ULFRCO 1Khz or 2kHz operation. */ uint32_t lowPowerComp; /**< Number of least significantt clock bits to ignore in low power mode. */ bool timeStamp; /**< Enable time stamp on entering backup power domain. */ bool compare0Top; /**< Set if Compare Value 0 is also top value (counter restart). */ BURTC_LP_TypeDef lowPowerMode; /**< Low power operation mode, requires LFXO or LFRCO. */ } BURTC_Init_TypeDef; /** Default configuration for BURTC initialization structure. */ #define BURTC_INIT_DEFAULT \ { \ true, \ burtcModeEM2, \ false, \ burtcClkSelULFRCO, \ burtcClkDiv_1, \ 0, \ true, \ false, \ burtcLPDisable, \ } #elif defined(_SILICON_LABS_32B_SERIES_2) /** BURTC initialization structure for Series 2 devices. */ typedef struct { bool start; /**< Start BURTC after initialization */ bool debugRun; /**< If true, counter will keep running under debug halt */ uint32_t clkDiv; /**< Clock divider. Supported range is 1-32768 */ bool compare0Top; /**< Set if Compare Value 0 is also top value (counter restart) */ bool em4comp; /**< Enable EM4 wakeup on compare match. */ bool em4overflow; /**< Enable EM4 wakeup on counter overflow. */ } BURTC_Init_TypeDef; /** Default configuration for BURTC init structure */ #define BURTC_INIT_DEFAULT \ { \ true, \ false, \ 1, \ 0, \ false, \ false, \ } #endif /******************************************************************************* ***************************** PROTOTYPES ********************************** ******************************************************************************/ /***************************************************************************//** * @brief * Clear one or more pending BURTC interrupts. * * @param[in] flags * BURTC interrupt sources to clear. Use a set of interrupt flags OR-ed * together to clear multiple interrupt sources for the BURTC module * (BURTC_IFS_nnn). ******************************************************************************/ __STATIC_INLINE void BURTC_IntClear(uint32_t flags) { #if defined(BURTC_HAS_SET_CLEAR) BURTC->IF_CLR = flags; #else BURTC->IFC = flags; #endif } /***************************************************************************//** * @brief * Disable one or more BURTC interrupts. * * @param[in] flags * BURTC interrupt sources to disable. Use a set of interrupt flags OR-ed * together to disable multiple interrupt sources for the BURTC module * (BURTC_IFS_nnn). ******************************************************************************/ __STATIC_INLINE void BURTC_IntDisable(uint32_t flags) { #if defined(BURTC_HAS_SET_CLEAR) BURTC->IEN_CLR = flags; #else BURTC->IEN &= ~(flags); #endif } /***************************************************************************//** * @brief * Enable one or more BURTC interrupts. * * @note * Depending on use, a pending interrupt may already be set prior to * enabling the interrupt. Consider using BURTC_IntClear() prior to enabling * if a pending interrupt should be ignored. * * @param[in] flags * BURTC interrupt sources to enable. Use a set of interrupt flags OR-ed * together to set multiple interrupt sources for the BURTC module * (BURTC_IFS_nnn). ******************************************************************************/ __STATIC_INLINE void BURTC_IntEnable(uint32_t flags) { #if defined(BURTC_HAS_SET_CLEAR) BURTC->IEN_SET = flags; #else BURTC->IEN |= flags; #endif } /***************************************************************************//** * @brief * Get pending BURTC interrupt flags. * * @note * This function does not clear the event bits. * * @return * Pending BURTC interrupt sources. Returns a set of interrupt flags OR-ed * together for multiple interrupt sources in the BURTC module (BURTC_IFS_nnn). ******************************************************************************/ __STATIC_INLINE uint32_t BURTC_IntGet(void) { return BURTC->IF; } /***************************************************************************//** * @brief * Get enabled and pending BURTC interrupt flags. * * @note * The event bits are not cleared by the use of this function. * * @return * Pending BURTC interrupt sources that is also enabled. Returns a set of * interrupt flags OR-ed together for multiple interrupt sources in the * BURTC module (BURTC_IFS_nnn). ******************************************************************************/ __STATIC_INLINE uint32_t BURTC_IntGetEnabled(void) { uint32_t tmp; /* Get enabled interrupts */ tmp = BURTC->IEN; /* Return set interrupts */ return BURTC->IF & tmp; } /***************************************************************************//** * @brief * Set one or more pending BURTC interrupts from SW. * * @param[in] flags * BURTC interrupt sources to set to pending. Use a set of interrupt flags * OR-ed together to set multiple interrupt sources for the BURTC module * (BURTC_IFS_nnn). ******************************************************************************/ __STATIC_INLINE void BURTC_IntSet(uint32_t flags) { #if defined(BURTC_HAS_SET_CLEAR) BURTC->IF_SET = flags; #else BURTC->IFS = flags; #endif } /***************************************************************************//** * @brief * Status of BURTC RAM, timestamp and LP Mode * * @return A mask logially OR-ed status bits ******************************************************************************/ __STATIC_INLINE uint32_t BURTC_Status(void) { return BURTC->STATUS; } #if defined(BURTC_CMD_CLRSTATUS) /***************************************************************************//** * @brief * Clear and reset BURTC status register ******************************************************************************/ __STATIC_INLINE void BURTC_StatusClear(void) { BURTC->CMD = BURTC_CMD_CLRSTATUS; } #endif /***************************************************************************//** * @brief * Wait for the BURTC to complete all synchronization of register changes * and commands. ******************************************************************************/ __STATIC_INLINE void BURTC_SyncWait(void) { #if defined(_SILICON_LABS_32B_SERIES_2) while ((BURTC->EN != 0U) && (BURTC->SYNCBUSY != 0U)) { /* Wait for previous synchronization to finish */ } #else while (BURTC->SYNCBUSY != 0U) { /* Wait for previous synchronization to finish */ } #endif } #if defined(_SILICON_LABS_32B_SERIES_2) /***************************************************************************//** * @brief * Start BURTC counter. * * @detail * This function will send a start command to the BURTC peripheral. The BURTC * peripheral will use some LF clock ticks before the command is executed. * The @ref BURTC_SyncWait() function can be used to wait for the start command * to be executed. * * @note * This function requires the BURTC to be enabled. ******************************************************************************/ __STATIC_INLINE void BURTC_Start(void) { BURTC_SyncWait(); BURTC->CMD = BURTC_CMD_START; } /***************************************************************************//** * @brief * Stop the BURTC counter. * * @detail * This function will send a stop command to the BURTC peripheral. The BURTC * peripheral will use some LF clock ticks before the command is executed. * The @ref BURTC_SyncWait() function can be used to wait for the stop command * to be executed. * * @note * This function requires the BURTC to be enabled. ******************************************************************************/ __STATIC_INLINE void BURTC_Stop(void) { BURTC_SyncWait(); BURTC->CMD = BURTC_CMD_STOP; } #endif /***************************************************************************//** * @brief Get BURTC counter * * @return * BURTC counter value ******************************************************************************/ __STATIC_INLINE uint32_t BURTC_CounterGet(void) { return BURTC->CNT; } #if defined(_SILICON_LABS_32B_SERIES_0) /***************************************************************************//** * @brief Get BURTC timestamp for entering BU * * @return * BURTC Time Stamp value ******************************************************************************/ __STATIC_INLINE uint32_t BURTC_TimestampGet(void) { return BURTC->TIMESTAMP; } /***************************************************************************//** * @brief Freeze register updates until enabled * @param[in] enable If true, registers are not updated until enabled again. ******************************************************************************/ __STATIC_INLINE void BURTC_FreezeEnable(bool enable) { BUS_RegBitWrite(&BURTC->FREEZE, _BURTC_FREEZE_REGFREEZE_SHIFT, enable); } /***************************************************************************//** * @brief Shut down power to rentention register bank. * @param[in] enable * If true, shuts off power to retention registers. * @note * When power rentention is disabled, it cannot be enabled again (until * reset). ******************************************************************************/ __STATIC_INLINE void BURTC_Powerdown(bool enable) { BUS_RegBitWrite(&BURTC->POWERDOWN, _BURTC_POWERDOWN_RAM_SHIFT, enable); } /***************************************************************************//** * @brief * Set a value in one of the retention registers * * @param[in] num * Register to set * @param[in] data * Value to put into register ******************************************************************************/ __STATIC_INLINE void BURTC_RetRegSet(uint32_t num, uint32_t data) { EFM_ASSERT(num <= 127); BURTC->RET[num].REG = data; } /***************************************************************************//** * @brief * Read a value from one of the retention registers * * @param[in] num * Retention Register to read ******************************************************************************/ __STATIC_INLINE uint32_t BURTC_RetRegGet(uint32_t num) { EFM_ASSERT(num <= 127); return BURTC->RET[num].REG; } #endif /***************************************************************************//** * @brief * Lock BURTC registers, will protect from writing new config settings ******************************************************************************/ __STATIC_INLINE void BURTC_Lock(void) { BURTC->LOCK = 0x0; } /***************************************************************************//** * @brief * Unlock BURTC registers, enable write access to change configuration ******************************************************************************/ __STATIC_INLINE void BURTC_Unlock(void) { BURTC->LOCK = BURTC_LOCK_LOCKKEY_UNLOCK; } void BURTC_Reset(void); void BURTC_Init(const BURTC_Init_TypeDef *burtcInit); void BURTC_Enable(bool enable); void BURTC_CounterReset(void); void BURTC_CompareSet(unsigned int comp, uint32_t value); uint32_t BURTC_CompareGet(unsigned int comp); uint32_t BURTC_ClockFreqGet(void); /** @} (end addtogroup BURTC) */ /** @} (end addtogroup emlib) */ #ifdef __cplusplus } #endif #endif /* BURTC_PRESENT */ #endif /* EM_BURTC_H */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/emlib/inc/em_bus.h.
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/***************************************************************************//** * @file * @brief RAM and peripheral bit-field set and clear API * @version 5.7.0 ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * SPDX-License-Identifier: Zlib * * The licensor of this software is Silicon Laboratories Inc. * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be * appreciated but is not required. * 2. Altered source versions must be plainly marked as such, and must not be * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * ******************************************************************************/ #ifndef EM_BUS_H #define EM_BUS_H #include "em_device.h" #ifdef __cplusplus extern "C" { #endif /***************************************************************************//** * @addtogroup emlib * @{ ******************************************************************************/ /***************************************************************************//** * @addtogroup BUS * @brief BUS register and RAM bit/field read/write API * @details * API to perform bit-band and field set/clear access to RAM and peripherals. * @{ ******************************************************************************/ /***************************************************************************//** * @brief * Perform a single-bit write operation on a 32-bit word in RAM. * * @details * This function uses Cortex-M bit-banding hardware to perform an atomic * read-modify-write operation on a single bit write on a 32-bit word in RAM. * See the reference manual for more details about bit-banding. * * @note * This function is atomic on Cortex-M cores with bit-banding support. Bit- * banding is a multicycle read-modify-write bus operation. RAM bit-banding is * performed using the memory alias region at BITBAND_RAM_BASE. * * @param[in] addr An ddress of a 32-bit word in RAM. * * @param[in] bit A bit position to write, 0-31. * * @param[in] val A value to set bit to, 0 or 1. ******************************************************************************/ __STATIC_INLINE void BUS_RamBitWrite(volatile uint32_t *addr, unsigned int bit, unsigned int val) { #if defined(BITBAND_RAM_BASE) uint32_t aliasAddr = BITBAND_RAM_BASE + (((uint32_t)addr - SRAM_BASE) * (uint32_t) 32) + (bit * (uint32_t) 4); *(volatile uint32_t *)aliasAddr = (uint32_t)val; #else uint32_t tmp = *addr; /* Make sure val is not more than 1 because only one bit needs to be set. */ *addr = (tmp & ~(1 << bit)) | ((val & 1) << bit); #endif } /***************************************************************************//** * @brief * Perform a single-bit read operation on a 32-bit word in RAM. * * @details * This function uses Cortex-M bit-banding hardware to perform an atomic * read operation on a single register bit. See the * reference manual for more details about bit-banding. * * @note * This function is atomic on Cortex-M cores with bit-banding support. * RAM bit-banding is performed using the memory alias region * at BITBAND_RAM_BASE. * * @param[in] addr RAM address. * * @param[in] bit A bit position to read, 0-31. * * @return * The requested bit shifted to bit position 0 in the return value. ******************************************************************************/ __STATIC_INLINE unsigned int BUS_RamBitRead(volatile const uint32_t *addr, unsigned int bit) { #if defined(BITBAND_RAM_BASE) uint32_t aliasAddr = BITBAND_RAM_BASE + (((uint32_t)addr - SRAM_BASE) * (uint32_t) 32) + (bit * (uint32_t) 4); return *(volatile uint32_t *)aliasAddr; #else return ((*addr) >> bit) & 1; #endif } /***************************************************************************//** * @brief * Perform a single-bit write operation on a peripheral register. * * @details * This function uses Cortex-M bit-banding hardware to perform an atomic * read-modify-write operation on a single register bit. See the * reference manual for more details about bit-banding. * * @note * This function is atomic on Cortex-M cores with bit-banding support. Bit- * banding is a multicycle read-modify-write bus operation. Peripheral register * bit-banding is performed using the memory alias region at BITBAND_PER_BASE. * * @param[in] addr A peripheral register address. * * @param[in] bit A bit position to write, 0-31. * * @param[in] val A value to set bit to, 0 or 1. ******************************************************************************/ __STATIC_INLINE void BUS_RegBitWrite(volatile uint32_t *addr, unsigned int bit, unsigned int val) { #if defined(PER_REG_BLOCK_SET_OFFSET) && defined(PER_REG_BLOCK_CLR_OFFSET) uint32_t aliasAddr; if (val) { aliasAddr = (uint32_t)addr + PER_REG_BLOCK_SET_OFFSET; } else { aliasAddr = (uint32_t)addr + PER_REG_BLOCK_CLR_OFFSET; } *(volatile uint32_t *)aliasAddr = 1 << bit; #elif defined(BITBAND_PER_BASE) uint32_t aliasAddr = BITBAND_PER_BASE + (((uint32_t)addr - PER_MEM_BASE) * (uint32_t) 32) + (bit * (uint32_t) 4); *(volatile uint32_t *)aliasAddr = (uint32_t)val; #else uint32_t tmp = *addr; /* Make sure val is not more than 1 because only one bit needs to be set. */ *addr = (tmp & ~(1 << bit)) | ((val & 1) << bit); #endif } /***************************************************************************//** * @brief * Perform a single-bit read operation on a peripheral register. * * @details * This function uses Cortex-M bit-banding hardware to perform an atomic * read operation on a single register bit. See the * reference manual for more details about bit-banding. * * @note * This function is atomic on Cortex-M cores with bit-banding support. * Peripheral register bit-banding is performed using the memory alias * region at BITBAND_PER_BASE. * * @param[in] addr A peripheral register address. * * @param[in] bit A bit position to read, 0-31. * * @return * The requested bit shifted to bit position 0 in the return value. ******************************************************************************/ __STATIC_INLINE unsigned int BUS_RegBitRead(volatile const uint32_t *addr, unsigned int bit) { #if defined(BITBAND_PER_BASE) uint32_t aliasAddr = BITBAND_PER_BASE + (((uint32_t)addr - PER_MEM_BASE) * (uint32_t)32) + (bit * (uint32_t) 4); return *(volatile uint32_t *)aliasAddr; #else return ((*addr) >> bit) & 1; #endif } /***************************************************************************//** * @brief * Perform a masked set operation on a peripheral register address. * * @details * A peripheral register masked set provides a single-cycle and atomic set * operation of a bit-mask in a peripheral register. All 1s in the mask are * set to 1 in the register. All 0s in the mask are not changed in the * register. * RAMs and special peripherals are not supported. See the * reference manual for more details about the peripheral register field set. * * @note * This function is single-cycle and atomic on cores with peripheral bit set * and clear support. It uses the memory alias region at PER_BITSET_MEM_BASE. * * @param[in] addr A peripheral register address. * * @param[in] mask A mask to set. ******************************************************************************/ __STATIC_INLINE void BUS_RegMaskedSet(volatile uint32_t *addr, uint32_t mask) { #if defined(PER_REG_BLOCK_SET_OFFSET) uint32_t aliasAddr = (uint32_t)addr + PER_REG_BLOCK_SET_OFFSET; *(volatile uint32_t *)aliasAddr = mask; #elif defined(PER_BITSET_MEM_BASE) uint32_t aliasAddr = PER_BITSET_MEM_BASE + ((uint32_t)addr - PER_MEM_BASE); *(volatile uint32_t *)aliasAddr = mask; #else *addr |= mask; #endif } /***************************************************************************//** * @brief * Perform a masked clear operation on the peripheral register address. * * @details * A peripheral register masked clear provides a single-cycle and atomic clear * operation of a bit-mask in a peripheral register. All 1s in the mask are * set to 0 in the register. * All 0s in the mask are not changed in the register. * RAMs and special peripherals are not supported. See the * reference manual for more details about the peripheral register field clear. * * @note * This function is single-cycle and atomic on cores with peripheral bit set * and clear support. It uses the memory alias region at PER_BITCLR_MEM_BASE. * * @param[in] addr A peripheral register address. * * @param[in] mask A mask to clear. ******************************************************************************/ __STATIC_INLINE void BUS_RegMaskedClear(volatile uint32_t *addr, uint32_t mask) { #if defined(PER_REG_BLOCK_CLR_OFFSET) uint32_t aliasAddr = (uint32_t)addr + PER_REG_BLOCK_CLR_OFFSET; *(volatile uint32_t *)aliasAddr = mask; #elif defined(PER_BITCLR_MEM_BASE) uint32_t aliasAddr = PER_BITCLR_MEM_BASE + ((uint32_t)addr - PER_MEM_BASE); *(volatile uint32_t *)aliasAddr = mask; #else *addr &= ~mask; #endif } /***************************************************************************//** * @brief * Perform peripheral register masked clear and value write. * * @details * This function first clears the mask in the peripheral register, then * writes the value. Typically, the mask is a bit-field in the register and * the value val is within the mask. * * @note * This operation is not atomic. Note that the mask is first set to 0 before * the val is set. * * @param[in] addr A peripheral register address. * * @param[in] mask A peripheral register mask. * * @param[in] val A peripheral register value. The value must be shifted to the correct bit position in the register corresponding to the field defined by the mask parameter. The register value must be contained in the field defined by the mask parameter. This function is not performing masking of val internally. ******************************************************************************/ __STATIC_INLINE void BUS_RegMaskedWrite(volatile uint32_t *addr, uint32_t mask, uint32_t val) { #if defined(PER_BITCLR_MEM_BASE) || defined(PER_REG_BLOCK_SET_OFFSET) BUS_RegMaskedClear(addr, mask); BUS_RegMaskedSet(addr, val); #else *addr = (*addr & ~mask) | val; #endif } /***************************************************************************//** * @brief * Perform a peripheral register masked read. * * @details * Read an unshifted and masked value from a peripheral register. * * @note * This operation is not hardware accelerated. * * @param[in] addr A peripheral register address. * * @param[in] mask A peripheral register mask. * * @return * An unshifted and masked register value. ******************************************************************************/ __STATIC_INLINE uint32_t BUS_RegMaskedRead(volatile const uint32_t *addr, uint32_t mask) { return *addr & mask; } /** @} (end addtogroup BUS) */ /** @} (end addtogroup emlib) */ #ifdef __cplusplus } #endif #endif /* EM_BUS_H */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/emlib/inc/em_chip.h.
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/***************************************************************************//** * @file * @brief Chip Initialization API * @version 5.7.0 ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * SPDX-License-Identifier: Zlib * * The licensor of this software is Silicon Laboratories Inc. * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be * appreciated but is not required. * 2. Altered source versions must be plainly marked as such, and must not be * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * ******************************************************************************/ #ifndef EM_CHIP_H #define EM_CHIP_H #include "em_device.h" #include "em_system.h" #include "em_gpio.h" #include "em_bus.h" #ifdef __cplusplus extern "C" { #endif /***************************************************************************//** * @addtogroup emlib * @{ ******************************************************************************/ /***************************************************************************//** * @addtogroup CHIP * @brief Chip errata workarounds initialization API * @details * API to initialize chip for errata workarounds. * @{ ******************************************************************************/ /**************************************************************************//** * @brief * Chip initialization routine for revision errata workarounds. * * @note * This function must be called immediately in main(). * * This initialization function configures the device to a state * as similar to later revisions as possible to improve software compatibility * with newer parts. See the device-specific errata for details. *****************************************************************************/ __STATIC_INLINE void CHIP_Init(void) { #if defined(MSC_CACHECMD_INVCACHE) MSC->CACHECMD = MSC_CACHECMD_INVCACHE; #elif defined(MSC_CMD_INVCACHE) MSC->CMD = MSC_CMD_INVCACHE; #endif #if defined(_SILICON_LABS_32B_SERIES_0) && defined(_EFM32_GECKO_FAMILY) uint32_t rev; SYSTEM_ChipRevision_TypeDef chipRev; volatile uint32_t *reg; rev = *(volatile uint32_t *)(0x0FE081FC); /* Engineering Sample calibration setup. */ if ((rev >> 24) == 0) { reg = (volatile uint32_t *)0x400CA00C; *reg &= ~(0x70UL); /* DREG */ reg = (volatile uint32_t *)0x400C6020; *reg &= ~(0xE0000000UL); *reg |= ~(7UL << 25); } if ((rev >> 24) <= 3) { /* DREG */ reg = (volatile uint32_t *)0x400C6020; *reg &= ~(0x00001F80UL); /* Update CMU reset values. */ reg = (volatile uint32_t *)0x400C8040; *reg = 0; reg = (volatile uint32_t *)0x400C8044; *reg = 0; reg = (volatile uint32_t *)0x400C8058; *reg = 0; reg = (volatile uint32_t *)0x400C8060; *reg = 0; reg = (volatile uint32_t *)0x400C8078; *reg = 0; } SYSTEM_ChipRevisionGet(&chipRev); if (chipRev.major == 0x01) { /* Rev A errata handling for EM2/3. Must enable DMA clock to get EM2/3 */ /* to work. This will be fixed in later chip revisions and is only needed for rev A. */ if (chipRev.minor == 00) { reg = (volatile uint32_t *)0x400C8040; *reg |= 0x2; } /* Rev A+B errata handling for I2C when using EM2/3. USART0 clock must be enabled */ /* after waking up from EM2/EM3 to get I2C to work. This will be fixed in */ /* later chip revisions and is only needed for rev A+B. */ if (chipRev.minor <= 0x01) { reg = (volatile uint32_t *)0x400C8044; *reg |= 0x1; } } /* Ensure correct ADC/DAC calibration value. */ rev = *(volatile uint32_t *)0x0FE081F0; if (rev < 0x4C8ABA00) { uint32_t cal; /* Enable ADC/DAC clocks. */ reg = (volatile uint32_t *)0x400C8044UL; *reg |= (1 << 14 | 1 << 11); /* Retrive calibration values. */ cal = ((*(volatile uint32_t *)(0x0FE081B4UL) & 0x00007F00UL) >> 8) << 24; cal |= ((*(volatile uint32_t *)(0x0FE081B4UL) & 0x0000007FUL) >> 0) << 16; cal |= ((*(volatile uint32_t *)(0x0FE081B4UL) & 0x00007F00UL) >> 8) << 8; cal |= ((*(volatile uint32_t *)(0x0FE081B4UL) & 0x0000007FUL) >> 0) << 0; /* ADC0->CAL = 1.25 reference. */ reg = (volatile uint32_t *)0x40002034UL; *reg = cal; /* DAC0->CAL = 1.25 reference. */ reg = (volatile uint32_t *)(0x4000402CUL); cal = *(volatile uint32_t *)0x0FE081C8UL; *reg = cal; /* Turn off ADC/DAC clocks. */ reg = (volatile uint32_t *)0x400C8044UL; *reg &= ~(1 << 14 | 1 << 11); } #endif #if defined(_SILICON_LABS_32B_SERIES_0) && defined(_EFM32_GIANT_FAMILY) /****************************/ /* Fix for errata CMU_E113. */ uint8_t prodRev; SYSTEM_ChipRevision_TypeDef chipRev; prodRev = SYSTEM_GetProdRev(); SYSTEM_ChipRevisionGet(&chipRev); if ((prodRev >= 16) && (chipRev.minor >= 3)) { /* This fixes an issue with the LFXO on high temperatures. */ *(volatile uint32_t*)0x400C80C0 = (*(volatile uint32_t*)0x400C80C0 & ~(1 << 6) ) | (1 << 4); } #endif #if defined(_SILICON_LABS_32B_SERIES_0) && defined(_EFM32_HAPPY_FAMILY) uint8_t prodRev; prodRev = SYSTEM_GetProdRev(); if (prodRev <= 129) { /* This fixes a mistaken internal connection between PC0 and PC4. */ /* This disables an internal pulldown on PC4. */ *(volatile uint32_t*)(0x400C6018) = (1 << 26) | (5 << 0); /* This disables an internal LDO test signal driving PC4. */ *(volatile uint32_t*)(0x400C80E4) &= ~(1 << 24); } #endif #if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) /**************************** * Fixes for errata GPIO_E201 (slewrate) and * HFXO high-temperature oscillator startup robustness fix. */ uint32_t port; uint32_t clkEn; uint8_t prodRev; const uint32_t setVal = (0x5 << _GPIO_P_CTRL_SLEWRATEALT_SHIFT) | (0x5 << _GPIO_P_CTRL_SLEWRATE_SHIFT); const uint32_t resetVal = _GPIO_P_CTRL_RESETVALUE & ~(_GPIO_P_CTRL_SLEWRATE_MASK | _GPIO_P_CTRL_SLEWRATEALT_MASK); prodRev = SYSTEM_GetProdRev(); SYSTEM_ChipRevision_TypeDef chipRev; SYSTEM_ChipRevisionGet(&chipRev); /* This errata is fixed in hardware from PRODREV 0x8F. */ if (prodRev < 0x8F) { /* Fixes for errata GPIO_E201 (slewrate). */ /* Save HFBUSCLK enable state and enable GPIO clock. */ clkEn = CMU->HFBUSCLKEN0; CMU->HFBUSCLKEN0 = clkEn | CMU_HFBUSCLKEN0_GPIO; /* Update slewrate. */ for (port = 0; port <= GPIO_PORT_MAX; port++) { GPIO->P[port].CTRL = setVal | resetVal; } /* Restore HFBUSCLK enable state. */ CMU->HFBUSCLKEN0 = clkEn; } /* This errata is fixed in hardware from PRODREV 0x90. */ if (prodRev < 0x90) { /* HFXO high-temperature oscillator startup robustness fix. */ CMU->HFXOSTARTUPCTRL = (CMU->HFXOSTARTUPCTRL & ~_CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_MASK) | (0x20 << _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_SHIFT); } if (chipRev.major == 0x01) { /* Fix for errata EMU_E210 - Potential Power-Down When Entering EM2 */ *(volatile uint32_t *)(EMU_BASE + 0x164) |= 0x4; } #if defined(_EFR_DEVICE) /**************************** * Fix for errata DCDC_E206. * Disable bypass limit enabled temporarily in SystemInit() errata * workaround. */ BUS_RegBitWrite(&EMU->DCDCCLIMCTRL, _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT, 0); #endif #endif #if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_84) uint8_t prodRev = SYSTEM_GetProdRev(); /* EM2 current fixes for early samples. */ if (prodRev == 0U) { *(volatile uint32_t *)(EMU_BASE + 0x190UL) = 0x0000ADE8UL; *(volatile uint32_t *)(EMU_BASE + 0x198UL) |= (0x1UL << 2); *(volatile uint32_t *)(EMU_BASE + 0x190UL) = 0x0; } if (prodRev < 2U) { *(volatile uint32_t *)(EMU_BASE + 0x164UL) |= (0x1UL << 13); } /* Set optimal LFRCOCTRL VREFUPDATE and enable duty cycling of VREF. */ CMU->LFRCOCTRL = (CMU->LFRCOCTRL & ~_CMU_LFRCOCTRL_VREFUPDATE_MASK) | CMU_LFRCOCTRL_VREFUPDATE_64CYCLES | CMU_LFRCOCTRL_ENVREF; #endif #if defined(_SILICON_LABS_32B_SERIES_1) \ && defined(_EFR_DEVICE) && (_SILICON_LABS_GECKO_INTERNAL_SDID >= 84) MSC->CTRL |= 0x1UL << 8; #endif /* Charge redist setup (fixed value): LCD->DBGCTRL.CHGRDSTSTR = 1 (reset: 0). */ #if defined(_LCD_DISPCTRL_CHGRDST_MASK) CMU->HFBUSCLKEN0 |= CMU_HFBUSCLKEN0_LE; CMU->LFACLKEN0 |= CMU_LFACLKEN0_LCD; *(volatile uint32_t *)(LCD_BASE + 0x034) |= (0x1UL << 12); CMU->LFACLKEN0 &= ~CMU_LFACLKEN0_LCD; CMU->HFBUSCLKEN0 &= ~CMU_HFBUSCLKEN0_LE; #endif #if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_200) SYSTEM_ChipRevision_TypeDef chipRev; SYSTEM_ChipRevisionGet(&chipRev); if ((HFXO0->STATUS & HFXO_STATUS_ENS) == 0U) { /* Change HFXO default peak detector settings. */ *(volatile uint32_t*)(HFXO0_BASE + 0x34U) = (*(volatile uint32_t*)(HFXO0_BASE + 0x34U) & 0xFF8000FFU) | 0x00178500U; /* Change HFXO low power control settings. */ *(volatile uint32_t*)(HFXO0_BASE + 0x30U) = (*(volatile uint32_t*)(HFXO0_BASE + 0x30U) & 0xFFFF0FFFU) | 0x0000C000U; /* Change default SQBUF bias current. */ *(volatile uint32_t*)(HFXO0_BASE + 0x30U) |= 0x700; } if (chipRev.major == 0x01 && chipRev.minor == 0x0) { /* Trigger RAM read for each RAM instance */ uint32_t value; volatile uint32_t *dmem = (volatile uint32_t *) DMEM_RAM0_RAM_MEM_BASE; for (uint32_t i = 0U; i < DMEM_NUM_BANK; i++) { value = *dmem; dmem += (DMEM_BANK0_SIZE / 4U); (void) value; } } #endif } /** @} (end addtogroup CHIP) */ /** @} (end addtogroup emlib) */ #ifdef __cplusplus } #endif #endif /* EM_CHIP_H */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/emlib/inc/em_cmu.h.
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/***************************************************************************//** * @file * @brief Clock management unit (CMU) API * @version 5.7.0 ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * SPDX-License-Identifier: Zlib * * The licensor of this software is Silicon Laboratories Inc. * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be * appreciated but is not required. * 2. Altered source versions must be plainly marked as such, and must not be * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * ******************************************************************************/ #ifndef EM_CMU_H #define EM_CMU_H #include "em_device.h" #if defined(CMU_PRESENT) #include <stdbool.h> #include "em_assert.h" #include "em_bus.h" #include "em_gpio.h" #ifdef __cplusplus extern "C" { #endif /***************************************************************************//** * @addtogroup emlib * @{ ******************************************************************************/ /***************************************************************************//** * @addtogroup CMU * @{ ******************************************************************************/ #if defined(_SILICON_LABS_32B_SERIES_2) /******************************************************************************* ******************************** ENUMS ************************************ ******************************************************************************/ /** Clock divider configuration */ typedef uint32_t CMU_ClkDiv_TypeDef; /** HFRCODPLL frequency bands */ typedef enum { cmuHFRCODPLLFreq_1M0Hz = 1000000U, /**< 1MHz RC band. */ cmuHFRCODPLLFreq_2M0Hz = 2000000U, /**< 2MHz RC band. */ cmuHFRCODPLLFreq_4M0Hz = 4000000U, /**< 4MHz RC band. */ cmuHFRCODPLLFreq_7M0Hz = 7000000U, /**< 7MHz RC band. */ cmuHFRCODPLLFreq_13M0Hz = 13000000U, /**< 13MHz RC band. */ cmuHFRCODPLLFreq_16M0Hz = 16000000U, /**< 16MHz RC band. */ cmuHFRCODPLLFreq_19M0Hz = 19000000U, /**< 19MHz RC band. */ cmuHFRCODPLLFreq_26M0Hz = 26000000U, /**< 26MHz RC band. */ cmuHFRCODPLLFreq_32M0Hz = 32000000U, /**< 32MHz RC band. */ cmuHFRCODPLLFreq_38M0Hz = 38000000U, /**< 38MHz RC band. */ cmuHFRCODPLLFreq_48M0Hz = 48000000U, /**< 48MHz RC band. */ cmuHFRCODPLLFreq_56M0Hz = 56000000U, /**< 56MHz RC band. */ cmuHFRCODPLLFreq_64M0Hz = 64000000U, /**< 64MHz RC band. */ cmuHFRCODPLLFreq_80M0Hz = 80000000U, /**< 80MHz RC band. */ cmuHFRCODPLLFreq_UserDefined = 0, } CMU_HFRCODPLLFreq_TypeDef; /** HFRCODPLL maximum frequency */ #define CMU_HFRCODPLL_MIN cmuHFRCODPLLFreq_1M0Hz /** HFRCODPLL minimum frequency */ #define CMU_HFRCODPLL_MAX cmuHFRCODPLLFreq_80M0Hz /** HFRCOEM23 frequency bands */ typedef enum { cmuHFRCOEM23Freq_1M0Hz = 1000000U, /**< 1MHz RC band. */ cmuHFRCOEM23Freq_2M0Hz = 2000000U, /**< 2MHz RC band. */ cmuHFRCOEM23Freq_4M0Hz = 4000000U, /**< 4MHz RC band. */ cmuHFRCOEM23Freq_13M0Hz = 13000000U, /**< 13MHz RC band. */ cmuHFRCOEM23Freq_16M0Hz = 16000000U, /**< 16MHz RC band. */ cmuHFRCOEM23Freq_19M0Hz = 19000000U, /**< 19MHz RC band. */ cmuHFRCOEM23Freq_26M0Hz = 26000000U, /**< 26MHz RC band. */ cmuHFRCOEM23Freq_32M0Hz = 32000000U, /**< 32MHz RC band. */ cmuHFRCOEM23Freq_40M0Hz = 40000000U, /**< 40MHz RC band. */ cmuHFRCOEM23Freq_UserDefined = 0, } CMU_HFRCOEM23Freq_TypeDef; /** HFRCOEM23 maximum frequency */ #define CMU_HFRCOEM23_MIN cmuHFRCOEM23Freq_1M0Hz /** HFRCOEM23 minimum frequency */ #define CMU_HFRCOEM23_MAX cmuHFRCOEM23Freq_40M0Hz /** Clock points in CMU clock-tree. */ typedef enum { /*******************/ /* Clock branches */ /*******************/ cmuClock_SYSCLK, /**< System clock. */ cmuClock_HCLK, /**< Core and AHB bus interface clock. */ cmuClock_EXPCLK, /**< Export clock. */ cmuClock_PCLK, /**< Peripheral APB bus interface clock. */ cmuClock_LSPCLK, /**< Low speed peripheral APB bus interface clock. */ cmuClock_IADCCLK, /**< IADC clock. */ cmuClock_EM01GRPACLK, /**< EM01GRPA clock. */ cmuClock_EM23GRPACLK, /**< EM23GRPA clock. */ cmuClock_EM4GRPACLK, /**< EM4GRPA clock. */ cmuClock_WDOG0CLK, /**< WDOG0 clock. */ cmuClock_WDOG1CLK, /**< WDOG1 clock. */ cmuClock_DPLLREFCLK, /**< DPLL reference clock. */ cmuClock_TRACECLK, /**< Debug trace clock. */ cmuClock_RTCCCLK, /**< RTCC clock. */ /*********************/ /* Peripheral clocks */ /*********************/ cmuClock_CORE, /**< Cortex-M33 core clock. */ cmuClock_SYSTICK, /**< Optional Cortex-M33 SYSTICK clock. */ cmuClock_ACMP0, /**< ACMP0 clock. */ cmuClock_ACMP1, /**< ACMP1 clock. */ cmuClock_BURTC, /**< BURTC clock. */ cmuClock_GPCRC, /**< GPCRC clock. */ cmuClock_GPIO, /**< GPIO clock. */ cmuClock_I2C0, /**< I2C0 clock. */ cmuClock_I2C1, /**< I2C1 clock. */ cmuClock_IADC0, /**< IADC clock. */ cmuClock_LDMA, /**< RTCC clock. */ cmuClock_LETIMER0, /**< LETIMER clock. */ cmuClock_PRS, /**< PRS clock. */ cmuClock_RTCC, /**< RTCC clock. */ cmuClock_TIMER0, /**< TIMER0 clock. */ cmuClock_TIMER1, /**< TIMER1 clock. */ cmuClock_TIMER2, /**< TIMER2 clock. */ cmuClock_TIMER3, /**< TIMER3 clock. */ cmuClock_USART0, /**< USART0 clock. */ cmuClock_USART1, /**< USART1 clock. */ cmuClock_USART2, /**< USART2 clock. */ cmuClock_WDOG0, /**< WDOG0 clock. */ cmuClock_WDOG1, /**< WDOG1 clock. */ cmuClock_PDM, /**< PDM clock. */ } CMU_Clock_TypeDef; /** Oscillator types. */ typedef enum { cmuOsc_LFXO, /**< Low frequency crystal oscillator. */ cmuOsc_LFRCO, /**< Low frequency RC oscillator. */ cmuOsc_FSRCO, /**< Fast startup fixed frequency RC oscillator. */ cmuOsc_HFXO, /**< High frequency crystal oscillator. */ cmuOsc_HFRCODPLL, /**< High frequency RC and DPLL oscillator. */ cmuOsc_HFRCOEM23, /**< High frequency deep sleep RC oscillator. */ cmuOsc_ULFRCO, /**< Ultra low frequency RC oscillator. */ } CMU_Osc_TypeDef; /** Selectable clock sources. */ typedef enum { cmuSelect_Error, /**< Usage error. */ cmuSelect_Disabled, /**< Clock selector disabled. */ cmuSelect_FSRCO, /**< Fast startup fixed frequency RC oscillator. */ cmuSelect_HFXO, /**< High frequency crystal oscillator. */ cmuSelect_HFRCODPLL, /**< High frequency RC and DPLL oscillator. */ cmuSelect_HFRCOEM23, /**< High frequency deep sleep RC oscillator. */ cmuSelect_CLKIN0, /**< External clock input. */ cmuSelect_LFXO, /**< Low frequency crystal oscillator. */ cmuSelect_LFRCO, /**< Low frequency RC oscillator. */ cmuSelect_ULFRCO, /**< Ultra low frequency RC oscillator. */ cmuSelect_PCLK, /**< Peripheral APB bus interface clock. */ cmuSelect_HCLK, /**< Core and AHB bus interface clock. */ cmuSelect_HCLKDIV1024, /**< Prescaled HCLK frequency clock. */ cmuSelect_EM01GRPACLK, /**< EM01GRPA clock. */ cmuSelect_EXPCLK, /**< Pin export clock. */ cmuSelect_PRS /**< PRS input as clock. */ } CMU_Select_TypeDef; /** DPLL reference clock edge detect selector. */ typedef enum { cmuDPLLEdgeSel_Fall = 0, /**< Detect falling edge of reference clock. */ cmuDPLLEdgeSel_Rise = 1 /**< Detect rising edge of reference clock. */ } CMU_DPLLEdgeSel_TypeDef; /** DPLL lock mode selector. */ typedef enum { cmuDPLLLockMode_Freq = _DPLL_CFG_MODE_FLL, /**< Frequency lock mode. */ cmuDPLLLockMode_Phase = _DPLL_CFG_MODE_PLL /**< Phase lock mode. */ } CMU_DPLLLockMode_TypeDef; /** LFXO oscillator modes. */ typedef enum { cmuLfxoOscMode_Crystal = _LFXO_CFG_MODE_XTAL, /**< Crystal oscillator. */ cmuLfxoOscMode_AcCoupledSine = _LFXO_CFG_MODE_BUFEXTCLK, /**< External AC coupled sine. */ cmuLfxoOscMode_External = _LFXO_CFG_MODE_DIGEXTCLK, /**< External digital clock. */ } CMU_LfxoOscMode_TypeDef; /** LFXO start-up timeout delay. */ typedef enum { cmuLfxoStartupDelay_2Cycles = _LFXO_CFG_TIMEOUT_CYCLES2, /**< 2 cycles start-up delay. */ cmuLfxoStartupDelay_256Cycles = _LFXO_CFG_TIMEOUT_CYCLES256, /**< 256 cycles start-up delay. */ cmuLfxoStartupDelay_1KCycles = _LFXO_CFG_TIMEOUT_CYCLES1K, /**< 1K cycles start-up delay. */ cmuLfxoStartupDelay_2KCycles = _LFXO_CFG_TIMEOUT_CYCLES2K, /**< 2K cycles start-up delay. */ cmuLfxoStartupDelay_4KCycles = _LFXO_CFG_TIMEOUT_CYCLES4K, /**< 4K cycles start-up delay. */ cmuLfxoStartupDelay_8KCycles = _LFXO_CFG_TIMEOUT_CYCLES8K, /**< 8K cycles start-up delay. */ cmuLfxoStartupDelay_16KCycles = _LFXO_CFG_TIMEOUT_CYCLES16K, /**< 16K cycles start-up delay. */ cmuLfxoStartupDelay_32KCycles = _LFXO_CFG_TIMEOUT_CYCLES32K, /**< 32K cycles start-up delay. */ } CMU_LfxoStartupDelay_TypeDef; /** HFXO oscillator modes. */ typedef enum { cmuHfxoOscMode_Crystal = _HFXO_CFG_MODE_XTAL, /**< Crystal oscillator. */ cmuHfxoOscMode_ExternalSine = _HFXO_CFG_MODE_EXTCLK, /**< External digital clock. */ } CMU_HfxoOscMode_TypeDef; /** HFXO core bias LSB change timeout. */ typedef enum { cmuHfxoCbLsbTimeout_8us = _HFXO_XTALCFG_TIMEOUTCBLSB_T8US, /**< 8 us timeout. */ cmuHfxoCbLsbTimeout_20us = _HFXO_XTALCFG_TIMEOUTCBLSB_T20US, /**< 20 us timeout. */ cmuHfxoCbLsbTimeout_41us = _HFXO_XTALCFG_TIMEOUTCBLSB_T41US, /**< 41 us timeout. */ cmuHfxoCbLsbTimeout_62us = _HFXO_XTALCFG_TIMEOUTCBLSB_T62US, /**< 62 us timeout. */ cmuHfxoCbLsbTimeout_83us = _HFXO_XTALCFG_TIMEOUTCBLSB_T83US, /**< 83 us timeout. */ cmuHfxoCbLsbTimeout_104us = _HFXO_XTALCFG_TIMEOUTCBLSB_T104US, /**< 104 us timeout. */ cmuHfxoCbLsbTimeout_125us = _HFXO_XTALCFG_TIMEOUTCBLSB_T125US, /**< 125 us timeout. */ cmuHfxoCbLsbTimeout_166us = _HFXO_XTALCFG_TIMEOUTCBLSB_T166US, /**< 166 us timeout. */ cmuHfxoCbLsbTimeout_208us = _HFXO_XTALCFG_TIMEOUTCBLSB_T208US, /**< 208 us timeout. */ cmuHfxoCbLsbTimeout_250us = _HFXO_XTALCFG_TIMEOUTCBLSB_T250US, /**< 250 us timeout. */ cmuHfxoCbLsbTimeout_333us = _HFXO_XTALCFG_TIMEOUTCBLSB_T333US, /**< 333 us timeout. */ cmuHfxoCbLsbTimeout_416us = _HFXO_XTALCFG_TIMEOUTCBLSB_T416US, /**< 416 us timeout. */ cmuHfxoCbLsbTimeout_833us = _HFXO_XTALCFG_TIMEOUTCBLSB_T833US, /**< 833 us timeout. */ cmuHfxoCbLsbTimeout_1250us = _HFXO_XTALCFG_TIMEOUTCBLSB_T1250US, /**< 1250 us timeout. */ cmuHfxoCbLsbTimeout_2083us = _HFXO_XTALCFG_TIMEOUTCBLSB_T2083US, /**< 2083 us timeout. */ cmuHfxoCbLsbTimeout_3750us = _HFXO_XTALCFG_TIMEOUTCBLSB_T3750US, /**< 3750 us timeout. */ } CMU_HfxoCbLsbTimeout_TypeDef; /** HFXO steady state timeout. */ typedef enum { cmuHfxoSteadyStateTimeout_16us = _HFXO_XTALCFG_TIMEOUTSTEADY_T16US, /**< 16 us timeout. */ cmuHfxoSteadyStateTimeout_41us = _HFXO_XTALCFG_TIMEOUTSTEADY_T41US, /**< 41 us timeout. */ cmuHfxoSteadyStateTimeout_83us = _HFXO_XTALCFG_TIMEOUTSTEADY_T83US, /**< 83 us timeout. */ cmuHfxoSteadyStateTimeout_125us = _HFXO_XTALCFG_TIMEOUTSTEADY_T125US, /**< 125 us timeout. */ cmuHfxoSteadyStateTimeout_166us = _HFXO_XTALCFG_TIMEOUTSTEADY_T166US, /**< 166 us timeout. */ cmuHfxoSteadyStateTimeout_208us = _HFXO_XTALCFG_TIMEOUTSTEADY_T208US, /**< 208 us timeout. */ cmuHfxoSteadyStateTimeout_250us = _HFXO_XTALCFG_TIMEOUTSTEADY_T250US, /**< 250 us timeout. */ cmuHfxoSteadyStateTimeout_333us = _HFXO_XTALCFG_TIMEOUTSTEADY_T333US, /**< 333 us timeout. */ cmuHfxoSteadyStateTimeout_416us = _HFXO_XTALCFG_TIMEOUTSTEADY_T416US, /**< 416 us timeout. */ cmuHfxoSteadyStateTimeout_500us = _HFXO_XTALCFG_TIMEOUTSTEADY_T500US, /**< 500 us timeout. */ cmuHfxoSteadyStateTimeout_666us = _HFXO_XTALCFG_TIMEOUTSTEADY_T666US, /**< 666 us timeout. */ cmuHfxoSteadyStateTimeout_833us = _HFXO_XTALCFG_TIMEOUTSTEADY_T833US, /**< 833 us timeout. */ cmuHfxoSteadyStateTimeout_1666us = _HFXO_XTALCFG_TIMEOUTSTEADY_T1666US, /**< 1666 us timeout. */ cmuHfxoSteadyStateTimeout_2500us = _HFXO_XTALCFG_TIMEOUTSTEADY_T2500US, /**< 2500 us timeout. */ cmuHfxoSteadyStateTimeout_4166us = _HFXO_XTALCFG_TIMEOUTSTEADY_T4166US, /**< 4166 us timeout. */ cmuHfxoSteadyStateTimeout_7500us = _HFXO_XTALCFG_TIMEOUTSTEADY_T7500US, /**< 7500 us timeout. */ } CMU_HfxoSteadyStateTimeout_TypeDef; /** HFXO core degeneration control. */ typedef enum { cmuHfxoCoreDegen_None = _HFXO_XTALCTRL_COREDGENANA_NONE, /**< No core degeneration. */ cmuHfxoCoreDegen_33 = _HFXO_XTALCTRL_COREDGENANA_DGEN33, /**< Core degeneration control 33. */ cmuHfxoCoreDegen_50 = _HFXO_XTALCTRL_COREDGENANA_DGEN50, /**< Core degeneration control 50. */ cmuHfxoCoreDegen_100 = _HFXO_XTALCTRL_COREDGENANA_DGEN100, /**< Core degeneration control 100. */ } CMU_HfxoCoreDegen_TypeDef; /** HFXO XI and XO pin fixed capacitor control. */ typedef enum { cmuHfxoCtuneFixCap_None = _HFXO_XTALCTRL_CTUNEFIXANA_NONE, /**< No fixed capacitors. */ cmuHfxoCtuneFixCap_Xi = _HFXO_XTALCTRL_CTUNEFIXANA_XI, /**< Fixed capacitor on XI pin. */ cmuHfxoCtuneFixCap_Xo = _HFXO_XTALCTRL_CTUNEFIXANA_XO, /**< Fixed capacitor on XO pin. */ cmuHfxoCtuneFixCap_Both = _HFXO_XTALCTRL_CTUNEFIXANA_BOTH, /**< Fixed capacitor on both pins. */ } CMU_HfxoCtuneFixCap_TypeDef; /******************************************************************************* ******************************* STRUCTS *********************************** ******************************************************************************/ /** LFXO initialization structure. Init values should be obtained from a configuration tool, app. note or xtal datasheet. */ typedef struct { uint8_t gain; /**< Startup gain. */ uint8_t capTune; /**< Internal capacitance tuning. */ CMU_LfxoStartupDelay_TypeDef timeout; /**< Startup delay. */ CMU_LfxoOscMode_TypeDef mode; /**< Oscillator mode. */ bool highAmplitudeEn; /**< High amplitude enable. */ bool agcEn; /**< AGC enable. */ bool failDetEM4WUEn; /**< EM4 wakeup on failure enable. */ bool failDetEn; /**< Oscillator failure detection enable. */ bool disOnDemand; /**< Disable on-demand requests. */ bool forceEn; /**< Force oscillator enable. */ bool regLock; /**< Lock register access. */ } CMU_LFXOInit_TypeDef; /** Default LFXO initialization values for XTAL mode. */ #define CMU_LFXOINIT_DEFAULT \ { \ 1, \ 38, \ cmuLfxoStartupDelay_4KCycles, \ cmuLfxoOscMode_Crystal, \ false, /* highAmplitudeEn */ \ true, /* agcEn */ \ false, /* failDetEM4WUEn */ \ false, /* failDetEn */ \ false, /* DisOndemand */ \ false, /* ForceEn */ \ false /* Lock registers */ \ } /** Default LFXO initialization values for external clock mode. */ #define CMU_LFXOINIT_EXTERNAL_CLOCK \ { \ 0U, \ 0U, \ cmuLfxoStartupDelay_2Cycles, \ cmuLfxoOscMode_External, \ false, /* highAmplitudeEn */ \ false, /* agcEn */ \ false, /* failDetEM4WUEn */ \ false, /* failDetEn */ \ false, /* DisOndemand */ \ false, /* ForceEn */ \ false /* Lock registers */ \ } /** Default LFXO initialization values for external sine mode. */ #define CMU_LFXOINIT_EXTERNAL_SINE \ { \ 0U, \ 0U, \ cmuLfxoStartupDelay_2Cycles, \ cmuLfxoOscMode_AcCoupledSine, \ false, /* highAmplitudeEn */ \ false, /* agcEn */ \ false, /* failDetEM4WUEn */ \ false, /* failDetEn */ \ false, /* DisOndemand */ \ false, /* ForceEn */ \ false /* Lock registers */ \ } /** HFXO initialization structure. Init values should be obtained from a configuration tool, app. note or xtal datasheet. */ typedef struct { CMU_HfxoCbLsbTimeout_TypeDef timeoutCbLsb; /**< Core bias change timeout. */ CMU_HfxoSteadyStateTimeout_TypeDef timeoutSteadyFirstLock; /**< Steady state timeout duration for first lock. */ CMU_HfxoSteadyStateTimeout_TypeDef timeoutSteady; /**< Steady state timeout duration. */ uint8_t ctuneXoStartup; /**< XO pin startup tuning capacitance. */ uint8_t ctuneXiStartup; /**< XI pin startup tuning capacitance. */ uint8_t coreBiasStartup; /**< Core bias startup current. */ uint8_t imCoreBiasStartup; /**< Core bias intermediate startup current. */ CMU_HfxoCoreDegen_TypeDef coreDegenAna; /**< Core degeneration control. */ CMU_HfxoCtuneFixCap_TypeDef ctuneFixAna; /**< Fixed tuning capacitance on XI/XO. */ uint8_t ctuneXoAna; /**< Tuning capacitance on XO. */ uint8_t ctuneXiAna; /**< Tuning capacitance on XI. */ uint8_t coreBiasAna; /**< Core bias current. */ bool enXiDcBiasAna; /**< Enable XI internal DC bias. */ CMU_HfxoOscMode_TypeDef mode; /**< Oscillator mode. */ bool forceXo2GndAna; /**< Force XO pin to ground. */ bool forceXi2GndAna; /**< Force XI pin to ground. */ bool disOnDemand; /**< Disable on-demand requests. */ bool forceEn; /**< Force oscillator enable. */ bool regLock; /**< Lock register access. */ } CMU_HFXOInit_TypeDef; /** Default HFXO initialization values for XTAL mode. */ #define CMU_HFXOINIT_DEFAULT \ { \ cmuHfxoCbLsbTimeout_416us, \ cmuHfxoSteadyStateTimeout_833us, /* First lock */ \ cmuHfxoSteadyStateTimeout_83us, /* Subsequent locks */ \ 0U, /* ctuneXoStartup */ \ 0U, /* ctuneXiStartup */ \ 32U, /* coreBiasStartup */ \ 32U, /* imCoreBiasStartup */ \ cmuHfxoCoreDegen_None, \ cmuHfxoCtuneFixCap_Both, \ _HFXO_XTALCTRL_CTUNEXOANA_DEFAULT, /* ctuneXoAna */ \ _HFXO_XTALCTRL_CTUNEXIANA_DEFAULT, /* ctuneXiAna */ \ 60U, /* coreBiasAna */ \ false, /* enXiDcBiasAna */ \ cmuHfxoOscMode_Crystal, \ false, /* forceXo2GndAna */ \ false, /* forceXi2GndAna */ \ false, /* DisOndemand */ \ false, /* ForceEn */ \ false /* Lock registers */ \ } /** Default HFXO initialization values for external sine mode. */ #define CMU_HFXOINIT_EXTERNAL_SINE \ { \ (CMU_HfxoCbLsbTimeout_TypeDef)0, /* timeoutCbLsb */ \ (CMU_HfxoSteadyStateTimeout_TypeDef)0, /* timeoutSteady, first lock */ \ (CMU_HfxoSteadyStateTimeout_TypeDef)0, /* timeoutSteady, subseq. locks */ \ 0U, /* ctuneXoStartup */ \ 0U, /* ctuneXiStartup */ \ 0U, /* coreBiasStartup */ \ 0U, /* imCoreBiasStartup */ \ cmuHfxoCoreDegen_None, \ cmuHfxoCtuneFixCap_None, \ 0U, /* ctuneXoAna */ \ 0U, /* ctuneXiAna */ \ 0U, /* coreBiasAna */ \ false, /* enXiDcBiasAna, false=DC true=AC coupling of signal */ \ cmuHfxoOscMode_ExternalSine, \ false, /* forceXo2GndAna */ \ false, /* forceXi2GndAna */ \ false, /* DisOndemand */ \ false, /* ForceEn */ \ false /* Lock registers */ \ } /** DPLL initialization structure. Frequency will be Fref*(N+1)/(M+1). */ typedef struct { uint32_t frequency; /**< PLL frequency value, max 80 MHz. */ uint16_t n; /**< Factor N. 300 <= N <= 4095 */ uint16_t m; /**< Factor M. M <= 4095 */ CMU_Select_TypeDef refClk; /**< Reference clock selector. */ CMU_DPLLEdgeSel_TypeDef edgeSel; /**< Reference clock edge detect selector. */ CMU_DPLLLockMode_TypeDef lockMode; /**< DPLL lock mode selector. */ bool autoRecover; /**< Enable automatic lock recovery. */ bool ditherEn; /**< Enable dither functionalityery. */ } CMU_DPLLInit_TypeDef; /** * DPLL initialization values for 39,998,805 Hz using LFXO as reference * clock, M=2 and N=3661. */ #define CMU_DPLL_LFXO_TO_40MHZ \ { \ 39998805, /* Target frequency. */ \ 3661, /* Factor N. */ \ 2, /* Factor M. */ \ cmuSelect_LFXO, /* Select LFXO as reference clock. */ \ cmuDPLLEdgeSel_Fall, /* Select falling edge of ref clock. */ \ cmuDPLLLockMode_Freq, /* Use frequency lock mode. */ \ true, /* Enable automatic lock recovery. */ \ false /* Don't enable dither function. */ \ } /** * DPLL initialization values for 80,000,000 Hz using HFXO as reference * clock, M = 1919, N = 3999. */ #define CMU_DPLL_HFXO_TO_80MHZ \ { \ 80000000, /* Target frequency. */ \ (4000 - 1), /* Factor N. */ \ (1920 - 1), /* Factor M. */ \ cmuSelect_HFXO, /* Select HFXO as reference clock. */ \ cmuDPLLEdgeSel_Fall, /* Select falling edge of ref clock. */ \ cmuDPLLLockMode_Freq, /* Use frequency lock mode. */ \ true, /* Enable automatic lock recovery. */ \ false /* Don't enable dither function. */ \ } /** * Default configurations for DPLL initialization. When using this macro * you need to modify the N and M factor and the desired frequency to match * the components placed on the board. */ #define CMU_DPLLINIT_DEFAULT \ { \ 80000000, /* Target frequency. */ \ (4000 - 1), /* Factor N. */ \ (1920 - 1), /* Factor M. */ \ cmuSelect_HFXO, /* Select HFXO as reference clock. */ \ cmuDPLLEdgeSel_Fall, /* Select falling edge of ref clock. */ \ cmuDPLLLockMode_Freq, /* Use frequency lock mode. */ \ true, /* Enable automatic lock recovery. */ \ false /* Don't enable dither function. */ \ } /******************************************************************************* ***************************** PROTOTYPES ********************************** ******************************************************************************/ uint32_t CMU_Calibrate(uint32_t cycles, CMU_Select_TypeDef reference); void CMU_CalibrateConfig(uint32_t downCycles, CMU_Select_TypeDef downSel, CMU_Select_TypeDef upSel); uint32_t CMU_CalibrateCountGet(void); void CMU_ClkOutPinConfig(uint32_t clkno, CMU_Select_TypeDef sel, CMU_ClkDiv_TypeDef clkdiv, GPIO_Port_TypeDef port, unsigned int pin); CMU_ClkDiv_TypeDef CMU_ClockDivGet(CMU_Clock_TypeDef clock); void CMU_ClockDivSet(CMU_Clock_TypeDef clock, CMU_ClkDiv_TypeDef div); uint32_t CMU_ClockFreqGet(CMU_Clock_TypeDef clock); CMU_Select_TypeDef CMU_ClockSelectGet(CMU_Clock_TypeDef clock); void CMU_ClockSelectSet(CMU_Clock_TypeDef clock, CMU_Select_TypeDef ref); CMU_HFRCODPLLFreq_TypeDef CMU_HFRCODPLLBandGet(void); void CMU_HFRCODPLLBandSet(CMU_HFRCODPLLFreq_TypeDef freq); CMU_HFRCOEM23Freq_TypeDef CMU_HFRCOEM23BandGet(void); void CMU_HFRCOEM23BandSet(CMU_HFRCOEM23Freq_TypeDef freq); bool CMU_DPLLLock(const CMU_DPLLInit_TypeDef *init); void CMU_HFXOInit(const CMU_HFXOInit_TypeDef *hfxoInit); void CMU_LFXOInit(const CMU_LFXOInit_TypeDef *lfxoInit); uint32_t CMU_OscillatorTuningGet(CMU_Osc_TypeDef osc); void CMU_OscillatorTuningSet(CMU_Osc_TypeDef osc, uint32_t val); void CMU_UpdateWaitStates(uint32_t freq, int vscale); /***************************************************************************//** * @brief * Configures continuous calibration mode. * @param[in] enable * If true, enables continuous calibration, if false disables continuous * calibration. ******************************************************************************/ __STATIC_INLINE void CMU_CalibrateCont(bool enable) { BUS_RegBitWrite(&CMU->CALCTRL, _CMU_CALCTRL_CONT_SHIFT, (uint32_t)enable); } /***************************************************************************//** * @brief * Starts calibration. * @note * This call is usually invoked after @ref CMU_CalibrateConfig() and possibly * @ref CMU_CalibrateCont(). ******************************************************************************/ __STATIC_INLINE void CMU_CalibrateStart(void) { CMU->CALCMD = CMU_CALCMD_CALSTART; } /***************************************************************************//** * @brief * Stop calibration counters. ******************************************************************************/ __STATIC_INLINE void CMU_CalibrateStop(void) { CMU->CALCMD = CMU_CALCMD_CALSTOP; } /***************************************************************************//** * @brief * Enable/disable a clock. * * @note * This is a dummy function to solve backward compatibility issues. * * @param[in] clock * The clock to enable/disable. * * @param[in] enable * @li true - enable specified clock. * @li false - disable specified clock. ******************************************************************************/ __STATIC_INLINE void CMU_ClockEnable(CMU_Clock_TypeDef clock, bool enable) { (void)clock; (void)enable; } /***************************************************************************//** * @brief * Unlock the DPLL. * @note * The HFRCODPLL oscillator is not turned off. ******************************************************************************/ __STATIC_INLINE void CMU_DPLLUnlock(void) { DPLL0->EN_CLR = DPLL_EN_EN; } /***************************************************************************//** * @brief * Clear one or more pending CMU interrupt flags. * * @param[in] flags * CMU interrupt sources to clear. ******************************************************************************/ __STATIC_INLINE void CMU_IntClear(uint32_t flags) { CMU->IF_CLR = flags; } /***************************************************************************//** * @brief * Disable one or more CMU interrupt sources. * * @param[in] flags * CMU interrupt sources to disable. ******************************************************************************/ __STATIC_INLINE void CMU_IntDisable(uint32_t flags) { CMU->IEN_CLR = flags; } /***************************************************************************//** * @brief * Enable one or more CMU interrupt sources. * * @note * Depending on the use, a pending interrupt may already be set prior to * enabling the interrupt. Consider using @ref CMU_IntClear() prior to * enabling if such a pending interrupt should be ignored. * * @param[in] flags * CMU interrupt sources to enable. ******************************************************************************/ __STATIC_INLINE void CMU_IntEnable(uint32_t flags) { CMU->IEN_SET = flags; } /***************************************************************************//** * @brief * Get pending CMU interrupt sources. * * @return * CMU interrupt sources pending. ******************************************************************************/ __STATIC_INLINE uint32_t CMU_IntGet(void) { return CMU->IF; } /***************************************************************************//** * @brief * Get enabled and pending CMU interrupt flags. * * @details * Useful for handling more interrupt sources in the same interrupt handler. * * @note * The event bits are not cleared by the use of this function. * * @return * Pending and enabled CMU interrupt sources. * The return value is the bitwise AND of * - the enabled interrupt sources in CMU_IEN and * - the pending interrupt flags CMU_IF ******************************************************************************/ __STATIC_INLINE uint32_t CMU_IntGetEnabled(void) { uint32_t ien; ien = CMU->IEN; return CMU->IF & ien; } /**************************************************************************//** * @brief * Set one or more pending CMU interrupt sources. * * @param[in] flags * CMU interrupt sources to set to pending. *****************************************************************************/ __STATIC_INLINE void CMU_IntSet(uint32_t flags) { CMU->IF_SET = flags; } /***************************************************************************//** * @brief * Lock CMU register access in order to protect registers contents against * unintended modification. * * @details * Please refer to the reference manual for CMU registers that will be * locked. * * @note * If locking the CMU registers, they must be unlocked prior to using any * CMU API functions modifying CMU registers protected by the lock. ******************************************************************************/ __STATIC_INLINE void CMU_Lock(void) { CMU->LOCK = ~CMU_LOCK_LOCKKEY_UNLOCK; } /***************************************************************************//** * @brief * Enable/disable oscillator. * * @note * This is a dummy function to solve backward compatibility issues. * * @param[in] osc * The oscillator to enable/disable. * * @param[in] enable * @li true - enable specified oscillator. * @li false - disable specified oscillator. * * @param[in] wait * Only used if @p enable is true. * @li true - wait for oscillator start-up time to timeout before returning. * @li false - do not wait for oscillator start-up time to timeout before * returning. ******************************************************************************/ __STATIC_INLINE void CMU_OscillatorEnable(CMU_Osc_TypeDef osc, bool enable, bool wait) { (void)osc; (void)enable; (void)wait; } /***************************************************************************//** * @brief * Unlock CMU register access so that writing to registers is possible. ******************************************************************************/ __STATIC_INLINE void CMU_Unlock(void) { CMU->LOCK = CMU_LOCK_LOCKKEY_UNLOCK; } /***************************************************************************//** * @brief * Lock WDOG register access in order to protect registers contents against * unintended modification. * * @note * If locking the WDOG registers, they must be unlocked prior to using any * emlib API functions modifying registers protected by the lock. ******************************************************************************/ __STATIC_INLINE void CMU_WdogLock(void) { CMU->WDOGLOCK = ~CMU_WDOGLOCK_LOCKKEY_UNLOCK; } /***************************************************************************//** * @brief * Unlock WDOG register access so that writing to registers is possible. ******************************************************************************/ __STATIC_INLINE void CMU_WdogUnlock(void) { CMU->WDOGLOCK = CMU_WDOGLOCK_LOCKKEY_UNLOCK; } #else // defined(_SILICON_LABS_32B_SERIES_2) /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ /* Select register IDs for internal use. */ #define CMU_NOSEL_REG 0 #define CMU_HFCLKSEL_REG 1 #define CMU_LFACLKSEL_REG 2 #define CMU_LFBCLKSEL_REG 3 #define CMU_LFCCLKSEL_REG 4 #define CMU_LFECLKSEL_REG 5 #define CMU_DBGCLKSEL_REG 6 #define CMU_USBCCLKSEL_REG 7 #define CMU_ADC0ASYNCSEL_REG 8 #define CMU_ADC1ASYNCSEL_REG 9 #define CMU_SDIOREFSEL_REG 10 #define CMU_QSPI0REFSEL_REG 11 #define CMU_USBRCLKSEL_REG 12 #define CMU_PDMREFSEL_REG 13 #define CMU_SEL_REG_POS 0U #define CMU_SEL_REG_MASK 0xfU /* Divisor/prescaler register IDs for internal use. */ #define CMU_NODIV_REG 0 #define CMU_NOPRESC_REG 0 #define CMU_HFPRESC_REG 1 #define CMU_HFCLKDIV_REG 1 #define CMU_HFEXPPRESC_REG 2 #define CMU_HFCLKLEPRESC_REG 3 #define CMU_HFPERPRESC_REG 4 #define CMU_HFPERCLKDIV_REG 4 #define CMU_HFPERPRESCB_REG 5 #define CMU_HFPERPRESCC_REG 6 #define CMU_HFCOREPRESC_REG 7 #define CMU_HFCORECLKDIV_REG 7 #define CMU_LFAPRESC0_REG 8 #define CMU_LFBPRESC0_REG 9 #define CMU_LFEPRESC0_REG 10 #define CMU_ADCASYNCDIV_REG 11 #define CMU_HFBUSPRESC_REG 12 #define CMU_PRESC_REG_POS 4U #define CMU_DIV_REG_POS CMU_PRESC_REG_POS #define CMU_PRESC_REG_MASK 0xfU #define CMU_DIV_REG_MASK CMU_PRESC_REG_MASK /* Enable register IDs for internal use. */ #define CMU_NO_EN_REG 0 #define CMU_CTRL_EN_REG 1 #define CMU_HFPERCLKDIV_EN_REG 1 #define CMU_HFPERCLKEN0_EN_REG 2 #define CMU_HFCORECLKEN0_EN_REG 3 #define CMU_PDMREF_EN_REG 4 #define CMU_HFBUSCLKEN0_EN_REG 5 #define CMU_LFACLKEN0_EN_REG 6 #define CMU_LFBCLKEN0_EN_REG 7 #define CMU_LFCCLKEN0_EN_REG 8 #define CMU_LFECLKEN0_EN_REG 9 #define CMU_PCNT_EN_REG 10 #define CMU_SDIOREF_EN_REG 11 #define CMU_QSPI0REF_EN_REG 12 #define CMU_QSPI1REF_EN_REG 13 #define CMU_HFPERCLKEN1_EN_REG 14 #define CMU_USBRCLK_EN_REG 15 #define CMU_EN_REG_POS 8U #define CMU_EN_REG_MASK 0xfU /* Enable register bit positions, for internal use. */ #define CMU_EN_BIT_POS 12U #define CMU_EN_BIT_MASK 0x1fU /* Clock branch bitfield positions, for internal use. */ #define CMU_HF_CLK_BRANCH 0 #define CMU_HFCORE_CLK_BRANCH 1 #define CMU_HFPER_CLK_BRANCH 2 #define CMU_HFPERB_CLK_BRANCH 3 #define CMU_HFPERC_CLK_BRANCH 4 #define CMU_HFBUS_CLK_BRANCH 5 #define CMU_HFEXP_CLK_BRANCH 6 #define CMU_DBG_CLK_BRANCH 7 #define CMU_AUX_CLK_BRANCH 8 #define CMU_RTC_CLK_BRANCH 9 #define CMU_RTCC_CLK_BRANCH 10 #define CMU_LETIMER0_CLK_BRANCH 11 #define CMU_LETIMER1_CLK_BRANCH 12 #define CMU_LEUART0_CLK_BRANCH 13 #define CMU_LEUART1_CLK_BRANCH 14 #define CMU_LFA_CLK_BRANCH 15 #define CMU_LFB_CLK_BRANCH 16 #define CMU_LFC_CLK_BRANCH 17 #define CMU_LFE_CLK_BRANCH 18 #define CMU_USBC_CLK_BRANCH 19 #define CMU_USBLE_CLK_BRANCH 20 #define CMU_LCDPRE_CLK_BRANCH 21 #define CMU_LCD_CLK_BRANCH 22 #define CMU_LESENSE_CLK_BRANCH 23 #define CMU_CSEN_LF_CLK_BRANCH 24 #define CMU_ADC0ASYNC_CLK_BRANCH 25 #define CMU_ADC1ASYNC_CLK_BRANCH 26 #define CMU_SDIOREF_CLK_BRANCH 27 #define CMU_QSPI0REF_CLK_BRANCH 28 #define CMU_USBR_CLK_BRANCH 29 #define CMU_PDMREF_CLK_BRANCH 30 #define CMU_CLK_BRANCH_POS 17U #define CMU_CLK_BRANCH_MASK 0x1fU #if defined(_EMU_CMD_EM01VSCALE0_MASK) /* Maximum clock frequency for VSCALE voltages. */ #define CMU_VSCALEEM01_LOWPOWER_VOLTAGE_CLOCK_MAX 20000000UL #endif #if defined(USB_PRESENT) && defined(_CMU_HFCORECLKEN0_USBC_MASK) #define USBC_CLOCK_PRESENT #endif #if defined(USB_PRESENT) && defined(_CMU_USBCTRL_MASK) #define USBR_CLOCK_PRESENT #endif /** @endcond */ /******************************************************************************* ******************************** ENUMS ************************************ ******************************************************************************/ /** Clock divisors. These values are valid for prescalers. */ #define cmuClkDiv_1 1 /**< Divide clock by 1. */ #define cmuClkDiv_2 2 /**< Divide clock by 2. */ #define cmuClkDiv_4 4 /**< Divide clock by 4. */ #define cmuClkDiv_8 8 /**< Divide clock by 8. */ #define cmuClkDiv_16 16 /**< Divide clock by 16. */ #define cmuClkDiv_32 32 /**< Divide clock by 32. */ #define cmuClkDiv_64 64 /**< Divide clock by 64. */ #define cmuClkDiv_128 128 /**< Divide clock by 128. */ #define cmuClkDiv_256 256 /**< Divide clock by 256. */ #define cmuClkDiv_512 512 /**< Divide clock by 512. */ #define cmuClkDiv_1024 1024 /**< Divide clock by 1024. */ #define cmuClkDiv_2048 2048 /**< Divide clock by 2048. */ #define cmuClkDiv_4096 4096 /**< Divide clock by 4096. */ #define cmuClkDiv_8192 8192 /**< Divide clock by 8192. */ #define cmuClkDiv_16384 16384 /**< Divide clock by 16384. */ #define cmuClkDiv_32768 32768 /**< Divide clock by 32768. */ /** Clock divider configuration */ typedef uint32_t CMU_ClkDiv_TypeDef; #if defined(_SILICON_LABS_32B_SERIES_1) /** Clockprescaler configuration */ typedef uint32_t CMU_ClkPresc_TypeDef; #endif #if defined(_CMU_HFRCOCTRL_BAND_MASK) /** High-frequency system RCO bands */ typedef enum { cmuHFRCOBand_1MHz = _CMU_HFRCOCTRL_BAND_1MHZ, /**< 1 MHz HFRCO band */ cmuHFRCOBand_7MHz = _CMU_HFRCOCTRL_BAND_7MHZ, /**< 7 MHz HFRCO band */ cmuHFRCOBand_11MHz = _CMU_HFRCOCTRL_BAND_11MHZ, /**< 11 MHz HFRCO band */ cmuHFRCOBand_14MHz = _CMU_HFRCOCTRL_BAND_14MHZ, /**< 14 MHz HFRCO band */ cmuHFRCOBand_21MHz = _CMU_HFRCOCTRL_BAND_21MHZ, /**< 21 MHz HFRCO band */ #if defined(CMU_HFRCOCTRL_BAND_28MHZ) cmuHFRCOBand_28MHz = _CMU_HFRCOCTRL_BAND_28MHZ, /**< 28 MHz HFRCO band */ #endif } CMU_HFRCOBand_TypeDef; #endif /* _CMU_HFRCOCTRL_BAND_MASK */ #if defined(_CMU_AUXHFRCOCTRL_BAND_MASK) /** AUX high-frequency RCO bands */ typedef enum { cmuAUXHFRCOBand_1MHz = _CMU_AUXHFRCOCTRL_BAND_1MHZ, /**< 1 MHz RC band */ cmuAUXHFRCOBand_7MHz = _CMU_AUXHFRCOCTRL_BAND_7MHZ, /**< 7 MHz RC band */ cmuAUXHFRCOBand_11MHz = _CMU_AUXHFRCOCTRL_BAND_11MHZ, /**< 11 MHz RC band */ cmuAUXHFRCOBand_14MHz = _CMU_AUXHFRCOCTRL_BAND_14MHZ, /**< 14 MHz RC band */ cmuAUXHFRCOBand_21MHz = _CMU_AUXHFRCOCTRL_BAND_21MHZ, /**< 21 MHz RC band */ #if defined(CMU_AUXHFRCOCTRL_BAND_28MHZ) cmuAUXHFRCOBand_28MHz = _CMU_AUXHFRCOCTRL_BAND_28MHZ, /**< 28 MHz RC band */ #endif } CMU_AUXHFRCOBand_TypeDef; #endif #if defined(_CMU_USHFRCOCONF_BAND_MASK) /** Universal serial high-frequency RC bands */ typedef enum { /** 24 MHz RC band. */ cmuUSHFRCOBand_24MHz = _CMU_USHFRCOCONF_BAND_24MHZ, /** 48 MHz RC band. */ cmuUSHFRCOBand_48MHz = _CMU_USHFRCOCONF_BAND_48MHZ, } CMU_USHFRCOBand_TypeDef; #endif #if defined(_CMU_USHFRCOCTRL_FREQRANGE_MASK) /** High-USHFRCO bands */ typedef enum { cmuUSHFRCOFreq_16M0Hz = 16000000U, /**< 16 MHz RC band */ cmuUSHFRCOFreq_32M0Hz = 32000000U, /**< 32 MHz RC band */ cmuUSHFRCOFreq_48M0Hz = 48000000U, /**< 48 MHz RC band */ cmuUSHFRCOFreq_50M0Hz = 50000000U, /**< 50 MHz RC band */ cmuUSHFRCOFreq_UserDefined = 0, } CMU_USHFRCOFreq_TypeDef; #define CMU_USHFRCO_MIN cmuUSHFRCOFreq_16M0Hz #define CMU_USHFRCO_MAX cmuUSHFRCOFreq_50M0Hz #endif #if defined(_CMU_HFRCOCTRL_FREQRANGE_MASK) /** High-frequency system RCO bands */ typedef enum { cmuHFRCOFreq_1M0Hz = 1000000U, /**< 1 MHz RC band */ cmuHFRCOFreq_2M0Hz = 2000000U, /**< 2 MHz RC band */ cmuHFRCOFreq_4M0Hz = 4000000U, /**< 4 MHz RC band */ cmuHFRCOFreq_7M0Hz = 7000000U, /**< 7 MHz RC band */ cmuHFRCOFreq_13M0Hz = 13000000U, /**< 13 MHz RC band */ cmuHFRCOFreq_16M0Hz = 16000000U, /**< 16 MHz RC band */ cmuHFRCOFreq_19M0Hz = 19000000U, /**< 19 MHz RC band */ cmuHFRCOFreq_26M0Hz = 26000000U, /**< 26 MHz RC band */ cmuHFRCOFreq_32M0Hz = 32000000U, /**< 32 MHz RC band */ cmuHFRCOFreq_38M0Hz = 38000000U, /**< 38 MHz RC band */ #if defined(_DEVINFO_HFRCOCAL13_MASK) cmuHFRCOFreq_48M0Hz = 48000000U, /**< 48 MHz RC band */ #endif #if defined(_DEVINFO_HFRCOCAL14_MASK) cmuHFRCOFreq_56M0Hz = 56000000U, /**< 56 MHz RC band */ #endif #if defined(_DEVINFO_HFRCOCAL15_MASK) cmuHFRCOFreq_64M0Hz = 64000000U, /**< 64 MHz RC band */ #endif #if defined(_DEVINFO_HFRCOCAL16_MASK) cmuHFRCOFreq_72M0Hz = 72000000U, /**< 72 MHz RC band */ #endif cmuHFRCOFreq_UserDefined = 0, } CMU_HFRCOFreq_TypeDef; #define CMU_HFRCO_MIN cmuHFRCOFreq_1M0Hz #if defined(_DEVINFO_HFRCOCAL16_MASK) #define CMU_HFRCO_MAX cmuHFRCOFreq_72M0Hz #elif defined(_DEVINFO_HFRCOCAL15_MASK) #define CMU_HFRCO_MAX cmuHFRCOFreq_64M0Hz #elif defined(_DEVINFO_HFRCOCAL14_MASK) #define CMU_HFRCO_MAX cmuHFRCOFreq_56M0Hz #elif defined(_DEVINFO_HFRCOCAL13_MASK) #define CMU_HFRCO_MAX cmuHFRCOFreq_48M0Hz #else #define CMU_HFRCO_MAX cmuHFRCOFreq_38M0Hz #endif #endif #if defined(_CMU_AUXHFRCOCTRL_FREQRANGE_MASK) /** AUX high-frequency RCO bands */ typedef enum { cmuAUXHFRCOFreq_1M0Hz = 1000000U, /**< 1 MHz RC band */ cmuAUXHFRCOFreq_2M0Hz = 2000000U, /**< 2 MHz RC band */ cmuAUXHFRCOFreq_4M0Hz = 4000000U, /**< 4 MHz RC band */ cmuAUXHFRCOFreq_7M0Hz = 7000000U, /**< 7 MHz RC band */ cmuAUXHFRCOFreq_13M0Hz = 13000000U, /**< 13 MHz RC band */ cmuAUXHFRCOFreq_16M0Hz = 16000000U, /**< 16 MHz RC band */ cmuAUXHFRCOFreq_19M0Hz = 19000000U, /**< 19 MHz RC band */ cmuAUXHFRCOFreq_26M0Hz = 26000000U, /**< 26 MHz RC band */ cmuAUXHFRCOFreq_32M0Hz = 32000000U, /**< 32 MHz RC band */ cmuAUXHFRCOFreq_38M0Hz = 38000000U, /**< 38 MHz RC band */ #if defined(_DEVINFO_AUXHFRCOCAL13_MASK) cmuAUXHFRCOFreq_48M0Hz = 48000000U, /**< 48 MHz RC band */ #endif #if defined(_DEVINFO_AUXHFRCOCAL14_MASK) cmuAUXHFRCOFreq_50M0Hz = 50000000U, /**< 50 MHz RC band */ #endif cmuAUXHFRCOFreq_UserDefined = 0, } CMU_AUXHFRCOFreq_TypeDef; #define CMU_AUXHFRCO_MIN cmuAUXHFRCOFreq_1M0Hz #if defined(_DEVINFO_AUXHFRCOCAL14_MASK) #define CMU_AUXHFRCO_MAX cmuAUXHFRCOFreq_50M0Hz #elif defined(_DEVINFO_AUXHFRCOCAL13_MASK) #define CMU_AUXHFRCO_MAX cmuAUXHFRCOFreq_48M0Hz #else #define CMU_AUXHFRCO_MAX cmuAUXHFRCOFreq_38M0Hz #endif #endif /** Clock points in CMU. See CMU overview in the reference manual. */ typedef enum { /*******************/ /* HF clock branch */ /*******************/ /** High-frequency clock */ #if defined(_CMU_CTRL_HFCLKDIV_MASK) \ || defined(_CMU_HFPRESC_MASK) cmuClock_HF = (CMU_HFCLKDIV_REG << CMU_DIV_REG_POS) | (CMU_HFCLKSEL_REG << CMU_SEL_REG_POS) | (CMU_NO_EN_REG << CMU_EN_REG_POS) | (0 << CMU_EN_BIT_POS) | (CMU_HF_CLK_BRANCH << CMU_CLK_BRANCH_POS), #else cmuClock_HF = (CMU_NODIV_REG << CMU_DIV_REG_POS) | (CMU_HFCLKSEL_REG << CMU_SEL_REG_POS) | (CMU_NO_EN_REG << CMU_EN_REG_POS) | (0 << CMU_EN_BIT_POS) | (CMU_HF_CLK_BRANCH << CMU_CLK_BRANCH_POS), #endif /** Debug clock */ cmuClock_DBG = (CMU_NODIV_REG << CMU_DIV_REG_POS) | (CMU_DBGCLKSEL_REG << CMU_SEL_REG_POS) | (CMU_NO_EN_REG << CMU_EN_REG_POS) | (0 << CMU_EN_BIT_POS) | (CMU_DBG_CLK_BRANCH << CMU_CLK_BRANCH_POS), /** AUX clock */ cmuClock_AUX = (CMU_NODIV_REG << CMU_DIV_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_NO_EN_REG << CMU_EN_REG_POS) | (0 << CMU_EN_BIT_POS) | (CMU_AUX_CLK_BRANCH << CMU_CLK_BRANCH_POS), #if defined(_CMU_HFEXPPRESC_MASK) /**********************/ /* HF export sub-branch */ /**********************/ /** Export clock */ cmuClock_EXPORT = (CMU_HFEXPPRESC_REG << CMU_PRESC_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_NO_EN_REG << CMU_EN_REG_POS) | (0 << CMU_EN_BIT_POS) | (CMU_HFEXP_CLK_BRANCH << CMU_CLK_BRANCH_POS), #endif #if defined(_CMU_HFBUSCLKEN0_MASK) /**********************************/ /* HF bus clock sub-branch */ /**********************************/ /** High-frequency bus clock */ #if defined(_CMU_HFBUSPRESC_MASK) cmuClock_BUS = (CMU_HFBUSPRESC_REG << CMU_PRESC_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_NO_EN_REG << CMU_EN_REG_POS) | (0 << CMU_EN_BIT_POS) | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS), #else cmuClock_BUS = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_NO_EN_REG << CMU_EN_REG_POS) | (0 << CMU_EN_BIT_POS) | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS), #endif #if defined(CMU_HFBUSCLKEN0_CRYPTO) /** Cryptography accelerator clock */ cmuClock_CRYPTO = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_HFBUSCLKEN0_CRYPTO_SHIFT << CMU_EN_BIT_POS) | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS), #endif #if defined(CMU_HFBUSCLKEN0_CRYPTO0) /** Cryptography accelerator 0 clock */ cmuClock_CRYPTO0 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_HFBUSCLKEN0_CRYPTO0_SHIFT << CMU_EN_BIT_POS) | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS), #endif #if defined(CMU_HFBUSCLKEN0_CRYPTO1) /** Cryptography accelerator 1 clock */ cmuClock_CRYPTO1 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_HFBUSCLKEN0_CRYPTO1_SHIFT << CMU_EN_BIT_POS) | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS), #endif #if defined(CMU_HFBUSCLKEN0_LDMA) /** Direct-memory access controller clock */ cmuClock_LDMA = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_HFBUSCLKEN0_LDMA_SHIFT << CMU_EN_BIT_POS) | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS), #endif #if defined(CMU_HFBUSCLKEN0_QSPI0) /** Quad SPI clock */ cmuClock_QSPI0 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_HFBUSCLKEN0_QSPI0_SHIFT << CMU_EN_BIT_POS) | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS), #endif #if defined(CMU_HFBUSCLKEN0_GPCRC) /** General-purpose cyclic redundancy checksum clock */ cmuClock_GPCRC = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_HFBUSCLKEN0_GPCRC_SHIFT << CMU_EN_BIT_POS) | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS), #endif #if defined(CMU_HFBUSCLKEN0_GPIO) /** General-purpose input/output clock */ cmuClock_GPIO = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_HFBUSCLKEN0_GPIO_SHIFT << CMU_EN_BIT_POS) | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS), #endif /** Low-energy clock divided down from HFBUSCLK */ cmuClock_HFLE = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_HFBUSCLKEN0_LE_SHIFT << CMU_EN_BIT_POS) | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS), #if defined(CMU_HFBUSCLKEN0_PRS) /** Peripheral reflex system clock */ cmuClock_PRS = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_HFBUSCLKEN0_PRS_SHIFT << CMU_EN_BIT_POS) | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS), #endif #endif /**********************************/ /* HF peripheral clock sub-branch */ /**********************************/ /** High-frequency peripheral clock */ #if defined(_CMU_HFPRESC_MASK) cmuClock_HFPER = (CMU_HFPERPRESC_REG << CMU_PRESC_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_CTRL_EN_REG << CMU_EN_REG_POS) | (_CMU_CTRL_HFPERCLKEN_SHIFT << CMU_EN_BIT_POS) | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), #else cmuClock_HFPER = (CMU_HFPERCLKDIV_REG << CMU_DIV_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_HFPERCLKDIV_EN_REG << CMU_EN_REG_POS) | (_CMU_HFPERCLKDIV_HFPERCLKEN_SHIFT << CMU_EN_BIT_POS) | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), #endif #if defined(_CMU_HFPERPRESCB_MASK) /** Branch B figh-frequency peripheral clock */ cmuClock_HFPERB = (CMU_HFPERPRESCB_REG << CMU_PRESC_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_CTRL_EN_REG << CMU_EN_REG_POS) | (_CMU_CTRL_HFPERCLKEN_SHIFT << CMU_EN_BIT_POS) | (CMU_HFPERB_CLK_BRANCH << CMU_CLK_BRANCH_POS), #endif #if defined(_CMU_HFPERPRESCC_MASK) /** Branch C figh-frequency peripheral clock */ cmuClock_HFPERC = (CMU_HFPERPRESCC_REG << CMU_PRESC_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_CTRL_EN_REG << CMU_EN_REG_POS) | (_CMU_CTRL_HFPERCLKEN_SHIFT << CMU_EN_BIT_POS) | (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS), #endif #if defined(CMU_HFPERCLKEN0_PDM) /** PDM clock */ cmuClock_PDM = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_HFPERCLKEN0_PDM_SHIFT << CMU_EN_BIT_POS) | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), #endif #if defined(CMU_HFPERCLKEN0_USART0) /** Universal sync/async receiver/transmitter 0 clock */ cmuClock_USART0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_HFPERCLKEN0_USART0_SHIFT << CMU_EN_BIT_POS) | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), #endif #if defined(CMU_HFPERCLKEN0_USARTRF0) /** Universal sync/async receiver/transmitter 0 clock */ cmuClock_USARTRF0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_HFPERCLKEN0_USARTRF0_SHIFT << CMU_EN_BIT_POS) | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), #endif #if defined(CMU_HFPERCLKEN0_USARTRF1) /** Universal sync/async receiver/transmitter 0 clock */ cmuClock_USARTRF1 = (CMU_NODIV_REG << CMU_DIV_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_HFPERCLKEN0_USARTRF1_SHIFT << CMU_EN_BIT_POS) | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), #endif #if defined(CMU_HFPERCLKEN0_USART1) /** Universal sync/async receiver/transmitter 1 clock */ cmuClock_USART1 = (CMU_NODIV_REG << CMU_DIV_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_HFPERCLKEN0_USART1_SHIFT << CMU_EN_BIT_POS) | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), #endif #if defined(CMU_HFPERCLKEN0_USART2) /** Universal sync/async receiver/transmitter 2 clock */ cmuClock_USART2 = (CMU_NODIV_REG << CMU_DIV_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_HFPERCLKEN0_USART2_SHIFT << CMU_EN_BIT_POS) #if defined(_CMU_HFPERPRESCB_MASK) | (CMU_HFPERB_CLK_BRANCH << CMU_CLK_BRANCH_POS), #else | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), #endif #endif #if defined(CMU_HFPERCLKEN0_USART3) /** Universal sync/async receiver/transmitter 3 clock */ cmuClock_USART3 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_HFPERCLKEN0_USART3_SHIFT << CMU_EN_BIT_POS) | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), #endif #if defined(CMU_HFPERCLKEN0_USART4) /** Universal sync/async receiver/transmitter 4 clock */ cmuClock_USART4 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_HFPERCLKEN0_USART4_SHIFT << CMU_EN_BIT_POS) | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), #endif #if defined(CMU_HFPERCLKEN0_USART5) /** Universal sync/async receiver/transmitter 5 clock */ cmuClock_USART5 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_HFPERCLKEN0_USART5_SHIFT << CMU_EN_BIT_POS) | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), #endif #if defined(CMU_HFPERCLKEN0_UART0) /** Universal async receiver/transmitter 0 clock */ cmuClock_UART0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_HFPERCLKEN0_UART0_SHIFT << CMU_EN_BIT_POS) | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), #elif defined(_CMU_HFPERCLKEN1_UART0_MASK) /** Universal async receiver/transmitter 0 clock */ cmuClock_UART0 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_HFPERCLKEN1_EN_REG << CMU_EN_REG_POS) | (_CMU_HFPERCLKEN1_UART0_SHIFT << CMU_EN_BIT_POS) | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), #endif #if defined(CMU_HFPERCLKEN0_UART1) /** Universal async receiver/transmitter 1 clock */ cmuClock_UART1 = (CMU_NODIV_REG << CMU_DIV_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_HFPERCLKEN0_UART1_SHIFT << CMU_EN_BIT_POS) | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), #elif defined(_CMU_HFPERCLKEN1_UART1_MASK) /** Universal async receiver/transmitter 1 clock */ cmuClock_UART1 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_HFPERCLKEN1_EN_REG << CMU_EN_REG_POS) | (_CMU_HFPERCLKEN1_UART1_SHIFT << CMU_EN_BIT_POS) | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), #endif #if defined(CMU_HFPERCLKEN0_TIMER0) /** Timer 0 clock */ cmuClock_TIMER0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_HFPERCLKEN0_TIMER0_SHIFT << CMU_EN_BIT_POS) #if defined(_CMU_HFPERPRESCB_MASK) | (CMU_HFPERB_CLK_BRANCH << CMU_CLK_BRANCH_POS), #else | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), #endif #endif #if defined(CMU_HFPERCLKEN0_TIMER1) /** Timer 1 clock */ cmuClock_TIMER1 = (CMU_NODIV_REG << CMU_DIV_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_HFPERCLKEN0_TIMER1_SHIFT << CMU_EN_BIT_POS) | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), #endif #if defined(CMU_HFPERCLKEN0_TIMER2) /** Timer 2 clock */ cmuClock_TIMER2 = (CMU_NODIV_REG << CMU_DIV_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_HFPERCLKEN0_TIMER2_SHIFT << CMU_EN_BIT_POS) | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), #endif #if defined(CMU_HFPERCLKEN0_TIMER3) /** Timer 3 clock */ cmuClock_TIMER3 = (CMU_NODIV_REG << CMU_DIV_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_HFPERCLKEN0_TIMER3_SHIFT << CMU_EN_BIT_POS) | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), #endif #if defined(CMU_HFPERCLKEN0_TIMER4) /** Timer 4 clock */ cmuClock_TIMER4 = (CMU_NODIV_REG << CMU_DIV_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_HFPERCLKEN0_TIMER4_SHIFT << CMU_EN_BIT_POS) | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), #endif #if defined(CMU_HFPERCLKEN0_TIMER5) /** Timer 5 clock */ cmuClock_TIMER5 = (CMU_NODIV_REG << CMU_DIV_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_HFPERCLKEN0_TIMER5_SHIFT << CMU_EN_BIT_POS) | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), #endif #if defined(CMU_HFPERCLKEN0_TIMER6) /** Timer 6 clock */ cmuClock_TIMER6 = (CMU_NODIV_REG << CMU_DIV_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_HFPERCLKEN0_TIMER6_SHIFT << CMU_EN_BIT_POS) | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), #endif #if defined(CMU_HFPERCLKEN0_WTIMER0) /** Wide-timer 0 clock */ cmuClock_WTIMER0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_HFPERCLKEN0_WTIMER0_SHIFT << CMU_EN_BIT_POS) | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), #elif defined(CMU_HFPERCLKEN1_WTIMER0) /** Wide-timer 0 clock */ cmuClock_WTIMER0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_HFPERCLKEN1_EN_REG << CMU_EN_REG_POS) | (_CMU_HFPERCLKEN1_WTIMER0_SHIFT << CMU_EN_BIT_POS) | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), #endif #if defined(CMU_HFPERCLKEN0_WTIMER1) /** Wide-timer 1 clock */ cmuClock_WTIMER1 = (CMU_NODIV_REG << CMU_DIV_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_HFPERCLKEN0_WTIMER1_SHIFT << CMU_EN_BIT_POS) | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), #elif defined(CMU_HFPERCLKEN1_WTIMER1) /** Wide-timer 1 clock */ cmuClock_WTIMER1 = (CMU_NODIV_REG << CMU_DIV_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_HFPERCLKEN1_EN_REG << CMU_EN_REG_POS) | (_CMU_HFPERCLKEN1_WTIMER1_SHIFT << CMU_EN_BIT_POS) | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), #endif #if defined(CMU_HFPERCLKEN1_WTIMER2) /** Wide-timer 2 clock */ cmuClock_WTIMER2 = (CMU_NODIV_REG << CMU_DIV_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_HFPERCLKEN1_EN_REG << CMU_EN_REG_POS) | (_CMU_HFPERCLKEN1_WTIMER2_SHIFT << CMU_EN_BIT_POS) | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), #endif #if defined(CMU_HFPERCLKEN1_WTIMER3) /** Wide-timer 3 clock */ cmuClock_WTIMER3 = (CMU_NODIV_REG << CMU_DIV_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_HFPERCLKEN1_EN_REG << CMU_EN_REG_POS) | (_CMU_HFPERCLKEN1_WTIMER3_SHIFT << CMU_EN_BIT_POS) | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), #endif #if defined(CMU_HFPERCLKEN0_CRYOTIMER) /** CRYOtimer clock */ cmuClock_CRYOTIMER = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_HFPERCLKEN0_CRYOTIMER_SHIFT << CMU_EN_BIT_POS) #if defined(_CMU_HFPERPRESCC_MASK) | (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS), #else | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), #endif #endif #if defined(CMU_HFPERCLKEN0_ACMP0) /** Analog comparator 0 clock */ cmuClock_ACMP0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_HFPERCLKEN0_ACMP0_SHIFT << CMU_EN_BIT_POS) #if defined(_CMU_HFPERPRESCC_MASK) | (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS), #else | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), #endif #endif #if defined(CMU_HFPERCLKEN0_ACMP1) /** Analog comparator 1 clock */ cmuClock_ACMP1 = (CMU_NODIV_REG << CMU_DIV_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_HFPERCLKEN0_ACMP1_SHIFT << CMU_EN_BIT_POS) #if defined(_CMU_HFPERPRESCC_MASK) | (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS), #else | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), #endif #endif #if defined(CMU_HFPERCLKEN0_ACMP2) /** Analog comparator 2 clock */ cmuClock_ACMP2 = (CMU_NODIV_REG << CMU_DIV_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_HFPERCLKEN0_ACMP2_SHIFT << CMU_EN_BIT_POS) | (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS), #endif #if defined(CMU_HFPERCLKEN0_ACMP3) /** Analog comparator 3 clock */ cmuClock_ACMP3 = (CMU_NODIV_REG << CMU_DIV_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_HFPERCLKEN0_ACMP3_SHIFT << CMU_EN_BIT_POS) | (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS), #endif #if defined(CMU_HFPERCLKEN0_PRS) /** Peripheral-reflex system clock */ cmuClock_PRS = (CMU_NODIV_REG << CMU_DIV_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_HFPERCLKEN0_PRS_SHIFT << CMU_EN_BIT_POS) | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), #endif #if defined(CMU_HFPERCLKEN0_DAC0) /** Digital-to-analog converter 0 clock */ cmuClock_DAC0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_HFPERCLKEN0_DAC0_SHIFT << CMU_EN_BIT_POS) | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), #endif #if defined(CMU_HFPERCLKEN0_VDAC0) /** Voltage digital-to-analog converter 0 clock */ cmuClock_VDAC0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_HFPERCLKEN0_VDAC0_SHIFT << CMU_EN_BIT_POS) | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), #elif defined(CMU_HFPERCLKEN1_VDAC0) /** Voltage digital-to-analog converter 0 clock */ cmuClock_VDAC0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_HFPERCLKEN1_EN_REG << CMU_EN_REG_POS) | (_CMU_HFPERCLKEN1_VDAC0_SHIFT << CMU_EN_BIT_POS) #if defined(_CMU_HFPERPRESCC_MASK) | (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS), #else | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), #endif #endif #if defined(CMU_HFPERCLKEN0_IDAC0) /** Current digital-to-analog converter 0 clock */ cmuClock_IDAC0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_HFPERCLKEN0_IDAC0_SHIFT << CMU_EN_BIT_POS) #if defined(_CMU_HFPERPRESCC_MASK) | (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS), #else | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), #endif #endif #if defined(CMU_HFPERCLKEN0_GPIO) /** General-purpose input/output clock */ cmuClock_GPIO = (CMU_NODIV_REG << CMU_DIV_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_HFPERCLKEN0_GPIO_SHIFT << CMU_EN_BIT_POS) | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), #endif #if defined(CMU_HFPERCLKEN0_VCMP) /** Voltage comparator clock */ cmuClock_VCMP = (CMU_NODIV_REG << CMU_DIV_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_HFPERCLKEN0_VCMP_SHIFT << CMU_EN_BIT_POS) | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), #endif #if defined(CMU_HFPERCLKEN0_ADC0) /** Analog-to-digital converter 0 clock */ cmuClock_ADC0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_HFPERCLKEN0_ADC0_SHIFT << CMU_EN_BIT_POS) #if defined(_CMU_HFPERPRESCC_MASK) | (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS), #else | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), #endif #endif #if defined(CMU_HFPERCLKEN0_ADC1) /** Analog-to-digital converter 1 clock */ cmuClock_ADC1 = (CMU_NODIV_REG << CMU_DIV_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_HFPERCLKEN0_ADC1_SHIFT << CMU_EN_BIT_POS) | (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS), #endif #if defined(CMU_HFPERCLKEN0_I2C0) /** I2C 0 clock */ cmuClock_I2C0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_HFPERCLKEN0_I2C0_SHIFT << CMU_EN_BIT_POS) #if defined(_CMU_HFPERPRESCC_MASK) | (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS), #else | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), #endif #endif #if defined(CMU_HFPERCLKEN0_I2C1) /** I2C 1 clock */ cmuClock_I2C1 = (CMU_NODIV_REG << CMU_DIV_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_HFPERCLKEN0_I2C1_SHIFT << CMU_EN_BIT_POS) #if defined(_CMU_HFPERPRESCC_MASK) | (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS), #else | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), #endif #endif #if defined(CMU_HFPERCLKEN0_I2C2) /** I2C 2 clock */ cmuClock_I2C2 = (CMU_NODIV_REG << CMU_DIV_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_HFPERCLKEN0_I2C2_SHIFT << CMU_EN_BIT_POS) | (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS), #endif #if defined(CMU_HFPERCLKEN0_CSEN) /** Capacitive Sense HF clock */ cmuClock_CSEN_HF = (CMU_NODIV_REG << CMU_DIV_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_HFPERCLKEN0_CSEN_SHIFT << CMU_EN_BIT_POS) | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), #elif defined(CMU_HFPERCLKEN1_CSEN) /** Capacitive Sense HF clock */ cmuClock_CSEN_HF = (CMU_NODIV_REG << CMU_DIV_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_HFPERCLKEN1_EN_REG << CMU_EN_REG_POS) | (_CMU_HFPERCLKEN1_CSEN_SHIFT << CMU_EN_BIT_POS) | (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS), #endif #if defined(CMU_HFPERCLKEN0_TRNG0) /** True random number generator clock */ cmuClock_TRNG0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_HFPERCLKEN0_TRNG0_SHIFT << CMU_EN_BIT_POS) | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), #endif #if defined(_CMU_HFPERCLKEN1_CAN0_MASK) /** Controller Area Network 0 clock */ cmuClock_CAN0 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_HFPERCLKEN1_EN_REG << CMU_EN_REG_POS) | (_CMU_HFPERCLKEN1_CAN0_SHIFT << CMU_EN_BIT_POS) | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), #endif #if defined(_CMU_HFPERCLKEN1_CAN1_MASK) /** Controller Area Network 1 clock. */ cmuClock_CAN1 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_HFPERCLKEN1_EN_REG << CMU_EN_REG_POS) | (_CMU_HFPERCLKEN1_CAN1_SHIFT << CMU_EN_BIT_POS) | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), #endif /**********************/ /* HF core sub-branch */ /**********************/ /** Core clock */ cmuClock_CORE = (CMU_HFCORECLKDIV_REG << CMU_DIV_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_NO_EN_REG << CMU_EN_REG_POS) | (0 << CMU_EN_BIT_POS) | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS), #if defined(CMU_HFCORECLKEN0_AES) /** Advanced encryption standard accelerator clock */ cmuClock_AES = (CMU_NODIV_REG << CMU_DIV_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_HFCORECLKEN0_AES_SHIFT << CMU_EN_BIT_POS) | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS), #endif #if defined(CMU_HFCORECLKEN0_DMA) /** Direct memory access controller clock */ cmuClock_DMA = (CMU_NODIV_REG << CMU_DIV_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_HFCORECLKEN0_DMA_SHIFT << CMU_EN_BIT_POS) | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS), #endif #if defined(CMU_HFCORECLKEN0_LE) /** Low-energy clock divided down from HFCORECLK */ cmuClock_HFLE = (CMU_NODIV_REG << CMU_DIV_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_HFCORECLKEN0_LE_SHIFT << CMU_EN_BIT_POS) | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS), #endif #if defined(CMU_HFCORECLKEN0_EBI) /** External bus interface clock */ cmuClock_EBI = (CMU_NODIV_REG << CMU_DIV_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_HFCORECLKEN0_EBI_SHIFT << CMU_EN_BIT_POS) | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS), #elif defined(_CMU_HFBUSCLKEN0_EBI_MASK) /** External bus interface clock */ cmuClock_EBI = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_HFBUSCLKEN0_EBI_SHIFT << CMU_EN_BIT_POS) | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS), #endif #if defined(_CMU_HFBUSCLKEN0_ETH_MASK) /** Ethernet clock */ cmuClock_ETH = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_HFBUSCLKEN0_ETH_SHIFT << CMU_EN_BIT_POS) | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS), #endif #if defined(_CMU_HFBUSCLKEN0_SDIO_MASK) /** SDIO clock */ cmuClock_SDIO = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_HFBUSCLKEN0_SDIO_SHIFT << CMU_EN_BIT_POS) | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS), #endif #if defined(USBC_CLOCK_PRESENT) /** USB Core clock */ cmuClock_USBC = (CMU_NODIV_REG << CMU_DIV_REG_POS) | (CMU_USBCCLKSEL_REG << CMU_SEL_REG_POS) | (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_HFCORECLKEN0_USBC_SHIFT << CMU_EN_BIT_POS) | (CMU_USBC_CLK_BRANCH << CMU_CLK_BRANCH_POS), #endif #if defined (USBR_CLOCK_PRESENT) /** USB Rate clock */ cmuClock_USBR = (CMU_NODIV_REG << CMU_DIV_REG_POS) | (CMU_USBRCLKSEL_REG << CMU_SEL_REG_POS) | (CMU_USBRCLK_EN_REG << CMU_EN_REG_POS) | (_CMU_USBCTRL_USBCLKEN_SHIFT << CMU_EN_BIT_POS) | (CMU_USBR_CLK_BRANCH << CMU_CLK_BRANCH_POS), #endif #if defined(CMU_HFCORECLKEN0_USB) /** USB clock */ cmuClock_USB = (CMU_NODIV_REG << CMU_DIV_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_HFCORECLKEN0_USB_SHIFT << CMU_EN_BIT_POS) | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS), #elif defined(CMU_HFBUSCLKEN0_USB) /** USB clock */ cmuClock_USB = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_HFBUSCLKEN0_USB_SHIFT << CMU_EN_BIT_POS) | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS), #endif /***************/ /* LF A branch */ /***************/ /** Low-frequency A clock */ cmuClock_LFA = (CMU_NODIV_REG << CMU_DIV_REG_POS) | (CMU_LFACLKSEL_REG << CMU_SEL_REG_POS) | (CMU_NO_EN_REG << CMU_EN_REG_POS) | (0 << CMU_EN_BIT_POS) | (CMU_LFA_CLK_BRANCH << CMU_CLK_BRANCH_POS), #if defined(CMU_LFACLKEN0_RTC) /** Real time counter clock */ cmuClock_RTC = (CMU_LFAPRESC0_REG << CMU_DIV_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_LFACLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_LFACLKEN0_RTC_SHIFT << CMU_EN_BIT_POS) | (CMU_RTC_CLK_BRANCH << CMU_CLK_BRANCH_POS), #endif #if defined(CMU_LFACLKEN0_LETIMER0) /** Low-energy timer 0 clock */ cmuClock_LETIMER0 = (CMU_LFAPRESC0_REG << CMU_DIV_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_LFACLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_LFACLKEN0_LETIMER0_SHIFT << CMU_EN_BIT_POS) | (CMU_LETIMER0_CLK_BRANCH << CMU_CLK_BRANCH_POS), #endif #if defined(CMU_LFACLKEN0_LETIMER1) /** Low-energy timer 1 clock */ cmuClock_LETIMER1 = (CMU_LFAPRESC0_REG << CMU_DIV_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_LFACLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_LFACLKEN0_LETIMER1_SHIFT << CMU_EN_BIT_POS) | (CMU_LETIMER1_CLK_BRANCH << CMU_CLK_BRANCH_POS), #endif #if defined(CMU_LFACLKEN0_LCD) /** Liquid crystal display, pre FDIV clock */ cmuClock_LCDpre = (CMU_LFAPRESC0_REG << CMU_DIV_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_NO_EN_REG << CMU_EN_REG_POS) | (0 << CMU_EN_BIT_POS) | (CMU_LCDPRE_CLK_BRANCH << CMU_CLK_BRANCH_POS), /** Liquid crystal display clock. Note that FDIV prescaler * must be set by special API. */ cmuClock_LCD = (CMU_NODIV_REG << CMU_DIV_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_LFACLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_LFACLKEN0_LCD_SHIFT << CMU_EN_BIT_POS) | (CMU_LCD_CLK_BRANCH << CMU_CLK_BRANCH_POS), #endif #if defined(CMU_PCNTCTRL_PCNT0CLKEN) /** Pulse counter 0 clock */ cmuClock_PCNT0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_PCNT_EN_REG << CMU_EN_REG_POS) | (_CMU_PCNTCTRL_PCNT0CLKEN_SHIFT << CMU_EN_BIT_POS) | (CMU_LFA_CLK_BRANCH << CMU_CLK_BRANCH_POS), #endif #if defined(CMU_PCNTCTRL_PCNT1CLKEN) /** Pulse counter 1 clock */ cmuClock_PCNT1 = (CMU_NODIV_REG << CMU_DIV_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_PCNT_EN_REG << CMU_EN_REG_POS) | (_CMU_PCNTCTRL_PCNT1CLKEN_SHIFT << CMU_EN_BIT_POS) | (CMU_LFA_CLK_BRANCH << CMU_CLK_BRANCH_POS), #endif #if defined(CMU_PCNTCTRL_PCNT2CLKEN) /** Pulse counter 2 clock */ cmuClock_PCNT2 = (CMU_NODIV_REG << CMU_DIV_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_PCNT_EN_REG << CMU_EN_REG_POS) | (_CMU_PCNTCTRL_PCNT2CLKEN_SHIFT << CMU_EN_BIT_POS) | (CMU_LFA_CLK_BRANCH << CMU_CLK_BRANCH_POS), #endif #if defined(CMU_LFACLKEN0_LESENSE) /** LESENSE clock */ cmuClock_LESENSE = (CMU_LFAPRESC0_REG << CMU_DIV_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_LFACLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_LFACLKEN0_LESENSE_SHIFT << CMU_EN_BIT_POS) | (CMU_LESENSE_CLK_BRANCH << CMU_CLK_BRANCH_POS), #endif /***************/ /* LF B branch */ /***************/ /** Low-frequency B clock */ cmuClock_LFB = (CMU_NODIV_REG << CMU_DIV_REG_POS) | (CMU_LFBCLKSEL_REG << CMU_SEL_REG_POS) | (CMU_NO_EN_REG << CMU_EN_REG_POS) | (0 << CMU_EN_BIT_POS) | (CMU_LFB_CLK_BRANCH << CMU_CLK_BRANCH_POS), #if defined(CMU_LFBCLKEN0_LEUART0) /** Low-energy universal asynchronous receiver/transmitter 0 clock */ cmuClock_LEUART0 = (CMU_LFBPRESC0_REG << CMU_DIV_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_LFBCLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_LFBCLKEN0_LEUART0_SHIFT << CMU_EN_BIT_POS) | (CMU_LEUART0_CLK_BRANCH << CMU_CLK_BRANCH_POS), #endif #if defined(CMU_LFBCLKEN0_CSEN) /** Capacitive Sense LF clock */ cmuClock_CSEN_LF = (CMU_LFBPRESC0_REG << CMU_DIV_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_LFBCLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_LFBCLKEN0_CSEN_SHIFT << CMU_EN_BIT_POS) | (CMU_CSEN_LF_CLK_BRANCH << CMU_CLK_BRANCH_POS), #endif #if defined(CMU_LFBCLKEN0_LEUART1) /** Low-energy universal asynchronous receiver/transmitter 1 clock */ cmuClock_LEUART1 = (CMU_LFBPRESC0_REG << CMU_DIV_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_LFBCLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_LFBCLKEN0_LEUART1_SHIFT << CMU_EN_BIT_POS) | (CMU_LEUART1_CLK_BRANCH << CMU_CLK_BRANCH_POS), #endif #if defined(CMU_LFBCLKEN0_SYSTICK) /** Cortex SYSTICK LF clock */ cmuClock_SYSTICK = (CMU_LFBPRESC0_REG << CMU_DIV_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_LFBCLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_LFBCLKEN0_SYSTICK_SHIFT << CMU_EN_BIT_POS) | (CMU_LEUART0_CLK_BRANCH << CMU_CLK_BRANCH_POS), #endif #if defined(_CMU_LFCCLKEN0_MASK) /***************/ /* LF C branch */ /***************/ /** Low-frequency C clock */ cmuClock_LFC = (CMU_NODIV_REG << CMU_DIV_REG_POS) | (CMU_LFCCLKSEL_REG << CMU_SEL_REG_POS) | (CMU_NO_EN_REG << CMU_EN_REG_POS) | (0 << CMU_EN_BIT_POS) | (CMU_LFC_CLK_BRANCH << CMU_CLK_BRANCH_POS), #if defined(CMU_LFCCLKEN0_USBLE) /** USB LE clock */ cmuClock_USBLE = (CMU_NODIV_REG << CMU_DIV_REG_POS) | (CMU_LFCCLKSEL_REG << CMU_SEL_REG_POS) | (CMU_LFCCLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_LFCCLKEN0_USBLE_SHIFT << CMU_EN_BIT_POS) | (CMU_USBLE_CLK_BRANCH << CMU_CLK_BRANCH_POS), #elif defined(CMU_LFCCLKEN0_USB) /** USB LE clock */ cmuClock_USBLE = (CMU_NODIV_REG << CMU_DIV_REG_POS) | (CMU_LFCCLKSEL_REG << CMU_SEL_REG_POS) | (CMU_LFCCLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_LFCCLKEN0_USB_SHIFT << CMU_EN_BIT_POS) | (CMU_USBLE_CLK_BRANCH << CMU_CLK_BRANCH_POS), #endif #endif #if defined(_CMU_LFECLKEN0_MASK) /***************/ /* LF E branch */ /***************/ /** Low-frequency E clock */ cmuClock_LFE = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) | (CMU_LFECLKSEL_REG << CMU_SEL_REG_POS) | (CMU_NO_EN_REG << CMU_EN_REG_POS) | (0 << CMU_EN_BIT_POS) | (CMU_LFE_CLK_BRANCH << CMU_CLK_BRANCH_POS), /** Real-time counter and calendar clock */ #if defined (CMU_LFECLKEN0_RTCC) cmuClock_RTCC = (CMU_LFEPRESC0_REG << CMU_PRESC_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_LFECLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_LFECLKEN0_RTCC_SHIFT << CMU_EN_BIT_POS) | (CMU_RTCC_CLK_BRANCH << CMU_CLK_BRANCH_POS), #endif #endif /**********************************/ /* Asynchronous peripheral clocks */ /**********************************/ #if defined(_CMU_ADCCTRL_ADC0CLKSEL_MASK) /** ADC0 asynchronous clock */ cmuClock_ADC0ASYNC = (CMU_ADCASYNCDIV_REG << CMU_DIV_REG_POS) | (CMU_ADC0ASYNCSEL_REG << CMU_SEL_REG_POS) | (CMU_NO_EN_REG << CMU_EN_REG_POS) | (0 << CMU_EN_BIT_POS) | (CMU_ADC0ASYNC_CLK_BRANCH << CMU_CLK_BRANCH_POS), #endif #if defined(_CMU_ADCCTRL_ADC1CLKSEL_MASK) /** ADC1 asynchronous clock */ cmuClock_ADC1ASYNC = (CMU_ADCASYNCDIV_REG << CMU_DIV_REG_POS) | (CMU_ADC1ASYNCSEL_REG << CMU_SEL_REG_POS) | (CMU_NO_EN_REG << CMU_EN_REG_POS) | (0 << CMU_EN_BIT_POS) | (CMU_ADC1ASYNC_CLK_BRANCH << CMU_CLK_BRANCH_POS), #endif #if defined(_CMU_SDIOCTRL_SDIOCLKDIS_MASK) /** SDIO reference clock */ cmuClock_SDIOREF = (CMU_NODIV_REG << CMU_DIV_REG_POS) | (CMU_SDIOREFSEL_REG << CMU_SEL_REG_POS) | (CMU_SDIOREF_EN_REG << CMU_EN_REG_POS) | (_CMU_SDIOCTRL_SDIOCLKDIS_SHIFT << CMU_EN_BIT_POS) | (CMU_SDIOREF_CLK_BRANCH << CMU_CLK_BRANCH_POS), #endif #if defined(_CMU_QSPICTRL_QSPI0CLKDIS_MASK) /** QSPI0 reference clock */ cmuClock_QSPI0REF = (CMU_NODIV_REG << CMU_DIV_REG_POS) | (CMU_QSPI0REFSEL_REG << CMU_SEL_REG_POS) | (CMU_QSPI0REF_EN_REG << CMU_EN_REG_POS) | (_CMU_QSPICTRL_QSPI0CLKDIS_SHIFT << CMU_EN_BIT_POS) | (CMU_QSPI0REF_CLK_BRANCH << CMU_CLK_BRANCH_POS), #endif #if defined(_CMU_PDMCTRL_PDMCLKEN_MASK) /** PDM reference clock */ cmuClock_PDMREF = (CMU_NODIV_REG << CMU_DIV_REG_POS) | (CMU_PDMREFSEL_REG << CMU_SEL_REG_POS) | (CMU_PDMREF_EN_REG << CMU_EN_REG_POS) | (_CMU_PDMCTRL_PDMCLKEN_SHIFT << CMU_EN_BIT_POS) | (CMU_PDMREF_CLK_BRANCH << CMU_CLK_BRANCH_POS), #endif } CMU_Clock_TypeDef; /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ /* Deprecated CMU_Clock_TypeDef member */ #define cmuClock_CORELE cmuClock_HFLE /** @endcond */ /** Oscillator types. */ typedef enum { cmuOsc_LFXO, /**< Low-frequency crystal oscillator. */ cmuOsc_LFRCO, /**< Low-frequency RC oscillator. */ cmuOsc_HFXO, /**< High-frequency crystal oscillator. */ cmuOsc_HFRCO, /**< High-frequency RC oscillator. */ cmuOsc_AUXHFRCO, /**< Auxiliary high-frequency RC oscillator. */ #if defined(_CMU_STATUS_USHFRCOENS_MASK) cmuOsc_USHFRCO, /**< Universal serial high-frequency RC oscillator */ #endif #if defined(CMU_LFCLKSEL_LFAE_ULFRCO) || defined(CMU_LFACLKSEL_LFA_ULFRCO) cmuOsc_ULFRCO, /**< Ultra low-frequency RC oscillator. */ #endif #if defined(CMU_HFCLKSTATUS_SELECTED_CLKIN0) cmuOsc_CLKIN0, /**< External oscillator. */ #endif } CMU_Osc_TypeDef; /** Oscillator modes. */ typedef enum { cmuOscMode_Crystal, /**< Crystal oscillator. */ cmuOscMode_AcCoupled, /**< AC-coupled buffer. */ cmuOscMode_External, /**< External digital clock. */ } CMU_OscMode_TypeDef; /** Selectable clock sources. */ typedef enum { cmuSelect_Error, /**< Usage error. */ cmuSelect_Disabled, /**< Clock selector disabled. */ cmuSelect_LFXO, /**< Low-frequency crystal oscillator. */ cmuSelect_LFRCO, /**< Low-frequency RC oscillator. */ cmuSelect_HFXO, /**< High-frequency crystal oscillator. */ cmuSelect_HFRCO, /**< High-frequency RC oscillator. */ cmuSelect_HFCLKLE, /**< High-frequency LE clock divided by 2 or 4. */ cmuSelect_AUXHFRCO, /**< Auxilliary clock source can be used for debug clock. */ cmuSelect_HFSRCCLK, /**< High-frequency source clock. */ cmuSelect_HFCLK, /**< Divided HFCLK on Giant for debug clock, undivided on Tiny Gecko and for USBC (not used on Gecko). */ #if defined(CMU_STATUS_USHFRCOENS) cmuSelect_USHFRCO, /**< Universal serial high-frequency RC oscillator. */ #endif #if defined(CMU_CMD_HFCLKSEL_USHFRCODIV2) cmuSelect_USHFRCODIV2, /**< Universal serial high-frequency RC oscillator / 2. */ #endif #if defined(CMU_HFXOCTRL_HFXOX2EN) cmuSelect_HFXOX2, /**< High-frequency crystal oscillator x 2. */ #endif #if defined(CMU_LFCLKSEL_LFAE_ULFRCO) || defined(CMU_LFACLKSEL_LFA_ULFRCO) cmuSelect_ULFRCO, /**< Ultra low-frequency RC oscillator. */ #endif #if defined(CMU_HFCLKSTATUS_SELECTED_HFRCODIV2) cmuSelect_HFRCODIV2, /**< High-frequency RC oscillator divided by 2. */ #endif #if defined(CMU_HFCLKSTATUS_SELECTED_CLKIN0) cmuSelect_CLKIN0, /**< External clock input. */ #endif } CMU_Select_TypeDef; #if defined(CMU_HFCORECLKEN0_LE) /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ /* Deprecated CMU_Select_TypeDef member */ #define cmuSelect_CORELEDIV2 cmuSelect_HFCLKLE /** @endcond */ #endif #if defined(_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK) || defined(_CMU_HFXOCTRL_PEAKDETMODE_MASK) /** HFXO tuning modes */ typedef enum { cmuHFXOTuningMode_Auto = 0, cmuHFXOTuningMode_PeakDetectCommand = CMU_CMD_HFXOPEAKDETSTART, /**< Run peak detect optimization only. */ #if defined(CMU_CMD_HFXOSHUNTOPTSTART) cmuHFXOTuningMode_ShuntCommand = CMU_CMD_HFXOSHUNTOPTSTART, /**< Run shunt current optimization only. */ cmuHFXOTuningMode_PeakShuntCommand = CMU_CMD_HFXOPEAKDETSTART /**< Run peak and shunt current optimization. */ | CMU_CMD_HFXOSHUNTOPTSTART, #endif } CMU_HFXOTuningMode_TypeDef; #endif #if defined(_CMU_CTRL_LFXOBOOST_MASK) /** LFXO Boost values. */ typedef enum { cmuLfxoBoost70 = 0x0, cmuLfxoBoost100 = 0x2, #if defined(_EMU_AUXCTRL_REDLFXOBOOST_MASK) cmuLfxoBoost70Reduced = 0x1, cmuLfxoBoost100Reduced = 0x3, #endif } CMU_LFXOBoost_TypeDef; #endif #if defined(CMU_OSCENCMD_DPLLEN) /** DPLL reference clock selector. */ typedef enum { cmuDPLLClkSel_Hfxo = _CMU_DPLLCTRL_REFSEL_HFXO, /**< HFXO is DPLL reference clock. */ cmuDPLLClkSel_Lfxo = _CMU_DPLLCTRL_REFSEL_LFXO, /**< LFXO is DPLL reference clock. */ cmuDPLLClkSel_Clkin0 = _CMU_DPLLCTRL_REFSEL_CLKIN0 /**< CLKIN0 is DPLL reference clock. */ } CMU_DPLLClkSel_TypeDef; /** DPLL reference clock edge detect selector. */ typedef enum { cmuDPLLEdgeSel_Fall = _CMU_DPLLCTRL_EDGESEL_FALL, /**< Detect falling edge of reference clock. */ cmuDPLLEdgeSel_Rise = _CMU_DPLLCTRL_EDGESEL_RISE /**< Detect rising edge of reference clock. */ } CMU_DPLLEdgeSel_TypeDef; /** DPLL lock mode selector. */ typedef enum { cmuDPLLLockMode_Freq = _CMU_DPLLCTRL_MODE_FREQLL, /**< Frequency lock mode. */ cmuDPLLLockMode_Phase = _CMU_DPLLCTRL_MODE_PHASELL /**< Phase lock mode. */ } CMU_DPLLLockMode_TypeDef; #endif // CMU_OSCENCMD_DPLLEN /******************************************************************************* ******************************* STRUCTS *********************************** ******************************************************************************/ /** LFXO initialization structure. Initialization values should be obtained from a configuration tool, app note, or xtal data sheet. */ typedef struct { #if defined(_CMU_LFXOCTRL_MASK) uint8_t ctune; /**< CTUNE (load capacitance) value */ uint8_t gain; /**< Gain/max startup margin */ #else CMU_LFXOBoost_TypeDef boost; /**< LFXO boost */ #endif uint8_t timeout; /**< Startup delay */ CMU_OscMode_TypeDef mode; /**< Oscillator mode */ } CMU_LFXOInit_TypeDef; #if defined(_CMU_LFXOCTRL_MASK) /** Default LFXO initialization values for platform 2 devices, which contain a * separate LFXOCTRL register. */ #define CMU_LFXOINIT_DEFAULT \ { \ _CMU_LFXOCTRL_TUNING_DEFAULT, /* Default CTUNE value, 0 */ \ _CMU_LFXOCTRL_GAIN_DEFAULT, /* Default gain, 2 */ \ _CMU_LFXOCTRL_TIMEOUT_DEFAULT, /* Default start-up delay, 32 K cycles */ \ cmuOscMode_Crystal, /* Crystal oscillator */ \ } #define CMU_LFXOINIT_EXTERNAL_CLOCK \ { \ 0, /* No CTUNE value needed */ \ 0, /* No LFXO startup gain */ \ _CMU_LFXOCTRL_TIMEOUT_2CYCLES, /* Minimal lfxo start-up delay, 2 cycles */ \ cmuOscMode_External, /* External digital clock */ \ } #else /** Default LFXO initialization values for platform 1 devices. */ #define CMU_LFXOINIT_DEFAULT \ { \ cmuLfxoBoost70, \ _CMU_CTRL_LFXOTIMEOUT_DEFAULT, \ cmuOscMode_Crystal, \ } #define CMU_LFXOINIT_EXTERNAL_CLOCK \ { \ cmuLfxoBoost70, \ _CMU_CTRL_LFXOTIMEOUT_8CYCLES, \ cmuOscMode_External, \ } #endif /** HFXO initialization structure. Initialization values should be obtained from a configuration tool, app note, or xtal data sheet. */ typedef struct { #if defined(_SILICON_LABS_32B_SERIES_1) && (_SILICON_LABS_GECKO_INTERNAL_SDID >= 100) uint16_t ctuneStartup; /**< Startup phase CTUNE (load capacitance) value */ uint16_t ctuneSteadyState; /**< Steady-state phase CTUNE (load capacitance) value */ uint16_t xoCoreBiasTrimStartup; /**< Startup XO core bias current trim */ uint16_t xoCoreBiasTrimSteadyState; /**< Steady-state XO core bias current trim */ uint8_t timeoutPeakDetect; /**< Timeout - peak detection */ uint8_t timeoutSteady; /**< Timeout - steady-state */ uint8_t timeoutStartup; /**< Timeout - startup */ #elif defined(_CMU_HFXOCTRL_MASK) bool lowPowerMode; /**< Enable low-power mode */ bool autoStartEm01; /**< @deprecated Use @ref CMU_HFXOAutostartEnable instead. */ bool autoSelEm01; /**< @deprecated Use @ref CMU_HFXOAutostartEnable instead. */ bool autoStartSelOnRacWakeup; /**< @deprecated Use @ref CMU_HFXOAutostartEnable instead. */ uint16_t ctuneStartup; /**< Startup phase CTUNE (load capacitance) value */ uint16_t ctuneSteadyState; /**< Steady-state phase CTUNE (load capacitance) value */ uint8_t regIshSteadyState; /**< Shunt steady-state current */ uint8_t xoCoreBiasTrimStartup; /**< Startup XO core bias current trim */ uint8_t xoCoreBiasTrimSteadyState; /**< Steady-state XO core bias current trim */ uint8_t thresholdPeakDetect; /**< Peak detection threshold */ uint8_t timeoutShuntOptimization; /**< Timeout - shunt optimization */ uint8_t timeoutPeakDetect; /**< Timeout - peak detection */ uint8_t timeoutSteady; /**< Timeout - steady-state */ uint8_t timeoutStartup; /**< Timeout - startup */ #else uint8_t boost; /**< HFXO Boost, 0=50% 1=70%, 2=80%, 3=100% */ uint8_t timeout; /**< Startup delay */ bool glitchDetector; /**< Enable/disable glitch detector */ #endif CMU_OscMode_TypeDef mode; /**< Oscillator mode */ } CMU_HFXOInit_TypeDef; #if defined(_SILICON_LABS_32B_SERIES_1) && (_SILICON_LABS_GECKO_INTERNAL_SDID >= 100) #define CMU_HFXOINIT_DEFAULT \ { \ _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT, \ _CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT, \ _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT, \ _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT, \ _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT, \ _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT, \ _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT, \ cmuOscMode_Crystal, \ } #define CMU_HFXOINIT_EXTERNAL_CLOCK \ { \ _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT, \ _CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT, \ _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT, \ _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT, \ _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT, \ _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT, \ _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT, \ cmuOscMode_External, \ } #elif defined(_CMU_HFXOCTRL_MASK) /** * Default HFXO initialization values for Platform 2 devices, which contain a * separate HFXOCTRL register. */ #if defined(_EFR_DEVICE) #define CMU_HFXOINIT_DEFAULT \ { \ false, /* Low-noise mode for EFR32 */ \ false, /* @deprecated no longer in use */ \ false, /* @deprecated no longer in use */ \ false, /* @deprecated no longer in use */ \ _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT, \ _CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT, \ 0xA, /* Default Shunt steady-state current */ \ 0x20, /* Matching errata fix in @ref CHIP_Init() */ \ 0x7, /* Recommended steady-state XO core bias current */ \ 0x6, /* Recommended peak detection threshold */ \ 0x2, /* Recommended shunt optimization timeout */ \ 0xA, /* Recommended peak detection timeout */ \ 0x4, /* Recommended steady timeout */ \ _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT, \ cmuOscMode_Crystal, \ } #else /* EFM32 device */ #define CMU_HFXOINIT_DEFAULT \ { \ true, /* Low-power mode for EFM32 */ \ false, /* @deprecated no longer in use */ \ false, /* @deprecated no longer in use */ \ false, /* @deprecated no longer in use */ \ _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT, \ _CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT, \ 0xA, /* Default shunt steady-state current */ \ 0x20, /* Matching errata fix in @ref CHIP_Init() */ \ 0x7, /* Recommended steady-state osc core bias current */ \ 0x6, /* Recommended peak detection threshold */ \ 0x2, /* Recommended shunt optimization timeout */ \ 0xA, /* Recommended peak detection timeout */ \ 0x4, /* Recommended steady timeout */ \ _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT, \ cmuOscMode_Crystal, \ } #endif /* _EFR_DEVICE */ #define CMU_HFXOINIT_EXTERNAL_CLOCK \ { \ true, /* Low-power mode */ \ false, /* @deprecated no longer in use */ \ false, /* @deprecated no longer in use */ \ false, /* @deprecated no longer in use */ \ 0, /* Startup CTUNE=0 recommended for external clock */ \ 0, /* Steady CTUNE=0 recommended for external clock */ \ 0xA, /* Default shunt steady-state current */ \ 0, /* Startup IBTRIMXOCORE=0 recommended for external clock */ \ 0, /* Steady IBTRIMXOCORE=0 recommended for external clock */ \ 0x6, /* Recommended peak detection threshold */ \ 0x2, /* Recommended shunt optimization timeout */ \ 0x0, /* Peak-detect not recommended for external clock usage */ \ _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES, /* Minimal steady timeout */ \ _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES, /* Minimal startup timeout */ \ cmuOscMode_External, \ } #else /* _CMU_HFXOCTRL_MASK */ /** * Default HFXO initialization values for Platform 1 devices. */ #define CMU_HFXOINIT_DEFAULT \ { \ _CMU_CTRL_HFXOBOOST_DEFAULT, /* 100% HFXO boost */ \ _CMU_CTRL_HFXOTIMEOUT_DEFAULT, /* 16 K startup delay */ \ false, /* Disable glitch detector */ \ cmuOscMode_Crystal, /* Crystal oscillator */ \ } #define CMU_HFXOINIT_EXTERNAL_CLOCK \ { \ 0, /* Minimal HFXO boost, 50% */ \ _CMU_CTRL_HFXOTIMEOUT_8CYCLES, /* Minimal startup delay, 8 cycles */ \ false, /* Disable glitch detector */ \ cmuOscMode_External, /* External digital clock */ \ } #endif /* _CMU_HFXOCTRL_MASK */ #if defined(CMU_OSCENCMD_DPLLEN) /** DPLL initialization structure. Frequency will be Fref*(N+1)/(M+1). */ typedef struct { uint32_t frequency; /**< PLL frequency value, max 40 MHz. */ uint16_t n; /**< Factor N. 300 <= N <= 4095 */ uint16_t m; /**< Factor M. M <= 4095 */ uint8_t ssInterval; /**< Spread spectrum update interval. */ uint8_t ssAmplitude; /**< Spread spectrum amplitude. */ CMU_DPLLClkSel_TypeDef refClk; /**< Reference clock selector. */ CMU_DPLLEdgeSel_TypeDef edgeSel; /**< Reference clock edge detect selector. */ CMU_DPLLLockMode_TypeDef lockMode; /**< DPLL lock mode selector. */ bool autoRecover; /**< Enable automatic lock recovery. */ } CMU_DPLLInit_TypeDef; /** * DPLL initialization values for 39,998,805 Hz using LFXO as reference * clock, M=2 and N=3661. */ #define CMU_DPLL_LFXO_TO_40MHZ \ { \ 39998805, /* Target frequency. */ \ 3661, /* Factor N. */ \ 2, /* Factor M. */ \ 0, /* No spread spectrum clocking. */ \ 0, /* No spread spectrum clocking. */ \ cmuDPLLClkSel_Lfxo, /* Select LFXO as reference clock. */ \ cmuDPLLEdgeSel_Fall, /* Select falling edge of ref clock. */ \ cmuDPLLLockMode_Freq, /* Use frequency lock mode. */ \ true /* Enable automatic lock recovery. */ \ } #endif // CMU_OSCENCMD_DPLLEN /******************************************************************************* ***************************** PROTOTYPES ********************************** ******************************************************************************/ #if defined(_CMU_AUXHFRCOCTRL_BAND_MASK) CMU_AUXHFRCOBand_TypeDef CMU_AUXHFRCOBandGet(void); void CMU_AUXHFRCOBandSet(CMU_AUXHFRCOBand_TypeDef band); #elif defined(_CMU_AUXHFRCOCTRL_FREQRANGE_MASK) CMU_AUXHFRCOFreq_TypeDef CMU_AUXHFRCOBandGet(void); void CMU_AUXHFRCOBandSet(CMU_AUXHFRCOFreq_TypeDef setFreq); #endif uint32_t CMU_Calibrate(uint32_t HFCycles, CMU_Osc_TypeDef reference); #if defined(_CMU_CALCTRL_UPSEL_MASK) && defined(_CMU_CALCTRL_DOWNSEL_MASK) void CMU_CalibrateConfig(uint32_t downCycles, CMU_Osc_TypeDef downSel, CMU_Osc_TypeDef upSel); #endif uint32_t CMU_CalibrateCountGet(void); void CMU_ClockEnable(CMU_Clock_TypeDef clock, bool enable); CMU_ClkDiv_TypeDef CMU_ClockDivGet(CMU_Clock_TypeDef clock); void CMU_ClockDivSet(CMU_Clock_TypeDef clock, CMU_ClkDiv_TypeDef div); uint32_t CMU_ClockFreqGet(CMU_Clock_TypeDef clock); #if defined(_SILICON_LABS_32B_SERIES_1) void CMU_ClockPrescSet(CMU_Clock_TypeDef clock, CMU_ClkPresc_TypeDef presc); uint32_t CMU_ClockPrescGet(CMU_Clock_TypeDef clock); #endif void CMU_ClockSelectSet(CMU_Clock_TypeDef clock, CMU_Select_TypeDef ref); CMU_Select_TypeDef CMU_ClockSelectGet(CMU_Clock_TypeDef clock); #if defined(CMU_OSCENCMD_DPLLEN) bool CMU_DPLLLock(const CMU_DPLLInit_TypeDef *init); #endif void CMU_FreezeEnable(bool enable); #if defined(_CMU_HFRCOCTRL_BAND_MASK) CMU_HFRCOBand_TypeDef CMU_HFRCOBandGet(void); void CMU_HFRCOBandSet(CMU_HFRCOBand_TypeDef band); #elif defined(_CMU_HFRCOCTRL_FREQRANGE_MASK) CMU_HFRCOFreq_TypeDef CMU_HFRCOBandGet(void); void CMU_HFRCOBandSet(CMU_HFRCOFreq_TypeDef setFreq); #endif #if defined(_CMU_HFRCOCTRL_SUDELAY_MASK) uint32_t CMU_HFRCOStartupDelayGet(void); void CMU_HFRCOStartupDelaySet(uint32_t delay); #endif #if defined(_CMU_USHFRCOCTRL_FREQRANGE_MASK) CMU_USHFRCOFreq_TypeDef CMU_USHFRCOBandGet(void); void CMU_USHFRCOBandSet(CMU_USHFRCOFreq_TypeDef setFreq); uint32_t CMU_USHFRCOFreqGet(void); #endif #if defined(_CMU_HFXOCTRL_AUTOSTARTEM0EM1_MASK) void CMU_HFXOAutostartEnable(uint32_t userSel, bool enEM0EM1Start, bool enEM0EM1StartSel); #endif void CMU_HFXOInit(const CMU_HFXOInit_TypeDef *hfxoInit); uint32_t CMU_LCDClkFDIVGet(void); void CMU_LCDClkFDIVSet(uint32_t div); void CMU_LFXOInit(const CMU_LFXOInit_TypeDef *lfxoInit); void CMU_OscillatorEnable(CMU_Osc_TypeDef osc, bool enable, bool wait); uint32_t CMU_OscillatorTuningGet(CMU_Osc_TypeDef osc); void CMU_OscillatorTuningSet(CMU_Osc_TypeDef osc, uint32_t val); #if defined(_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK) || defined(_CMU_HFXOCTRL_PEAKDETMODE_MASK) bool CMU_OscillatorTuningWait(CMU_Osc_TypeDef osc, CMU_HFXOTuningMode_TypeDef mode); bool CMU_OscillatorTuningOptimize(CMU_Osc_TypeDef osc, CMU_HFXOTuningMode_TypeDef mode, bool wait); #endif #if (_SILICON_LABS_32B_SERIES < 2) bool CMU_PCNTClockExternalGet(unsigned int instance); void CMU_PCNTClockExternalSet(unsigned int instance, bool external); #endif #if defined(_CMU_USHFRCOCONF_BAND_MASK) CMU_USHFRCOBand_TypeDef CMU_USHFRCOBandGet(void); void CMU_USHFRCOBandSet(CMU_USHFRCOBand_TypeDef band); uint32_t CMU_USHFRCOFreqGet(void); #endif void CMU_UpdateWaitStates(uint32_t freq, int vscale); #if defined(CMU_CALCTRL_CONT) /***************************************************************************//** * @brief * Configure continuous calibration mode. * @param[in] enable * If true, enables continuous calibration, if false disables continuous * calibration. ******************************************************************************/ __STATIC_INLINE void CMU_CalibrateCont(bool enable) { BUS_RegBitWrite(&CMU->CALCTRL, _CMU_CALCTRL_CONT_SHIFT, (uint32_t)enable); } #endif /***************************************************************************//** * @brief * Start calibration. * @note * This call is usually invoked after @ref CMU_CalibrateConfig() and possibly * @ref CMU_CalibrateCont(). ******************************************************************************/ __STATIC_INLINE void CMU_CalibrateStart(void) { CMU->CMD = CMU_CMD_CALSTART; } #if defined(CMU_CMD_CALSTOP) /***************************************************************************//** * @brief * Stop the calibration counters. ******************************************************************************/ __STATIC_INLINE void CMU_CalibrateStop(void) { CMU->CMD = CMU_CMD_CALSTOP; } #endif /***************************************************************************//** * @brief * Convert dividend to logarithmic value. It only works for even * numbers equal to 2^n. * * @param[in] div * An unscaled dividend. * * @return * Logarithm of 2, as used by fixed prescalers. ******************************************************************************/ __STATIC_INLINE uint32_t CMU_DivToLog2(CMU_ClkDiv_TypeDef div) { uint32_t log2; /* Fixed 2^n prescalers take argument of 32768 or less. */ EFM_ASSERT((div > 0U) && (div <= 32768U)); /* Count leading zeroes and "reverse" result */ log2 = 31UL - __CLZ(div); return log2; } #if defined(CMU_OSCENCMD_DPLLEN) /***************************************************************************//** * @brief * Unlock DPLL. * @note * HFRCO is not turned off. ******************************************************************************/ __STATIC_INLINE void CMU_DPLLUnlock(void) { CMU->OSCENCMD = CMU_OSCENCMD_DPLLDIS; } #endif /***************************************************************************//** * @brief * Clear one or more pending CMU interrupts. * * @param[in] flags * CMU interrupt sources to clear. ******************************************************************************/ __STATIC_INLINE void CMU_IntClear(uint32_t flags) { CMU->IFC = flags; } /***************************************************************************//** * @brief * Disable one or more CMU interrupts. * * @param[in] flags * CMU interrupt sources to disable. ******************************************************************************/ __STATIC_INLINE void CMU_IntDisable(uint32_t flags) { CMU->IEN &= ~flags; } /***************************************************************************//** * @brief * Enable one or more CMU interrupts. * * @note * Depending on use case, a pending interrupt may already be set prior to * enabling the interrupt. Consider using @ref CMU_IntClear() prior to enabling * if the pending interrupt should be ignored. * * @param[in] flags * CMU interrupt sources to enable. ******************************************************************************/ __STATIC_INLINE void CMU_IntEnable(uint32_t flags) { CMU->IEN |= flags; } /***************************************************************************//** * @brief * Get pending CMU interrupts. * * @return * CMU interrupt sources pending. ******************************************************************************/ __STATIC_INLINE uint32_t CMU_IntGet(void) { return CMU->IF; } /***************************************************************************//** * @brief * Get enabled and pending CMU interrupt flags. * * @details * Useful for handling more interrupt sources in the same interrupt handler. * * @note * This function does not clear event bits. * * @return * Pending and enabled CMU interrupt sources. * The return value is the bitwise AND of * - the enabled interrupt sources in CMU_IEN and * - the pending interrupt flags CMU_IF ******************************************************************************/ __STATIC_INLINE uint32_t CMU_IntGetEnabled(void) { uint32_t ien; ien = CMU->IEN; return CMU->IF & ien; } /**************************************************************************//** * @brief * Set one or more pending CMU interrupts. * * @param[in] flags * CMU interrupt sources to set to pending. *****************************************************************************/ __STATIC_INLINE void CMU_IntSet(uint32_t flags) { CMU->IFS = flags; } /***************************************************************************//** * @brief * Lock the CMU to protect some of its registers against unintended * modification. * * @details * See the reference manual for CMU registers that will be * locked. * * @note * If locking the CMU registers, they must be unlocked prior to using any * CMU API functions modifying CMU registers protected by the lock. ******************************************************************************/ __STATIC_INLINE void CMU_Lock(void) { CMU->LOCK = CMU_LOCK_LOCKKEY_LOCK; } /***************************************************************************//** * @brief * Convert logarithm of 2 prescaler to division factor. * * @param[in] log2 * Logarithm of 2, as used by fixed prescalers. * * @return * Dividend. ******************************************************************************/ __STATIC_INLINE uint32_t CMU_Log2ToDiv(uint32_t log2) { EFM_ASSERT(log2 < 32U); return 1UL << log2; } #if defined(_SILICON_LABS_32B_SERIES_1) /***************************************************************************//** * @brief * Convert prescaler dividend to a logarithmic value. It only works for even * numbers equal to 2^n. * * @param[in] presc * An unscaled dividend (dividend = presc + 1). * * @return * Logarithm of 2, as used by fixed 2^n prescalers. ******************************************************************************/ __STATIC_INLINE uint32_t CMU_PrescToLog2(CMU_ClkPresc_TypeDef presc) { uint32_t log2; /* Integer prescalers take argument less than 32768. */ EFM_ASSERT(presc < 32768U); /* Count leading zeroes and "reverse" result. */ log2 = 31UL - __CLZ(presc + (uint32_t) 1); /* Check that prescaler is a 2^n number. */ EFM_ASSERT(presc == (CMU_Log2ToDiv(log2) - 1U)); return log2; } #endif /***************************************************************************//** * @brief * Unlock the CMU so that writing to locked registers again is possible. ******************************************************************************/ __STATIC_INLINE void CMU_Unlock(void) { CMU->LOCK = CMU_LOCK_LOCKKEY_UNLOCK; } #if defined(_CMU_HFRCOCTRL_FREQRANGE_MASK) /***************************************************************************//** * @brief * Get the current HFRCO frequency. * * @deprecated * A deprecated function. New code should use @ref CMU_HFRCOBandGet(). * * @return * HFRCO frequency. ******************************************************************************/ __STATIC_INLINE CMU_HFRCOFreq_TypeDef CMU_HFRCOFreqGet(void) { return CMU_HFRCOBandGet(); } /***************************************************************************//** * @brief * Set HFRCO calibration for the selected target frequency. * * @deprecated * A deprecated function. New code should use @ref CMU_HFRCOBandSet(). * * @param[in] setFreq * HFRCO frequency to set. ******************************************************************************/ __STATIC_INLINE void CMU_HFRCOFreqSet(CMU_HFRCOFreq_TypeDef setFreq) { CMU_HFRCOBandSet(setFreq); } #endif #if defined(_CMU_AUXHFRCOCTRL_FREQRANGE_MASK) /***************************************************************************//** * @brief * Get the current AUXHFRCO frequency. * * @deprecated * A deprecated function. New code should use @ref CMU_AUXHFRCOBandGet(). * * @return * AUXHFRCO frequency. ******************************************************************************/ __STATIC_INLINE CMU_AUXHFRCOFreq_TypeDef CMU_AUXHFRCOFreqGet(void) { return CMU_AUXHFRCOBandGet(); } /***************************************************************************//** * @brief * Set AUXHFRCO calibration for the selected target frequency. * * @deprecated * A deprecated function. New code should use @ref CMU_AUXHFRCOBandSet(). * * @param[in] setFreq * AUXHFRCO frequency to set. ******************************************************************************/ __STATIC_INLINE void CMU_AUXHFRCOFreqSet(CMU_AUXHFRCOFreq_TypeDef setFreq) { CMU_AUXHFRCOBandSet(setFreq); } #endif #endif // defined(_SILICON_LABS_32B_SERIES_2) /** @} (end addtogroup CMU) */ /** @} (end addtogroup emlib) */ #ifdef __cplusplus } #endif #endif /* defined(CMU_PRESENT) */ #endif /* EM_CMU_H */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/emlib/inc/em_common.h.
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/***************************************************************************//** * @file * @brief General purpose utilities. * @version 5.7.0 ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * SPDX-License-Identifier: Zlib * * The licensor of this software is Silicon Laboratories Inc. * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be * appreciated but is not required. * 2. Altered source versions must be plainly marked as such, and must not be * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * ******************************************************************************/ #ifndef EM_COMMON_H #define EM_COMMON_H #include "em_device.h" #include <stdbool.h> #ifdef __cplusplus extern "C" { #endif /***************************************************************************//** * @defgroup emlib EMLIB * @brief Low-level peripheral library * @details * EMLIB is a low-level peripheral support library that provides a unified API for * all EFM32, EZR32 and EFR32 MCUs and SoCs from Silicon Laboratories. * * EMLIB modules are provided for all peripherals and core features. The library * implements no interrupt handlers. Static data, critical sections and module * interdependencies are kept at a minimum. * * @note * EMLIB functions assert on error if DEBUG_EFM is defined. See @ref ASSERT * for more information on error handling and default assertion and how to * implement a custom handler. * * @n * @note * The RAIL library provides a generic interface for all Silicon Labs radio features. * RAIL documentation is available from Simplicity Studio. * * @{ ******************************************************************************/ /***************************************************************************//** * @addtogroup COMMON * @brief General purpose utilities and cross-compiler support. * @details * This SDK supports the following compilers/IDEs: * @li Simplicity Studio * @li IAR Embedded Workbench * @li Keil µVision IDE * @li Plain armgcc * * Certain compiler features such as alignment is implemented differently in the tools. * Therefore, macros such as @ref SL_ALIGN are provided to enable compiler independent * code. * * @note RAM code macros are implemented in a separate module @ref RAMFUNC. * Cross-compiler RAM code support needs extended documentation and it is therefore * implemented as a separate module. * * @{ ******************************************************************************/ /** @brief Round n up to closest interval of i. */ #define SL_CEILING(n, i) ((((n) + (i) - 1U) / (i)) * (i)) /** @brief Round n down to closest interval of i. */ #define SL_FLOOR(n, i) ((n / i) * i)) /** @brief Stringify X */ #define STRINGIZE(X) #X #if !defined(__GNUC__) /* Not GCC compilers */ /** @brief Macro for getting minimum value. */ #define SL_MIN(a, b) ((a) < (b) ? (a) : (b)) /** @brief Macro for getting maximum value. */ #define SL_MAX(a, b) ((a) > (b) ? (a) : (b)) /** @brief Macros for handling packed structs. */ #define SL_PACK_START(X) _Pragma(STRINGIZE(pack(X))) #define SL_PACK_END() _Pragma("pack()") #define SL_ATTRIBUTE_PACKED #if defined(__CC_ARM) /** @brief MDK-ARM compiler: Macros for handling aligned structs. */ #define SL_ALIGN(X) __align(X) /** MDK-ARM compiler: Macro for handling weak symbols. */ #define SL_WEAK __attribute__ ((weak)) /** MDK-ARM compiler: Macro for handling non-returning functions. */ #define SL_NORETURN __attribute__ ((noreturn)) /** MDK-ARM compiler: Macro for handling section placement */ #define SL_ATTRIBUTE_SECTION(X) __attribute__ ((section(X))) #endif #if defined(__ICCARM__) #if (__VER__ >= 8000000) /** @brief Obsoleted macro from version 8.00 and on . */ #define _STD_BEGIN /** @brief Obsoleted macro from version 8.00 and on . */ #define _STD_END #endif /** @brief IAR Embedded Workbench: Macros for handling aligned structs. */ #define SL_ALIGN(X) _Pragma(STRINGIZE(data_alignment = X)) /** @brief IAR Embedded Workbench: Macros for handling weak symbols. */ #define SL_WEAK __weak /** @brief IAR Embedded Workbench: Macro for handling non-returning functions. */ #define SL_NORETURN __noreturn /* *INDENT-OFF* */ /** IAR Embedded Workbench: Macro for handling section placement */ #define SL_ATTRIBUTE_SECTION(X) @ X #endif /* *INDENT-ON* */ #define SL_ATTRIBUTE_ALIGN(X) /** @brief Macro for notifying the compiler of an intended * switch case fallthrough. */ #define SL_FALLTHROUGH #else // !defined(__GNUC__) /* GCC compilers */ /** @brief A macro for getting the minimum value. No sideeffects, a and b are evaluated one time only. */ #define SL_MIN(a, b) __extension__({ __typeof__(a)_a = (a); __typeof__(b)_b = (b); _a < _b ? _a : _b; }) /** @brief A macro for getting the maximum value. No sideeffects, a and b are evaluated one time only. */ #define SL_MAX(a, b) __extension__({ __typeof__(a)_a = (a); __typeof__(b)_b = (b); _a > _b ? _a : _b; }) /** @brief A GCC style macro for handling packed structures. */ #define SL_ATTRIBUTE_PACKED __attribute__ ((packed)) /** @brief A macro for handling packed structures. * @n Use this macro before the structure definition. * @n X denotes the maximum alignment of structure members. X is not supported with * GCC. GCC always uses 1 byte maximum alignment. */ #define SL_PACK_START(x) /** @brief A macro for handling packed structures. * @n Use this macro after the structure definition. * @n With GCC, add SL_ATTRIBUTE_PACKED after the closing curly braces of the structure * definition. */ #define SL_PACK_END() /** @brief GCC style macro for aligning a variable. */ #define SL_ATTRIBUTE_ALIGN(X) __attribute__ ((aligned(X))) /** @brief A macro for aligning a variable. * @n Use this macro before the variable definition. * @n X denotes the storage alignment value in bytes. * @n To be GCC-compatible, use SL_ATTRIBUTE_ALIGN(X) before the semicolon on normal * variables. Use SL_ATTRIBUTE_ALIGN(X) before the opening curly brace on structure variables. */ #define SL_ALIGN(X) /** @brief A macro for defining a weak symbol. */ #define SL_WEAK __attribute__ ((weak)) /** @brief A macro for handling non-returning functions. */ #define SL_NORETURN __attribute__ ((noreturn)) /** A macro for placing a variable in a section. * @n Use this macro after the variable definition, before the equal sign or a semicolon. * @n X denotes the section to place the variable in. */ #define SL_ATTRIBUTE_SECTION(X) __attribute__ ((section(X))) /** @brief A macro for notifying the compiler of an intended * switch case fallthrough. */ #if __GNUC__ >= 7 #define SL_FALLTHROUGH __attribute__ ((fallthrough)); #else #define SL_FALLTHROUGH #endif #endif // !defined(__GNUC__) /***************************************************************************//** * @brief * Count trailing number of zeros. Use CLZ instruction if available. * * @param[in] value * Data value to check for number of trailing zero bits. * * @return * A number of trailing zeros in value. ******************************************************************************/ __STATIC_INLINE uint32_t SL_CTZ(uint32_t value) { #if (__CORTEX_M >= 3) return __CLZ(__RBIT(value)); #else uint32_t zeros; for (zeros = 0; (zeros < 32) && ((value & 0x1) == 0); zeros++, value >>= 1) { ; } return zeros; #endif } /* Deprecated function. New code should use @ref SL_CTZ. */ __STATIC_INLINE uint32_t EFM32_CTZ(uint32_t value) { return SL_CTZ(value); } /***************************************************************************//** * @brief * Reverse the bits. Use the RBIT instruction if available, else process. * * @param[in] value * Data value to reverse. * * @return * A reversed value. ******************************************************************************/ __STATIC_INLINE uint32_t SL_RBIT(uint32_t value) { uint32_t result; #if (__CORTEX_M >= 0x03U) result = __RBIT(value); #else int32_t s = 4 * 8 - 1; result = value; for (value >>= 1U; value; value >>= 1U) { result <<= 1U; result |= value & 1U; s--; } result <<= s; #endif return result; } /***************************************************************************//** * @brief * Reverse the bits. Use the RBIT instruction if available, else process. * * @param[in] value * 16-bit data value to reverse. * * @return * A 16-bit reversed value. ******************************************************************************/ __STATIC_INLINE uint32_t SL_RBIT16(uint32_t value) { return SL_RBIT(value) >> 16; } /** @} (end addtogroup COMMON) */ /** @} (end addtogroup emlib) */ #ifdef __cplusplus } #endif #endif /* EM_COMMON_H */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/emlib/inc/em_core.h.
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/***************************************************************************//** * @file * @brief Core interrupt handling API * @version 5.7.0 ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * SPDX-License-Identifier: Zlib * * The licensor of this software is Silicon Laboratories Inc. * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be * appreciated but is not required. * 2. Altered source versions must be plainly marked as such, and must not be * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * ******************************************************************************/ #ifndef EM_CORE_H #define EM_CORE_H #include "em_device.h" #include "em_common.h" #include <stdbool.h> /***************************************************************************//** * @addtogroup emlib * @{ ******************************************************************************/ /***************************************************************************//** * @addtogroup CORE * @{ ******************************************************************************/ /******************************************************************************* ******************************* DEFINES *********************************** ******************************************************************************/ /** Use PRIMASK register to disable interrupts in ATOMIC sections. */ #define CORE_ATOMIC_METHOD_PRIMASK 0 /** Use BASEPRI register to disable interrupts in ATOMIC sections. */ #define CORE_ATOMIC_METHOD_BASEPRI 1 /** Number of words in a NVIC mask set. */ #define CORE_NVIC_REG_WORDS ((EXT_IRQ_COUNT + 31) / 32) /** Number of entries in a default interrupt vector table. */ #define CORE_DEFAULT_VECTOR_TABLE_ENTRIES (EXT_IRQ_COUNT + 16) // Compile time sanity check. #if (CORE_NVIC_REG_WORDS > 3) #error "em_core: Unexpected NVIC external interrupt count." #endif #ifdef __cplusplus extern "C" { #endif /******************************************************************************* ************************ MACRO API *************************************** ******************************************************************************/ // // CRITICAL section macro API. // /** Allocate storage for PRIMASK or BASEPRI value for use by * CORE_ENTER/EXIT_ATOMIC() and CORE_ENTER/EXIT_CRITICAL() macros. */ #define CORE_DECLARE_IRQ_STATE CORE_irqState_t irqState /** CRITICAL style interrupt disable. */ #define CORE_CRITICAL_IRQ_DISABLE() CORE_CriticalDisableIrq() /** CRITICAL style interrupt enable. */ #define CORE_CRITICAL_IRQ_ENABLE() CORE_CriticalEnableIrq() /** Convenience macro for implementing a CRITICAL section. */ #define CORE_CRITICAL_SECTION(yourcode) \ { \ CORE_DECLARE_IRQ_STATE; \ CORE_ENTER_CRITICAL(); \ { \ yourcode \ } \ CORE_EXIT_CRITICAL(); \ } /** Enter CRITICAL section. Assumes that a @ref CORE_DECLARE_IRQ_STATE exist in * scope. */ #define CORE_ENTER_CRITICAL() irqState = CORE_EnterCritical() /** Exit CRITICAL section. Assumes that a @ref CORE_DECLARE_IRQ_STATE exist in * scope. */ #define CORE_EXIT_CRITICAL() CORE_ExitCritical(irqState) /** CRITICAL style yield. */ #define CORE_YIELD_CRITICAL() CORE_YieldCritical() // // ATOMIC section macro API. // /** ATOMIC style interrupt disable. */ #define CORE_ATOMIC_IRQ_DISABLE() CORE_AtomicDisableIrq() /** ATOMIC style interrupt enable. */ #define CORE_ATOMIC_IRQ_ENABLE() CORE_AtomicEnableIrq() /** Convenience macro for implementing an ATOMIC section. */ #define CORE_ATOMIC_SECTION(yourcode) \ { \ CORE_DECLARE_IRQ_STATE; \ CORE_ENTER_ATOMIC(); \ { \ yourcode \ } \ CORE_EXIT_ATOMIC(); \ } /** Enter ATOMIC section. Assumes that a @ref CORE_DECLARE_IRQ_STATE exist in * scope. */ #define CORE_ENTER_ATOMIC() irqState = CORE_EnterAtomic() /** Exit ATOMIC section. Assumes that a @ref CORE_DECLARE_IRQ_STATE exist in * scope. */ #define CORE_EXIT_ATOMIC() CORE_ExitAtomic(irqState) /** ATOMIC style yield. */ #define CORE_YIELD_ATOMIC() CORE_YieldAtomic() // // NVIC mask section macro API. // /** Allocate storage for NVIC interrupt masks for use by * CORE_ENTER/EXIT_NVIC() macros. */ #define CORE_DECLARE_NVIC_STATE CORE_nvicMask_t nvicState /** Allocate storage for NVIC interrupt masks. * @param[in] x * The storage variable name to use.*/ #define CORE_DECLARE_NVIC_MASK(x) CORE_nvicMask_t x /** Allocate storage for and zero initialize NVIC interrupt mask. * @param[in] x * The storage variable name to use.*/ #define CORE_DECLARE_NVIC_ZEROMASK(x) CORE_nvicMask_t x = { { 0 } } /** NVIC mask style interrupt disable. * @param[in] mask * Mask specifying which NVIC interrupts to disable. */ #define CORE_NVIC_DISABLE(mask) CORE_NvicDisableMask(mask) /** NVIC mask style interrupt enable. * @param[in] mask * Mask specifying which NVIC interrupts to enable. */ #define CORE_NVIC_ENABLE(mask) CORE_NvicEnableMask(mask) /** Convenience macro for implementing a NVIC mask section. * @param[in] mask * Mask specifying which NVIC interrupts to disable within the section. * @param[in] yourcode * The code for the section. */ #define CORE_NVIC_SECTION(mask, yourcode) \ { \ CORE_DECLARE_NVIC_STATE; \ CORE_ENTER_NVIC(mask); \ { \ yourcode \ } \ CORE_EXIT_NVIC(); \ } /** Enter NVIC mask section. Assumes that a @ref CORE_DECLARE_NVIC_STATE exist * in scope. * @param[in] disable * Mask specifying which NVIC interrupts to disable within the section. */ #define CORE_ENTER_NVIC(disable) CORE_EnterNvicMask(&nvicState, disable) /** Exit NVIC mask section. Assumes that a @ref CORE_DECLARE_NVIC_STATE exist * in scope. */ #define CORE_EXIT_NVIC() CORE_NvicEnableMask(&nvicState) /** NVIC maks style yield. * @param[in] enable * Mask specifying which NVIC interrupts to briefly enable. */ #define CORE_YIELD_NVIC(enable) CORE_YieldNvicMask(enable) // // Miscellaneous macros. // /** Check if IRQ is disabled. */ #define CORE_IRQ_DISABLED() CORE_IrqIsDisabled() /** Check if inside an IRQ handler. */ #define CORE_IN_IRQ_CONTEXT() CORE_InIrqContext() /******************************************************************************* ************************* TYPEDEFS **************************************** ******************************************************************************/ /** Storage for PRIMASK or BASEPRI value. */ typedef uint32_t CORE_irqState_t; /** Storage for NVIC interrupt masks. */ typedef struct { uint32_t a[CORE_NVIC_REG_WORDS]; /*!< Array of NVIC mask words. */ } CORE_nvicMask_t; /******************************************************************************* ***************************** PROTOTYPES ********************************** ******************************************************************************/ void CORE_CriticalDisableIrq(void); void CORE_CriticalEnableIrq(void); void CORE_ExitCritical(CORE_irqState_t irqState); void CORE_YieldCritical(void); CORE_irqState_t CORE_EnterCritical(void); void CORE_AtomicDisableIrq(void); void CORE_AtomicEnableIrq(void); void CORE_ExitAtomic(CORE_irqState_t irqState); void CORE_YieldAtomic(void); CORE_irqState_t CORE_EnterAtomic(void); bool CORE_InIrqContext(void); bool CORE_IrqIsBlocked(IRQn_Type irqN); bool CORE_IrqIsDisabled(void); void CORE_GetNvicEnabledMask(CORE_nvicMask_t *mask); bool CORE_GetNvicMaskDisableState(const CORE_nvicMask_t *mask); void CORE_EnterNvicMask(CORE_nvicMask_t *nvicState, const CORE_nvicMask_t *disable); void CORE_NvicDisableMask(const CORE_nvicMask_t *disable); void CORE_NvicEnableMask(const CORE_nvicMask_t *enable); void CORE_YieldNvicMask(const CORE_nvicMask_t *enable); void CORE_NvicMaskSetIRQ(IRQn_Type irqN, CORE_nvicMask_t *mask); void CORE_NvicMaskClearIRQ(IRQn_Type irqN, CORE_nvicMask_t *mask); bool CORE_NvicIRQDisabled(IRQn_Type irqN); void *CORE_GetNvicRamTableHandler(IRQn_Type irqN); void CORE_SetNvicRamTableHandler(IRQn_Type irqN, void *handler); void CORE_InitNvicVectorTable(uint32_t *sourceTable, uint32_t sourceSize, uint32_t *targetTable, uint32_t targetSize, void *defaultHandler, bool overwriteActive); #ifdef __cplusplus } #endif /** @} (end addtogroup CORE) */ /** @} (end addtogroup emlib) */ #endif /* EM_CORE_H */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/emlib/inc/em_cryotimer.h.
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/***************************************************************************//** * @file * @brief Ultra Low Energy Timer/Counter (CRYOTIMER) peripheral API * @version 5.7.0 ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * SPDX-License-Identifier: Zlib * * The licensor of this software is Silicon Laboratories Inc. * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be * appreciated but is not required. * 2. Altered source versions must be plainly marked as such, and must not be * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * ******************************************************************************/ #ifndef EM_CRYOTIMER_H #define EM_CRYOTIMER_H #include <stdbool.h> #include "em_device.h" #include "em_bus.h" #if defined(CRYOTIMER_PRESENT) && (CRYOTIMER_COUNT == 1) #ifdef __cplusplus extern "C" { #endif /***************************************************************************//** * @addtogroup emlib * @{ ******************************************************************************/ /***************************************************************************//** * @addtogroup CRYOTIMER * @brief Ultra Low Energy Timer/Counter (CRYOTIMER) Peripheral API * * @details * The CRYOTIMER is a 32 bit counter which operates on a low-frequency * oscillator and is capable of running in all Energy Modes. It can provide * periodic wakeup events and PRS signals which can be used to wake up * peripherals from any energy mode. The CRYOTIMER provides a very wide range * of periods for the interrupts facilitating flexible ultra-low energy * operation. Because of its simplicity, the CRYOTIMER is a lower energy * solution for periodically waking up the MCU compared to the RTCC. * * To configure the CRYOTIMER, call the @ref CRYOTIMER_Init function. * This function will configure the CRYOTIMER peripheral according to the * user configuration. * * @details * When using the CRYOTIMER, choose which oscillator to use * as the CRYOTIMER clock. The CRYOTIMER supports 3 low-frequency clocks * LFXO, LFRCO, and ULFRCO. The oscillator that is chosen must be * enabled and ready before calling this @ref CRYOTIMER_Init function. * See @ref CMU_OscillatorEnable for details of how to enable and wait for an * oscillator to become ready. Note that ULFRCO is always ready while LFRCO * @ref cmuOsc_LFRCO and LFXO @ref cmuOsc_LFXO must be enabled by the user. * * @details * Note that the only oscillator which is running in EM3 is ULFRCO. Keep this * in mind when choosing which oscillator to use for the CRYOTIMER. * * This example shows how to use the CRYOTIMER to generate an interrupt * at a configurable period. * * @include em_cryotimer_period.c * * @details * To use the CRYOTIMER in EM4, enable EM4 wakeup in the * CRYOTIMER. This can be done either in the @ref CRYOTIMER_Init_TypeDef * structure when initializing the CRYOTIMER or at a later time by using * @ref CRYOTIMER_EM4WakeupEnable. * * Note that when using the CRYOTIMER to wake up from EM4, the application has * the responsibility to clear the wakeup event. This is done by calling * @ref CRYOTIMER_IntClear. If the user does not clear the wakeup event, * the wakeup event will stay pending and will cause an immediate wakeup the * next time the application attempts to enter EM4. * * This example shows how to use the CRYOTIMER to wake up from EM4 after * a configurable amount of time. * * @include em_cryotimer_em4.c * * @details * All the low frequency oscillators can be used in EM4, however, the * oscillator that is used must be be configured to be retained when going * into EM4. This can be configured by using functions in the @ref EMU module. * See @ref EMU_EM4Init and @ref EMU_EM4Init_TypeDef. If an oscillator is * retained in EM4, the user is also responsible for unlatching the retained * configuration on a wakeup from EM4. * * @{ ******************************************************************************/ /******************************************************************************* ********************************* ENUM ************************************ ******************************************************************************/ /** Prescaler selection. */ typedef enum { cryotimerPresc_1 = _CRYOTIMER_CTRL_PRESC_DIV1, /**< Divide clock by 1. */ cryotimerPresc_2 = _CRYOTIMER_CTRL_PRESC_DIV2, /**< Divide clock by 2. */ cryotimerPresc_4 = _CRYOTIMER_CTRL_PRESC_DIV4, /**< Divide clock by 4. */ cryotimerPresc_8 = _CRYOTIMER_CTRL_PRESC_DIV8, /**< Divide clock by 8. */ cryotimerPresc_16 = _CRYOTIMER_CTRL_PRESC_DIV16, /**< Divide clock by 16. */ cryotimerPresc_32 = _CRYOTIMER_CTRL_PRESC_DIV32, /**< Divide clock by 32. */ cryotimerPresc_64 = _CRYOTIMER_CTRL_PRESC_DIV64, /**< Divide clock by 64. */ cryotimerPresc_128 = _CRYOTIMER_CTRL_PRESC_DIV128, /**< Divide clock by 128. */ } CRYOTIMER_Presc_TypeDef; /** Low frequency oscillator selection. */ typedef enum { cryotimerOscLFRCO = _CRYOTIMER_CTRL_OSCSEL_LFRCO, /**< Select Low-frequency RC Oscillator. */ cryotimerOscLFXO = _CRYOTIMER_CTRL_OSCSEL_LFXO, /**< Select Low-frequency Crystal Oscillator. */ cryotimerOscULFRCO = _CRYOTIMER_CTRL_OSCSEL_ULFRCO, /**< Select Ultra Low Frequency RC Oscillator. */ } CRYOTIMER_Osc_TypeDef; /** Period selection value */ typedef enum { cryotimerPeriod_1 = 0, /**< Wakeup event after every Pre-scaled clock cycle. */ cryotimerPeriod_2 = 1, /**< Wakeup event after 2 Pre-scaled clock cycles. */ cryotimerPeriod_4 = 2, /**< Wakeup event after 4 Pre-scaled clock cycles. */ cryotimerPeriod_8 = 3, /**< Wakeup event after 8 Pre-scaled clock cycles. */ cryotimerPeriod_16 = 4, /**< Wakeup event after 16 Pre-scaled clock cycles. */ cryotimerPeriod_32 = 5, /**< Wakeup event after 32 Pre-scaled clock cycles. */ cryotimerPeriod_64 = 6, /**< Wakeup event after 64 Pre-scaled clock cycles. */ cryotimerPeriod_128 = 7, /**< Wakeup event after 128 Pre-scaled clock cycles. */ cryotimerPeriod_256 = 8, /**< Wakeup event after 256 Pre-scaled clock cycles. */ cryotimerPeriod_512 = 9, /**< Wakeup event after 512 Pre-scaled clock cycles. */ cryotimerPeriod_1k = 10, /**< Wakeup event after 1k Pre-scaled clock cycles. */ cryotimerPeriod_2k = 11, /**< Wakeup event after 2k Pre-scaled clock cycles. */ cryotimerPeriod_4k = 12, /**< Wakeup event after 4k Pre-scaled clock cycles. */ cryotimerPeriod_8k = 13, /**< Wakeup event after 8k Pre-scaled clock cycles. */ cryotimerPeriod_16k = 14, /**< Wakeup event after 16k Pre-scaled clock cycles. */ cryotimerPeriod_32k = 15, /**< Wakeup event after 32k Pre-scaled clock cycles. */ cryotimerPeriod_64k = 16, /**< Wakeup event after 64k Pre-scaled clock cycles. */ cryotimerPeriod_128k = 17, /**< Wakeup event after 128k Pre-scaled clock cycles. */ cryotimerPeriod_256k = 18, /**< Wakeup event after 256k Pre-scaled clock cycles. */ cryotimerPeriod_512k = 19, /**< Wakeup event after 512k Pre-scaled clock cycles. */ cryotimerPeriod_1m = 20, /**< Wakeup event after 1m Pre-scaled clock cycles. */ cryotimerPeriod_2m = 21, /**< Wakeup event after 2m Pre-scaled clock cycles. */ cryotimerPeriod_4m = 22, /**< Wakeup event after 4m Pre-scaled clock cycles. */ cryotimerPeriod_8m = 23, /**< Wakeup event after 8m Pre-scaled clock cycles. */ cryotimerPeriod_16m = 24, /**< Wakeup event after 16m Pre-scaled clock cycles. */ cryotimerPeriod_32m = 25, /**< Wakeup event after 32m Pre-scaled clock cycles. */ cryotimerPeriod_64m = 26, /**< Wakeup event after 64m Pre-scaled clock cycles. */ cryotimerPeriod_128m = 27, /**< Wakeup event after 128m Pre-scaled clock cycles. */ cryotimerPeriod_256m = 28, /**< Wakeup event after 256m Pre-scaled clock cycles. */ cryotimerPeriod_512m = 29, /**< Wakeup event after 512m Pre-scaled clock cycles. */ cryotimerPeriod_1024m = 30, /**< Wakeup event after 1024m Pre-scaled clock cycles. */ cryotimerPeriod_2048m = 31, /**< Wakeup event after 2048m Pre-scaled clock cycles. */ cryotimerPeriod_4096m = 32, /**< Wakeup event after 4096m Pre-scaled clock cycles. */ } CRYOTIMER_Period_TypeDef; /******************************************************************************* ******************************* STRUCTURES *********************************** ******************************************************************************/ /** CRYOTIMER initialization structure. */ typedef struct { /** Enable/disable counting when initialization is complete. */ bool enable; /** Enable/disable timer counting during debug halt. */ bool debugRun; /** Enable/disable EM4 Wakeup. */ bool em4Wakeup; /** Select the oscillator for the CRYOTIMER. */ CRYOTIMER_Osc_TypeDef osc; /** Prescaler. */ CRYOTIMER_Presc_TypeDef presc; /** A period between a wakeup event/interrupt. */ CRYOTIMER_Period_TypeDef period; } CRYOTIMER_Init_TypeDef; /******************************************************************************* ******************************* DEFINES *********************************** ******************************************************************************/ /** Default CRYOTIMER init structure. */ #define CRYOTIMER_INIT_DEFAULT \ { \ true, /* Start counting when the initialization is done. */ \ false, /* Disable CRYOTIMER during debug halt. */ \ false, /* Disable EM4 wakeup. */ \ cryotimerOscLFRCO, /* Select Low Frequency RC Oscillator. */ \ cryotimerPresc_1, /* LF Oscillator frequency undivided. */ \ cryotimerPeriod_4096m, /* Wakeup event after 4096 M pre-scaled clock cycles. */ \ } /******************************************************************************* ***************************** PROTOTYPES ********************************** ******************************************************************************/ /***************************************************************************//** * @brief * Clear the CRYOTIMER period interrupt. * * @param[in] flags * CRYOTIMER interrupt sources to clear. Use @ref CRYOTIMER_IFC_PERIOD. ******************************************************************************/ __STATIC_INLINE void CRYOTIMER_IntClear(uint32_t flags) { CRYOTIMER->IFC = flags & _CRYOTIMER_IFC_MASK; } /***************************************************************************//** * @brief * Get the CRYOTIMER interrupt flag. * * @note * This function does not clear event bits. * * @return * Pending CRYOTIMER interrupt sources. The only interrupt source available * for the CRYOTIMER is @ref CRYOTIMER_IF_PERIOD. ******************************************************************************/ __STATIC_INLINE uint32_t CRYOTIMER_IntGet(void) { return CRYOTIMER->IF; } /***************************************************************************//** * @brief * Get enabled and pending CRYOTIMER interrupt flags. * Useful for handling more interrupt sources in the same interrupt handler. * * @note * This function does not clear interrupt flags. * * @return * Pending and enabled CRYOTIMER interrupt sources. * The return value is the bitwise AND of * - the enabled interrupt sources in CRYOTIMER_IEN and * - the pending interrupt flags CRYOTIMER_IF ******************************************************************************/ __STATIC_INLINE uint32_t CRYOTIMER_IntGetEnabled(void) { uint32_t ien; ien = CRYOTIMER->IEN & _CRYOTIMER_IEN_MASK; return CRYOTIMER->IF & ien; } /***************************************************************************//** * @brief * Enable one or more CRYOTIMER interrupts. * * @param[in] flags * CRYOTIMER interrupt sources to enable. Use @ref CRYOTIMER_IEN_PERIOD. ******************************************************************************/ __STATIC_INLINE void CRYOTIMER_IntEnable(uint32_t flags) { CRYOTIMER->IEN |= (flags & _CRYOTIMER_IEN_MASK); } /***************************************************************************//** * @brief * Disable one or more CRYOTIMER interrupts. * * @param[in] flags * CRYOTIMER interrupt sources to disable. Use @ref CRYOTIMER_IEN_PERIOD. ******************************************************************************/ __STATIC_INLINE void CRYOTIMER_IntDisable(uint32_t flags) { CRYOTIMER->IEN &= ~(flags & _CRYOTIMER_IEN_MASK); } /***************************************************************************//** * @brief * Set the CRYOTIMER period interrupt flag. * * @note * Writes 1 to the interrupt flag set register. * * @param[in] flags * CRYOTIMER interrupt sources to set to pending. Use * @ref CRYOTIMER_IFS_PERIOD. ******************************************************************************/ __STATIC_INLINE void CRYOTIMER_IntSet(uint32_t flags) { CRYOTIMER->IFS = flags & _CRYOTIMER_IFS_MASK; } /***************************************************************************//** * @brief * Set the CRYOTIMER period select. * * @note * Sets the duration between the interrupts/wakeup events based on * the pre-scaled clock. * * @param[in] period * 2^period is the number of clock cycles before a wakeup event or * interrupt is triggered. The CRYOTIMER_Periodsel_TypeDef enumeration can * be used a convenience type when calling this function. ******************************************************************************/ __STATIC_INLINE void CRYOTIMER_PeriodSet(uint32_t period) { CRYOTIMER->PERIODSEL = period & _CRYOTIMER_PERIODSEL_MASK; } /***************************************************************************//** * @brief * Get the CRYOTIMER period select value. * * @note * Gets the duration between the interrupts/wakeup events in the * CRYOTIMER. * * @return * Duration between the interrupts/wakeup events. Returns the value * of the PERIODSEL register. The number of clock cycles can be calculated * as the 2^n where n is the return value of this function. ******************************************************************************/ __STATIC_INLINE uint32_t CRYOTIMER_PeriodGet(void) { return CRYOTIMER->PERIODSEL; } /***************************************************************************//** * @brief * Get the CRYOTIMER counter value. * * @return * Returns the current CRYOTIMER counter value. ******************************************************************************/ __STATIC_INLINE uint32_t CRYOTIMER_CounterGet(void) { return CRYOTIMER->CNT; } /***************************************************************************//** * @brief * Enable/disable EM4 wakeup capability. * * @param[in] enable * True to enable EM4 wakeup, false to disable. ******************************************************************************/ __STATIC_INLINE void CRYOTIMER_EM4WakeupEnable(bool enable) { BUS_RegBitWrite((&CRYOTIMER->EM4WUEN), _CRYOTIMER_EM4WUEN_EM4WU_SHIFT, (uint32_t)enable); } /***************************************************************************//** * @brief * Enable/disable the CRYOTIMER. * * @param[in] enable * True to enable the CRYOTIMER, false to disable. ******************************************************************************/ __STATIC_INLINE void CRYOTIMER_Enable(bool enable) { BUS_RegBitWrite((&CRYOTIMER->CTRL), _CRYOTIMER_CTRL_EN_SHIFT, (uint32_t)enable); } void CRYOTIMER_Init(const CRYOTIMER_Init_TypeDef *init); #ifdef __cplusplus } #endif /** @} (end addtogroup CRYOTIMER) */ /** @} (end addtogroup emlib) */ #endif /* defined(CRYOTIMER_PRESENT) && (CRYOTIMER_COUNT == 1) */ #endif /* EM_CRYOTIMER_H */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/emlib/inc/em_crypto.h.
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/***************************************************************************//** * @file * @brief Cryptography accelerator peripheral API * @version 5.7.0 ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * SPDX-License-Identifier: Zlib * * The licensor of this software is Silicon Laboratories Inc. * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be * appreciated but is not required. * 2. Altered source versions must be plainly marked as such, and must not be * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * ******************************************************************************/ #ifndef EM_CRYPTO_H #define EM_CRYPTO_H #include "em_device.h" #if defined(CRYPTO_COUNT) && (CRYPTO_COUNT > 0) #include "em_bus.h" #include <stdbool.h> #ifdef __cplusplus extern "C" { #endif /***************************************************************************//** * @addtogroup emlib * @{ ******************************************************************************/ /***************************************************************************//** * @addtogroup CRYPTO * * @brief Cryptography accelerator peripheral API * * @details * For cryptographic support, users should consider the * crypto APIs of the mbedTLS library provided by Silicon Labs instead of the * interface provided in em_crypto.h. The mbedTLS library provides a much * richer crypto API, including hardware acceleration of several functions. * * The main purpose of em_crypto.h is to implement a thin software interface * for the CRYPTO hardware functions especially for the accelerated APIs of * the mbedTLS library. Additionally em_crypto.h implement the AES API of the * em_aes.h (supported by classic EFM32) for backwards compatibility. The * following list summarizes the em_crypto.h inteface: * @li AES (Advanced Encryption Standard) @ref crypto_aes * @li SHA (Secure Hash Algorithm) @ref crypto_sha * @li Big Integer multiplier @ref crypto_mul * @li Functions for loading data and executing instruction sequences @ref crypto_exec * * @n @section crypto_aes AES * The AES APIs include support for AES-128 and AES-256 with block cipher * modes: * @li CBC - Cipher Block Chaining mode * @li CFB - Cipher Feedback mode * @li CTR - Counter mode * @li ECB - Electronic Code Book mode * @li OFB - Output Feedback mode * * For the AES APIs input/output data (plaintext, ciphertext, key, and so on) are * treated as byte arrays, starting with most significant byte. In other words, 32 bytes * of plaintext (B0...B31) is located in memory in the same order, with B0 at * the lower address and B31 at the higher address. * * Byte arrays must always be a multiple of AES block size, ie. a multiple * of 16. Padding, if required, is done at the end of the byte array. * * Byte arrays should be word (32 bit) aligned for performance * considerations, since the array is accessed with 32 bit access type. * The core MCUs supports unaligned accesses, but with a performance penalty. * * It is possible to specify the same output buffer as input buffer as long * as they point to the same address. In that case the provided input buffer * is replaced with the encrypted/decrypted output. Notice that the buffers * must be exactly overlapping. If partly overlapping, the behavior is * undefined. * * It is up to the user to use a cipher mode according to its requirements * to avoid breaking security. See the specific cipher mode * theory for details. * * References: * @li Wikipedia - Cipher modes, en.wikipedia.org/wiki/Cipher_modes * * @li Recommendation for Block Cipher Modes of Operation, * NIST Special Publication 800-38A, 2001 Edition, * csrc.nist.gov/publications/nistpubs/800-38a/sp800-38a.pdf * * @li Recommendation for Block Cipher Modes of Operation, * csrc.nist.gov/publications/fips/fips180-4/fips-180-4.pdf * * @n @section crypto_sha SHA * The SHA APIs include support for * @li SHA-1 @ref CRYPTO_SHA_1 * @li SHA-256 @ref CRYPTO_SHA_256 * * The SHA-1 implementation is FIPS-180-1 compliant, ref: * @li Wikipedia - SHA-1, en.wikipedia.org/wiki/SHA-1 * @li SHA-1 spec - www.itl.nist.gov/fipspubs/fip180-1.htm * * The SHA-256 implementation is FIPS-180-2 compliant, ref: * @li Wikipedia - SHA-2, en.wikipedia.org/wiki/SHA-2 * @li SHA-2 spec - csrc.nist.gov/publications/fips/fips180-2/fips180-2.pdf * * @n @section crypto_mul CRYPTO_Mul * @ref CRYPTO_Mul is a function for multiplying big integers that are * bigger than the operand size of the MUL instruction, which is 128 bits. * CRYPTO_Mul multiplies all partial operands of the input operands using * MUL to form a resulting number which may be twice the size of * the operands. * * CRPYTO_Mul is typically used by RSA implementations, which perform a * huge amount of multiplication and square operations to * implement modular exponentiation. * Some RSA implementations use a number representation including arrays * of 32bit words of variable size. Compile with * -D USE_VARIABLE_SIZED_DATA_LOADS in order to load these numbers * directly into CRYPTO without converting the number representation. * * @n @section crypto_exec Load and Execute Instruction Sequences * The functions for loading data and executing instruction sequences can * be used to implement complex algorithms like elliptic curve cryptography * (ECC)) and authenticated encryption algorithms. There are two typical * modes of operation: * @li Multi-sequence operation * @li Single static instruction sequence operation * * In multi-sequence mode the software starts by loading input data, * an instruction sequence, execute, and finally read the result. This * process is repeated until the full crypto operation is complete. * * When using a single static instruction sequence, only one * instruction sequence is loaded initially. The sequence can be set up * to run multiple times. Data can be loaded during the execution of the * sequence by using DMA, BUFC and/or programmed I/O directly from the MCU * core. For details about how to program the instruction sequences, see * the reference manual of the particular Silicon Labs device. * * To load input data to the CRYPTO module, use any of the following * functions: * @li @ref CRYPTO_DataWrite - Write 128 bits to a DATA register. * @li @ref CRYPTO_DDataWrite - Write 256 bits to a DDATA register. * @li @ref CRYPTO_QDataWrite - Write 512 bits to a QDATA register. * * In order to read output data from the CRYPTO module use any of the * following functions: * @li @ref CRYPTO_DataRead - Read 128 bits from a DATA register. * @li @ref CRYPTO_DDataRead - Read 256 bits from a DDATA register. * @li @ref CRYPTO_QDataRead - Read 512 bits from a QDATA register. * * To load an instruction sequence to the CRYPTO module, use * @ref CRYPTO_InstructionSequenceLoad. * * To execute the current instruction sequence in the CRYPTO module, * use @ref CRYPTO_InstructionSequenceExecute. * * To check whether an instruction sequence has completed, * use @ref CRYPTO_InstructionSequenceDone. * * To wait for an instruction sequence to complete, * use @ref CRYPTO_InstructionSequenceWait. * * To optimally load (with regards to speed) and execute an * instruction sequence, use any of the CRYPTO_EXECUTE_X macros (where X is * in the range 1-20) defined in @ref em_crypto.h. E.g. CRYPTO_EXECUTE_19. * @{ ******************************************************************************/ /******************************************************************************* ****************************** DEFINES *********************************** ******************************************************************************/ /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ /** Default CRYPTO instance for deprecated AES functions. */ #if !defined(DEFAULT_CRYPTO) #if defined(CRYPTO) #define DEFAULT_CRYPTO CRYPTO #elif defined(CRYPTO0) #define DEFAULT_CRYPTO CRYPTO0 #endif #endif /** Data sizes used by CRYPTO operations. */ #define CRYPTO_DATA_SIZE_IN_BITS (128) #define CRYPTO_DATA_SIZE_IN_BYTES (CRYPTO_DATA_SIZE_IN_BITS / 8) #define CRYPTO_DATA_SIZE_IN_32BIT_WORDS (CRYPTO_DATA_SIZE_IN_BYTES / sizeof(uint32_t)) #define CRYPTO_KEYBUF_SIZE_IN_BITS (256) #define CRYPTO_KEYBUF_SIZE_IN_BYTES (CRYPTO_DDATA_SIZE_IN_BITS / 8) #define CRYPTO_KEYBUF_SIZE_IN_32BIT_WORDS (CRYPTO_DDATA_SIZE_IN_BYTES / sizeof(uint32_t)) #define CRYPTO_DDATA_SIZE_IN_BITS (256) #define CRYPTO_DDATA_SIZE_IN_BYTES (CRYPTO_DDATA_SIZE_IN_BITS / 8) #define CRYPTO_DDATA_SIZE_IN_32BIT_WORDS (CRYPTO_DDATA_SIZE_IN_BYTES / sizeof(uint32_t)) #define CRYPTO_QDATA_SIZE_IN_BITS (512) #define CRYPTO_QDATA_SIZE_IN_BYTES (CRYPTO_QDATA_SIZE_IN_BITS / 8) #define CRYPTO_QDATA_SIZE_IN_32BIT_WORDS (CRYPTO_QDATA_SIZE_IN_BYTES / sizeof(uint32_t)) #define CRYPTO_DATA260_SIZE_IN_32BIT_WORDS (9) /** SHA-1 digest sizes */ #define CRYPTO_SHA1_DIGEST_SIZE_IN_BITS (160) #define CRYPTO_SHA1_DIGEST_SIZE_IN_BYTES (CRYPTO_SHA1_DIGEST_SIZE_IN_BITS / 8) /** SHA-256 digest sizes */ #define CRYPTO_SHA256_DIGEST_SIZE_IN_BITS (256) #define CRYPTO_SHA256_DIGEST_SIZE_IN_BYTES (CRYPTO_SHA256_DIGEST_SIZE_IN_BITS / 8) /** * Read and write all 260 bits of DDATA0 when in 260 bit mode. */ #define CRYPTO_DDATA0_260_BITS_READ(crypto, bigint260) CRYPTO_DData0Read260(crypto, bigint260) #define CRYPTO_DDATA0_260_BITS_WRITE(crypto, bigint260) CRYPTO_DData0Write260(crypto, bigint260) /** @endcond */ /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ /** * Instruction sequence load macros CRYPTO_SEQ_LOAD_X (where X is in the range * 1-20), for example, @ref CRYPTO_SEQ_LOAD_20. * Use these macros for faster execution than the function API. */ #define CRYPTO_SEQ_LOAD_1(crypto, a1) { \ crypto->SEQ0 = a1 | (CRYPTO_CMD_INSTR_END << 8); } #define CRYPTO_SEQ_LOAD_2(crypto, a1, a2) { \ crypto->SEQ0 = a1 | (a2 << 8) | (CRYPTO_CMD_INSTR_END << 16); } #define CRYPTO_SEQ_LOAD_3(crypto, a1, a2, a3) { \ crypto->SEQ0 = a1 | (a2 << 8) | (a3 << 16) | (CRYPTO_CMD_INSTR_END << 24); } #define CRYPTO_SEQ_LOAD_4(crypto, a1, a2, a3, a4) { \ crypto->SEQ0 = a1 | (a2 << 8) | (a3 << 16) | (a4 << 24); \ crypto->SEQ1 = CRYPTO_CMD_INSTR_END; } #define CRYPTO_SEQ_LOAD_5(crypto, a1, a2, a3, a4, a5) { \ crypto->SEQ0 = a1 | (a2 << 8) | (a3 << 16) | (a4 << 24); \ crypto->SEQ1 = a5 | (CRYPTO_CMD_INSTR_END << 8); } #define CRYPTO_SEQ_LOAD_6(crypto, a1, a2, a3, a4, a5, a6) { \ crypto->SEQ0 = a1 | (a2 << 8) | (a3 << 16) | (a4 << 24); \ crypto->SEQ1 = a5 | (a6 << 8) | (CRYPTO_CMD_INSTR_END << 16); } #define CRYPTO_SEQ_LOAD_7(crypto, a1, a2, a3, a4, a5, a6, a7) { \ crypto->SEQ0 = a1 | (a2 << 8) | (a3 << 16) | (a4 << 24); \ crypto->SEQ1 = a5 | (a6 << 8) | (a7 << 16) | (CRYPTO_CMD_INSTR_END << 24); } #define CRYPTO_SEQ_LOAD_8(crypto, a1, a2, a3, a4, a5, a6, a7, a8) { \ crypto->SEQ0 = a1 | (a2 << 8) | (a3 << 16) | (a4 << 24); \ crypto->SEQ1 = a5 | (a6 << 8) | (a7 << 16) | (a8 << 24); \ crypto->SEQ2 = CRYPTO_CMD_INSTR_END; } #define CRYPTO_SEQ_LOAD_9(crypto, a1, a2, a3, a4, a5, a6, a7, a8, a9) { \ crypto->SEQ0 = a1 | (a2 << 8) | (a3 << 16) | (a4 << 24); \ crypto->SEQ1 = a5 | (a6 << 8) | (a7 << 16) | (a8 << 24); \ crypto->SEQ2 = a9 | (CRYPTO_CMD_INSTR_END << 8); } #define CRYPTO_SEQ_LOAD_10(crypto, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10) { \ crypto->SEQ0 = a1 | (a2 << 8) | (a3 << 16) | (a4 << 24); \ crypto->SEQ1 = a5 | (a6 << 8) | (a7 << 16) | (a8 << 24); \ crypto->SEQ2 = a9 | (a10 << 8) | (CRYPTO_CMD_INSTR_END << 16); } #define CRYPTO_SEQ_LOAD_11(crypto, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11) { \ crypto->SEQ0 = a1 | (a2 << 8) | (a3 << 16) | (a4 << 24); \ crypto->SEQ1 = a5 | (a6 << 8) | (a7 << 16) | (a8 << 24); \ crypto->SEQ2 = a9 | (a10 << 8) | (a11 << 16) | (CRYPTO_CMD_INSTR_END << 24); } #define CRYPTO_SEQ_LOAD_12(crypto, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12) { \ crypto->SEQ0 = a1 | (a2 << 8) | (a3 << 16) | (a4 << 24); \ crypto->SEQ1 = a5 | (a6 << 8) | (a7 << 16) | (a8 << 24); \ crypto->SEQ2 = a9 | (a10 << 8) | (a11 << 16) | (a12 << 24); \ crypto->SEQ3 = CRYPTO_CMD_INSTR_END; } #define CRYPTO_SEQ_LOAD_13(crypto, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13) { \ crypto->SEQ0 = a1 | (a2 << 8) | (a3 << 16) | (a4 << 24); \ crypto->SEQ1 = a5 | (a6 << 8) | (a7 << 16) | (a8 << 24); \ crypto->SEQ2 = a9 | (a10 << 8) | (a11 << 16) | (a12 << 24); \ crypto->SEQ3 = a13 | (CRYPTO_CMD_INSTR_END << 8); } #define CRYPTO_SEQ_LOAD_14(crypto, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14) { \ crypto->SEQ0 = a1 | (a2 << 8) | (a3 << 16) | (a4 << 24); \ crypto->SEQ1 = a5 | (a6 << 8) | (a7 << 16) | (a8 << 24); \ crypto->SEQ2 = a9 | (a10 << 8) | (a11 << 16) | (a12 << 24); \ crypto->SEQ3 = a13 | (a14 << 8) | (CRYPTO_CMD_INSTR_END << 16); } #define CRYPTO_SEQ_LOAD_15(crypto, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15) { \ crypto->SEQ0 = a1 | (a2 << 8) | (a3 << 16) | (a4 << 24); \ crypto->SEQ1 = a5 | (a6 << 8) | (a7 << 16) | (a8 << 24); \ crypto->SEQ2 = a9 | (a10 << 8) | (a11 << 16) | (a12 << 24); \ crypto->SEQ3 = a13 | (a14 << 8) | (a15 << 16) | (CRYPTO_CMD_INSTR_END << 24); } #define CRYPTO_SEQ_LOAD_16(crypto, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15, a16) { \ crypto->SEQ0 = a1 | (a2 << 8) | (a3 << 16) | (a4 << 24); \ crypto->SEQ1 = a5 | (a6 << 8) | (a7 << 16) | (a8 << 24); \ crypto->SEQ2 = a9 | (a10 << 8) | (a11 << 16) | (a12 << 24); \ crypto->SEQ3 = a13 | (a14 << 8) | (a15 << 16) | (a16 << 24); \ crypto->SEQ4 = CRYPTO_CMD_INSTR_END; } #define CRYPTO_SEQ_LOAD_17(crypto, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15, a16, a17) { \ crypto->SEQ0 = a1 | (a2 << 8) | (a3 << 16) | (a4 << 24); \ crypto->SEQ1 = a5 | (a6 << 8) | (a7 << 16) | (a8 << 24); \ crypto->SEQ2 = a9 | (a10 << 8) | (a11 << 16) | (a12 << 24); \ crypto->SEQ3 = a13 | (a14 << 8) | (a15 << 16) | (a16 << 24); \ crypto->SEQ4 = a17 | (CRYPTO_CMD_INSTR_END << 8); } #define CRYPTO_SEQ_LOAD_18(crypto, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15, a16, a17, a18) { \ crypto->SEQ0 = a1 | (a2 << 8) | (a3 << 16) | (a4 << 24); \ crypto->SEQ1 = a5 | (a6 << 8) | (a7 << 16) | (a8 << 24); \ crypto->SEQ2 = a9 | (a10 << 8) | (a11 << 16) | (a12 << 24); \ crypto->SEQ3 = a13 | (a14 << 8) | (a15 << 16) | (a16 << 24); \ crypto->SEQ4 = a17 | (a18 << 8) | (CRYPTO_CMD_INSTR_END << 16); } #define CRYPTO_SEQ_LOAD_19(crypto, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15, a16, a17, a18, a19) { \ crypto->SEQ0 = a1 | (a2 << 8) | (a3 << 16) | (a4 << 24); \ crypto->SEQ1 = a5 | (a6 << 8) | (a7 << 16) | (a8 << 24); \ crypto->SEQ2 = a9 | (a10 << 8) | (a11 << 16) | (a12 << 24); \ crypto->SEQ3 = a13 | (a14 << 8) | (a15 << 16) | (a16 << 24); \ crypto->SEQ4 = a17 | (a18 << 8) | (a19 << 16) | (CRYPTO_CMD_INSTR_END << 24); } #define CRYPTO_SEQ_LOAD_20(crypto, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15, a16, a17, a18, a19, a20) { \ crypto->SEQ0 = a1 | (a2 << 8) | (a3 << 16) | (a4 << 24); \ crypto->SEQ1 = a5 | (a6 << 8) | (a7 << 16) | (a8 << 24); \ crypto->SEQ2 = a9 | (a10 << 8) | (a11 << 16) | (a12 << 24); \ crypto->SEQ3 = a13 | (a14 << 8) | (a15 << 16) | (a16 << 24); \ crypto->SEQ4 = a17 | (a18 << 8) | (a19 << 16) | (a20 << 24); } /** @endcond */ /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ /** * Instruction sequence execution macros CRYPTO_EXECUTE_X (where X is in range * 1-20), for example @ref CRYPTO_EXECUTE_19. * Use these macros for faster execution than the function API. */ #define CRYPTO_EXECUTE_1(crypto, a1) { \ crypto->SEQ0 = a1 | (CRYPTO_CMD_INSTR_EXEC << 8); } #define CRYPTO_EXECUTE_2(crypto, a1, a2) { \ crypto->SEQ0 = a1 | (a2 << 8) | (CRYPTO_CMD_INSTR_EXEC << 16); } #define CRYPTO_EXECUTE_3(crypto, a1, a2, a3) { \ crypto->SEQ0 = a1 | (a2 << 8) | (a3 << 16) | (CRYPTO_CMD_INSTR_EXEC << 24); } #define CRYPTO_EXECUTE_4(crypto, a1, a2, a3, a4) { \ crypto->SEQ0 = a1 | (a2 << 8) | (a3 << 16) | (a4 << 24); \ crypto->SEQ1 = CRYPTO_CMD_INSTR_EXEC; } #define CRYPTO_EXECUTE_5(crypto, a1, a2, a3, a4, a5) { \ crypto->SEQ0 = a1 | (a2 << 8) | (a3 << 16) | (a4 << 24); \ crypto->SEQ1 = a5 | (CRYPTO_CMD_INSTR_EXEC << 8); } #define CRYPTO_EXECUTE_6(crypto, a1, a2, a3, a4, a5, a6) { \ crypto->SEQ0 = a1 | (a2 << 8) | (a3 << 16) | (a4 << 24); \ crypto->SEQ1 = a5 | (a6 << 8) | (CRYPTO_CMD_INSTR_EXEC << 16); } #define CRYPTO_EXECUTE_7(crypto, a1, a2, a3, a4, a5, a6, a7) { \ crypto->SEQ0 = a1 | (a2 << 8) | (a3 << 16) | (a4 << 24); \ crypto->SEQ1 = a5 | (a6 << 8) | (a7 << 16) | (CRYPTO_CMD_INSTR_EXEC << 24); } #define CRYPTO_EXECUTE_8(crypto, a1, a2, a3, a4, a5, a6, a7, a8) { \ crypto->SEQ0 = a1 | (a2 << 8) | (a3 << 16) | (a4 << 24); \ crypto->SEQ1 = a5 | (a6 << 8) | (a7 << 16) | (a8 << 24); \ crypto->SEQ2 = CRYPTO_CMD_INSTR_EXEC; } #define CRYPTO_EXECUTE_9(crypto, a1, a2, a3, a4, a5, a6, a7, a8, a9) { \ crypto->SEQ0 = a1 | (a2 << 8) | (a3 << 16) | (a4 << 24); \ crypto->SEQ1 = a5 | (a6 << 8) | (a7 << 16) | (a8 << 24); \ crypto->SEQ2 = a9 | (CRYPTO_CMD_INSTR_EXEC << 8); } #define CRYPTO_EXECUTE_10(crypto, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10) { \ crypto->SEQ0 = a1 | (a2 << 8) | (a3 << 16) | (a4 << 24); \ crypto->SEQ1 = a5 | (a6 << 8) | (a7 << 16) | (a8 << 24); \ crypto->SEQ2 = a9 | (a10 << 8) | (CRYPTO_CMD_INSTR_EXEC << 16); } #define CRYPTO_EXECUTE_11(crypto, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11) { \ crypto->SEQ0 = a1 | (a2 << 8) | (a3 << 16) | (a4 << 24); \ crypto->SEQ1 = a5 | (a6 << 8) | (a7 << 16) | (a8 << 24); \ crypto->SEQ2 = a9 | (a10 << 8) | (a11 << 16) | (CRYPTO_CMD_INSTR_EXEC << 24); } #define CRYPTO_EXECUTE_12(crypto, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12) { \ crypto->SEQ0 = a1 | (a2 << 8) | (a3 << 16) | (a4 << 24); \ crypto->SEQ1 = a5 | (a6 << 8) | (a7 << 16) | (a8 << 24); \ crypto->SEQ2 = a9 | (a10 << 8) | (a11 << 16) | (a12 << 24); \ crypto->SEQ3 = CRYPTO_CMD_INSTR_EXEC; } #define CRYPTO_EXECUTE_13(crypto, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13) { \ crypto->SEQ0 = a1 | (a2 << 8) | (a3 << 16) | (a4 << 24); \ crypto->SEQ1 = a5 | (a6 << 8) | (a7 << 16) | (a8 << 24); \ crypto->SEQ2 = a9 | (a10 << 8) | (a11 << 16) | (a12 << 24); \ crypto->SEQ3 = a13 | (CRYPTO_CMD_INSTR_EXEC << 8); } #define CRYPTO_EXECUTE_14(crypto, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14) { \ crypto->SEQ0 = a1 | (a2 << 8) | (a3 << 16) | (a4 << 24); \ crypto->SEQ1 = a5 | (a6 << 8) | (a7 << 16) | (a8 << 24); \ crypto->SEQ2 = a9 | (a10 << 8) | (a11 << 16) | (a12 << 24); \ crypto->SEQ3 = a13 | (a14 << 8) | (CRYPTO_CMD_INSTR_EXEC << 16); } #define CRYPTO_EXECUTE_15(crypto, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15) { \ crypto->SEQ0 = a1 | (a2 << 8) | (a3 << 16) | (a4 << 24); \ crypto->SEQ1 = a5 | (a6 << 8) | (a7 << 16) | (a8 << 24); \ crypto->SEQ2 = a9 | (a10 << 8) | (a11 << 16) | (a12 << 24); \ crypto->SEQ3 = a13 | (a14 << 8) | (a15 << 16) | (CRYPTO_CMD_INSTR_EXEC << 24); } #define CRYPTO_EXECUTE_16(crypto, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15, a16) { \ crypto->SEQ0 = a1 | (a2 << 8) | (a3 << 16) | (a4 << 24); \ crypto->SEQ1 = a5 | (a6 << 8) | (a7 << 16) | (a8 << 24); \ crypto->SEQ2 = a9 | (a10 << 8) | (a11 << 16) | (a12 << 24); \ crypto->SEQ3 = a13 | (a14 << 8) | (a15 << 16) | (a16 << 24); \ crypto->SEQ4 = CRYPTO_CMD_INSTR_EXEC; } #define CRYPTO_EXECUTE_17(crypto, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15, a16, a17) { \ crypto->SEQ0 = a1 | (a2 << 8) | (a3 << 16) | (a4 << 24); \ crypto->SEQ1 = a5 | (a6 << 8) | (a7 << 16) | (a8 << 24); \ crypto->SEQ2 = a9 | (a10 << 8) | (a11 << 16) | (a12 << 24); \ crypto->SEQ3 = a13 | (a14 << 8) | (a15 << 16) | (a16 << 24); \ crypto->SEQ4 = a17 | (CRYPTO_CMD_INSTR_EXEC << 8); } #define CRYPTO_EXECUTE_18(crypto, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15, a16, a17, a18) { \ crypto->SEQ0 = a1 | (a2 << 8) | (a3 << 16) | (a4 << 24); \ crypto->SEQ1 = a5 | (a6 << 8) | (a7 << 16) | (a8 << 24); \ crypto->SEQ2 = a9 | (a10 << 8) | (a11 << 16) | (a12 << 24); \ crypto->SEQ3 = a13 | (a14 << 8) | (a15 << 16) | (a16 << 24); \ crypto->SEQ4 = a17 | (a18 << 8) | (CRYPTO_CMD_INSTR_EXEC << 16); } #define CRYPTO_EXECUTE_19(crypto, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15, a16, a17, a18, a19) { \ crypto->SEQ0 = a1 | (a2 << 8) | (a3 << 16) | (a4 << 24); \ crypto->SEQ1 = a5 | (a6 << 8) | (a7 << 16) | (a8 << 24); \ crypto->SEQ2 = a9 | (a10 << 8) | (a11 << 16) | (a12 << 24); \ crypto->SEQ3 = a13 | (a14 << 8) | (a15 << 16) | (a16 << 24); \ crypto->SEQ4 = a17 | (a18 << 8) | (a19 << 16) | (CRYPTO_CMD_INSTR_EXEC << 24); } #define CRYPTO_EXECUTE_20(crypto, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15, a16, a17, a18, a19, a20) { \ crypto->SEQ0 = a1 | (a2 << 8) | (a3 << 16) | (a4 << 24); \ crypto->SEQ1 = a5 | (a6 << 8) | (a7 << 16) | (a8 << 24); \ crypto->SEQ2 = a9 | (a10 << 8) | (a11 << 16) | (a12 << 24); \ crypto->SEQ3 = a13 | (a14 << 8) | (a15 << 16) | (a16 << 24); \ crypto->SEQ4 = a17 | (a18 << 8) | (a19 << 16) | (a20 << 24); \ CRYPTO_InstructionSequenceExecute(crypto); } /** @endcond */ /******************************************************************************* ****************************** TYPEDEFS *********************************** ******************************************************************************/ /** * CRYPTO data types used for data load functions. This data type is * capable of storing a 128 bits value as used in the crypto DATA * registers. */ typedef uint32_t CRYPTO_Data_TypeDef[CRYPTO_DATA_SIZE_IN_32BIT_WORDS]; /** * CRYPTO data type used for data load functions. This data type * is capable of storing a 256 bits value as used in the crypto DDATA * registers. */ typedef uint32_t CRYPTO_DData_TypeDef[CRYPTO_DDATA_SIZE_IN_32BIT_WORDS]; /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ typedef uint32_t* CRYPTO_DDataPtr_TypeDef; /** @endcond */ /** * CRYPTO data type used for data load functions. This data type is * capable of storing a 512 bits value as used in the crypto QDATA * registers. */ typedef uint32_t CRYPTO_QData_TypeDef[CRYPTO_QDATA_SIZE_IN_32BIT_WORDS]; /** * CRYPTO data type used for data load functions. This data type is * capable of storing a 260 bits value as used by the @ref CRYPTO_DData0Write260 * function. * * Note that this data type is multiple of 32 bit words, so the * actual storage used by this type is 32x9=288 bits. */ typedef uint32_t CRYPTO_Data260_TypeDef[CRYPTO_DATA260_SIZE_IN_32BIT_WORDS]; /** * CRYPTO data type used for data load functions. This data type is * capable of storing 256 bits as used in the crypto KEYBUF register. */ typedef uint32_t CRYPTO_KeyBuf_TypeDef[CRYPTO_KEYBUF_SIZE_IN_32BIT_WORDS]; /** * CRYPTO 128 bit Data register pointer type. The 128 bit registers are used to * load 128 bit values as input and output data for cryptographic and big * integer arithmetic functions of the CRYPTO module. */ typedef volatile uint32_t* CRYPTO_DataReg_TypeDef; /** * CRYPTO 256 bit DData (Double Data) register pointer type. The 256 bit * registers are used to load 256 bit values as input and output data for * cryptographic and big integer arithmetic functions of the CRYPTO module. */ typedef volatile uint32_t* CRYPTO_DDataReg_TypeDef; /** * CRYPTO 512 bit QData (Quad data) register pointer type. The 512 bit * registers are used to load 512 bit values as input and output data for * cryptographic and big integer arithmetic functions of the CRYPTO module. */ typedef volatile uint32_t* CRYPTO_QDataReg_TypeDef; /** CRYPTO modulus identifiers. */ typedef enum { cryptoModulusBin256 = CRYPTO_WAC_MODULUS_BIN256, /**< Generic 256 bit modulus 2^256 */ cryptoModulusBin128 = CRYPTO_WAC_MODULUS_BIN128, /**< Generic 128 bit modulus 2^128 */ cryptoModulusGcmBin128 = CRYPTO_WAC_MODULUS_GCMBIN128, /**< GCM 128 bit modulus = 2^128 + 2^7 + 2^2 + 2 + 1 */ cryptoModulusEccB233 = CRYPTO_WAC_MODULUS_ECCBIN233P, /**< ECC B233 prime modulus = 2^233 + 2^74 + 1 */ cryptoModulusEccB163 = CRYPTO_WAC_MODULUS_ECCBIN163P, /**< ECC B163 prime modulus = 2^163 + 2^7 + 2^6 + 2^3 + 1 */ cryptoModulusEccP256 = CRYPTO_WAC_MODULUS_ECCPRIME256P, /**< ECC P256 prime modulus = 2^256 - 2^224 + 2^192 + 2^96 - 1 */ cryptoModulusEccP224 = CRYPTO_WAC_MODULUS_ECCPRIME224P, /**< ECC P224 prime modulus = 2^224 - 2^96 - 1 */ cryptoModulusEccP192 = CRYPTO_WAC_MODULUS_ECCPRIME192P, /**< ECC P192 prime modulus = 2^192 - 2^64 - 1 */ cryptoModulusEccB233Order = CRYPTO_WAC_MODULUS_ECCBIN233N, /**< ECC B233 order modulus */ cryptoModulusEccB233KOrder = CRYPTO_WAC_MODULUS_ECCBIN233KN, /**< ECC B233K order modulus */ cryptoModulusEccB163Order = CRYPTO_WAC_MODULUS_ECCBIN163N, /**< ECC B163 order modulus */ cryptoModulusEccB163KOrder = CRYPTO_WAC_MODULUS_ECCBIN163KN, /**< ECC B163K order modulus */ cryptoModulusEccP256Order = CRYPTO_WAC_MODULUS_ECCPRIME256N, /**< ECC P256 order modulus */ cryptoModulusEccP224Order = CRYPTO_WAC_MODULUS_ECCPRIME224N, /**< ECC P224 order modulus */ cryptoModulusEccP192Order = CRYPTO_WAC_MODULUS_ECCPRIME192N /**< ECC P192 order modulus */ } CRYPTO_ModulusId_TypeDef; /** CRYPTO multiplication widths for wide arithmetic operations. */ typedef enum { cryptoMulOperand256Bits = CRYPTO_WAC_MULWIDTH_MUL256, /**< 256 bits operands */ cryptoMulOperand128Bits = CRYPTO_WAC_MULWIDTH_MUL128, /**< 128 bits operands */ cryptoMulOperandModulusBits = CRYPTO_WAC_MULWIDTH_MULMOD /**< MUL operand width is specified by the modulus type.*/ } CRYPTO_MulOperandWidth_TypeDef; /** CRYPTO result widths for MUL operations. */ typedef enum { cryptoResult128Bits = CRYPTO_WAC_RESULTWIDTH_128BIT, /**< Multiplication result width is 128 bits*/ cryptoResult256Bits = CRYPTO_WAC_RESULTWIDTH_256BIT, /**< Multiplication result width is 256 bits*/ cryptoResult260Bits = CRYPTO_WAC_RESULTWIDTH_260BIT /**< Multiplication result width is 260 bits*/ } CRYPTO_ResultWidth_TypeDef; /** CRYPTO result widths for MUL operations. */ typedef enum { cryptoInc1byte = CRYPTO_CTRL_INCWIDTH_INCWIDTH1, /**< inc width is 1 byte*/ cryptoInc2byte = CRYPTO_CTRL_INCWIDTH_INCWIDTH2, /**< inc width is 2 byte*/ cryptoInc3byte = CRYPTO_CTRL_INCWIDTH_INCWIDTH3, /**< inc width is 3 byte*/ cryptoInc4byte = CRYPTO_CTRL_INCWIDTH_INCWIDTH4 /**< inc width is 4 byte*/ } CRYPTO_IncWidth_TypeDef; /** CRYPTO key width. */ typedef enum { cryptoKey128Bits = 8, /**< Key width is 128 bits*/ cryptoKey256Bits = 16, /**< Key width is 256 bits*/ } CRYPTO_KeyWidth_TypeDef; /** * The maximum number of crypto instructions in an instruction sequence. */ #define CRYPTO_MAX_SEQUENCE_INSTRUCTIONS (20) /** * Instruction sequence type. * Fill in the desired operations from step1, step2, and so on. * The CRYPTO_CMD_INSTR_END marks the end of the sequence. * Bit fields are used to format the memory layout of the struct equal to the * sequence registers in the CRYPTO module. */ typedef uint8_t CRYPTO_InstructionSequence_TypeDef[CRYPTO_MAX_SEQUENCE_INSTRUCTIONS]; /** Default instruction sequence consisting of all ENDs. The user can initialize the instruction sequence with this default value set and fill in the desired operations from step 1. The first END instruction marks the end of the sequence. */ #define CRYPTO_INSTRUCTIONSEQUENSE_DEFAULT \ { CRYPTO_CMD_INSTR_END, CRYPTO_CMD_INSTR_END, CRYPTO_CMD_INSTR_END, \ CRYPTO_CMD_INSTR_END, CRYPTO_CMD_INSTR_END, CRYPTO_CMD_INSTR_END, \ CRYPTO_CMD_INSTR_END, CRYPTO_CMD_INSTR_END, CRYPTO_CMD_INSTR_END, \ CRYPTO_CMD_INSTR_END, CRYPTO_CMD_INSTR_END, CRYPTO_CMD_INSTR_END, \ CRYPTO_CMD_INSTR_END, CRYPTO_CMD_INSTR_END, CRYPTO_CMD_INSTR_END, \ CRYPTO_CMD_INSTR_END, CRYPTO_CMD_INSTR_END, CRYPTO_CMD_INSTR_END, \ CRYPTO_CMD_INSTR_END, CRYPTO_CMD_INSTR_END } /** SHA-1 Digest type. */ typedef uint8_t CRYPTO_SHA1_Digest_TypeDef[CRYPTO_SHA1_DIGEST_SIZE_IN_BYTES]; /** SHA-256 Digest type. */ typedef uint8_t CRYPTO_SHA256_Digest_TypeDef[CRYPTO_SHA256_DIGEST_SIZE_IN_BYTES]; /** * @brief * AES counter modification function pointer. * * @note * This is defined for backwards compatibility with EFM32 em_aes.h. * The CRYPTO implementation of counter mode does not support counter update * callbacks. * * @param[in] ctr A counter value to be modified. */ typedef void (*CRYPTO_AES_CtrFuncPtr_TypeDef)(uint8_t * ctr); /******************************************************************************* ***************************** PROTOTYPES ********************************** ******************************************************************************/ /***************************************************************************//** * @brief * Set the modulus type used for wide arithmetic operations. * * @details * This function sets the modulus type to be used by the modulus instructions * of the CRYPTO module. * * @param[in] crypto * A pointer to the CRYPTO peripheral register block. * * @param[in] modType * A modulus type. ******************************************************************************/ void CRYPTO_ModulusSet(CRYPTO_TypeDef * crypto, CRYPTO_ModulusId_TypeDef modType); /***************************************************************************//** * @brief * Set the number of bits in the operands of the MUL instruction. * * @details * This function sets the number of bits to be used in the operands of * the MUL instruction. * * @param[in] crypto * A pointer to the CRYPTO peripheral register block. * * @param[in] mulOperandWidth * Multiplication width in bits. ******************************************************************************/ __STATIC_INLINE void CRYPTO_MulOperandWidthSet(CRYPTO_TypeDef *crypto, CRYPTO_MulOperandWidth_TypeDef mulOperandWidth) { uint32_t temp = crypto->WAC & (~_CRYPTO_WAC_MULWIDTH_MASK); crypto->WAC = temp | (uint32_t)mulOperandWidth; } /***************************************************************************//** * @brief * Set the width of the results of the non-modulus instructions. * * @details * This function sets the result width of the non-modulus instructions. * * @param[in] crypto * A pointer to the CRYPTO peripheral register block. * * @param[in] resultWidth * A result width of non-modulus instructions. ******************************************************************************/ __STATIC_INLINE void CRYPTO_ResultWidthSet(CRYPTO_TypeDef *crypto, CRYPTO_ResultWidth_TypeDef resultWidth) { uint32_t temp = crypto->WAC & (~_CRYPTO_WAC_RESULTWIDTH_MASK); crypto->WAC = temp | (uint32_t)resultWidth; } /***************************************************************************//** * @brief * Set the width of the DATA1 increment instruction DATA1INC. * * @details * This function sets the width of the DATA1 increment instruction * @ref CRYPTO_CMD_INSTR_DATA1INC. * * @param[in] crypto * A pointer to CRYPTO peripheral register block. * * @param[in] incWidth * An incrementation width. ******************************************************************************/ __STATIC_INLINE void CRYPTO_IncWidthSet(CRYPTO_TypeDef *crypto, CRYPTO_IncWidth_TypeDef incWidth) { uint32_t temp = crypto->CTRL & (~_CRYPTO_CTRL_INCWIDTH_MASK); crypto->CTRL = temp | (uint32_t)incWidth; } /***************************************************************************//** * @brief * Write a 128 bit value into a crypto register. * * @note * This function provides a low-level API for writing to the multi-word * registers in the crypto peripheral. Applications should use * @ref CRYPTO_DataWrite, @ref CRYPTO_DDataWrite or @ref CRYPTO_QDataWrite * for writing to DATA, DDATA, and QDATA registers. * * @param[in] reg * A pointer to the crypto register. * * @param[in] val * This is a pointer to 4 32 bit integers that contains the 128 bit value * which will be written to the crypto register. ******************************************************************************/ __STATIC_INLINE void CRYPTO_BurstToCrypto(volatile uint32_t * reg, const uint32_t * val) { /* Load data from memory into local registers. */ register uint32_t v0 = val[0]; register uint32_t v1 = val[1]; register uint32_t v2 = val[2]; register uint32_t v3 = val[3]; /* Store data to CRYPTO */ *reg = v0; *reg = v1; *reg = v2; *reg = v3; } /***************************************************************************//** * @brief * Read a 128 bit value from a crypto register. * * @note * This function provides a low-level API for reading one of the multi-word * registers in the crypto peripheral. Applications should use * @ref CRYPTO_DataRead, @ref CRYPTO_DDataRead or @ref CRYPTO_QDataRead * for reading the value of DATA, DDATA, and QDATA registers. * * @param[in] reg * A pointer to the crypto register. * * @param[out] val * This is a pointer to an array that is capable of holding 4 32 bit integers * that will be filled with the 128 bit value from the crypto register. ******************************************************************************/ __STATIC_INLINE void CRYPTO_BurstFromCrypto(volatile uint32_t * reg, uint32_t * val) { /* Load data from CRYPTO into local registers. */ register uint32_t v0 = *reg; register uint32_t v1 = *reg; register uint32_t v2 = *reg; register uint32_t v3 = *reg; /* Store data to memory */ val[0] = v0; val[1] = v1; val[2] = v2; val[3] = v3; } /***************************************************************************//** * @brief * Write 128 bits of data to a DATAX register in the CRYPTO module. * * @details * Write 128 bits of data to a DATAX register in the crypto module. The data * value is typically input to a big integer operation (see crypto * instructions). * * @param[in] dataReg The 128 bit DATA register. * @param[in] val Value of the data to write to the DATA register. ******************************************************************************/ __STATIC_INLINE void CRYPTO_DataWrite(CRYPTO_DataReg_TypeDef dataReg, const CRYPTO_Data_TypeDef val) { CRYPTO_BurstToCrypto(dataReg, val); } /***************************************************************************//** * @brief * Read 128 bits of data from a DATAX register in the CRYPTO module. * * @details * Read 128 bits of data from a DATAX register in the crypto module. The data * value is typically output from a big integer operation (see crypto * instructions) * * @param[in] dataReg The 128 bit DATA register. * @param[out] val Location where to store the value in memory. ******************************************************************************/ __STATIC_INLINE void CRYPTO_DataRead(CRYPTO_DataReg_TypeDef dataReg, CRYPTO_Data_TypeDef val) { CRYPTO_BurstFromCrypto(dataReg, val); } /***************************************************************************//** * @brief * Write 256 bits of data to a DDATAX register in the CRYPTO module. * * @details * Write 256 bits of data into a DDATAX (Double Data) register in the crypto * module. The data value is typically input to a big integer operation (see * crypto instructions). * * @param[in] ddataReg The 256 bit DDATA register. * @param[in] val Value of the data to write to the DDATA register. ******************************************************************************/ __STATIC_INLINE void CRYPTO_DDataWrite(CRYPTO_DDataReg_TypeDef ddataReg, const CRYPTO_DData_TypeDef val) { CRYPTO_BurstToCrypto(ddataReg, &val[0]); CRYPTO_BurstToCrypto(ddataReg, &val[4]); } /***************************************************************************//** * @brief * Read 256 bits of data from a DDATAX register in the CRYPTO module. * * @details * Read 256 bits of data from a DDATAX (Double Data) register in the crypto * module. The data value is typically output from a big integer operation * (see crypto instructions). * * @param[in] ddataReg The 256 bit DDATA register. * @param[out] val Location where to store the value in memory. ******************************************************************************/ __STATIC_INLINE void CRYPTO_DDataRead(CRYPTO_DDataReg_TypeDef ddataReg, CRYPTO_DData_TypeDef val) { CRYPTO_BurstFromCrypto(ddataReg, &val[0]); CRYPTO_BurstFromCrypto(ddataReg, &val[4]); } /***************************************************************************//** * @brief * Write 512 bits of data to a QDATAX register in the CRYPTO module. * * @details * Write 512 bits of data into a QDATAX (Quad Data) register in the crypto module * The data value is typically input to a big integer operation (see crypto * instructions). * * @param[in] qdataReg The 512 bits QDATA register. * @param[in] val Value of the data to write to the QDATA register. ******************************************************************************/ __STATIC_INLINE void CRYPTO_QDataWrite(CRYPTO_QDataReg_TypeDef qdataReg, const CRYPTO_QData_TypeDef val) { CRYPTO_BurstToCrypto(qdataReg, &val[0]); CRYPTO_BurstToCrypto(qdataReg, &val[4]); CRYPTO_BurstToCrypto(qdataReg, &val[8]); CRYPTO_BurstToCrypto(qdataReg, &val[12]); } /***************************************************************************//** * @brief * Read 512 bits of data from a QDATAX register in the CRYPTO module. * * @details * Read 512 bits of data from a QDATAX register in the crypto module. The data * value is typically input to a big integer operation (see crypto * instructions). * * @param[in] qdataReg The 512 bits QDATA register. * @param[in] val Value of the data to write to the QDATA register. ******************************************************************************/ __STATIC_INLINE void CRYPTO_QDataRead(CRYPTO_QDataReg_TypeDef qdataReg, CRYPTO_QData_TypeDef val) { CRYPTO_BurstFromCrypto(qdataReg, &val[0]); CRYPTO_BurstFromCrypto(qdataReg, &val[4]); CRYPTO_BurstFromCrypto(qdataReg, &val[8]); CRYPTO_BurstFromCrypto(qdataReg, &val[12]); } /***************************************************************************//** * @brief * Set the key value to be used by the CRYPTO module. * * @details * Write 128 or 256 bit key to the KEYBUF register in the crypto module. * * @param[in] crypto * A pointer to the CRYPTO peripheral register block. * * @param[in] val * Value of the data to write to the KEYBUF register. * * @param[in] keyWidth * Key width - 128 or 256 bits. ******************************************************************************/ __STATIC_INLINE void CRYPTO_KeyBufWrite(CRYPTO_TypeDef *crypto, CRYPTO_KeyBuf_TypeDef val, CRYPTO_KeyWidth_TypeDef keyWidth) { if (keyWidth == cryptoKey256Bits) { /* Set AES-256 mode */ BUS_RegBitWrite(&crypto->CTRL, _CRYPTO_CTRL_AES_SHIFT, _CRYPTO_CTRL_AES_AES256); /* Load key in KEYBUF register (= DDATA4) */ CRYPTO_DDataWrite(&crypto->DDATA4, val); } else { /* Set AES-128 mode */ BUS_RegBitWrite(&crypto->CTRL, _CRYPTO_CTRL_AES_SHIFT, _CRYPTO_CTRL_AES_AES128); CRYPTO_BurstToCrypto(&crypto->KEYBUF, &val[0]); } } void CRYPTO_KeyRead(CRYPTO_TypeDef *crypto, CRYPTO_KeyBuf_TypeDef val, CRYPTO_KeyWidth_TypeDef keyWidth); /***************************************************************************//** * @brief * Quick write 128 bit key to the CRYPTO module. * * @details * Quick write 128 bit key to the KEYBUF register in the CRYPTO module. * * @param[in] crypto * A pointer to the CRYPTO peripheral register block. * * @param[in] val * Value of the data to write to the KEYBUF register. ******************************************************************************/ __STATIC_INLINE void CRYPTO_KeyBuf128Write(CRYPTO_TypeDef *crypto, const uint32_t * val) { CRYPTO_BurstToCrypto(&crypto->KEYBUF, val); } /***************************************************************************//** * @brief * Quick read access of the carry bit from arithmetic operations. * * @details * This function reads the carry bit of the CRYPTO ALU. * * @param[in] crypto * A pointer to the CRYPTO peripheral register block. * * @return * Returns 'true' if carry is 1, and 'false' if carry is 0. ******************************************************************************/ __STATIC_INLINE bool CRYPTO_CarryIsSet(CRYPTO_TypeDef *crypto) { return ((crypto->DSTATUS & _CRYPTO_DSTATUS_CARRY_MASK) >> _CRYPTO_DSTATUS_CARRY_SHIFT) != 0UL; } /***************************************************************************//** * @brief * Quick read access of the 4 LSbits of the DDATA0 register. * * @details * This function quickly retrieves the 4 least significant bits of the * DDATA0 register via the DDATA0LSBS bit field in the DSTATUS register. * * @param[in] crypto * A pointer to the CRYPTO peripheral register block. * * @return * Returns the 4 LSbits of DDATA0. ******************************************************************************/ __STATIC_INLINE uint8_t CRYPTO_DData0_4LSBitsRead(CRYPTO_TypeDef *crypto) { return (uint8_t)((crypto->DSTATUS & _CRYPTO_DSTATUS_DDATA0LSBS_MASK) >> _CRYPTO_DSTATUS_DDATA0LSBS_SHIFT); } /***************************************************************************//** * @brief * Read 260 bits from the DDATA0 register. * * @details * This functions reads 260 bits from the DDATA0 register in the CRYPTO * module. The data value is typically output from a big integer operation * (see crypto instructions) when the result width is set to 260 bits by * calling @ref CRYPTO_ResultWidthSet(cryptoResult260Bits); * * @param[in] crypto * A pointer to the CRYPTO peripheral register block. * * @param[out] val * A location to store the value in memory. ******************************************************************************/ __STATIC_INLINE void CRYPTO_DData0Read260(CRYPTO_TypeDef *crypto, CRYPTO_Data260_TypeDef val) { CRYPTO_DDataRead(&crypto->DDATA0, val); val[8] = (crypto->DSTATUS & _CRYPTO_DSTATUS_DDATA0MSBS_MASK) >> _CRYPTO_DSTATUS_DDATA0MSBS_SHIFT; } /***************************************************************************//** * @brief * Write 260 bits to the DDATA0 register. * * @details * This functions writes 260 bits to the DDATA0 register in the CRYPTO * module. The data value is typically input to a big integer operation * (see crypto instructions) when the result width is set to 260 bits by * calling @ref CRYPTO_ResultWidthSet(cryptoResult260Bits); * * @param[in] crypto * Pointer to CRYPTO peripheral register block. * * @param[out] val * Location where of the value in memory. ******************************************************************************/ __STATIC_INLINE void CRYPTO_DData0Write260(CRYPTO_TypeDef *crypto, const CRYPTO_Data260_TypeDef val) { CRYPTO_DDataWrite(&crypto->DDATA0, val); crypto->DDATA0BYTE32 = val[8] & _CRYPTO_DDATA0BYTE32_DDATA0BYTE32_MASK; } /***************************************************************************//** * @brief * Quick read the MSbit of the DDATA1 register. * * @details * This function reads the most significant bit (bit 255) of the DDATA1 * register via the DDATA1MSB bit field in the DSTATUS register. This can * be used to quickly check the signedness of a big integer resident in the * CRYPTO module. * * @param[in] crypto * A pointer to the CRYPTO peripheral register block. * * @return * Returns 'true' if MSbit is 1, and 'false' if MSbit is 0. ******************************************************************************/ __STATIC_INLINE bool CRYPTO_DData1_MSBitRead(CRYPTO_TypeDef *crypto) { return ((crypto->DSTATUS & _CRYPTO_DSTATUS_DDATA1MSB_MASK) >> _CRYPTO_DSTATUS_DDATA1MSB_SHIFT) != 0UL; } /***************************************************************************//** * @brief * Load a sequence of instructions to be executed on the current values in * the data registers. * * @details * This function loads a sequence of instructions to the crypto module. The * instructions will be executed when the CRYPTO_InstructionSequenceExecute * function is called. The first END marks the end of the sequence. * * @param[in] crypto * A pointer to the CRYPTO peripheral register block. * * @param[in] instructionSequence * An instruction sequence to load. ******************************************************************************/ __STATIC_INLINE void CRYPTO_InstructionSequenceLoad(CRYPTO_TypeDef *crypto, const CRYPTO_InstructionSequence_TypeDef instructionSequence) { const uint32_t * pas = (const uint32_t *) instructionSequence; crypto->SEQ0 = pas[0]; crypto->SEQ1 = pas[1]; crypto->SEQ2 = pas[2]; crypto->SEQ3 = pas[3]; crypto->SEQ4 = pas[4]; } /***************************************************************************//** * @brief * Execute the current programmed instruction sequence. * * @details * This function starts the execution of the current instruction sequence * in the CRYPTO module. * * @param[in] crypto * A pointer to the CRYPTO peripheral register block. ******************************************************************************/ __STATIC_INLINE void CRYPTO_InstructionSequenceExecute(CRYPTO_TypeDef *crypto) { /* Start the command sequence. */ crypto->CMD = CRYPTO_CMD_SEQSTART; } /***************************************************************************//** * @brief * Check whether the execution of an instruction sequence has completed. * * @details * This function checks whether an instruction sequence has completed. * * @param[in] crypto * A pointer to the CRYPTO peripheral register block. * * @return * Returns 'true' if the instruction sequence is done, and 'false' if not. ******************************************************************************/ __STATIC_INLINE bool CRYPTO_InstructionSequenceDone(CRYPTO_TypeDef *crypto) { /* Return true if operation has completed. */ return (crypto->STATUS & (CRYPTO_STATUS_INSTRRUNNING | CRYPTO_STATUS_SEQRUNNING)) == 0UL; } /***************************************************************************//** * @brief * Wait for completion of the current sequence of instructions. * * @details * This function "busy"-waits until the execution of the ongoing instruction * sequence has completed. * * @param[in] crypto * A pointer to the CRYPTO peripheral register block. ******************************************************************************/ __STATIC_INLINE void CRYPTO_InstructionSequenceWait(CRYPTO_TypeDef *crypto) { while (!CRYPTO_InstructionSequenceDone(crypto)) { } } /***************************************************************************//** * @brief * Wait for completion of the current command. * * @details * This function "busy"-waits until the execution of the ongoing instruction * has completed. * * @param[in] crypto * A pointer to the CRYPTO peripheral register block. ******************************************************************************/ __STATIC_INLINE void CRYPTO_InstructionWait(CRYPTO_TypeDef *crypto) { /* Wait for completion */ while ((crypto->IF & CRYPTO_IF_INSTRDONE) == 0UL) { } crypto->IFC = CRYPTO_IF_INSTRDONE; } void CRYPTO_SHA_1(CRYPTO_TypeDef *crypto, const uint8_t *msg, uint64_t msgLen, CRYPTO_SHA1_Digest_TypeDef digest); void CRYPTO_SHA_256(CRYPTO_TypeDef *crypto, const uint8_t *msg, uint64_t msgLen, CRYPTO_SHA256_Digest_TypeDef digest); void CRYPTO_Mul(CRYPTO_TypeDef *crypto, uint32_t * A, int aSize, uint32_t * B, int bSize, uint32_t * R, int rSize); void CRYPTO_AES_CBC128(CRYPTO_TypeDef *crypto, uint8_t * out, const uint8_t * in, unsigned int len, const uint8_t * key, const uint8_t * iv, bool encrypt); void CRYPTO_AES_CBC256(CRYPTO_TypeDef *crypto, uint8_t * out, const uint8_t * in, unsigned int len, const uint8_t * key, const uint8_t * iv, bool encrypt); void CRYPTO_AES_CFB128(CRYPTO_TypeDef *crypto, uint8_t * out, const uint8_t * in, unsigned int len, const uint8_t * key, const uint8_t * iv, bool encrypt); void CRYPTO_AES_CFB256(CRYPTO_TypeDef *crypto, uint8_t * out, const uint8_t * in, unsigned int len, const uint8_t * key, const uint8_t * iv, bool encrypt); void CRYPTO_AES_CTR128(CRYPTO_TypeDef *crypto, uint8_t * out, const uint8_t * in, unsigned int len, const uint8_t * key, uint8_t * ctr, CRYPTO_AES_CtrFuncPtr_TypeDef ctrFunc); void CRYPTO_AES_CTR256(CRYPTO_TypeDef *crypto, uint8_t * out, const uint8_t * in, unsigned int len, const uint8_t * key, uint8_t * ctr, CRYPTO_AES_CtrFuncPtr_TypeDef ctrFunc); void CRYPTO_AES_CTRUpdate32Bit(uint8_t * ctr); void CRYPTO_AES_DecryptKey128(CRYPTO_TypeDef *crypto, uint8_t * out, const uint8_t * in); void CRYPTO_AES_DecryptKey256(CRYPTO_TypeDef *crypto, uint8_t * out, const uint8_t * in); void CRYPTO_AES_ECB128(CRYPTO_TypeDef *crypto, uint8_t * out, const uint8_t * in, unsigned int len, const uint8_t * key, bool encrypt); void CRYPTO_AES_ECB256(CRYPTO_TypeDef *crypto, uint8_t * out, const uint8_t * in, unsigned int len, const uint8_t * key, bool encrypt); void CRYPTO_AES_OFB128(CRYPTO_TypeDef *crypto, uint8_t * out, const uint8_t * in, unsigned int len, const uint8_t * key, const uint8_t * iv); void CRYPTO_AES_OFB256(CRYPTO_TypeDef *crypto, uint8_t * out, const uint8_t * in, unsigned int len, const uint8_t * key, const uint8_t * iv); /***************************************************************************//** * @brief * Clear one or more pending CRYPTO interrupts. * * @param[in] crypto * A pointer to the CRYPTO peripheral register block. * * @param[in] flags * A pending CRYPTO interrupt source to clear. Use a bitwise logic OR combination of * valid interrupt flags for the CRYPTO module (CRYPTO_IF_nnn). ******************************************************************************/ __STATIC_INLINE void CRYPTO_IntClear(CRYPTO_TypeDef *crypto, uint32_t flags) { crypto->IFC = flags; } /***************************************************************************//** * @brief * Disable one or more CRYPTO interrupts. * * @param[in] crypto * A pointer to the CRYPTO peripheral register block. * * @param[in] flags * CRYPTO interrupt sources to disable. Use a bitwise logic OR combination of * valid interrupt flags for the CRYPTO module (CRYPTO_IF_nnn). ******************************************************************************/ __STATIC_INLINE void CRYPTO_IntDisable(CRYPTO_TypeDef *crypto, uint32_t flags) { crypto->IEN &= ~(flags); } /***************************************************************************//** * @brief * Enable one or more CRYPTO interrupts. * * @note * Depending on the use, a pending interrupt may already be set prior to * enabling the interrupt. Consider using CRYPTO_IntClear() prior to enabling * if such a pending interrupt should be ignored. * * @param[in] crypto * A pointer to the CRYPTO peripheral register block. * * @param[in] flags * CRYPTO interrupt sources to enable. Use a bitwise logic OR combination of * valid interrupt flags for the CRYPTO module (CRYPTO_IF_nnn). ******************************************************************************/ __STATIC_INLINE void CRYPTO_IntEnable(CRYPTO_TypeDef *crypto, uint32_t flags) { crypto->IEN |= flags; } /***************************************************************************//** * @brief * Get pending CRYPTO interrupt flags. * * @note * The event bits are not cleared by the use of this function. * * @param[in] crypto * A pointer to the CRYPTO peripheral register block. * * @return * CRYPTO interrupt sources pending. A bitwise logic OR combination of valid * interrupt flags for the CRYPTO module (CRYPTO_IF_nnn). ******************************************************************************/ __STATIC_INLINE uint32_t CRYPTO_IntGet(CRYPTO_TypeDef *crypto) { return crypto->IF; } /***************************************************************************//** * @brief * Get enabled and pending CRYPTO interrupt flags. * Useful for handling more interrupt sources in the same interrupt handler. * * @note * Interrupt flags are not cleared by the use of this function. * * @param[in] crypto * A pointer to the CRYPTO peripheral register block. * * @return * Pending and enabled CRYPTO interrupt sources * The return value is the bitwise AND of * - the enabled interrupt sources in CRYPTO_IEN and * - the pending interrupt flags CRYPTO_IF ******************************************************************************/ __STATIC_INLINE uint32_t CRYPTO_IntGetEnabled(CRYPTO_TypeDef *crypto) { uint32_t tmp; /* Store IEN in temporary variable in order to define explicit order * of volatile accesses. */ tmp = crypto->IEN; /* Bitwise AND of pending and enabled interrupts */ return crypto->IF & tmp; } /***************************************************************************//** * @brief * Set one or more pending CRYPTO interrupts from software. * * @param[in] crypto * A pointer to the CRYPTO peripheral register block. * * @param[in] flags * CRYPTO interrupt sources to set to pending. Use a bitwise logic OR combination * of valid interrupt flags for the CRYPTO module (CRYPTO_IF_nnn). ******************************************************************************/ __STATIC_INLINE void CRYPTO_IntSet(CRYPTO_TypeDef *crypto, uint32_t flags) { crypto->IFS = flags; } /******************************************************************************* ***** Static inline wrappers for CRYPTO AES functions to ***** ***** preserve backwards compatibility with AES module API functions. ***** ******************************************************************************/ /***************************************************************************//** * @brief * AES Cipher-block chaining (CBC) cipher mode encryption/decryption, * 128 bit key. * * @deprecated * This function preserves backwards compatibility. Use * @ref CRYPTO_AES_CBC128 instead. ******************************************************************************/ __STATIC_INLINE void AES_CBC128(uint8_t * out, const uint8_t * in, unsigned int len, const uint8_t * key, const uint8_t * iv, bool encrypt) { CRYPTO_AES_CBC128(DEFAULT_CRYPTO, out, in, len, key, iv, encrypt); } /***************************************************************************//** * @brief * AES Cipher-block chaining (CBC) cipher mode encryption/decryption, 256 bit * key. * * @deprecated * This function preserves backwards compatibility. Use * @ref CRYPTO_AES_CBC256 instead. ******************************************************************************/ __STATIC_INLINE void AES_CBC256(uint8_t * out, const uint8_t * in, unsigned int len, const uint8_t * key, const uint8_t * iv, bool encrypt) { CRYPTO_AES_CBC256(DEFAULT_CRYPTO, out, in, len, key, iv, encrypt); } /***************************************************************************//** * @brief * AES Cipher feedback (CFB) cipher mode encryption/decryption, 128 bit key. * * @deprecated * This function preserves backwards compatibility. Use * @ref CRYPTO_AES_CFB128 instead. ******************************************************************************/ __STATIC_INLINE void AES_CFB128(uint8_t * out, const uint8_t * in, unsigned int len, const uint8_t * key, const uint8_t * iv, bool encrypt) { CRYPTO_AES_CFB128(DEFAULT_CRYPTO, out, in, len, key, iv, encrypt); } /***************************************************************************//** * @brief * AES Cipher feedback (CFB) cipher mode encryption/decryption, 256 bit key. * * @deprecated * This function preserves backwards compatibility. Use * @ref CRYPTO_AES_CFB256 instead. ******************************************************************************/ __STATIC_INLINE void AES_CFB256(uint8_t * out, const uint8_t * in, unsigned int len, const uint8_t * key, const uint8_t * iv, bool encrypt) { CRYPTO_AES_CFB256(DEFAULT_CRYPTO, out, in, len, key, iv, encrypt); } /***************************************************************************//** * @brief * AES Counter (CTR) cipher mode encryption/decryption, 128 bit key. * * @deprecated * This function preserves backwards compatibility. Use * @ref CRYPTO_AES_CTR128 instead. ******************************************************************************/ __STATIC_INLINE void AES_CTR128(uint8_t * out, const uint8_t * in, unsigned int len, const uint8_t * key, uint8_t * ctr, CRYPTO_AES_CtrFuncPtr_TypeDef ctrFunc) { CRYPTO_AES_CTR128(DEFAULT_CRYPTO, out, in, len, key, ctr, ctrFunc); } /***************************************************************************//** * @brief * AES Counter (CTR) cipher mode encryption/decryption, 256 bit key. * * @deprecated * This function preserves backwards compatibility. Use * @ref CRYPTO_AES_CTR256 instead. ******************************************************************************/ __STATIC_INLINE void AES_CTR256(uint8_t * out, const uint8_t * in, unsigned int len, const uint8_t * key, uint8_t * ctr, CRYPTO_AES_CtrFuncPtr_TypeDef ctrFunc) { CRYPTO_AES_CTR256(DEFAULT_CRYPTO, out, in, len, key, ctr, ctrFunc); } /***************************************************************************//** * @brief * Update last 32 bits of 128 bit counter, by incrementing with 1. * * @deprecated * This function preserves backwards compatibility. Use * @ref CRYPTO_AES_CTRUpdate32Bit instead. ******************************************************************************/ __STATIC_INLINE void AES_CTRUpdate32Bit(uint8_t * ctr) { CRYPTO_AES_CTRUpdate32Bit(ctr); } /***************************************************************************//** * @brief * Generate 128 bit AES decryption key from 128 bit encryption key. The * decryption key is used for some cipher modes when decrypting. * * @deprecated * This function preserves backwards compatibility. Use * @ref CRYPTO_AES_DecryptKey128 instead. ******************************************************************************/ __STATIC_INLINE void AES_DecryptKey128(uint8_t * out, const uint8_t * in) { CRYPTO_AES_DecryptKey128(DEFAULT_CRYPTO, out, in); } /***************************************************************************//** * @brief * Generate 256 bit AES decryption key from 256 bit encryption key. The * decryption key is used for some cipher modes when decrypting. * * @deprecated * This function preserves backwards compatibility. Use * @ref CRYPTO_AES_DecryptKey256 instead. ******************************************************************************/ __STATIC_INLINE void AES_DecryptKey256(uint8_t * out, const uint8_t * in) { CRYPTO_AES_DecryptKey256(DEFAULT_CRYPTO, out, in); } /***************************************************************************//** * @brief * AES Electronic Codebook (ECB) cipher mode encryption/decryption, * 128 bit key. * * @deprecated * This function preserves backwards compatibility. Use * @ref CRYPTO_AES_ECB128 instead. ******************************************************************************/ __STATIC_INLINE void AES_ECB128(uint8_t * out, const uint8_t * in, unsigned int len, const uint8_t * key, bool encrypt) { CRYPTO_AES_ECB128(DEFAULT_CRYPTO, out, in, len, key, encrypt); } /***************************************************************************//** * @brief * AES Electronic Codebook (ECB) cipher mode encryption/decryption, * 256 bit key. * * @deprecated * This function preserves backwards compatibility. Use * @ref CRYPTO_AES_ECB256 instead. ******************************************************************************/ __STATIC_INLINE void AES_ECB256(uint8_t * out, const uint8_t * in, unsigned int len, const uint8_t * key, bool encrypt) { CRYPTO_AES_ECB256(DEFAULT_CRYPTO, out, in, len, key, encrypt); } /***************************************************************************//** * @brief * AES Output feedback (OFB) cipher mode encryption/decryption, 128 bit key. * * @deprecated * This function preserves backwards compatibility. Use * @ref CRYPTO_AES_OFB128 instead. ******************************************************************************/ __STATIC_INLINE void AES_OFB128(uint8_t * out, const uint8_t * in, unsigned int len, const uint8_t * key, const uint8_t * iv) { CRYPTO_AES_OFB128(DEFAULT_CRYPTO, out, in, len, key, iv); } /***************************************************************************//** * @brief * AES Output feedback (OFB) cipher mode encryption/decryption, 256 bit key. * * @deprecated * This function preserves backwards compatibility. Use * @ref CRYPTO_AES_OFB256 instead. ******************************************************************************/ __STATIC_INLINE void AES_OFB256(uint8_t * out, const uint8_t * in, unsigned int len, const uint8_t * key, const uint8_t * iv) { CRYPTO_AES_OFB256(DEFAULT_CRYPTO, out, in, len, key, iv); } #ifdef __cplusplus } #endif /** @} (end addtogroup CRYPTO) */ /** @} (end addtogroup emlib) */ #endif /* defined(CRYPTO_COUNT) && (CRYPTO_COUNT > 0) */ #endif /* EM_CRYPTO_H */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/emlib/inc/em_emu.h.
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/***************************************************************************//** * @file * @brief Energy Management Unit (EMU) peripheral API * @version 5.7.0 ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * SPDX-License-Identifier: Zlib * * The licensor of this software is Silicon Laboratories Inc. * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be * appreciated but is not required. * 2. Altered source versions must be plainly marked as such, and must not be * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * ******************************************************************************/ #ifndef EM_EMU_H #define EM_EMU_H #include "em_device.h" #if defined(EMU_PRESENT) #include <stdbool.h> #include "em_bus.h" #ifdef __cplusplus extern "C" { #endif /***************************************************************************//** * @addtogroup emlib * @{ ******************************************************************************/ /***************************************************************************//** * @addtogroup EMU * @{ ******************************************************************************/ /******************************************************************************* ******************************* DEFINES *********************************** ******************************************************************************/ #if defined(_EMU_CTRL_EM23VSCALE_MASK) #define EMU_VSCALE_PRESENT #endif /******************************************************************************* ******************************** ENUMS ************************************ ******************************************************************************/ #if defined(_EMU_EM4CONF_OSC_MASK) /** EM4 duty oscillator. */ typedef enum { /** Select ULFRCO as duty oscillator in EM4. */ emuEM4Osc_ULFRCO = EMU_EM4CONF_OSC_ULFRCO, /** Select LFXO as duty oscillator in EM4. */ emuEM4Osc_LFXO = EMU_EM4CONF_OSC_LFXO, /** Select LFRCO as duty oscillator in EM4. */ emuEM4Osc_LFRCO = EMU_EM4CONF_OSC_LFRCO } EMU_EM4Osc_TypeDef; #endif #if defined(_EMU_BUCTRL_PROBE_MASK) /** Backup Power Voltage Probe types. */ typedef enum { /** Disable voltage probe. */ emuProbe_Disable = EMU_BUCTRL_PROBE_DISABLE, /** Connect probe to VDD_DREG. */ emuProbe_VDDDReg = EMU_BUCTRL_PROBE_VDDDREG, /** Connect probe to BU_IN. */ emuProbe_BUIN = EMU_BUCTRL_PROBE_BUIN, /** Connect probe to BU_OUT. */ emuProbe_BUOUT = EMU_BUCTRL_PROBE_BUOUT } EMU_Probe_TypeDef; #endif #if defined(_EMU_PWRCONF_PWRRES_MASK) /** Backup Power Domain resistor selection. */ typedef enum { /** Main power and backup power connected with RES0 series resistance. */ emuRes_Res0 = EMU_PWRCONF_PWRRES_RES0, /** Main power and backup power connected with RES1 series resistance. */ emuRes_Res1 = EMU_PWRCONF_PWRRES_RES1, /** Main power and backup power connected with RES2 series resistance. */ emuRes_Res2 = EMU_PWRCONF_PWRRES_RES2, /** Main power and backup power connected with RES3 series resistance. */ emuRes_Res3 = EMU_PWRCONF_PWRRES_RES3, } EMU_Resistor_TypeDef; #endif #if defined(BU_PRESENT) && defined(_SILICON_LABS_32B_SERIES_0) /** Backup Power Domain power connection. */ typedef enum { /** No connection between main and backup power. */ emuPower_None = EMU_BUINACT_PWRCON_NONE, /** Main power and backup power connected through diode, allowing current from backup to main only. */ emuPower_BUMain = EMU_BUINACT_PWRCON_BUMAIN, /** Main power and backup power connected through diode, allowing current from main to backup only. */ emuPower_MainBU = EMU_BUINACT_PWRCON_MAINBU, /** Main power and backup power connected without diode. */ emuPower_NoDiode = EMU_BUINACT_PWRCON_NODIODE, } EMU_Power_TypeDef; #endif #if defined(_EMU_BUCTRL_BUINACTPWRCON_MASK) /** Backup Power Domain power connection configuration when not in backup mode selection. */ typedef enum { /** No connection. */ emuBuBuInactPwrCon_None = EMU_BUCTRL_BUINACTPWRCON_NONE, /** Allow power from backup to main. */ emuBuBuInactPwrCon_MainBu = EMU_BUCTRL_BUINACTPWRCON_MAINBU, /** Allow power from main to backup. */ emuBuBuInactPwrCon_BuMain = EMU_BUCTRL_BUINACTPWRCON_BUMAIN, /** Backup and main power are connected. */ emuBuBuInactPwrCon_NoDiode = EMU_BUCTRL_BUINACTPWRCON_NODIODE, } EMU_BUBuInactPwrCon_TypeDef; #endif #if defined(_EMU_BUCTRL_BUACTPWRCON_MASK) /** Backup Power Domain power connection configuration in backup mode selection. */ typedef enum { /** No connection. */ emuBuBuActPwrCon_None = EMU_BUCTRL_BUACTPWRCON_NONE, /** Allow power from backup to main. */ emuBuBuActPwrCon_MainBu = EMU_BUCTRL_BUACTPWRCON_MAINBU, /** Allow power from main to backup. */ emuBuBuActPwrCon_BuMain = EMU_BUCTRL_BUACTPWRCON_BUMAIN, /** Backup and main power are connected. */ emuBuBuActPwrCon_NoDiode = EMU_BUCTRL_BUACTPWRCON_NODIODE, } EMU_BUBuActPwrCon_TypeDef; #endif #if defined(_EMU_BUCTRL_PWRRES_MASK) /** Backup Power Domain resistor selection. */ typedef enum { /** Main power and backup power connected with RES0 series resistance. */ emuBuPwrRes_Res0 = EMU_BUCTRL_PWRRES_RES0, /** Main power and backup power connected with RES1 series resistance. */ emuBuPwrRes_Res1 = EMU_BUCTRL_PWRRES_RES1, /** Main power and backup power connected with RES2 series resistance. */ emuBuPwrRes_Res2 = EMU_BUCTRL_PWRRES_RES2, /** Main power and backup power connected with RES3 series resistance. */ emuBuPwrRes_Res3 = EMU_BUCTRL_PWRRES_RES3, } EMU_BUPwrRes_TypeDef; #endif #if defined(_EMU_BUCTRL_VOUTRES_MASK) /** Resistance between backup domain power supply and BU_VOUT. */ typedef enum { /** BU_VOUT is not connected. */ emuBuVoutRes_Dis = EMU_BUCTRL_VOUTRES_DIS, /** Enable weak switch. */ emuBuVoutRes_Weak = EMU_BUCTRL_VOUTRES_WEAK, /** Enable medium switch. */ emuBuVoutRes_Med = EMU_BUCTRL_VOUTRES_MED, /** Enable strong switch. */ emuBuVoutRes_Strong = EMU_BUCTRL_VOUTRES_STRONG, } EMU_BUVoutRes_TypeDef; #endif /** BOD threshold setting selector, active or inactive mode. */ typedef enum { /** Configure BOD threshold for active mode. */ emuBODMode_Active, /** Configure BOD threshold for inactive mode. */ emuBODMode_Inactive, } EMU_BODMode_TypeDef; /** EM4 modes. */ typedef enum { /** EM4 Shutoff. */ emuEM4Shutoff = 0, /** EM4 Hibernate. */ emuEM4Hibernate = 1, } EMU_EM4State_TypeDef; #if defined(_EMU_EM4CTRL_EM4IORETMODE_MASK) typedef enum { /** No Retention: Pads enter reset state when entering EM4. */ emuPinRetentionDisable = EMU_EM4CTRL_EM4IORETMODE_DISABLE, /** Retention through EM4: Pads enter reset state when exiting EM4. */ emuPinRetentionEm4Exit = EMU_EM4CTRL_EM4IORETMODE_EM4EXIT, /** Retention through EM4 and wakeup: call @ref EMU_UnlatchPinRetention() to release pins from retention after EM4 wakeup. */ emuPinRetentionLatch = EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH, } EMU_EM4PinRetention_TypeDef; #endif /** Power configurations. DCDC-to-DVDD is currently the only supported mode. */ typedef enum { /** DCDC is connected to DVDD. */ emuPowerConfig_DcdcToDvdd, } EMU_PowerConfig_TypeDef; #if defined(_EMU_DCDCCTRL_MASK) /** DCDC operating modes. */ typedef enum { /** DCDC regulator bypass. */ emuDcdcMode_Bypass = EMU_DCDCCTRL_DCDCMODE_BYPASS, /** DCDC low-noise mode. */ emuDcdcMode_LowNoise = EMU_DCDCCTRL_DCDCMODE_LOWNOISE, #if defined(_EMU_DCDCLPEM01CFG_MASK) /** DCDC low-power mode. */ emuDcdcMode_LowPower = EMU_DCDCCTRL_DCDCMODE_LOWPOWER, #endif } EMU_DcdcMode_TypeDef; #endif #if defined(_EMU_DCDCCTRL_MASK) /** DCDC conduction modes. */ typedef enum { /** DCDC Low-Noise Continuous Conduction Mode (CCM). EFR32 interference minimization features are available in this mode. */ emuDcdcConductionMode_ContinuousLN, /** DCDC Low-Noise Discontinuous Conduction Mode (DCM). This mode should be used for EFM32 or for EFR32 when its radio is not enabled. */ emuDcdcConductionMode_DiscontinuousLN, } EMU_DcdcConductionMode_TypeDef; #endif #if defined(_EMU_PWRCTRL_MASK) /** DCDC to DVDD mode analog peripheral power supply select. */ typedef enum { /** Select AVDD as analog power supply. Typically lower noise, but less energy efficient. */ emuDcdcAnaPeripheralPower_AVDD = EMU_PWRCTRL_ANASW_AVDD, /** Select DCDC (DVDD) as analog power supply. Typically more energy efficient, but more noise. */ emuDcdcAnaPeripheralPower_DCDC = EMU_PWRCTRL_ANASW_DVDD } EMU_DcdcAnaPeripheralPower_TypeDef; #endif #if defined(_EMU_DCDCMISCCTRL_MASK) /** DCDC Forced CCM and reverse current limiter control. Positive values have unit mA. */ typedef int16_t EMU_DcdcLnReverseCurrentControl_TypeDef; /** High efficiency mode. EMU_DCDCZDETCTRL_ZDETILIMSEL is "don't care". */ #define emuDcdcLnHighEfficiency -1 /** Default reverse current for fast transient response mode (low noise). */ #define emuDcdcLnFastTransient 160 #endif #if defined(_EMU_DCDCCTRL_MASK) /** DCDC Low-noise RCO band select. */ typedef enum { /** Set RCO to 3MHz. */ emuDcdcLnRcoBand_3MHz = 0, /** Set RCO to 4MHz. */ emuDcdcLnRcoBand_4MHz = 1, /** Set RCO to 5MHz. */ emuDcdcLnRcoBand_5MHz = 2, /** Set RCO to 6MHz. */ emuDcdcLnRcoBand_6MHz = 3, /** Set RCO to 7MHz. */ emuDcdcLnRcoBand_7MHz = 4, /** Set RCO to 8MHz. */ emuDcdcLnRcoBand_8MHz = 5, /** Set RCO to 9MHz. */ emuDcdcLnRcoBand_9MHz = 6, /** Set RCO to 10MHz. */ emuDcdcLnRcoBand_10MHz = 7, } EMU_DcdcLnRcoBand_TypeDef; /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ /* Deprecated. */ #define EMU_DcdcLnRcoBand_3MHz emuDcdcLnRcoBand_3MHz #define EMU_DcdcLnRcoBand_4MHz emuDcdcLnRcoBand_4MHz #define EMU_DcdcLnRcoBand_5MHz emuDcdcLnRcoBand_5MHz #define EMU_DcdcLnRcoBand_6MHz emuDcdcLnRcoBand_6MHz #define EMU_DcdcLnRcoBand_7MHz emuDcdcLnRcoBand_7MHz #define EMU_DcdcLnRcoBand_8MHz emuDcdcLnRcoBand_8MHz #define EMU_DcdcLnRcoBand_9MHz emuDcdcLnRcoBand_9MHz #define EMU_DcdcLnRcoBand_10MHz emuDcdcLnRcoBand_10MHz /** @endcond */ #endif #if defined(_EMU_DCDCCTRL_MASK) /** DCDC Low Noise Compensator Control register. */ typedef enum { /** DCDC capacitor is 1uF. */ emuDcdcLnCompCtrl_1u0F, /** DCDC capacitor is 4.7uF. */ emuDcdcLnCompCtrl_4u7F, } EMU_DcdcLnCompCtrl_TypeDef; #endif #if defined(EMU_STATUS_VMONRDY) /** VMON channels. */ typedef enum { emuVmonChannel_AVDD, emuVmonChannel_ALTAVDD, emuVmonChannel_DVDD, emuVmonChannel_IOVDD0, #if defined(_EMU_VMONIO1CTRL_EN_MASK) emuVmonChannel_IOVDD1, #endif #if defined(_EMU_VMONBUVDDCTRL_EN_MASK) emuVmonChannel_BUVDD, #endif } EMU_VmonChannel_TypeDef; #endif /* EMU_STATUS_VMONRDY */ #if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) /** Bias mode configurations. */ typedef enum { emuBiasMode_1KHz, emuBiasMode_4KHz, emuBiasMode_Continuous } EMU_BiasMode_TypeDef; #endif #if defined(EMU_VSCALE_PRESENT) /** Supported EM0/1 Voltage Scaling Levels. */ typedef enum { /** High-performance voltage level. HF clock can be set to any frequency. */ emuVScaleEM01_HighPerformance = _EMU_STATUS_VSCALE_VSCALE2, /** Low-power optimized voltage level. HF clock must be limited to @ref CMU_VSCALEEM01_LOWPOWER_VOLTAGE_CLOCK_MAX Hz at this voltage. EM0/1 voltage scaling is applied when core clock frequency is changed from @ref CMU or when calling @ref EMU_EM01Init() when HF clock is already below the limit. */ emuVScaleEM01_LowPower = _EMU_STATUS_VSCALE_VSCALE0, } EMU_VScaleEM01_TypeDef; #endif #if defined(EMU_VSCALE_PRESENT) /** Supported EM2/3 Voltage Scaling Levels. */ typedef enum { /** Fast-wakeup voltage level. */ emuVScaleEM23_FastWakeup = _EMU_CTRL_EM23VSCALE_VSCALE2, /** Low-power optimized voltage level. Using this voltage level in EM2 and 3 adds approximately 30 us to wakeup time if EM0 and 1 voltage must be scaled up to @ref emuVScaleEM01_HighPerformance on EM2 or 3 exit. */ emuVScaleEM23_LowPower = _EMU_CTRL_EM23VSCALE_VSCALE0, } EMU_VScaleEM23_TypeDef; #endif #if defined(_EMU_CTRL_EM4HVSCALE_MASK) /** Supported EM4H Voltage Scaling Levels */ typedef enum { /** Fast-wakeup voltage level. */ emuVScaleEM4H_FastWakeup = _EMU_CTRL_EM4HVSCALE_VSCALE2, /** Low-power optimized voltage level. Using this voltage level in EM4H adds approximately 30 us to wakeup time if EM0 and 1 voltage must be scaled up to @ref emuVScaleEM01_HighPerformance on EM4H exit. */ emuVScaleEM4H_LowPower = _EMU_CTRL_EM4HVSCALE_VSCALE0, } EMU_VScaleEM4H_TypeDef; #endif #if defined(_EMU_EM23PERNORETAINCTRL_MASK) /** Peripheral EM2 and 3 retention control. */ typedef enum { #if defined(_EMU_EM23PERNORETAINCTRL_USBDIS_MASK) emuPeripheralRetention_USB = _EMU_EM23PERNORETAINCTRL_USBDIS_MASK, /* Select USB retention control. */ #endif #if defined(_EMU_EM23PERNORETAINCTRL_RTCDIS_MASK) emuPeripheralRetention_RTC = _EMU_EM23PERNORETAINCTRL_RTCDIS_MASK, /* Select RTC retention control. */ #endif #if defined(_EMU_EM23PERNORETAINCTRL_ACMP3DIS_MASK) emuPeripheralRetention_ACMP3 = _EMU_EM23PERNORETAINCTRL_ACMP3DIS_MASK, /* Select ACMP3 retention control. */ #endif #if defined(_EMU_EM23PERNORETAINCTRL_ACMP2DIS_MASK) emuPeripheralRetention_ACMP2 = _EMU_EM23PERNORETAINCTRL_ACMP2DIS_MASK, /* Select ACMP2 retention control. */ #endif #if defined(_EMU_EM23PERNORETAINCTRL_ADC1DIS_MASK) emuPeripheralRetention_ADC1 = _EMU_EM23PERNORETAINCTRL_ADC1DIS_MASK, /* Select ADC1 retention control. */ #endif #if defined(_EMU_EM23PERNORETAINCTRL_I2C2DIS_MASK) emuPeripheralRetention_I2C2 = _EMU_EM23PERNORETAINCTRL_I2C2DIS_MASK, /* Select I2C2 retention control. */ #endif #if defined(_EMU_EM23PERNORETAINCTRL_LETIMER1DIS_MASK) emuPeripheralRetention_LETIMER1 = _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_MASK, /* Select LETIMER1 retention control. */ #endif #if defined(_EMU_EM23PERNORETAINCTRL_LCDDIS_MASK) emuPeripheralRetention_LCD = _EMU_EM23PERNORETAINCTRL_LCDDIS_MASK, /* Select LCD retention control. */ #endif #if defined(_EMU_EM23PERNORETAINCTRL_LEUART1DIS_MASK) emuPeripheralRetention_LEUART1 = _EMU_EM23PERNORETAINCTRL_LEUART1DIS_MASK, /* Select LEUART1 retention control. */ #endif emuPeripheralRetention_LEUART0 = _EMU_EM23PERNORETAINCTRL_LEUART0DIS_MASK, /* Select LEUART0 retention control. */ #if defined(_EMU_EM23PERNORETAINCTRL_CSENDIS_MASK) emuPeripheralRetention_CSEN = _EMU_EM23PERNORETAINCTRL_CSENDIS_MASK, /* Select CSEN retention control. */ #endif emuPeripheralRetention_LESENSE0 = _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_MASK, /* Select LESENSE0 retention control. */ #if defined(_EMU_EM23PERNORETAINCTRL_WDOG1DIS_MASK) emuPeripheralRetention_WDOG1 = _EMU_EM23PERNORETAINCTRL_WDOG1DIS_MASK, /* Select WDOG1 retention control. */ #endif emuPeripheralRetention_WDOG0 = _EMU_EM23PERNORETAINCTRL_WDOG0DIS_MASK, /* Select WDOG0 retention control. */ emuPeripheralRetention_LETIMER0 = _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_MASK, /* Select LETIMER0 retention control. */ emuPeripheralRetention_ADC0 = _EMU_EM23PERNORETAINCTRL_ADC0DIS_MASK, /* Select ADC0 retention control. */ #if defined(_EMU_EM23PERNORETAINCTRL_IDAC0DIS_MASK) emuPeripheralRetention_IDAC0 = _EMU_EM23PERNORETAINCTRL_IDAC0DIS_MASK, /* Select IDAC0 retention control. */ #endif #if defined(_EMU_EM23PERNORETAINCTRL_VDAC0DIS_MASK) emuPeripheralRetention_VDAC0 = _EMU_EM23PERNORETAINCTRL_VDAC0DIS_MASK, /* Select VDAC0 retention control. */ #endif #if defined(_EMU_EM23PERNORETAINCTRL_I2C1DIS_MASK) emuPeripheralRetention_I2C1 = _EMU_EM23PERNORETAINCTRL_I2C1DIS_MASK, /* Select I2C1 retention control. */ #endif emuPeripheralRetention_I2C0 = _EMU_EM23PERNORETAINCTRL_I2C0DIS_MASK, /* Select I2C0 retention control. */ emuPeripheralRetention_ACMP1 = _EMU_EM23PERNORETAINCTRL_ACMP1DIS_MASK, /* Select ACMP1 retention control. */ emuPeripheralRetention_ACMP0 = _EMU_EM23PERNORETAINCTRL_ACMP0DIS_MASK, /* Select ACMP0 retention control. */ #if defined(_EMU_EM23PERNORETAINCTRL_PCNT1DIS_MASK) emuPeripheralRetention_PCNT2 = _EMU_EM23PERNORETAINCTRL_PCNT2DIS_MASK, /* Select PCNT2 retention control. */ emuPeripheralRetention_PCNT1 = _EMU_EM23PERNORETAINCTRL_PCNT1DIS_MASK, /* Select PCNT1 retention control. */ #endif emuPeripheralRetention_PCNT0 = _EMU_EM23PERNORETAINCTRL_PCNT0DIS_MASK, /* Select PCNT0 retention control. */ emuPeripheralRetention_D1 = _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_MASK | _EMU_EM23PERNORETAINCTRL_PCNT0DIS_MASK | _EMU_EM23PERNORETAINCTRL_ADC0DIS_MASK | _EMU_EM23PERNORETAINCTRL_ACMP0DIS_MASK | _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_MASK,/* Select all peripherals in domain 1. */ emuPeripheralRetention_D2 = _EMU_EM23PERNORETAINCTRL_ACMP1DIS_MASK #if defined(_EMU_EM23PERNORETAINCTRL_IDAC0DIS_MASK) | _EMU_EM23PERNORETAINCTRL_IDAC0DIS_MASK #endif #if defined(_EMU_EM23PERNORETAINCTRL_VDAC0DIS_MASK) | _EMU_EM23PERNORETAINCTRL_VDAC0DIS_MASK #endif #if defined(_EMU_EM23PERNORETAINCTRL_CSENDIS_MASK) | _EMU_EM23PERNORETAINCTRL_CSENDIS_MASK #endif | _EMU_EM23PERNORETAINCTRL_LEUART0DIS_MASK #if defined(_EMU_EM23PERNORETAINCTRL_USBDIS_MASK) | _EMU_EM23PERNORETAINCTRL_USBDIS_MASK #endif #if defined(_EMU_EM23PERNORETAINCTRL_RTCDIS_MASK) | _EMU_EM23PERNORETAINCTRL_RTCDIS_MASK #endif #if defined(_EMU_EM23PERNORETAINCTRL_ACMP3DIS_MASK) | _EMU_EM23PERNORETAINCTRL_ACMP3DIS_MASK #endif #if defined(_EMU_EM23PERNORETAINCTRL_ACMP2DIS_MASK) | _EMU_EM23PERNORETAINCTRL_ACMP2DIS_MASK #endif #if defined(_EMU_EM23PERNORETAINCTRL_ADC1DIS_MASK) | _EMU_EM23PERNORETAINCTRL_ADC1DIS_MASK #endif #if defined(_EMU_EM23PERNORETAINCTRL_I2C2DIS_MASK) | _EMU_EM23PERNORETAINCTRL_I2C2DIS_MASK #endif #if defined(_EMU_EM23PERNORETAINCTRL_LETIMER1DIS_MASK) | _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_MASK #endif #if defined(_EMU_EM23PERNORETAINCTRL_LCDDIS_MASK) | _EMU_EM23PERNORETAINCTRL_LCDDIS_MASK #endif #if defined(_EMU_EM23PERNORETAINCTRL_LEUART1DIS_MASK) | _EMU_EM23PERNORETAINCTRL_LEUART1DIS_MASK #endif #if defined(_EMU_EM23PERNORETAINCTRL_PCNT1DIS_MASK) | _EMU_EM23PERNORETAINCTRL_PCNT1DIS_MASK | _EMU_EM23PERNORETAINCTRL_PCNT2DIS_MASK #endif #if defined(_EMU_EM23PERNORETAINCTRL_I2C1DIS_MASK) | _EMU_EM23PERNORETAINCTRL_I2C1DIS_MASK /* Select all peripherals in domain 2. */ #endif | _EMU_EM23PERNORETAINCTRL_I2C0DIS_MASK, emuPeripheralRetention_ALL = emuPeripheralRetention_D1 | emuPeripheralRetention_D2 #if defined(_EMU_EM23PERNORETAINCTRL_WDOG1DIS_MASK) | emuPeripheralRetention_WDOG1 #endif | emuPeripheralRetention_WDOG0, /* Select all peripherals with retention control. */ } EMU_PeripheralRetention_TypeDef; #endif /******************************************************************************* ******************************* STRUCTS *********************************** ******************************************************************************/ #if defined(EMU_VSCALE_PRESENT) /** EM0 and 1 initialization structure. Voltage scaling is applied when the core clock frequency is changed from @ref CMU. EM0 and 1 emuVScaleEM01_HighPerformance is always enabled. */ typedef struct { bool vScaleEM01LowPowerVoltageEnable; /**< EM0/1 low power voltage status. */ } EMU_EM01Init_TypeDef; #endif #if defined(EMU_VSCALE_PRESENT) /** Default initialization of EM0 and 1 configuration. */ #define EMU_EM01INIT_DEFAULT \ { \ false /** Do not scale down in EM0/1.*/ \ } #endif /** EM2 and 3 initialization structure. */ typedef struct { bool em23VregFullEn; /**< Enable full VREG drive strength in EM2/3. */ #if defined(EMU_VSCALE_PRESENT) EMU_VScaleEM23_TypeDef vScaleEM23Voltage; /**< EM2/3 voltage scaling level. */ #endif } EMU_EM23Init_TypeDef; /** Default initialization of EM2 and 3 configuration. */ #if defined(EMU_VSCALE_PRESENT) #define EMU_EM23INIT_DEFAULT \ { \ false, /* Reduced voltage regulator drive strength in EM2/3.*/ \ emuVScaleEM23_FastWakeup, /* Do not scale down in EM2/3. */ \ } #else #define EMU_EM23INIT_DEFAULT \ { \ false, /* Reduced voltage regulator drive strength in EM2/3.*/ \ } #endif #if defined(_EMU_EM4CONF_MASK) || defined(_EMU_EM4CTRL_MASK) /** EM4 initialization structure. */ typedef struct { #if defined(_EMU_EM4CONF_MASK) /* Initialization parameters for platforms with EMU->EM4CONF register (Series 0). */ bool lockConfig; /**< Lock configuration of regulator, BOD and oscillator. */ bool buBodRstDis; /**< When set, no reset will be asserted due to Brownout when in EM4. */ EMU_EM4Osc_TypeDef osc; /**< EM4 duty oscillator. */ bool buRtcWakeup; /**< Wake up on EM4 BURTC interrupt. */ bool vreg; /**< Enable EM4 voltage regulator. */ #elif defined(_EMU_EM4CTRL_MASK) /* Initialization parameters for platforms with EMU->EM4CTRL register (Series 1). */ bool retainLfxo; /**< Disable LFXO upon EM4 entry. */ bool retainLfrco; /**< Disable LFRCO upon EM4 entry. */ bool retainUlfrco; /**< Disable ULFRCO upon EM4 entry. */ EMU_EM4State_TypeDef em4State; /**< Hibernate or shutoff EM4 state. */ EMU_EM4PinRetention_TypeDef pinRetentionMode; /**< EM4 pin retention mode. */ #endif #if defined(_EMU_CTRL_EM4HVSCALE_MASK) EMU_VScaleEM4H_TypeDef vScaleEM4HVoltage;/**< EM4H voltage scaling level. */ #endif } EMU_EM4Init_TypeDef; #endif #if defined(_EMU_EM4CONF_MASK) /** Default initialization of EM4 configuration (Series 0). */ #define EMU_EM4INIT_DEFAULT \ { \ false, /* Do not lock configuration after it's been set. */ \ false, /* No reset will be asserted due to BOD in EM4. */ \ emuEM4Osc_ULFRCO, /* Use default ULFRCO oscillator. */ \ true, /* Wake up on EM4 BURTC interrupt. */ \ true, /* Enable VREG. */ \ } #elif defined(_EMU_CTRL_EM4HVSCALE_MASK) /** Default initialization of EM4 configuration (Series 1 with VSCALE). */ #define EMU_EM4INIT_DEFAULT \ { \ false, /* Retain LFXO configuration upon EM4 entry. */ \ false, /* Retain LFRCO configuration upon EM4 entry. */ \ false, /* Retain ULFRCO configuration upon EM4 entry. */ \ emuEM4Shutoff, /* Use EM4 shutoff state. */ \ emuPinRetentionDisable, /* Do not retain pins in EM4. */ \ emuVScaleEM4H_FastWakeup, /* Do not scale down in EM4H. */ \ } #elif defined(_EMU_EM4CTRL_MASK) /** Default initialization of EM4 configuration (Series 1 without VSCALE). */ #define EMU_EM4INIT_DEFAULT \ { \ false, /* Retain LFXO configuration upon EM4 entry. */ \ false, /* Retain LFRCO configuration upon EM4 entry. */ \ false, /* Retain ULFRCO configuration upon EM4 entry. */ \ emuEM4Shutoff, /* Use EM4 shutoff state. */ \ emuPinRetentionDisable, /* Do not retain pins in EM4. */ \ } #endif #if defined(BU_PRESENT) && defined(_SILICON_LABS_32B_SERIES_0) /** Backup Power Domain Initialization structure. */ typedef struct { /* Backup Power Domain power configuration. */ /** Voltage probe select, selects ADC voltage. */ EMU_Probe_TypeDef probe; /** Enable BOD calibration mode. */ bool bodCal; /** Enable BU_STAT status pin for active BU mode. */ bool statusPinEnable; /* Backup Power Domain connection configuration. */ /** Power domain resistor. */ EMU_Resistor_TypeDef resistor; /** BU_VOUT strong enable. */ bool voutStrong; /** BU_VOUT medium enable. */ bool voutMed; /** BU_VOUT weak enable. */ bool voutWeak; /** Power connection, when not in Backup Mode. */ EMU_Power_TypeDef inactivePower; /** Power connection, when in Backup Mode. */ EMU_Power_TypeDef activePower; /** Enable backup power domain, and release reset, enable BU_VIN pin. */ bool enable; } EMU_BUPDInit_TypeDef; /** Default Backup Power Domain configuration. */ #define EMU_BUPDINIT_DEFAULT \ { \ emuProbe_Disable, /* Do not enable voltage probe. */ \ false, /* Disable BOD calibration mode. */ \ false, /* Disable BU_STAT pin for backup mode indication. */ \ \ emuRes_Res0, /* RES0 series resistance between main and backup power. */ \ false, /* Do not enable strong switch. */ \ false, /* Do not enable medium switch. */ \ false, /* Do not enable weak switch. */ \ \ emuPower_None, /* No connection between main and backup power. (inactive mode) */ \ emuPower_None, /* No connection between main and backup power. (active mode) */ \ true /* Enable BUPD enter on BOD, enable BU_VIN pin, release BU reset. */ \ } #endif #if defined(BU_PRESENT) && defined(_SILICON_LABS_32B_SERIES_1) /** Backup Power Domain Initialization structure. */ typedef struct { bool disMaxComp; /**< Disable MAIN-BU Comparator. */ EMU_BUBuInactPwrCon_TypeDef inactivePwrCon; /**< Power connection configuration when not in backup mode. */ EMU_BUBuActPwrCon_TypeDef activePwrCon; /**< Power connection configuration when in backup mode. */ EMU_BUPwrRes_TypeDef pwrRes; /**< Power domain resistor. */ EMU_BUVoutRes_TypeDef voutRes; /**< BU_VOUT resistor select. */ bool buVinProbeEn; /**< Enable BU_VIN probing. */ bool staEn; /**< Enable backup mode status export. */ bool enable; /**< Enable backup power domain. */ } EMU_BUInit_TypeDef; /** Default Backup Power Domain configuration. */ #define EMU_BUINIT_DEFAULT \ { \ false, /**< MAIN-BU Comparator is not disabloed */ \ emuBuBuInactPwrCon_None, /**< No power connection wen not in backup mode */ \ emuBuBuActPwrCon_None, /**< No power connection when in backup mode */ \ emuBuPwrRes_Res0, /**< RES0 series resistance between main and backup power. */ \ emuBuVoutRes_Dis, /**< Vout resistor is set to not connected */ \ false, /**< BU_VIN probe is disabled */ \ false, /**< Status export is disabled */ \ true /**< Enable backup mode */ \ } #endif #if defined(_EMU_DCDCCTRL_MASK) /** DCDC initialization structure. */ typedef struct { EMU_PowerConfig_TypeDef powerConfig; /**< Device external power configuration. @ref emuPowerConfig_DcdcToDvdd is currently the only supported mode. */ EMU_DcdcMode_TypeDef dcdcMode; /**< DCDC regulator operating mode in EM0/1. */ uint16_t mVout; /**< Target output voltage (mV). */ uint16_t em01LoadCurrent_mA; /**< Estimated average load current in EM0/1. (mA). This estimate is also used for EM1 optimization; if EM1 current is expected to be higher than EM0, then this parameter should hold the higher EM1 current. */ uint16_t em234LoadCurrent_uA; /**< Estimated average load current in EM2 (uA). This estimate is also used for EM3 and 4 optimization; if EM3 or 4 current is expected to be higher than EM2, then this parameter should hold the higher EM3 or 4 current. */ uint16_t maxCurrent_mA; /**< Maximum average DCDC output current (mA). This can be set to the maximum for the power source, for example the maximum for a battery. */ EMU_DcdcAnaPeripheralPower_TypeDef anaPeripheralPower; /**< Select analog peripheral power in DCDC-to-DVDD mode. */ EMU_DcdcLnReverseCurrentControl_TypeDef reverseCurrentControl; /**< Low-noise reverse current control. NOTE: this parameter uses special encoding: >= 0 is forced CCM mode where the parameter is used as the reverse current threshold in mA. -1 is encoded as emuDcdcLnHighEfficiencyMode (EFM32 only). */ EMU_DcdcLnCompCtrl_TypeDef dcdcLnCompCtrl; /**< DCDC Low-noise mode compensator control. */ } EMU_DCDCInit_TypeDef; /** Default DCDC initialization. */ #if defined(_EFM_DEVICE) #if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) #define EMU_DCDCINIT_DEFAULT \ { \ emuPowerConfig_DcdcToDvdd, /* DCDC to DVDD. */ \ emuDcdcMode_LowNoise, /* Low-noise mode in EM0. */ \ 1800, /* Nominal output voltage for DVDD mode, 1.8V. */ \ 5, /* Nominal EM0/1 load current of less than 5mA. */ \ 10, /* Nominal EM2/3/4 load current less than 10uA. */ \ 200, /* Maximum average current of 200mA (assume strong battery or other power source). */ \ emuDcdcAnaPeripheralPower_DCDC,/* Select DCDC as analog power supply (lower power). */ \ emuDcdcLnHighEfficiency, /* Use high-efficiency mode. */ \ emuDcdcLnCompCtrl_1u0F, /* 1uF DCDC capacitor. */ \ } #else #define EMU_DCDCINIT_DEFAULT \ { \ emuPowerConfig_DcdcToDvdd, /* DCDC to DVDD. */ \ emuDcdcMode_LowPower, /* Low-power mode in EM0. */ \ 1800, /* Nominal output voltage for DVDD mode, 1.8V. */ \ 5, /* Nominal EM0/1 load current of less than 5mA. */ \ 10, /* Nominal EM2/3/4 load current less than 10uA. */ \ 200, /* Maximum average current of 200mA (assume strong battery or other power source). */ \ emuDcdcAnaPeripheralPower_AVDD,/* Select AVDD as analog power supply). */ \ emuDcdcLnHighEfficiency, /* Use high-efficiency mode. */ \ emuDcdcLnCompCtrl_4u7F, /* 4.7uF DCDC capacitor. */ \ } #endif #else /* EFR32 device. */ #if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) #define EMU_DCDCINIT_DEFAULT \ { \ emuPowerConfig_DcdcToDvdd, /* DCDC to DVDD. */ \ emuDcdcMode_LowNoise, /* Low-noise mode in EM0. */ \ 1800, /* Nominal output voltage for DVDD mode, 1.8V. */ \ 15, /* Nominal EM0/1 load current of less than 15mA. */ \ 10, /* Nominal EM2/3/4 load current less than 10uA. */ \ 200, /* Maximum average current of 200mA (assume strong battery or other power source). */ \ emuDcdcAnaPeripheralPower_DCDC,/* Select DCDC as analog power supply (lower power). */ \ 160, /* Maximum reverse current of 160mA. */ \ emuDcdcLnCompCtrl_1u0F, /* 1uF DCDC capacitor. */ \ } #else #define EMU_DCDCINIT_DEFAULT \ { \ emuPowerConfig_DcdcToDvdd, /* DCDC to DVDD. */ \ emuDcdcMode_LowNoise, /* Low-noise mode in EM0. */ \ 1800, /* Nominal output voltage for DVDD mode, 1.8V. */ \ 15, /* Nominal EM0/1 load current of less than 15mA. */ \ 10, /* Nominal EM2/3/4 load current less than 10uA. */ \ 200, /* Maximum average current of 200mA (assume strong battery or other power source). */ \ emuDcdcAnaPeripheralPower_DCDC,/* Select DCDC as analog power supply (lower power). */ \ 160, /* Maximum reverse current of 160mA. */ \ emuDcdcLnCompCtrl_4u7F, /* 4.7uF DCDC capacitor. */ \ } #endif #endif #endif #if defined(EMU_STATUS_VMONRDY) /** VMON initialization structure. */ typedef struct { EMU_VmonChannel_TypeDef channel; /**< VMON channel to configure. */ int threshold; /**< Trigger threshold (mV). Supported range is 1620 mV to 3400 mV. */ bool riseWakeup; /**< Wake up from EM4H on rising edge. */ bool fallWakeup; /**< Wake up from EM4H on falling edge. */ bool enable; /**< Enable VMON channel. */ bool retDisable; /**< Disable IO0 retention when voltage drops below threshold (IOVDD only). */ } EMU_VmonInit_TypeDef; /** Default VMON initialization structure. */ #define EMU_VMONINIT_DEFAULT \ { \ emuVmonChannel_AVDD, /* AVDD VMON channel. */ \ 3200, /* 3.2 V threshold. */ \ false, /* Do not wake from EM4H on rising edge. */ \ false, /* Do not wake from EM4H on falling edge. */ \ true, /* Enable VMON channel. */ \ false /* Do not disable IO0 retention */ \ } /** VMON Hysteresis initialization structure. */ typedef struct { EMU_VmonChannel_TypeDef channel; /**< VMON channel to configure. */ int riseThreshold; /**< Rising threshold (mV). */ int fallThreshold; /**< Falling threshold (mV). */ bool riseWakeup; /**< Wake up from EM4H on rising edge. */ bool fallWakeup; /**< Wake up from EM4H on falling edge. */ bool enable; /**< Enable VMON channel. */ } EMU_VmonHystInit_TypeDef; /** Default VMON Hysteresis initialization structure. */ #define EMU_VMONHYSTINIT_DEFAULT \ { \ emuVmonChannel_AVDD, /* AVDD VMON channel. */ \ 3200, /* 3.2 V rise threshold. */ \ 3200, /* 3.2 V fall threshold. */ \ false, /* Do not wake from EM4H on rising edge. */ \ false, /* Do not wake from EM4H on falling edge. */ \ true /* Enable VMON channel. */ \ } #endif /* EMU_STATUS_VMONRDY */ /******************************************************************************* ***************************** PROTOTYPES ********************************** ******************************************************************************/ #if defined(EMU_VSCALE_PRESENT) void EMU_EM01Init(const EMU_EM01Init_TypeDef *em01Init); #endif void EMU_EM23Init(const EMU_EM23Init_TypeDef *em23Init); #if defined(_EMU_EM4CONF_MASK) || defined(_EMU_EM4CTRL_MASK) void EMU_EM4Init(const EMU_EM4Init_TypeDef *em4Init); #endif void EMU_EnterEM2(bool restore); void EMU_EnterEM3(bool restore); void EMU_Save(void); void EMU_Restore(void); void EMU_EnterEM4(void); #if defined(_EMU_EM4CTRL_MASK) void EMU_EnterEM4H(void); void EMU_EnterEM4S(void); #endif void EMU_MemPwrDown(uint32_t blocks); void EMU_RamPowerDown(uint32_t start, uint32_t end); void EMU_RamPowerUp(void); #if defined(_EMU_EM23PERNORETAINCTRL_MASK) void EMU_PeripheralRetention(EMU_PeripheralRetention_TypeDef periMask, bool enable); #endif void EMU_UpdateOscConfig(void); #if defined(EMU_VSCALE_PRESENT) void EMU_VScaleEM01ByClock(uint32_t clockFrequency, bool wait); void EMU_VScaleEM01(EMU_VScaleEM01_TypeDef voltage, bool wait); #endif #if defined(BU_PRESENT) && defined(_SILICON_LABS_32B_SERIES_0) void EMU_BUPDInit(const EMU_BUPDInit_TypeDef *bupdInit); void EMU_BUThresholdSet(EMU_BODMode_TypeDef mode, uint32_t value); void EMU_BUThresRangeSet(EMU_BODMode_TypeDef mode, uint32_t value); #endif #if defined(BU_PRESENT) && defined(_SILICON_LABS_32B_SERIES_1) void EMU_BUInit(const EMU_BUInit_TypeDef *buInit); #endif #if defined(_EMU_BUCTRL_DISMAXCOMP_MASK) void EMU_BUDisMaxCompSet(bool disableMainBuComparator); #endif #if defined(_EMU_BUCTRL_BUINACTPWRCON_MASK) void EMU_BUBuInactPwrConSet(EMU_BUBuInactPwrCon_TypeDef inactPwrCon); #endif #if defined(_EMU_BUCTRL_BUACTPWRCON_MASK) void EMU_BUBuActPwrConSet(EMU_BUBuActPwrCon_TypeDef actPwrCon); #endif #if defined(_EMU_BUCTRL_PWRRES_MASK) void EMU_BUPwrResSet(EMU_BUPwrRes_TypeDef pwrRes); #endif #if defined(_EMU_BUCTRL_VOUTRES_MASK) void EMU_BUVoutResSet(EMU_BUVoutRes_TypeDef resistorSel); #endif #if defined(_EMU_BUCTRL_BUVINPROBEEN_MASK) void EMU_BUBuVinProbeEnSet(bool enable); #endif #if defined(_EMU_BUCTRL_STATEN_MASK) void EMU_BUStatEnSet(bool enable); #endif #if defined(_EMU_BUCTRL_EN_MASK) void EMU_BUEnableSet(bool enable); #endif #if defined(_EMU_DCDCCTRL_MASK) bool EMU_DCDCInit(const EMU_DCDCInit_TypeDef *dcdcInit); void EMU_DCDCModeSet(EMU_DcdcMode_TypeDef dcdcMode); void EMU_DCDCConductionModeSet(EMU_DcdcConductionMode_TypeDef conductionMode, bool rcoDefaultSet); bool EMU_DCDCOutputVoltageSet(uint32_t mV, bool setLpVoltage, bool setLnVoltage); void EMU_DCDCOptimizeSlice(uint32_t em0LoadCurrentmA); void EMU_DCDCLnRcoBandSet(EMU_DcdcLnRcoBand_TypeDef band); bool EMU_DCDCPowerOff(void); #endif #if defined(EMU_STATUS_VMONRDY) void EMU_VmonInit(const EMU_VmonInit_TypeDef *vmonInit); void EMU_VmonHystInit(const EMU_VmonHystInit_TypeDef *vmonInit); void EMU_VmonEnable(EMU_VmonChannel_TypeDef channel, bool enable); bool EMU_VmonChannelStatusGet(EMU_VmonChannel_TypeDef channel); #endif /***************************************************************************//** * @brief * Enter energy mode 1 (EM1). ******************************************************************************/ __STATIC_INLINE void EMU_EnterEM1(void) { /* Enter sleep mode. */ SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; __WFI(); } #if defined(EMU_VSCALE_PRESENT) /***************************************************************************//** * @brief * Wait for voltage scaling to complete. ******************************************************************************/ __STATIC_INLINE void EMU_VScaleWait(void) { while (BUS_RegBitRead(&EMU->STATUS, _EMU_STATUS_VSCALEBUSY_SHIFT) != 0U) { } } #endif #if defined(EMU_VSCALE_PRESENT) /***************************************************************************//** * @brief * Get current voltage scaling level. * * @return * Current voltage scaling level. ******************************************************************************/ __STATIC_INLINE EMU_VScaleEM01_TypeDef EMU_VScaleGet(void) { EMU_VScaleWait(); return (EMU_VScaleEM01_TypeDef)((uint32_t) ((EMU->STATUS & _EMU_STATUS_VSCALE_MASK) >> _EMU_STATUS_VSCALE_SHIFT)); } #endif #if defined(_EMU_STATUS_VMONRDY_MASK) /***************************************************************************//** * @brief * Get the status of the voltage monitor (VMON). * * @return * Status of the VMON. True if all the enabled channels are ready, false if * one or more of the enabled channels are not ready. ******************************************************************************/ __STATIC_INLINE bool EMU_VmonStatusGet(void) { return BUS_RegBitRead(&EMU->STATUS, _EMU_STATUS_VMONRDY_SHIFT) != 0U; } #endif /* _EMU_STATUS_VMONRDY_MASK */ #if defined(_EMU_IF_MASK) /***************************************************************************//** * @brief * Clear one or more pending EMU interrupts. * * @param[in] flags * Pending EMU interrupt sources to clear. Use one or more valid * interrupt flags for the EMU module (EMU_IFC_nnn). ******************************************************************************/ __STATIC_INLINE void EMU_IntClear(uint32_t flags) { #if defined(EMU_HAS_SET_CLEAR) EMU->IF_CLR = flags; #else EMU->IFC = flags; #endif } /***************************************************************************//** * @brief * Disable one or more EMU interrupts. * * @param[in] flags * EMU interrupt sources to disable. Use one or more valid * interrupt flags for the EMU module (EMU_IEN_nnn). ******************************************************************************/ __STATIC_INLINE void EMU_IntDisable(uint32_t flags) { #if defined(EMU_HAS_SET_CLEAR) EMU->IEN_CLR = flags; #else EMU->IEN &= ~flags; #endif } /***************************************************************************//** * @brief * Enable one or more EMU interrupts. * * @note * Depending on the use, a pending interrupt may already be set prior to * enabling the interrupt. To ignore a pending interrupt, consider using * @ref EMU_IntClear() prior to enabling the interrupt. * * @param[in] flags * EMU interrupt sources to enable. Use one or more valid * interrupt flags for the EMU module (EMU_IEN_nnn). ******************************************************************************/ __STATIC_INLINE void EMU_IntEnable(uint32_t flags) { #if defined(EMU_HAS_SET_CLEAR) EMU->IEN_SET = flags; #else EMU->IEN |= flags; #endif } /***************************************************************************//** * @brief * Get pending EMU interrupt flags. * * @note * Event bits are not cleared by the use of this function. * * @return * EMU interrupt sources pending. Returns one or more valid * interrupt flags for the EMU module (EMU_IF_nnn). ******************************************************************************/ __STATIC_INLINE uint32_t EMU_IntGet(void) { return EMU->IF; } /***************************************************************************//** * @brief * Get enabled and pending EMU interrupt flags. * Useful for handling more interrupt sources in the same interrupt handler. * * @note * Interrupt flags are not cleared by the use of this function. * * @return * Pending and enabled EMU interrupt sources * Return value is the bitwise AND of * - the enabled interrupt sources in EMU_IEN and * - the pending interrupt flags EMU_IF. ******************************************************************************/ __STATIC_INLINE uint32_t EMU_IntGetEnabled(void) { uint32_t ien; ien = EMU->IEN; return EMU->IF & ien; } /***************************************************************************//** * @brief * Set one or more pending EMU interrupts. * * @param[in] flags * EMU interrupt sources to set to pending. Use one or more valid * interrupt flags for the EMU module (EMU_IFS_nnn). ******************************************************************************/ __STATIC_INLINE void EMU_IntSet(uint32_t flags) { #if defined(EMU_HAS_SET_CLEAR) EMU->IF_SET = flags; #else EMU->IFS = flags; #endif } #endif /* _EMU_IF_MASK */ #if defined(_EMU_EM4CONF_LOCKCONF_MASK) /***************************************************************************//** * @brief * Enable or disable EM4 lock configuration. * @param[in] enable * If true, locks down EM4 configuration. ******************************************************************************/ __STATIC_INLINE void EMU_EM4Lock(bool enable) { BUS_RegBitWrite(&(EMU->EM4CONF), _EMU_EM4CONF_LOCKCONF_SHIFT, enable); } #endif #if defined(_EMU_STATUS_BURDY_MASK) /***************************************************************************//** * @brief * Halts until backup power functionality is ready. ******************************************************************************/ __STATIC_INLINE void EMU_BUReady(void) { while (!(EMU->STATUS & EMU_STATUS_BURDY)) ; } #endif #if defined(_EMU_ROUTE_BUVINPEN_MASK) /***************************************************************************//** * @brief * Disable BU_VIN support. * @param[in] enable * If true, enables BU_VIN input pin support, if false disables it. ******************************************************************************/ __STATIC_INLINE void EMU_BUPinEnable(bool enable) { BUS_RegBitWrite(&(EMU->ROUTE), _EMU_ROUTE_BUVINPEN_SHIFT, enable); } #endif /***************************************************************************//** * @brief * Lock EMU registers in order to protect them against unintended * modification. * * @note * If locking EMU registers, they must be unlocked prior to using any * EMU API functions modifying EMU registers, excluding interrupt control * and regulator control if the architecture has a EMU_PWRCTRL register. * An exception to this is the energy mode entering API (EMU_EnterEMn()), * which can be used when the EMU registers are locked. ******************************************************************************/ __STATIC_INLINE void EMU_Lock(void) { EMU->LOCK = 0x0; } /***************************************************************************//** * @brief * Unlock the EMU so that writing to locked registers again is possible. ******************************************************************************/ __STATIC_INLINE void EMU_Unlock(void) { EMU->LOCK = EMU_LOCK_LOCKKEY_UNLOCK; } #if defined(_EMU_PWRLOCK_MASK) /***************************************************************************//** * @brief * Lock the EMU regulator control registers in order to protect against * unintended modification. ******************************************************************************/ __STATIC_INLINE void EMU_PowerLock(void) { EMU->PWRLOCK = EMU_PWRLOCK_LOCKKEY_LOCK; } /***************************************************************************//** * @brief * Unlock the EMU power control registers so that writing to * locked registers again is possible. ******************************************************************************/ __STATIC_INLINE void EMU_PowerUnlock(void) { EMU->PWRLOCK = EMU_PWRLOCK_LOCKKEY_UNLOCK; } #endif #if defined(_EMU_CTRL_EM2BLOCK_MASK) /***************************************************************************//** * @brief * Block entering EM2 or higher number energy modes. ******************************************************************************/ __STATIC_INLINE void EMU_EM2Block(void) { BUS_RegBitWrite(&EMU->CTRL, _EMU_CTRL_EM2BLOCK_SHIFT, 1U); } /***************************************************************************//** * @brief * Unblock entering EM2 or higher number energy modes. ******************************************************************************/ __STATIC_INLINE void EMU_EM2UnBlock(void) { BUS_RegBitWrite(&EMU->CTRL, _EMU_CTRL_EM2BLOCK_SHIFT, 0U); } #endif #if defined(_EMU_EM4CTRL_EM4IORETMODE_MASK) /***************************************************************************//** * @brief * When EM4 pin retention is set to emuPinRetentionLatch, then pins are retained * through EM4 entry and wakeup. The pin state is released by calling this function. * The feature allows peripherals or GPIO to be re-initialized after EM4 exit (reset), * and when initialization is done, this function can release pins and return control * to the peripherals or GPIO. ******************************************************************************/ __STATIC_INLINE void EMU_UnlatchPinRetention(void) { EMU->CMD = EMU_CMD_EM4UNLATCH; } #endif #if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) void EMU_SetBiasMode(EMU_BiasMode_TypeDef mode); #endif /** @} (end addtogroup EMU) */ /** @} (end addtogroup emlib) */ #ifdef __cplusplus } #endif #endif /* defined( EMU_PRESENT ) */ #endif /* EM_EMU_H */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/emlib/inc/em_gpcrc.h.
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/***************************************************************************//** * @file * @brief General Purpose Cyclic Redundancy Check (GPCRC) API. * @version 5.7.0 ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * SPDX-License-Identifier: Zlib * * The licensor of this software is Silicon Laboratories Inc. * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be * appreciated but is not required. * 2. Altered source versions must be plainly marked as such, and must not be * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * ******************************************************************************/ #ifndef EM_GPCRC_H #define EM_GPCRC_H #include "em_bus.h" #include "em_device.h" #if defined(GPCRC_PRESENT) && (GPCRC_COUNT > 0) #include <stdint.h> #include <stdbool.h> #ifdef __cplusplus extern "C" { #endif /***************************************************************************//** * @addtogroup emlib * @{ ******************************************************************************/ /***************************************************************************//** * @addtogroup GPCRC * @brief General Purpose Cyclic Redundancy Check (GPCRC) API. * * @details * The GPCRC API functions provide full support for the GPCRC peripheral. * * The GPCRC module is a peripheral that implements a Cyclic Redundancy Check * (CRC) function. It supports a fixed 32-bit polynomial and a user * configurable 16-bit polynomial. The fixed 32-bit polynomial is the commonly * used IEEE 802.3 polynomial 0x04C11DB7. * * When using a 16-bit polynomial it is up to the user to choose a polynomial * that fits the application. Commonly used 16-bit polynomials are 0x1021 * (CCITT-16), 0x3D65 (IEC16-MBus), and 0x8005 (ZigBee, 802.15.4, and USB). * See this link for other polynomials: * https://en.wikipedia.org/wiki/Cyclic_redundancy_check * * Before a CRC calculation can begin it is important to call the * @ref GPCRC_Start function. This function will reset CRC calculation * by copying the configured initialization value over to the CRC data register. * * There are two ways of sending input data to the GPCRC. Either write * the input data into the input data register using input functions * @ref GPCRC_InputU32, @ref GPCRC_InputU16 and @ref GPCRC_InputU8, or the * user can configure @ref LDMA to transfer data directly to one of the GPCRC * input data registers. * * <b> Examples of GPCRC usage: </b> * * A CRC-32 Calculation: * * @include em_gpcrc_crc32.c * * A CRC-16 Calculation: * * @include em_gpcrc_crc16.c * * A CRC-CCITT calculation: * * @include em_gpcrc_ccit.c * * @{ ******************************************************************************/ /******************************************************************************* ******************************* STRUCTS *********************************** ******************************************************************************/ /** CRC initialization structure. */ typedef struct { /** * CRC polynomial value. GPCRC supports either a fixed 32-bit polynomial * or a user configurable 16 bit polynomial. The fixed 32-bit polynomial * is the one used in IEEE 802.3, which has the value 0x04C11DB7. To use the * 32-bit fixed polynomial, just assign 0x04C11DB7 to the crcPoly field. * To use a 16-bit polynomial, assign a value to crcPoly where the upper 16 * bits are zero. * * The polynomial should be written in normal bit order. For instance, * to use the CRC-16 polynomial X^16 + X^15 + X^2 + 1, first convert * it to hex representation and remove the highest order term * of the polynomial. This would give us 0x8005 as the value to write into * crcPoly. */ uint32_t crcPoly; /** * CRC initialization value. This value is assigned to the GPCRC_INIT register. * The initValue is loaded into the data register when calling the * @ref GPCRC_Start function or when one of the data registers are read * while @ref autoInit is enabled. */ uint32_t initValue; /** * Reverse byte order. This has an effect when sending a 32-bit word or * 16-bit half word input to the CRC calculation. When set to true, the input * bytes are reversed before entering the CRC calculation. When set to * false, the input bytes stay in the same order. */ bool reverseByteOrder; /** * Reverse bits within each input byte. This setting enables or disables byte * level bit reversal. When byte-level bit reversal is enabled, then each byte * of input data will be reversed before entering CRC calculation. */ bool reverseBits; /** * Enable/disable byte mode. When byte mode is enabled, then all input * is treated as single byte input even though the input is a 32-bit word * or a 16-bit half word. Only the least significant byte of the data-word * will be used for CRC calculation for all writes. */ bool enableByteMode; /** * Enable automatic initialization by re-seeding the CRC result based on * the init value after reading one of the CRC data registers. */ bool autoInit; /** Enable/disable GPCRC when initialization is completed. */ bool enable; } GPCRC_Init_TypeDef; /** Default configuration for GPCRC_Init_TypeDef structure. */ #define GPCRC_INIT_DEFAULT \ { \ 0x04C11DB7UL, /* CRC32 Polynomial value. */ \ 0x00000000UL, /* Initialization value. */ \ false, /* Byte order is normal. */ \ false, /* Bit order is not reversed on output. */ \ false, /* Disable byte mode. */ \ false, /* Disable automatic initialization on data read. */ \ true, /* Enable GPCRC. */ \ } /******************************************************************************* ****************************** PROTOTYPES ********************************* ******************************************************************************/ void GPCRC_Init(GPCRC_TypeDef * gpcrc, const GPCRC_Init_TypeDef * init); void GPCRC_Reset(GPCRC_TypeDef * gpcrc); /***************************************************************************//** * @brief * Enable/disable GPCRC. * * @param[in] gpcrc * Pointer to GPCRC peripheral register block. * * @param[in] enable * True to enable GPCRC, false to disable. ******************************************************************************/ __STATIC_INLINE void GPCRC_Enable(GPCRC_TypeDef * gpcrc, bool enable) { #if defined(GPCRC_EN_EN) BUS_RegBitWrite(&gpcrc->EN, _GPCRC_EN_EN_SHIFT, enable); #else BUS_RegBitWrite(&gpcrc->CTRL, _GPCRC_CTRL_EN_SHIFT, enable); #endif } /***************************************************************************//** * @brief * Issues a command to initialize CRC calculation. * * @details * Issues the command INIT in GPCRC_CMD that initializes * CRC calculation by writing the initial values to the DATA register. * * @param[in] gpcrc * Pointer to GPCRC peripheral register block. ******************************************************************************/ __STATIC_INLINE void GPCRC_Start(GPCRC_TypeDef * gpcrc) { gpcrc->CMD = GPCRC_CMD_INIT; } /***************************************************************************//** * @brief * Set the initialization value of the CRC. * * @param [in] initValue * Value to use to initialize a CRC calculation. This value is moved into * the data register when calling @ref GPCRC_Start * * @param[in] gpcrc * Pointer to GPCRC peripheral register block. ******************************************************************************/ __STATIC_INLINE void GPCRC_InitValueSet(GPCRC_TypeDef * gpcrc, uint32_t initValue) { gpcrc->INIT = initValue; } /***************************************************************************//** * @brief * Writes a 32-bit value to the input data register of the CRC. * * @details * Use this function to write a 32-bit input data to the CRC. CRC * calculation is based on the provided input data using the configured * CRC polynomial. * * @param[in] gpcrc * Pointer to GPCRC peripheral register block. * * @param[in] data * Data to be written to the input data register. ******************************************************************************/ __STATIC_INLINE void GPCRC_InputU32(GPCRC_TypeDef * gpcrc, uint32_t data) { gpcrc->INPUTDATA = data; } /***************************************************************************//** * @brief * Writes a 16-bit value to the input data register of the CRC. * * @details * Use this function to write a 16 bit input data to the CRC. CRC * calculation is based on the provided input data using the configured * CRC polynomial. * * @param[in] gpcrc * Pointer to GPCRC peripheral register block. * * @param[in] data * Data to be written to the input data register. ******************************************************************************/ __STATIC_INLINE void GPCRC_InputU16(GPCRC_TypeDef * gpcrc, uint16_t data) { gpcrc->INPUTDATAHWORD = data; } /***************************************************************************//** * @brief * Writes an 8-bit value to the input data register of the CRC. * * @details * Use this function to write an 8-bit input data to the CRC. CRC * calculation is based on the provided input data using the configured * CRC polynomial. * * @param[in] gpcrc * Pointer to GPCRC peripheral register block. * * @param[in] data * Data to be written to the input data register. ******************************************************************************/ __STATIC_INLINE void GPCRC_InputU8(GPCRC_TypeDef * gpcrc, uint8_t data) { gpcrc->INPUTDATABYTE = data; } /***************************************************************************//** * @brief * Reads the data register of the CRC. * * @details * Use this function to read the calculated CRC value. * * @param[in] gpcrc * Pointer to GPCRC peripheral register block. * * @return * Content of the CRC data register. ******************************************************************************/ __STATIC_INLINE uint32_t GPCRC_DataRead(GPCRC_TypeDef * gpcrc) { return gpcrc->DATA; } /***************************************************************************//** * @brief * Reads the data register of the CRC bit reversed. * * @details * Use this function to read the calculated CRC value bit reversed. When * using a 32-bit polynomial, bits [31:0] are reversed, when using a * 16-bit polynomial, bits [15:0] are reversed. * * @param[in] gpcrc * Pointer to GPCRC peripheral register block. * * @return * Content of the CRC data register bit reversed. ******************************************************************************/ __STATIC_INLINE uint32_t GPCRC_DataReadBitReversed(GPCRC_TypeDef * gpcrc) { return gpcrc->DATAREV; } /***************************************************************************//** * @brief * Reads the data register of the CRC byte reversed. * * @details * Use this function to read the calculated CRC value byte reversed. * * @param[in] gpcrc * Pointer to GPCRC peripheral register block. * * @return * Content of the CRC data register byte reversed. ******************************************************************************/ __STATIC_INLINE uint32_t GPCRC_DataReadByteReversed(GPCRC_TypeDef * gpcrc) { return gpcrc->DATABYTEREV; } /** @} (end addtogroup GPCRC) */ /** @} (end addtogroup emlib) */ #ifdef __cplusplus } #endif #endif /* defined(GPCRC_COUNT) && (GPCRC_COUNT > 0) */ #endif /* EM_GPCRC_H */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/emlib/inc/em_gpio.h.
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/***************************************************************************//** * @file * @brief General Purpose IO (GPIO) peripheral API * @version 5.7.0 ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * SPDX-License-Identifier: Zlib * * The licensor of this software is Silicon Laboratories Inc. * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be * appreciated but is not required. * 2. Altered source versions must be plainly marked as such, and must not be * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * ******************************************************************************/ #ifndef EM_GPIO_H #define EM_GPIO_H #if defined(__ICCARM__) #pragma system_include //TODO: Remove when this file has been MISRA-ized #endif #include "em_device.h" #if defined(GPIO_COUNT) && (GPIO_COUNT > 0) #include <stdbool.h> #include "em_bus.h" #include "em_assert.h" #ifdef __cplusplus extern "C" { #endif /***************************************************************************//** * @addtogroup emlib * @{ ******************************************************************************/ /***************************************************************************//** * @addtogroup GPIO * @{ ******************************************************************************/ /******************************************************************************* ******************************* DEFINES *********************************** ******************************************************************************/ /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ #if defined(_SILICON_LABS_32B_SERIES_0) \ && defined(_EFM32_TINY_FAMILY) || defined(_EFM32_ZERO_FAMILY) #define _GPIO_PORT_A_PIN_COUNT 14 #define _GPIO_PORT_B_PIN_COUNT 10 #define _GPIO_PORT_C_PIN_COUNT 16 #define _GPIO_PORT_D_PIN_COUNT 9 #define _GPIO_PORT_E_PIN_COUNT 12 #define _GPIO_PORT_F_PIN_COUNT 6 #define _GPIO_PORT_G_PIN_COUNT 0 #define _GPIO_PORT_H_PIN_COUNT 0 #define _GPIO_PORT_I_PIN_COUNT 0 #define _GPIO_PORT_J_PIN_COUNT 0 #define _GPIO_PORT_K_PIN_COUNT 0 #define _GPIO_PORT_A_PIN_MASK 0xF77F #define _GPIO_PORT_B_PIN_MASK 0x79F8 #define _GPIO_PORT_C_PIN_MASK 0xFFFF #define _GPIO_PORT_D_PIN_MASK 0x01FF #define _GPIO_PORT_E_PIN_MASK 0xFFF0 #define _GPIO_PORT_F_PIN_MASK 0x003F #define _GPIO_PORT_G_PIN_MASK 0x0000 #define _GPIO_PORT_H_PIN_MASK 0x0000 #define _GPIO_PORT_I_PIN_MASK 0x0000 #define _GPIO_PORT_J_PIN_MASK 0x0000 #define _GPIO_PORT_K_PIN_MASK 0x0000 #elif defined(_EFM32_HAPPY_FAMILY) #define _GPIO_PORT_A_PIN_COUNT 6 #define _GPIO_PORT_B_PIN_COUNT 5 #define _GPIO_PORT_C_PIN_COUNT 12 #define _GPIO_PORT_D_PIN_COUNT 4 #define _GPIO_PORT_E_PIN_COUNT 4 #define _GPIO_PORT_F_PIN_COUNT 6 #define _GPIO_PORT_G_PIN_COUNT 0 #define _GPIO_PORT_H_PIN_COUNT 0 #define _GPIO_PORT_I_PIN_COUNT 0 #define _GPIO_PORT_J_PIN_COUNT 0 #define _GPIO_PORT_K_PIN_COUNT 0 #define _GPIO_PORT_A_PIN_MASK 0x0707 #define _GPIO_PORT_B_PIN_MASK 0x6980 #define _GPIO_PORT_C_PIN_MASK 0xEF1F #define _GPIO_PORT_D_PIN_MASK 0x00F0 #define _GPIO_PORT_E_PIN_MASK 0x3C00 #define _GPIO_PORT_F_PIN_MASK 0x003F #define _GPIO_PORT_G_PIN_MASK 0x0000 #define _GPIO_PORT_H_PIN_MASK 0x0000 #define _GPIO_PORT_I_PIN_MASK 0x0000 #define _GPIO_PORT_J_PIN_MASK 0x0000 #define _GPIO_PORT_K_PIN_MASK 0x0000 #elif defined(_SILICON_LABS_32B_SERIES_0) \ && (defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)) #define _GPIO_PORT_A_PIN_COUNT 16 #define _GPIO_PORT_B_PIN_COUNT 16 #define _GPIO_PORT_C_PIN_COUNT 16 #define _GPIO_PORT_D_PIN_COUNT 16 #define _GPIO_PORT_E_PIN_COUNT 16 #define _GPIO_PORT_F_PIN_COUNT 13 #define _GPIO_PORT_G_PIN_COUNT 0 #define _GPIO_PORT_H_PIN_COUNT 0 #define _GPIO_PORT_I_PIN_COUNT 0 #define _GPIO_PORT_J_PIN_COUNT 0 #define _GPIO_PORT_K_PIN_COUNT 0 #define _GPIO_PORT_A_PIN_MASK 0xFFFF #define _GPIO_PORT_B_PIN_MASK 0xFFFF #define _GPIO_PORT_C_PIN_MASK 0xFFFF #define _GPIO_PORT_D_PIN_MASK 0xFFFF #define _GPIO_PORT_E_PIN_MASK 0xFFFF #define _GPIO_PORT_F_PIN_MASK 0x1FFF #define _GPIO_PORT_G_PIN_MASK 0x0000 #define _GPIO_PORT_H_PIN_MASK 0x0000 #define _GPIO_PORT_I_PIN_MASK 0x0000 #define _GPIO_PORT_J_PIN_MASK 0x0000 #define _GPIO_PORT_K_PIN_MASK 0x0000 #elif defined(_EFM32_GECKO_FAMILY) #define _GPIO_PORT_A_PIN_COUNT 16 #define _GPIO_PORT_B_PIN_COUNT 16 #define _GPIO_PORT_C_PIN_COUNT 16 #define _GPIO_PORT_D_PIN_COUNT 16 #define _GPIO_PORT_E_PIN_COUNT 16 #define _GPIO_PORT_F_PIN_COUNT 10 #define _GPIO_PORT_G_PIN_COUNT 0 #define _GPIO_PORT_H_PIN_COUNT 0 #define _GPIO_PORT_I_PIN_COUNT 0 #define _GPIO_PORT_J_PIN_COUNT 0 #define _GPIO_PORT_K_PIN_COUNT 0 #define _GPIO_PORT_A_PIN_MASK 0xFFFF #define _GPIO_PORT_B_PIN_MASK 0xFFFF #define _GPIO_PORT_C_PIN_MASK 0xFFFF #define _GPIO_PORT_D_PIN_MASK 0xFFFF #define _GPIO_PORT_E_PIN_MASK 0xFFFF #define _GPIO_PORT_F_PIN_MASK 0x03FF #define _GPIO_PORT_G_PIN_MASK 0x0000 #define _GPIO_PORT_H_PIN_MASK 0x0000 #define _GPIO_PORT_I_PIN_MASK 0x0000 #define _GPIO_PORT_J_PIN_MASK 0x0000 #define _GPIO_PORT_K_PIN_MASK 0x0000 #elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) && defined(_EFR_DEVICE) #define _GPIO_PORT_A_PIN_COUNT 6 #define _GPIO_PORT_B_PIN_COUNT 5 #define _GPIO_PORT_C_PIN_COUNT 6 #define _GPIO_PORT_D_PIN_COUNT 7 #define _GPIO_PORT_E_PIN_COUNT 0 #define _GPIO_PORT_F_PIN_COUNT 8 #define _GPIO_PORT_G_PIN_COUNT 0 #define _GPIO_PORT_H_PIN_COUNT 0 #define _GPIO_PORT_I_PIN_COUNT 0 #define _GPIO_PORT_J_PIN_COUNT 0 #define _GPIO_PORT_K_PIN_COUNT 0 #define _GPIO_PORT_A_PIN_MASK 0x003F #define _GPIO_PORT_B_PIN_MASK 0xF800 #define _GPIO_PORT_C_PIN_MASK 0x0FC0 #define _GPIO_PORT_D_PIN_MASK 0xFE00 #define _GPIO_PORT_E_PIN_MASK 0x0000 #define _GPIO_PORT_F_PIN_MASK 0x00FF #define _GPIO_PORT_G_PIN_MASK 0x0000 #define _GPIO_PORT_H_PIN_MASK 0x0000 #define _GPIO_PORT_I_PIN_MASK 0x0000 #define _GPIO_PORT_J_PIN_MASK 0x0000 #define _GPIO_PORT_K_PIN_MASK 0x0000 #elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) && defined(_EFM_DEVICE) #define _GPIO_PORT_A_PIN_COUNT 6 #define _GPIO_PORT_B_PIN_COUNT 5 #define _GPIO_PORT_C_PIN_COUNT 6 #define _GPIO_PORT_D_PIN_COUNT 7 #define _GPIO_PORT_E_PIN_COUNT 0 #define _GPIO_PORT_F_PIN_COUNT 8 #define _GPIO_PORT_G_PIN_COUNT 0 #define _GPIO_PORT_H_PIN_COUNT 0 #define _GPIO_PORT_I_PIN_COUNT 0 #define _GPIO_PORT_J_PIN_COUNT 0 #define _GPIO_PORT_K_PIN_COUNT 0 #define _GPIO_PORT_A_PIN_MASK 0x003F #define _GPIO_PORT_B_PIN_MASK 0xF800 #define _GPIO_PORT_C_PIN_MASK 0x0FC0 #define _GPIO_PORT_D_PIN_MASK 0xFE00 #define _GPIO_PORT_E_PIN_MASK 0x0000 #define _GPIO_PORT_F_PIN_MASK 0x00FF #define _GPIO_PORT_G_PIN_MASK 0x0000 #define _GPIO_PORT_H_PIN_MASK 0x0000 #define _GPIO_PORT_I_PIN_MASK 0x0000 #define _GPIO_PORT_J_PIN_MASK 0x0000 #define _GPIO_PORT_K_PIN_MASK 0x0000 #elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_84) #define _GPIO_PORT_A_PIN_COUNT 10 #define _GPIO_PORT_B_PIN_COUNT 10 #define _GPIO_PORT_C_PIN_COUNT 12 #define _GPIO_PORT_D_PIN_COUNT 8 #define _GPIO_PORT_E_PIN_COUNT 0 #define _GPIO_PORT_F_PIN_COUNT 16 #define _GPIO_PORT_G_PIN_COUNT 0 #define _GPIO_PORT_H_PIN_COUNT 0 #define _GPIO_PORT_I_PIN_COUNT 4 #define _GPIO_PORT_J_PIN_COUNT 2 #define _GPIO_PORT_K_PIN_COUNT 3 #define _GPIO_PORT_A_PIN_MASK 0x03FF #define _GPIO_PORT_B_PIN_MASK 0xFFC0 #define _GPIO_PORT_C_PIN_MASK 0x0FFF #define _GPIO_PORT_D_PIN_MASK 0xFF00 #define _GPIO_PORT_E_PIN_MASK 0x0000 #define _GPIO_PORT_F_PIN_MASK 0xFFFF #define _GPIO_PORT_G_PIN_MASK 0x0000 #define _GPIO_PORT_H_PIN_MASK 0x0000 #define _GPIO_PORT_I_PIN_MASK 0x000F #define _GPIO_PORT_J_PIN_MASK 0xC000 #define _GPIO_PORT_K_PIN_MASK 0x0007 #elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_89) #define _GPIO_PORT_A_PIN_COUNT 6 #define _GPIO_PORT_B_PIN_COUNT 5 #define _GPIO_PORT_C_PIN_COUNT 6 #define _GPIO_PORT_D_PIN_COUNT 6 #define _GPIO_PORT_E_PIN_COUNT 0 #define _GPIO_PORT_F_PIN_COUNT 8 #define _GPIO_PORT_G_PIN_COUNT 0 #define _GPIO_PORT_H_PIN_COUNT 0 #define _GPIO_PORT_I_PIN_COUNT 0 #define _GPIO_PORT_J_PIN_COUNT 0 #define _GPIO_PORT_K_PIN_COUNT 0 #define _GPIO_PORT_A_PIN_MASK 0x003F #define _GPIO_PORT_B_PIN_MASK 0xF800 #define _GPIO_PORT_C_PIN_MASK 0x0FC0 #define _GPIO_PORT_D_PIN_MASK 0xFC00 #define _GPIO_PORT_E_PIN_MASK 0x0000 #define _GPIO_PORT_F_PIN_MASK 0x00FF #define _GPIO_PORT_G_PIN_MASK 0x0000 #define _GPIO_PORT_H_PIN_MASK 0x0000 #define _GPIO_PORT_I_PIN_MASK 0x0000 #define _GPIO_PORT_J_PIN_MASK 0x0000 #define _GPIO_PORT_K_PIN_MASK 0x0000 #elif defined (_SILICON_LABS_GECKO_INTERNAL_SDID_106) #define _GPIO_PORT_A_PIN_COUNT 16 #define _GPIO_PORT_B_PIN_COUNT 16 #define _GPIO_PORT_C_PIN_COUNT 16 #define _GPIO_PORT_D_PIN_COUNT 16 #define _GPIO_PORT_E_PIN_COUNT 16 #define _GPIO_PORT_F_PIN_COUNT 15 #define _GPIO_PORT_G_PIN_COUNT 0 #define _GPIO_PORT_H_PIN_COUNT 0 #define _GPIO_PORT_I_PIN_COUNT 0 #define _GPIO_PORT_J_PIN_COUNT 0 #define _GPIO_PORT_K_PIN_COUNT 0 #define _GPIO_PORT_A_PIN_MASK 0xFFFF #define _GPIO_PORT_B_PIN_MASK 0xFFFF #define _GPIO_PORT_C_PIN_MASK 0xFFFF #define _GPIO_PORT_D_PIN_MASK 0xFFFF #define _GPIO_PORT_E_PIN_MASK 0xFFFF #define _GPIO_PORT_F_PIN_MASK 0x7FFF #define _GPIO_PORT_G_PIN_MASK 0x0000 #define _GPIO_PORT_H_PIN_MASK 0x0000 #define _GPIO_PORT_I_PIN_MASK 0x0000 #define _GPIO_PORT_J_PIN_MASK 0x0000 #define _GPIO_PORT_K_PIN_MASK 0x0000 #elif defined(_SILICON_LABS_32B_SERIES_1) && defined(_EFM32_GIANT_FAMILY) #define _GPIO_PORT_A_PIN_COUNT 16 #define _GPIO_PORT_B_PIN_COUNT 16 #define _GPIO_PORT_C_PIN_COUNT 16 #define _GPIO_PORT_D_PIN_COUNT 16 #define _GPIO_PORT_E_PIN_COUNT 16 #define _GPIO_PORT_F_PIN_COUNT 16 #define _GPIO_PORT_G_PIN_COUNT 16 #define _GPIO_PORT_H_PIN_COUNT 16 #define _GPIO_PORT_I_PIN_COUNT 16 #define _GPIO_PORT_J_PIN_COUNT 0 #define _GPIO_PORT_K_PIN_COUNT 0 #define _GPIO_PORT_A_PIN_MASK 0xFFFF #define _GPIO_PORT_B_PIN_MASK 0xFFFF #define _GPIO_PORT_C_PIN_MASK 0xFFFF #define _GPIO_PORT_D_PIN_MASK 0xFFFF #define _GPIO_PORT_E_PIN_MASK 0xFFFF #define _GPIO_PORT_F_PIN_MASK 0xFFFF #define _GPIO_PORT_G_PIN_MASK 0xFFFF #define _GPIO_PORT_H_PIN_MASK 0xFFFF #define _GPIO_PORT_I_PIN_MASK 0xFFFF #define _GPIO_PORT_J_PIN_MASK 0x0000 #define _GPIO_PORT_K_PIN_MASK 0x0000 #elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_95) #define _GPIO_PORT_A_PIN_COUNT 6 #define _GPIO_PORT_B_PIN_COUNT 5 #define _GPIO_PORT_C_PIN_COUNT 6 #define _GPIO_PORT_D_PIN_COUNT 6 #define _GPIO_PORT_E_PIN_COUNT 0 #define _GPIO_PORT_F_PIN_COUNT 8 #define _GPIO_PORT_G_PIN_COUNT 0 #define _GPIO_PORT_H_PIN_COUNT 0 #define _GPIO_PORT_I_PIN_COUNT 0 #define _GPIO_PORT_J_PIN_COUNT 0 #define _GPIO_PORT_K_PIN_COUNT 0 #define _GPIO_PORT_A_PIN_MASK 0x003F #define _GPIO_PORT_B_PIN_MASK 0xF800 #define _GPIO_PORT_C_PIN_MASK 0x0FC0 #define _GPIO_PORT_D_PIN_MASK 0xFC00 #define _GPIO_PORT_E_PIN_MASK 0x0000 #define _GPIO_PORT_F_PIN_MASK 0x00FF #define _GPIO_PORT_G_PIN_MASK 0x0000 #define _GPIO_PORT_H_PIN_MASK 0x0000 #define _GPIO_PORT_I_PIN_MASK 0x0000 #define _GPIO_PORT_J_PIN_MASK 0x0000 #define _GPIO_PORT_K_PIN_MASK 0x0000 #elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_103) #define _GPIO_PORT_A_PIN_COUNT 14 #define _GPIO_PORT_B_PIN_COUNT 10 #define _GPIO_PORT_C_PIN_COUNT 16 #define _GPIO_PORT_D_PIN_COUNT 9 #define _GPIO_PORT_E_PIN_COUNT 12 #define _GPIO_PORT_F_PIN_COUNT 6 #define _GPIO_PORT_G_PIN_COUNT 0 #define _GPIO_PORT_H_PIN_COUNT 0 #define _GPIO_PORT_I_PIN_COUNT 0 #define _GPIO_PORT_J_PIN_COUNT 0 #define _GPIO_PORT_K_PIN_COUNT 0 #define _GPIO_PORT_A_PIN_MASK 0xF77F #define _GPIO_PORT_B_PIN_MASK 0x79F8 #define _GPIO_PORT_C_PIN_MASK 0xFFFF #define _GPIO_PORT_D_PIN_MASK 0x01FF #define _GPIO_PORT_E_PIN_MASK 0xFFF0 #define _GPIO_PORT_F_PIN_MASK 0x003F #define _GPIO_PORT_G_PIN_MASK 0x0000 #define _GPIO_PORT_H_PIN_MASK 0x0000 #define _GPIO_PORT_I_PIN_MASK 0x0000 #define _GPIO_PORT_J_PIN_MASK 0x0000 #define _GPIO_PORT_K_PIN_MASK 0x0000 #elif defined (_SILICON_LABS_32B_SERIES_2_CONFIG_1) #define _GPIO_PORT_A_PIN_COUNT 7 #define _GPIO_PORT_B_PIN_COUNT 2 #define _GPIO_PORT_C_PIN_COUNT 6 #define _GPIO_PORT_D_PIN_COUNT 5 #define _GPIO_PORT_E_PIN_COUNT 0 #define _GPIO_PORT_F_PIN_COUNT 0 #define _GPIO_PORT_G_PIN_COUNT 0 #define _GPIO_PORT_H_PIN_COUNT 0 #define _GPIO_PORT_I_PIN_COUNT 0 #define _GPIO_PORT_J_PIN_COUNT 0 #define _GPIO_PORT_K_PIN_COUNT 0 #define _GPIO_PORT_A_PIN_MASK 0x007F #define _GPIO_PORT_B_PIN_MASK 0x0003 #define _GPIO_PORT_C_PIN_MASK 0x003F #define _GPIO_PORT_D_PIN_MASK 0x001F #define _GPIO_PORT_E_PIN_MASK 0x0000 #define _GPIO_PORT_F_PIN_MASK 0x0000 #define _GPIO_PORT_G_PIN_MASK 0x0000 #define _GPIO_PORT_H_PIN_MASK 0x0000 #define _GPIO_PORT_I_PIN_MASK 0x0000 #define _GPIO_PORT_J_PIN_MASK 0x0000 #define _GPIO_PORT_K_PIN_MASK 0x0000 #else #warning "Port and pin masks are not defined for this family." #endif #define _GPIO_PORT_SIZE(port) ( \ (port) == 0 ? _GPIO_PORT_A_PIN_COUNT \ : (port) == 1 ? _GPIO_PORT_B_PIN_COUNT \ : (port) == 2 ? _GPIO_PORT_C_PIN_COUNT \ : (port) == 3 ? _GPIO_PORT_D_PIN_COUNT \ : (port) == 4 ? _GPIO_PORT_E_PIN_COUNT \ : (port) == 5 ? _GPIO_PORT_F_PIN_COUNT \ : (port) == 6 ? _GPIO_PORT_G_PIN_COUNT \ : (port) == 7 ? _GPIO_PORT_H_PIN_COUNT \ : (port) == 8 ? _GPIO_PORT_I_PIN_COUNT \ : (port) == 9 ? _GPIO_PORT_J_PIN_COUNT \ : (port) == 10 ? _GPIO_PORT_K_PIN_COUNT \ : 0) #define _GPIO_PORT_MASK(port) ( \ (port) == 0 ? _GPIO_PORT_A_PIN_MASK \ : (port) == 1 ? _GPIO_PORT_B_PIN_MASK \ : (port) == 2 ? _GPIO_PORT_C_PIN_MASK \ : (port) == 3 ? _GPIO_PORT_D_PIN_MASK \ : (port) == 4 ? _GPIO_PORT_E_PIN_MASK \ : (port) == 5 ? _GPIO_PORT_F_PIN_MASK \ : (port) == 6 ? _GPIO_PORT_G_PIN_MASK \ : (port) == 7 ? _GPIO_PORT_H_PIN_MASK \ : (port) == 8 ? _GPIO_PORT_I_PIN_MASK \ : (port) == 9 ? _GPIO_PORT_J_PIN_MASK \ : (port) == 10 ? _GPIO_PORT_K_PIN_MASK \ : 0) /** Validation of port and pin. */ #define GPIO_PORT_VALID(port) (_GPIO_PORT_MASK(port) ) #define GPIO_PORT_PIN_VALID(port, pin) (((_GPIO_PORT_MASK(port)) >> (pin)) & 0x1) #if defined(_GPIO_EXTIPINSELL_MASK) /** Validation of interrupt number and pin. */ #define GPIO_INTNO_PIN_VALID(intNo, pin) \ (((intNo) & ~_GPIO_EXTIPINSELL_EXTIPINSEL0_MASK) \ == ((pin) & ~_GPIO_EXTIPINSELL_EXTIPINSEL0_MASK)) #endif /** Highest GPIO pin number. */ #define GPIO_PIN_MAX 15 /** Highest GPIO port number. */ #if (_GPIO_PORT_K_PIN_COUNT > 0) #define GPIO_PORT_MAX 10 #elif (_GPIO_PORT_J_PIN_COUNT > 0) #define GPIO_PORT_MAX 9 #elif (_GPIO_PORT_I_PIN_COUNT > 0) #define GPIO_PORT_MAX 8 #elif (_GPIO_PORT_H_PIN_COUNT > 0) #define GPIO_PORT_MAX 7 #elif (_GPIO_PORT_G_PIN_COUNT > 0) #define GPIO_PORT_MAX 6 #elif (_GPIO_PORT_F_PIN_COUNT > 0) #define GPIO_PORT_MAX 5 #elif (_GPIO_PORT_E_PIN_COUNT > 0) #define GPIO_PORT_MAX 4 #elif (_GPIO_PORT_D_PIN_COUNT > 0) #define GPIO_PORT_MAX 3 #else #error "Max GPIO port number is undefined for this part." #endif /** Highest EXT GPIO interrupt number. */ #define GPIO_EXTINTNO_MAX 15 /** @endcond */ /******************************************************************************* ******************************** ENUMS ************************************ ******************************************************************************/ /** GPIO ports IDs. */ typedef enum { #if (_GPIO_PORT_A_PIN_COUNT > 0) gpioPortA = 0, #endif #if (_GPIO_PORT_B_PIN_COUNT > 0) gpioPortB = 1, #endif #if (_GPIO_PORT_C_PIN_COUNT > 0) gpioPortC = 2, #endif #if (_GPIO_PORT_D_PIN_COUNT > 0) gpioPortD = 3, #endif #if (_GPIO_PORT_E_PIN_COUNT > 0) gpioPortE = 4, #endif #if (_GPIO_PORT_F_PIN_COUNT > 0) gpioPortF = 5, #endif #if (_GPIO_PORT_G_PIN_COUNT > 0) gpioPortG = 6, #endif #if (_GPIO_PORT_H_PIN_COUNT > 0) gpioPortH = 7, #endif #if (_GPIO_PORT_I_PIN_COUNT > 0) gpioPortI = 8, #endif #if (_GPIO_PORT_J_PIN_COUNT > 0) gpioPortJ = 9, #endif #if (_GPIO_PORT_K_PIN_COUNT > 0) gpioPortK = 10, #endif } GPIO_Port_TypeDef; #if defined(_GPIO_P_CTRL_DRIVEMODE_MASK) /** GPIO drive mode. */ typedef enum { /** Default 6mA. */ gpioDriveModeStandard = GPIO_P_CTRL_DRIVEMODE_STANDARD, /** 0.5 mA. */ gpioDriveModeLowest = GPIO_P_CTRL_DRIVEMODE_LOWEST, /** 20 mA. */ gpioDriveModeHigh = GPIO_P_CTRL_DRIVEMODE_HIGH, /** 2 mA. */ gpioDriveModeLow = GPIO_P_CTRL_DRIVEMODE_LOW } GPIO_DriveMode_TypeDef; #endif #if defined(_GPIO_P_CTRL_DRIVESTRENGTH_MASK) && defined(_GPIO_P_CTRL_DRIVESTRENGTHALT_MASK) /** GPIO drive strength. */ typedef enum { /** GPIO weak 1mA and alternate function weak 1mA. */ gpioDriveStrengthWeakAlternateWeak = GPIO_P_CTRL_DRIVESTRENGTH_WEAK | GPIO_P_CTRL_DRIVESTRENGTHALT_WEAK, /** GPIO weak 1mA and alternate function strong 10mA. */ gpioDriveStrengthWeakAlternateStrong = GPIO_P_CTRL_DRIVESTRENGTH_WEAK | GPIO_P_CTRL_DRIVESTRENGTHALT_STRONG, /** GPIO strong 10mA and alternate function weak 1mA. */ gpioDriveStrengthStrongAlternateWeak = GPIO_P_CTRL_DRIVESTRENGTH_STRONG | GPIO_P_CTRL_DRIVESTRENGTHALT_WEAK, /** GPIO strong 10mA and alternate function strong 10mA. */ gpioDriveStrengthStrongAlternateStrong = GPIO_P_CTRL_DRIVESTRENGTH_STRONG | GPIO_P_CTRL_DRIVESTRENGTHALT_STRONG, } GPIO_DriveStrength_TypeDef; /* Deprecated enums. */ #define gpioDriveStrengthStrong gpioDriveStrengthStrongAlternateStrong #define gpioDriveStrengthWeak gpioDriveStrengthWeakAlternateWeak #endif /** Pin mode. For more details on each mode, refer to the * reference manual. */ typedef enum { /** Input disabled. Pull-up if DOUT is set. */ gpioModeDisabled = _GPIO_P_MODEL_MODE0_DISABLED, /** Input enabled. Filter if DOUT is set. */ gpioModeInput = _GPIO_P_MODEL_MODE0_INPUT, /** Input enabled. DOUT determines pull direction. */ gpioModeInputPull = _GPIO_P_MODEL_MODE0_INPUTPULL, /** Input enabled with filter. DOUT determines pull direction. */ gpioModeInputPullFilter = _GPIO_P_MODEL_MODE0_INPUTPULLFILTER, /** Push-pull output. */ gpioModePushPull = _GPIO_P_MODEL_MODE0_PUSHPULL, #if defined(_GPIO_P_MODEL_MODE0_PUSHPULLDRIVE) /** Push-pull output with drive-strength set by DRIVEMODE. */ gpioModePushPullDrive = _GPIO_P_MODEL_MODE0_PUSHPULLDRIVE, #endif #if defined(_GPIO_P_MODEL_MODE0_PUSHPULLALT) /** Push-pull using alternate control. */ gpioModePushPullAlternate = _GPIO_P_MODEL_MODE0_PUSHPULLALT, #endif /** Wired-or output. */ gpioModeWiredOr = _GPIO_P_MODEL_MODE0_WIREDOR, /** Wired-or output with pull-down. */ gpioModeWiredOrPullDown = _GPIO_P_MODEL_MODE0_WIREDORPULLDOWN, /** Open-drain output. */ gpioModeWiredAnd = _GPIO_P_MODEL_MODE0_WIREDAND, /** Open-drain output with filter. */ gpioModeWiredAndFilter = _GPIO_P_MODEL_MODE0_WIREDANDFILTER, /** Open-drain output with pull-up. */ gpioModeWiredAndPullUp = _GPIO_P_MODEL_MODE0_WIREDANDPULLUP, /** Open-drain output with filter and pull-up. */ gpioModeWiredAndPullUpFilter = _GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER, #if defined(_GPIO_P_MODEL_MODE0_WIREDANDDRIVE) /** Open-drain output with drive-strength set by DRIVEMODE. */ gpioModeWiredAndDrive = _GPIO_P_MODEL_MODE0_WIREDANDDRIVE, /** Open-drain output with filter and drive-strength set by DRIVEMODE. */ gpioModeWiredAndDriveFilter = _GPIO_P_MODEL_MODE0_WIREDANDDRIVEFILTER, /** Open-drain output with pull-up and drive-strength set by DRIVEMODE. */ gpioModeWiredAndDrivePullUp = _GPIO_P_MODEL_MODE0_WIREDANDDRIVEPULLUP, /** Open-drain output with filter, pull-up and drive-strength set by DRIVEMODE. */ gpioModeWiredAndDrivePullUpFilter = _GPIO_P_MODEL_MODE0_WIREDANDDRIVEPULLUPFILTER #endif #if defined(_GPIO_P_MODEL_MODE0_WIREDANDALT) /** Open-drain output using alternate control. */ gpioModeWiredAndAlternate = _GPIO_P_MODEL_MODE0_WIREDANDALT, /** Open-drain output using alternate control with filter. */ gpioModeWiredAndAlternateFilter = _GPIO_P_MODEL_MODE0_WIREDANDALTFILTER, /** Open-drain output using alternate control with pull-up. */ gpioModeWiredAndAlternatePullUp = _GPIO_P_MODEL_MODE0_WIREDANDALTPULLUP, /** Open-drain output using alternate control with filter and pull-up. */ gpioModeWiredAndAlternatePullUpFilter = _GPIO_P_MODEL_MODE0_WIREDANDALTPULLUPFILTER, #endif } GPIO_Mode_TypeDef; /******************************************************************************* ***************************** PROTOTYPES ********************************** ******************************************************************************/ void GPIO_DbgLocationSet(unsigned int location); /***************************************************************************//** * @brief * Enable/disable serial wire clock pin. * * @note * Disabling SWDClk will disable the debug interface, which may result in * a lockout if done early in startup (before debugger is able to halt core). * * @param[in] enable * @li false - disable serial wire clock. * @li true - enable serial wire clock (default after reset). ******************************************************************************/ __STATIC_INLINE void GPIO_DbgSWDClkEnable(bool enable) { #if defined(_GPIO_ROUTE_SWCLKPEN_MASK) BUS_RegBitWrite(&(GPIO->ROUTE), _GPIO_ROUTE_SWCLKPEN_SHIFT, enable); #elif defined(_GPIO_ROUTEPEN_SWCLKTCKPEN_MASK) BUS_RegBitWrite(&(GPIO->ROUTEPEN), _GPIO_ROUTEPEN_SWCLKTCKPEN_SHIFT, enable); #elif defined(_GPIO_DBGROUTEPEN_SWCLKTCKPEN_MASK) BUS_RegBitWrite(&(GPIO->DBGROUTEPEN), _GPIO_DBGROUTEPEN_SWCLKTCKPEN_SHIFT, enable); #else #warning "ROUTE enable for SWCLK pin is not defined." #endif } /***************************************************************************//** * @brief * Enable/disable serial wire data I/O pin. * * @note * Disabling SWDClk will disable the debug interface, which may result in * a lockout if done early in startup (before debugger is able to halt core). * * @param[in] enable * @li false - disable serial wire data pin. * @li true - enable serial wire data pin (default after reset). ******************************************************************************/ __STATIC_INLINE void GPIO_DbgSWDIOEnable(bool enable) { #if defined(_GPIO_ROUTE_SWDIOPEN_MASK) BUS_RegBitWrite(&(GPIO->ROUTE), _GPIO_ROUTE_SWDIOPEN_SHIFT, enable); #elif defined(_GPIO_ROUTEPEN_SWDIOTMSPEN_MASK) BUS_RegBitWrite(&(GPIO->ROUTEPEN), _GPIO_ROUTEPEN_SWDIOTMSPEN_SHIFT, enable); #elif defined(_GPIO_DBGROUTEPEN_SWDIOTMSPEN_MASK) BUS_RegBitWrite(&(GPIO->DBGROUTEPEN), _GPIO_DBGROUTEPEN_SWDIOTMSPEN_SHIFT, enable); #else #warning "ROUTE enable for SWDIO pin is not defined." #endif } #if defined(_GPIO_ROUTE_SWOPEN_MASK) || defined(_GPIO_ROUTEPEN_SWVPEN_MASK) \ || defined(_GPIO_TRACEROUTEPEN_SWVPEN_MASK) /***************************************************************************//** * @brief * Enable/Disable serial wire output pin. * * @note * Enabling this pin is not sufficient to fully enable serial wire output, * which is also dependent on issues outside the GPIO module. Refer to * @ref DBG_SWOEnable(). * * @param[in] enable * @li false - disable serial wire viewer pin (default after reset). * @li true - enable serial wire viewer pin. ******************************************************************************/ __STATIC_INLINE void GPIO_DbgSWOEnable(bool enable) { #if defined(_GPIO_ROUTE_SWOPEN_MASK) BUS_RegBitWrite(&(GPIO->ROUTE), _GPIO_ROUTE_SWOPEN_SHIFT, enable); #elif defined(_GPIO_ROUTEPEN_SWVPEN_MASK) BUS_RegBitWrite(&(GPIO->ROUTEPEN), _GPIO_ROUTEPEN_SWVPEN_SHIFT, enable); #elif defined(_GPIO_TRACEROUTEPEN_SWVPEN_MASK) BUS_RegBitWrite(&(GPIO->TRACEROUTEPEN), _GPIO_TRACEROUTEPEN_SWVPEN_SHIFT, enable); #else #warning "ROUTE enable for SWO/SWV pin is not defined." #endif } #endif #if defined (_GPIO_P_CTRL_DRIVEMODE_MASK) void GPIO_DriveModeSet(GPIO_Port_TypeDef port, GPIO_DriveMode_TypeDef mode); #endif #if defined(_GPIO_P_CTRL_DRIVESTRENGTH_MASK) void GPIO_DriveStrengthSet(GPIO_Port_TypeDef port, GPIO_DriveStrength_TypeDef strength); #endif # if defined(_GPIO_EM4WUEN_MASK) /**************************************************************************//** * @brief * Disable GPIO pin wake-up from EM4. * * @param[in] pinmask * Bit mask containing the bitwise logic OR of which GPIO pin(s) to disable. * Refer to Reference Manuals for pinmask to GPIO port/pin mapping. *****************************************************************************/ __STATIC_INLINE void GPIO_EM4DisablePinWakeup(uint32_t pinmask) { EFM_ASSERT((pinmask & ~_GPIO_EM4WUEN_MASK) == 0); GPIO->EM4WUEN &= ~pinmask; } #endif # if defined(_GPIO_EM4WUEN_MASK) void GPIO_EM4EnablePinWakeup(uint32_t pinmask, uint32_t polaritymask); #endif #if defined(_GPIO_EM4WUCAUSE_MASK) || defined(_GPIO_IF_EM4WU_MASK) /**************************************************************************//** * @brief * Check which GPIO pin(s) that caused a wake-up from EM4. * * @return * Bit mask containing the bitwise logic OR of which GPIO pin(s) caused the * wake-up. Refer to Reference Manuals for pinmask to GPIO port/pin mapping. *****************************************************************************/ __STATIC_INLINE uint32_t GPIO_EM4GetPinWakeupCause(void) { #if defined(_GPIO_EM4WUCAUSE_MASK) return GPIO->EM4WUCAUSE & _GPIO_EM4WUCAUSE_MASK; #else return GPIO->IF & _GPIO_IF_EM4WU_MASK; #endif } #endif #if defined(GPIO_CTRL_EM4RET) || defined(_EMU_EM4CTRL_EM4IORETMODE_MASK) /**************************************************************************//** * @brief * Enable GPIO pin retention of output enable, output value, pull enable, and * pull direction in EM4. * * @note * On series 0 devices EM4 gpio retention can either be turned on or off. On * series 1 devices there are three EM4 GPIO retention modes available. These * modes are "Disabled", "EM4EXIT" and "SWUNLATCH". Use the @ref EMU_EM4Init() * to configure the GPIO retention mode on a series 1 device. * * The behavior of this function depends on the configured GPIO retention mode. * If the GPIO retention mode is configured to be "SWUNLATCH" then this * function will not change anything. If the retention mode is anything else * then this function will set the GPIO retention mode to "EM4EXIT" when the * enable argument is true, and "Disabled" when false. * * @param[in] enable * @li true - enable EM4 pin retention. * @li false - disable EM4 pin retention. *****************************************************************************/ __STATIC_INLINE void GPIO_EM4SetPinRetention(bool enable) { #if defined(GPIO_CTRL_EM4RET) BUS_RegBitWrite(&GPIO->CTRL, _GPIO_CTRL_EM4RET_SHIFT, enable); #else // Leave configuration alone when software unlatch is used. uint32_t mode = EMU->EM4CTRL & _EMU_EM4CTRL_EM4IORETMODE_MASK; if (mode == EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH) { return; } if (enable) { EMU->EM4CTRL = (EMU->EM4CTRL & ~_EMU_EM4CTRL_EM4IORETMODE_MASK) | EMU_EM4CTRL_EM4IORETMODE_EM4EXIT; } else { EMU->EM4CTRL = (EMU->EM4CTRL & ~_EMU_EM4CTRL_EM4IORETMODE_MASK) | EMU_EM4CTRL_EM4IORETMODE_DISABLE; } #endif } #endif void GPIO_ExtIntConfig(GPIO_Port_TypeDef port, unsigned int pin, unsigned int intNo, bool risingEdge, bool fallingEdge, bool enable); /***************************************************************************//** * @brief * Enable/disable input sensing. * * @details * Disabling input sensing if not used, can save some energy consumption. * * @param[in] val * Bitwise logic OR of one or more of: * @li GPIO_INSENSE_INT - interrupt input sensing. * @li GPIO_INSENSE_PRS - peripheral reflex system input sensing. * * @param[in] mask * Mask containing bitwise logic OR of bits similar as for @p val used to * indicate which input sense options to disable/enable. ******************************************************************************/ __STATIC_INLINE void GPIO_InputSenseSet(uint32_t val, uint32_t mask) { #if defined(_GPIO_INSENSE_MASK) GPIO->INSENSE = (GPIO->INSENSE & ~mask) | (val & mask); #else (void) val; (void) mask; #endif } /***************************************************************************//** * @brief * Clear one or more pending GPIO interrupts. * * @param[in] flags * Bitwise logic OR of GPIO interrupt sources to clear. ******************************************************************************/ __STATIC_INLINE void GPIO_IntClear(uint32_t flags) { #if defined(GPIO_HAS_SET_CLEAR) GPIO->IF_CLR = flags; #else GPIO->IFC = flags; #endif } /***************************************************************************//** * @brief * Disable one or more GPIO interrupts. * * @param[in] flags * GPIO interrupt sources to disable. ******************************************************************************/ __STATIC_INLINE void GPIO_IntDisable(uint32_t flags) { GPIO->IEN &= ~flags; } /***************************************************************************//** * @brief * Enable one or more GPIO interrupts. * * @note * Depending on the use, a pending interrupt may already be set prior to * enabling the interrupt. To ignore a pending interrupt, consider using * GPIO_IntClear() prior to enabling the interrupt. * * @param[in] flags * GPIO interrupt sources to enable. ******************************************************************************/ __STATIC_INLINE void GPIO_IntEnable(uint32_t flags) { GPIO->IEN |= flags; } /***************************************************************************//** * @brief * Get pending GPIO interrupts. * * @return * GPIO interrupt sources pending. ******************************************************************************/ __STATIC_INLINE uint32_t GPIO_IntGet(void) { return GPIO->IF; } /***************************************************************************//** * @brief * Get enabled and pending GPIO interrupt flags. * Useful for handling more interrupt sources in the same interrupt handler. * * @note * Interrupt flags are not cleared by the use of this function. * * @return * Pending and enabled GPIO interrupt sources. * The return value is the bitwise AND combination of * - the OR combination of enabled interrupt sources in GPIO_IEN register * and * - the OR combination of valid interrupt flags in GPIO_IF register. ******************************************************************************/ __STATIC_INLINE uint32_t GPIO_IntGetEnabled(void) { uint32_t tmp; /* Store GPIO->IEN in temporary variable in order to define explicit order * of volatile accesses. */ tmp = GPIO->IEN; /* Bitwise AND of pending and enabled interrupts */ return GPIO->IF & tmp; } /**************************************************************************//** * @brief * Set one or more pending GPIO interrupts from SW. * * @param[in] flags * GPIO interrupt sources to set to pending. *****************************************************************************/ __STATIC_INLINE void GPIO_IntSet(uint32_t flags) { #if defined (GPIO_HAS_SET_CLEAR) GPIO->IF_SET = flags; #else GPIO->IFS = flags; #endif } /***************************************************************************//** * @brief * Locks the GPIO configuration. ******************************************************************************/ __STATIC_INLINE void GPIO_Lock(void) { GPIO->LOCK = ~GPIO_LOCK_LOCKKEY_UNLOCK; } /***************************************************************************//** * @brief * Read the pad value for a single pin in a GPIO port. * * @param[in] port * The GPIO port to access. * * @param[in] pin * The pin number to read. * * @return * The pin value, 0 or 1. ******************************************************************************/ __STATIC_INLINE unsigned int GPIO_PinInGet(GPIO_Port_TypeDef port, unsigned int pin) { EFM_ASSERT(GPIO_PORT_PIN_VALID(port, pin)); return BUS_RegBitRead(&GPIO->P[port].DIN, pin); } #if defined (_GPIO_P_PINLOCKN_MASK) /***************************************************************************//** * @brief * Lock all GPIO configuration settings for a given pin. * The lock can only be cleared by a chip reset. * * @param[in] port * The GPIO port to access. * * @param[in] pin * The pin number to lock. ******************************************************************************/ __STATIC_INLINE void GPIO_PinLock(GPIO_Port_TypeDef port, unsigned int pin) { BUS_RegBitWrite(&GPIO->P[port].PINLOCKN, pin, 0); } #endif GPIO_Mode_TypeDef GPIO_PinModeGet(GPIO_Port_TypeDef port, unsigned int pin); void GPIO_PinModeSet(GPIO_Port_TypeDef port, unsigned int pin, GPIO_Mode_TypeDef mode, unsigned int out); /***************************************************************************//** * @brief * Set a single pin in GPIO data out port register to 0. * * @note * In order for the setting to take effect on the output pad, the pin must * have been configured properly. If not, it will take effect whenever the * pin has been properly configured. * * @param[in] port * The GPIO port to access. * * @param[in] pin * The pin to set. ******************************************************************************/ __STATIC_INLINE void GPIO_PinOutClear(GPIO_Port_TypeDef port, unsigned int pin) { EFM_ASSERT(GPIO_PORT_PIN_VALID(port, pin)); #if defined(_GPIO_P_DOUTCLR_MASK) GPIO->P[port].DOUTCLR = 1 << pin; #elif defined(GPIO_HAS_SET_CLEAR) GPIO->P_CLR[port].DOUT = 1 << pin; #else BUS_RegMaskedClear(&GPIO->P[port].DOUT, 1 << pin); #endif } /***************************************************************************//** * @brief * Get current setting for a pin in a GPIO port data out register. * * @param[in] port * The GPIO port to access. * * @param[in] pin * The pin to get setting for. * * @return * The DOUT setting for the requested pin, 0 or 1. ******************************************************************************/ __STATIC_INLINE unsigned int GPIO_PinOutGet(GPIO_Port_TypeDef port, unsigned int pin) { EFM_ASSERT(GPIO_PORT_PIN_VALID(port, pin)); return BUS_RegBitRead(&GPIO->P[port].DOUT, pin); } /***************************************************************************//** * @brief * Set a single pin in GPIO data out register to 1. * * @note * In order for the setting to take effect on the output pad, the pin must * have been configured properly. If not, it will take effect whenever the * pin has been properly configured. * * @param[in] port * The GPIO port to access. * * @param[in] pin * The pin to set. ******************************************************************************/ __STATIC_INLINE void GPIO_PinOutSet(GPIO_Port_TypeDef port, unsigned int pin) { EFM_ASSERT(GPIO_PORT_PIN_VALID(port, pin)); #if defined(_GPIO_P_DOUTSET_MASK) GPIO->P[port].DOUTSET = 1 << pin; #elif defined(GPIO_HAS_SET_CLEAR) GPIO->P_SET[port].DOUT = 1 << pin; #else BUS_RegMaskedSet(&GPIO->P[port].DOUT, 1 << pin); #endif } /***************************************************************************//** * @brief * Toggle a single pin in GPIO port data out register. * * @note * In order for the setting to take effect on the output pad, the pin must * have been configured properly. If not, it will take effect whenever the * pin has been properly configured. * * @param[in] port * The GPIO port to access. * * @param[in] pin * The pin to toggle. ******************************************************************************/ __STATIC_INLINE void GPIO_PinOutToggle(GPIO_Port_TypeDef port, unsigned int pin) { EFM_ASSERT(GPIO_PORT_PIN_VALID(port, pin)); #if defined (_GPIO_P_DOUTTGL_MASK) GPIO->P[port].DOUTTGL = 1 << pin; #elif defined(GPIO_HAS_SET_CLEAR) GPIO->P_TGL[port].DOUT = 1 << pin; #else GPIO->P[port].DOUT ^= 1 << pin; #endif } /***************************************************************************//** * @brief * Read the pad values for GPIO port. * * @param[in] port * The GPIO port to access. ******************************************************************************/ __STATIC_INLINE uint32_t GPIO_PortInGet(GPIO_Port_TypeDef port) { EFM_ASSERT(GPIO_PORT_VALID(port)); return GPIO->P[port].DIN; } /***************************************************************************//** * @brief * Set bits in DOUT register for a port to 0. * * @note * In order for the setting to take effect on the output pad, the pin must * have been configured properly. If not, it will take effect whenever the * pin has been properly configured. * * @param[in] port * The GPIO port to access. * * @param[in] pins * Bit mask for bits to clear in DOUT register. ******************************************************************************/ __STATIC_INLINE void GPIO_PortOutClear(GPIO_Port_TypeDef port, uint32_t pins) { EFM_ASSERT(GPIO_PORT_VALID(port)); #if defined(_GPIO_P_DOUTCLR_MASK) GPIO->P[port].DOUTCLR = pins; #elif defined(GPIO_HAS_SET_CLEAR) GPIO->P_CLR[port].DOUT = pins; #else BUS_RegMaskedClear(&GPIO->P[port].DOUT, pins); #endif } /***************************************************************************//** * @brief * Get current setting for a GPIO port data out register. * * @param[in] port * The GPIO port to access. * * @return * The data out setting for the requested port. ******************************************************************************/ __STATIC_INLINE uint32_t GPIO_PortOutGet(GPIO_Port_TypeDef port) { EFM_ASSERT(GPIO_PORT_VALID(port)); return GPIO->P[port].DOUT; } /***************************************************************************//** * @brief * Set bits GPIO data out register to 1. * * @note * In order for the setting to take effect on the respective output pads, the * pins must have been configured properly. If not, it will take effect * whenever the pin has been properly configured. * * @param[in] port * The GPIO port to access. * * @param[in] pins * Bit mask for bits to set to 1 in DOUT register. ******************************************************************************/ __STATIC_INLINE void GPIO_PortOutSet(GPIO_Port_TypeDef port, uint32_t pins) { EFM_ASSERT(GPIO_PORT_VALID(port)); #if defined(_GPIO_P_DOUTSET_MASK) GPIO->P[port].DOUTSET = pins; #elif defined(GPIO_HAS_SET_CLEAR) GPIO->P_SET[port].DOUT = pins; #else BUS_RegMaskedSet(&GPIO->P[port].DOUT, pins); #endif } /***************************************************************************//** * @brief * Set GPIO port data out register. * * @note * In order for the setting to take effect on the respective output pads, the * pins must have been configured properly. If not, it will take effect * whenever the pin has been properly configured. * * @param[in] port * The GPIO port to access. * * @param[in] val * Value to write to port data out register. * * @param[in] mask * Mask indicating which bits to modify. ******************************************************************************/ __STATIC_INLINE void GPIO_PortOutSetVal(GPIO_Port_TypeDef port, uint32_t val, uint32_t mask) { EFM_ASSERT(GPIO_PORT_VALID(port)); GPIO->P[port].DOUT = (GPIO->P[port].DOUT & ~mask) | (val & mask); } /***************************************************************************//** * @brief * Toggle pins in GPIO port data out register. * * @note * In order for the setting to take effect on the output pad, the pin must * have been configured properly. If not, it will take effect whenever the * pin has been properly configured. * * @param[in] port * The GPIO port to access. * * @param[in] pins * Bit mask with pins to toggle. ******************************************************************************/ __STATIC_INLINE void GPIO_PortOutToggle(GPIO_Port_TypeDef port, uint32_t pins) { EFM_ASSERT(GPIO_PORT_VALID(port)); #if defined (GPIO_HAS_SET_CLEAR) GPIO->P_TGL[port].DOUT = pins; #else GPIO->P[port].DOUTTGL = pins; #endif } #if defined(_GPIO_P_CTRL_SLEWRATE_MASK) /***************************************************************************//** * @brief * Set slewrate for pins on a GPIO port. * * @param[in] port * The GPIO port to configure. * * @param[in] slewrate * The slewrate to configure for pins on this GPIO port. * * @param[in] slewrateAlt * The slewrate to configure for pins using alternate modes on this GPIO port. ******************************************************************************/ __STATIC_INLINE void GPIO_SlewrateSet(GPIO_Port_TypeDef port, uint32_t slewrate, uint32_t slewrateAlt) { EFM_ASSERT(GPIO_PORT_VALID(port)); EFM_ASSERT(slewrate <= (_GPIO_P_CTRL_SLEWRATE_MASK >> _GPIO_P_CTRL_SLEWRATE_SHIFT)); EFM_ASSERT(slewrateAlt <= (_GPIO_P_CTRL_SLEWRATEALT_MASK >> _GPIO_P_CTRL_SLEWRATEALT_SHIFT)); GPIO->P[port].CTRL = (GPIO->P[port].CTRL & ~(_GPIO_P_CTRL_SLEWRATE_MASK | _GPIO_P_CTRL_SLEWRATEALT_MASK)) | (slewrate << _GPIO_P_CTRL_SLEWRATE_SHIFT) | (slewrateAlt << _GPIO_P_CTRL_SLEWRATEALT_SHIFT); } #endif /***************************************************************************//** * @brief * Unlocks the GPIO configuration. ******************************************************************************/ __STATIC_INLINE void GPIO_Unlock(void) { GPIO->LOCK = GPIO_LOCK_LOCKKEY_UNLOCK; } /******************************************************************************* *********************** DEPRECATED PROTOTYPES ***************************** *********************** (will be removed) ***************************** ******************************************************************************/ /***************************************************************************//** * @brief * Configure GPIO interrupt. * * @details * If reconfiguring a GPIO interrupt that is already enabled, it is generally * recommended to disable it first, see @ref GPIO_Disable(). * * The actual GPIO interrupt handler must be in place before enabling the * interrupt. * * Notice that any pending interrupt for the selected pin is cleared by this * function. * * @deprecated * Deprecated function. New code should use @ref GPIO_ExtIntConfig(). * * @note * A certain pin number can only be associated with one port; i.e., if GPIO * interrupt 1 is assigned to port A/pin 1, then it is not possible to use * pin 1 from any other ports for interrupts. Refer to the reference * manual. On devices which implement GPIO_EXTIPINSEL registers a more * flexible approach is possible, refer to @ref GPIO_ExtIntConfig(). * * @param[in] port * The port to associate with @p pin. * * @param[in] pin * The pin number on the port ( == GPIO EXTI interrupt number). * * @param[in] risingEdge * Set to true if interrupts will be enabled on rising edge, otherwise false. * * @param[in] fallingEdge * Set to true if interrupts will be enabled on falling edge, otherwise false. * * @param[in] enable * Set to true if interrupt will be enabled after configuration completed, * false to leave disabled. See @ref GPIO_IntDisable() and @ref GPIO_IntEnable(). ******************************************************************************/ __STATIC_INLINE void GPIO_IntConfig(GPIO_Port_TypeDef port, unsigned int pin, bool risingEdge, bool fallingEdge, bool enable) { GPIO_ExtIntConfig(port, pin, pin, risingEdge, fallingEdge, enable); } /** @} (end addtogroup GPIO) */ /** @} (end addtogroup emlib) */ #ifdef __cplusplus } #endif #endif /* defined(GPIO_COUNT) && (GPIO_COUNT > 0) */ #endif /* EM_GPIO_H */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/emlib/inc/em_i2c.h.
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/***************************************************************************//** * @file * @brief Inter-integrated circuit (I2C) peripheral API * @version 5.7.0 ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * SPDX-License-Identifier: Zlib * * The licensor of this software is Silicon Laboratories Inc. * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be * appreciated but is not required. * 2. Altered source versions must be plainly marked as such, and must not be * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * ******************************************************************************/ #ifndef EM_I2C_H #define EM_I2C_H #include "em_device.h" #if defined(I2C_COUNT) && (I2C_COUNT > 0) #include <stdbool.h> #ifdef __cplusplus extern "C" { #endif /***************************************************************************//** * @addtogroup emlib * @{ ******************************************************************************/ /***************************************************************************//** * @addtogroup I2C * @{ ******************************************************************************/ /******************************************************************************* ******************************* DEFINES *********************************** ******************************************************************************/ /** * @brief * Standard mode max frequency assuming using 4:4 ratio for Nlow:Nhigh. * @details * From I2C specification: Min Tlow = 4.7us, min Thigh = 4.0us, * max Trise=1.0us, max Tfall=0.3us. Since ratio is 4:4, have to use * worst case value of Tlow or Thigh as base. * * 1/(Tlow + Thigh + 1us + 0.3us) = 1/(4.7 + 4.7 + 1.3)us = 93458Hz * @note * Due to chip characteristics, max value is somewhat reduced. */ #if defined(_SILICON_LABS_32B_SERIES_0) \ && (defined(_EFM32_GECKO_FAMILY) \ || defined(_EFM32_TINY_FAMILY) \ || defined(_EFM32_ZERO_FAMILY) \ || defined(_EFM32_HAPPY_FAMILY)) #define I2C_FREQ_STANDARD_MAX 93000 #elif defined(_SILICON_LABS_32B_SERIES_0) \ && (defined(_EFM32_GIANT_FAMILY) \ || defined(_EFM32_WONDER_FAMILY)) #define I2C_FREQ_STANDARD_MAX 92000 #elif defined(_SILICON_LABS_32B_SERIES_1) // None of the chips on this platform has been characterized on this parameter. // Use same value as on Wonder until further notice. #define I2C_FREQ_STANDARD_MAX 92000 #elif defined(_SILICON_LABS_32B_SERIES_2) #define I2C_FREQ_STANDARD_MAX 100000 #else #error "Unknown device family." #endif /** * @brief * Fast mode max frequency assuming using 6:3 ratio for Nlow:Nhigh. * @details * From I2C specification: Min Tlow = 1.3us, min Thigh = 0.6us, * max Trise=0.3us, max Tfall=0.3us. Since ratio is 6:3, have to use * worst case value of Tlow or 2xThigh as base. * * 1/(Tlow + Thigh + 0.3us + 0.3us) = 1/(1.3 + 0.65 + 0.6)us = 392157Hz */ #define I2C_FREQ_FAST_MAX 392157 /** * @brief * Fast mode+ max frequency assuming using 11:6 ratio for Nlow:Nhigh. * @details * From I2C specification: Min Tlow = 0.5us, min Thigh = 0.26us, * max Trise=0.12us, max Tfall=0.12us. Since ratio is 11:6, have to use * worst case value of Tlow or (11/6)xThigh as base. * * 1/(Tlow + Thigh + 0.12us + 0.12us) = 1/(0.5 + 0.273 + 0.24)us = 987167Hz */ #define I2C_FREQ_FASTPLUS_MAX 987167 /** * @brief * Indicate plain write sequence: S+ADDR(W)+DATA0+P. * @details * @li S - Start * @li ADDR(W) - address with W/R bit cleared * @li DATA0 - Data taken from buffer with index 0 * @li P - Stop */ #define I2C_FLAG_WRITE 0x0001 /** * @brief * Indicate plain read sequence: S+ADDR(R)+DATA0+P. * @details * @li S - Start * @li ADDR(R) - Address with W/R bit set * @li DATA0 - Data read into buffer with index 0 * @li P - Stop */ #define I2C_FLAG_READ 0x0002 /** * @brief * Indicate combined write/read sequence: S+ADDR(W)+DATA0+Sr+ADDR(R)+DATA1+P. * @details * @li S - Start * @li Sr - Repeated start * @li ADDR(W) - Address with W/R bit cleared * @li ADDR(R) - Address with W/R bit set * @li DATAn - Data written from/read into buffer with index n * @li P - Stop */ #define I2C_FLAG_WRITE_READ 0x0004 /** * @brief * Indicate write sequence using two buffers: S+ADDR(W)+DATA0+DATA1+P. * @details * @li S - Start * @li ADDR(W) - Address with W/R bit cleared * @li DATAn - Data written from buffer with index n * @li P - Stop */ #define I2C_FLAG_WRITE_WRITE 0x0008 /** Use 10 bit address. */ #define I2C_FLAG_10BIT_ADDR 0x0010 /******************************************************************************* ******************************** ENUMS ************************************ ******************************************************************************/ /** Clock low to high ratio settings. */ typedef enum { i2cClockHLRStandard = _I2C_CTRL_CLHR_STANDARD, /**< Ratio is 4:4 */ i2cClockHLRAsymetric = _I2C_CTRL_CLHR_ASYMMETRIC, /**< Ratio is 6:3 */ i2cClockHLRFast = _I2C_CTRL_CLHR_FAST /**< Ratio is 11:3 */ } I2C_ClockHLR_TypeDef; /** Return codes for single master mode transfer function. */ typedef enum { /* In progress code (>0) */ i2cTransferInProgress = 1, /**< Transfer in progress. */ /* Complete code (=0) */ i2cTransferDone = 0, /**< Transfer completed successfully. */ /* Transfer error codes (<0). */ i2cTransferNack = -1, /**< NACK received during transfer. */ i2cTransferBusErr = -2, /**< Bus error during transfer (misplaced START/STOP). */ i2cTransferArbLost = -3, /**< Arbitration lost during transfer. */ i2cTransferUsageFault = -4, /**< Usage fault. */ i2cTransferSwFault = -5 /**< SW fault. */ } I2C_TransferReturn_TypeDef; /******************************************************************************* ******************************* STRUCTS *********************************** ******************************************************************************/ /** I2C initialization structure. */ typedef struct { /** Enable I2C peripheral when initialization completed. */ bool enable; /** Set to master (true) or slave (false) mode */ bool master; /** * I2C reference clock assumed when configuring bus frequency setup. * Set it to 0 if currently configured reference clock will be used * This parameter is only applicable if operating in master mode. */ uint32_t refFreq; /** * (Max) I2C bus frequency to use. This parameter is only applicable * if operating in master mode. */ uint32_t freq; /** Clock low/high ratio control. */ I2C_ClockHLR_TypeDef clhr; } I2C_Init_TypeDef; /** Suggested default configuration for I2C initialization structure. */ #define I2C_INIT_DEFAULT \ { \ true, /* Enable when initialization done. */ \ true, /* Set to master mode. */ \ 0, /* Use currently configured reference clock. */ \ I2C_FREQ_STANDARD_MAX, /* Set to standard rate assuring being */ \ /* within I2C specification. */ \ i2cClockHLRStandard /* Set to use 4:4 low/high duty cycle. */ \ } /** * @brief * Master mode transfer message structure used to define a complete * I2C transfer sequence (from start to stop). * @details * The structure allows for defining the following types of sequences * (refer to defines for sequence details): * @li #I2C_FLAG_READ - Data read into buf[0].data * @li #I2C_FLAG_WRITE - Data written from buf[0].data * @li #I2C_FLAG_WRITE_READ - Data written from buf[0].data and read * into buf[1].data * @li #I2C_FLAG_WRITE_WRITE - Data written from buf[0].data and * buf[1].data */ typedef struct { /** * @brief * Address to use after (repeated) start. * @details * Layout details, A = Address bit, X = don't care bit (set to 0): * @li 7 bit address - Use format AAAA AAAX * @li 10 bit address - Use format XXXX XAAX AAAA AAAA */ uint16_t addr; /** Flags defining sequence type and details, see I2C_FLAG_ defines. */ uint16_t flags; /** * Buffers used to hold data to send from or receive into, depending * on sequence type. */ struct { /** Buffer used for data to transmit/receive, must be @p len long. */ uint8_t *data; /** * Number of bytes in @p data to send or receive. Notice that when * receiving data to this buffer, at least 1 byte must be received. * Setting @p len to 0 in the receive case is considered a usage fault. * Transmitting 0 bytes is legal, in which case only the address * is transmitted after the start condition. */ uint16_t len; } buf[2]; } I2C_TransferSeq_TypeDef; /******************************************************************************* ***************************** PROTOTYPES ********************************** ******************************************************************************/ uint32_t I2C_BusFreqGet(I2C_TypeDef *i2c); void I2C_BusFreqSet(I2C_TypeDef *i2c, uint32_t freqRef, uint32_t freqScl, I2C_ClockHLR_TypeDef i2cMode); void I2C_Enable(I2C_TypeDef *i2c, bool enable); void I2C_Init(I2C_TypeDef *i2c, const I2C_Init_TypeDef *init); /***************************************************************************//** * @brief * Clear one or more pending I2C interrupts. * * @param[in] i2c * Pointer to I2C peripheral register block. * * @param[in] flags * Pending I2C interrupt source to clear. Use a bitwise logic OR combination of * valid interrupt flags for the I2C module (I2C_IF_nnn). ******************************************************************************/ __STATIC_INLINE void I2C_IntClear(I2C_TypeDef *i2c, uint32_t flags) { #if defined (I2C_HAS_SET_CLEAR) i2c->IF_CLR = flags; #else i2c->IFC = flags; #endif } /***************************************************************************//** * @brief * Disable one or more I2C interrupts. * * @param[in] i2c * Pointer to I2C peripheral register block. * * @param[in] flags * I2C interrupt sources to disable. Use a bitwise logic OR combination of * valid interrupt flags for the I2C module (I2C_IF_nnn). ******************************************************************************/ __STATIC_INLINE void I2C_IntDisable(I2C_TypeDef *i2c, uint32_t flags) { #if defined (I2C_HAS_SET_CLEAR) i2c->IEN_CLR = flags; #else i2c->IEN &= ~(flags); #endif } /***************************************************************************//** * @brief * Enable one or more I2C interrupts. * * @note * Depending on the use, a pending interrupt may already be set prior to * enabling the interrupt. To ignore a pending interrupt, consider using * I2C_IntClear() prior to enabling the interrupt. * * @param[in] i2c * Pointer to I2C peripheral register block. * * @param[in] flags * I2C interrupt sources to enable. Use a bitwise logic OR combination of * valid interrupt flags for the I2C module (I2C_IF_nnn). ******************************************************************************/ __STATIC_INLINE void I2C_IntEnable(I2C_TypeDef *i2c, uint32_t flags) { #if defined (I2C_HAS_SET_CLEAR) i2c->IEN_SET = flags; #else i2c->IEN |= flags; #endif } /***************************************************************************//** * @brief * Get pending I2C interrupt flags. * * @note * Event bits are not cleared by the use of this function. * * @param[in] i2c * Pointer to I2C peripheral register block. * * @return * I2C interrupt sources pending. A bitwise logic OR combination of valid * interrupt flags for the I2C module (I2C_IF_nnn). ******************************************************************************/ __STATIC_INLINE uint32_t I2C_IntGet(I2C_TypeDef *i2c) { return i2c->IF; } /***************************************************************************//** * @brief * Get enabled and pending I2C interrupt flags. * Useful for handling more interrupt sources in the same interrupt handler. * * @note * Interrupt flags are not cleared by the use of this function. * * @param[in] i2c * Pointer to I2C peripheral register block. * * @return * Pending and enabled I2C interrupt sources * Return value is the bitwise AND of * - the enabled interrupt sources in I2Cn_IEN and * - the pending interrupt flags I2Cn_IF ******************************************************************************/ __STATIC_INLINE uint32_t I2C_IntGetEnabled(I2C_TypeDef *i2c) { uint32_t ien; ien = i2c->IEN; return i2c->IF & ien; } /***************************************************************************//** * @brief * Set one or more pending I2C interrupts from SW. * * @param[in] i2c * Pointer to I2C peripheral register block. * * @param[in] flags * I2C interrupt sources to set to pending. Use a bitwise logic OR combination * of valid interrupt flags for the I2C module (I2C_IF_nnn). ******************************************************************************/ __STATIC_INLINE void I2C_IntSet(I2C_TypeDef *i2c, uint32_t flags) { #if defined (I2C_HAS_SET_CLEAR) i2c->IF_SET = flags; #else i2c->IFS = flags; #endif } void I2C_Reset(I2C_TypeDef *i2c); /***************************************************************************//** * @brief * Get slave address used for I2C peripheral (when operating in slave mode). * * @details * For 10-bit addressing mode, the address is split in two bytes, and only * the first byte setting is fetched, effectively only controlling the 2 most * significant bits of the 10-bit address. Full handling of 10-bit addressing * in slave mode requires additional SW handling. * * @param[in] i2c * Pointer to I2C peripheral register block. * * @return * I2C slave address in use. The 7 most significant bits define the actual * address, the least significant bit is reserved and always returned as 0. ******************************************************************************/ __STATIC_INLINE uint8_t I2C_SlaveAddressGet(I2C_TypeDef *i2c) { return ((uint8_t)(i2c->SADDR)); } /***************************************************************************//** * @brief * Set slave address to use for I2C peripheral (when operating in slave mode). * * @details * For 10- bit addressing mode, the address is split in two bytes, and only * the first byte is set, effectively only controlling the 2 most significant * bits of the 10-bit address. Full handling of 10-bit addressing in slave * mode requires additional SW handling. * * @param[in] i2c * Pointer to I2C peripheral register block. * * @param[in] addr * I2C slave address to use. The 7 most significant bits define the actual * address, the least significant bit is reserved and always set to 0. ******************************************************************************/ __STATIC_INLINE void I2C_SlaveAddressSet(I2C_TypeDef *i2c, uint8_t addr) { i2c->SADDR = (uint32_t)addr & 0xfe; } /***************************************************************************//** * @brief * Get slave address mask used for I2C peripheral (when operating in slave * mode). * * @details * The address mask defines how the comparator works. A bit position with * value 0 means that the corresponding slave address bit is ignored during * comparison (don't care). A bit position with value 1 means that the * corresponding slave address bit must match. * * For 10-bit addressing mode, the address is split in two bytes, and only * the mask for the first address byte is fetched, effectively only * controlling the 2 most significant bits of the 10-bit address. * * @param[in] i2c * Pointer to I2C peripheral register block. * * @return * I2C slave address mask in use. The 7 most significant bits define the * actual address mask, the least significant bit is reserved and always * returned as 0. ******************************************************************************/ __STATIC_INLINE uint8_t I2C_SlaveAddressMaskGet(I2C_TypeDef *i2c) { return ((uint8_t)(i2c->SADDRMASK)); } /***************************************************************************//** * @brief * Set slave address mask used for I2C peripheral (when operating in slave * mode). * * @details * The address mask defines how the comparator works. A bit position with * value 0 means that the corresponding slave address bit is ignored during * comparison (don't care). A bit position with value 1 means that the * corresponding slave address bit must match. * * For 10-bit addressing mode, the address is split in two bytes, and only * the mask for the first address byte is set, effectively only controlling * the 2 most significant bits of the 10-bit address. * * @param[in] i2c * Pointer to I2C peripheral register block. * * @param[in] mask * I2C slave address mask to use. The 7 most significant bits define the * actual address mask, the least significant bit is reserved and should * be 0. ******************************************************************************/ __STATIC_INLINE void I2C_SlaveAddressMaskSet(I2C_TypeDef *i2c, uint8_t mask) { i2c->SADDRMASK = (uint32_t)mask & 0xfe; } I2C_TransferReturn_TypeDef I2C_Transfer(I2C_TypeDef *i2c); I2C_TransferReturn_TypeDef I2C_TransferInit(I2C_TypeDef *i2c, I2C_TransferSeq_TypeDef *seq); /** @} (end addtogroup I2C) */ /** @} (end addtogroup emlib) */ #ifdef __cplusplus } #endif #endif /* defined(I2C_COUNT) && (I2C_COUNT > 0) */ #endif /* EM_I2C_H */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/emlib/inc/em_ldma.h.
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/***************************************************************************//** * @file * @brief Direct memory access (LDMA) API * @version 5.7.0 ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * SPDX-License-Identifier: Zlib * * The licensor of this software is Silicon Laboratories Inc. * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be * appreciated but is not required. * 2. Altered source versions must be plainly marked as such, and must not be * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * ******************************************************************************/ #ifndef EM_LDMA_H #define EM_LDMA_H #include "em_device.h" #if defined(LDMA_PRESENT) && (LDMA_COUNT == 1) #include <stdbool.h> #ifdef __cplusplus extern "C" { #endif /***************************************************************************//** * @addtogroup emlib * @{ ******************************************************************************/ /***************************************************************************//** * @addtogroup LDMA * @brief Linked Direct Memory Access (LDMA) Peripheral API * * @details * LDMA API functions provide full support for the LDMA peripheral. * * LDMA supports these DMA transfer types: * * @li Memory to memory. * @li Memory to peripheral. * @li Peripheral to memory. * @li Peripheral to peripheral. * @li Constant value to memory. * * LDMA supports linked lists of DMA descriptors allowing: * * @li Circular and ping-pong buffer transfers. * @li Scatter-gather transfers. * @li Looped transfers. * * LDMA has some advanced features: * * @li Intra-channel synchronization (SYNC), allowing hardware events to * pause and restart a DMA sequence. * @li Immediate-write (WRI), allowing DMA to write a constant anywhere * in the memory map. * @li Complex flow control allowing if-else constructs. * * Basic understanding of LDMA controller is assumed. Please refer to * the reference manual for further details. The LDMA examples described * in the reference manual are particularly helpful in understanding LDMA * operations. * * In order to use the DMA controller, the initialization function @ref * LDMA_Init() must have been executed once (normally during system initialization). * * DMA transfers are initiated by a call to @ref LDMA_StartTransfer(), * transfer properties are controlled by the contents of @ref LDMA_TransferCfg_t * and @ref LDMA_Descriptor_t structure parameters. * The @htmlonly LDMA_Descriptor_t @endhtmlonly structure parameter may be a * pointer to an array of descriptors, descriptors in array should * be linked together as needed. * * Transfer and descriptor initialization macros are provided for the most common * transfer types. Due to the flexibility of LDMA peripheral, only a small * subset of all possible initializer macros are provided, users should create * new ones when needed. * * <b> Examples of LDMA usage: </b> * * A simple memory to memory transfer: * * @include em_ldma_single.c * * @n A linked list of three memory to memory transfers: * * @include em_ldma_link_memory.c * * @n DMA from serial port peripheral to memory: * * @include em_ldma_peripheral.c * * @n Ping-pong DMA from serial port peripheral to memory: * * @include em_ldma_pingpong.c * * @note LDMA module does not implement LDMA interrupt handler. A * template for an LDMA IRQ handler is included here as an example. * * @include em_ldma_irq.c * * @{ ******************************************************************************/ /******************************************************************************* ******************************** ENUMS ************************************ ******************************************************************************/ /** * Controls the number of unit data transfers per arbitration * cycle, providing a means to balance DMA channels' load on the controller. */ typedef enum { ldmaCtrlBlockSizeUnit1 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT1, /**< One transfer per arbitration. */ ldmaCtrlBlockSizeUnit2 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT2, /**< Two transfers per arbitration. */ ldmaCtrlBlockSizeUnit3 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT3, /**< Three transfers per arbitration. */ ldmaCtrlBlockSizeUnit4 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT4, /**< Four transfers per arbitration. */ ldmaCtrlBlockSizeUnit6 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT6, /**< Six transfers per arbitration. */ ldmaCtrlBlockSizeUnit8 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT8, /**< Eight transfers per arbitration. */ ldmaCtrlBlockSizeUnit16 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT16, /**< 16 transfers per arbitration. */ ldmaCtrlBlockSizeUnit32 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT32, /**< 32 transfers per arbitration. */ ldmaCtrlBlockSizeUnit64 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT64, /**< 64 transfers per arbitration. */ ldmaCtrlBlockSizeUnit128 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT128, /**< 128 transfers per arbitration. */ ldmaCtrlBlockSizeUnit256 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT256, /**< 256 transfers per arbitration. */ ldmaCtrlBlockSizeUnit512 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT512, /**< 512 transfers per arbitration. */ ldmaCtrlBlockSizeUnit1024 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT1024, /**< 1024 transfers per arbitration. */ ldmaCtrlBlockSizeAll = _LDMA_CH_CTRL_BLOCKSIZE_ALL /**< Lock arbitration during transfer. */ } LDMA_CtrlBlockSize_t; /** DMA structure type. */ typedef enum { ldmaCtrlStructTypeXfer = _LDMA_CH_CTRL_STRUCTTYPE_TRANSFER, /**< TRANSFER transfer type. */ ldmaCtrlStructTypeSync = _LDMA_CH_CTRL_STRUCTTYPE_SYNCHRONIZE, /**< SYNCHRONIZE transfer type. */ ldmaCtrlStructTypeWrite = _LDMA_CH_CTRL_STRUCTTYPE_WRITE /**< WRITE transfer type. */ } LDMA_CtrlStructType_t; /** DMA transfer block or cycle selector. */ typedef enum { ldmaCtrlReqModeBlock = _LDMA_CH_CTRL_REQMODE_BLOCK, /**< Each DMA request trigger transfer of one block. */ ldmaCtrlReqModeAll = _LDMA_CH_CTRL_REQMODE_ALL /**< A DMA request trigger transfer of a complete cycle. */ } LDMA_CtrlReqMode_t; /** Source address increment unit size. */ typedef enum { ldmaCtrlSrcIncOne = _LDMA_CH_CTRL_SRCINC_ONE, /**< Increment source address by one unit data size. */ ldmaCtrlSrcIncTwo = _LDMA_CH_CTRL_SRCINC_TWO, /**< Increment source address by two unit data sizes. */ ldmaCtrlSrcIncFour = _LDMA_CH_CTRL_SRCINC_FOUR, /**< Increment source address by four unit data sizes. */ ldmaCtrlSrcIncNone = _LDMA_CH_CTRL_SRCINC_NONE /**< Do not increment source address. */ } LDMA_CtrlSrcInc_t; /** DMA transfer unit size. */ typedef enum { ldmaCtrlSizeByte = _LDMA_CH_CTRL_SIZE_BYTE, /**< Each unit transfer is a byte. */ ldmaCtrlSizeHalf = _LDMA_CH_CTRL_SIZE_HALFWORD, /**< Each unit transfer is a half-word. */ ldmaCtrlSizeWord = _LDMA_CH_CTRL_SIZE_WORD /**< Each unit transfer is a word. */ } LDMA_CtrlSize_t; /** Destination address increment unit size. */ typedef enum { ldmaCtrlDstIncOne = _LDMA_CH_CTRL_DSTINC_ONE, /**< Increment destination address by one unit data size. */ ldmaCtrlDstIncTwo = _LDMA_CH_CTRL_DSTINC_TWO, /**< Increment destination address by two unit data sizes. */ ldmaCtrlDstIncFour = _LDMA_CH_CTRL_DSTINC_FOUR, /**< Increment destination address by four unit data sizes. */ ldmaCtrlDstIncNone = _LDMA_CH_CTRL_DSTINC_NONE /**< Do not increment destination address. */ } LDMA_CtrlDstInc_t; /** Source addressing mode. */ typedef enum { ldmaCtrlSrcAddrModeAbs = _LDMA_CH_CTRL_SRCMODE_ABSOLUTE, /**< Address fetched from a linked structure is absolute. */ ldmaCtrlSrcAddrModeRel = _LDMA_CH_CTRL_SRCMODE_RELATIVE /**< Address fetched from a linked structure is relative. */ } LDMA_CtrlSrcAddrMode_t; /** Destination addressing mode. */ typedef enum { ldmaCtrlDstAddrModeAbs = _LDMA_CH_CTRL_DSTMODE_ABSOLUTE, /**< Address fetched from a linked structure is absolute. */ ldmaCtrlDstAddrModeRel = _LDMA_CH_CTRL_DSTMODE_RELATIVE /**< Address fetched from a linked structure is relative. */ } LDMA_CtrlDstAddrMode_t; /** DMA link load address mode. */ typedef enum { ldmaLinkModeAbs = _LDMA_CH_LINK_LINKMODE_ABSOLUTE, /**< Link address is an absolute address value. */ ldmaLinkModeRel = _LDMA_CH_LINK_LINKMODE_RELATIVE /**< Link address is a two's complement relative address. */ } LDMA_LinkMode_t; /** Insert extra arbitration slots to increase channel arbitration priority. */ typedef enum { ldmaCfgArbSlotsAs1 = _LDMA_CH_CFG_ARBSLOTS_ONE, /**< One arbitration slot selected. */ ldmaCfgArbSlotsAs2 = _LDMA_CH_CFG_ARBSLOTS_TWO, /**< Two arbitration slots selected. */ ldmaCfgArbSlotsAs4 = _LDMA_CH_CFG_ARBSLOTS_FOUR, /**< Four arbitration slots selected. */ ldmaCfgArbSlotsAs8 = _LDMA_CH_CFG_ARBSLOTS_EIGHT /**< Eight arbitration slots selected. */ } LDMA_CfgArbSlots_t; /** Source address increment sign. */ typedef enum { ldmaCfgSrcIncSignPos = _LDMA_CH_CFG_SRCINCSIGN_POSITIVE, /**< Increment source address. */ ldmaCfgSrcIncSignNeg = _LDMA_CH_CFG_SRCINCSIGN_NEGATIVE /**< Decrement source address. */ } LDMA_CfgSrcIncSign_t; /** Destination address increment sign. */ typedef enum { ldmaCfgDstIncSignPos = _LDMA_CH_CFG_DSTINCSIGN_POSITIVE, /**< Increment destination address. */ ldmaCfgDstIncSignNeg = _LDMA_CH_CFG_DSTINCSIGN_NEGATIVE /**< Decrement destination address. */ } LDMA_CfgDstIncSign_t; #if defined(LDMAXBAR_COUNT) && (LDMAXBAR_COUNT > 0) /** Peripherals that can trigger LDMA transfers. */ typedef enum { ldmaPeripheralSignal_NONE = LDMAXBAR_CH_REQSEL_SOURCESEL_NONE, ///< No peripheral selected for DMA triggering. #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC0 ldmaPeripheralSignal_TIMER0_CC0 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC0 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER0, #endif #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC1 ldmaPeripheralSignal_TIMER0_CC1 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC1 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER0, #endif #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC2 ldmaPeripheralSignal_TIMER0_CC2 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC2 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER0, #endif #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0UFOF ldmaPeripheralSignal_TIMER0_UFOF = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0UFOF | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER0, #endif #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC0 ldmaPeripheralSignal_TIMER1_CC0 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC0 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER1, #endif #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC1 ldmaPeripheralSignal_TIMER1_CC1 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC1 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER1, #endif #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC2 ldmaPeripheralSignal_TIMER1_CC2 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC2 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER1, #endif #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1UFOF ldmaPeripheralSignal_TIMER1_UFOF = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1UFOF | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER1, #endif #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAV ldmaPeripheralSignal_USART0_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAV | LDMAXBAR_CH_REQSEL_SOURCESEL_USART0, #endif #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAVRIGHT ldmaPeripheralSignal_USART0_RXDATAVRIGHT = LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAVRIGHT | LDMAXBAR_CH_REQSEL_SOURCESEL_USART0, #endif #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBL ldmaPeripheralSignal_USART0_TXBL = LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBL | LDMAXBAR_CH_REQSEL_SOURCESEL_USART0, #endif #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBLRIGHT ldmaPeripheralSignal_USART0_TXBLRIGHT = LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBLRIGHT | LDMAXBAR_CH_REQSEL_SOURCESEL_USART0, #endif #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXEMPTY ldmaPeripheralSignal_USART0_TXEMPTY = LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXEMPTY | LDMAXBAR_CH_REQSEL_SOURCESEL_USART0, #endif #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART1RXDATAV ldmaPeripheralSignal_USART1_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_USART1RXDATAV | LDMAXBAR_CH_REQSEL_SOURCESEL_USART1, #endif #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT ldmaPeripheralSignal_USART1_RXDATAVRIGHT = LDMAXBAR_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT | LDMAXBAR_CH_REQSEL_SOURCESEL_USART1, #endif #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXBL ldmaPeripheralSignal_USART1_TXBL = LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXBL | LDMAXBAR_CH_REQSEL_SOURCESEL_USART1, #endif #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXBLRIGHT ldmaPeripheralSignal_USART1_TXBLRIGHT = LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXBLRIGHT | LDMAXBAR_CH_REQSEL_SOURCESEL_USART1, #endif #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXEMPTY ldmaPeripheralSignal_USART1_TXEMPTY = LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXEMPTY | LDMAXBAR_CH_REQSEL_SOURCESEL_USART1, #endif #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART2RXDATAV ldmaPeripheralSignal_USART2_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_USART2RXDATAV | LDMAXBAR_CH_REQSEL_SOURCESEL_USART2, #endif #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART2RXDATAVRIGHT ldmaPeripheralSignal_USART2_RXDATAVRIGHT = LDMAXBAR_CH_REQSEL_SIGSEL_USART2RXDATAVRIGHT | LDMAXBAR_CH_REQSEL_SOURCESEL_USART2, #endif #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART2TXBL ldmaPeripheralSignal_USART2_TXBL = LDMAXBAR_CH_REQSEL_SIGSEL_USART2TXBL | LDMAXBAR_CH_REQSEL_SOURCESEL_USART2, #endif #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART2TXBLRIGHT ldmaPeripheralSignal_USART2_TXBLRIGHT = LDMAXBAR_CH_REQSEL_SIGSEL_USART2TXBLRIGHT | LDMAXBAR_CH_REQSEL_SOURCESEL_USART2, #endif #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART2TXEMPTY ldmaPeripheralSignal_USART2_TXEMPTY = LDMAXBAR_CH_REQSEL_SIGSEL_USART2TXEMPTY | LDMAXBAR_CH_REQSEL_SOURCESEL_USART2, #endif #if defined LDMAXBAR_CH_REQSEL_SIGSEL_I2C0RXDATAV ldmaPeripheralSignal_I2C0_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_I2C0RXDATAV | LDMAXBAR_CH_REQSEL_SOURCESEL_I2C0, #endif #if defined LDMAXBAR_CH_REQSEL_SIGSEL_I2C0TXBL ldmaPeripheralSignal_I2C0_TXBL = LDMAXBAR_CH_REQSEL_SIGSEL_I2C0TXBL | LDMAXBAR_CH_REQSEL_SOURCESEL_I2C0, #endif #if defined LDMAXBAR_CH_REQSEL_SIGSEL_I2C1RXDATAV ldmaPeripheralSignal_I2C1_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_I2C1RXDATAV | LDMAXBAR_CH_REQSEL_SOURCESEL_I2C1, #endif #if defined LDMAXBAR_CH_REQSEL_SIGSEL_I2C1TXBL ldmaPeripheralSignal_I2C1_TXBL = LDMAXBAR_CH_REQSEL_SIGSEL_I2C1TXBL | LDMAXBAR_CH_REQSEL_SOURCESEL_I2C1, #endif #if defined LDMAXBAR_CH_REQSEL_SIGSEL_AGCRSSI ldmaPeripheralSignal_AGC_RSSI = LDMAXBAR_CH_REQSEL_SIGSEL_AGCRSSI | LDMAXBAR_CH_REQSEL_SOURCESEL_AGC, #endif #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERBOF ldmaPeripheralSignal_PROTIMER_BOF = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERBOF | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER, #endif #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC0 ldmaPeripheralSignal_PROTIMER_CC0 = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC0 | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER, #endif #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC1 ldmaPeripheralSignal_PROTIMER_CC1 = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC1 | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER, #endif #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC2 ldmaPeripheralSignal_PROTIMER_CC2 = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC2 | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER, #endif #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC3 ldmaPeripheralSignal_PROTIMER_CC3 = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC3 | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER, #endif #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC4 ldmaPeripheralSignal_PROTIMER_CC4 = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC4 | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER, #endif #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERPOF ldmaPeripheralSignal_PROTIMER_POF = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERPOF | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER, #endif #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERWOF ldmaPeripheralSignal_PROTIMER_WOF = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERWOF | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER, #endif #if defined LDMAXBAR_CH_REQSEL_SIGSEL_MODEMDEBUG ldmaPeripheralSignal_MODEM_DEBUG = LDMAXBAR_CH_REQSEL_SIGSEL_MODEMDEBUG | LDMAXBAR_CH_REQSEL_SOURCESEL_MODEM, #endif #if defined LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SCAN ldmaPeripheralSignal_IADC0_IADC_SCAN = LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SCAN | LDMAXBAR_CH_REQSEL_SOURCESEL_IADC0, #endif #if defined LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SINGLE ldmaPeripheralSignal_IADC0_IADC_SINGLE = LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SINGLE | LDMAXBAR_CH_REQSEL_SOURCESEL_IADC0, #endif #if defined LDMAXBAR_CH_REQSEL_SIGSEL_IMEMWDATA ldmaPeripheralSignal_IMEM_WDATA = LDMAXBAR_CH_REQSEL_SIGSEL_IMEMWDATA | LDMAXBAR_CH_REQSEL_SOURCESEL_IMEM, #endif #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC0 ldmaPeripheralSignal_TIMER2_CC0 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC0 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER2, #endif #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC1 ldmaPeripheralSignal_TIMER2_CC1 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC1 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER2, #endif #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC2 ldmaPeripheralSignal_TIMER2_CC2 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC2 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER2, #endif #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2UFOF ldmaPeripheralSignal_TIMER2_UFOF = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2UFOF | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER2, #endif #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC0 ldmaPeripheralSignal_TIMER3_CC0 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC0 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER3, #endif #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC1 ldmaPeripheralSignal_TIMER3_CC1 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC1 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER3, #endif #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC2 ldmaPeripheralSignal_TIMER3_CC2 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC2 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER3, #endif #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3UFOF ldmaPeripheralSignal_TIMER3_UFOF = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3UFOF | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER3, #endif } LDMA_PeripheralSignal_t; #else typedef enum { ldmaPeripheralSignal_NONE = LDMA_CH_REQSEL_SOURCESEL_NONE, ///< No peripheral selected for DMA triggering. #if defined(LDMA_CH_REQSEL_SIGSEL_ADC0SCAN) ldmaPeripheralSignal_ADC0_SCAN = LDMA_CH_REQSEL_SIGSEL_ADC0SCAN | LDMA_CH_REQSEL_SOURCESEL_ADC0, ///< Trigger on ADC0_SCAN. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_ADC0SINGLE) ldmaPeripheralSignal_ADC0_SINGLE = LDMA_CH_REQSEL_SIGSEL_ADC0SINGLE | LDMA_CH_REQSEL_SOURCESEL_ADC0, ///< Trigger on ADC0_SINGLE. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_ADC1SCAN) ldmaPeripheralSignal_ADC1_SCAN = LDMA_CH_REQSEL_SIGSEL_ADC1SCAN | LDMA_CH_REQSEL_SOURCESEL_ADC1, ///< Trigger on ADC1_SCAN. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_ADC1SINGLE) ldmaPeripheralSignal_ADC1_SINGLE = LDMA_CH_REQSEL_SIGSEL_ADC1SINGLE | LDMA_CH_REQSEL_SOURCESEL_ADC1, ///< Trigger on ADC1_SINGLE. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0RD) ldmaPeripheralSignal_CRYPTO_DATA0RD = LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO, ///< Trigger on CRYPTO_DATA0RD. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0WR) ldmaPeripheralSignal_CRYPTO_DATA0WR = LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0WR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO, ///< Trigger on CRYPTO_DATA0WR. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0XWR) ldmaPeripheralSignal_CRYPTO_DATA0XWR = LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0XWR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO, ///< Trigger on CRYPTO_DATA0XWR. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1RD) ldmaPeripheralSignal_CRYPTO_DATA1RD = LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO, ///< Trigger on CRYPTO_DATA1RD. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1WR) ldmaPeripheralSignal_CRYPTO_DATA1WR = LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1WR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO, ///< Trigger on CRYPTO_DATA1WR. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0RD) ldmaPeripheralSignal_CRYPTO0_DATA0RD = LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO0, ///< Trigger on CRYPTO0_DATA0RD. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0WR) ldmaPeripheralSignal_CRYPTO0_DATA0WR = LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0WR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO0, ///< Trigger on CRYPTO0_DATA0WR. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0XWR) ldmaPeripheralSignal_CRYPTO0_DATA0XWR = LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0XWR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO0, ///< Trigger on CRYPTO0_DATA0XWR. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1RD) ldmaPeripheralSignal_CRYPTO0_DATA1RD = LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO0, ///< Trigger on CRYPTO0_DATA1RD. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1WR) ldmaPeripheralSignal_CRYPTO0_DATA1WR = LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1WR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO0, ///< Trigger on CRYPTO0_DATA1WR. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0RD) ldmaPeripheralSignal_CRYPTO1_DATA0RD = LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO1, ///< Trigger on CRYPTO1_DATA0RD. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0WR) ldmaPeripheralSignal_CRYPTO1_DATA0WR = LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0WR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO1, ///< Trigger on CRYPTO1_DATA0WR. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0XWR) ldmaPeripheralSignal_CRYPTO1_DATA0XWR = LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0XWR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO1, ///< Trigger on CRYPTO1_DATA0XWR. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA1RD) ldmaPeripheralSignal_CRYPTO1_DATA1RD = LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA1RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO1, ///< Trigger on CRYPTO1_DATA1RD. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA1WR) ldmaPeripheralSignal_CRYPTO1_DATA1WR = LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA1WR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO1, ///< Trigger on CRYPTO1_DATA1WR. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_CSENBSLN) ldmaPeripheralSignal_CSEN_BSLN = LDMA_CH_REQSEL_SIGSEL_CSENBSLN | LDMA_CH_REQSEL_SOURCESEL_CSEN, ///< Trigger on CSEN_BSLN. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_CSENDATA) ldmaPeripheralSignal_CSEN_DATA = LDMA_CH_REQSEL_SIGSEL_CSENDATA | LDMA_CH_REQSEL_SOURCESEL_CSEN, ///< Trigger on CSEN_DATA. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_EBIPXL0EMPTY) ldmaPeripheralSignal_EBI_PXL0EMPTY = LDMA_CH_REQSEL_SIGSEL_EBIPXL0EMPTY | LDMA_CH_REQSEL_SOURCESEL_EBI, ///< Trigger on EBI_PXL0EMPTY. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_EBIPXL1EMPTY) ldmaPeripheralSignal_EBI_PXL1EMPTY = LDMA_CH_REQSEL_SIGSEL_EBIPXL1EMPTY | LDMA_CH_REQSEL_SOURCESEL_EBI, ///< Trigger on EBI_PXL1EMPTY. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_EBIPXLFULL) ldmaPeripheralSignal_EBI_PXLFULL = LDMA_CH_REQSEL_SIGSEL_EBIPXLFULL | LDMA_CH_REQSEL_SOURCESEL_EBI, ///< Trigger on EBI_PXLFULL. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_EBIDDEMPTY) ldmaPeripheralSignal_EBI_DDEMPTY = LDMA_CH_REQSEL_SIGSEL_EBIDDEMPTY | LDMA_CH_REQSEL_SOURCESEL_EBI, ///< Trigger on EBI_DDEMPTY. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_EBIVSYNC) ldmaPeripheralSignal_EBI_VSYNC = LDMA_CH_REQSEL_SIGSEL_EBIVSYNC | LDMA_CH_REQSEL_SOURCESEL_EBI, ///< Trigger on EBI_VSYNC. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_EBIHSYNC) ldmaPeripheralSignal_EBI_HSYNC = LDMA_CH_REQSEL_SIGSEL_EBIHSYNC | LDMA_CH_REQSEL_SOURCESEL_EBI, ///< Trigger on EBI_HSYNC. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_I2C0RXDATAV) ldmaPeripheralSignal_I2C0_RXDATAV = LDMA_CH_REQSEL_SIGSEL_I2C0RXDATAV | LDMA_CH_REQSEL_SOURCESEL_I2C0, ///< Trigger on I2C0_RXDATAV. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_I2C0TXBL) ldmaPeripheralSignal_I2C0_TXBL = LDMA_CH_REQSEL_SIGSEL_I2C0TXBL | LDMA_CH_REQSEL_SOURCESEL_I2C0, ///< Trigger on I2C0_TXBL. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_I2C1RXDATAV) ldmaPeripheralSignal_I2C1_RXDATAV = LDMA_CH_REQSEL_SIGSEL_I2C1RXDATAV | LDMA_CH_REQSEL_SOURCESEL_I2C1, ///< Trigger on I2C1_RXDATAV. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_I2C1TXBL) ldmaPeripheralSignal_I2C1_TXBL = LDMA_CH_REQSEL_SIGSEL_I2C1TXBL | LDMA_CH_REQSEL_SOURCESEL_I2C1, ///< Trigger on I2C1_TXBL. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_I2C2RXDATAV) ldmaPeripheralSignal_I2C2_RXDATAV = LDMA_CH_REQSEL_SIGSEL_I2C2RXDATAV | LDMA_CH_REQSEL_SOURCESEL_I2C2, ///< Trigger on I2C2_RXDATAV. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_I2C2TXBL) ldmaPeripheralSignal_I2C2_TXBL = LDMA_CH_REQSEL_SIGSEL_I2C2TXBL | LDMA_CH_REQSEL_SOURCESEL_I2C2, ///< Trigger on I2C2_TXBL. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_LESENSEBUFDATAV) ldmaPeripheralSignal_LESENSE_BUFDATAV = LDMA_CH_REQSEL_SIGSEL_LESENSEBUFDATAV | LDMA_CH_REQSEL_SOURCESEL_LESENSE, ///< Trigger on LESENSE_BUFDATAV. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_LEUART0RXDATAV) ldmaPeripheralSignal_LEUART0_RXDATAV = LDMA_CH_REQSEL_SIGSEL_LEUART0RXDATAV | LDMA_CH_REQSEL_SOURCESEL_LEUART0, ///< Trigger on LEUART0_RXDATAV. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_LEUART0TXBL) ldmaPeripheralSignal_LEUART0_TXBL = LDMA_CH_REQSEL_SIGSEL_LEUART0TXBL | LDMA_CH_REQSEL_SOURCESEL_LEUART0, ///< Trigger on LEUART0_TXBL. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_LEUART0TXEMPTY) ldmaPeripheralSignal_LEUART0_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_LEUART0TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_LEUART0, ///< Trigger on LEUART0_TXEMPTY. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_LEUART1RXDATAV) ldmaPeripheralSignal_LEUART1_RXDATAV = LDMA_CH_REQSEL_SIGSEL_LEUART1RXDATAV | LDMA_CH_REQSEL_SOURCESEL_LEUART1, ///< Trigger on LEUART1_RXDATAV. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_LEUART1TXBL) ldmaPeripheralSignal_LEUART1_TXBL = LDMA_CH_REQSEL_SIGSEL_LEUART1TXBL | LDMA_CH_REQSEL_SOURCESEL_LEUART1, ///< Trigger on LEUART1_TXBL. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_LEUART1TXEMPTY) ldmaPeripheralSignal_LEUART1_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_LEUART1TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_LEUART1, ///< Trigger on LEUART1_TXEMPTY. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_MSCWDATA) ldmaPeripheralSignal_MSC_WDATA = LDMA_CH_REQSEL_SIGSEL_MSCWDATA | LDMA_CH_REQSEL_SOURCESEL_MSC, ///< Trigger on MSC_WDATA. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_PDMRXDATAV) ldmaPeripheralSignal_PDM_RXDATAV = LDMA_CH_REQSEL_SIGSEL_PDMRXDATAV | LDMA_CH_REQSEL_SOURCESEL_PDM, ///< Trigger on PDM_RXDATAV. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_PRSREQ0) ldmaPeripheralSignal_PRS_REQ0 = LDMA_CH_REQSEL_SIGSEL_PRSREQ0 | LDMA_CH_REQSEL_SOURCESEL_PRS, ///< Trigger on PRS_REQ0. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_PRSREQ1) ldmaPeripheralSignal_PRS_REQ1 = LDMA_CH_REQSEL_SIGSEL_PRSREQ1 | LDMA_CH_REQSEL_SOURCESEL_PRS, ///< Trigger on PRS_REQ1. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER0CC0) ldmaPeripheralSignal_TIMER0_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER0CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER0, ///< Trigger on TIMER0_CC0. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER0CC1) ldmaPeripheralSignal_TIMER0_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER0CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER0, ///< Trigger on TIMER0_CC1. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER0CC2) ldmaPeripheralSignal_TIMER0_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER0CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER0, ///< Trigger on TIMER0_CC2. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER0UFOF) ldmaPeripheralSignal_TIMER0_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER0UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER0, ///< Trigger on TIMER0_UFOF. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER1CC0) ldmaPeripheralSignal_TIMER1_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER1CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER1, ///< Trigger on TIMER1_CC0. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER1CC1) ldmaPeripheralSignal_TIMER1_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER1CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER1, ///< Trigger on TIMER1_CC1. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER1CC2) ldmaPeripheralSignal_TIMER1_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER1CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER1, ///< Trigger on TIMER1_CC2. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER1CC3) ldmaPeripheralSignal_TIMER1_CC3 = LDMA_CH_REQSEL_SIGSEL_TIMER1CC3 | LDMA_CH_REQSEL_SOURCESEL_TIMER1, ///< Trigger on TIMER1_CC3. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER1UFOF) ldmaPeripheralSignal_TIMER1_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER1UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER1, ///< Trigger on TIMER1_UFOF. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER2CC0) ldmaPeripheralSignal_TIMER2_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER2CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER2, ///< Trigger on TIMER2_CC0. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER2CC1) ldmaPeripheralSignal_TIMER2_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER2CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER2, ///< Trigger on TIMER2_CC1. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER2CC2) ldmaPeripheralSignal_TIMER2_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER2CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER2, ///< Trigger on TIMER2_CC2. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER2UFOF) ldmaPeripheralSignal_TIMER2_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER2UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER2, ///< Trigger on TIMER2_UFOF. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER3CC0) ldmaPeripheralSignal_TIMER3_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER3CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER3, ///< Trigger on TIMER3_CC0. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER3CC1) ldmaPeripheralSignal_TIMER3_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER3CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER3, ///< Trigger on TIMER3_CC1. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER3CC2) ldmaPeripheralSignal_TIMER3_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER3CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER3, ///< Trigger on TIMER3_CC2. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER3UFOF) ldmaPeripheralSignal_TIMER3_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER3UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER3, ///< Trigger on TIMER3_UFOF. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER4CC0) ldmaPeripheralSignal_TIMER4_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER4CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER4, ///< Trigger on TIMER4_CC0. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER4CC1) ldmaPeripheralSignal_TIMER4_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER4CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER4, ///< Trigger on TIMER4_CC1. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER4CC2) ldmaPeripheralSignal_TIMER4_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER4CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER4, ///< Trigger on TIMER4_CC2. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER4UFOF) ldmaPeripheralSignal_TIMER4_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER4UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER4, ///< Trigger on TIMER4_UFOF. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER5CC0) ldmaPeripheralSignal_TIMER5_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER5CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER5, ///< Trigger on TIMER5_CC0. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER5CC1) ldmaPeripheralSignal_TIMER5_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER5CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER5, ///< Trigger on TIMER5_CC1. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER5CC2) ldmaPeripheralSignal_TIMER5_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER5CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER5, ///< Trigger on TIMER5_CC2. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER5UFOF) ldmaPeripheralSignal_TIMER5_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER5UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER5, ///< Trigger on TIMER5_UFOF. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER6CC0) ldmaPeripheralSignal_TIMER6_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER6CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER6, ///< Trigger on TIMER6_CC0. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER6CC1) ldmaPeripheralSignal_TIMER6_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER6CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER6, ///< Trigger on TIMER6_CC1. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER6CC2) ldmaPeripheralSignal_TIMER6_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER6CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER6, ///< Trigger on TIMER6_CC2. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER6UFOF) ldmaPeripheralSignal_TIMER6_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER6UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER6, ///< Trigger on TIMER6_UFOF. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_UART0RXDATAV) ldmaPeripheralSignal_UART0_RXDATAV = LDMA_CH_REQSEL_SIGSEL_UART0RXDATAV | LDMA_CH_REQSEL_SOURCESEL_UART0, ///< Trigger on UART0_RXDATAV. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_UART0TXBL) ldmaPeripheralSignal_UART0_TXBL = LDMA_CH_REQSEL_SIGSEL_UART0TXBL | LDMA_CH_REQSEL_SOURCESEL_UART0, ///< Trigger on UART0_TXBL. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_UART0TXEMPTY) ldmaPeripheralSignal_UART0_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_UART0TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_UART0, ///< Trigger on UART0_TXEMPTY. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_UART1RXDATAV) ldmaPeripheralSignal_UART1_RXDATAV = LDMA_CH_REQSEL_SIGSEL_UART1RXDATAV | LDMA_CH_REQSEL_SOURCESEL_UART1, ///< Trigger on UART1_RXDATAV. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_UART1TXBL) ldmaPeripheralSignal_UART1_TXBL = LDMA_CH_REQSEL_SIGSEL_UART1TXBL | LDMA_CH_REQSEL_SOURCESEL_UART1, ///< Trigger on UART1_TXBL. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_UART1TXEMPTY) ldmaPeripheralSignal_UART1_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_UART1TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_UART1, ///< Trigger on UART1_TXEMPTY. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_USART0RXDATAV) ldmaPeripheralSignal_USART0_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART0RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART0, ///< Trigger on USART0_RXDATAV. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_USART0TXBL) ldmaPeripheralSignal_USART0_TXBL = LDMA_CH_REQSEL_SIGSEL_USART0TXBL | LDMA_CH_REQSEL_SOURCESEL_USART0, ///< Trigger on USART0_TXBL. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_USART0TXEMPTY) ldmaPeripheralSignal_USART0_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART0TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART0, ///< Trigger on USART0_TXEMPTY. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_USART1RXDATAV) ldmaPeripheralSignal_USART1_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART1RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART1, ///< Trigger on USART1_RXDATAV. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT) ldmaPeripheralSignal_USART1_RXDATAVRIGHT = LDMA_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART1, ///< Trigger on USART1_RXDATAVRIGHT. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_USART1TXBL) ldmaPeripheralSignal_USART1_TXBL = LDMA_CH_REQSEL_SIGSEL_USART1TXBL | LDMA_CH_REQSEL_SOURCESEL_USART1, ///< Trigger on USART1_TXBL. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_USART1TXBLRIGHT) ldmaPeripheralSignal_USART1_TXBLRIGHT = LDMA_CH_REQSEL_SIGSEL_USART1TXBLRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART1, ///< Trigger on USART1_TXBLRIGHT. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_USART1TXEMPTY) ldmaPeripheralSignal_USART1_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART1TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART1, ///< Trigger on USART1_TXEMPTY. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_USART2RXDATAV) ldmaPeripheralSignal_USART2_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART2RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART2, ///< Trigger on USART2_RXDATAV. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_USART2TXBL) ldmaPeripheralSignal_USART2_TXBL = LDMA_CH_REQSEL_SIGSEL_USART2TXBL | LDMA_CH_REQSEL_SOURCESEL_USART2, ///< Trigger on USART2_TXBL. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_USART2TXEMPTY) ldmaPeripheralSignal_USART2_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART2TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART2, ///< Trigger on USART2_TXEMPTY. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_USART3RXDATAV) ldmaPeripheralSignal_USART3_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART3RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART3, ///< Trigger on USART3_RXDATAV. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_USART3RXDATAVRIGHT) ldmaPeripheralSignal_USART3_RXDATAVRIGHT = LDMA_CH_REQSEL_SIGSEL_USART3RXDATAVRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART3, ///< Trigger on USART3_RXDATAVRIGHT. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_USART3TXBL) ldmaPeripheralSignal_USART3_TXBL = LDMA_CH_REQSEL_SIGSEL_USART3TXBL | LDMA_CH_REQSEL_SOURCESEL_USART3, ///< Trigger on USART3_TXBL. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_USART3TXBLRIGHT) ldmaPeripheralSignal_USART3_TXBLRIGHT = LDMA_CH_REQSEL_SIGSEL_USART3TXBLRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART3, ///< Trigger on USART3_TXBLRIGHT. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_USART3TXEMPTY) ldmaPeripheralSignal_USART3_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART3TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART3, ///< Trigger on USART3_TXEMPTY. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_USART4RXDATAV) ldmaPeripheralSignal_USART4_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART4RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART4, ///< Trigger on USART4_RXDATAV. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_USART4RXDATAVRIGHT) ldmaPeripheralSignal_USART4_RXDATAVRIGHT = LDMA_CH_REQSEL_SIGSEL_USART4RXDATAVRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART4, ///< Trigger on USART4_RXDATAVRIGHT. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_USART4TXBL) ldmaPeripheralSignal_USART4_TXBL = LDMA_CH_REQSEL_SIGSEL_USART4TXBL | LDMA_CH_REQSEL_SOURCESEL_USART4, ///< Trigger on USART4_TXBL. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_USART4TXBLRIGHT) ldmaPeripheralSignal_USART4_TXBLRIGHT = LDMA_CH_REQSEL_SIGSEL_USART4TXBLRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART4, ///< Trigger on USART4_TXBLRIGHT. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_USART4TXEMPTY) ldmaPeripheralSignal_USART4_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART4TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART4, ///< Trigger on USART4_TXEMPTY. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_USART5RXDATAV) ldmaPeripheralSignal_USART5_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART5RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART5, ///< Trigger on USART5_RXDATAV. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_USART5TXBL) ldmaPeripheralSignal_USART5_TXBL = LDMA_CH_REQSEL_SIGSEL_USART5TXBL | LDMA_CH_REQSEL_SOURCESEL_USART5, ///< Trigger on USART5_TXBL. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_USART5TXEMPTY) ldmaPeripheralSignal_USART5_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART5TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART5, ///< Trigger on USART5_TXEMPTY. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_VDAC0CH0) ldmaPeripheralSignal_VDAC0_CH0 = LDMA_CH_REQSEL_SIGSEL_VDAC0CH0 | LDMA_CH_REQSEL_SOURCESEL_VDAC0, ///< Trigger on VDAC0_CH0. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_VDAC0CH1) ldmaPeripheralSignal_VDAC0_CH1 = LDMA_CH_REQSEL_SIGSEL_VDAC0CH1 | LDMA_CH_REQSEL_SOURCESEL_VDAC0, ///< Trigger on VDAC0_CH1. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER0CC0) ldmaPeripheralSignal_WTIMER0_CC0 = LDMA_CH_REQSEL_SIGSEL_WTIMER0CC0 | LDMA_CH_REQSEL_SOURCESEL_WTIMER0, ///< Trigger on WTIMER0_CC0. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER0CC1) ldmaPeripheralSignal_WTIMER0_CC1 = LDMA_CH_REQSEL_SIGSEL_WTIMER0CC1 | LDMA_CH_REQSEL_SOURCESEL_WTIMER0, ///< Trigger on WTIMER0_CC1. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER0CC2) ldmaPeripheralSignal_WTIMER0_CC2 = LDMA_CH_REQSEL_SIGSEL_WTIMER0CC2 | LDMA_CH_REQSEL_SOURCESEL_WTIMER0, ///< Trigger on WTIMER0_CC2. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER0UFOF) ldmaPeripheralSignal_WTIMER0_UFOF = LDMA_CH_REQSEL_SIGSEL_WTIMER0UFOF | LDMA_CH_REQSEL_SOURCESEL_WTIMER0, ///< Trigger on WTIMER0_UFOF. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER1CC0) ldmaPeripheralSignal_WTIMER1_CC0 = LDMA_CH_REQSEL_SIGSEL_WTIMER1CC0 | LDMA_CH_REQSEL_SOURCESEL_WTIMER1, ///< Trigger on WTIMER1_CC0. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER1CC1) ldmaPeripheralSignal_WTIMER1_CC1 = LDMA_CH_REQSEL_SIGSEL_WTIMER1CC1 | LDMA_CH_REQSEL_SOURCESEL_WTIMER1, ///< Trigger on WTIMER1_CC1. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER1CC2) ldmaPeripheralSignal_WTIMER1_CC2 = LDMA_CH_REQSEL_SIGSEL_WTIMER1CC2 | LDMA_CH_REQSEL_SOURCESEL_WTIMER1, ///< Trigger on WTIMER1_CC2. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER1CC3) ldmaPeripheralSignal_WTIMER1_CC3 = LDMA_CH_REQSEL_SIGSEL_WTIMER1CC3 | LDMA_CH_REQSEL_SOURCESEL_WTIMER1, ///< Trigger on WTIMER1_CC3. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER1UFOF) ldmaPeripheralSignal_WTIMER1_UFOF = LDMA_CH_REQSEL_SIGSEL_WTIMER1UFOF | LDMA_CH_REQSEL_SOURCESEL_WTIMER1, ///< Trigger on WTIMER1_UFOF. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER2CC0) ldmaPeripheralSignal_WTIMER2_CC0 = LDMA_CH_REQSEL_SIGSEL_WTIMER2CC0 | LDMA_CH_REQSEL_SOURCESEL_WTIMER2, ///< Trigger on WTIMER2_CC0. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER2CC1) ldmaPeripheralSignal_WTIMER2_CC1 = LDMA_CH_REQSEL_SIGSEL_WTIMER2CC1 | LDMA_CH_REQSEL_SOURCESEL_WTIMER2, ///< Trigger on WTIMER2_CC1. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER2CC2) ldmaPeripheralSignal_WTIMER2_CC2 = LDMA_CH_REQSEL_SIGSEL_WTIMER2CC2 | LDMA_CH_REQSEL_SOURCESEL_WTIMER2, ///< Trigger on WTIMER2_CC2. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER2UFOF) ldmaPeripheralSignal_WTIMER2_UFOF = LDMA_CH_REQSEL_SIGSEL_WTIMER2UFOF | LDMA_CH_REQSEL_SOURCESEL_WTIMER2, ///< Trigger on WTIMER2_UFOF. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER3CC0) ldmaPeripheralSignal_WTIMER3_CC0 = LDMA_CH_REQSEL_SIGSEL_WTIMER3CC0 | LDMA_CH_REQSEL_SOURCESEL_WTIMER3, ///< Trigger on WTIMER3_CC0. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER3CC1) ldmaPeripheralSignal_WTIMER3_CC1 = LDMA_CH_REQSEL_SIGSEL_WTIMER3CC1 | LDMA_CH_REQSEL_SOURCESEL_WTIMER3, ///< Trigger on WTIMER3_CC1. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER3CC2) ldmaPeripheralSignal_WTIMER3_CC2 = LDMA_CH_REQSEL_SIGSEL_WTIMER3CC2 | LDMA_CH_REQSEL_SOURCESEL_WTIMER3, ///< Trigger on WTIMER3_CC2. #endif #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER3UFOF) ldmaPeripheralSignal_WTIMER3_UFOF = LDMA_CH_REQSEL_SIGSEL_WTIMER3UFOF | LDMA_CH_REQSEL_SOURCESEL_WTIMER3, ///< Trigger on WTIMER3_UFOF. #endif } LDMA_PeripheralSignal_t; #endif /******************************************************************************* ******************************* STRUCTS *********************************** ******************************************************************************/ /** * @brief * DMA descriptor. * @details * The LDMA DMA controller supports three different DMA descriptors. Each * consists of four WORDs which map directly onto HW control registers for a * given DMA channel. The three descriptor types are XFER, SYNC and WRI. * Refer to the reference manual for further information. */ typedef union { /** * TRANSFER DMA descriptor, this is the only descriptor type which can be * used to start a DMA transfer. */ struct { uint32_t structType : 2; /**< Set to 0 to select XFER descriptor type. */ uint32_t reserved0 : 1; uint32_t structReq : 1; /**< DMA transfer trigger during LINKLOAD. */ uint32_t xferCnt : 11; /**< Transfer count minus one. */ uint32_t byteSwap : 1; /**< Enable byte swapping transfers. */ uint32_t blockSize : 4; /**< Number of unit transfers per arbitration cycle. */ uint32_t doneIfs : 1; /**< Generate interrupt when done. */ uint32_t reqMode : 1; /**< Block or cycle transfer selector. */ uint32_t decLoopCnt : 1; /**< Enable looped transfers. */ uint32_t ignoreSrec : 1; /**< Ignore single requests. */ uint32_t srcInc : 2; /**< Source address increment unit size. */ uint32_t size : 2; /**< DMA transfer unit size. */ uint32_t dstInc : 2; /**< Destination address increment unit size. */ uint32_t srcAddrMode : 1; /**< Source addressing mode. */ uint32_t dstAddrMode : 1; /**< Destination addressing mode. */ uint32_t srcAddr; /**< DMA source address. */ uint32_t dstAddr; /**< DMA destination address. */ uint32_t linkMode : 1; /**< Select absolute or relative link address. */ uint32_t link : 1; /**< Enable LINKLOAD when transfer is done. */ int32_t linkAddr : 30; /**< Address of next (linked) descriptor. */ } xfer; /** SYNCHRONIZE DMA descriptor, used for intra channel transfer * synchronization. */ struct { uint32_t structType : 2; /**< Set to 1 to select SYNC descriptor type. */ uint32_t reserved0 : 1; uint32_t structReq : 1; /**< DMA transfer trigger during LINKLOAD. */ uint32_t xferCnt : 11; /**< Transfer count minus one. */ uint32_t byteSwap : 1; /**< Enable byte swapping transfers. */ uint32_t blockSize : 4; /**< Number of unit transfers per arbitration cycle. */ uint32_t doneIfs : 1; /**< Generate interrupt when done. */ uint32_t reqMode : 1; /**< Block or cycle transfer selector. */ uint32_t decLoopCnt : 1; /**< Enable looped transfers. */ uint32_t ignoreSrec : 1; /**< Ignore single requests. */ uint32_t srcInc : 2; /**< Source address increment unit size. */ uint32_t size : 2; /**< DMA transfer unit size. */ uint32_t dstInc : 2; /**< Destination address increment unit size. */ uint32_t srcAddrMode : 1; /**< Source addressing mode. */ uint32_t dstAddrMode : 1; /**< Destination addressing mode. */ uint32_t syncSet : 8; /**< Set bits in LDMA_CTRL.SYNCTRIG register. */ uint32_t syncClr : 8; /**< Clear bits in LDMA_CTRL.SYNCTRIG register. */ uint32_t reserved3 : 16; uint32_t matchVal : 8; /**< Sync trigger match value. */ uint32_t matchEn : 8; /**< Sync trigger match enable. */ uint32_t reserved4 : 16; uint32_t linkMode : 1; /**< Select absolute or relative link address. */ uint32_t link : 1; /**< Enable LINKLOAD when transfer is done. */ int32_t linkAddr : 30; /**< Address of next (linked) descriptor. */ } sync; /** WRITE DMA descriptor, used for write immediate operations. */ struct { uint32_t structType : 2; /**< Set to 2 to select WRITE descriptor type. */ uint32_t reserved0 : 1; uint32_t structReq : 1; /**< DMA transfer trigger during LINKLOAD. */ uint32_t xferCnt : 11; /**< Transfer count minus one. */ uint32_t byteSwap : 1; /**< Enable byte swapping transfers. */ uint32_t blockSize : 4; /**< Number of unit transfers per arbitration cycle. */ uint32_t doneIfs : 1; /**< Generate interrupt when done. */ uint32_t reqMode : 1; /**< Block or cycle transfer selector. */ uint32_t decLoopCnt : 1; /**< Enable looped transfers. */ uint32_t ignoreSrec : 1; /**< Ignore single requests. */ uint32_t srcInc : 2; /**< Source address increment unit size. */ uint32_t size : 2; /**< DMA transfer unit size. */ uint32_t dstInc : 2; /**< Destination address increment unit size. */ uint32_t srcAddrMode : 1; /**< Source addressing mode. */ uint32_t dstAddrMode : 1; /**< Destination addressing mode. */ uint32_t immVal; /**< Data to be written at dstAddr. */ uint32_t dstAddr; /**< DMA write destination address. */ uint32_t linkMode : 1; /**< Select absolute or relative link address. */ uint32_t link : 1; /**< Enable LINKLOAD when transfer is done. */ int32_t linkAddr : 30; /**< Address of next (linked) descriptor. */ } wri; } LDMA_Descriptor_t; /** @brief LDMA initialization configuration structure. */ typedef struct { uint8_t ldmaInitCtrlNumFixed; /**< Arbitration mode separator. */ uint8_t ldmaInitCtrlSyncPrsClrEn; /**< PRS Synctrig clear enable. */ uint8_t ldmaInitCtrlSyncPrsSetEn; /**< PRS Synctrig set enable. */ uint8_t ldmaInitIrqPriority; /**< LDMA IRQ priority (0..7). */ } LDMA_Init_t; /** * @brief * DMA transfer configuration structure. * @details * This struct configures all aspects of a DMA transfer. */ typedef struct { uint32_t ldmaReqSel; /**< Selects DMA trigger source. */ uint8_t ldmaCtrlSyncPrsClrOff; /**< PRS Synctrig clear enables to clear. */ uint8_t ldmaCtrlSyncPrsClrOn; /**< PRS Synctrig clear enables to set. */ uint8_t ldmaCtrlSyncPrsSetOff; /**< PRS Synctrig set enables to clear. */ uint8_t ldmaCtrlSyncPrsSetOn; /**< PRS Synctrig set enables to set. */ bool ldmaReqDis; /**< Mask the PRS trigger input. */ bool ldmaDbgHalt; /**< Dis. DMA trig when CPU is halted. */ uint8_t ldmaCfgArbSlots; /**< Arbitration slot number. */ uint8_t ldmaCfgSrcIncSign; /**< Source address increment sign. */ uint8_t ldmaCfgDstIncSign; /**< Destination address increment sign. */ uint8_t ldmaLoopCnt; /**< Counter for looped transfers. */ } LDMA_TransferCfg_t; /******************************************************************************* ************************** STRUCT INITIALIZERS **************************** ******************************************************************************/ /** @brief Default DMA initialization structure. */ #define LDMA_INIT_DEFAULT \ { \ .ldmaInitCtrlNumFixed = _LDMA_CTRL_NUMFIXED_DEFAULT,/* Fixed priority arbitration.*/ \ .ldmaInitCtrlSyncPrsClrEn = 0, /* No PRS Synctrig clear enable*/ \ .ldmaInitCtrlSyncPrsSetEn = 0, /* No PRS Synctrig set enable. */ \ .ldmaInitIrqPriority = 3 /* IRQ priority level 3. */ \ } /** * @brief * Generic DMA transfer configuration for memory to memory transfers. */ #define LDMA_TRANSFER_CFG_MEMORY() \ { \ 0, 0, 0, 0, 0, \ false, false, ldmaCfgArbSlotsAs1, \ ldmaCfgSrcIncSignPos, ldmaCfgDstIncSignPos, 0 \ } /** * @brief * Generic DMA transfer configuration for looped memory to memory transfers. */ #define LDMA_TRANSFER_CFG_MEMORY_LOOP(loopCnt) \ { \ 0, 0, 0, 0, 0, \ false, false, ldmaCfgArbSlotsAs1, \ ldmaCfgSrcIncSignPos, ldmaCfgDstIncSignPos, \ loopCnt \ } /** * @brief * Generic DMA transfer configuration for memory to/from peripheral transfers. */ #define LDMA_TRANSFER_CFG_PERIPHERAL(signal) \ { \ signal, 0, 0, 0, 0, \ false, false, ldmaCfgArbSlotsAs1, \ ldmaCfgSrcIncSignPos, ldmaCfgDstIncSignPos, 0 \ } /** * @brief * Generic DMA transfer configuration for looped memory to/from peripheral transfers. */ #define LDMA_TRANSFER_CFG_PERIPHERAL_LOOP(signal, loopCnt) \ { \ signal, 0, 0, 0, 0, \ false, false, ldmaCfgArbSlotsAs1, \ ldmaCfgSrcIncSignPos, ldmaCfgDstIncSignPos, loopCnt \ } /** * @brief * DMA descriptor initializer for single memory to memory word transfer. * @param[in] src Source data address. * @param[in] dest Destination data address. * @param[in] count Number of words to transfer. */ #define LDMA_DESCRIPTOR_SINGLE_M2M_WORD(src, dest, count) \ { \ .xfer = \ { \ .structType = ldmaCtrlStructTypeXfer, \ .structReq = 1, \ .xferCnt = (count) - 1, \ .byteSwap = 0, \ .blockSize = ldmaCtrlBlockSizeUnit1, \ .doneIfs = 1, \ .reqMode = ldmaCtrlReqModeAll, \ .decLoopCnt = 0, \ .ignoreSrec = 0, \ .srcInc = ldmaCtrlSrcIncOne, \ .size = ldmaCtrlSizeWord, \ .dstInc = ldmaCtrlDstIncOne, \ .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ .srcAddr = (uint32_t)(src), \ .dstAddr = (uint32_t)(dest), \ .linkMode = 0, \ .link = 0, \ .linkAddr = 0 \ } \ } /** * @brief * DMA descriptor initializer for single memory to memory half-word transfer. * @param[in] src Source data address. * @param[in] dest Destination data address. * @param[in] count Number of half-words to transfer. */ #define LDMA_DESCRIPTOR_SINGLE_M2M_HALF(src, dest, count) \ { \ .xfer = \ { \ .structType = ldmaCtrlStructTypeXfer, \ .structReq = 1, \ .xferCnt = (count) - 1, \ .byteSwap = 0, \ .blockSize = ldmaCtrlBlockSizeUnit1, \ .doneIfs = 1, \ .reqMode = ldmaCtrlReqModeAll, \ .decLoopCnt = 0, \ .ignoreSrec = 0, \ .srcInc = ldmaCtrlSrcIncOne, \ .size = ldmaCtrlSizeHalf, \ .dstInc = ldmaCtrlDstIncOne, \ .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ .srcAddr = (uint32_t)(src), \ .dstAddr = (uint32_t)(dest), \ .linkMode = 0, \ .link = 0, \ .linkAddr = 0 \ } \ } /** * @brief * DMA descriptor initializer for single memory to memory byte transfer. * @param[in] src Source data address. * @param[in] dest Destination data address. * @param[in] count Number of bytes to transfer. */ #define LDMA_DESCRIPTOR_SINGLE_M2M_BYTE(src, dest, count) \ { \ .xfer = \ { \ .structType = ldmaCtrlStructTypeXfer, \ .structReq = 1, \ .xferCnt = (count) - 1, \ .byteSwap = 0, \ .blockSize = ldmaCtrlBlockSizeUnit1, \ .doneIfs = 1, \ .reqMode = ldmaCtrlReqModeAll, \ .decLoopCnt = 0, \ .ignoreSrec = 0, \ .srcInc = ldmaCtrlSrcIncOne, \ .size = ldmaCtrlSizeByte, \ .dstInc = ldmaCtrlDstIncOne, \ .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ .srcAddr = (uint32_t)(src), \ .dstAddr = (uint32_t)(dest), \ .linkMode = 0, \ .link = 0, \ .linkAddr = 0 \ } \ } /** * @brief * DMA descriptor initializer for linked memory to memory word transfer. * * Link address must be an absolute address. * @note * The linkAddr member of the transfer descriptor is not * initialized. * @param[in] src Source data address. * @param[in] dest Destination data address. * @param[in] count Number of words to transfer. */ #define LDMA_DESCRIPTOR_LINKABS_M2M_WORD(src, dest, count) \ { \ .xfer = \ { \ .structType = ldmaCtrlStructTypeXfer, \ .structReq = 1, \ .xferCnt = (count) - 1, \ .byteSwap = 0, \ .blockSize = ldmaCtrlBlockSizeUnit1, \ .doneIfs = 0, \ .reqMode = ldmaCtrlReqModeAll, \ .decLoopCnt = 0, \ .ignoreSrec = 0, \ .srcInc = ldmaCtrlSrcIncOne, \ .size = ldmaCtrlSizeWord, \ .dstInc = ldmaCtrlDstIncOne, \ .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ .srcAddr = (uint32_t)(src), \ .dstAddr = (uint32_t)(dest), \ .linkMode = ldmaLinkModeAbs, \ .link = 1, \ .linkAddr = 0 /* Must be set runtime ! */ \ } \ } /** * @brief * DMA descriptor initializer for linked memory to memory half-word transfer. * * Link address must be an absolute address. * @note * The linkAddr member of the transfer descriptor is not * initialized. * @param[in] src Source data address. * @param[in] dest Destination data address. * @param[in] count Number of half-words to transfer. */ #define LDMA_DESCRIPTOR_LINKABS_M2M_HALF(src, dest, count) \ { \ .xfer = \ { \ .structType = ldmaCtrlStructTypeXfer, \ .structReq = 1, \ .xferCnt = (count) - 1, \ .byteSwap = 0, \ .blockSize = ldmaCtrlBlockSizeUnit1, \ .doneIfs = 0, \ .reqMode = ldmaCtrlReqModeAll, \ .decLoopCnt = 0, \ .ignoreSrec = 0, \ .srcInc = ldmaCtrlSrcIncOne, \ .size = ldmaCtrlSizeHalf, \ .dstInc = ldmaCtrlDstIncOne, \ .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ .srcAddr = (uint32_t)(src), \ .dstAddr = (uint32_t)(dest), \ .linkMode = ldmaLinkModeAbs, \ .link = 1, \ .linkAddr = 0 /* Must be set runtime ! */ \ } \ } /** * @brief * DMA descriptor initializer for linked memory to memory byte transfer. * * Link address must be an absolute address. * @note * The linkAddr member of the transfer descriptor is not * initialized. * @param[in] src Source data address. * @param[in] dest Destination data address. * @param[in] count Number of bytes to transfer. */ #define LDMA_DESCRIPTOR_LINKABS_M2M_BYTE(src, dest, count) \ { \ .xfer = \ { \ .structType = ldmaCtrlStructTypeXfer, \ .structReq = 1, \ .xferCnt = (count) - 1, \ .byteSwap = 0, \ .blockSize = ldmaCtrlBlockSizeUnit1, \ .doneIfs = 0, \ .reqMode = ldmaCtrlReqModeAll, \ .decLoopCnt = 0, \ .ignoreSrec = 0, \ .srcInc = ldmaCtrlSrcIncOne, \ .size = ldmaCtrlSizeByte, \ .dstInc = ldmaCtrlDstIncOne, \ .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ .srcAddr = (uint32_t)(src), \ .dstAddr = (uint32_t)(dest), \ .linkMode = ldmaLinkModeAbs, \ .link = 1, \ .linkAddr = 0 /* Must be set runtime ! */ \ } \ } /** * @brief * DMA descriptor initializer for linked memory to memory word transfer. * * Link address is a relative address. * @note * The linkAddr member of the transfer descriptor is initialized to 4, * assuming that the next descriptor immediately follows * this descriptor (in memory). * @param[in] src Source data address. * @param[in] dest Destination data address. * @param[in] count Number of words to transfer. * @param[in] linkjmp Address of descriptor to link to, expressed as a * signed number of descriptors from "here". * 1=one descriptor forward in memory, * 0=this descriptor, * -1=one descriptor back in memory. */ #define LDMA_DESCRIPTOR_LINKREL_M2M_WORD(src, dest, count, linkjmp) \ { \ .xfer = \ { \ .structType = ldmaCtrlStructTypeXfer, \ .structReq = 1, \ .xferCnt = (count) - 1, \ .byteSwap = 0, \ .blockSize = ldmaCtrlBlockSizeUnit1, \ .doneIfs = 0, \ .reqMode = ldmaCtrlReqModeAll, \ .decLoopCnt = 0, \ .ignoreSrec = 0, \ .srcInc = ldmaCtrlSrcIncOne, \ .size = ldmaCtrlSizeWord, \ .dstInc = ldmaCtrlDstIncOne, \ .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ .srcAddr = (uint32_t)(src), \ .dstAddr = (uint32_t)(dest), \ .linkMode = ldmaLinkModeRel, \ .link = 1, \ .linkAddr = (linkjmp) * 4 \ } \ } /** * @brief * DMA descriptor initializer for linked memory to memory half-word transfer. * * Link address is a relative address. * @note * The linkAddr member of transfer descriptor is initialized to 4, * assuming that the next descriptor immediately follows * this descriptor (in memory). * @param[in] src Source data address. * @param[in] dest Destination data address. * @param[in] count Number of half-words to transfer. * @param[in] linkjmp Address of descriptor to link to, expressed as a * signed number of descriptors from "here". * 1=one descriptor forward in memory, * 0=this descriptor, * -1=one descriptor back in memory. */ #define LDMA_DESCRIPTOR_LINKREL_M2M_HALF(src, dest, count, linkjmp) \ { \ .xfer = \ { \ .structType = ldmaCtrlStructTypeXfer, \ .structReq = 1, \ .xferCnt = (count) - 1, \ .byteSwap = 0, \ .blockSize = ldmaCtrlBlockSizeUnit1, \ .doneIfs = 0, \ .reqMode = ldmaCtrlReqModeAll, \ .decLoopCnt = 0, \ .ignoreSrec = 0, \ .srcInc = ldmaCtrlSrcIncOne, \ .size = ldmaCtrlSizeHalf, \ .dstInc = ldmaCtrlDstIncOne, \ .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ .srcAddr = (uint32_t)(src), \ .dstAddr = (uint32_t)(dest), \ .linkMode = ldmaLinkModeRel, \ .link = 1, \ .linkAddr = (linkjmp) * 4 \ } \ } /** * @brief * DMA descriptor initializer for linked memory to memory byte transfer. * * Link address is a relative address. * @note * The linkAddr member of transfer descriptor is initialized to 4, * assuming that the next descriptor immediately follows * this descriptor (in memory). * @param[in] src Source data address. * @param[in] dest Destination data address. * @param[in] count Number of bytes to transfer. * @param[in] linkjmp Address of descriptor to link to, expressed as a * signed number of descriptors from "here". * 1=one descriptor forward in memory, * 0=this descriptor, * -1=one descriptor back in memory. */ #define LDMA_DESCRIPTOR_LINKREL_M2M_BYTE(src, dest, count, linkjmp) \ { \ .xfer = \ { \ .structType = ldmaCtrlStructTypeXfer, \ .structReq = 1, \ .xferCnt = (count) - 1, \ .byteSwap = 0, \ .blockSize = ldmaCtrlBlockSizeUnit1, \ .doneIfs = 0, \ .reqMode = ldmaCtrlReqModeAll, \ .decLoopCnt = 0, \ .ignoreSrec = 0, \ .srcInc = ldmaCtrlSrcIncOne, \ .size = ldmaCtrlSizeByte, \ .dstInc = ldmaCtrlDstIncOne, \ .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ .srcAddr = (uint32_t)(src), \ .dstAddr = (uint32_t)(dest), \ .linkMode = ldmaLinkModeRel, \ .link = 1, \ .linkAddr = (linkjmp) * 4 \ } \ } /** * @brief * DMA descriptor initializer for byte transfers from a peripheral to memory. * @param[in] src Peripheral data source register address. * @param[in] dest Destination data address. * @param[in] count Number of bytes to transfer. */ #define LDMA_DESCRIPTOR_SINGLE_P2M_BYTE(src, dest, count) \ { \ .xfer = \ { \ .structType = ldmaCtrlStructTypeXfer, \ .structReq = 0, \ .xferCnt = (count) - 1, \ .byteSwap = 0, \ .blockSize = ldmaCtrlBlockSizeUnit1, \ .doneIfs = 1, \ .reqMode = ldmaCtrlReqModeBlock, \ .decLoopCnt = 0, \ .ignoreSrec = 0, \ .srcInc = ldmaCtrlSrcIncNone, \ .size = ldmaCtrlSizeByte, \ .dstInc = ldmaCtrlDstIncOne, \ .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ .srcAddr = (uint32_t)(src), \ .dstAddr = (uint32_t)(dest), \ .linkMode = 0, \ .link = 0, \ .linkAddr = 0 \ } \ } /** * @brief * DMA descriptor initializer for byte transfers from a peripheral to a peripheral. * @param[in] src Peripheral data source register address. * @param[in] dest Peripheral data destination register address. * @param[in] count Number of bytes to transfer. */ #define LDMA_DESCRIPTOR_SINGLE_P2P_BYTE(src, dest, count) \ { \ .xfer = \ { \ .structType = ldmaCtrlStructTypeXfer, \ .structReq = 0, \ .xferCnt = (count) - 1, \ .byteSwap = 0, \ .blockSize = ldmaCtrlBlockSizeUnit1, \ .doneIfs = 1, \ .reqMode = ldmaCtrlReqModeBlock, \ .decLoopCnt = 0, \ .ignoreSrec = 0, \ .srcInc = ldmaCtrlSrcIncNone, \ .size = ldmaCtrlSizeByte, \ .dstInc = ldmaCtrlDstIncNone, \ .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ .srcAddr = (uint32_t)(src), \ .dstAddr = (uint32_t)(dest), \ .linkMode = 0, \ .link = 0, \ .linkAddr = 0 \ } \ } /** * @brief * DMA descriptor initializer for byte transfers from memory to a peripheral * @param[in] src Source data address. * @param[in] dest Peripheral data register destination address. * @param[in] count Number of bytes to transfer. */ #define LDMA_DESCRIPTOR_SINGLE_M2P_BYTE(src, dest, count) \ { \ .xfer = \ { \ .structType = ldmaCtrlStructTypeXfer, \ .structReq = 0, \ .xferCnt = (count) - 1, \ .byteSwap = 0, \ .blockSize = ldmaCtrlBlockSizeUnit1, \ .doneIfs = 1, \ .reqMode = ldmaCtrlReqModeBlock, \ .decLoopCnt = 0, \ .ignoreSrec = 0, \ .srcInc = ldmaCtrlSrcIncOne, \ .size = ldmaCtrlSizeByte, \ .dstInc = ldmaCtrlDstIncNone, \ .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ .srcAddr = (uint32_t)(src), \ .dstAddr = (uint32_t)(dest), \ .linkMode = 0, \ .link = 0, \ .linkAddr = 0 \ } \ } /** * @brief * DMA descriptor initializer for byte transfers from a peripheral to memory. * @param[in] src Peripheral data source register address. * @param[in] dest Destination data address. * @param[in] count Number of bytes to transfer. * @param[in] linkjmp Address of descriptor to link to, expressed as a * signed number of descriptors from "here". * 1=one descriptor forward in memory, * 0=this descriptor, * -1=one descriptor back in memory. */ #define LDMA_DESCRIPTOR_LINKREL_P2M_BYTE(src, dest, count, linkjmp) \ { \ .xfer = \ { \ .structType = ldmaCtrlStructTypeXfer, \ .structReq = 0, \ .xferCnt = (count) - 1, \ .byteSwap = 0, \ .blockSize = ldmaCtrlBlockSizeUnit1, \ .doneIfs = 1, \ .reqMode = ldmaCtrlReqModeBlock, \ .decLoopCnt = 0, \ .ignoreSrec = 0, \ .srcInc = ldmaCtrlSrcIncNone, \ .size = ldmaCtrlSizeByte, \ .dstInc = ldmaCtrlDstIncOne, \ .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ .srcAddr = (uint32_t)(src), \ .dstAddr = (uint32_t)(dest), \ .linkMode = ldmaLinkModeRel, \ .link = 1, \ .linkAddr = (linkjmp) * 4 \ } \ } /** * @brief * DMA descriptor initializer for word transfers from a peripheral to memory. * @param[in] src Peripheral data source register address. * @param[in] dest Destination data address. * @param[in] count Number of words to transfer. * @param[in] linkjmp Address of descriptor to link to, expressed as a * signed number of descriptors from "here". * 1=one descriptor forward in memory, * 0=this descriptor, * -1=one descriptor back in memory. */ #define LDMA_DESCRIPTOR_LINKREL_P2M_WORD(src, dest, count, linkjmp) \ { \ .xfer = \ { \ .structType = ldmaCtrlStructTypeXfer, \ .structReq = 0, \ .xferCnt = (count) - 1, \ .byteSwap = 0, \ .blockSize = ldmaCtrlBlockSizeUnit1, \ .doneIfs = 1, \ .reqMode = ldmaCtrlReqModeBlock, \ .decLoopCnt = 0, \ .ignoreSrec = 0, \ .srcInc = ldmaCtrlSrcIncNone, \ .size = ldmaCtrlSizeWord, \ .dstInc = ldmaCtrlDstIncOne, \ .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ .srcAddr = (uint32_t)(src), \ .dstAddr = (uint32_t)(dest), \ .linkMode = ldmaLinkModeRel, \ .link = 1, \ .linkAddr = (linkjmp) * 4 \ } \ } /** * @brief * DMA descriptor initializer for byte transfers from memory to a peripheral * @param[in] src Source data address. * @param[in] dest Peripheral data register destination address. * @param[in] count Number of bytes to transfer. * @param[in] linkjmp Address of descriptor to link to, expressed as a * signed number of descriptors from "here". * 1=one descriptor forward in memory, * 0=this descriptor, * -1=one descriptor back in memory. */ #define LDMA_DESCRIPTOR_LINKREL_M2P_BYTE(src, dest, count, linkjmp) \ { \ .xfer = \ { \ .structType = ldmaCtrlStructTypeXfer, \ .structReq = 0, \ .xferCnt = (count) - 1, \ .byteSwap = 0, \ .blockSize = ldmaCtrlBlockSizeUnit1, \ .doneIfs = 1, \ .reqMode = ldmaCtrlReqModeBlock, \ .decLoopCnt = 0, \ .ignoreSrec = 0, \ .srcInc = ldmaCtrlSrcIncOne, \ .size = ldmaCtrlSizeByte, \ .dstInc = ldmaCtrlDstIncNone, \ .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ .srcAddr = (uint32_t)(src), \ .dstAddr = (uint32_t)(dest), \ .linkMode = ldmaLinkModeRel, \ .link = 1, \ .linkAddr = (linkjmp) * 4 \ } \ } /** * @brief * DMA descriptor initializer for Immediate WRITE transfer * @param[in] value Immediate value to write. * @param[in] address Write address. */ #define LDMA_DESCRIPTOR_SINGLE_WRITE(value, address) \ { \ .wri = \ { \ .structType = ldmaCtrlStructTypeWrite, \ .structReq = 1, \ .xferCnt = 0, \ .byteSwap = 0, \ .blockSize = 0, \ .doneIfs = 1, \ .reqMode = 0, \ .decLoopCnt = 0, \ .ignoreSrec = 0, \ .srcInc = 0, \ .size = 0, \ .dstInc = 0, \ .srcAddrMode = 0, \ .dstAddrMode = 0, \ .immVal = (value), \ .dstAddr = (uint32_t)(address), \ .linkMode = 0, \ .link = 0, \ .linkAddr = 0 \ } \ } /** * @brief * DMA descriptor initializer for Immediate WRITE transfer * * Link address must be an absolute address. * @note * The linkAddr member of the transfer descriptor is not * initialized. * @param[in] value Immediate value to write. * @param[in] address Write address. */ #define LDMA_DESCRIPTOR_LINKABS_WRITE(value, address) \ { \ .wri = \ { \ .structType = ldmaCtrlStructTypeWrite, \ .structReq = 1, \ .xferCnt = 0, \ .byteSwap = 0, \ .blockSize = 0, \ .doneIfs = 0, \ .reqMode = 0, \ .decLoopCnt = 0, \ .ignoreSrec = 0, \ .srcInc = 0, \ .size = 0, \ .dstInc = 0, \ .srcAddrMode = 0, \ .dstAddrMode = 0, \ .immVal = (value), \ .dstAddr = (uint32_t)(address), \ .linkMode = ldmaLinkModeAbs, \ .link = 1, \ .linkAddr = 0 /* Must be set runtime ! */ \ } \ } /** * @brief * DMA descriptor initializer for Immediate WRITE transfer * @param[in] value Immediate value to write. * @param[in] address Write address. * @param[in] linkjmp Address of descriptor to link to, expressed as a * signed number of descriptors from "here". * 1=one descriptor forward in memory, * 0=this descriptor, * -1=one descriptor back in memory. */ #define LDMA_DESCRIPTOR_LINKREL_WRITE(value, address, linkjmp) \ { \ .wri = \ { \ .structType = ldmaCtrlStructTypeWrite, \ .structReq = 1, \ .xferCnt = 0, \ .byteSwap = 0, \ .blockSize = 0, \ .doneIfs = 0, \ .reqMode = 0, \ .decLoopCnt = 0, \ .ignoreSrec = 0, \ .srcInc = 0, \ .size = 0, \ .dstInc = 0, \ .srcAddrMode = 0, \ .dstAddrMode = 0, \ .immVal = (value), \ .dstAddr = (uint32_t)(address), \ .linkMode = ldmaLinkModeRel, \ .link = 1, \ .linkAddr = (linkjmp) * 4 \ } \ } /** * @brief * DMA descriptor initializer for SYNC transfer * @param[in] set Sync pattern bits to set. * @param[in] clr Sync pattern bits to clear. * @param[in] matchValue Sync pattern to match. * @param[in] matchEnable Sync pattern bits to enable for match. */ #define LDMA_DESCRIPTOR_SINGLE_SYNC(set, clr, matchValue, matchEnable) \ { \ .sync = \ { \ .structType = ldmaCtrlStructTypeSync, \ .structReq = 1, \ .xferCnt = 0, \ .byteSwap = 0, \ .blockSize = 0, \ .doneIfs = 1, \ .reqMode = 0, \ .decLoopCnt = 0, \ .ignoreSrec = 0, \ .srcInc = 0, \ .size = 0, \ .dstInc = 0, \ .srcAddrMode = 0, \ .dstAddrMode = 0, \ .syncSet = (set), \ .syncClr = (clr), \ .matchVal = (matchValue), \ .matchEn = (matchEnable), \ .linkMode = 0, \ .link = 0, \ .linkAddr = 0 \ } \ } /** * @brief * DMA descriptor initializer for SYNC transfer * * Link address must be an absolute address. * @note * The linkAddr member of the transfer descriptor is not * initialized. * @param[in] set Sync pattern bits to set. * @param[in] clr Sync pattern bits to clear. * @param[in] matchValue Sync pattern to match. * @param[in] matchEnable Sync pattern bits to enable for match. */ #define LDMA_DESCRIPTOR_LINKABS_SYNC(set, clr, matchValue, matchEnable) \ { \ .sync = \ { \ .structType = ldmaCtrlStructTypeSync, \ .structReq = 1, \ .xferCnt = 0, \ .byteSwap = 0, \ .blockSize = 0, \ .doneIfs = 0, \ .reqMode = 0, \ .decLoopCnt = 0, \ .ignoreSrec = 0, \ .srcInc = 0, \ .size = 0, \ .dstInc = 0, \ .srcAddrMode = 0, \ .dstAddrMode = 0, \ .syncSet = (set), \ .syncClr = (clr), \ .matchVal = (matchValue), \ .matchEn = (matchEnable), \ .linkMode = ldmaLinkModeAbs, \ .link = 1, \ .linkAddr = 0 /* Must be set runtime ! */ \ } \ } /** * @brief * DMA descriptor initializer for SYNC transfer * @param[in] set Sync pattern bits to set. * @param[in] clr Sync pattern bits to clear. * @param[in] matchValue Sync pattern to match. * @param[in] matchEnable Sync pattern bits to enable for match. * @param[in] linkjmp Address of descriptor to link to, expressed as a * signed number of descriptors from "here". * 1=one descriptor forward in memory, * 0=this descriptor, * -1=one descriptor back in memory. */ #define LDMA_DESCRIPTOR_LINKREL_SYNC(set, clr, matchValue, matchEnable, linkjmp) \ { \ .sync = \ { \ .structType = ldmaCtrlStructTypeSync, \ .structReq = 1, \ .xferCnt = 0, \ .byteSwap = 0, \ .blockSize = 0, \ .doneIfs = 0, \ .reqMode = 0, \ .decLoopCnt = 0, \ .ignoreSrec = 0, \ .srcInc = 0, \ .size = 0, \ .dstInc = 0, \ .srcAddrMode = 0, \ .dstAddrMode = 0, \ .syncSet = (set), \ .syncClr = (clr), \ .matchVal = (matchValue), \ .matchEn = (matchEnable), \ .linkMode = ldmaLinkModeRel, \ .link = 1, \ .linkAddr = (linkjmp) * 4 \ } \ } /******************************************************************************* ***************************** PROTOTYPES ********************************** ******************************************************************************/ void LDMA_DeInit(void); void LDMA_EnableChannelRequest(int ch, bool enable); void LDMA_Init(const LDMA_Init_t *init); void LDMA_StartTransfer(int ch, const LDMA_TransferCfg_t *transfer, const LDMA_Descriptor_t *descriptor); void LDMA_StopTransfer(int ch); bool LDMA_TransferDone(int ch); uint32_t LDMA_TransferRemainingCount(int ch); /***************************************************************************//** * @brief * Check if a certain channel is enabled. * * @param[in] ch * LDMA channel to check. * * @return * return true if the LDMA channel is enabled and false if the channel is not * enabled. ******************************************************************************/ __STATIC_INLINE bool LDMA_ChannelEnabled(int ch) { if ((ch < 0) || (ch > 31)) { return false; } #if defined(_LDMA_CHSTATUS_MASK) return LDMA->CHSTATUS & (1 << ch); #else // We've already confirmed ch is between 0 and 31, // so it's now safe to cast it to uint8_t return LDMA->CHEN & (1 << (uint8_t)ch); #endif } /***************************************************************************//** * @brief * Clear one or more pending LDMA interrupts. * * @param[in] flags * Pending LDMA interrupt sources to clear. Use one or more valid * interrupt flags for the LDMA module. The flags are @ref LDMA_IFC_ERROR * and one done flag for each channel. ******************************************************************************/ __STATIC_INLINE void LDMA_IntClear(uint32_t flags) { #if defined (LDMA_HAS_SET_CLEAR) LDMA->IF_CLR = flags; #else LDMA->IFC = flags; #endif } /***************************************************************************//** * @brief * Disable one or more LDMA interrupts. * * @param[in] flags * LDMA interrupt sources to disable. Use one or more valid * interrupt flags for LDMA module. The flags are @ref LDMA_IEN_ERROR * and one done flag for each channel. ******************************************************************************/ __STATIC_INLINE void LDMA_IntDisable(uint32_t flags) { LDMA->IEN &= ~flags; } /***************************************************************************//** * @brief * Enable one or more LDMA interrupts. * * @note * Depending on the use, a pending interrupt may already be set prior to * enabling the interrupt. To ignore a pending interrupt, consider using * LDMA_IntClear() prior to enabling the interrupt. * * @param[in] flags * LDMA interrupt sources to enable. Use one or more valid * interrupt flags for LDMA module. The flags are @ref LDMA_IEN_ERROR * and one done flag for each channel. ******************************************************************************/ __STATIC_INLINE void LDMA_IntEnable(uint32_t flags) { LDMA->IEN |= flags; } /***************************************************************************//** * @brief * Get pending LDMA interrupt flags. * * @note * Event bits are not cleared by the use of this function. * * @return * LDMA interrupt sources pending. Returns one or more valid * interrupt flags for LDMA module. The flags are @ref LDMA_IF_ERROR and * one flag for each LDMA channel. ******************************************************************************/ __STATIC_INLINE uint32_t LDMA_IntGet(void) { return LDMA->IF; } /***************************************************************************//** * @brief * Get enabled and pending LDMA interrupt flags. * Useful for handling more interrupt sources in the same interrupt handler. * * @note * Interrupt flags are not cleared by the use of this function. * * @return * Pending and enabled LDMA interrupt sources * Return value is the bitwise AND of * - the enabled interrupt sources in LDMA_IEN and * - the pending interrupt flags LDMA_IF ******************************************************************************/ __STATIC_INLINE uint32_t LDMA_IntGetEnabled(void) { uint32_t ien; ien = LDMA->IEN; return LDMA->IF & ien; } /***************************************************************************//** * @brief * Set one or more pending LDMA interrupts * * @param[in] flags * LDMA interrupt sources to set to pending. Use one or more valid * interrupt flags for LDMA module. The flags are @ref LDMA_IFS_ERROR and * one done flag for each LDMA channel. ******************************************************************************/ __STATIC_INLINE void LDMA_IntSet(uint32_t flags) { #if defined (LDMA_HAS_SET_CLEAR) LDMA->IF_SET = flags; #else LDMA->IFS = flags; #endif } /** @} (end addtogroup LDMA) */ /** @} (end addtogroup emlib) */ #ifdef __cplusplus } #endif #endif /* defined( LDMA_PRESENT ) && ( LDMA_COUNT == 1 ) */ #endif /* EM_LDMA_H */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/emlib/inc/em_letimer.h.
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/***************************************************************************//** * @file * @brief Low Energy Timer (LETIMER) peripheral API * @version 5.7.0 ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * SPDX-License-Identifier: Zlib * * The licensor of this software is Silicon Laboratories Inc. * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be * appreciated but is not required. * 2. Altered source versions must be plainly marked as such, and must not be * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * ******************************************************************************/ #ifndef EM_LETIMER_H #define EM_LETIMER_H #include <stdbool.h> #include "em_device.h" #if defined(LETIMER_COUNT) && (LETIMER_COUNT > 0) #ifdef __cplusplus extern "C" { #endif /***************************************************************************//** * @addtogroup emlib * @{ ******************************************************************************/ /***************************************************************************//** * @addtogroup LETIMER * @{ ******************************************************************************/ /******************************************************************************* ******************************** ENUMS ************************************ ******************************************************************************/ /** Repeat mode. */ typedef enum { /** Count until stopped by SW. */ letimerRepeatFree = _LETIMER_CTRL_REPMODE_FREE, /** Count REP0 times. */ letimerRepeatOneshot = _LETIMER_CTRL_REPMODE_ONESHOT, /** * Count REP0 times, if REP1 has been written to, it is loaded into * REP0 when REP0 is about to be decremented to 0. */ letimerRepeatBuffered = _LETIMER_CTRL_REPMODE_BUFFERED, /** * Run as long as both REP0 and REP1 are not 0. Both REP0 and REP1 * are decremented when counter underflows. */ letimerRepeatDouble = _LETIMER_CTRL_REPMODE_DOUBLE } LETIMER_RepeatMode_TypeDef; /** Underflow action on output. */ typedef enum { /** No output action. */ letimerUFOANone = _LETIMER_CTRL_UFOA0_NONE, /** Toggle output when counter underflows. */ letimerUFOAToggle = _LETIMER_CTRL_UFOA0_TOGGLE, /** Hold output one LETIMER clock cycle when counter underflows. */ letimerUFOAPulse = _LETIMER_CTRL_UFOA0_PULSE, /** Set output idle when counter underflows, and active when matching COMP1. */ letimerUFOAPwm = _LETIMER_CTRL_UFOA0_PWM } LETIMER_UFOA_TypeDef; /******************************************************************************* ******************************* STRUCTS *********************************** ******************************************************************************/ /** LETIMER initialization structure. */ typedef struct { bool enable; /**< Start counting when initialization completes. */ bool debugRun; /**< Counter shall keep running during debug halt. */ #if defined(LETIMER_CTRL_RTCC0TEN) bool rtcComp0Enable; /**< Start counting on RTC COMP0 match. */ bool rtcComp1Enable; /**< Start counting on RTC COMP1 match. */ #endif bool comp0Top; /**< Load COMP0 register into CNT when counter underflows. */ bool bufTop; /**< Load COMP1 into COMP0 when REP0 reaches 0. */ uint8_t out0Pol; /**< Idle value for output 0. */ uint8_t out1Pol; /**< Idle value for output 1. */ LETIMER_UFOA_TypeDef ufoa0; /**< Underflow output 0 action. */ LETIMER_UFOA_TypeDef ufoa1; /**< Underflow output 1 action. */ LETIMER_RepeatMode_TypeDef repMode; /**< Repeat mode. */ uint32_t topValue; /**< Top value. Counter wraps when top value matches counter value is reached. */ } LETIMER_Init_TypeDef; /** Default configuration for LETIMER initialization structure. */ #if defined(LETIMER_CTRL_RTCC0TEN) #define LETIMER_INIT_DEFAULT \ { \ true, /* Enable timer when initialization completes. */ \ false, /* Stop counter during debug halt. */ \ false, /* Do not start counting on RTC COMP0 match. */ \ false, /* Do not start counting on RTC COMP1 match. */ \ false, /* Do not load COMP0 into CNT on underflow. */ \ false, /* Do not load COMP1 into COMP0 when REP0 reaches 0. */ \ 0, /* Idle value 0 for output 0. */ \ 0, /* Idle value 0 for output 1. */ \ letimerUFOANone, /* No action on underflow on output 0. */ \ letimerUFOANone, /* No action on underflow on output 1. */ \ letimerRepeatFree, /* Count until stopped by SW. */ \ 0 /* Use default top Value. */ \ } #else #define LETIMER_INIT_DEFAULT \ { \ true, /* Enable timer when initialization completes. */ \ false, /* Stop counter during debug halt. */ \ false, /* Do not load COMP0 into CNT on underflow. */ \ false, /* Do not load COMP1 into COMP0 when REP0 reaches 0. */ \ 0, /* Idle value 0 for output 0. */ \ 0, /* Idle value 0 for output 1. */ \ letimerUFOANone, /* No action on underflow on output 0. */ \ letimerUFOANone, /* No action on underflow on output 1. */ \ letimerRepeatFree, /* Count until stopped by SW. */ \ 0 /* Use default top Value. */ \ } #endif /******************************************************************************* ***************************** PROTOTYPES ********************************** ******************************************************************************/ uint32_t LETIMER_CompareGet(LETIMER_TypeDef *letimer, unsigned int comp); void LETIMER_CompareSet(LETIMER_TypeDef *letimer, unsigned int comp, uint32_t value); /***************************************************************************//** * @brief * Get LETIMER counter value. * * @param[in] letimer * Pointer to the LETIMER peripheral register block. * * @return * Current LETIMER counter value. ******************************************************************************/ __STATIC_INLINE uint32_t LETIMER_CounterGet(LETIMER_TypeDef *letimer) { return(letimer->CNT); } void LETIMER_Enable(LETIMER_TypeDef *letimer, bool enable); #if defined(_LETIMER_FREEZE_MASK) void LETIMER_FreezeEnable(LETIMER_TypeDef *letimer, bool enable); #endif void LETIMER_Init(LETIMER_TypeDef *letimer, const LETIMER_Init_TypeDef *init); /***************************************************************************//** * @brief * Clear one or more pending LETIMER interrupts. * * @param[in] letimer * Pointer to LETIMER peripheral register block. * * @param[in] flags * Pending LETIMER interrupt source to clear. Use a bitwise logic OR * combination of valid interrupt flags for the LETIMER module * (LETIMER_IF_nnn). ******************************************************************************/ __STATIC_INLINE void LETIMER_IntClear(LETIMER_TypeDef *letimer, uint32_t flags) { #if defined (LETIMER_HAS_SET_CLEAR) letimer->IF_CLR = flags; #else letimer->IFC = flags; #endif } /***************************************************************************//** * @brief * Disable one or more LETIMER interrupts. * * @param[in] letimer * Pointer to LETIMER peripheral register block. * * @param[in] flags * LETIMER interrupt sources to disable. Use a bitwise logic OR combination of * valid interrupt flags for the LETIMER module (LETIMER_IF_nnn). ******************************************************************************/ __STATIC_INLINE void LETIMER_IntDisable(LETIMER_TypeDef *letimer, uint32_t flags) { letimer->IEN &= ~flags; } /***************************************************************************//** * @brief * Enable one or more LETIMER interrupts. * * @note * Depending on the use, a pending interrupt may already be set prior to * enabling the interrupt. To ignore a pending interrupt, consider using * LETIMER_IntClear() prior to enabling the interrupt. * * @param[in] letimer * Pointer to the LETIMER peripheral register block. * * @param[in] flags * LETIMER interrupt sources to enable. Use a bitwise logic OR combination of * valid interrupt flags for the LETIMER module (LETIMER_IF_nnn). ******************************************************************************/ __STATIC_INLINE void LETIMER_IntEnable(LETIMER_TypeDef *letimer, uint32_t flags) { letimer->IEN |= flags; } /***************************************************************************//** * @brief * Get pending LETIMER interrupt flags. * * @note * Event bits are not cleared by the use of this function. * * @param[in] letimer * Pointer to LETIMER peripheral register block. * * @return * LETIMER interrupt sources pending. A bitwise logic OR combination of * valid interrupt flags for the LETIMER module (LETIMER_IF_nnn). ******************************************************************************/ __STATIC_INLINE uint32_t LETIMER_IntGet(LETIMER_TypeDef *letimer) { return letimer->IF; } /***************************************************************************//** * @brief * Get enabled and pending LETIMER interrupt flags. * * @details * Useful for handling more interrupt sources in the same interrupt handler. * * @note * Event bits are not cleared by the use of this function. * * @param[in] letimer * Pointer to LETIMER peripheral register block. * * @return * Pending and enabled LETIMER interrupt sources. * Return value is the bitwise AND combination of * - the OR combination of enabled interrupt sources in LETIMER_IEN_nnn * register (LETIMER_IEN_nnn) and * - the OR combination of valid interrupt flags of the LETIMER module * (LETIMER_IF_nnn). ******************************************************************************/ __STATIC_INLINE uint32_t LETIMER_IntGetEnabled(LETIMER_TypeDef *letimer) { uint32_t ien; /* Store flags in temporary variable in order to define explicit order * of volatile accesses. */ ien = letimer->IEN; /* Bitwise AND of pending and enabled interrupts */ return letimer->IF & ien; } /***************************************************************************//** * @brief * Set one or more pending LETIMER interrupts from SW. * * @param[in] letimer * Pointer to LETIMER peripheral register block. * * @param[in] flags * LETIMER interrupt sources to set to pending. Use a bitwise logic OR * combination of valid interrupt flags for the LETIMER module (LETIMER_IF_nnn). ******************************************************************************/ __STATIC_INLINE void LETIMER_IntSet(LETIMER_TypeDef *letimer, uint32_t flags) { #if defined (LETIMER_HAS_SET_CLEAR) letimer->IF_SET = flags; #else letimer->IFS = flags; #endif } uint32_t LETIMER_RepeatGet(LETIMER_TypeDef *letimer, unsigned int rep); void LETIMER_RepeatSet(LETIMER_TypeDef *letimer, unsigned int rep, uint32_t value); void LETIMER_Reset(LETIMER_TypeDef *letimer); void LETIMER_SyncWait(LETIMER_TypeDef *letimer); void LETIMER_TopSet(LETIMER_TypeDef *letimer, uint32_t value); /***************************************************************************//** * @brief * Get the current LETIMER top value. * * @param[in] letimer * A pointer to the LETIMER peripheral register block. * * @return * The top value. This will be a 16 bit value on series-0 and series-1 * devices and a 24 bit value on series-2 devices. ******************************************************************************/ __STATIC_INLINE uint32_t LETIMER_TopGet(LETIMER_TypeDef *letimer) { #if defined(_LETIMER_TOP_MASK) return letimer->TOP; #else return letimer->COMP0; #endif } /** @} (end addtogroup LETIMER) */ /** @} (end addtogroup emlib) */ #ifdef __cplusplus } #endif #endif /* defined(LETIMER_COUNT) && (LETIMER_COUNT > 0) */ #endif /* EM_LETIMER_H */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/emlib/inc/em_msc.h.
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/***************************************************************************//** * @file * @brief Flash Controller (MSC) Peripheral API * @version 5.7.0 ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * SPDX-License-Identifier: Zlib * * The licensor of this software is Silicon Laboratories Inc. * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be * appreciated but is not required. * 2. Altered source versions must be plainly marked as such, and must not be * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * ******************************************************************************/ #ifndef EM_MSC_H #define EM_MSC_H #include "em_device.h" #if defined(MSC_COUNT) && (MSC_COUNT > 0) #include <stdint.h> #include <stdbool.h> #include "em_bus.h" #include "em_ramfunc.h" #ifdef __cplusplus extern "C" { #endif /***************************************************************************//** * @addtogroup emlib * @{ ******************************************************************************/ /***************************************************************************//** * @addtogroup MSC * @brief Memory System Controller API. * @details * Contains functions to control the MSC, primarily the Flash. * Users can perform Flash memory write and erase operations, as well as * optimization of the CPU instruction fetch interface for the application. * Available instruction fetch features depends on the MCU or SoC family, but * features such as instruction pre-fetch, cache, and configurable branch prediction * are typically available. * * @note Flash wait-state configuration is handled by @ref CMU module. * When core clock configuration is changed by a call to functions such as * @ref CMU_ClockSelectSet() or @ref CMU_HFRCOBandSet(), then Flash wait-state * configuration is also updated. * * MSC resets into a safe state. To initialize the instruction interface * to recommended settings: * @include em_msc_init_exec.c * * @note The optimal configuration is highly application dependent. Performance * benchmarking is supported by most families. See @ref MSC_StartCacheMeasurement() * and @ref MSC_GetCacheMeasurement() for more details. * * Support for Flash write and erase runs from RAM by default. This code may be * allocated to Flash by defining @ref EM_MSC_RUN_FROM_FLASH. * * @note * Flash erase may add ms of delay to interrupt latency if executing from Flash. * * Flash write and erase operations are supported by @ref MSC_WriteWord(), * @ref MSC_WriteWordFast(), @ref MSC_ErasePage(), and @ref MSC_MassErase(). * Fast write is not supported for EFM32G and mass erase is supported for MCU and * SoC families with larger Flash sizes. * * @note * @ref MSC_Init() must be called prior to any Flash write or erase operation. * * The following steps are necessary to perform a page erase and write: * @include em_msc_erase_write.c * @{ ******************************************************************************/ /******************************************************************************* ************************* DEFINES ***************************************** ******************************************************************************/ /** * @brief * Timeout used while waiting for Flash to become ready after a write. * This number indicates the number of iterations to perform before * issuing a timeout. * * @note * Timeout is set very large (in the order of 100x longer than * necessary). This is to avoid any corner case. */ #define MSC_PROGRAM_TIMEOUT 10000000ul /** * @brief * By compiling with define EM_MSC_RUN_FROM_FLASH, functions * performing erase or write operations will remain in and execute from Flash. * This is useful for targets that don't want to allocate RAM space to * hold the flash functions. Without this define, code for Flash operations * will be copied into RAM at startup. * * @note * This define is not present by default. The MSC controller API * will run from RAM by default. */ #if defined(DOXY_DOC_ONLY) #define EM_MSC_RUN_FROM_FLASH #endif /******************************************************************************* ************************* TYPEDEFS **************************************** ******************************************************************************/ /** Return codes for writing/erasing Flash. */ typedef enum { mscReturnOk = 0, /**< Flash write/erase successful. */ mscReturnInvalidAddr = -1, /**< Invalid address. Write to an address that is not Flash. */ mscReturnLocked = -2, /**< Flash address is locked. */ mscReturnTimeOut = -3, /**< Timeout while writing to Flash. */ mscReturnUnaligned = -4 /**< Unaligned access to Flash. */ } MSC_Status_TypeDef; #if defined(_MSC_READCTRL_BUSSTRATEGY_MASK) /** Strategy for prioritized bus access. */ typedef enum { mscBusStrategyCPU = MSC_READCTRL_BUSSTRATEGY_CPU, /**< Prioritize CPU bus accesses. */ mscBusStrategyDMA = MSC_READCTRL_BUSSTRATEGY_DMA, /**< Prioritize DMA bus accesses. */ mscBusStrategyDMAEM1 = MSC_READCTRL_BUSSTRATEGY_DMAEM1, /**< Prioritize DMAEM1 for bus accesses. */ mscBusStrategyNone = MSC_READCTRL_BUSSTRATEGY_NONE /**< No unit has bus priority. */ } MSC_BusStrategy_Typedef; #endif #if defined(MSC_READCTRL_DOUTBUFEN) /** Code execution configuration */ typedef struct { bool doutBufEn; /**< Flash dout pipeline buffer enable */ } MSC_ExecConfig_TypeDef; /** Default MSC ExecConfig initialization */ #define MSC_EXECCONFIG_DEFAULT \ { \ false, \ } #else /** Code execution configuration. */ typedef struct { bool scbtEn; /**< Enable Suppressed Conditional Branch Target Prefetch. */ bool prefetchEn; /**< Enable MSC prefetching. */ bool ifcDis; /**< Disable instruction cache. */ bool aiDis; /**< Disable automatic cache invalidation on write or erase. */ bool iccDis; /**< Disable automatic caching of fetches in interrupt context. */ bool useHprot; /**< Use ahb_hprot to determine if the instruction is cacheable or not. */ } MSC_ExecConfig_TypeDef; /** Default MSC ExecConfig initialization. */ #define MSC_EXECCONFIG_DEFAULT \ { \ false, \ true, \ false, \ false, \ false, \ false, \ } #endif #if defined(_MSC_ECCCTRL_MASK) || defined(_SYSCFG_DMEM0ECCCTRL_MASK) #if defined(_SILICON_LABS_32B_SERIES_1_CONFIG_1) /** EFM32GG11B incorporates 2 memory banks including ECC support. */ #define MSC_ECC_BANKS (2) /** Default MSC EccConfig initialization. */ #define MSC_ECCCONFIG_DEFAULT \ { \ { false, false }, \ { 0, 1 }, \ } #elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_106) /** EFM32GG12B incorporates 3 memory banks including ECC support. */ #define MSC_ECC_BANKS (3) /** Default MSC EccConfig initialization. */ #define MSC_ECCCONFIG_DEFAULT \ { \ { false, false, false }, \ { 0, 1 }, \ } #elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) /** EFR32XG21 incorporates 1 memory bank including ECC support. */ #define MSC_ECC_BANKS (1) /** Default MSC EccConfig initialization */ #define MSC_ECCCONFIG_DEFAULT \ { \ { false }, \ { 0, 1 }, \ } #else #error Device not supported. #endif /** ECC configuration. */ typedef struct { bool enableEccBank[MSC_ECC_BANKS]; /**< Array of bools to enable/disable Error Correcting Code (ECC) for each RAM bank that supports ECC on the device. */ uint32_t dmaChannels[2]; /**< Array of 2 DMA channel numbers to use for ECC initialization. */ } MSC_EccConfig_TypeDef; #endif /* #if defined(_MSC_ECCCTRL_MASK) */ /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ /* Deprecated type names. */ #define mscBusStrategy_Typedef MSC_BusStrategy_Typedef #define msc_Return_TypeDef MSC_Status_TypeDef /** @endcond */ /***************************************************************************//** * @brief * Clear one or more pending MSC interrupts. * * @param[in] flags * Pending MSC intterupt source to clear. Use a bitwise logic OR combination * of valid interrupt flags for the MSC module (MSC_IF_nnn). ******************************************************************************/ __STATIC_INLINE void MSC_IntClear(uint32_t flags) { #if defined(MSC_HAS_SET_CLEAR) MSC->IF_CLR = flags; #else MSC->IFC = flags; #endif } /***************************************************************************//** * @brief * Disable one or more MSC interrupts. * * @param[in] flags * MSC interrupt sources to disable. Use a bitwise logic OR combination of * valid interrupt flags for the MSC module (MSC_IF_nnn). ******************************************************************************/ __STATIC_INLINE void MSC_IntDisable(uint32_t flags) { #if defined(MSC_HAS_SET_CLEAR) MSC->IEN_CLR = flags; #else MSC->IEN &= ~(flags); #endif } /***************************************************************************//** * @brief * Enable one or more MSC interrupts. * * @note * Depending on the use, a pending interrupt may already be set prior to * enabling the interrupt. To ignore a pending interrupt, consider using * MSC_IntClear() prior to enabling the interrupt. * * @param[in] flags * MSC interrupt sources to enable. Use a bitwise logic OR combination of * valid interrupt flags for the MSC module (MSC_IF_nnn). ******************************************************************************/ __STATIC_INLINE void MSC_IntEnable(uint32_t flags) { #if defined(MSC_HAS_SET_CLEAR) MSC->IEN_SET = flags; #else MSC->IEN |= flags; #endif } /***************************************************************************//** * @brief * Get pending MSC interrupt flags. * * @note * The event bits are not cleared by the use of this function. * * @return * MSC interrupt sources pending. A bitwise logic OR combination of valid * interrupt flags for the MSC module (MSC_IF_nnn). ******************************************************************************/ __STATIC_INLINE uint32_t MSC_IntGet(void) { return MSC->IF; } /***************************************************************************//** * @brief * Get enabled and pending MSC interrupt flags. * Useful for handling more interrupt sources in the same interrupt handler. * * @note * Interrupt flags are not cleared by the use of this function. * * @return * Pending and enabled MSC interrupt sources. * The return value is the bitwise AND of * - the enabled interrupt sources in MSC_IEN and * - the pending interrupt flags MSC_IF ******************************************************************************/ __STATIC_INLINE uint32_t MSC_IntGetEnabled(void) { uint32_t ien; ien = MSC->IEN; return MSC->IF & ien; } /***************************************************************************//** * @brief * Set one or more pending MSC interrupts from SW. * * @param[in] flags * MSC interrupt sources to set to pending. Use a bitwise logic OR combination of * valid interrupt flags for the MSC module (MSC_IF_nnn). ******************************************************************************/ __STATIC_INLINE void MSC_IntSet(uint32_t flags) { #if defined(MSC_HAS_SET_CLEAR) MSC->IF_SET = flags; #else MSC->IFS = flags; #endif } #if defined(MSC_IF_CHOF) && defined(MSC_IF_CMOF) /***************************************************************************//** * @brief * Starts measuring cache hit ratio. * @details * Starts performance counters. It is defined inline to * minimize the impact of this code on the measurement itself. ******************************************************************************/ __STATIC_INLINE void MSC_StartCacheMeasurement(void) { /* Clear CMOF and CHOF to catch these later. */ MSC->IFC = MSC_IF_CHOF | MSC_IF_CMOF; /* Start performance counters. */ #if defined(_MSC_CACHECMD_MASK) MSC->CACHECMD = MSC_CACHECMD_STARTPC; #else MSC->CMD = MSC_CMD_STARTPC; #endif } /***************************************************************************//** * @brief * Stops measuring hit rate. * @note * Defined inline to minimize the impact of this * code on the measurement itself. * Only works for relatively short sections of code. * To measure longer sections of code, implement an IRQ Handler for * the CHOF and CMOF overflow interrupts. These overflows need to be * counted and included in the total. * Functions can then be implemented as follows: * @verbatim * volatile uint32_t hitOverflows * volatile uint32_t missOverflows * * void MSC_IRQHandler(void) * { * uint32_t flags; * flags = MSC->IF; * if (flags & MSC_IF_CHOF) { * MSC->IFC = MSC_IF_CHOF; * hitOverflows++; * } * if (flags & MSC_IF_CMOF) { * MSC->IFC = MSC_IF_CMOF; * missOverflows++; * } * } * * void startPerformanceCounters(void) * { * hitOverflows = 0; * missOverflows = 0; * * MSC_IntEnable(MSC_IF_CHOF | MSC_IF_CMOF); * NVIC_EnableIRQ(MSC_IRQn); * * MSC_StartCacheMeasurement(); * } * @endverbatim * @return * Returns -1 if there has been no cache accesses. * Returns -2 if there has been an overflow in the performance counters. * If not, it will return the percentage of hits versus misses. ******************************************************************************/ __STATIC_INLINE int32_t MSC_GetCacheMeasurement(void) { int32_t total; int32_t hits; /* Stop counter before computing hit-rate. */ #if defined(_MSC_CACHECMD_MASK) MSC->CACHECMD = MSC_CACHECMD_STOPPC; #else MSC->CMD = MSC_CMD_STOPPC; #endif /* Check for overflows in performance counters. */ if (MSC->IF & (MSC_IF_CHOF | MSC_IF_CMOF)) { return -2; } hits = MSC->CACHEHITS; total = MSC->CACHEMISSES + hits; /* To avoid a division by zero. */ if (total == 0) { return -1; } return (hits * 100) / total; } /***************************************************************************//** * @brief * Flush contents of instruction cache. ******************************************************************************/ __STATIC_INLINE void MSC_FlushCache(void) { #if defined(_MSC_CACHECMD_MASK) MSC->CACHECMD = MSC_CACHECMD_INVCACHE; #else MSC->CMD = MSC_CMD_INVCACHE; #endif } /***************************************************************************//** * @brief * Enable or disable instruction cache functionality. * @param[in] enable * Enable instruction cache. Default is on. ******************************************************************************/ __STATIC_INLINE void MSC_EnableCache(bool enable) { BUS_RegBitWrite(&(MSC->READCTRL), _MSC_READCTRL_IFCDIS_SHIFT, !enable); } #if defined(MSC_READCTRL_ICCDIS) /***************************************************************************//** * @brief * Enable or disable instruction cache functionality in IRQs. * @param[in] enable * Enable instruction cache. Default is on. ******************************************************************************/ __STATIC_INLINE void MSC_EnableCacheIRQs(bool enable) { BUS_RegBitWrite(&(MSC->READCTRL), _MSC_READCTRL_ICCDIS_SHIFT, !enable); } #endif /***************************************************************************//** * @brief * Enable or disable instruction cache flushing when writing to flash. * @param[in] enable * Enable automatic cache flushing. Default is on. ******************************************************************************/ __STATIC_INLINE void MSC_EnableAutoCacheFlush(bool enable) { BUS_RegBitWrite(&(MSC->READCTRL), _MSC_READCTRL_AIDIS_SHIFT, !enable); } #endif /* defined( MSC_IF_CHOF ) && defined( MSC_IF_CMOF ) */ #if defined(_MSC_READCTRL_BUSSTRATEGY_MASK) /***************************************************************************//** * @brief * Configure which unit should get priority on system bus. * @param[in] mode * Unit to prioritize bus accesses for. ******************************************************************************/ __STATIC_INLINE void MSC_BusStrategy(mscBusStrategy_Typedef mode) { MSC->READCTRL = (MSC->READCTRL & ~(_MSC_READCTRL_BUSSTRATEGY_MASK)) | mode; } #endif /******************************************************************************* ************************* PROTOTYPES ************************************** ******************************************************************************/ void MSC_Init(void); void MSC_Deinit(void); void MSC_ExecConfigSet(MSC_ExecConfig_TypeDef *execConfig); #if defined(_MSC_ECCCTRL_MASK) || defined(_SYSCFG_DMEM0ECCCTRL_MASK) void MSC_EccConfigSet(MSC_EccConfig_TypeDef *eccConfig); #endif #if defined(EM_MSC_RUN_FROM_FLASH) /** @brief Expands to @ref SL_RAMFUNC_DECLARATOR if @ref EM_MSC_RUN_FROM_FLASH is undefined and to nothing if @ref EM_MSC_RUN_FROM_FLASH is defined. */ #define MSC_RAMFUNC_DECLARATOR /** @brief Expands to @ref SL_RAMFUNC_DEFINITION_BEGIN if @ref EM_MSC_RUN_FROM_FLASH is undefined and to nothing if @ref EM_MSC_RUN_FROM_FLASH is defined. */ #define MSC_RAMFUNC_DEFINITION_BEGIN /** @brief Expands to @ref SL_RAMFUNC_DEFINITION_END if @ref EM_MSC_RUN_FROM_FLASH is undefined and to nothing if @ref EM_MSC_RUN_FROM_FLASH is defined. */ #define MSC_RAMFUNC_DEFINITION_END #else #define MSC_RAMFUNC_DECLARATOR SL_RAMFUNC_DECLARATOR #define MSC_RAMFUNC_DEFINITION_BEGIN SL_RAMFUNC_DEFINITION_BEGIN #define MSC_RAMFUNC_DEFINITION_END SL_RAMFUNC_DEFINITION_END #endif MSC_RAMFUNC_DECLARATOR MSC_Status_TypeDef MSC_WriteWord(uint32_t *address, void const *data, uint32_t numBytes); #if !defined(_EFM32_GECKO_FAMILY) && !defined(_SILICON_LABS_32B_SERIES_2) #if !defined (EM_MSC_RUN_FROM_FLASH) || (_SILICON_LABS_GECKO_INTERNAL_SDID < 84) MSC_RAMFUNC_DECLARATOR MSC_Status_TypeDef MSC_WriteWordFast(uint32_t *address, void const *data, uint32_t numBytes); #endif #endif MSC_RAMFUNC_DECLARATOR MSC_Status_TypeDef MSC_ErasePage(uint32_t *startAddress); #if defined(_MSC_MASSLOCK_MASK) MSC_RAMFUNC_DECLARATOR MSC_Status_TypeDef MSC_MassErase(void); #endif /** @} (end addtogroup MSC) */ /** @} (end addtogroup emlib) */ #ifdef __cplusplus } #endif #endif /* defined(MSC_COUNT) && (MSC_COUNT > 0) */ #endif /* EM_MSC_H */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/emlib/inc/em_prs.h.
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/***************************************************************************//** * @file * @brief Peripheral Reflex System (PRS) peripheral API * @version 5.7.0 ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * SPDX-License-Identifier: Zlib * * The licensor of this software is Silicon Laboratories Inc. * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be * appreciated but is not required. * 2. Altered source versions must be plainly marked as such, and must not be * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * ******************************************************************************/ #ifndef EM_PRS_H #define EM_PRS_H #include "em_device.h" #include "em_gpio.h" #include <stdbool.h> #include <stddef.h> #if defined(PRS_COUNT) && (PRS_COUNT > 0) #ifdef __cplusplus extern "C" { #endif /***************************************************************************//** * @addtogroup emlib * @{ ******************************************************************************/ /***************************************************************************//** * @addtogroup PRS * @{ ******************************************************************************/ /******************************************************************************* ******************************* DEFINES *********************************** ******************************************************************************/ #if defined(_SILICON_LABS_32B_SERIES_2) #define PRS_SYNC_CHAN_COUNT PRS_SYNC_CH_NUM #define PRS_ASYNC_CHAN_COUNT PRS_ASYNC_CH_NUM #elif defined(_EFM32_GECKO_FAMILY) #define PRS_SYNC_CHAN_COUNT PRS_CHAN_COUNT #define PRS_ASYNC_CHAN_COUNT 0 #else #define PRS_SYNC_CHAN_COUNT PRS_CHAN_COUNT #define PRS_ASYNC_CHAN_COUNT PRS_CHAN_COUNT #endif #if !defined(_EFM32_GECKO_FAMILY) #define PRS_ASYNC_SUPPORTED 1 #endif /* Some devices have renamed signals so we map some of these signals to common names. */ #if defined(PRS_USART0_RXDATAV) #define PRS_USART0_RXDATA PRS_USART0_RXDATAV #endif #if defined(PRS_USART1_RXDATAV) #define PRS_USART1_RXDATA PRS_USART1_RXDATAV #endif #if defined(PRS_USART2_RXDATAV) #define PRS_USART2_RXDATA PRS_USART2_RXDATAV #endif #if defined(PRS_BURTC_OVERFLOW) #define PRS_BURTC_OF PRS_BURTC_OVERFLOW #endif #if defined(PRS_BURTC_COMP0) #define PRS_BURTC_COMP PRS_BURTC_COMP0 #endif /******************************************************************************* ******************************** ENUMS ************************************ ******************************************************************************/ /** PRS Channel type. */ typedef enum { prsTypeAsync, /**< Asynchronous channel type. */ prsTypeSync /**< Synchronous channel type.*/ } PRS_ChType_t; /** Edge detection type. */ typedef enum { prsEdgeOff, /**< Leave signal as is. */ prsEdgePos, /**< Generate pulses on positive edge. */ prsEdgeNeg, /**< Generate pulses on negative edge. */ prsEdgeBoth /**< Generate pulses on both edges. */ } PRS_Edge_TypeDef; #if defined(_PRS_ASYNC_CH_CTRL_FNSEL_MASK) /** Logic functions that can be used when combining two PRS channels. */ typedef enum { prsLogic_Zero = _PRS_ASYNC_CH_CTRL_FNSEL_LOGICAL_ZERO, prsLogic_A_NOR_B = _PRS_ASYNC_CH_CTRL_FNSEL_A_NOR_B, prsLogic_NOT_A_AND_B = _PRS_ASYNC_CH_CTRL_FNSEL_NOT_A_AND_B, prsLogic_NOT_A = _PRS_ASYNC_CH_CTRL_FNSEL_NOT_A, prsLogic_A_AND_NOT_B = _PRS_ASYNC_CH_CTRL_FNSEL_A_AND_NOT_B, prsLogic_NOT_B = _PRS_ASYNC_CH_CTRL_FNSEL_NOT_B, prsLogic_A_XOR_B = _PRS_ASYNC_CH_CTRL_FNSEL_A_XOR_B, prsLogic_A_NAND_B = _PRS_ASYNC_CH_CTRL_FNSEL_A_NAND_B, prsLogic_A_AND_B = _PRS_ASYNC_CH_CTRL_FNSEL_A_AND_B, prsLogic_A_XNOR_B = _PRS_ASYNC_CH_CTRL_FNSEL_A_XNOR_B, prsLogic_B = _PRS_ASYNC_CH_CTRL_FNSEL_B, prsLogic_A_OR_NOT_B = _PRS_ASYNC_CH_CTRL_FNSEL_A_OR_NOT_B, prsLogic_A = _PRS_ASYNC_CH_CTRL_FNSEL_A, prsLogic_NOT_A_OR_B = _PRS_ASYNC_CH_CTRL_FNSEL_NOT_A_OR_B, prsLogic_A_OR_B = _PRS_ASYNC_CH_CTRL_FNSEL_A_OR_B, prsLogic_One = _PRS_ASYNC_CH_CTRL_FNSEL_LOGICAL_ONE, } PRS_Logic_t; #endif /** PRS Signal. */ typedef enum { prsSignalNone = 0x0, /* Timer Signals */ #if defined(TIMER0) prsSignalTIMER0_UF = PRS_TIMER0_UF, /**< TIMER0 underflow Signal. */ prsSignalTIMER0_OF = PRS_TIMER0_OF, /**< TIMER0 overflow Signal. */ prsSignalTIMER0_CC0 = PRS_TIMER0_CC0, /**< TIMER0 capture/compare channel 0 Signal. */ prsSignalTIMER0_CC1 = PRS_TIMER0_CC1, /**< TIMER0 capture/compare channel 1 Signal. */ prsSignalTIMER0_CC2 = PRS_TIMER0_CC2, /**< TIMER0 capture/compare channel 2 Signal. */ #endif #if defined(TIMER1) prsSignalTIMER1_UF = PRS_TIMER1_UF, /**< TIMER1 underflow Signal. */ prsSignalTIMER1_OF = PRS_TIMER1_OF, /**< TIMER1 overflow Signal. */ prsSignalTIMER1_CC0 = PRS_TIMER1_CC0, /**< TIMER1 capture/compare channel 0 Signal. */ prsSignalTIMER1_CC1 = PRS_TIMER1_CC1, /**< TIMER1 capture/compare channel 1 Signal. */ prsSignalTIMER1_CC2 = PRS_TIMER1_CC2, /**< TIMER1 capture/compare channel 2 Signal. */ #endif #if defined(TIMER2) prsSignalTIMER2_UF = PRS_TIMER2_UF, /**< TIMER2 underflow Signal. */ prsSignalTIMER2_OF = PRS_TIMER2_OF, /**< TIMER2 overflow Signal. */ prsSignalTIMER2_CC0 = PRS_TIMER2_CC0, /**< TIMER2 capture/compare channel 0 Signal. */ prsSignalTIMER2_CC1 = PRS_TIMER2_CC1, /**< TIMER2 capture/compare channel 1 Signal. */ prsSignalTIMER2_CC2 = PRS_TIMER2_CC2, /**< TIMER2 capture/compare channel 2 Signal. */ #endif #if defined(TIMER3) prsSignalTIMER3_UF = PRS_TIMER3_UF, /**< TIMER3 underflow Signal. */ prsSignalTIMER3_OF = PRS_TIMER3_OF, /**< TIMER3 overflow Signal. */ prsSignalTIMER3_CC0 = PRS_TIMER3_CC0, /**< TIMER3 capture/compare channel 0 Signal. */ prsSignalTIMER3_CC1 = PRS_TIMER3_CC1, /**< TIMER3 capture/compare channel 1 Signal. */ prsSignalTIMER3_CC2 = PRS_TIMER3_CC2, /**< TIMER3 capture/compare channel 2 Signal. */ #endif #if defined(PRS_LETIMER0_CH0) prsSignalLETIMER0_CH0 = PRS_LETIMER0_CH0, /**< LETIMER0 channel 0 Signal. */ prsSignalLETIMER0_CH1 = PRS_LETIMER0_CH1, /**< LETIMER0 channel 1 Signal. */ #endif /* RTC/RTCC/BURTC Signals */ #if defined(RTCC) prsSignalRTCC_CCV0 = PRS_RTCC_CCV0, /**< RTCC capture/compare channel 0 Signal. */ prsSignalRTCC_CCV1 = PRS_RTCC_CCV1, /**< RTCC capture/compare channel 1 Signal. */ prsSignalRTCC_CCV2 = PRS_RTCC_CCV2, /**< RTCC capture/compare channel 2 Signal. */ #endif #if defined(BURTC) prsSignalBURTC_COMP = PRS_BURTC_COMP, /**< BURTC compare Signal. */ prsSignalBURTC_OF = PRS_BURTC_OF, /**< BURTC overflow Signal. */ #endif /* ACMP Signals */ #if defined(ACMP0) prsSignalACMP0_OUT = PRS_ACMP0_OUT, /**< ACMP0 Signal. */ #endif #if defined(ACMP1) prsSignalACMP1_OUT = PRS_ACMP1_OUT, /**< ACMP1 output Signal. */ #endif /* USART Signals */ #if defined(USART0) prsSignalUSART0_IRTX = PRS_USART0_IRTX, /**< USART0 IR tx Signal. */ prsSignalUSART0_TXC = PRS_USART0_TXC, /**< USART0 tx complete Signal. */ prsSignalUSART0_RXDATA = PRS_USART0_RXDATA, /**< USART0 rx data available Signal. */ #if (_SILICON_LABS_32B_SERIES > 0) prsSignalUSART0_RTS = PRS_USART0_RTS, /**< USART0 RTS Signal. */ prsSignalUSART0_TX = PRS_USART0_TX, /**< USART0 tx Signal. */ prsSignalUSART0_CS = PRS_USART0_CS, /**< USART0 chip select Signal. */ #endif #endif #if defined(USART1) prsSignalUSART1_TXC = PRS_USART1_TXC, /**< USART1 tx complete Signal. */ prsSignalUSART1_RXDATA = PRS_USART1_RXDATA, /**< USART1 rx data available Signal. */ #if defined(PRS_USART1_IRTX) prsSignalUSART1_IRTX = PRS_USART1_IRTX, /**< USART1 IR tx Signal. */ #endif #if (_SILICON_LABS_32B_SERIES > 0) prsSignalUSART1_RTS = PRS_USART1_RTS, /**< USART1 RTS Signal. */ prsSignalUSART1_TX = PRS_USART1_TX, /**< USART1 tx Signal. */ prsSignalUSART1_CS = PRS_USART1_CS, /**< USART1 chip select Signal. */ #endif #endif #if defined(USART2) prsSignalUSART2_TXC = PRS_USART2_TXC, /**< USART2 tx complete Signal. */ prsSignalUSART2_RXDATA = PRS_USART2_RXDATA, /**< USART2 rx data available Signal. */ #if defined(PRS_USART2_IRTX) prsSignalUSART2_IRTX = PRS_USART2_IRTX, /**< USART2 IR tx Signal. */ #endif #if (_SILICON_LABS_32B_SERIES > 0) prsSignalUSART2_RTS = PRS_USART2_RTS, /**< USART2 RTS Signal. */ prsSignalUSART2_TX = PRS_USART2_TX, /**< USART2 tx Signal. */ prsSignalUSART2_CS = PRS_USART2_CS, /**< USART2 chip select Signal. */ #endif #endif /* ADC Signals */ #if defined(IADC0) prsSignalIADC0_SCANENTRY = PRS_IADC0_SCANENTRYDONE, /**< IADC0 scan entry Signal. */ prsSignalIADC0_SCANTABLE = PRS_IADC0_SCANTABLEDONE, /**< IADC0 scan table Signal. */ prsSignalIADC0_SINGLE = PRS_IADC0_SINGLEDONE, /**< IADC0 single Signal. */ #endif /* GPIO pin Signals */ prsSignalGPIO_PIN0 = PRS_GPIO_PIN0, /**< GPIO Pin 0 Signal. */ prsSignalGPIO_PIN1 = PRS_GPIO_PIN1, /**< GPIO Pin 1 Signal. */ prsSignalGPIO_PIN2 = PRS_GPIO_PIN2, /**< GPIO Pin 2 Signal. */ prsSignalGPIO_PIN3 = PRS_GPIO_PIN3, /**< GPIO Pin 3 Signal. */ prsSignalGPIO_PIN4 = PRS_GPIO_PIN4, /**< GPIO Pin 4 Signal. */ prsSignalGPIO_PIN5 = PRS_GPIO_PIN5, /**< GPIO Pin 5 Signal. */ prsSignalGPIO_PIN6 = PRS_GPIO_PIN6, /**< GPIO Pin 6 Signal. */ prsSignalGPIO_PIN7 = PRS_GPIO_PIN7, /**< GPIO Pin 7 Signal. */ #if defined(PRS_GPIO_PIN15) prsSignalGPIO_PIN8 = PRS_GPIO_PIN8, /**< GPIO Pin 8 Signal. */ prsSignalGPIO_PIN9 = PRS_GPIO_PIN9, /**< GPIO Pin 9 Signal. */ prsSignalGPIO_PIN10 = PRS_GPIO_PIN10, /**< GPIO Pin 10 Signal. */ prsSignalGPIO_PIN11 = PRS_GPIO_PIN11, /**< GPIO Pin 11 Signal. */ prsSignalGPIO_PIN12 = PRS_GPIO_PIN12, /**< GPIO Pin 12 Signal. */ prsSignalGPIO_PIN13 = PRS_GPIO_PIN13, /**< GPIO Pin 13 Signal. */ prsSignalGPIO_PIN14 = PRS_GPIO_PIN14, /**< GPIO Pin 14 Signal. */ prsSignalGPIO_PIN15 = PRS_GPIO_PIN15, /**< GPIO Pin 15 Signal. */ #endif } PRS_Signal_t; #if defined(_SILICON_LABS_32B_SERIES_2) /** PRS Consumers. */ typedef enum { prsConsumerNone = 0x000, /**< No PRS consumer */ prsConsumerCMU_CALDN = offsetof(PRS_TypeDef, CONSUMER_CMU_CALDN), /**< CMU calibration down consumer. */ prsConsumerCMU_CALUP = offsetof(PRS_TypeDef, CONSUMER_CMU_CALUP), /**< CMU calibration up consumer. */ prsConsumerIADC0_SCANTRIGGER = offsetof(PRS_TypeDef, CONSUMER_IADC0_SCANTRIGGER), /**< IADC0 scan trigger consumer. */ prsConsumerIADC0_SINGLETRIGGER = offsetof(PRS_TypeDef, CONSUMER_IADC0_SINGLETRIGGER), /**< IADC0 single trigger consumer. */ prsConsumerLDMA_REQUEST0 = offsetof(PRS_TypeDef, CONSUMER_LDMAXBAR_DMAREQ0), /**< LDMA Request 0 consumer. */ prsConsumerLDMA_REQUEST1 = offsetof(PRS_TypeDef, CONSUMER_LDMAXBAR_DMAREQ1), /**< LDMA Request 1 consumer. */ prsConsumerLETIMER0_CLEAR = offsetof(PRS_TypeDef, CONSUMER_LETIMER_CLEAR), /**< LETIMER0 clear consumer. */ prsConsumerLETIMER0_START = offsetof(PRS_TypeDef, CONSUMER_LETIMER_START), /**< LETIMER0 start consumer. */ prsConsumerLETIMER0_STOP = offsetof(PRS_TypeDef, CONSUMER_LETIMER_STOP), /**< LETIMER0 stop consumer. */ prsConsumerTIMER0_CC0 = offsetof(PRS_TypeDef, CONSUMER_TIMER0_CC0), /**< TIMER0 capture/compare channel 0 consumer. */ prsConsumerTIMER0_CC1 = offsetof(PRS_TypeDef, CONSUMER_TIMER0_CC1), /**< TIMER0 capture/compare channel 1 consumer. */ prsConsumerTIMER0_CC2 = offsetof(PRS_TypeDef, CONSUMER_TIMER0_CC2), /**< TIMER0 capture/compare channel 2 consumer. */ prsConsumerTIMER1_CC0 = offsetof(PRS_TypeDef, CONSUMER_TIMER1_CC0), /**< TIMER1 capture/compare channel 0 consumer. */ prsConsumerTIMER1_CC1 = offsetof(PRS_TypeDef, CONSUMER_TIMER1_CC1), /**< TIMER1 capture/compare channel 1 consumer. */ prsConsumerTIMER1_CC2 = offsetof(PRS_TypeDef, CONSUMER_TIMER1_CC2), /**< TIMER1 capture/compare channel 2 consumer. */ prsConsumerTIMER2_CC0 = offsetof(PRS_TypeDef, CONSUMER_TIMER2_CC0), /**< TIMER2 capture/compare channel 0 consumer. */ prsConsumerTIMER2_CC1 = offsetof(PRS_TypeDef, CONSUMER_TIMER2_CC1), /**< TIMER2 capture/compare channel 1 consumer. */ prsConsumerTIMER2_CC2 = offsetof(PRS_TypeDef, CONSUMER_TIMER2_CC2), /**< TIMER2 capture/compare channel 2 consumer. */ prsConsumerTIMER3_CC0 = offsetof(PRS_TypeDef, CONSUMER_TIMER3_CC0), /**< TIMER3 capture/compare channel 0 consumer. */ prsConsumerTIMER3_CC1 = offsetof(PRS_TypeDef, CONSUMER_TIMER3_CC1), /**< TIMER3 capture/compare channel 1 consumer. */ prsConsumerTIMER3_CC2 = offsetof(PRS_TypeDef, CONSUMER_TIMER3_CC2), /**< TIMER3 capture/compare channel 2 consumer. */ prsConsumerUSART0_CLK = offsetof(PRS_TypeDef, CONSUMER_USART0_CLK), /**< USART0 clock consumer. */ prsConsumerUSART0_IR = offsetof(PRS_TypeDef, CONSUMER_USART0_IR), /**< USART0 IR consumer. */ prsConsumerUSART0_RX = offsetof(PRS_TypeDef, CONSUMER_USART0_RX), /**< USART0 rx consumer. */ prsConsumerUSART0_TRIGGER = offsetof(PRS_TypeDef, CONSUMER_USART0_TRIGGER), /**< USART0 trigger consumer. */ prsConsumerUSART1_CLK = offsetof(PRS_TypeDef, CONSUMER_USART1_CLK), /**< USART1 clock consumer. */ prsConsumerUSART1_IR = offsetof(PRS_TypeDef, CONSUMER_USART1_IR), /**< USART1 IR consumer. */ prsConsumerUSART1_RX = offsetof(PRS_TypeDef, CONSUMER_USART1_RX), /**< USART1 rx consumer. */ prsConsumerUSART1_TRIGGER = offsetof(PRS_TypeDef, CONSUMER_USART1_TRIGGER), /**< USART1 trigger consumer. */ prsConsumerUSART2_CLK = offsetof(PRS_TypeDef, CONSUMER_USART2_CLK), /**< USART2 clock consumer. */ prsConsumerUSART2_IR = offsetof(PRS_TypeDef, CONSUMER_USART2_IR), /**< USART2 IR consumer. */ prsConsumerUSART2_RX = offsetof(PRS_TypeDef, CONSUMER_USART2_RX), /**< USART2 rx consumer. */ prsConsumerUSART2_TRIGGER = offsetof(PRS_TypeDef, CONSUMER_USART2_TRIGGER), /**< USART2 trigger consumer. */ prsConsumerWDOG0_SRC0 = offsetof(PRS_TypeDef, CONSUMER_WDOG0_SRC0), /**< WDOG0 source 0 consumer. */ prsConsumerWDOG0_SRC1 = offsetof(PRS_TypeDef, CONSUMER_WDOG0_SRC1), /**< WDOG0 source 1 consumer. */ prsConsumerWDOG1_SRC0 = offsetof(PRS_TypeDef, CONSUMER_WDOG1_SRC0), /**< WDOG1 source 0 consumer. */ prsConsumerWDOG1_SRC1 = offsetof(PRS_TypeDef, CONSUMER_WDOG1_SRC1), /**< WDOG1 source 1 consumer. */ } PRS_Consumer_t; #endif /******************************************************************************* ***************************** PROTOTYPES ********************************** ******************************************************************************/ /***************************************************************************//** * @brief * Set level control bit for one or more channels. * * @details * The level value for a channel is XORed with both the pulse possibly issued * by PRS_PulseTrigger() and the PRS input signal selected for the channel(s). * * @cond DOXYDOC_S2_DEVICE * @note * Note that software level control is only available for asynchronous * channels on Series 2 devices. * @endcond * * @param[in] level * Level to use for channels indicated by @p mask. Use logical OR combination * of PRS_SWLEVEL_CHnLEVEL defines for channels to set high level, otherwise 0. * * @param[in] mask * Mask indicating which channels to set level for. Use logical OR combination * of PRS_SWLEVEL_CHnLEVEL defines. ******************************************************************************/ __STATIC_INLINE void PRS_LevelSet(uint32_t level, uint32_t mask) { #if defined(_PRS_SWLEVEL_MASK) PRS->SWLEVEL = (PRS->SWLEVEL & ~mask) | (level & mask); #else PRS->ASYNC_SWLEVEL = (PRS->ASYNC_SWLEVEL & ~mask) | (level & mask); #endif } /***************************************************************************//** * @brief * Get level control bit for all channels. * * @return * The current software level configuration. ******************************************************************************/ __STATIC_INLINE uint32_t PRS_LevelGet(void) { #if defined(_PRS_SWLEVEL_MASK) return PRS->SWLEVEL; #else return PRS->ASYNC_SWLEVEL; #endif } #if defined(_PRS_ASYNC_PEEK_MASK) || defined(_PRS_PEEK_MASK) /***************************************************************************//** * @brief * Get the PRS channel values for all channels. * * @param[in] type * PRS channel type. This can be either @ref prsTypeAsync or * @ref prsTypeSync. * * @return * The current PRS channel output values for all channels as a bitset. ******************************************************************************/ __STATIC_INLINE uint32_t PRS_Values(PRS_ChType_t type) { #if defined(_PRS_ASYNC_PEEK_MASK) if (type == prsTypeAsync) { return PRS->ASYNC_PEEK; } else { return PRS->SYNC_PEEK; } #else (void) type; return PRS->PEEK; #endif } /***************************************************************************//** * @brief * Get the PRS channel value for a single channel. * * @param[in] ch * PRS channel number. * * @param[in] type * PRS channel type. This can be either @ref prsTypeAsync or * @ref prsTypeSync. * * @return * The current PRS channel output value. This is either 0 or 1. ******************************************************************************/ __STATIC_INLINE bool PRS_ChannelValue(unsigned int ch, PRS_ChType_t type) { return (PRS_Values(type) >> ch) & 0x1U; } #endif /***************************************************************************//** * @brief * Trigger a high pulse (one HFPERCLK) for one or more channels. * * @details * Setting a bit for a channel causes the bit in the register to remain high * for one HFPERCLK cycle. Pulse is XORed with both the corresponding bit * in PRS SWLEVEL register and the PRS input signal selected for the * channel(s). * * @param[in] channels * Logical ORed combination of channels to trigger a pulse for. Use * PRS_SWPULSE_CHnPULSE defines. ******************************************************************************/ __STATIC_INLINE void PRS_PulseTrigger(uint32_t channels) { #if defined(_PRS_SWPULSE_MASK) PRS->SWPULSE = channels & _PRS_SWPULSE_MASK; #else PRS->ASYNC_SWPULSE = channels & _PRS_ASYNC_SWPULSE_MASK; #endif } /***************************************************************************//** * @brief * Set the PRS channel level for one asynchronous PRS channel. * * @param[in] ch * PRS channel number. * * @param[in] level * true to set the level high (1) and false to set the level low (0). ******************************************************************************/ __STATIC_INLINE void PRS_ChannelLevelSet(unsigned int ch, bool level) { PRS_LevelSet(level << ch, 0x1U << ch); } /***************************************************************************//** * @brief * Trigger a pulse on one PRS channel. * * @param[in] ch * PRS channel number. ******************************************************************************/ __STATIC_INLINE void PRS_ChannelPulse(unsigned int ch) { PRS_PulseTrigger(0x1U << ch); } void PRS_SourceSignalSet(unsigned int ch, uint32_t source, uint32_t signal, PRS_Edge_TypeDef edge); #if defined(PRS_ASYNC_SUPPORTED) void PRS_SourceAsyncSignalSet(unsigned int ch, uint32_t source, uint32_t signal); #endif #if defined(_PRS_ROUTELOC0_MASK) || (_PRS_ROUTE_MASK) void PRS_GpioOutputLocation(unsigned int ch, unsigned int location); #endif int PRS_GetFreeChannel(PRS_ChType_t type); void PRS_Reset(void); void PRS_ConnectSignal(unsigned int ch, PRS_ChType_t type, PRS_Signal_t signal); #if defined(_SILICON_LABS_32B_SERIES_2) void PRS_ConnectConsumer(unsigned int ch, PRS_ChType_t type, PRS_Consumer_t consumer); void PRS_PinOutput(unsigned int ch, PRS_ChType_t type, GPIO_Port_TypeDef port, uint8_t pin); void PRS_Combine(unsigned int chA, unsigned int chB, PRS_Logic_t logic); #endif /** @} (end addtogroup PRS) */ /** @} (end addtogroup emlib) */ #ifdef __cplusplus } #endif #endif /* defined(PRS_COUNT) && (PRS_COUNT > 0) */ #endif /* EM_PRS_H */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/emlib/inc/em_ramfunc.h.
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/***************************************************************************//** * @file * @brief RAM code support. * @version 5.7.0 ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * SPDX-License-Identifier: Zlib * * The licensor of this software is Silicon Laboratories Inc. * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be * appreciated but is not required. * 2. Altered source versions must be plainly marked as such, and must not be * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * ******************************************************************************/ #ifndef EM_RAMFUNC_H #define EM_RAMFUNC_H #ifdef __cplusplus extern "C" { #endif /* *INDENT-OFF* */ /***************************************************************************//** * @addtogroup emlib * @{ * @addtogroup RAMFUNC * @brief RAM code support * @details * Provides support for executing code from RAM. * Provides a unified method to manage RAM code across all supported tools. * @{ @note Other cross-compiler support macros are implemented in @ref COMMON. @note Functions executing from RAM should not be declared as static. @warning Standard library facilities are available to the tool with GCC in hosted mode (default), regardless of the section attribute. Calls to standard libraries placed in the default section may therefore occur. To disable hosted mode, add '-ffreestanding' to the build command line. This is the only way to guarantee no calls to standard libraries with GCC. Read more at https://gcc.gnu.org/onlinedocs/gcc-5.3.0/gcc/Standards.html @warning Keil/ARM uVision users must add a section named "ram_code" in their linker scatter file. This section must be in RAM memory. Look in the MCU SDK for example scatter files (ram_code.sct). @n @section ramfunc_usage Usage In your .h file: @verbatim #include "em_ramfunc.h" SL_RAMFUNC_DECLARATOR void MyPrint(const char* string); @endverbatim Issues have been observed with armgcc when there is no declarator. It is recommended to have a declarator also for internal functions, but move the declarator to the .c file. In your .c file: @verbatim #include "em_ramfunc.h" SL_RAMFUNC_DEFINITION_BEGIN void MyPrint(const char* string) { ... } SL_RAMFUNC_DEFINITION_END @endverbatim ******************************************************************************/ /* *INDENT-ON* */ /******************************************************************************* ****************************** DEFINES *********************************** ******************************************************************************/ /** * @brief * This define is not present by default. By compiling with define * @ref SL_RAMFUNC_DISABLE, code placed in RAM by SL_RAMFUNC macros * will be placed in default code space (Flash) instead. * * @note * This define is not present by default. */ #if defined(DOXY_DOC_ONLY) #define SL_RAMFUNC_DISABLE #endif #if defined(SL_RAMFUNC_DISABLE) /** @brief Compiler ported function declarator for RAM code. */ #define SL_RAMFUNC_DECLARATOR /** @brief Compiler ported function definition begin marker for RAM code. */ #define SL_RAMFUNC_DEFINITION_BEGIN /** @brief Compiler ported function definition end marker for RAM code. */ #define SL_RAMFUNC_DEFINITION_END #elif defined(__CC_ARM) /* MDK-ARM compiler */ #define SL_RAMFUNC_DECLARATOR #define SL_RAMFUNC_DEFINITION_BEGIN _Pragma("arm section code=\"ram_code\"") #define SL_RAMFUNC_DEFINITION_END _Pragma("arm section code") #elif defined(__ICCARM__) /* IAR Embedded Workbench */ #define SL_RAMFUNC_DECLARATOR __ramfunc #define SL_RAMFUNC_DEFINITION_BEGIN SL_RAMFUNC_DECLARATOR #define SL_RAMFUNC_DEFINITION_END #elif defined(__GNUC__) && defined(__CROSSWORKS_ARM) /* Rowley Crossworks */ #define SL_RAMFUNC_DECLARATOR __attribute__ ((section(".fast"))) #define SL_RAMFUNC_DEFINITION_BEGIN SL_RAMFUNC_DECLARATOR #define SL_RAMFUNC_DEFINITION_END #elif defined(__GNUC__) /* Simplicity Studio, Atollic and Vanilla armgcc */ #define SL_RAMFUNC_DECLARATOR __attribute__ ((section(".ram"))) #define SL_RAMFUNC_DEFINITION_BEGIN SL_RAMFUNC_DECLARATOR #define SL_RAMFUNC_DEFINITION_END #endif /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ /* Deprecated macro names and user configuration */ #if defined(RAMFUNC_DISABLE) #define SL_RAMFUNC_DISABLE #endif #define RAMFUNC_DECLARATOR SL_RAMFUNC_DECLARATOR #define RAMFUNC_DEFINITION_BEGIN SL_RAMFUNC_DEFINITION_BEGIN #define RAMFUNC_DEFINITION_END SL_RAMFUNC_DEFINITION_END /** @endcond */ /** @} (end addtogroup RAMFUNC) */ /** @} (end addtogroup emlib) */ #ifdef __cplusplus } #endif #endif /* EM_RAMFUNC_H */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/emlib/inc/em_rmu.h.
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/***************************************************************************//** * @file * @brief Reset Management Unit (RMU) peripheral API * @version 5.7.0 ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * SPDX-License-Identifier: Zlib * * The licensor of this software is Silicon Laboratories Inc. * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be * appreciated but is not required. * 2. Altered source versions must be plainly marked as such, and must not be * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * ******************************************************************************/ #ifndef EM_RMU_H #define EM_RMU_H #include "em_device.h" #if (defined(RMU_COUNT) && (RMU_COUNT > 0)) || (_EMU_RSTCTRL_MASK) #include "em_assert.h" #include <stdbool.h> #ifdef __cplusplus extern "C" { #endif /***************************************************************************//** * @addtogroup emlib * @{ ******************************************************************************/ /***************************************************************************//** * @addtogroup RMU * @{ ******************************************************************************/ /******************************************************************************* ******************************** ENUMS ************************************ ******************************************************************************/ /** RMU reset modes. */ typedef enum { #if defined(_RMU_CTRL_PINRMODE_MASK) rmuResetModeDisabled = _RMU_CTRL_PINRMODE_DISABLED, rmuResetModeLimited = _RMU_CTRL_PINRMODE_LIMITED, rmuResetModeExtended = _RMU_CTRL_PINRMODE_EXTENDED, rmuResetModeFull = _RMU_CTRL_PINRMODE_FULL, #elif defined(_EMU_RSTCTRL_MASK) rmuResetModeDisabled = 0, rmuResetModeEnabled = 1, #else rmuResetModeClear = 0, rmuResetModeSet = 1, #endif } RMU_ResetMode_TypeDef; /** RMU controlled peripheral reset control and reset source control. */ typedef enum { #if defined(RMU_CTRL_BURSTEN) rmuResetBU = _RMU_CTRL_BURSTEN_MASK, /**< Reset control over Backup Power domain select. */ #endif #if defined(RMU_CTRL_LOCKUPRDIS) rmuResetLockUp = _RMU_CTRL_LOCKUPRDIS_MASK, /**< Cortex lockup reset select. */ #elif defined(_RMU_CTRL_LOCKUPRMODE_MASK) rmuResetLockUp = _RMU_CTRL_LOCKUPRMODE_MASK, /**< Cortex lockup reset select. */ #endif #if defined(_RMU_CTRL_WDOGRMODE_MASK) rmuResetWdog = _RMU_CTRL_WDOGRMODE_MASK, /**< WDOG reset select. */ #endif #if defined(_RMU_CTRL_LOCKUPRMODE_MASK) rmuResetCoreLockup = _RMU_CTRL_LOCKUPRMODE_MASK, /**< Cortex lockup reset select. */ #endif #if defined(_RMU_CTRL_SYSRMODE_MASK) rmuResetSys = _RMU_CTRL_SYSRMODE_MASK, /**< SYSRESET select. */ #endif #if defined(_RMU_CTRL_PINRMODE_MASK) rmuResetPin = _RMU_CTRL_PINRMODE_MASK, /**< Pin reset select. */ #endif #if defined(_EMU_RSTCTRL_WDOG0RMODE_MASK) rmuResetWdog0 = _EMU_RSTCTRL_WDOG0RMODE_MASK, /**< WDOG0 reset select */ #endif #if defined(_EMU_RSTCTRL_WDOG1RMODE_MASK) rmuResetWdog1 = _EMU_RSTCTRL_WDOG1RMODE_MASK, /**< WDOG1 reset select */ #endif #if defined(_EMU_RSTCTRL_SYSRMODE_MASK) rmuResetSys = _EMU_RSTCTRL_SYSRMODE_MASK, /**< SYSRESET select */ #endif #if defined(_EMU_RSTCTRL_LOCKUPRMODE_MASK) rmuResetCoreLockup = _EMU_RSTCTRL_LOCKUPRMODE_MASK, /**< Cortex lockup reset select */ #endif #if defined(_EMU_RSTCTRL_AVDDBODRMODE_MASK) rmuResetAVDD = _EMU_RSTCTRL_AVDDBODRMODE_MASK, /**< AVDD monitoring select */ #endif #if defined(_EMU_RSTCTRL_IOVDD0BODRMODE_MASK) rmuResetIOVDD0 = _EMU_RSTCTRL_IOVDD0BODRMODE_MASK, /**< IOVDD0 monitoring select */ #endif #if defined(_EMU_RSTCTRL_DECBODRMODE_MASK) rmuResetDecouple = _EMU_RSTCTRL_DECBODRMODE_MASK, /**< Decouple monitoring select */ #endif #if defined(_EMU_RSTCTRL_M0SYSRMODE_MASK) rmuResetM0Sys = _EMU_RSTCTRL_M0SYSRMODE_MASK, /**< M0+ (SE) system reset select */ #endif #if defined(_EMU_RSTCTRL_M0LOCKUPRMODE_MASK) rmuResetM0Lockup = _EMU_RSTCTRL_M0LOCKUPRMODE_MASK, /**< M0+ (SE) lockup select */ #endif } RMU_Reset_TypeDef; /******************************************************************************* ***************************** PROTOTYPES ********************************** ******************************************************************************/ /** RMU_LockupResetDisable kept for backwards compatibility. */ #define RMU_LockupResetDisable(A) RMU_ResetControl(rmuResetLockUp, A) void RMU_ResetControl(RMU_Reset_TypeDef reset, RMU_ResetMode_TypeDef mode); void RMU_ResetCauseClear(void); uint32_t RMU_ResetCauseGet(void); #if defined(_RMU_CTRL_RESETSTATE_MASK) /***************************************************************************//** * @brief * Set user reset state. Reset only by a Power-on-reset and a pin reset. * * @param[in] userState User state to set ******************************************************************************/ __STATIC_INLINE void RMU_UserResetStateSet(uint32_t userState) { EFM_ASSERT(!(userState & ~(_RMU_CTRL_RESETSTATE_MASK >> _RMU_CTRL_RESETSTATE_SHIFT))); RMU->CTRL = (RMU->CTRL & ~_RMU_CTRL_RESETSTATE_MASK) | (userState << _RMU_CTRL_RESETSTATE_SHIFT); } /***************************************************************************//** * @brief * Get user reset state. Reset only by a Power-on-reset and a pin reset. * * @return * Reset surviving user state. ******************************************************************************/ __STATIC_INLINE uint32_t RMU_UserResetStateGet(void) { uint32_t userState = (RMU->CTRL & _RMU_CTRL_RESETSTATE_MASK) >> _RMU_CTRL_RESETSTATE_SHIFT; return userState; } #endif /** @} (end addtogroup RMU) */ /** @} (end addtogroup emlib) */ #ifdef __cplusplus } #endif #endif /* defined(RMU_COUNT) && (RMU_COUNT > 0) */ #endif /* EM_RMU_H */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/emlib/inc/em_rtcc.h.
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/***************************************************************************//** * @file * @brief Real Time Counter (RTCC) peripheral API. * @version 5.7.0 ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * SPDX-License-Identifier: Zlib * * The licensor of this software is Silicon Laboratories Inc. * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be * appreciated but is not required. * 2. Altered source versions must be plainly marked as such, and must not be * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * ******************************************************************************/ #ifndef EM_RTCC_H #define EM_RTCC_H #include "em_device.h" #if defined(RTCC_COUNT) && (RTCC_COUNT == 1) #include <stdbool.h> #include "em_assert.h" #ifdef __cplusplus extern "C" { #endif /***************************************************************************//** * @addtogroup emlib * @{ ******************************************************************************/ /***************************************************************************//** * @addtogroup RTCC * @{ ******************************************************************************/ /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ #if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_84) \ || defined(_SILICON_LABS_GECKO_INTERNAL_SDID_89) /* Enable fix for errata "RTCC_E203 - Potential Stability Issue with RTCC * Registers". */ #define ERRATA_FIX_RTCC_E203 #endif #if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_84) /* Enable fix for errata "RTCC_E204 - Disabling the RTCC Backup RAM may consume extra * current". */ #define ERRATA_FIX_RTCC_E204 #endif /** @endcond */ /******************************************************************************* ********************************* ENUM ************************************ ******************************************************************************/ #if defined (_RTCC_CTRL_CNTMODE_MASK) /** Operational mode of the counter. */ typedef enum { /** Normal counter mode. The counter is incremented by 1 for each tick. */ rtccCntModeNormal = _RTCC_CTRL_CNTMODE_NORMAL, /** Calendar mode. Refer to the RTCC chapter of the Reference Manual for more * details on the calendar mode. */ rtccCntModeCalendar = _RTCC_CTRL_CNTMODE_CALENDAR } RTCC_CntMode_TypeDef; #endif /** Counter prescaler selection. */ #if defined (_RTCC_CTRL_CNTPRESC_DIV1) typedef enum { rtccCntPresc_1 = _RTCC_CTRL_CNTPRESC_DIV1, /**< Divide clock by 1. */ rtccCntPresc_2 = _RTCC_CTRL_CNTPRESC_DIV2, /**< Divide clock by 2. */ rtccCntPresc_4 = _RTCC_CTRL_CNTPRESC_DIV4, /**< Divide clock by 4. */ rtccCntPresc_8 = _RTCC_CTRL_CNTPRESC_DIV8, /**< Divide clock by 8. */ rtccCntPresc_16 = _RTCC_CTRL_CNTPRESC_DIV16, /**< Divide clock by 16. */ rtccCntPresc_32 = _RTCC_CTRL_CNTPRESC_DIV32, /**< Divide clock by 32. */ rtccCntPresc_64 = _RTCC_CTRL_CNTPRESC_DIV64, /**< Divide clock by 64. */ rtccCntPresc_128 = _RTCC_CTRL_CNTPRESC_DIV128, /**< Divide clock by 128. */ rtccCntPresc_256 = _RTCC_CTRL_CNTPRESC_DIV256, /**< Divide clock by 256. */ rtccCntPresc_512 = _RTCC_CTRL_CNTPRESC_DIV512, /**< Divide clock by 512. */ rtccCntPresc_1024 = _RTCC_CTRL_CNTPRESC_DIV1024, /**< Divide clock by 1024. */ rtccCntPresc_2048 = _RTCC_CTRL_CNTPRESC_DIV2048, /**< Divide clock by 2048. */ rtccCntPresc_4096 = _RTCC_CTRL_CNTPRESC_DIV4096, /**< Divide clock by 4096. */ rtccCntPresc_8192 = _RTCC_CTRL_CNTPRESC_DIV8192, /**< Divide clock by 8192. */ rtccCntPresc_16384 = _RTCC_CTRL_CNTPRESC_DIV16384, /**< Divide clock by 16384. */ rtccCntPresc_32768 = _RTCC_CTRL_CNTPRESC_DIV32768 /**< Divide clock by 32768. */ } RTCC_CntPresc_TypeDef; #elif defined (_RTCC_CFG_CNTPRESC_DIV1) typedef enum { rtccCntPresc_1 = _RTCC_CFG_CNTPRESC_DIV1, /**< Divide clock by 1. */ rtccCntPresc_2 = _RTCC_CFG_CNTPRESC_DIV2, /**< Divide clock by 2. */ rtccCntPresc_4 = _RTCC_CFG_CNTPRESC_DIV4, /**< Divide clock by 4. */ rtccCntPresc_8 = _RTCC_CFG_CNTPRESC_DIV8, /**< Divide clock by 8. */ rtccCntPresc_16 = _RTCC_CFG_CNTPRESC_DIV16, /**< Divide clock by 16. */ rtccCntPresc_32 = _RTCC_CFG_CNTPRESC_DIV32, /**< Divide clock by 32. */ rtccCntPresc_64 = _RTCC_CFG_CNTPRESC_DIV64, /**< Divide clock by 64. */ rtccCntPresc_128 = _RTCC_CFG_CNTPRESC_DIV128, /**< Divide clock by 128. */ rtccCntPresc_256 = _RTCC_CFG_CNTPRESC_DIV256, /**< Divide clock by 256. */ rtccCntPresc_512 = _RTCC_CFG_CNTPRESC_DIV512, /**< Divide clock by 512. */ rtccCntPresc_1024 = _RTCC_CFG_CNTPRESC_DIV1024, /**< Divide clock by 1024. */ rtccCntPresc_2048 = _RTCC_CFG_CNTPRESC_DIV2048, /**< Divide clock by 2048. */ rtccCntPresc_4096 = _RTCC_CFG_CNTPRESC_DIV4096, /**< Divide clock by 4096. */ rtccCntPresc_8192 = _RTCC_CFG_CNTPRESC_DIV8192, /**< Divide clock by 8192. */ rtccCntPresc_16384 = _RTCC_CFG_CNTPRESC_DIV16384, /**< Divide clock by 16384. */ rtccCntPresc_32768 = _RTCC_CFG_CNTPRESC_DIV32768 /**< Divide clock by 32768. */ } RTCC_CntPresc_TypeDef; #endif /** Prescaler mode of the RTCC counter. */ #if defined (_RTCC_CTRL_CNTTICK_MASK) typedef enum { /** CNT register ticks according to prescaler value. */ rtccCntTickPresc = _RTCC_CTRL_CNTTICK_PRESC, /** CNT register ticks when PRECNT matches the 15 least significant bits of * ch. 0 CCV register. */ rtccCntTickCCV0Match = _RTCC_CTRL_CNTTICK_CCV0MATCH } RTCC_PrescMode_TypeDef; #elif defined (_RTCC_CFG_CNTTICK_MASK) typedef enum { /** CNT register ticks according to the prescaler value. */ rtccCntTickPresc = _RTCC_CFG_CNTTICK_PRESC, /** CNT register ticks when PRECNT matches the 15 least significant bits of * ch. 0 CCV register. */ rtccCntTickCCV0Match = _RTCC_CFG_CNTTICK_CCV0MATCH } RTCC_PrescMode_TypeDef; #endif /** Capture/Compare channel mode. */ typedef enum { rtccCapComChModeOff = _RTCC_CC_CTRL_MODE_OFF, /**< Capture/Compare channel turned off. */ rtccCapComChModeCapture = _RTCC_CC_CTRL_MODE_INPUTCAPTURE, /**< Capture mode. */ rtccCapComChModeCompare = _RTCC_CC_CTRL_MODE_OUTPUTCOMPARE, /**< Compare mode. */ } RTCC_CapComChMode_TypeDef; /** Compare match output action mode. */ typedef enum { rtccCompMatchOutActionPulse = _RTCC_CC_CTRL_CMOA_PULSE, /**< Generate a pulse. */ rtccCompMatchOutActionToggle = _RTCC_CC_CTRL_CMOA_TOGGLE, /**< Toggle output. */ rtccCompMatchOutActionClear = _RTCC_CC_CTRL_CMOA_CLEAR, /**< Clear output. */ rtccCompMatchOutActionSet = _RTCC_CC_CTRL_CMOA_SET /**< Set output. */ } RTCC_CompMatchOutAction_TypeDef; /** PRS channel number. This type is used when configuring input capture mode on * a RTCC channel. */ typedef uint8_t RTCC_PRSSel_TypeDef; /** Deprecated PRS channel values. New code should use an integer instead of * using these deprecated enum values. */ #define rtccPRSCh0 0U #define rtccPRSCh1 1U #define rtccPRSCh2 2U #define rtccPRSCh3 3U #define rtccPRSCh4 4U #define rtccPRSCh5 5U #define rtccPRSCh6 6U #define rtccPRSCh7 7U #define rtccPRSCh8 8U #define rtccPRSCh9 9U #define rtccPRSCh10 10U #define rtccPRSCh11 11U /** Input edge select. */ typedef enum { rtccInEdgeRising = _RTCC_CC_CTRL_ICEDGE_RISING, /**< Rising edges detected. */ rtccInEdgeFalling = _RTCC_CC_CTRL_ICEDGE_FALLING, /**< Falling edges detected. */ rtccInEdgeBoth = _RTCC_CC_CTRL_ICEDGE_BOTH, /**< Both edges detected. */ rtccInEdgeNone = _RTCC_CC_CTRL_ICEDGE_NONE /**< No edge detection, signal is left as is. */ } RTCC_InEdgeSel_TypeDef; /** Capture/Compare channel compare mode. */ typedef enum { /** CCVx is compared with the CNT register. */ rtccCompBaseCnt = _RTCC_CC_CTRL_COMPBASE_CNT, /** CCVx is compared with a CNT[16:0] and PRECNT[14:0]. */ rtccCompBasePreCnt = _RTCC_CC_CTRL_COMPBASE_PRECNT } RTCC_CompBase_TypeDef; #if defined (_RTCC_CC_CTRL_DAYCC_MASK) /** Day compare mode. */ typedef enum { rtccDayCompareModeMonth = _RTCC_CC_CTRL_DAYCC_MONTH, /**< Day of month is selected for Capture/Compare. */ rtccDayCompareModeWeek = _RTCC_CC_CTRL_DAYCC_WEEK /**< Day of week is selected for Capture/Compare. */ } RTCC_DayCompareMode_TypeDef; #endif /******************************************************************************* ******************************* STRUCTS *********************************** ******************************************************************************/ /** RTCC initialization structure. */ typedef struct { /** Enable/disable counting when initialization is completed. */ bool enable; /** Enable/disable timer counting during debug halt. */ bool debugRun; /** Enable/disable pre-counter wrap on ch. 0 CCV value. */ bool precntWrapOnCCV0; /** Enable/disable counter wrap on ch. 1 CCV value. */ bool cntWrapOnCCV1; /** Counter prescaler. */ RTCC_CntPresc_TypeDef presc; /** Prescaler mode. */ RTCC_PrescMode_TypeDef prescMode; #if defined(_RTCC_CTRL_BUMODETSEN_MASK) /** Enable/disable storing RTCC counter value in RTCC_CCV2 upon backup mode * entry. */ bool enaBackupModeSet; #endif #if defined(_RTCC_CTRL_OSCFDETEN_MASK) /** Enable/disable the check that sets OSCFFAIL interrupt flag if no * LFCLK-RTCC ticks are detected within one ULFRCO cycles. */ bool enaOSCFailDetect; #endif #if defined (_RTCC_CTRL_CNTMODE_MASK) /** Select operational mode of the counter. */ RTCC_CntMode_TypeDef cntMode; #endif #if defined (_RTCC_CTRL_LYEARCORRDIS_MASK) /** Disable leap year correction for calendar mode. When this parameter is * set to false, February has 29 days if (year % 4 == 0). If set to true, * February always has 28 days. */ bool disLeapYearCorr; #endif } RTCC_Init_TypeDef; /** RTCC capture/compare channel configuration structure. */ typedef struct { /** Select mode of Capture/Compare channel. */ RTCC_CapComChMode_TypeDef chMode; /** Compare mode channel match output action. */ RTCC_CompMatchOutAction_TypeDef compMatchOutAction; /** Capture mode channel PRS input channel selection. */ RTCC_PRSSel_TypeDef prsSel; /** Capture mode channel input edge selection. */ RTCC_InEdgeSel_TypeDef inputEdgeSel; /** Comparison base of channel in compare mode. */ RTCC_CompBase_TypeDef compBase; #if defined (_RTCC_CC_CTRL_COMPMASK_MASK) /** The COMPMASK (5 bit) most significant bits of compare value will not * be subject to comparison. */ uint8_t compMask; #endif #if defined (_RTCC_CC_CTRL_DAYCC_MASK) /** Day compare mode. */ RTCC_DayCompareMode_TypeDef dayCompMode; #endif } RTCC_CCChConf_TypeDef; /******************************************************************************* ******************************* DEFINES *********************************** ******************************************************************************/ /** Default RTCC initialization structure. */ #if defined(_SILICON_LABS_32B_SERIES_2) #define RTCC_INIT_DEFAULT \ { \ true, /* Start counting when init done. */ \ false, /* Disable RTCC during debug halt. */ \ false, /* Disable precounter wrap on ch. 0 CCV value. */ \ false, /* Disable counter wrap on ch. 1 CCV value. */ \ rtccCntPresc_32, /* 977 us per tick. */ \ rtccCntTickPresc, /* Counter increments according to prescaler value.*/ \ } #elif defined(_RTCC_CTRL_BUMODETSEN_MASK) #define RTCC_INIT_DEFAULT \ { \ true, /* Start counting when initialization is done. */ \ false, /* Disable RTCC during debug halt. */ \ false, /* Disable pre-counter wrap on ch. 0 CCV value. */ \ false, /* Disable counter wrap on ch. 1 CCV value. */ \ rtccCntPresc_32, /* 977 us per tick. */ \ rtccCntTickPresc, /* Counter increments according to prescaler value.*/ \ false, /* No RTCC storage on backup mode entry. */ \ false, /* No RTCC oscillator failure detection. */ \ rtccCntModeNormal, /* Normal RTCC mode. */ \ false, /* No leap year correction. */ \ } #else #define RTCC_INIT_DEFAULT \ { \ true, /* Start counting when initialization is done. */ \ false, /* Disable RTCC during debug halt. */ \ false, /* Disable pre-counter wrap on ch. 0 CCV value. */ \ false, /* Disable counter wrap on ch. 1 CCV value. */ \ rtccCntPresc_32, /* 977 us per tick. */ \ rtccCntTickPresc, /* Counter increments according to prescaler value.*/ \ false, /* No RTCC oscillator failure detection. */ \ rtccCntModeNormal, /* Normal RTCC mode. */ \ false, /* No leap year correction. */ \ } #endif #if defined(_SILICON_LABS_32B_SERIES_2) /** Default RTCC channel output compare initialization structure. */ #define RTCC_CH_INIT_COMPARE_DEFAULT \ { \ rtccCapComChModeCompare, /* Select output compare mode. */ \ rtccCompMatchOutActionPulse, /* Create pulse on compare match. */ \ 0, /* Don't care. */ \ rtccInEdgeNone, /* Don't care. */ \ rtccCompBaseCnt, /* Use CNT for comparison. */ \ } /** Default RTCC channel input capture initialization structure. */ #define RTCC_CH_INIT_CAPTURE_DEFAULT \ { \ rtccCapComChModeCapture, /* Select input capture mode. */ \ rtccCompMatchOutActionPulse, /* Don't care. */ \ 0, /* Use PRS channel 0 as trigger. */ \ rtccInEdgeRising, /* Capture on rising edge. */ \ rtccCompBaseCnt, /* Don't care. */ \ } #else // Series 1 devices /** Default RTCC channel output compare initialization structure. */ #define RTCC_CH_INIT_COMPARE_DEFAULT \ { \ rtccCapComChModeCompare, /* Select output compare mode. */ \ rtccCompMatchOutActionPulse, /* Create pulse on compare match.*/ \ 0, /* PRS channel 0 (not used). */ \ rtccInEdgeNone, /* No edge detection. */ \ rtccCompBaseCnt, /* Counter comparison base. */ \ 0, /* No compare mask bits set. */ \ rtccDayCompareModeMonth /* Don't care */ \ } /** Default RTCC channel input capture initialization structure. */ #define RTCC_CH_INIT_CAPTURE_DEFAULT \ { \ rtccCapComChModeCapture, /* Select input capture mode. */ \ rtccCompMatchOutActionPulse, /* Create pulse on capture. */ \ 0, /* PRS channel 0. */ \ rtccInEdgeRising, /* Rising edge detection. */ \ rtccCompBaseCnt, /* Don't care. */ \ 0, /* Don't care. */ \ rtccDayCompareModeMonth /* Don't care */ \ } #endif /** Number of RTCC capture/compare channels */ #if !defined(RTCC_CC_NUM) #define RTCC_CC_NUM 3UL #endif /** Validation of valid RTCC channel for assert statements. */ #define RTCC_CH_VALID(ch) ((unsigned)(ch) < RTCC_CC_NUM) /******************************************************************************* ***************************** PROTOTYPES ********************************** ******************************************************************************/ /***************************************************************************//** * @brief * Get RTCC compare register value for selected channel. * * @param[in] ch * Channel selector. * * @return * Compare register value. ******************************************************************************/ __STATIC_INLINE uint32_t RTCC_ChannelCompareValueGet(int ch) { EFM_ASSERT(RTCC_CH_VALID(ch) ); #if defined (_RTCC_CC_CCV_MASK) return RTCC->CC[ch].CCV; #elif defined (_RTCC_CC_OCVALUE_MASK) return RTCC->CC[ch].OCVALUE; #endif } /***************************************************************************//** * @brief * Set RTCC compare register value for selected channel. * * @param[in] ch * Channel selector. * * @param[in] value * Compare register value ******************************************************************************/ __STATIC_INLINE void RTCC_ChannelCompareValueSet(int ch, uint32_t value) { EFM_ASSERT(RTCC_CH_VALID(ch) ); #if defined (_RTCC_CC_CCV_MASK) RTCC->CC[ch].CCV = value; #elif defined (_RTCC_CC_OCVALUE_MASK) RTCC->CC[ch].OCVALUE = value; #endif } /***************************************************************************//** * @brief * Get RTCC input capture register value for selected channel. * * @param[in] ch * Channel selector. * * @return * Capture register value. ******************************************************************************/ __STATIC_INLINE uint32_t RTCC_ChannelCaptureValueGet(int ch) { EFM_ASSERT(RTCC_CH_VALID(ch) ); #if defined (_RTCC_CC_CCV_MASK) return RTCC->CC[ch].CCV; #elif defined (_RTCC_CC_ICVALUE_MASK) return RTCC->CC[ch].ICVALUE; #endif } /***************************************************************************//** * @brief * Get RTCC capture/compare register value for selected channel. * For parts with separate capture compare value registers, this function * returns the compare value. * * @param[in] ch * Channel selector. * * @return * Capture/compare register value. ******************************************************************************/ __STATIC_INLINE uint32_t RTCC_ChannelCCVGet(int ch) { return RTCC_ChannelCompareValueGet(ch); } /***************************************************************************//** * @brief * Set RTCC capture/compare register value for selected channel. * For parts with separate capture compare value registers, this function * sets the compare value. * * @param[in] ch * Channel selector. * * @param[in] value * Capture/compare register value ******************************************************************************/ __STATIC_INLINE void RTCC_ChannelCCVSet(int ch, uint32_t value) { RTCC_ChannelCompareValueSet(ch, value); } #if defined (_RTCC_CC_DATE_MASK) /***************************************************************************//** * @brief * Get the calendar DATE register content for selected channel. * * @param[in] ch * Channel selector. * * @return * DATE register value. ******************************************************************************/ __STATIC_INLINE uint32_t RTCC_ChannelDateGet(int ch) { EFM_ASSERT(RTCC_CH_VALID(ch) ); return RTCC->CC[ch].DATE; } /***************************************************************************//** * @brief * Set calendar DATE register for selected channel. * * @param[in] ch * Channel selector. * * @param[in] date * DATE value. ******************************************************************************/ __STATIC_INLINE void RTCC_ChannelDateSet(int ch, uint32_t date) { EFM_ASSERT(RTCC_CH_VALID(ch) ); RTCC->CC[ch].DATE = date; } /***************************************************************************//** * @brief * Get calendar TIME register content for selected channel. * * @param[in] ch * Channel selector. * * @return * TIME register value. ******************************************************************************/ __STATIC_INLINE uint32_t RTCC_ChannelTimeGet(int ch) { EFM_ASSERT(RTCC_CH_VALID(ch) ); return RTCC->CC[ch].TIME; } /***************************************************************************//** * @brief * Set calendar TIME register for selected channel. * * @param[in] ch * Channel selector. * * @param[in] time * TIME value. ******************************************************************************/ __STATIC_INLINE void RTCC_ChannelTimeSet(int ch, uint32_t time) { EFM_ASSERT(RTCC_CH_VALID(ch) ); RTCC->CC[ch].TIME = time; } #endif /* defined (_RTCC_CC_DATE_MASK) */ /***************************************************************************//** * @brief * Get combined CNT/PRECNT register content. * * @return * CNT/PRECNT register value. ******************************************************************************/ __STATIC_INLINE uint32_t RTCC_CombinedCounterGet(void) { #if defined (RTCC_SYNCBUSY_CNT) || defined (RTCC_SYNCBUSY_CNT) while ((RTCC->SYNCBUSY & (RTCC_SYNCBUSY_CNT | RTCC_SYNCBUSY_PRECNT)) != 0U) { /* Wait for CNT and PRECNT to synchronize */ } #endif return RTCC->COMBCNT; } /***************************************************************************//** * @brief * Get RTCC counter value. * * @return * Current RTCC counter value. ******************************************************************************/ __STATIC_INLINE uint32_t RTCC_CounterGet(void) { #if defined (RTCC_SYNCBUSY_CNT) while ((RTCC->SYNCBUSY & RTCC_SYNCBUSY_CNT) != 0U) { /* Wait for CNT to synchronize before getting value */ } #endif return RTCC->CNT; } /***************************************************************************//** * @brief * Set RTCC CNT counter. * * @param[in] value * CNT value. ******************************************************************************/ __STATIC_INLINE void RTCC_CounterSet(uint32_t value) { #if defined (RTCC_SYNCBUSY_CNT) while ((RTCC->SYNCBUSY & RTCC_SYNCBUSY_CNT) != 0U) { /* Wait for CNT to synchronize before setting new value */ } #endif RTCC->CNT = value; } #if defined (_RTCC_CC_DATE_MASK) /***************************************************************************//** * @brief * Get DATE register value. * * @return * Current DATE register value. ******************************************************************************/ __STATIC_INLINE uint32_t RTCC_DateGet(void) { return RTCC->DATE; } /***************************************************************************//** * @brief * Set RTCC DATE register. * * @param[in] date * DATE value. ******************************************************************************/ __STATIC_INLINE void RTCC_DateSet(uint32_t date) { RTCC->DATE = date; } #endif /* defined (_RTCC_CC_DATE_MASK) */ #if defined (RTCC_EM4WUEN_EM4WU) /***************************************************************************//** * @brief * Enable/disable EM4 wakeup capability. * * @param[in] enable * Set to true to enable EM4 wakeup, set to false otherwise. ******************************************************************************/ __STATIC_INLINE void RTCC_EM4WakeupEnable(bool enable) { if ( enable ) { RTCC->EM4WUEN = RTCC_EM4WUEN_EM4WU; } else { RTCC->EM4WUEN = 0; } } #endif void RTCC_Enable(bool enable); void RTCC_Init(const RTCC_Init_TypeDef *init); void RTCC_ChannelInit(int ch, RTCC_CCChConf_TypeDef const *confPtr); /***************************************************************************//** * @brief * Clear one or more pending RTCC interrupts. * * @param[in] flags * RTCC interrupt sources to clear. Use a set of interrupt flags OR-ed * together to clear multiple interrupt sources. ******************************************************************************/ __STATIC_INLINE void RTCC_IntClear(uint32_t flags) { #if defined (RTCC_HAS_SET_CLEAR) RTCC->IF_CLR = flags; #else RTCC->IFC = flags; #endif } /***************************************************************************//** * @brief * Disable one or more RTCC interrupts. * * @param[in] flags * RTCC interrupt sources to disable. Use a set of interrupt flags OR-ed * together to disable multiple interrupt. ******************************************************************************/ __STATIC_INLINE void RTCC_IntDisable(uint32_t flags) { RTCC->IEN &= ~flags; } /***************************************************************************//** * @brief * Enable one or more RTCC interrupts. * * @note * Depending on the use, a pending interrupt may already be set prior to * enabling the interrupt. To ignore a pending interrupt, consider using * RTCC_IntClear() prior to enabling the interrupt. * * @param[in] flags * RTCC interrupt sources to enable. Use a set of interrupt flags OR-ed * together to set multiple interrupt. ******************************************************************************/ __STATIC_INLINE void RTCC_IntEnable(uint32_t flags) { RTCC->IEN |= flags; } /***************************************************************************//** * @brief * Get pending RTCC interrupt flags. * * @note * Event bits are not cleared by using this function. * * @return * Pending RTCC interrupt sources. Returns a set of interrupt flags OR-ed * together for the interrupt sources set. ******************************************************************************/ __STATIC_INLINE uint32_t RTCC_IntGet(void) { return RTCC->IF; } /***************************************************************************//** * @brief * Get enabled and pending RTCC interrupt flags. * * @details * Useful for handling more interrupt sources in the same interrupt handler. * * @return * Pending and enabled RTCC interrupt sources. Returns a set of interrupt * flags OR-ed together for the interrupt sources set. ******************************************************************************/ __STATIC_INLINE uint32_t RTCC_IntGetEnabled(void) { uint32_t tmp; tmp = RTCC->IEN; /* Bitwise AND of pending and enabled interrupt flags. */ return RTCC->IF & tmp; } /***************************************************************************//** * @brief * Set one or more pending RTCC interrupts from SW. * * @param[in] flags * RTCC interrupt sources to set to pending. Use a set of interrupt flags * (RTCC_IFS_nnn). ******************************************************************************/ __STATIC_INLINE void RTCC_IntSet(uint32_t flags) { #if defined (RTCC_HAS_SET_CLEAR) RTCC->IF_SET = flags; #else RTCC->IFS = flags; #endif } /***************************************************************************//** * @brief * Lock RTCC registers. * * @note * When RTCC registers are locked, RTCC_CTRL, RTCC_PRECNT, RTCC_CNT, * RTCC_TIME, RTCC_DATE, RTCC_IEN, RTCC_POWERDOWN and RTCC_CCx_XXX registers * cannot be written to. ******************************************************************************/ __STATIC_INLINE void RTCC_Lock(void) { #if defined(ERRATA_FIX_RTCC_E203) /* RTCC_E203 - Potential Stability Issue with RTCC Registers. * RTCC_LOCK register must be modified while RTCC clock is disabled. */ uint32_t lfeReg = CMU->LFECLKEN0; bool cmuLocked = (CMU->LOCK == CMU_LOCK_LOCKKEY_LOCKED); if (cmuLocked) { CMU->LOCK = CMU_LOCK_LOCKKEY_UNLOCK; } CMU->LFECLKEN0 = 0x0; #endif RTCC->LOCK = ~RTCC_LOCK_LOCKKEY_UNLOCK; #if defined(ERRATA_FIX_RTCC_E203) /* Restore clock state after RTCC_E203 fix. */ CMU->LFECLKEN0 = lfeReg; if (cmuLocked) { CMU->LOCK = CMU_LOCK_LOCKKEY_LOCK; } #endif } /***************************************************************************//** * @brief * Get RTCC pre-counter value. * * @return * Current RTCC pre-counter value. ******************************************************************************/ __STATIC_INLINE uint32_t RTCC_PreCounterGet(void) { #if defined (RTCC_SYNCBUSY_PRECNT) while ((RTCC->SYNCBUSY & RTCC_SYNCBUSY_PRECNT) != 0U) { /* Wait for PRECNT to synchronize */ } #endif return RTCC->PRECNT; } /***************************************************************************//** * @brief * Set RTCC pre-counter value. * * @param[in] preCntVal * RTCC pre-counter value to be set. ******************************************************************************/ __STATIC_INLINE void RTCC_PreCounterSet(uint32_t preCntVal) { #if defined (RTCC_SYNCBUSY_PRECNT) while ((RTCC->SYNCBUSY & RTCC_SYNCBUSY_PRECNT) != 0U) { /* Wait for PRECNT to synchronize */ } #endif RTCC->PRECNT = preCntVal; } void RTCC_Reset(void); #if defined (_RTCC_POWERDOWN_MASK) /***************************************************************************//** * @brief * Power down retention RAM. * * @note * Once retention RAM is powered down, it cannot be powered up again. ******************************************************************************/ __STATIC_INLINE void RTCC_RetentionRamPowerDown(void) { #if !defined(ERRATA_FIX_RTCC_E204) /* Devices that are affected by RTCC_E204 should always keep RTCC * backup RAM retained. */ RTCC->POWERDOWN = RTCC_POWERDOWN_RAM; #endif } #endif void RTCC_StatusClear(void); /***************************************************************************//** * @brief * Get STATUS register value. * * @return * Current STATUS register value. ******************************************************************************/ __STATIC_INLINE uint32_t RTCC_StatusGet(void) { #if defined (RTCC_SYNCBUSY_CMD) while ((RTCC->SYNCBUSY & RTCC_SYNCBUSY_CMD) != 0U) { // Wait for synchronization. } #elif defined (RTCC_SYNCBUSY_START) while ((RTCC->SYNCBUSY & (RTCC_SYNCBUSY_START | RTCC_SYNCBUSY_STOP)) != 0U) { /* Wait for synchronization. */ } #endif return RTCC->STATUS; } #if defined(_SILICON_LABS_32B_SERIES_2) /***************************************************************************//** * @brief * Wait for the RTCC to complete all synchronization of register changes * and commands. ******************************************************************************/ __STATIC_INLINE void RTCC_SyncWait(void) { while ((RTCC->EN != 0U) && (RTCC->SYNCBUSY != 0U)) { /* Wait for synchronization to finish */ } } /***************************************************************************//** * @brief * Start RTCC counter. * * @detail * This function will send a start command to the RTCC peripheral. The RTCC * peripheral will use some LF clock ticks before the command is executed. * The @ref RTCC_SyncWait() function can be used to wait for the start command * to be executed. * * @note * This function requires the RTCC to be enabled. ******************************************************************************/ __STATIC_INLINE void RTCC_Start(void) { RTCC_SyncWait(); RTCC->CMD = RTCC_CMD_START; } /***************************************************************************//** * @brief * Stop the RTCC counter. * * @detail * This function will send a stop command to the RTCC peripheral. The RTCC * peripheral will use some LF clock ticks before the command is executed. * The @ref RTCC_SyncWait() function can be used to wait for the stop command * to be executed. * * @note * This function requires the RTCC to be enabled. ******************************************************************************/ __STATIC_INLINE void RTCC_Stop(void) { RTCC_SyncWait(); RTCC->CMD = RTCC_CMD_STOP; } #endif #if defined (_RTCC_TIME_MASK) /***************************************************************************//** * @brief * Get TIME register value. * * @return * Current TIME register value. ******************************************************************************/ __STATIC_INLINE uint32_t RTCC_TimeGet(void) { return RTCC->TIME; } /***************************************************************************//** * @brief * Set RTCC TIME register. * * @param[in] time * TIME value. ******************************************************************************/ __STATIC_INLINE void RTCC_TimeSet(uint32_t time) { RTCC->TIME = time; } #endif /***************************************************************************//** * @brief * Unlock RTCC registers. * * @note * When RTCC registers are locked, RTCC_CTRL, RTCC_PRECNT, RTCC_CNT, * RTCC_TIME, RTCC_DATE, RTCC_IEN, RTCC_POWERDOWN and RTCC_CCx_XXX registers * cannot be written to. ******************************************************************************/ __STATIC_INLINE void RTCC_Unlock(void) { #if defined(ERRATA_FIX_RTCC_E203) /* RTCC_E203 - Potential Stability Issue with RTCC Registers. * RTCC_LOCK register must be modified while RTCC clock is disabled. */ uint32_t lfeReg = CMU->LFECLKEN0; bool cmuLocked = (CMU->LOCK == CMU_LOCK_LOCKKEY_LOCKED); if (cmuLocked) { CMU->LOCK = CMU_LOCK_LOCKKEY_UNLOCK; } CMU->LFECLKEN0 = 0x0; #endif RTCC->LOCK = RTCC_LOCK_LOCKKEY_UNLOCK; #if defined(ERRATA_FIX_RTCC_E203) /* Restore clock state after RTCC_E203 fix. */ CMU->LFECLKEN0 = lfeReg; if (cmuLocked) { CMU->LOCK = CMU_LOCK_LOCKKEY_LOCK; } #endif } /** @} (end addtogroup RTCC) */ /** @} (end addtogroup emlib) */ #ifdef __cplusplus } #endif #endif /* defined( RTCC_COUNT ) && ( RTC_COUNT == 1 ) */ #endif /* EM_RTCC_H */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/emlib/inc/em_se.h.
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/***************************************************************************//** * @file * @brief Secure Element API * @version 5.7.0 ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * SPDX-License-Identifier: Zlib * * The licensor of this software is Silicon Laboratories Inc. * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be * appreciated but is not required. * 2. Altered source versions must be plainly marked as such, and must not be * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * ******************************************************************************/ #ifndef EM_SE_H #define EM_SE_H #include "em_device.h" #if defined(SEMAILBOX_PRESENT) #include <stdint.h> #include <stdbool.h> #include <stddef.h> #ifdef __cplusplus extern "C" { #endif /***************************************************************************//** * @addtogroup emlib * @{ ******************************************************************************/ /***************************************************************************//** * @addtogroup SE * * @brief Secure Element peripheral API * * @details * Abstraction of the Secure Element's mailbox interface. * * @note Although commands to interact with the mailbox directly are * available, it is always recommended to use the higher level APIs available * in em_se and through mbedTLS. * * @{ ******************************************************************************/ /******************************************************************************* ****************************** DEFINES *********************************** ******************************************************************************/ /* Command words for the Secure Element. */ #if (defined(_SILICON_LABS_SECURITY_FEATURE) \ && (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_ADVANCED)) #define SE_COMMAND_WRAP_KEY 0x01000000UL #define SE_COMMAND_UNWRAP_KEY 0x01020000UL #define SE_COMMAND_TRANSFER_KEY 0x01060000UL #endif /* _SILICON_LABS_SECURITY_FEATURE_ADVANCED */ #define SE_COMMAND_CREATE_KEY 0x02000000UL #define SE_COMMAND_READPUB_KEY 0x02010000UL #if (defined(_SILICON_LABS_SECURITY_FEATURE) \ && (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_ADVANCED)) #define SE_COMMAND_DERIVE_KEY_PBKDF2 0x02020002UL #define SE_COMMAND_DERIVE_KEY_HKDF 0x02020003UL #endif /* _SILICON_LABS_SECURITY_FEATURE_ADVANCED */ #define SE_COMMAND_HASH 0x03000000UL #define SE_COMMAND_HASHUPDATE 0x03010000UL #define SE_COMMAND_HMAC 0x03020000UL #define SE_COMMAND_AES_ENCRYPT 0x04000000UL #define SE_COMMAND_AES_DECRYPT 0x04010000UL #define SE_COMMAND_AES_GCM_ENCRYPT 0x04020000UL #define SE_COMMAND_AES_GCM_DECRYPT 0x04030000UL #define SE_COMMAND_AES_CMAC 0x04040000UL #define SE_COMMAND_AES_CCM_ENCRYPT 0x04050000UL #define SE_COMMAND_AES_CCM_DECRYPT 0x04060000UL #define SE_COMMAND_SIGNATURE_SIGN 0x06000000UL #define SE_COMMAND_SIGNATURE_VERIFY 0x06010000UL #if (defined(_SILICON_LABS_SECURITY_FEATURE) \ && (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_ADVANCED)) #define SE_COMMAND_EDDSA_SIGN 0x06020000UL #define SE_COMMAND_EDDSA_VERIFY 0x06030000UL #endif /* _SILICON_LABS_SECURITY_FEATURE_ADVANCED */ #define SE_COMMAND_TRNG_GET_RANDOM 0x07000000UL #define SE_COMMAND_READ_CLOCK 0x07020000UL #if (defined(_SILICON_LABS_SECURITY_FEATURE) \ && (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_ADVANCED)) #define SE_COMMAND_ATTEST_CERTIFY 0x0A000000UL #define SE_COMMAND_ATTEST_TIME 0x0A010000UL #define SE_COMMAND_ATTEST_PUBKEY 0x0A020000UL #endif /* _SILICON_LABS_SECURITY_FEATURE_ADVANCED */ #define SE_COMMAND_JPAKE_R1_GENERATE 0x0B000000UL #define SE_COMMAND_JPAKE_R1_VERIFY 0x0B000100UL #define SE_COMMAND_JPAKE_R2_GENERATE 0x0B010000UL #define SE_COMMAND_JPAKE_R2_VERIFY 0x0B010100UL #define SE_COMMAND_JPAKE_GEN_SESSIONKEY 0x0B020000UL #if (defined(_SILICON_LABS_SECURITY_FEATURE) \ && (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_ADVANCED)) #define SE_COMMAND_AEAD_ENCRYPT 0x0C000000UL #define SE_COMMAND_AEAD_DECRYPT 0x0C010000UL #define SE_COMMAND_CHACHA20_ENCRYPT 0x0C020000UL #define SE_COMMAND_CHACHA20_DECRYPT 0x0C030000UL #define SE_COMMAND_POLY1305_KEY_MAC 0x0C040000UL #endif /* _SILICON_LABS_SECURITY_FEATURE_ADVANCED */ #define SE_COMMAND_DH 0x0E000000UL #define SE_COMMAND_CHECK_SE_IMAGE 0x43020000UL #define SE_COMMAND_APPLY_SE_IMAGE 0x43030000UL #define SE_COMMAND_STATUS_SE_IMAGE 0x43040000UL #define SE_COMMAND_CHECK_HOST_IMAGE 0x43050001UL #define SE_COMMAND_APPLY_HOST_IMAGE 0x43060001UL #define SE_COMMAND_STATUS_HOST_IMAGE 0x43070001UL #define SE_COMMAND_STATUS_SE_VERSION 0x43080000UL #define SE_COMMAND_STATUS_OTP_VERSION 0x43080100UL #define SE_COMMAND_WRITE_USER_DATA 0x43090000UL #define SE_COMMAND_ERASE_USER_DATA 0x430A0000UL #define SE_COMMAND_DBG_LOCK_APPLY 0x430C0000 #define SE_COMMAND_DBG_LOCK_ENABLE_SECURE 0x430D0000 #define SE_COMMAND_DBG_LOCK_DISABLE_SECURE 0x430E0000 #define SE_COMMAND_DEVICE_ERASE 0x430F0000 #define SE_COMMAND_DEVICE_ERASE_DISABLE 0x43100000 #define SE_COMMAND_DBG_LOCK_STATUS 0x43110000 #define SE_COMMAND_GET_CHALLENGE 0xFD000000UL #define SE_COMMAND_OPEN_DEBUG 0xFD010001UL #define SE_COMMAND_DISABLE_TAMPER 0xFD020001UL #define SE_COMMAND_READ_SERIAL 0xFE000000UL #define SE_COMMAND_GET_STATUS 0xFE010000UL #define SE_COMMAND_READ_PUBKEYBOOT 0xFE020001UL #define SE_COMMAND_SET_UPGRADEFLAG_SE 0xFE030000UL #define SE_COMMAND_SET_UPGRADEFLAG_HOST 0xFE030001UL #define SE_COMMAND_INIT_OTP 0xFF000001UL #define SE_COMMAND_INIT_PUBKEY 0xFF070001UL #define SE_COMMAND_READ_PUBKEY 0xFF080001UL #define SE_COMMAND_INIT_PUBKEY_SIGNATURE 0xFF090001UL #define SE_COMMAND_READ_PUBKEY_SIGNATURE 0xFF0A0001UL /* Command options for the Secure Element commands. */ /** Use MD5 as hash algorithm */ #define SE_COMMAND_OPTION_HASH_MD5 0x00000100UL /** Use SHA1 as hash algorithm */ #define SE_COMMAND_OPTION_HASH_SHA1 0x00000200UL /** Use SHA224 as hash algorithm */ #define SE_COMMAND_OPTION_HASH_SHA224 0x00000300UL /** Use SHA256 as hash algorithm */ #define SE_COMMAND_OPTION_HASH_SHA256 0x00000400UL #if (defined(_SILICON_LABS_SECURITY_FEATURE) \ && (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_ADVANCED)) /** Use SHA384 as hash algorithm */ #define SE_COMMAND_OPTION_HASH_SHA384 0x00000500UL /** Use SHA512 as hash algorithm */ #define SE_COMMAND_OPTION_HASH_SHA512 0x00000600UL #endif /* _SILICON_LABS_SECURITY_FEATURE_ADVANCED */ /** Execute algorithm in ECB mode */ #define SE_COMMAND_OPTION_MODE_ECB 0x00000100UL /** Execute algorithm in CBC mode */ #define SE_COMMAND_OPTION_MODE_CBC 0x00000200UL /** Execute algorithm in CTR mode */ #define SE_COMMAND_OPTION_MODE_CTR 0x00000300UL /** Execute algorithm in CFB mode */ #define SE_COMMAND_OPTION_MODE_CFB 0x00000400UL /** Execute algorithm in OFB mode */ #define SE_COMMAND_OPTION_MODE_OFB 0x00000500UL /** Execute algorithm in XTS mode */ #define SE_COMMAND_OPTION_MODE_XTS 0x00000800UL #define SE_COMMAND_OPTION_CERT_DEVICE 0x00000100UL #define SE_COMMAND_OPTION_CERT_BATCH 0x00000200UL #define SE_COMMAND_OPTION_CERT_FACTORY 0x00000300UL /** Pubkey types */ #define SE_KEY_TYPE_BOOT 0x00000100UL #define SE_KEY_TYPE_AUTH 0x00000200UL #define SE_KEY_TYPE_ROOT 0x00000300UL /** Run the whole algorithm, all data present */ #define SE_COMMAND_OPTION_CONTEXT_WHOLE 0x00000000UL /** Start the algorithm, but get a context to later add more data */ #define SE_COMMAND_OPTION_CONTEXT_START 0x00000001UL /** End the algorithm, get the result */ #define SE_COMMAND_OPTION_CONTEXT_END 0x00000002UL /** Add more data input to the algorithm. Need to supply previous context, * and get a context back */ #define SE_COMMAND_OPTION_CONTEXT_ADD 0x00000003UL /** Padding options for signature functionality. */ #define SE_COMMAND_OPTION_PADDING_NONE 0x00000000UL #define SE_COMMAND_OPTION_PADDING_EMSA_PKCS 0x00000003UL #define SE_COMMAND_OPTION_PADDING_PSS 0x00000004UL /* Special parameters for the Secure Element commands. */ /** Magic paramater for deleting user data */ #define SE_COMMAND_OPTION_ERASE_UD 0xDE1E7EADUL /* Response status codes for the Secure Element */ #define SE_RESPONSE_MASK 0x000F0000UL /** Command executed successfully or signature was successfully validated. */ #define SE_RESPONSE_OK 0x00000000UL /** * Command was not recognized as a valid command, or is not allowed in the * current context. */ #define SE_RESPONSE_INVALID_COMMAND 0x00010000UL /** * User did not provide the required credentials to be allowed to execute the * command. */ #define SE_RESPONSE_AUTHORIZATION_ERROR 0x00020000UL /** * Signature validation command (e.g. SE_COMMAND_SIGNATURE_VERIFY) failed to * verify the given signature as being correct. */ #define SE_RESPONSE_INVALID_SIGNATURE 0x00030000UL /** A command started in non-secure mode is trying to access secure memory. */ #define SE_RESPONSE_BUS_ERROR 0x00040000UL /** Internal error */ #define SE_RESPONSE_INTERNAL_ERROR 0x00050000UL /** An internal error was raised and the command did not execute. */ #define SE_RESPONSE_CRYPTO_ERROR 0x00060000UL /** One of the passed parameters is deemed invalid (e.g. out of bounds). */ #define SE_RESPONSE_INVALID_PARAMETER 0x00070000UL /* Abort status code is given when no operation is attempted. */ #define SE_RESPONSE_ABORT 0x00090000UL #define SE_DATATRANSFER_STOP 0x00000001UL #define SE_DATATRANSFER_DISCARD 0x40000000UL #define SE_DATATRANSFER_REALIGN 0x20000000UL #define SE_DATATRANSFER_CONSTADDRESS 0x10000000UL #define SE_DATATRANSFER_LENGTH_MASK 0x0FFFFFFFUL /** Maximum amount of parameters for largest command in defined command set */ #ifndef SE_MAX_PARAMETERS #define SE_MAX_PARAMETERS 4U #endif /** Maximum amount of parameters supported by the hardware FIFO */ #define SE_FIFO_MAX_PARAMETERS 13U /* Sanity-check defines */ #if SE_MAX_PARAMETERS > SE_FIFO_MAX_PARAMETERS #error "Trying to configure more parameters than supported by the hardware" #endif /******************************************************************************* ****************************** TYPEDEFS *********************************** ******************************************************************************/ /** * SE DMA transfer descriptor. Can be linked to each other to provide * scatter-gather behavior. */ typedef struct { volatile void* volatile data; void* volatile next; volatile uint32_t length; } SE_DataTransfer_t; /** Default initialization of data transfer struct */ #define SE_DATATRANSFER_DEFAULT(address, length) \ { \ (address), /* Pointer to data block */ \ (void*)SE_DATATRANSFER_STOP, /* This is the last block by default */ \ (length) | SE_DATATRANSFER_REALIGN /* Add size, use realign by default */ \ } /** * SE Command structure to which all commands to the SE must adhere. */ typedef struct { uint32_t command; SE_DataTransfer_t* data_in; SE_DataTransfer_t* data_out; uint32_t parameters[SE_MAX_PARAMETERS]; size_t num_parameters; } SE_Command_t; /** Default initialization of command struct */ #define SE_COMMAND_DEFAULT(command) \ { \ (command), /* Given command */ \ NULL, /* No data in */ \ NULL, /* No data out */ \ { 0, 0, 0, 0 }, /* No parameters */ \ 0 /* No parameters */ \ } /** Possible responses to a command */ typedef uint32_t SE_Response_t; typedef struct { /** Enable secure boot for the host. */ bool enableSecureBoot; /** Enable verification of the secure boot certificate. */ bool verifySecureBootCertificate; /** Enable anti-rollback for the host application. */ bool enableAntiRollback; } SE_OTPInit_t; typedef struct { /** Whether debug lock is enabled */ bool debugLockEnabled; /** Whether device erase is enabled */ bool deviceEraseEnabled; /** Whether secure debug is enabled */ bool secureDebugEnabled; } SE_DebugStatus_t; typedef struct { /** Boot status code / error code (Bits [7:0]). */ uint32_t bootStatus; /** SE firmware version. */ uint32_t seFwVersion; /** Host firmware version (if available). */ uint32_t hostFwVersion; /** Debug lock status. */ SE_DebugStatus_t debugStatus; /** Secure boot enabled. */ bool secureBootEnabled; } SE_Status_t; /******************************************************************************* ***************************** PROTOTYPES ********************************** ******************************************************************************/ void SE_addDataInput(SE_Command_t *command, SE_DataTransfer_t *data); void SE_addDataOutput(SE_Command_t *command, SE_DataTransfer_t *data); void SE_addParameter(SE_Command_t *command, uint32_t parameter); void SE_executeCommand(SE_Command_t *command); // User data commands SE_Response_t SE_writeUserData(uint32_t offset, void *data, uint32_t numBytes); SE_Response_t SE_eraseUserData(void); // Initialization commands SE_Response_t SE_readPubkey(uint32_t key_type, void *pubkey, uint32_t numBytes, bool signature); SE_Response_t SE_initPubkey(uint32_t key_type, void *pubkey, uint32_t numBytes, bool signature); SE_Response_t SE_initOTP(SE_OTPInit_t *otp_init); // Debug commands SE_Response_t SE_debugLockStatus(SE_DebugStatus_t *status); SE_Response_t SE_debugLockApply(); SE_Response_t SE_debugSecureEnable(); SE_Response_t SE_debugSecureDisable(); SE_Response_t SE_deviceEraseDisable(); SE_Response_t SE_deviceErase(); // Device status commands SE_Response_t SE_getStatus(SE_Status_t *output); SE_Response_t SE_serialNumber(void *serial); // Utilities __STATIC_INLINE bool SE_isCommandCompleted(void); __STATIC_INLINE void SE_waitCommandCompletion(void); __STATIC_INLINE SE_Response_t SE_readCommandResponse(void); __STATIC_INLINE void SE_disableInterrupt(uint32_t flags); __STATIC_INLINE void SE_enableInterrupt(uint32_t flags); /***************************************************************************//** * @brief * Check whether the running command has completed. * * @details * This function polls the SE-to-host mailbox interrupt flag. * * @return True if a command has completed and the result is available ******************************************************************************/ __STATIC_INLINE bool SE_isCommandCompleted(void) { return (bool)(SEMAILBOX_HOST->RX_STATUS & SEMAILBOX_RX_STATUS_RXINT); } /***************************************************************************//** * @brief * Wait for completion of the current command. * * @details * This function "busy"-waits until the execution of the ongoing instruction * has completed. ******************************************************************************/ __STATIC_INLINE void SE_waitCommandCompletion(void) { /* Wait for completion */ while (!SE_isCommandCompleted()) { } } /***************************************************************************//** * @brief * Read the status of the previously executed command. * * @details * This function reads the status of the previously executed command. * * @note * The command response needs to be read for every executed command, and can * only be read once per executed command (FIFO behavior). * * @return * One of the SE_RESPONSE return codes: * SE_RESPONSE_OK when the command was executed successfully or a signature * was successfully verified, * SE_RESPONSE_INVALID_COMMAND when the command ID was not recognized, * SE_RESPONSE_AUTHORIZATION_ERROR when the command is not authorized, * SE_RESPONSE_INVALID_SIGNATURE when signature verification failed, * SE_RESPONSE_BUS_ERROR when a bus error was thrown during the command, e.g. * because of conflicting Secure/Non-Secure memory accesses, * SE_RESPONSE_CRYPTO_ERROR on an internal SE failure, or * SE_RESPONSE_INVALID_PARAMETER when an invalid parameter was passed ******************************************************************************/ __STATIC_INLINE SE_Response_t SE_readCommandResponse(void) { SE_waitCommandCompletion(); return (SE_Response_t)(SEMAILBOX_HOST->RX_HEADER & SE_RESPONSE_MASK); } /***************************************************************************//** * @brief * Disable one or more SE interrupts. * * @param[in] flags * SE interrupt sources to disable. Use a bitwise logic OR combination of * valid interrupt flags for the Secure Element module * (SE_CONFIGURATION_(TX/RX)INTEN). ******************************************************************************/ __STATIC_INLINE void SE_disableInterrupt(uint32_t flags) { SEMAILBOX_HOST->CONFIGURATION &= ~flags; } /***************************************************************************//** * @brief * Enable one or more SE interrupts. * * @param[in] flags * SE interrupt sources to enable. Use a bitwise logic OR combination of * valid interrupt flags for the Secure Element module * (SEMAILBOX_CONFIGURATION_TXINTEN or SEMAILBOX_CONFIGURATION_RXINTEN). ******************************************************************************/ __STATIC_INLINE void SE_enableInterrupt(uint32_t flags) { SEMAILBOX_HOST->CONFIGURATION |= flags; } #ifdef __cplusplus } #endif /** @} (end addtogroup SE) */ /** @} (end addtogroup emlib) */ #endif /* defined(SEMAILBOX_PRESENT) */ #endif /* EM_SE_H */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/emlib/inc/em_system.h.
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/***************************************************************************//** * @file * @brief System API * @version 5.7.0 ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * SPDX-License-Identifier: Zlib * * The licensor of this software is Silicon Laboratories Inc. * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be * appreciated but is not required. * 2. Altered source versions must be plainly marked as such, and must not be * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * ******************************************************************************/ #ifndef EM_SYSTEM_H #define EM_SYSTEM_H #include <stdbool.h> #include "em_device.h" #ifdef __cplusplus extern "C" { #endif /***************************************************************************//** * @addtogroup emlib * @{ ******************************************************************************/ /***************************************************************************//** * @addtogroup SYSTEM * @brief System API * @details * This module contains functions to read information such as RAM and Flash size, * device unique ID, chip revision, family, and part number from @ref DEVINFO and * @ref SCB blocks. Functions to configure and read status from FPU are available for * compatible devices. * @{ ******************************************************************************/ /******************************************************************************* ******************************** ENUMS ************************************ ******************************************************************************/ /** Family identifiers. */ typedef enum { /* New style family #defines */ #if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32G) systemPartFamilyEfm32Gecko = _DEVINFO_PART_DEVICE_FAMILY_EFM32G, /**< EFM32 Gecko Device Family. */ #endif #if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32GG) systemPartFamilyEfm32Giant = _DEVINFO_PART_DEVICE_FAMILY_EFM32GG, /**< EFM32 Giant Gecko Series 0 Device Family. */ #endif #if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32GG11B) systemPartFamilyEfm32Giant11B = _DEVINFO_PART_DEVICE_FAMILY_EFM32GG11B, /**< EFM32 Giant Gecko Series 1 Configuration 1 Basic Device Family. */ #endif #if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32GG12B) systemPartFamilyEfm32Giant12B = _DEVINFO_PART_DEVICE_FAMILY_EFM32GG12B, /**< EFM32 Giant Gecko Series 1 Configuration 2 Basic Device Family. */ #endif #if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32TG) systemPartFamilyEfm32Tiny = _DEVINFO_PART_DEVICE_FAMILY_EFM32TG, /**< EFM32 Tiny Gecko Device Family. */ #endif #if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32TG11B) systemPartFamilyEfm32Tiny11B = _DEVINFO_PART_DEVICE_FAMILY_EFM32TG11B, /**< EFM32 Tiny Gecko 11 Device Family. */ #endif #if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32LG) systemPartFamilyEfm32Leopard = _DEVINFO_PART_DEVICE_FAMILY_EFM32LG, /**< EFM32 Leopard Gecko Device Family. */ #endif #if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32WG) systemPartFamilyEfm32Wonder = _DEVINFO_PART_DEVICE_FAMILY_EFM32WG, /**< EFM32 Wonder Gecko Device Family. */ #endif #if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32ZG) systemPartFamilyEfm32Zero = _DEVINFO_PART_DEVICE_FAMILY_EFM32ZG, /**< EFM32 Zero Gecko Device Family. */ #endif #if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32HG) systemPartFamilyEfm32Happy = _DEVINFO_PART_DEVICE_FAMILY_EFM32HG, /**< EFM32 Happy Gecko Device Family. */ #endif #if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32PG1B) systemPartFamilyEfm32Pearl1B = _DEVINFO_PART_DEVICE_FAMILY_EFM32PG1B, /**< EFM32 Pearl Gecko Series 1 Configuration 1 Basic Device Family. */ #endif #if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B) systemPartFamilyEfm32Jade1B = _DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B, /**< EFM32 Jade Gecko Series 1 Configuration 1 Basic Device Family. */ #endif #if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32PG12B) systemPartFamilyEfm32Pearl12B = _DEVINFO_PART_DEVICE_FAMILY_EFM32PG12B, /**< EFM32 Pearl Gecko Series 1 Configuration 2 Basic Device Family. */ #endif #if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32JG12B) systemPartFamilyEfm32Jade12B = _DEVINFO_PART_DEVICE_FAMILY_EFM32JG12B, /**< EFM32 Jade Gecko Series 1 Configuration 2 Basic Device Family. */ #endif #if defined(_DEVINFO_PART_DEVICE_FAMILY_EZR32WG) systemPartFamilyEzr32Wonder = _DEVINFO_PART_DEVICE_FAMILY_EZR32WG, /**< EZR32 Wonder Device Family. */ #endif #if defined(_DEVINFO_PART_DEVICE_FAMILY_EZR32LG) systemPartFamilyEzr32Leopard = _DEVINFO_PART_DEVICE_FAMILY_EZR32LG, /**< EZR32 Leopard Device Family. */ #endif #if defined(_DEVINFO_PART_DEVICE_FAMILY_EZR32HG) systemPartFamilyEzr32Happy = _DEVINFO_PART_DEVICE_FAMILY_EZR32HG, /**< EZR32 Happy Device Family. */ #endif #if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG1P) systemPartFamilyMighty1P = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1P, /**< EFR32 Mighty Gecko Series 1 Configuration 1 Premium Device Family. */ #endif #if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG1B) systemPartFamilyMighty1B = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1B, /**< EFR32 Mighty Gecko Series 1 Configuration 1 Basic Device Family. */ #endif #if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG1V) systemPartFamilyMighty1V = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1V, /**< EFR32 Mighty Gecko Series 1 Configuration 1 Value Device Family. */ #endif #if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32BG1P) systemPartFamilyBlue1P = _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1P, /**< EFR32 Blue Gecko Series 1 Configuration 1 Premium Device Family. */ #endif #if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32BG1B) systemPartFamilyBlue1B = _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1B, /**< EFR32 Blue Gecko Series 1 Configuration 1 Basic Device Family. */ #endif #if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32BG1V) systemPartFamilyBlue1V = _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1V, /**< EFR32 Blue Gecko Series 1 Configuration 1 Value Device Family. */ #endif #if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG1P) systemPartFamilyFlex1P = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1P, /**< EFR32 Flex Gecko Series 1 Configuration 1 Premium Device Family. */ #endif #if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG1B) systemPartFamilyFlex1B = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1B, /**< EFR32 Flex Gecko Series 1 Configuration 1 Basic Device Family. */ #endif #if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG1V) systemPartFamilyFlex1V = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1V, /**< EFR32 Flex Gecko Series 1 Configuration 1 Value Device Family. */ #endif #if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG2P) systemPartFamilyMighty2P = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG2P, /**< EFR32 Mighty Gecko Series 1 Configuration 2 Premium Device Family. */ #endif #if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG12P) systemPartFamilyMighty12P = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG12P, /**< EFR32 Mighty Gecko Series 1 Configuration 2 Premium Device Family. */ #endif #if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG12B) systemPartFamilyMighty12B = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG12B, /**< EFR32 Mighty Gecko Series 1 Configuration 2 Basic Device Family. */ #endif #if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG12V) systemPartFamilyMighty12V = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG12V, /**< EFR32 Mighty Gecko Series 1 Configuration 2 Value Device Family. */ #endif #if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32BG12P) systemPartFamilyBlue12P = _DEVINFO_PART_DEVICE_FAMILY_EFR32BG12P, /**< EFR32 Blue Gecko Series 1 Configuration 2 Premium Device Family. */ #endif #if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32BG12B) systemPartFamilyBlue12B = _DEVINFO_PART_DEVICE_FAMILY_EFR32BG12B, /**< EFR32 Blue Gecko Series 1 Configuration 2 Basic Device Family. */ #endif #if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32BG12V) systemPartFamilyBlue12V = _DEVINFO_PART_DEVICE_FAMILY_EFR32BG12V, /**< EFR32 Blue Gecko Series 1 Configuration 2 Value Device Family. */ #endif #if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG12P) systemPartFamilyFlex12P = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG12P, /**< EFR32 Flex Gecko Series 1 Configuration 2 Premium Device Family. */ #endif #if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG12B) systemPartFamilyFlex12B = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG12B, /**< EFR32 Flex Gecko Series 1 Configuration 2 Basic Device Family. */ #endif #if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG12V) systemPartFamilyFlex12V = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG12V, /**< EFR32 Flex Gecko Series 1 Configuration 2 Value Device Family. */ #endif #if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG13P) systemPartFamilyMighty13P = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG13P, /**< EFR32 Mighty Gecko Series 1 Configuration 3 Premium Device Family. */ #endif #if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG13B) systemPartFamilyMighty13B = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG13B, /**< EFR32 Mighty Gecko Series 1 Configuration 3 Basic Device Family. */ #endif #if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG13V) systemPartFamilyMighty13V = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG13V, /**< EFR32 Mighty Gecko Series 1 Configuration 3 Value Device Family. */ #endif #if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32BG13P) systemPartFamilyBlue13P = _DEVINFO_PART_DEVICE_FAMILY_EFR32BG13P, /**< EFR32 Blue Gecko Series 1 Configuration 3 Premium Device Family. */ #endif #if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32BG13B) systemPartFamilyBlue13B = _DEVINFO_PART_DEVICE_FAMILY_EFR32BG13B, /**< EFR32 Blue Gecko Series 1 Configuration 3 Basic Device Family. */ #endif #if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32BG13V) systemPartFamilyBlue13V = _DEVINFO_PART_DEVICE_FAMILY_EFR32BG13V, /**< EFR32 Blue Gecko Series 1 Configuration 3 Value Device Family. */ #endif #if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG13P) systemPartFamilyFlex13P = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG13P, /**< EFR32 Flex Gecko Series 1 Configuration 3 Premium Device Family. */ #endif #if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG13B) systemPartFamilyFlex13B = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG13B, /**< EFR32 Flex Gecko Series 1 Configuration 3 Basic Device Family. */ #endif #if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG13V) systemPartFamilyFlex13V = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG13V, /**< EFR32 Flex Gecko Series 1 Configuration 3 Value Device Family. */ #endif #if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32ZG13P) systemPartFamilyZen13P = _DEVINFO_PART_DEVICE_FAMILY_EFR32ZG13P, /**< EFR32 Zen Gecko Series 1 Configuration 3 Premium Device Family. */ #endif #if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG14P) systemPartFamilyMighty14P = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG14P, /**< EFR32 Mighty Gecko Series 1 Configuration 4 Premium Device Family. */ #endif #if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG14B) systemPartFamilyMighty14B = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG14B, /**< EFR32 Mighty Gecko Series 1 Configuration 4 Basic Device Family. */ #endif #if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG14V) systemPartFamilyMighty14V = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG14V, /**< EFR32 Mighty Gecko Series 1 Configuration 4 Value Device Family. */ #endif #if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32BG14P) systemPartFamilyBlue14P = _DEVINFO_PART_DEVICE_FAMILY_EFR32BG14P, /**< EFR32 Blue Gecko Series 1 Configuration 4 Premium Device Family. */ #endif #if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32BG14B) systemPartFamilyBlue14B = _DEVINFO_PART_DEVICE_FAMILY_EFR32BG14B, /**< EFR32 Blue Gecko Series 1 Configuration 4 Basic Device Family. */ #endif #if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32BG14V) systemPartFamilyBlue14V = _DEVINFO_PART_DEVICE_FAMILY_EFR32BG14V, /**< EFR32 Blue Gecko Series 1 Configuration 4 Value Device Family. */ #endif #if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG14P) systemPartFamilyFlex14P = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG14P, /**< EFR32 Flex Gecko Series 1 Configuration 4 Premium Device Family. */ #endif #if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG14B) systemPartFamilyFlex14B = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG14B, /**< EFR32 Flex Gecko Series 1 Configuration 4 Basic Device Family. */ #endif #if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG14V) systemPartFamilyFlex14V = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG14V, /**< EFR32 Flex Gecko Series 1 Configuration 4 Value Device Family. */ #endif #if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32ZG14P) systemPartFamilyZen14P = _DEVINFO_PART_DEVICE_FAMILY_EFR32ZG14P, /**< EFR32 Zen Gecko Series 1 Configuration 4 Premium Device Family. */ #endif #if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) systemPartFamilyMighty21 = DEVINFO_PART_FAMILY_MG | (21 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFR32 Mighty Gecko Series 2 Config 1 Value Device Family */ systemPartFamilyFlex21 = DEVINFO_PART_FAMILY_FG | (21 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFR32 Flex Gecko Series 2 Config 1 Value Device Family */ systemPartFamilyBlue21 = DEVINFO_PART_FAMILY_BG | (21 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFR32 Blue Gecko Series 2 Config 1 Value Device Family */ #endif /* Deprecated family #defines */ #if defined(_DEVINFO_PART_DEVICE_FAMILY_G) systemPartFamilyGecko = _DEVINFO_PART_DEVICE_FAMILY_G, /**< Gecko Device Family. */ #endif #if defined(_DEVINFO_PART_DEVICE_FAMILY_GG) systemPartFamilyGiant = _DEVINFO_PART_DEVICE_FAMILY_GG, /**< Giant Gecko Device Family. */ #endif #if defined(_DEVINFO_PART_DEVICE_FAMILY_TG) systemPartFamilyTiny = _DEVINFO_PART_DEVICE_FAMILY_TG, /**< Tiny Gecko Device Family. */ #endif #if defined(_DEVINFO_PART_DEVICE_FAMILY_LG) systemPartFamilyLeopard = _DEVINFO_PART_DEVICE_FAMILY_LG, /**< Leopard Gecko Device Family. */ #endif #if defined(_DEVINFO_PART_DEVICE_FAMILY_WG) systemPartFamilyWonder = _DEVINFO_PART_DEVICE_FAMILY_WG, /**< Wonder Gecko Device Family. */ #endif #if defined(_DEVINFO_PART_DEVICE_FAMILY_ZG) systemPartFamilyZero = _DEVINFO_PART_DEVICE_FAMILY_ZG, /**< Zero Gecko Device Family. */ #endif #if defined(_DEVINFO_PART_DEVICE_FAMILY_HG) systemPartFamilyHappy = _DEVINFO_PART_DEVICE_FAMILY_HG, /**< Happy Gecko Device Family. */ #endif systemPartFamilyUnknown = 0xFF /**< Unknown Device Family. Family ID is missing on unprogrammed parts. */ } SYSTEM_PartFamily_TypeDef; /******************************************************************************* ******************************* STRUCTS *********************************** ******************************************************************************/ /** Chip revision details. */ typedef struct { uint8_t minor; /**< Minor revision number. */ uint8_t major; /**< Major revision number. */ uint8_t family;/**< Device family number. */ } SYSTEM_ChipRevision_TypeDef; #if defined(__FPU_PRESENT) && (__FPU_PRESENT == 1) /** Floating point co-processor access modes. */ typedef enum { fpuAccessDenied = (0x0 << 20), /**< Access denied, any attempted access generates a NOCP UsageFault. */ fpuAccessPrivilegedOnly = (0x5 << 20), /**< Privileged access only, an unprivileged access generates a NOCP UsageFault. */ fpuAccessReserved = (0xA << 20), /**< Reserved. */ fpuAccessFull = (0xF << 20) /**< Full access. */ } SYSTEM_FpuAccess_TypeDef; #endif /** DEVINFO calibration address/value pair. */ typedef struct { uint32_t address; /**< Peripheral calibration register address. */ uint32_t calValue; /**< Calibration value for register at address. */ } SYSTEM_CalAddrVal_TypeDef; /******************************************************************************* ***************************** PROTOTYPES ********************************** ******************************************************************************/ void SYSTEM_ChipRevisionGet(SYSTEM_ChipRevision_TypeDef *rev); bool SYSTEM_GetCalibrationValue(volatile uint32_t *regAddress); #if defined(_DEVINFO_DEVINFOREV_DEVINFOREV_MASK) || defined(_DEVINFO_INFO_DEVINFOREV_MASK) /***************************************************************************//** * @brief * Get DEVINFO revision. * * @return * Revision of the DEVINFO contents. ******************************************************************************/ __STATIC_INLINE uint8_t SYSTEM_GetDevinfoRev(void) { #if defined(_DEVINFO_DEVINFOREV_DEVINFOREV_MASK) return (uint8_t)((DEVINFO->DEVINFOREV & _DEVINFO_DEVINFOREV_DEVINFOREV_MASK) >> _DEVINFO_DEVINFOREV_DEVINFOREV_SHIFT); #elif defined(_DEVINFO_INFO_DEVINFOREV_MASK) return (uint8_t)((DEVINFO->INFO & _DEVINFO_INFO_DEVINFOREV_MASK) >> _DEVINFO_INFO_DEVINFOREV_SHIFT); #endif } #endif #if defined(__FPU_PRESENT) && (__FPU_PRESENT == 1) /***************************************************************************//** * @brief * Set floating point co-processor (FPU) access mode. * * @param[in] accessMode * Floating point co-processor access mode. See @ref SYSTEM_FpuAccess_TypeDef * for details. ******************************************************************************/ __STATIC_INLINE void SYSTEM_FpuAccessModeSet(SYSTEM_FpuAccess_TypeDef accessMode) { SCB->CPACR = (SCB->CPACR & ~(0xFUL << 20)) | (uint32_t)accessMode; } #endif /***************************************************************************//** * @brief * Get unique number for this device. * * @return * Unique number for this device. ******************************************************************************/ __STATIC_INLINE uint64_t SYSTEM_GetUnique(void) { #if defined (_DEVINFO_EUI64H_MASK) uint32_t tmp = DEVINFO->EUI64L; return (uint64_t)((uint64_t)DEVINFO->EUI64H << 32) | tmp; #elif defined(_DEVINFO_UNIQUEH_MASK) uint32_t tmp = DEVINFO->UNIQUEL; return (uint64_t)((uint64_t)DEVINFO->UNIQUEH << 32) | tmp; #else #error Location of device unique number is not defined. #endif } /***************************************************************************//** * @brief * Get production revision for this part. * * @return * Production revision for this part. ******************************************************************************/ __STATIC_INLINE uint8_t SYSTEM_GetProdRev(void) { #if defined (_DEVINFO_PART_PROD_REV_MASK) return (uint8_t)((DEVINFO->PART & _DEVINFO_PART_PROD_REV_MASK) >> _DEVINFO_PART_PROD_REV_SHIFT); #elif defined (_DEVINFO_INFO_PRODREV_MASK) return (uint8_t)((DEVINFO->INFO & _DEVINFO_INFO_PRODREV_MASK) >> _DEVINFO_INFO_PRODREV_SHIFT); #else #error Location of production revision is not defined. #endif } /***************************************************************************//** * @brief * Get SRAM size (in KB). * * @note * This function retrieves SRAM size by reading the chip device * info structure. If your binary is made for one specific device only, * use @ref SRAM_SIZE instead. * * @return * Size of internal SRAM (in KB). ******************************************************************************/ __STATIC_INLINE uint16_t SYSTEM_GetSRAMSize(void) { uint16_t sizekb; #if defined(_EFM32_GECKO_FAMILY) /* Early Gecko devices had a bug where SRAM and Flash size were swapped. */ if (SYSTEM_GetProdRev() < 5) { sizekb = (DEVINFO->MSIZE & _DEVINFO_MSIZE_FLASH_MASK) >> _DEVINFO_MSIZE_FLASH_SHIFT; } #endif sizekb = (uint16_t)((DEVINFO->MSIZE & _DEVINFO_MSIZE_SRAM_MASK) >> _DEVINFO_MSIZE_SRAM_SHIFT); #if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) && defined(_EFR_DEVICE) /* Do not include EFR32xG1 RAMH. */ sizekb--; #endif return sizekb; } /***************************************************************************//** * @brief * Get the flash size (in KB). * * @note * This function retrieves flash size by reading the chip device * info structure. If your binary is made for one specific device only, * use @ref FLASH_SIZE instead. * * @return * Size of internal flash (in KB). ******************************************************************************/ __STATIC_INLINE uint16_t SYSTEM_GetFlashSize(void) { #if defined(_EFM32_GECKO_FAMILY) /* Early Gecko devices had a bug where SRAM and Flash size were swapped. */ if (SYSTEM_GetProdRev() < 5) { return (DEVINFO->MSIZE & _DEVINFO_MSIZE_SRAM_MASK) >> _DEVINFO_MSIZE_SRAM_SHIFT; } #endif return (uint16_t)((DEVINFO->MSIZE & _DEVINFO_MSIZE_FLASH_MASK) >> _DEVINFO_MSIZE_FLASH_SHIFT); } /***************************************************************************//** * @brief * Get the flash page size in bytes. * * @note * This function retrieves flash page size by reading the chip device * info structure. If your binary is made for one specific device only, * use @ref FLASH_PAGE_SIZE instead. * * @return * Page size of internal flash in bytes. ******************************************************************************/ __STATIC_INLINE uint32_t SYSTEM_GetFlashPageSize(void) { uint32_t tmp; #if defined(_SILICON_LABS_32B_SERIES_0) #if defined(_EFM32_GIANT_FAMILY) if (SYSTEM_GetProdRev() < 18) { /* Early Giant/Leopard devices did not have MEMINFO in DEVINFO. */ return FLASH_PAGE_SIZE; } #elif defined(_EFM32_ZERO_FAMILY) if (SYSTEM_GetProdRev() < 24) { /* Early Zero devices have an incorrect DEVINFO flash page size */ return FLASH_PAGE_SIZE; } #endif #endif #if defined(_DEVINFO_MEMINFO_FLASHPAGESIZE_MASK) tmp = (DEVINFO->MEMINFO & _DEVINFO_MEMINFO_FLASHPAGESIZE_MASK) >> _DEVINFO_MEMINFO_FLASHPAGESIZE_SHIFT; #elif defined(_DEVINFO_MEMINFO_FLASH_PAGE_SIZE_MASK) tmp = (DEVINFO->MEMINFO & _DEVINFO_MEMINFO_FLASH_PAGE_SIZE_MASK) >> _DEVINFO_MEMINFO_FLASH_PAGE_SIZE_SHIFT; #else #error Location of flash page size is not defined. #endif return 1UL << ((tmp + 10UL) & 0x1FUL); } /***************************************************************************//** * @brief * Get part number of MCU. * * @return * The part number of MCU. ******************************************************************************/ __STATIC_INLINE uint16_t SYSTEM_GetPartNumber(void) { #if defined(_DEVINFO_PART_DEVICENUM_MASK) return (uint16_t)((DEVINFO->PART & _DEVINFO_PART_DEVICENUM_MASK) >> _DEVINFO_PART_DEVICENUM_SHIFT); #elif defined(_DEVINFO_PART_DEVICE_NUMBER_MASK) return (uint16_t)((DEVINFO->PART & _DEVINFO_PART_DEVICE_NUMBER_MASK) >> _DEVINFO_PART_DEVICE_NUMBER_SHIFT); #else #error Location of device part number is not defined. #endif } /***************************************************************************//** * @brief * Get family identifier of MCU. * * @note * This function retrieves family ID by reading the chip's device info * structure in flash memory. Users can retrieve family ID directly * by reading DEVINFO->PART item and decode with mask and shift * \#defines defined in \<part_family\>_devinfo.h (refer to code * below for details). * * @return * Family identifier of MCU. ******************************************************************************/ __STATIC_INLINE SYSTEM_PartFamily_TypeDef SYSTEM_GetFamily(void) { #if defined(_SYSCFG_CHIPREV_FAMILY_MASK) return (SYSTEM_PartFamily_TypeDef) ((uint32_t)((DEVINFO->PART & (_DEVINFO_PART_FAMILY_MASK | _DEVINFO_PART_FAMILYNUM_MASK)))); #elif defined(_DEVINFO_PART_DEVICE_FAMILY_MASK) return (SYSTEM_PartFamily_TypeDef) ((uint32_t)((DEVINFO->PART & _DEVINFO_PART_DEVICE_FAMILY_MASK) >> _DEVINFO_PART_DEVICE_FAMILY_SHIFT)); #else #error Location of device family name is not defined. #endif } /***************************************************************************//** * @brief * Get calibration temperature (in degrees Celsius). * * @return * Calibration temperature in Celsius. ******************************************************************************/ __STATIC_INLINE uint8_t SYSTEM_GetCalibrationTemperature(void) { #if defined(_DEVINFO_CAL_TEMP_MASK) return (uint8_t)((DEVINFO->CAL & _DEVINFO_CAL_TEMP_MASK) >> _DEVINFO_CAL_TEMP_SHIFT); #elif defined(_DEVINFO_CALTEMP_TEMP_MASK) return (uint8_t)((DEVINFO->CALTEMP & _DEVINFO_CALTEMP_TEMP_MASK) >> _DEVINFO_CALTEMP_TEMP_SHIFT); #else #error Location of calibration temperature is not defined. #endif } /** @} (end addtogroup SYSTEM) */ /** @} (end addtogroup emlib) */ #ifdef __cplusplus } #endif #endif /* EM_SYSTEM_H */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/emlib/inc/em_timer.h.
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/***************************************************************************//** * @file * @brief Timer/counter (TIMER) peripheral API * @version 5.7.0 ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * SPDX-License-Identifier: Zlib * * The licensor of this software is Silicon Laboratories Inc. * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be * appreciated but is not required. * 2. Altered source versions must be plainly marked as such, and must not be * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * ******************************************************************************/ #ifndef EM_TIMER_H #define EM_TIMER_H #include "em_device.h" #if defined(TIMER_COUNT) && (TIMER_COUNT > 0) #include <stdbool.h> #include "em_assert.h" #ifdef __cplusplus extern "C" { #endif /***************************************************************************//** * @addtogroup emlib * @{ ******************************************************************************/ /***************************************************************************//** * @addtogroup TIMER * @{ ******************************************************************************/ /******************************************************************************* ******************************* DEFINES *********************************** ******************************************************************************/ /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ /** Validation of TIMER register block pointer reference for assert statements. */ #define TIMER_REF_VALID(ref) TIMER_Valid(ref) /** Validation of TIMER compare/capture channel number. */ #if defined(_SILICON_LABS_32B_SERIES_0) #define TIMER_CH_VALID(ch) ((ch) < 3) #elif defined(_SILICON_LABS_32B_SERIES_1) #define TIMER_CH_VALID(ch) ((ch) < 4) #elif defined(_SILICON_LABS_32B_SERIES_2) #define TIMER_CH_VALID(ch) ((ch) < 3) #else #error "Unknown device. Undefined number of channels." #endif /** @endcond */ /******************************************************************************* ******************************** ENUMS ************************************ ******************************************************************************/ /** Timer compare/capture mode. */ typedef enum { #if defined (_TIMER_CC_CTRL_MODE_MASK) timerCCModeOff = _TIMER_CC_CTRL_MODE_OFF, /**< Channel turned off. */ timerCCModeCapture = _TIMER_CC_CTRL_MODE_INPUTCAPTURE, /**< Input capture. */ timerCCModeCompare = _TIMER_CC_CTRL_MODE_OUTPUTCOMPARE, /**< Output compare. */ timerCCModePWM = _TIMER_CC_CTRL_MODE_PWM /**< Pulse-Width modulation. */ #endif #if defined (_TIMER_CC_CFG_MODE_MASK) timerCCModeOff = _TIMER_CC_CFG_MODE_OFF, /**< Channel turned off. */ timerCCModeCapture = _TIMER_CC_CFG_MODE_INPUTCAPTURE, /**< Input capture. */ timerCCModeCompare = _TIMER_CC_CFG_MODE_OUTPUTCOMPARE, /**< Output compare. */ timerCCModePWM = _TIMER_CC_CFG_MODE_PWM /**< Pulse-Width modulation. */ #endif } TIMER_CCMode_TypeDef; /** Clock select. */ typedef enum { #if defined (_TIMER_CTRL_CLKSEL_MASK) timerClkSelHFPerClk = _TIMER_CTRL_CLKSEL_PRESCHFPERCLK, /**< Prescaled HFPER / HFPERB clock. */ timerClkSelCC1 = _TIMER_CTRL_CLKSEL_CC1, /**< Compare/Capture Channel 1 Input. */ timerClkSelCascade = _TIMER_CTRL_CLKSEL_TIMEROUF /**< Cascaded clocked by underflow or overflow by lower numbered timer. */ #endif #if defined (_TIMER_CFG_CLKSEL_MASK) timerClkSelHFPerClk = _TIMER_CFG_CLKSEL_PRESCEM01GRPACLK, /**< Prescaled EM01GRPA clock. */ timerClkSelCC1 = _TIMER_CFG_CLKSEL_CC1, /**< Compare/Capture Channel 1 Input. */ timerClkSelCascade = _TIMER_CFG_CLKSEL_TIMEROUF /**< Cascaded clocked by underflow or overflow by lower numbered timer. */ #endif } TIMER_ClkSel_TypeDef; /** Input capture edge select. */ typedef enum { /** Rising edges detected. */ timerEdgeRising = _TIMER_CC_CTRL_ICEDGE_RISING, /** Falling edges detected. */ timerEdgeFalling = _TIMER_CC_CTRL_ICEDGE_FALLING, /** Both edges detected. */ timerEdgeBoth = _TIMER_CC_CTRL_ICEDGE_BOTH, /** No edge detection, leave signal as is. */ timerEdgeNone = _TIMER_CC_CTRL_ICEDGE_NONE } TIMER_Edge_TypeDef; /** Input capture event control. */ typedef enum { /** PRS output pulse, interrupt flag, and DMA request set on every capture. */ timerEventEveryEdge = _TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE, /** PRS output pulse, interrupt flag, and DMA request set on every second capture. */ timerEventEvery2ndEdge = _TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE, /** * PRS output pulse, interrupt flag, and DMA request set on rising edge (if * input capture edge = BOTH). */ timerEventRising = _TIMER_CC_CTRL_ICEVCTRL_RISING, /** * PRS output pulse, interrupt flag, and DMA request set on falling edge (if * input capture edge = BOTH). */ timerEventFalling = _TIMER_CC_CTRL_ICEVCTRL_FALLING } TIMER_Event_TypeDef; /** Input edge action. */ typedef enum { /** No action taken. */ timerInputActionNone = _TIMER_CTRL_FALLA_NONE, /** Start counter without reload. */ timerInputActionStart = _TIMER_CTRL_FALLA_START, /** Stop counter without reload. */ timerInputActionStop = _TIMER_CTRL_FALLA_STOP, /** Reload and start counter. */ timerInputActionReloadStart = _TIMER_CTRL_FALLA_RELOADSTART } TIMER_InputAction_TypeDef; /** Timer mode. */ typedef enum { #if defined (_TIMER_CTRL_MODE_MASK) timerModeUp = _TIMER_CTRL_MODE_UP, /**< Up-counting. */ timerModeDown = _TIMER_CTRL_MODE_DOWN, /**< Down-counting. */ timerModeUpDown = _TIMER_CTRL_MODE_UPDOWN, /**< Up/down-counting. */ timerModeQDec = _TIMER_CTRL_MODE_QDEC /**< Quadrature decoder. */ #endif #if defined (_TIMER_CFG_MODE_MASK) timerModeUp = _TIMER_CFG_MODE_UP, /**< Up-counting. */ timerModeDown = _TIMER_CFG_MODE_DOWN, /**< Down-counting. */ timerModeUpDown = _TIMER_CFG_MODE_UPDOWN, /**< Up/down-counting. */ timerModeQDec = _TIMER_CFG_MODE_QDEC /**< Quadrature decoder. */ #endif } TIMER_Mode_TypeDef; /** Compare/capture output action. */ typedef enum { /** No action. */ timerOutputActionNone = _TIMER_CC_CTRL_CUFOA_NONE, /** Toggle on event. */ timerOutputActionToggle = _TIMER_CC_CTRL_CUFOA_TOGGLE, /** Clear on event. */ timerOutputActionClear = _TIMER_CC_CTRL_CUFOA_CLEAR, /** Set on event. */ timerOutputActionSet = _TIMER_CC_CTRL_CUFOA_SET } TIMER_OutputAction_TypeDef; /** Prescaler. */ typedef enum { #if defined (_TIMER_CTRL_PRESC_MASK) timerPrescale1 = _TIMER_CTRL_PRESC_DIV1, /**< Divide by 1. */ timerPrescale2 = _TIMER_CTRL_PRESC_DIV2, /**< Divide by 2. */ timerPrescale4 = _TIMER_CTRL_PRESC_DIV4, /**< Divide by 4. */ timerPrescale8 = _TIMER_CTRL_PRESC_DIV8, /**< Divide by 8. */ timerPrescale16 = _TIMER_CTRL_PRESC_DIV16, /**< Divide by 16. */ timerPrescale32 = _TIMER_CTRL_PRESC_DIV32, /**< Divide by 32. */ timerPrescale64 = _TIMER_CTRL_PRESC_DIV64, /**< Divide by 64. */ timerPrescale128 = _TIMER_CTRL_PRESC_DIV128, /**< Divide by 128. */ timerPrescale256 = _TIMER_CTRL_PRESC_DIV256, /**< Divide by 256. */ timerPrescale512 = _TIMER_CTRL_PRESC_DIV512, /**< Divide by 512. */ timerPrescale1024 = _TIMER_CTRL_PRESC_DIV1024 /**< Divide by 1024. */ #endif #if defined (_TIMER_CFG_PRESC_MASK) timerPrescale1 = _TIMER_CFG_PRESC_DIV1, /**< Divide by 1. */ timerPrescale2 = _TIMER_CFG_PRESC_DIV2, /**< Divide by 2. */ timerPrescale4 = _TIMER_CFG_PRESC_DIV4, /**< Divide by 4. */ timerPrescale8 = _TIMER_CFG_PRESC_DIV8, /**< Divide by 8. */ timerPrescale16 = _TIMER_CFG_PRESC_DIV16, /**< Divide by 16. */ timerPrescale32 = _TIMER_CFG_PRESC_DIV32, /**< Divide by 32. */ timerPrescale64 = _TIMER_CFG_PRESC_DIV64, /**< Divide by 64. */ timerPrescale128 = _TIMER_CFG_PRESC_DIV128, /**< Divide by 128. */ timerPrescale256 = _TIMER_CFG_PRESC_DIV256, /**< Divide by 256. */ timerPrescale512 = _TIMER_CFG_PRESC_DIV512, /**< Divide by 512. */ timerPrescale1024 = _TIMER_CFG_PRESC_DIV1024 /**< Divide by 1024. */ #endif } TIMER_Prescale_TypeDef; /** Peripheral Reflex System signal. */ typedef uint8_t TIMER_PRSSEL_TypeDef; /** Deprecated PRS channel selector. New code should use an integer instead of * using these deprecated enum values. */ #define timerPRSSELCh0 0UL #define timerPRSSELCh1 1UL #define timerPRSSELCh2 2UL #define timerPRSSELCh3 3UL #define timerPRSSELCh4 4UL #define timerPRSSELCh5 5UL #define timerPRSSELCh6 6UL #define timerPRSSELCh7 7UL #define timerPRSSELCh8 8UL #define timerPRSSELCh9 9UL #define timerPRSSELCh10 10UL #define timerPRSSELCh11 11UL #if defined (_TIMER_CC_CFG_INSEL_MASK) typedef enum { timerPrsInputNone = 0x0, timerPrsInputSync = _TIMER_CC_CFG_INSEL_PRSSYNC, timerPrsInputAsyncLevel = _TIMER_CC_CFG_INSEL_PRSASYNCLEVEL, timerPrsInputAsyncPulse = _TIMER_CC_CFG_INSEL_PRSASYNCPULSE, } TIMER_PrsInput_TypeDef; #endif #if defined(_TIMER_DTFC_DTFA_MASK) || defined(_TIMER_DTFCFG_DTFA_MASK) /** DT (Dead Time) Fault Actions. */ typedef enum { #if defined(_TIMER_DTFC_DTFA_MASK) timerDtiFaultActionNone = _TIMER_DTFC_DTFA_NONE, /**< No action on fault. */ timerDtiFaultActionInactive = _TIMER_DTFC_DTFA_INACTIVE, /**< Set outputs inactive. */ timerDtiFaultActionClear = _TIMER_DTFC_DTFA_CLEAR, /**< Clear outputs. */ timerDtiFaultActionTristate = _TIMER_DTFC_DTFA_TRISTATE /**< Tristate outputs. */ #endif #if defined(_TIMER_DTFCFG_DTFA_MASK) timerDtiFaultActionNone = _TIMER_DTFCFG_DTFA_NONE, /**< No action on fault. */ timerDtiFaultActionInactive = _TIMER_DTFCFG_DTFA_INACTIVE, /**< Set outputs inactive. */ timerDtiFaultActionClear = _TIMER_DTFCFG_DTFA_CLEAR, /**< Clear outputs. */ timerDtiFaultActionTristate = _TIMER_DTFCFG_DTFA_TRISTATE /**< Tristate outputs. */ #endif } TIMER_DtiFaultAction_TypeDef; #endif /******************************************************************************* ******************************* STRUCTS *********************************** ******************************************************************************/ /** TIMER initialization structure. */ typedef struct { /** Start counting when initialization completed. */ bool enable; /** Counter shall keep running during debug halt. */ bool debugRun; /** Prescaling factor, if HFPER / HFPERB clock used. */ TIMER_Prescale_TypeDef prescale; /** Clock selection. */ TIMER_ClkSel_TypeDef clkSel; #if defined(TIMER_CTRL_X2CNT) && (defined(TIMER_CTRL_ATI) || defined(TIMER_CFG_ATI)) /** 2x Count mode, counter increments/decrements by 2, meant for PWM mode. */ bool count2x; /** ATI (Always Track Inputs) makes CCPOL always track * the polarity of the inputs. */ bool ati; #endif /** Action on falling input edge. */ TIMER_InputAction_TypeDef fallAction; /** Action on rising input edge. */ TIMER_InputAction_TypeDef riseAction; /** Counting mode. */ TIMER_Mode_TypeDef mode; /** DMA request clear on active. */ bool dmaClrAct; /** Select X2 or X4 quadrature decode mode (if used). */ bool quadModeX4; /** Determines if only counting up or down once. */ bool oneShot; /** Timer start/stop/reload by other timers. */ bool sync; } TIMER_Init_TypeDef; /** Default configuration for TIMER initialization structure. */ #if defined(TIMER_CTRL_X2CNT) && (defined(TIMER_CTRL_ATI) || defined(TIMER_CFG_ATI)) #define TIMER_INIT_DEFAULT \ { \ true, /* Enable timer when initialization completes. */ \ false, /* Stop counter during debug halt. */ \ timerPrescale1, /* No prescaling. */ \ timerClkSelHFPerClk, /* Select HFPER / HFPERB clock. */ \ false, /* Not 2x count mode. */ \ false, /* No ATI. */ \ timerInputActionNone, /* No action on falling input edge. */ \ timerInputActionNone, /* No action on rising input edge. */ \ timerModeUp, /* Up-counting. */ \ false, /* Do not clear DMA requests when DMA channel is active. */ \ false, /* Select X2 quadrature decode mode (if used). */ \ false, /* Disable one shot. */ \ false /* Not started/stopped/reloaded by other timers. */ \ } #else #define TIMER_INIT_DEFAULT \ { \ true, /* Enable timer when initialization completes. */ \ false, /* Stop counter during debug halt. */ \ timerPrescale1, /* No prescaling. */ \ timerClkSelHFPerClk, /* Select HFPER / HFPERB clock. */ \ timerInputActionNone, /* No action on falling input edge. */ \ timerInputActionNone, /* No action on rising input edge. */ \ timerModeUp, /* Up-counting. */ \ false, /* Do not clear DMA requests when DMA channel is active. */ \ false, /* Select X2 quadrature decode mode (if used). */ \ false, /* Disable one shot. */ \ false /* Not started/stopped/reloaded by other timers. */ \ } #endif /** PRS Output configuration. */ typedef enum { timerPrsOutputPulse = 0, /**< Pulse PRS output from a channel. */ timerPrsOutputLevel = 1, /**< PRS output follows CC out level. */ timerPrsOutputDefault = timerPrsOutputPulse, /**< Default PRS output behavior. */ } TIMER_PrsOutput_t; /** TIMER compare/capture initialization structure. */ typedef struct { /** Input capture event control. */ TIMER_Event_TypeDef eventCtrl; /** Input capture edge select. */ TIMER_Edge_TypeDef edge; /** * Peripheral reflex system trigger selection. Only applicable if @p prsInput * is enabled. */ TIMER_PRSSEL_TypeDef prsSel; /** Counter underflow output action. */ TIMER_OutputAction_TypeDef cufoa; /** Counter overflow output action. */ TIMER_OutputAction_TypeDef cofoa; /** Counter match output action. */ TIMER_OutputAction_TypeDef cmoa; /** Compare/capture channel mode. */ TIMER_CCMode_TypeDef mode; /** Enable digital filter. */ bool filter; /** Select TIMERnCCx (false) or PRS input (true). */ bool prsInput; /** * Compare output initial state. Only used in Output Compare and PWM mode. * When true, the compare/PWM output is set high when the counter is * disabled. When counting resumes, this value will represent the initial * value for the compare/PWM output. If the bit is cleared, the output * will be cleared when the counter is disabled. */ bool coist; /** Invert output from compare/capture channel. */ bool outInvert; /** * PRS output configuration. PRS output from a timer can either be a * pulse output or a level output that follows the CC out value. */ TIMER_PrsOutput_t prsOutput; #if defined(_TIMER_CC_CFG_INSEL_MASK) /* When PRS input is used this field is used to configure the type of * PRS input. */ TIMER_PrsInput_TypeDef prsInputType; #endif } TIMER_InitCC_TypeDef; /** Default configuration for TIMER compare/capture initialization structure. */ #if defined(_TIMER_CC_CFG_INSEL_MASK) #define TIMER_INITCC_DEFAULT \ { \ timerEventEveryEdge, /* Event on every capture. */ \ timerEdgeRising, /* Input capture edge on rising edge. */ \ 0, /* Not used by default, select PRS channel 0. */ \ timerOutputActionNone, /* No action on underflow. */ \ timerOutputActionNone, /* No action on overflow. */ \ timerOutputActionNone, /* No action on match. */ \ timerCCModeOff, /* Disable compare/capture channel. */ \ false, /* Disable filter. */ \ false, /* No PRS input. */ \ false, /* Clear output when counter disabled. */ \ false, /* Do not invert output. */ \ timerPrsOutputDefault, /* Use default PRS output configuration. */ \ timerPrsInputNone /* No PRS input, so input type is none. */ \ } #else #define TIMER_INITCC_DEFAULT \ { \ timerEventEveryEdge, /* Event on every capture. */ \ timerEdgeRising, /* Input capture edge on rising edge. */ \ 0, /* Not used by default, select PRS channel 0. */ \ timerOutputActionNone, /* No action on underflow. */ \ timerOutputActionNone, /* No action on overflow. */ \ timerOutputActionNone, /* No action on match. */ \ timerCCModeOff, /* Disable compare/capture channel. */ \ false, /* Disable filter. */ \ false, /* No PRS input. */ \ false, /* Clear output when counter disabled. */ \ false, /* Do not invert output. */ \ timerPrsOutputDefault, /* Use default PRS output configuration. */ \ } #endif #if defined(_TIMER_DTCTRL_MASK) /** TIMER Dead Time Insertion (DTI) initialization structure. */ typedef struct { /** Enable DTI or leave it disabled until @ref TIMER_EnableDTI() is called. */ bool enable; /** DTI Output Polarity. */ bool activeLowOut; /** DTI Complementary Output Invert. */ bool invertComplementaryOut; /** Enable Automatic Start-up functionality (when debugger exits). */ bool autoRestart; /** Enable/disable PRS as DTI input. */ bool enablePrsSource; /** Select which PRS channel as DTI input. Only valid if @p enablePrsSource is enabled. */ TIMER_PRSSEL_TypeDef prsSel; /** DTI prescaling factor, if HFPER / HFPERB clock used. */ TIMER_Prescale_TypeDef prescale; /** DTI Rise Time */ unsigned int riseTime; /** DTI Fall Time */ unsigned int fallTime; /** DTI outputs enable bit mask, consisting of one bit per DTI output signal, i.e., CC0, CC1, CC2, CDTI0, CDTI1, and CDTI2. This value should consist of one or more TIMER_DTOGEN_DTOGnnnEN flags (defined in \<part_name\>_timer.h) OR'ed together. */ uint32_t outputsEnableMask; /** Enable core lockup as a fault source. */ bool enableFaultSourceCoreLockup; /** Enable debugger as a fault source. */ bool enableFaultSourceDebugger; /** Enable PRS fault source 0 (@p faultSourcePrsSel0). */ bool enableFaultSourcePrsSel0; /** Select which PRS signal to be PRS fault source 0. */ TIMER_PRSSEL_TypeDef faultSourcePrsSel0; /** Enable PRS fault source 1 (@p faultSourcePrsSel1). */ bool enableFaultSourcePrsSel1; /** Select which PRS signal to be PRS fault source 1. */ TIMER_PRSSEL_TypeDef faultSourcePrsSel1; /** Fault Action */ TIMER_DtiFaultAction_TypeDef faultAction; } TIMER_InitDTI_TypeDef; /** Default configuration for TIMER DTI initialization structure. */ #define TIMER_INITDTI_DEFAULT \ { \ true, /* Enable the DTI. */ \ false, /* CC[0|1|2] outputs are active high. */ \ false, /* CDTI[0|1|2] outputs are not inverted. */ \ false, /* No auto restart when debugger exits. */ \ false, /* No PRS source selected. */ \ 0, /* Not used by default, select PRS channel 0. */ \ timerPrescale1, /* No prescaling. */ \ 0, /* No rise time. */ \ 0, /* No fall time. */ \ TIMER_DTOGEN_DTOGCC0EN | TIMER_DTOGEN_DTOGCDTI0EN, /* Enable CC0 and CDTI0. */ \ true, /* Enable core lockup as fault source. */ \ true, /* Enable debugger as fault source. */ \ false, /* Disable PRS fault source 0. */ \ 0, /* Not used by default, select PRS channel 0. */ \ false, /* Disable PRS fault source 1. */ \ 0, /* Not used by default, select PRS channel 0. */ \ timerDtiFaultActionInactive, /* No fault action. */ \ } #endif /* _TIMER_DTCTRL_MASK */ /******************************************************************************* ***************************** PROTOTYPES ********************************** ******************************************************************************/ /***************************************************************************//** * @brief * Validate TIMER register block pointer. * * @param[in] ref * Pointer to TIMER peripheral register block. * * @return * True if ref points to a valid timer, false otherwise. ******************************************************************************/ __STATIC_INLINE bool TIMER_Valid(const TIMER_TypeDef *ref) { return (ref == TIMER0) #if defined(TIMER1) || (ref == TIMER1) #endif #if defined(TIMER2) || (ref == TIMER2) #endif #if defined(TIMER3) || (ref == TIMER3) #endif #if defined(TIMER4) || (ref == TIMER4) #endif #if defined(TIMER5) || (ref == TIMER5) #endif #if defined(TIMER6) || (ref == TIMER6) #endif #if defined(WTIMER0) || (ref == WTIMER0) #endif #if defined(WTIMER1) || (ref == WTIMER1) #endif #if defined(WTIMER2) || (ref == WTIMER2) #endif #if defined(WTIMER3) || (ref == WTIMER3) #endif ; } /***************************************************************************//** * @brief * Get the Max count of the timer. * * @param[in] timer * Pointer to TIMER peripheral register block. * * @return * The max count value of the timer. This is 0xFFFF for 16 bit timers * and 0xFFFFFFFF for 32 bit timers. ******************************************************************************/ __STATIC_INLINE uint32_t TIMER_MaxCount(const TIMER_TypeDef *ref) { #if defined(WTIMER_PRESENT) if ((ref == WTIMER0) #if defined(WTIMER1) || (ref == WTIMER1) #endif #if defined(WTIMER2) || (ref == WTIMER2) #endif #if defined(WTIMER3) || (ref == WTIMER3) #endif ) { return 0xFFFFFFFFUL; } #else (void) ref; #endif return 0xFFFFUL; } /***************************************************************************//** * @brief * Get compare/capture value for compare/capture channel. * * @param[in] timer * Pointer to TIMER peripheral register block. * * @param[in] ch * Compare/capture channel to access. * * @return * Current capture value. ******************************************************************************/ __STATIC_INLINE uint32_t TIMER_CaptureGet(TIMER_TypeDef *timer, unsigned int ch) { #if defined (_TIMER_CC_CFG_MASK) if ((timer->CC[ch].CFG & _TIMER_CC_CFG_MODE_MASK) == TIMER_CC_CFG_MODE_INPUTCAPTURE) { return timer->CC[ch].ICF; } else { return timer->CC[ch].OC; } #else return timer->CC[ch].CCV; #endif } /***************************************************************************//** * @brief * Get buffered compare/capture value for compare/capture channel. * * @param[in] timer * Pointer to TIMER peripheral register block. * * @param[in] ch * Compare/capture channel to access. * * @return * Current buffered capture value. ******************************************************************************/ __STATIC_INLINE uint32_t TIMER_CaptureBufGet(TIMER_TypeDef *timer, unsigned int ch) { #if defined (_TIMER_CC_CFG_MASK) if ((timer->CC[ch].CFG & _TIMER_CC_CFG_MODE_MASK) == TIMER_CC_CFG_MODE_INPUTCAPTURE) { return timer->CC[ch].ICOF; } else { return timer->CC[ch].OCB; } #else return timer->CC[ch].CCVB; #endif } /***************************************************************************//** * @brief * Set compare value buffer for compare/capture channel when operating in * compare or PWM mode. * * @details * The compare value buffer holds the value which will be written to * TIMERn_CCx_CCV on an update event if the buffer has been updated since * the last event. * * @param[in] timer * Pointer to TIMER peripheral register block. * * @param[in] ch * Compare/capture channel to access. * * @param[in] val * Value to set in compare value buffer register. ******************************************************************************/ __STATIC_INLINE void TIMER_CompareBufSet(TIMER_TypeDef *timer, unsigned int ch, uint32_t val) { EFM_ASSERT(val <= TIMER_MaxCount(timer)); #if defined (_TIMER_CC_CFG_MASK) EFM_ASSERT(timer->EN & TIMER_EN_EN); timer->CC[ch].OCB = val; #else timer->CC[ch].CCVB = val; #endif } /***************************************************************************//** * @brief * Set compare value for compare/capture channel when operating in compare * or PWM mode. * * @param[in] timer * Pointer to TIMER peripheral register block. * * @param[in] ch * Compare/capture channel to access. * * @param[in] val * Value to set in compare value register. ******************************************************************************/ __STATIC_INLINE void TIMER_CompareSet(TIMER_TypeDef *timer, unsigned int ch, uint32_t val) { EFM_ASSERT(val <= TIMER_MaxCount(timer)); #if defined (_TIMER_CC_CFG_MASK) EFM_ASSERT(timer->EN & TIMER_EN_EN); timer->CC[ch].OC = val; #else timer->CC[ch].CCV = val; #endif } /***************************************************************************//** * @brief * Get TIMER counter value. * * @param[in] timer * Pointer to TIMER peripheral register block. * * @return * Current TIMER counter value. ******************************************************************************/ __STATIC_INLINE uint32_t TIMER_CounterGet(TIMER_TypeDef *timer) { return timer->CNT; } /***************************************************************************//** * @brief * Set TIMER counter value. * * @param[in] timer * Pointer to TIMER peripheral register block. * * @param[in] val * Value to set counter to. ******************************************************************************/ __STATIC_INLINE void TIMER_CounterSet(TIMER_TypeDef *timer, uint32_t val) { EFM_ASSERT(val <= TIMER_MaxCount(timer)); #if defined(TIMER_HAS_SET_CLEAR) bool enabled = (timer->EN & TIMER_EN_EN) != 0UL; timer->EN_SET = TIMER_EN_EN; #endif timer->CNT = val; #if defined(TIMER_HAS_SET_CLEAR) if (!enabled) { timer->EN_CLR = TIMER_EN_EN; } #endif } /***************************************************************************//** * @brief * Start/stop TIMER. * * @param[in] timer * Pointer to TIMER peripheral register block. * * @param[in] enable * Set to true to enable counting; set to false otherwise. ******************************************************************************/ __STATIC_INLINE void TIMER_Enable(TIMER_TypeDef *timer, bool enable) { EFM_ASSERT(TIMER_REF_VALID(timer)); if (enable) { timer->CMD = TIMER_CMD_START; } else { timer->CMD = TIMER_CMD_STOP; } } void TIMER_Init(TIMER_TypeDef *timer, const TIMER_Init_TypeDef *init); void TIMER_InitCC(TIMER_TypeDef *timer, unsigned int ch, const TIMER_InitCC_TypeDef *init); #if defined(_TIMER_DTCTRL_MASK) void TIMER_InitDTI(TIMER_TypeDef *timer, const TIMER_InitDTI_TypeDef *init); /***************************************************************************//** * @brief * Enable or disable DTI unit. * * @param[in] timer * Pointer to TIMER peripheral register block. * * @param[in] enable * Set to true to enable DTI unit; set to false otherwise. ******************************************************************************/ __STATIC_INLINE void TIMER_EnableDTI(TIMER_TypeDef *timer, bool enable) { #if defined(TIMER_HAS_SET_CLEAR) uint32_t timerEn = timer->EN & TIMER_EN_EN; timer->EN_CLR = TIMER_EN_EN; if (enable) { timer->DTCFG_SET = TIMER_DTCFG_DTEN; } else { timer->DTCFG_CLR = TIMER_DTCFG_DTEN; } timer->EN_SET = timerEn; #else EFM_ASSERT(TIMER0 == timer); if (enable) { timer->DTCTRL |= TIMER_DTCTRL_DTEN; } else { timer->DTCTRL &= ~TIMER_DTCTRL_DTEN; } #endif } /***************************************************************************//** * @brief * Get DTI fault source flags status. * * @note * Event bits are not cleared by this function. * * @param[in] timer * Pointer to TIMER peripheral register block. * * @return * Status of the DTI fault source flags. Returns one or more valid * DTI fault source flags (TIMER_DTFAULT_nnn) OR'ed together. ******************************************************************************/ __STATIC_INLINE uint32_t TIMER_GetDTIFault(TIMER_TypeDef *timer) { EFM_ASSERT(TIMER0 == timer); return timer->DTFAULT; } /***************************************************************************//** * @brief * Clear DTI fault source flags. * * @param[in] timer * Pointer to TIMER peripheral register block. * * @param[in] flags * DTI fault source(s) to clear. Use one or more valid DTI fault * source flags (TIMER_DTFAULT_nnn) OR'ed together. ******************************************************************************/ __STATIC_INLINE void TIMER_ClearDTIFault(TIMER_TypeDef *timer, uint32_t flags) { EFM_ASSERT(TIMER0 == timer); #if defined (TIMER_EN_EN) EFM_ASSERT(timer->EN & TIMER_EN_EN); #endif timer->DTFAULTC = flags; } #endif /* _TIMER_DTCTRL_MASK */ /***************************************************************************//** * @brief * Clear one or more pending TIMER interrupts. * * @param[in] timer * Pointer to TIMER peripheral register block. * * @param[in] flags * Pending TIMER interrupt source(s) to clear. Use one or more valid * interrupt flags for the TIMER module (TIMER_IF_nnn) OR'ed together. ******************************************************************************/ __STATIC_INLINE void TIMER_IntClear(TIMER_TypeDef *timer, uint32_t flags) { #if defined (TIMER_HAS_SET_CLEAR) timer->IF_CLR = flags; #else timer->IFC = flags; #endif } /***************************************************************************//** * @brief * Disable one or more TIMER interrupts. * * @param[in] timer * Pointer to TIMER peripheral register block. * * @param[in] flags * TIMER interrupt source(s) to disable. Use one or more valid * interrupt flags for the TIMER module (TIMER_IF_nnn) OR'ed together. ******************************************************************************/ __STATIC_INLINE void TIMER_IntDisable(TIMER_TypeDef *timer, uint32_t flags) { timer->IEN &= ~flags; } /***************************************************************************//** * @brief * Enable one or more TIMER interrupts. * * @note * Depending on the use, a pending interrupt may already be set prior to * enabling the interrupt. To ignore a pending interrupt, consider using * TIMER_IntClear() prior to enabling the interrupt. * * @param[in] timer * Pointer to TIMER peripheral register block. * * @param[in] flags * TIMER interrupt source(s) to enable. Use one or more valid * interrupt flags for the TIMER module (TIMER_IF_nnn) OR'ed together. ******************************************************************************/ __STATIC_INLINE void TIMER_IntEnable(TIMER_TypeDef *timer, uint32_t flags) { timer->IEN |= flags; } /***************************************************************************//** * @brief * Get pending TIMER interrupt flags. * * @note * Event bits are not cleared by this function. * * @param[in] timer * Pointer to TIMER peripheral register block. * * @return * TIMER interrupt source(s) pending. Returns one or more valid * interrupt flags for the TIMER module (TIMER_IF_nnn) OR'ed together. ******************************************************************************/ __STATIC_INLINE uint32_t TIMER_IntGet(TIMER_TypeDef *timer) { return timer->IF; } /***************************************************************************//** * @brief * Get enabled and pending TIMER interrupt flags. * Useful for handling more interrupt sources in the same interrupt handler. * * @param[in] timer * Pointer to TIMER peripheral register block. * * @note * Interrupt flags are not cleared by this function. * * @return * Pending and enabled TIMER interrupt sources. * The return value is the bitwise AND combination of * - the OR combination of enabled interrupt sources in TIMERx_IEN_nnn * register (TIMERx_IEN_nnn) and * - the OR combination of valid interrupt flags of the TIMER module * (TIMERx_IF_nnn). ******************************************************************************/ __STATIC_INLINE uint32_t TIMER_IntGetEnabled(TIMER_TypeDef *timer) { uint32_t ien; /* Store TIMER->IEN in temporary variable in order to define explicit order * of volatile accesses. */ ien = timer->IEN; /* Bitwise AND of pending and enabled interrupts */ return timer->IF & ien; } /***************************************************************************//** * @brief * Set one or more pending TIMER interrupts from SW. * * @param[in] timer * Pointer to TIMER peripheral register block. * * @param[in] flags * TIMER interrupt source(s) to set to pending. Use one or more valid * interrupt flags for the TIMER module (TIMER_IF_nnn) OR'ed together. ******************************************************************************/ __STATIC_INLINE void TIMER_IntSet(TIMER_TypeDef *timer, uint32_t flags) { #if defined (TIMER_HAS_SET_CLEAR) timer->IF_SET = flags; #else timer->IFS = flags; #endif } #if defined(_TIMER_DTLOCK_LOCKKEY_LOCK) /***************************************************************************//** * @brief * Lock some of the TIMER registers in order to protect them from being * modified. * * @details * Refer to the reference manual for TIMER registers that will be locked. * * @note * If locking the TIMER registers, they must be unlocked prior to using any * TIMER API function that modifies TIMER registers protected by the lock. * * @param[in] timer * Pointer to TIMER peripheral register block. ******************************************************************************/ __STATIC_INLINE void TIMER_Lock(TIMER_TypeDef *timer) { EFM_ASSERT(TIMER0 == timer); #if defined (TIMER_EN_EN) EFM_ASSERT(timer->EN & TIMER_EN_EN); #endif timer->DTLOCK = TIMER_DTLOCK_LOCKKEY_LOCK; } #endif void TIMER_Reset(TIMER_TypeDef *timer); /***************************************************************************//** * @brief * Set top value buffer for timer. * * @details * When top value buffer register is updated, value is loaded into * top value register at the next wrap around. This feature is useful * in order to update top value safely when timer is running. * * @param[in] timer * Pointer to TIMER peripheral register block. * * @param[in] val * Value to set in top value buffer register. ******************************************************************************/ __STATIC_INLINE void TIMER_TopBufSet(TIMER_TypeDef *timer, uint32_t val) { EFM_ASSERT(val <= TIMER_MaxCount(timer)); #if defined (TIMER_EN_EN) EFM_ASSERT(timer->EN & TIMER_EN_EN); #endif timer->TOPB = val; } /***************************************************************************//** * @brief * Get top value setting for timer. * * @param[in] timer * Pointer to TIMER peripheral register block. * * @return * Current top value. ******************************************************************************/ __STATIC_INLINE uint32_t TIMER_TopGet(TIMER_TypeDef *timer) { return timer->TOP; } /***************************************************************************//** * @brief * Set top value for timer. * * @param[in] timer * Pointer to TIMER peripheral register block. * * @param[in] val * Value to set in top value register. ******************************************************************************/ __STATIC_INLINE void TIMER_TopSet(TIMER_TypeDef *timer, uint32_t val) { EFM_ASSERT(val <= TIMER_MaxCount(timer)); #if defined (TIMER_EN_EN) EFM_ASSERT(timer->EN & TIMER_EN_EN); #endif timer->TOP = val; } #if defined(TIMER_DTLOCK_LOCKKEY_UNLOCK) /***************************************************************************//** * @brief * Unlock TIMER to enable writing to locked registers again. * * @param[in] timer * Pointer to TIMER peripheral register block. ******************************************************************************/ __STATIC_INLINE void TIMER_Unlock(TIMER_TypeDef *timer) { EFM_ASSERT(TIMER0 == timer); #if defined (TIMER_EN_EN) EFM_ASSERT(timer->EN & TIMER_EN_EN); #endif timer->DTLOCK = TIMER_DTLOCK_LOCKKEY_UNLOCK; } #endif /** @} (end addtogroup TIMER) */ /** @} (end addtogroup emlib) */ #ifdef __cplusplus } #endif #endif /* defined(TIMER_COUNT) && (TIMER_COUNT > 0) */ #endif /* EM_TIMER_H */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/emlib/inc/em_usart.h.
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/***************************************************************************//** * @file * @brief Universal synchronous/asynchronous receiver/transmitter (USART/UART) * peripheral API * @version 5.7.0 ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * SPDX-License-Identifier: Zlib * * The licensor of this software is Silicon Laboratories Inc. * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be * appreciated but is not required. * 2. Altered source versions must be plainly marked as such, and must not be * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * ******************************************************************************/ #ifndef EM_USART_H #define EM_USART_H #include "em_device.h" #if defined(USART_COUNT) && (USART_COUNT > 0) #include <stdbool.h> #ifdef __cplusplus extern "C" { #endif /***************************************************************************//** * @addtogroup emlib * @{ ******************************************************************************/ /***************************************************************************//** * @addtogroup USART * @brief Universal Synchronous/Asynchronous Receiver/Transmitter * Peripheral API * @details * The Universal Synchronous/Asynchronous Receiver/Transmitter (USART) * is a very flexible serial I/O module. It supports full duplex asynchronous UART * communication as well as RS-485, SPI, MicroWire, and 3-wire. It can also interface * with ISO7816 Smart-Cards, and IrDA devices. * * The USART has a wide selection of operating modes, frame formats, and baud rates. * All features are supported through the API of this module. * * Triple buffering and DMA support makes high data-rates possible with minimal * CPU intervention. It is possible to transmit and receive large frames while * the MCU remains in EM1 Sleep. * * This module does not support DMA configuration. The @ref UARTDRV and @ref SPIDRV drivers * provide full support for DMA and more. * * The following steps are necessary for basic operation: * * Clock enable: * @include em_usart_clock_enable.c * * To initialize the USART for asynchronous operation (e.g., UART): * @include em_usart_init_async.c * * To initialize the USART for synchronous operation (e.g., SPI): * @include em_usart_init_sync.c * * After pins are assigned for the application/board, enable pins at the * desired location. Available locations can be obtained from the Pin Definitions * section in the data sheet. * @if DOXYDOC_P1_DEVICE * @include em_usart_route_p1.c * @note UART hardware flow control is not directly supported in hardware on * @ref _SILICON_LABS_32B_SERIES_0 parts. * @endif * @if DOXYDOC_P2_DEVICE * @include em_usart_route_p2.c * @endif * @note @ref UARTDRV supports all types of UART flow control. Software assisted * hardware flow control is available for parts without true UART hardware * flow control. * @{ ******************************************************************************/ /******************************************************************************* ******************************** ENUMS ************************************ ******************************************************************************/ /** Databit selection. */ typedef enum { usartDatabits4 = USART_FRAME_DATABITS_FOUR, /**< 4 data bits (not available for UART). */ usartDatabits5 = USART_FRAME_DATABITS_FIVE, /**< 5 data bits (not available for UART). */ usartDatabits6 = USART_FRAME_DATABITS_SIX, /**< 6 data bits (not available for UART). */ usartDatabits7 = USART_FRAME_DATABITS_SEVEN, /**< 7 data bits (not available for UART). */ usartDatabits8 = USART_FRAME_DATABITS_EIGHT, /**< 8 data bits. */ usartDatabits9 = USART_FRAME_DATABITS_NINE, /**< 9 data bits. */ usartDatabits10 = USART_FRAME_DATABITS_TEN, /**< 10 data bits (not available for UART). */ usartDatabits11 = USART_FRAME_DATABITS_ELEVEN, /**< 11 data bits (not available for UART). */ usartDatabits12 = USART_FRAME_DATABITS_TWELVE, /**< 12 data bits (not available for UART). */ usartDatabits13 = USART_FRAME_DATABITS_THIRTEEN, /**< 13 data bits (not available for UART). */ usartDatabits14 = USART_FRAME_DATABITS_FOURTEEN, /**< 14 data bits (not available for UART). */ usartDatabits15 = USART_FRAME_DATABITS_FIFTEEN, /**< 15 data bits (not available for UART). */ usartDatabits16 = USART_FRAME_DATABITS_SIXTEEN /**< 16 data bits (not available for UART). */ } USART_Databits_TypeDef; /** Enable selection. */ typedef enum { /** Disable both receiver and transmitter. */ usartDisable = 0x0, /** Enable receiver only, transmitter disabled. */ usartEnableRx = USART_CMD_RXEN, /** Enable transmitter only, receiver disabled. */ usartEnableTx = USART_CMD_TXEN, /** Enable both receiver and transmitter. */ usartEnable = (USART_CMD_RXEN | USART_CMD_TXEN) } USART_Enable_TypeDef; /** Oversampling selection, used for asynchronous operation. */ typedef enum { usartOVS16 = USART_CTRL_OVS_X16, /**< 16x oversampling (normal). */ usartOVS8 = USART_CTRL_OVS_X8, /**< 8x oversampling. */ usartOVS6 = USART_CTRL_OVS_X6, /**< 6x oversampling. */ usartOVS4 = USART_CTRL_OVS_X4 /**< 4x oversampling. */ } USART_OVS_TypeDef; /** Parity selection, mainly used for asynchronous operation. */ typedef enum { usartNoParity = USART_FRAME_PARITY_NONE, /**< No parity. */ usartEvenParity = USART_FRAME_PARITY_EVEN, /**< Even parity. */ usartOddParity = USART_FRAME_PARITY_ODD /**< Odd parity. */ } USART_Parity_TypeDef; /** Stop bits selection, used for asynchronous operation. */ typedef enum { usartStopbits0p5 = USART_FRAME_STOPBITS_HALF, /**< 0.5 stop bits. */ usartStopbits1 = USART_FRAME_STOPBITS_ONE, /**< 1 stop bits. */ usartStopbits1p5 = USART_FRAME_STOPBITS_ONEANDAHALF, /**< 1.5 stop bits. */ usartStopbits2 = USART_FRAME_STOPBITS_TWO /**< 2 stop bits. */ } USART_Stopbits_TypeDef; #if defined(_USART_ROUTEPEN_RTSPEN_MASK) && defined(_USART_ROUTEPEN_CTSPEN_MASK) typedef enum { usartHwFlowControlNone = 0, usartHwFlowControlCts = USART_ROUTEPEN_CTSPEN, usartHwFlowControlRts = USART_ROUTEPEN_RTSPEN, usartHwFlowControlCtsAndRts = USART_ROUTEPEN_CTSPEN | USART_ROUTEPEN_RTSPEN, } USART_HwFlowControl_TypeDef; #elif defined(USART_CTRLX_CTSEN) typedef enum { usartHwFlowControlNone = 0, usartHwFlowControlCts, usartHwFlowControlRts, usartHwFlowControlCtsAndRts } USART_HwFlowControl_TypeDef; #endif /** Clock polarity/phase mode. */ typedef enum { /** Clock idle low, sample on rising edge. */ usartClockMode0 = USART_CTRL_CLKPOL_IDLELOW | USART_CTRL_CLKPHA_SAMPLELEADING, /** Clock idle low, sample on falling edge. */ usartClockMode1 = USART_CTRL_CLKPOL_IDLELOW | USART_CTRL_CLKPHA_SAMPLETRAILING, /** Clock idle high, sample on falling edge. */ usartClockMode2 = USART_CTRL_CLKPOL_IDLEHIGH | USART_CTRL_CLKPHA_SAMPLELEADING, /** Clock idle high, sample on rising edge. */ usartClockMode3 = USART_CTRL_CLKPOL_IDLEHIGH | USART_CTRL_CLKPHA_SAMPLETRAILING } USART_ClockMode_TypeDef; /** Pulse width selection for IrDA mode. */ typedef enum { /** IrDA pulse width is 1/16 for OVS=0 and 1/8 for OVS=1 */ usartIrDAPwONE = USART_IRCTRL_IRPW_ONE, /** IrDA pulse width is 2/16 for OVS=0 and 2/8 for OVS=1 */ usartIrDAPwTWO = USART_IRCTRL_IRPW_TWO, /** IrDA pulse width is 3/16 for OVS=0 and 3/8 for OVS=1 */ usartIrDAPwTHREE = USART_IRCTRL_IRPW_THREE, /** IrDA pulse width is 4/16 for OVS=0 and 4/8 for OVS=1 */ usartIrDAPwFOUR = USART_IRCTRL_IRPW_FOUR } USART_IrDAPw_Typedef; /** PRS Channel type */ typedef uint8_t USART_PRS_Channel_t; /** Deprecated PRS channel selector value. * New code should use an integer instead. */ #define usartIrDAPrsCh0 0U #define usartIrDAPrsCh1 1U #define usartIrDAPrsCh2 2U #define usartIrDAPrsCh3 3U #define usartIrDAPrsCh4 4U #define usartIrDAPrsCh5 5U #define usartIrDAPrsCh6 6U #define usartIrDAPrsCh7 7U #define usartPrsRxCh0 0U #define usartPrsRxCh1 1U #define usartPrsRxCh2 2U #define usartPrsRxCh3 3U #define usartPrsRxCh4 4U #define usartPrsRxCh5 5U #define usartPrsRxCh6 6U #define usartPrsRxCh7 7U #define usartPrsRxCh8 8U #define usartPrsRxCh9 9U #define usartPrsRxCh10 10U #define usartPrsRxCh11 11U #define usartPrsTriggerCh0 0U #define usartPrsTriggerCh1 1U #define usartPrsTriggerCh2 2U #define usartPrsTriggerCh3 3U #define usartPrsTriggerCh4 4U #define usartPrsTriggerCh5 5U #define usartPrsTriggerCh6 6U #define usartPrsTriggerCh7 7U #if defined(_USART_I2SCTRL_MASK) && defined(USART_I2SCTRL_I2SEN) /** I2S format selection. */ typedef enum { usartI2sFormatW32D32 = USART_I2SCTRL_I2SFORMAT_W32D32, /**< 32-bit word, 32-bit data */ usartI2sFormatW32D24M = USART_I2SCTRL_I2SFORMAT_W32D24M, /**< 32-bit word, 32-bit data with 8 lsb masked */ usartI2sFormatW32D24 = USART_I2SCTRL_I2SFORMAT_W32D24, /**< 32-bit word, 24-bit data */ usartI2sFormatW32D16 = USART_I2SCTRL_I2SFORMAT_W32D16, /**< 32-bit word, 16-bit data */ usartI2sFormatW32D8 = USART_I2SCTRL_I2SFORMAT_W32D8, /**< 32-bit word, 8-bit data */ usartI2sFormatW16D16 = USART_I2SCTRL_I2SFORMAT_W16D16, /**< 16-bit word, 16-bit data */ usartI2sFormatW16D8 = USART_I2SCTRL_I2SFORMAT_W16D8, /**< 16-bit word, 8-bit data */ usartI2sFormatW8D8 = USART_I2SCTRL_I2SFORMAT_W8D8 /**< 8-bit word, 8-bit data */ } USART_I2sFormat_TypeDef; /** I2S frame data justify. */ typedef enum { usartI2sJustifyLeft = USART_I2SCTRL_I2SJUSTIFY_LEFT, /**< Data is left-justified within the frame */ usartI2sJustifyRight = USART_I2SCTRL_I2SJUSTIFY_RIGHT /**< Data is right-justified within the frame */ } USART_I2sJustify_TypeDef; #elif defined(_USART_I2SCTRL_MASK) /** I2S format selection. */ typedef enum { usartI2sFormatW32D32 = USART_I2SCTRL_FORMAT_W32D32, /**< 32-bit word, 32-bit data. */ usartI2sFormatW32D24M = USART_I2SCTRL_FORMAT_W32D24M, /**< 32-bit word, 32-bit data with 8 lsb masked. */ usartI2sFormatW32D24 = USART_I2SCTRL_FORMAT_W32D24, /**< 32-bit word, 24-bit data. */ usartI2sFormatW32D16 = USART_I2SCTRL_FORMAT_W32D16, /**< 32-bit word, 16-bit data. */ usartI2sFormatW32D8 = USART_I2SCTRL_FORMAT_W32D8, /**< 32-bit word, 8-bit data. */ usartI2sFormatW16D16 = USART_I2SCTRL_FORMAT_W16D16, /**< 16-bit word, 16-bit data. */ usartI2sFormatW16D8 = USART_I2SCTRL_FORMAT_W16D8, /**< 16-bit word, 8-bit data. */ usartI2sFormatW8D8 = USART_I2SCTRL_FORMAT_W8D8 /**< 8-bit word, 8-bit data. */ } USART_I2sFormat_TypeDef; /** I2S frame data justify. */ typedef enum { usartI2sJustifyLeft = USART_I2SCTRL_JUSTIFY_LEFT, /**< Data is left-justified within the frame. */ usartI2sJustifyRight = USART_I2SCTRL_JUSTIFY_RIGHT /**< Data is right-justified within the frame. */ } USART_I2sJustify_TypeDef; #endif /******************************************************************************* ******************************* STRUCTS *********************************** ******************************************************************************/ /** Asynchronous mode initialization structure. */ typedef struct { /** Specifies whether TX and/or RX is enabled when initialization is completed. */ USART_Enable_TypeDef enable; /** * USART/UART reference clock assumed when configuring baud rate setup. * Set to 0 to use the currently configured reference clock. */ uint32_t refFreq; /** Desired baud rate. */ uint32_t baudrate; /** Oversampling used. */ USART_OVS_TypeDef oversampling; /** Number of data bits in frame. Notice that UART modules only support 8 or * 9 data bits. */ USART_Databits_TypeDef databits; /** Parity mode to use. */ USART_Parity_TypeDef parity; /** Number of stop bits to use. */ USART_Stopbits_TypeDef stopbits; #if !defined(_EFM32_GECKO_FAMILY) /** Majority Vote Disable for 16x, 8x and 6x oversampling modes. */ bool mvdis; /** Enable USART Rx via PRS. */ bool prsRxEnable; /** Select PRS channel for USART Rx. (Only valid if prsRxEnable is true). */ USART_PRS_Channel_t prsRxCh; #endif /** Auto CS enabling. */ bool autoCsEnable; #if (_SILICON_LABS_32B_SERIES > 0) /** Auto CS hold time in baud cycles. */ uint8_t autoCsHold; /** Auto CS setup time in baud cycles. */ uint8_t autoCsSetup; /** Hardware flow control mode. */ USART_HwFlowControl_TypeDef hwFlowControl; #endif } USART_InitAsync_TypeDef; /** USART PRS trigger enable. */ typedef struct { #if defined(USART_TRIGCTRL_AUTOTXTEN) /** Enable AUTOTX. */ bool autoTxTriggerEnable; #endif /** Trigger receive via PRS channel. */ bool rxTriggerEnable; /** Trigger transmit via PRS channel. */ bool txTriggerEnable; /** PRS channel to be used to trigger auto transmission. */ USART_PRS_Channel_t prsTriggerChannel; } USART_PrsTriggerInit_TypeDef; /** Default configuration for USART asynchronous initialization structure. */ #if defined(_EFM32_GECKO_FAMILY) /* Default USART Async struct for the EFM32G device */ #define USART_INITASYNC_DEFAULT \ { \ usartEnable, /* Enable RX/TX when initialization is complete. */ \ 0, /* Use current configured reference clock for configuring baud rate. */ \ 115200, /* 115200 bits/s. */ \ usartOVS16, /* 16x oversampling. */ \ usartDatabits8, /* 8 data bits. */ \ usartNoParity, /* No parity. */ \ usartStopbits1, /* 1 stop bit. */ \ false, /* Auto CS functionality enable/disable switch */ \ } #elif defined(_SILICON_LABS_32B_SERIES_0) /* Default USART Async struct for Series 0 devices */ #define USART_INITASYNC_DEFAULT \ { \ usartEnable, /* Enable RX/TX when initialization is complete. */ \ 0, /* Use current configured reference clock for configuring baud rate. */ \ 115200, /* 115200 bits/s. */ \ usartOVS16, /* 16x oversampling. */ \ usartDatabits8, /* 8 data bits. */ \ usartNoParity, /* No parity. */ \ usartStopbits1, /* 1 stop bit. */ \ false, /* Do not disable majority vote. */ \ false, /* Not USART PRS input mode. */ \ 0, /* PRS channel 0. */ \ false, /* Auto CS functionality enable/disable switch */ \ } #elif (_SILICON_LABS_32B_SERIES > 0) /* Default USART Async struct for Series 1 and Series 2 devices */ #define USART_INITASYNC_DEFAULT \ { \ usartEnable, /* Enable RX/TX when initialization is complete. */ \ 0, /* Use current configured reference clock for configuring baud rate. */ \ 115200, /* 115200 bits/s. */ \ usartOVS16, /* 16x oversampling. */ \ usartDatabits8, /* 8 data bits. */ \ usartNoParity, /* No parity. */ \ usartStopbits1, /* 1 stop bit. */ \ false, /* Do not disable majority vote. */ \ false, /* Not USART PRS input mode. */ \ 0, /* PRS channel 0. */ \ false, /* Auto CS functionality enable/disable switch */ \ 0, /* Auto CS Hold cycles */ \ 0, /* Auto CS Setup cycles */ \ usartHwFlowControlNone /* No HW flow control */ \ } #endif /** Default configuration for USART PRS triggering structure. */ #if defined(USART_TRIGCTRL_AUTOTXTEN) #define USART_INITPRSTRIGGER_DEFAULT \ { \ false, /* Do not enable autoTX triggering. */ \ false, /* Do not enable receive triggering. */ \ false, /* Do not enable transmit triggering. */ \ 0 /* Set default channel to zero. */ \ } #else #define USART_INITPRSTRIGGER_DEFAULT \ { \ false, /* Do not enable receive triggering. */ \ false, /* Do not enable transmit triggering. */ \ 0 /* Set default channel to zero. */ \ } #endif /** Synchronous mode initialization structure. */ typedef struct { /** Specifies whether TX and/or RX shall be enabled when initialization is completed. */ USART_Enable_TypeDef enable; /** * USART/UART reference clock assumed when configuring baud rate setup. * Set to 0 to use the currently configured reference clock. */ uint32_t refFreq; /** Desired baud rate. */ uint32_t baudrate; /** Number of data bits in frame. */ USART_Databits_TypeDef databits; /** Select if to operate in master or slave mode. */ bool master; /** Select if to send most or least significant bit first. */ bool msbf; /** Clock polarity/phase mode. */ USART_ClockMode_TypeDef clockMode; #if !defined(_EFM32_GECKO_FAMILY) /** Enable USART Rx via PRS. */ bool prsRxEnable; /** Select PRS channel for USART Rx. (Only valid if prsRxEnable is true). */ USART_PRS_Channel_t prsRxCh; #endif #if defined(USART_TRIGCTRL_AUTOTXTEN) /** Enable AUTOTX mode. Transmits as long as RX is not full. * Generates underflows if TX is empty. */ bool autoTx; #endif /** Auto CS enabling */ bool autoCsEnable; #if defined(_USART_TIMING_CSHOLD_MASK) /** Auto CS hold time in baud cycles */ uint8_t autoCsHold; /** Auto CS setup time in baud cycles */ uint8_t autoCsSetup; #endif } USART_InitSync_TypeDef; /** Default configuration for USART sync initialization structure. */ #if defined(_EFM32_GECKO_FAMILY) /* Default USART Sync configuration for EFM32G devices. */ #define USART_INITSYNC_DEFAULT \ { \ usartEnable, /* Enable RX/TX when initialization is complete. */ \ 0, /* Use current configured reference clock for configuring baud rate. */ \ 1000000, /* 1 Mbits/s. */ \ usartDatabits8, /* 8 data bits. */ \ true, /* Master mode. */ \ false, /* Send least significant bit first. */ \ usartClockMode0, /* Clock idle low, sample on rising edge. */ \ false, /* No AUTOCS mode */ \ } #elif defined(_SILICON_LABS_32B_SERIES_0) /* Default USART Sync configuration for series 0 devices. */ #define USART_INITSYNC_DEFAULT \ { \ usartEnable, /* Enable RX/TX when initialization is complete. */ \ 0, /* Use current configured reference clock for configuring baud rate. */ \ 1000000, /* 1 Mbits/s. */ \ usartDatabits8, /* 8 data bits. */ \ true, /* Master mode. */ \ false, /* Send least significant bit first. */ \ usartClockMode0, /* Clock idle low, sample on rising edge. */ \ false, /* Not USART PRS input mode. */ \ 0, /* PRS channel 0. */ \ false, /* No AUTOTX mode. */ \ false, /* No AUTOCS mode */ \ } #elif (_SILICON_LABS_32B_SERIES > 0) /* Default USART Sync configuration for series 2 devices */ #define USART_INITSYNC_DEFAULT \ { \ usartEnable, /* Enable RX/TX when initialization is complete. */ \ 0, /* Use current configured reference clock for configuring baud rate. */ \ 1000000, /* 1 Mbits/s. */ \ usartDatabits8, /* 8 databits. */ \ true, /* Master mode. */ \ false, /* Send least significant bit first. */ \ usartClockMode0, /* Clock idle low, sample on rising edge. */ \ false, /* Not USART PRS input mode. */ \ 0, /* PRS channel 0. */ \ false, /* No AUTOTX mode. */ \ false, /* No AUTOCS mode. */ \ 0, /* Auto CS Hold cycles. */ \ 0 /* Auto CS Setup cycles. */ \ } #endif /** IrDA mode initialization structure. Inherited from asynchronous mode initialization structure. */ typedef struct { /** General Asynchronous initialization structure. */ USART_InitAsync_TypeDef async; /** Set to invert Rx signal before IrDA demodulator. */ bool irRxInv; /** Set to enable filter on IrDA demodulator. */ bool irFilt; /** Configure the pulse width generated by the IrDA modulator as a fraction * of the configured USART bit period. */ USART_IrDAPw_Typedef irPw; /** Enable the PRS channel selected by irPrsSel as input to IrDA module * instead of TX. */ bool irPrsEn; /** PRS can be used as input to the pulse modulator instead of TX. * This value selects the channel to use. */ USART_PRS_Channel_t irPrsSel; } USART_InitIrDA_TypeDef; /** Default configuration for IrDA mode initialization structure. */ #if defined(_EFM32_GECKO_FAMILY) /* Default USART IrDA struct for the EFM32G device */ #define USART_INITIRDA_DEFAULT \ { \ { \ usartEnable, /* Enable RX/TX when initialization is complete. */ \ 0, /* Use current configured reference clock for configuring baud rate. */ \ 115200, /* 115200 bits/s. */ \ usartOVS16, /* 16x oversampling. */ \ usartDatabits8, /* 8 data bits. */ \ usartEvenParity, /* Even parity. */ \ usartStopbits1, /* 1 stop bit. */ \ false, /* Auto CS functionality enable/disable switch */ \ }, \ false, /* Rx invert disabled. */ \ false, /* Filtering disabled. */ \ usartIrDAPwTHREE, /* Pulse width is set to ONE. */ \ false, /* Routing to PRS is disabled. */ \ 0 /* PRS channel 0. */ \ } #elif defined(_SILICON_LABS_32B_SERIES_0) /* Default USART IrDA struct for Series 0 devices */ #define USART_INITIRDA_DEFAULT \ { \ { \ usartEnable, /* Enable RX/TX when initialization is complete. */ \ 0, /* Use current configured reference clock for configuring baud rate. */ \ 115200, /* 115200 bits/s. */ \ usartOVS16, /* 16x oversampling. */ \ usartDatabits8, /* 8 data bits. */ \ usartEvenParity, /* Even parity. */ \ usartStopbits1, /* 1 stop bit. */ \ false, /* Do not disable majority vote. */ \ false, /* Not USART PRS input mode. */ \ 0, /* PRS channel 0. */ \ false, /* Auto CS functionality enable/disable switch */ \ }, \ false, /* Rx invert disabled. */ \ false, /* Filtering disabled. */ \ usartIrDAPwTHREE, /* Pulse width is set to ONE. */ \ false, /* Routing to PRS is disabled. */ \ 0 /* PRS channel 0. */ \ } #elif (_SILICON_LABS_32B_SERIES > 0) /* Default USART IrDA struct for Series 1 and Series 2 devices */ #define USART_INITIRDA_DEFAULT \ { \ { \ usartEnable, /* Enable RX/TX when initialization is complete. */ \ 0, /* Use current configured reference clock for configuring baud rate. */ \ 115200, /* 115200 bits/s. */ \ usartOVS16, /* 16x oversampling. */ \ usartDatabits8, /* 8 data bits. */ \ usartEvenParity, /* Even parity. */ \ usartStopbits1, /* 1 stop bit. */ \ false, /* Do not disable majority vote. */ \ false, /* Not USART PRS input mode. */ \ 0, /* PRS channel 0. */ \ false, /* Auto CS functionality enable/disable switch */ \ 0, /* Auto CS Hold cycles */ \ 0, /* Auto CS Setup cycles */ \ usartHwFlowControlNone /* No HW flow control */ \ }, \ false, /* Rx invert disabled. */ \ false, /* Filtering disabled. */ \ usartIrDAPwTHREE, /* Pulse width is set to ONE. */ \ false, /* Routing to PRS is disabled. */ \ 0 /* PRS channel 0. */ \ } #endif #if defined(_USART_I2SCTRL_MASK) /** I2S mode initialization structure. Inherited from synchronous mode initialization structure. */ typedef struct { /** General Synchronous initialization structure. */ USART_InitSync_TypeDef sync; /** I2S mode. */ USART_I2sFormat_TypeDef format; /** Delay on I2S data. Set to add a one-cycle delay between a transition * on the word-clock and the start of the I2S word. * Should be set for standard I2S format. */ bool delay; /** Separate DMA Request For Left/Right Data. */ bool dmaSplit; /** Justification of I2S data within the frame. */ USART_I2sJustify_TypeDef justify; /** Stereo or Mono, set to true for mono. */ bool mono; } USART_InitI2s_TypeDef; /** Default configuration for I2S mode initialization structure. */ #if defined(_EFM32_GECKO_FAMILY) /* Default USART Sync configuration for EFM32G devices. */ #define USART_INITI2S_DEFAULT \ { \ { \ usartEnable, /* Enable RX/TX when initialization is complete. */ \ 0, /* Use current configured reference clock for configuring baud rate. */ \ 1000000, /* 1 Mbits/s. */ \ usartDatabits16, /* 16 databits. */ \ true, /* Master mode. */ \ true, /* Most significant bit first. */ \ usartClockMode0, /* Clock idle low, sample on rising edge. */ \ false, /* No AUTOCS mode */ \ }, \ usartI2sFormatW16D16, /* 16-bit word, 16-bit data */ \ true, /* Delay on I2S data. */ \ false, /* No DMA split. */ \ usartI2sJustifyLeft,/* Data is left-justified within the frame */ \ false /* Stereo mode. */ \ } #elif defined(_SILICON_LABS_32B_SERIES_0) /* Default USART Sync configuration for series 0 devices. */ #define USART_INITI2S_DEFAULT \ { \ { \ usartEnable, /* Enable RX/TX when initialization is complete. */ \ 0, /* Use current configured reference clock for configuring baud rate. */ \ 1000000, /* 1 Mbits/s. */ \ usartDatabits16, /* 16 databits. */ \ true, /* Master mode. */ \ true, /* Most significant bit first. */ \ usartClockMode0, /* Clock idle low, sample on rising edge. */ \ false, /* Not USART PRS input mode. */ \ 0, /* PRS channel 0. */ \ false, /* No AUTOTX mode. */ \ false, /* No AUTOCS mode */ \ }, \ usartI2sFormatW16D16, /* 16-bit word, 16-bit data */ \ true, /* Delay on I2S data. */ \ false, /* No DMA split. */ \ usartI2sJustifyLeft,/* Data is left-justified within the frame */ \ false /* Stereo mode. */ \ } #elif (_SILICON_LABS_32B_SERIES > 0) /* Default USART Sync configuration for series 2 devices */ #define USART_INITI2S_DEFAULT \ { \ { \ usartEnableTx, /* Enable TX when init completed. */ \ 0, /* Use current configured reference clock for configuring baudrate. */ \ 1000000, /* Baudrate 1M bits/s. */ \ usartDatabits16, /* 16 databits. */ \ true, /* Operate as I2S master. */ \ true, /* Most significant bit first. */ \ usartClockMode0, /* Clock idle low, sample on rising edge. */ \ false, /* Don't enable USARTRx via PRS. */ \ usartPrsRxCh0, /* PRS channel selection (dummy). */ \ false, /* Disable AUTOTX mode. */ \ false, /* No AUTOCS mode */ \ 0, /* Auto CS Hold cycles */ \ 0 /* Auto CS Setup cycles */ \ }, \ usartI2sFormatW16D16, /* 16-bit word, 16-bit data */ \ true, /* Delay on I2S data. */ \ false, /* No DMA split. */ \ usartI2sJustifyLeft,/* Data is left-justified within the frame */ \ false /* Stereo mode. */ \ } #endif #endif /******************************************************************************* ***************************** PROTOTYPES ********************************** ******************************************************************************/ void USART_BaudrateAsyncSet(USART_TypeDef *usart, uint32_t refFreq, uint32_t baudrate, USART_OVS_TypeDef ovs); uint32_t USART_BaudrateCalc(uint32_t refFreq, uint32_t clkdiv, bool syncmode, USART_OVS_TypeDef ovs); uint32_t USART_BaudrateGet(USART_TypeDef *usart); void USART_BaudrateSyncSet(USART_TypeDef *usart, uint32_t refFreq, uint32_t baudrate); void USART_Enable(USART_TypeDef *usart, USART_Enable_TypeDef enable); void USART_InitAsync(USART_TypeDef *usart, const USART_InitAsync_TypeDef *init); void USART_InitSync(USART_TypeDef *usart, const USART_InitSync_TypeDef *init); void USARTn_InitIrDA(USART_TypeDef *usart, const USART_InitIrDA_TypeDef *init); #if defined(_USART_I2SCTRL_MASK) void USART_InitI2s(USART_TypeDef *usart, USART_InitI2s_TypeDef *init); #endif void USART_InitPrsTrigger(USART_TypeDef *usart, const USART_PrsTriggerInit_TypeDef *init); #if defined(DEFAULT_IRDA_USART) || defined(USART0) || ((USART_COUNT == 1) && defined(USART1)) /***************************************************************************//** * @brief * Initialization DEFAULT_IRDA_USART for asynchronous IrDA mode. * * @details * This function will configure basic settings in order to operate in * asynchronous IrDA mode. * * Special control setup not covered by this function must be done after * using this function by direct modification of the CTRL and IRCTRL * registers. * * Notice that pins used by the USART/UART module must be properly configured * by the user explicitly for the USART/UART to work as intended. * (When configuring pins, one should remember to consider the sequence of * configuration to avoid unintended pulses/glitches on output * pins.) * * @param[in] init * Pointer to initialization structure used to configure asynchronous IrDA setup. * * @deprecated * Deprecated function. New code should use USARTn_InitIrDA(). * This function uses DEFAULT_IRDA_USART, which unless otherwise specified, is * USART0 on most devices, and USART1 on devices that don't have a USART0. * ******************************************************************************/ __STATIC_INLINE void USART_InitIrDA(const USART_InitIrDA_TypeDef *init) { #if defined(DEFAULT_IRDA_USART) USART_TypeDef *usart = DEFAULT_IRDA_USART; #elif (USART_COUNT == 1) && defined(USART1) USART_TypeDef *usart = USART1; #else USART_TypeDef *usart = USART0; #endif USARTn_InitIrDA(usart, init); } #endif /***************************************************************************//** * @brief * Clear one or more pending USART interrupts. * * @param[in] usart * Pointer to USART/UART peripheral register block. * * @param[in] flags * Pending USART/UART interrupt source(s) to clear. Use one or more valid * interrupt flags for the USART module (USART_IF_nnn) OR'ed together. ******************************************************************************/ __STATIC_INLINE void USART_IntClear(USART_TypeDef *usart, uint32_t flags) { #if defined (USART_HAS_SET_CLEAR) usart->IF_CLR = flags; #else usart->IFC = flags; #endif } /***************************************************************************//** * @brief * Disable one or more USART interrupts. * * @param[in] usart * Pointer to USART/UART peripheral register block. * * @param[in] flags * USART/UART interrupt source(s) to disable. Use one or more valid * interrupt flags for the USART module (USART_IF_nnn) OR'ed together. ******************************************************************************/ __STATIC_INLINE void USART_IntDisable(USART_TypeDef *usart, uint32_t flags) { usart->IEN &= ~flags; } /***************************************************************************//** * @brief * Enable one or more USART interrupts. * * @note * Depending on the use, a pending interrupt may already be set prior to * enabling the interrupt. To ignore a pending interrupt, consider using * USART_IntClear() prior to enabling the interrupt. * * @param[in] usart * Pointer to USART/UART peripheral register block. * * @param[in] flags * USART/UART interrupt source(s) to enable. Use one or more valid * interrupt flags for the USART module (USART_IF_nnn) OR'ed together. ******************************************************************************/ __STATIC_INLINE void USART_IntEnable(USART_TypeDef *usart, uint32_t flags) { usart->IEN |= flags; } /***************************************************************************//** * @brief * Get pending USART interrupt flags. * * @note * The event bits are not cleared by the use of this function. * * @param[in] usart * Pointer to USART/UART peripheral register block. * * @return * USART/UART interrupt source(s) pending. Returns one or more valid * interrupt flags for the USART module (USART_IF_nnn) OR'ed together. ******************************************************************************/ __STATIC_INLINE uint32_t USART_IntGet(USART_TypeDef *usart) { return usart->IF; } /***************************************************************************//** * @brief * Get enabled and pending USART interrupt flags. * Useful for handling more interrupt sources in the same interrupt handler. * * @param[in] usart * Pointer to USART/UART peripheral register block. * * @note * Interrupt flags are not cleared by the use of this function. * * @return * Pending and enabled USART interrupt sources. * The return value is the bitwise AND combination of * - the OR combination of enabled interrupt sources in USARTx_IEN_nnn * register (USARTx_IEN_nnn) and * - the OR combination of valid interrupt flags of the USART module * (USARTx_IF_nnn). ******************************************************************************/ __STATIC_INLINE uint32_t USART_IntGetEnabled(USART_TypeDef *usart) { uint32_t ien; /* Store USARTx->IEN in temporary variable in order to define explicit order * of volatile accesses. */ ien = usart->IEN; /* Bitwise AND of pending and enabled interrupts. */ return usart->IF & ien; } /***************************************************************************//** * @brief * Set one or more pending USART interrupts from SW. * * @param[in] usart * Pointer to USART/UART peripheral register block. * * @param[in] flags * USART/UART interrupt source(s) to set to pending. Use one or more valid * interrupt flags for the USART module (USART_IF_nnn) OR'ed together. ******************************************************************************/ __STATIC_INLINE void USART_IntSet(USART_TypeDef *usart, uint32_t flags) { #if defined (USART_HAS_SET_CLEAR) usart->IF_SET = flags; #else usart->IFS = flags; #endif } /***************************************************************************//** * @brief * Get USART STATUS register. * * @param[in] usart * Pointer to USART/UART peripheral register block. * * @return * STATUS register value. * ******************************************************************************/ __STATIC_INLINE uint32_t USART_StatusGet(USART_TypeDef *usart) { return usart->STATUS; } void USART_Reset(USART_TypeDef *usart); uint8_t USART_Rx(USART_TypeDef *usart); uint16_t USART_RxDouble(USART_TypeDef *usart); uint32_t USART_RxDoubleExt(USART_TypeDef *usart); uint16_t USART_RxExt(USART_TypeDef *usart); /***************************************************************************//** * @brief * Receive one 4-8 bit frame, (or part of 10-16 bit frame). * * @details * This function is used to quickly receive one 4-8 bits frame by reading the * RXDATA register directly, without checking the STATUS register for the * RXDATAV flag. This can be useful from the RXDATAV interrupt handler, * i.e., waiting is superfluous, in order to quickly read the received data. * Please refer to @ref USART_RxDataXGet() for reception of 9 bit frames. * * @note * Since this function does not check whether the RXDATA register actually * holds valid data, it should only be used in situations when it is certain * that there is valid data, ensured by some external program routine, e.g., * when handling an RXDATAV interrupt. The @ref USART_Rx() is normally a * better choice if the validity of the RXDATA register is not certain. * * @note * Notice that possible parity/stop bits in asynchronous mode are not * considered part of specified frame bit length. * * @param[in] usart * Pointer to USART/UART peripheral register block. * * @return * Data received. ******************************************************************************/ __STATIC_INLINE uint8_t USART_RxDataGet(USART_TypeDef *usart) { return (uint8_t)usart->RXDATA; } /***************************************************************************//** * @brief * Receive two 4-8 bit frames, or one 10-16 bit frame. * * @details * This function is used to quickly receive one 10-16 bits frame or two 4-8 * bit frames by reading the RXDOUBLE register directly, without checking * the STATUS register for the RXDATAV flag. This can be useful from the * RXDATAV interrupt handler, i.e., waiting is superfluous, in order to * quickly read the received data. * This function is normally used to receive one frame when operating with * frame length 10-16 bits. Please refer to @ref USART_RxDoubleXGet() * for reception of two 9 bit frames. * * @note * Since this function does not check whether the RXDOUBLE register actually * holds valid data, it should only be used in situations when it is certain * that there is valid data, ensured by some external program routine, e.g., * when handling an RXDATAV interrupt. The @ref USART_RxDouble() is * normally a better choice if the validity of the RXDOUBLE register is not * certain. * * @note * Notice that possible parity/stop bits in asynchronous mode are not * considered part of specified frame bit length. * * @param[in] usart * Pointer to USART/UART peripheral register block. * * @return * Data received. ******************************************************************************/ __STATIC_INLINE uint16_t USART_RxDoubleGet(USART_TypeDef *usart) { return (uint16_t)usart->RXDOUBLE; } /***************************************************************************//** * @brief * Receive two 4-9 bit frames, or one 10-16 bit frame with extended * information. * * @details * This function is used to quickly receive one 10-16 bits frame or two 4-9 * bit frames by reading the RXDOUBLEX register directly, without checking * the STATUS register for the RXDATAV flag. This can be useful from the * RXDATAV interrupt handler, i.e., waiting is superfluous, in order to * quickly read the received data. * * @note * Since this function does not check whether the RXDOUBLEX register actually * holds valid data, it should only be used in situations when it is certain * that there is valid data, ensured by some external program routine, e.g., * when handling an RXDATAV interrupt. The @ref USART_RxDoubleExt() is * normally a better choice if the validity of the RXDOUBLEX register is not * certain. * * @note * Notice that possible parity/stop bits in asynchronous mode are not * considered part of specified frame bit length. * * @param[in] usart * Pointer to USART/UART peripheral register block. * * @return * Data received. ******************************************************************************/ __STATIC_INLINE uint32_t USART_RxDoubleXGet(USART_TypeDef *usart) { return usart->RXDOUBLEX; } /***************************************************************************//** * @brief * Receive one 4-9 bit frame, (or part of 10-16 bit frame) with extended * information. * * @details * This function is used to quickly receive one 4-9 bit frame, (or part of * 10-16 bit frame) with extended information by reading the RXDATAX register * directly, without checking the STATUS register for the RXDATAV flag. This * can be useful from the RXDATAV interrupt handler, i.e., waiting is * superfluous, in order to quickly read the received data. * * @note * Since this function does not check whether the RXDATAX register actually * holds valid data, it should only be used in situations when it is certain * that there is valid data, ensured by some external program routine, e.g., * when handling an RXDATAV interrupt. The @ref USART_RxExt() is normally * a better choice if the validity of the RXDATAX register is not certain. * * @note * Notice that possible parity/stop bits in asynchronous mode are not * considered part of specified frame bit length. * * @param[in] usart * Pointer to USART/UART peripheral register block. * * @return * Data received. ******************************************************************************/ __STATIC_INLINE uint16_t USART_RxDataXGet(USART_TypeDef *usart) { return (uint16_t)usart->RXDATAX; } uint8_t USART_SpiTransfer(USART_TypeDef *usart, uint8_t data); void USART_Tx(USART_TypeDef *usart, uint8_t data); void USART_TxDouble(USART_TypeDef *usart, uint16_t data); void USART_TxDoubleExt(USART_TypeDef *usart, uint32_t data); void USART_TxExt(USART_TypeDef *usart, uint16_t data); /** @} (end addtogroup USART) */ /** @} (end addtogroup emlib) */ #ifdef __cplusplus } #endif #endif /* defined(USART_COUNT) && (USART_COUNT > 0) */ #endif /* EM_USART_H */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/emlib/src/em_adc.c.
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/***************************************************************************//** * @file * @brief Analog to Digital Converter (ADC) Peripheral API * @version 5.7.0 ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * SPDX-License-Identifier: Zlib * * The licensor of this software is Silicon Laboratories Inc. * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be * appreciated but is not required. * 2. Altered source versions must be plainly marked as such, and must not be * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * ******************************************************************************/ #include "em_adc.h" #if defined(ADC_COUNT) && (ADC_COUNT > 0) #include "em_assert.h" #include "em_cmu.h" #include <stddef.h> /***************************************************************************//** * @addtogroup emlib * @{ ******************************************************************************/ /***************************************************************************//** * @addtogroup ADC * @brief Analog to Digital Converter (ADC) Peripheral API * @details * This module contains functions to control the ADC peripheral of Silicon * Labs 32-bit MCUs and SoCs. The ADC is used to convert analog signals into a * digital representation. * @{ ******************************************************************************/ /******************************************************************************* ******************************* DEFINES *********************************** ******************************************************************************/ /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ /** Validation of ADC register block pointer reference for assert statements. */ #if (ADC_COUNT == 1) #define ADC_REF_VALID(ref) ((ref) == ADC0) #elif (ADC_COUNT == 2) #define ADC_REF_VALID(ref) (((ref) == ADC0) || ((ref) == ADC1)) #endif /** Maximum ADC clock */ #if defined(_SILICON_LABS_32B_SERIES_0) #define ADC_MAX_CLOCK 13000000UL #else #define ADC_MAX_CLOCK 16000000UL #endif /** Minimum ADC clock */ #define ADC_MIN_CLOCK 32000UL /** Helper defines for selecting ADC calibration and DEVINFO register fields. */ #if defined(_DEVINFO_ADC0CAL0_1V25_GAIN_MASK) #define DEVINFO_ADC0_GAIN1V25_MASK _DEVINFO_ADC0CAL0_1V25_GAIN_MASK #elif defined(_DEVINFO_ADC0CAL0_GAIN1V25_MASK) #define DEVINFO_ADC0_GAIN1V25_MASK _DEVINFO_ADC0CAL0_GAIN1V25_MASK #endif #if defined(_DEVINFO_ADC0CAL0_1V25_GAIN_SHIFT) #define DEVINFO_ADC0_GAIN1V25_SHIFT _DEVINFO_ADC0CAL0_1V25_GAIN_SHIFT #elif defined(_DEVINFO_ADC0CAL0_GAIN1V25_SHIFT) #define DEVINFO_ADC0_GAIN1V25_SHIFT _DEVINFO_ADC0CAL0_GAIN1V25_SHIFT #endif #if defined(_DEVINFO_ADC0CAL0_1V25_OFFSET_MASK) #define DEVINFO_ADC0_OFFSET1V25_MASK _DEVINFO_ADC0CAL0_1V25_OFFSET_MASK #elif defined(_DEVINFO_ADC0CAL0_OFFSET1V25_MASK) #define DEVINFO_ADC0_OFFSET1V25_MASK _DEVINFO_ADC0CAL0_OFFSET1V25_MASK #endif #if defined(_DEVINFO_ADC0CAL0_1V25_OFFSET_SHIFT) #define DEVINFO_ADC0_OFFSET1V25_SHIFT _DEVINFO_ADC0CAL0_1V25_OFFSET_SHIFT #elif defined(_DEVINFO_ADC0CAL0_OFFSET1V25_SHIFT) #define DEVINFO_ADC0_OFFSET1V25_SHIFT _DEVINFO_ADC0CAL0_OFFSET1V25_SHIFT #endif #if defined(_DEVINFO_ADC0CAL0_2V5_GAIN_MASK) #define DEVINFO_ADC0_GAIN2V5_MASK _DEVINFO_ADC0CAL0_2V5_GAIN_MASK #elif defined(_DEVINFO_ADC0CAL0_GAIN2V5_MASK) #define DEVINFO_ADC0_GAIN2V5_MASK _DEVINFO_ADC0CAL0_GAIN2V5_MASK #endif #if defined(_DEVINFO_ADC0CAL0_2V5_GAIN_SHIFT) #define DEVINFO_ADC0_GAIN2V5_SHIFT _DEVINFO_ADC0CAL0_2V5_GAIN_SHIFT #elif defined(_DEVINFO_ADC0CAL0_GAIN2V5_SHIFT) #define DEVINFO_ADC0_GAIN2V5_SHIFT _DEVINFO_ADC0CAL0_GAIN2V5_SHIFT #endif #if defined(_DEVINFO_ADC0CAL0_2V5_OFFSET_MASK) #define DEVINFO_ADC0_OFFSET2V5_MASK _DEVINFO_ADC0CAL0_2V5_OFFSET_MASK #elif defined(_DEVINFO_ADC0CAL0_OFFSET2V5_MASK) #define DEVINFO_ADC0_OFFSET2V5_MASK _DEVINFO_ADC0CAL0_OFFSET2V5_MASK #endif #if defined(_DEVINFO_ADC0CAL0_2V5_OFFSET_SHIFT) #define DEVINFO_ADC0_OFFSET2V5_SHIFT _DEVINFO_ADC0CAL0_2V5_OFFSET_SHIFT #elif defined(_DEVINFO_ADC0CAL0_OFFSET2V5_SHIFT) #define DEVINFO_ADC0_OFFSET2V5_SHIFT _DEVINFO_ADC0CAL0_OFFSET2V5_SHIFT #endif #if defined(_DEVINFO_ADC0CAL1_VDD_GAIN_MASK) #define DEVINFO_ADC0_GAINVDD_MASK _DEVINFO_ADC0CAL1_VDD_GAIN_MASK #elif defined(_DEVINFO_ADC0CAL1_GAINVDD_MASK) #define DEVINFO_ADC0_GAINVDD_MASK _DEVINFO_ADC0CAL1_GAINVDD_MASK #endif #if defined(_DEVINFO_ADC0CAL1_VDD_GAIN_SHIFT) #define DEVINFO_ADC0_GAINVDD_SHIFT _DEVINFO_ADC0CAL1_VDD_GAIN_SHIFT #elif defined(_DEVINFO_ADC0CAL1_GAINVDD_SHIFT) #define DEVINFO_ADC0_GAINVDD_SHIFT _DEVINFO_ADC0CAL1_GAINVDD_SHIFT #endif #if defined(_DEVINFO_ADC0CAL1_VDD_OFFSET_MASK) #define DEVINFO_ADC0_OFFSETVDD_MASK _DEVINFO_ADC0CAL1_VDD_OFFSET_MASK #elif defined(_DEVINFO_ADC0CAL1_OFFSETVDD_MASK) #define DEVINFO_ADC0_OFFSETVDD_MASK _DEVINFO_ADC0CAL1_OFFSETVDD_MASK #endif #if defined(_DEVINFO_ADC0CAL1_VDD_OFFSET_SHIFT) #define DEVINFO_ADC0_OFFSETVDD_SHIFT _DEVINFO_ADC0CAL1_VDD_OFFSET_SHIFT #elif defined(_DEVINFO_ADC0CAL1_OFFSETVDD_SHIFT) #define DEVINFO_ADC0_OFFSETVDD_SHIFT _DEVINFO_ADC0CAL1_OFFSETVDD_SHIFT #endif #if defined(_DEVINFO_ADC0CAL1_5VDIFF_GAIN_MASK) #define DEVINFO_ADC0_GAIN5VDIFF_MASK _DEVINFO_ADC0CAL1_5VDIFF_GAIN_MASK #elif defined(_DEVINFO_ADC0CAL1_GAIN5VDIFF_MASK) #define DEVINFO_ADC0_GAIN5VDIFF_MASK _DEVINFO_ADC0CAL1_GAIN5VDIFF_MASK #endif #if defined(_DEVINFO_ADC0CAL1_5VDIFF_GAIN_SHIFT) #define DEVINFO_ADC0_GAIN5VDIFF_SHIFT _DEVINFO_ADC0CAL1_5VDIFF_GAIN_SHIFT #elif defined(_DEVINFO_ADC0CAL1_GAIN5VDIFF_SHIFT) #define DEVINFO_ADC0_GAIN5VDIFF_SHIFT _DEVINFO_ADC0CAL1_GAIN5VDIFF_SHIFT #endif #if defined(_DEVINFO_ADC0CAL1_5VDIFF_OFFSET_MASK) #define DEVINFO_ADC0_OFFSET5VDIFF_MASK _DEVINFO_ADC0CAL1_5VDIFF_OFFSET_MASK #elif defined(_DEVINFO_ADC0CAL1_OFFSET5VDIFF_MASK) #define DEVINFO_ADC0_OFFSET5VDIFF_MASK _DEVINFO_ADC0CAL1_OFFSET5VDIFF_MASK #endif #if defined(_DEVINFO_ADC0CAL1_5VDIFF_OFFSET_SHIFT) #define DEVINFO_ADC0_OFFSET5VDIFF_SHIFT _DEVINFO_ADC0CAL1_5VDIFF_OFFSET_SHIFT #elif defined(_DEVINFO_ADC0CAL1_OFFSET5VDIFF_SHIFT) #define DEVINFO_ADC0_OFFSET5VDIFF_SHIFT _DEVINFO_ADC0CAL1_OFFSET5VDIFF_SHIFT #endif #if defined(_DEVINFO_ADC0CAL2_2XVDDVSS_OFFSET_MASK) #define DEVINFO_ADC0_OFFSET2XVDD_MASK _DEVINFO_ADC0CAL2_2XVDDVSS_OFFSET_MASK #elif defined(_DEVINFO_ADC0CAL2_OFFSET2XVDD_MASK) #define DEVINFO_ADC0_OFFSET2XVDD_MASK _DEVINFO_ADC0CAL2_OFFSET2XVDD_MASK #endif #if defined(_DEVINFO_ADC0CAL2_2XVDDVSS_OFFSET_SHIFT) #define DEVINFO_ADC0_OFFSET2XVDD_SHIFT _DEVINFO_ADC0CAL2_2XVDDVSS_OFFSET_SHIFT #elif defined(_DEVINFO_ADC0CAL2_OFFSET2XVDD_SHIFT) #define DEVINFO_ADC0_OFFSET2XVDD_SHIFT _DEVINFO_ADC0CAL2_OFFSET2XVDD_SHIFT #endif /** @endcond */ /******************************************************************************* *************************** LOCAL FUNCTIONS ******************************* ******************************************************************************/ /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ /***************************************************************************//** * @brief * Load the ADC calibration register for a selected reference and conversion mode. * * @details * During production, calibration values are stored in the device * information page for internal references. Notice that, for external references, * calibration values must be determined explicitly. This function * will not modify the calibration register for external references. * * @param[in] adc * A pointer to ADC peripheral register block. * * @param[in] ref * A reference to load calibrated values for. No values are loaded for * external references. * * @param[in] setScanCal * Select scan mode (true) or single mode (false) calibration load. ******************************************************************************/ static void ADC_LoadDevinfoCal(ADC_TypeDef *adc, ADC_Ref_TypeDef ref, bool setScanCal) { uint32_t calReg; uint32_t newCal; uint32_t mask; uint32_t shift; __IM uint32_t * diCalReg; if (setScanCal) { shift = _ADC_CAL_SCANOFFSET_SHIFT; mask = ~(_ADC_CAL_SCANOFFSET_MASK #if defined(_ADC_CAL_SCANOFFSETINV_MASK) | _ADC_CAL_SCANOFFSETINV_MASK #endif | _ADC_CAL_SCANGAIN_MASK); } else { shift = _ADC_CAL_SINGLEOFFSET_SHIFT; mask = ~(_ADC_CAL_SINGLEOFFSET_MASK #if defined(_ADC_CAL_SINGLEOFFSETINV_MASK) | _ADC_CAL_SINGLEOFFSETINV_MASK #endif | _ADC_CAL_SINGLEGAIN_MASK); } calReg = adc->CAL & mask; newCal = 0; if (adc == ADC0) { diCalReg = &DEVINFO->ADC0CAL0; } #if defined(ADC1) else if (adc == ADC1) { diCalReg = &DEVINFO->ADC1CAL0; } #endif else { return; } switch (ref) { case adcRef1V25: newCal |= ((diCalReg[0] & DEVINFO_ADC0_GAIN1V25_MASK) >> DEVINFO_ADC0_GAIN1V25_SHIFT) << _ADC_CAL_SINGLEGAIN_SHIFT; newCal |= ((diCalReg[0] & DEVINFO_ADC0_OFFSET1V25_MASK) >> DEVINFO_ADC0_OFFSET1V25_SHIFT) << _ADC_CAL_SINGLEOFFSET_SHIFT; #if defined(_ADC_CAL_SINGLEOFFSETINV_MASK) newCal |= ((diCalReg[0] & _DEVINFO_ADC0CAL0_NEGSEOFFSET1V25_MASK) >> _DEVINFO_ADC0CAL0_NEGSEOFFSET1V25_SHIFT) << _ADC_CAL_SINGLEOFFSETINV_SHIFT; #endif break; case adcRef2V5: newCal |= ((diCalReg[0] & DEVINFO_ADC0_GAIN2V5_MASK) >> DEVINFO_ADC0_GAIN2V5_SHIFT) << _ADC_CAL_SINGLEGAIN_SHIFT; newCal |= ((diCalReg[0] & DEVINFO_ADC0_OFFSET2V5_MASK) >> DEVINFO_ADC0_OFFSET2V5_SHIFT) << _ADC_CAL_SINGLEOFFSET_SHIFT; #if defined(_ADC_CAL_SINGLEOFFSETINV_MASK) newCal |= ((diCalReg[0] & _DEVINFO_ADC0CAL0_NEGSEOFFSET2V5_MASK) >> _DEVINFO_ADC0CAL0_NEGSEOFFSET2V5_SHIFT) << _ADC_CAL_SINGLEOFFSETINV_SHIFT; #endif break; case adcRefVDD: newCal |= ((diCalReg[1] & DEVINFO_ADC0_GAINVDD_MASK) >> DEVINFO_ADC0_GAINVDD_SHIFT) << _ADC_CAL_SINGLEGAIN_SHIFT; newCal |= ((diCalReg[1] & DEVINFO_ADC0_OFFSETVDD_MASK) >> DEVINFO_ADC0_OFFSETVDD_SHIFT) << _ADC_CAL_SINGLEOFFSET_SHIFT; #if defined(_ADC_CAL_SINGLEOFFSETINV_MASK) newCal |= ((diCalReg[1] & _DEVINFO_ADC0CAL1_NEGSEOFFSETVDD_MASK) >> _DEVINFO_ADC0CAL1_NEGSEOFFSETVDD_SHIFT) << _ADC_CAL_SINGLEOFFSETINV_SHIFT; #endif break; case adcRef5VDIFF: newCal |= ((diCalReg[1] & DEVINFO_ADC0_GAIN5VDIFF_MASK) >> DEVINFO_ADC0_GAIN5VDIFF_SHIFT) << _ADC_CAL_SINGLEGAIN_SHIFT; newCal |= ((diCalReg[1] & DEVINFO_ADC0_OFFSET5VDIFF_MASK) >> DEVINFO_ADC0_OFFSET5VDIFF_SHIFT) << _ADC_CAL_SINGLEOFFSET_SHIFT; #if defined(_ADC_CAL_SINGLEOFFSETINV_MASK) newCal |= ((diCalReg[1] & _DEVINFO_ADC0CAL1_NEGSEOFFSET5VDIFF_MASK) >> _DEVINFO_ADC0CAL1_NEGSEOFFSET5VDIFF_SHIFT) << _ADC_CAL_SINGLEOFFSETINV_SHIFT; #endif break; case adcRef2xVDD: /* There is no gain calibration for this reference */ newCal |= ((diCalReg[2] & DEVINFO_ADC0_OFFSET2XVDD_MASK) >> DEVINFO_ADC0_OFFSET2XVDD_SHIFT) << _ADC_CAL_SINGLEOFFSET_SHIFT; #if defined(_ADC_CAL_SINGLEOFFSETINV_MASK) newCal |= ((diCalReg[2] & _DEVINFO_ADC0CAL2_NEGSEOFFSET2XVDD_MASK) >> _DEVINFO_ADC0CAL2_NEGSEOFFSET2XVDD_SHIFT) << _ADC_CAL_SINGLEOFFSETINV_SHIFT; #endif break; #if defined(_ADC_SINGLECTRLX_VREFSEL_VDDXWATT) case adcRefVddxAtt: newCal |= ((diCalReg[1] & DEVINFO_ADC0_GAINVDD_MASK) >> DEVINFO_ADC0_GAINVDD_SHIFT) << _ADC_CAL_SINGLEGAIN_SHIFT; newCal |= ((diCalReg[1] & DEVINFO_ADC0_OFFSETVDD_MASK) >> DEVINFO_ADC0_OFFSETVDD_SHIFT) << _ADC_CAL_SINGLEOFFSET_SHIFT; newCal |= ((diCalReg[1] & _DEVINFO_ADC0CAL1_NEGSEOFFSETVDD_MASK) >> _DEVINFO_ADC0CAL1_NEGSEOFFSETVDD_SHIFT) << _ADC_CAL_SINGLEOFFSETINV_SHIFT; break; #endif /* For external references, the calibration must be determined for the specific application and set by the user. Calibration data is also not available for the internal references adcRefVBGR, adcRefVEntropy, and adcRefVBGRlow. */ default: newCal = 0; break; } adc->CAL = calReg | (newCal << shift); } /** @endcond */ /******************************************************************************* ************************** GLOBAL FUNCTIONS ******************************* ******************************************************************************/ /***************************************************************************//** * @brief * Initialize ADC. * * @details * Initializes common parts for both single conversion and scan sequence. * In addition, single and/or scan control configuration must be done. See * @ref ADC_InitSingle() and @ref ADC_InitScan() respectively. * For ADC architectures with the ADCn->SCANINPUTSEL register, use * @ref ADC_ScanSingleEndedInputAdd() to configure single-ended scan inputs or * @ref ADC_ScanDifferentialInputAdd() to configure differential scan inputs. * @ref ADC_ScanInputClear() is also provided for applications that need to update * the input configuration. * * @note * This function will stop any ongoing conversion. * * @param[in] adc * A pointer to the ADC peripheral register block. * * @param[in] init * A pointer to the ADC initialization structure. ******************************************************************************/ void ADC_Init(ADC_TypeDef *adc, const ADC_Init_TypeDef *init) { uint32_t tmp; uint8_t presc = init->prescale; EFM_ASSERT(ADC_REF_VALID(adc)); if (presc == 0U) { /* Assume maximum ADC clock for prescaler 0. */ presc = ADC_PrescaleCalc(ADC_MAX_CLOCK, 0); } else { /* Check prescaler bounds against ADC_MAX_CLOCK and ADC_MIN_CLOCK. */ #if defined(_ADC_CTRL_ADCCLKMODE_MASK) if ((adc->CTRL & _ADC_CTRL_ADCCLKMODE_MASK) == ADC_CTRL_ADCCLKMODE_SYNC) #endif { EFM_ASSERT(presc >= ADC_PrescaleCalc(ADC_MAX_CLOCK, 0)); EFM_ASSERT(presc <= ADC_PrescaleCalc(ADC_MIN_CLOCK, 0)); } } /* Make sure conversion is not in progress. */ adc->CMD = ADC_CMD_SINGLESTOP | ADC_CMD_SCANSTOP; tmp = ((uint32_t)(init->ovsRateSel) << _ADC_CTRL_OVSRSEL_SHIFT) | (((uint32_t)(init->timebase) << _ADC_CTRL_TIMEBASE_SHIFT) & _ADC_CTRL_TIMEBASE_MASK) | (((uint32_t)(presc) << _ADC_CTRL_PRESC_SHIFT) & _ADC_CTRL_PRESC_MASK) #if defined (_ADC_CTRL_LPFMODE_MASK) | ((uint32_t)(init->lpfMode) << _ADC_CTRL_LPFMODE_SHIFT) #endif | ((uint32_t)(init->warmUpMode) << _ADC_CTRL_WARMUPMODE_SHIFT); if (init->tailgate) { tmp |= ADC_CTRL_TAILGATE; } adc->CTRL = tmp; #if defined(_ADC_CTRL_ADCCLKMODE_MASK) /* Set ADC EM2 clock configuration. */ BUS_RegMaskedWrite(&adc->CTRL, _ADC_CTRL_ADCCLKMODE_MASK | _ADC_CTRL_ASYNCCLKEN_MASK, (uint32_t)init->em2ClockConfig); #if defined(_SILICON_LABS_32B_SERIES_1) /* In asynch clock mode assert that the ADC clock frequency is less or equal to 2/3 of the HFPER/HFPERC clock frequency. */ if ((adc->CTRL & _ADC_CTRL_ADCCLKMODE_MASK) == ADC_CTRL_ADCCLKMODE_ASYNC) { CMU_Clock_TypeDef asyncClk = cmuClock_ADC0ASYNC; uint32_t adcClkFreq; uint32_t hfperClkFreq = 0; #if defined(_CMU_ADCCTRL_ADC1CLKSEL_MASK) if ( adc == ADC1 ) { asyncClk = cmuClock_ADC1ASYNC; } #endif adcClkFreq = CMU_ClockFreqGet(asyncClk); if (adc == ADC0) { hfperClkFreq = CMU_ClockFreqGet(cmuClock_ADC0); #if defined(ADC1) } else if (adc == ADC1) { hfperClkFreq = CMU_ClockFreqGet(cmuClock_ADC1); #endif } else { EFM_ASSERT(false); } EFM_ASSERT(hfperClkFreq >= (adcClkFreq * 3) / 2); } #endif /* #if defined(_SILICON_LABS_32B_SERIES_1) */ #endif /* #if defined(_ADC_CTRL_ADCCLKMODE_MASK) */ #if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) /* A debugger can trigger the SCANUF interrupt on EFM32xG1 or EFR32xG1 */ ADC_IntClear(adc, ADC_IFC_SCANUF); #endif } #if defined(_ADC_SCANINPUTSEL_MASK) /***************************************************************************//** * @brief * Clear ADC scan input configuration. * * @param[in] scanInit * Structure to hold the scan configuration and input configuration. ******************************************************************************/ void ADC_ScanInputClear(ADC_InitScan_TypeDef *scanInit) { /* Clear the input configuration. */ /* Select none. */ scanInit->scanInputConfig.scanInputSel = ADC_SCANINPUTSEL_NONE; scanInit->scanInputConfig.scanInputEn = 0; /* Default alternative negative inputs. */ scanInit->scanInputConfig.scanNegSel = _ADC_SCANNEGSEL_RESETVALUE; } /***************************************************************************//** * @brief * Initialize ADC scan single-ended input configuration. * * @details * Set a configuration for ADC scan conversion with single-ended inputs. The * ADC_InitScan_TypeDef structure updated from this function will be passed to * ADC_InitScan(). * * @param[in] inputGroup * ADC scan input group. See section 25.3.4 in the reference manual for * more information. * * @param[in] singleEndedSel * APORT select. * * @return * Scan ID of selected ADC input. See section 25.3.4 in the reference manual for * more information. Note that the returned integer represents the bit position * in ADCn_SCANMASK set by this function. The accumulated mask is stored in * scanInit->scanInputConfig->scanInputEn. ******************************************************************************/ uint32_t ADC_ScanSingleEndedInputAdd(ADC_InitScan_TypeDef *scanInit, ADC_ScanInputGroup_TypeDef inputGroup, ADC_PosSel_TypeDef singleEndedSel) { uint32_t currentSel; uint32_t newSel; uint32_t scanId; scanInit->diff = false; /* Check for unsupported APORTs. */ EFM_ASSERT((singleEndedSel <= adcPosSelAPORT0YCH0) || (singleEndedSel >= adcPosSelAPORT0YCH15)); /* Check for an illegal group. */ EFM_ASSERT((unsigned)inputGroup < 4U); /* Decode the input group select by shifting right by 3. */ newSel = (unsigned)singleEndedSel >> 3; currentSel = (scanInit->scanInputConfig.scanInputSel >> ((unsigned)inputGroup * 8U)) & 0xFFU; /* If none selected. */ if (currentSel == ADC_SCANINPUTSEL_GROUP_NONE) { scanInit->scanInputConfig.scanInputSel &= ~(0xFFU << ((unsigned)inputGroup * 8U)); scanInit->scanInputConfig.scanInputSel |= newSel << ((unsigned)inputGroup * 8U); } else if (currentSel == newSel) { /* Ok, but do nothing. */ } else { /* Invalid channel range. A range is already selected for this group. */ EFM_ASSERT(false); } /* Update and return scan input enable mask (SCANMASK). */ scanId = ((unsigned)inputGroup * 8U) + ((unsigned)singleEndedSel & 0x7U); EFM_ASSERT(scanId < 32U); scanInit->scanInputConfig.scanInputEn |= 0x1UL << scanId; return scanId; } /***************************************************************************//** * @brief * Initialize the ADC scan differential input configuration. * * @details * Set a configuration for the ADC scan conversion with differential inputs. The * ADC_InitScan_TypeDef structure updated by this function should be passed to * ADC_InitScan(). * * @param[in] scanInit * Structure to hold the scan and input configuration. * * @param[in] inputGroup * ADC scan input group. See section 25.3.4 in the reference manual for * more information. * * @param[in] posSel * APORT bus pair select. The negative terminal is implicitly selected by * the positive terminal. * * @param[in] negInput * ADC scan alternative negative input. Set to adcScanNegInputDefault to select * a default negative input (implicit from posSel). * * @return * Scan ID of the selected ADC input. See section 25.3.4 in the reference manual for * more information. Note that the returned integer represents the bit position * in ADCn_SCANMASK set by this function. The accumulated mask is stored in the * scanInit->scanInputConfig->scanInputEn. ******************************************************************************/ uint32_t ADC_ScanDifferentialInputAdd(ADC_InitScan_TypeDef *scanInit, ADC_ScanInputGroup_TypeDef inputGroup, ADC_PosSel_TypeDef posSel, ADC_ScanNegInput_TypeDef negInput) { uint32_t negInputRegMask = 0; uint32_t negInputRegShift = 0; uint32_t negInputRegVal = 0; uint32_t scanId; /* Perform a single-ended initialization, then update for differential scan. */ scanId = ADC_ScanSingleEndedInputAdd(scanInit, inputGroup, posSel); /* Reset to differential mode. */ scanInit->diff = true; /* Set negative ADC input unless the default is selected. */ if (negInput != adcScanNegInputDefault) { if (scanId == 0U) { negInputRegMask = _ADC_SCANNEGSEL_INPUT0NEGSEL_MASK; negInputRegShift = _ADC_SCANNEGSEL_INPUT0NEGSEL_SHIFT; EFM_ASSERT((unsigned)inputGroup == 0U); } else if (scanId == 2U) { negInputRegMask = _ADC_SCANNEGSEL_INPUT2NEGSEL_MASK; negInputRegShift = _ADC_SCANNEGSEL_INPUT2NEGSEL_SHIFT; EFM_ASSERT((unsigned)inputGroup == 0U); } else if (scanId == 4U) { negInputRegMask = _ADC_SCANNEGSEL_INPUT4NEGSEL_MASK; negInputRegShift = _ADC_SCANNEGSEL_INPUT4NEGSEL_SHIFT; EFM_ASSERT((unsigned)inputGroup == 0U); } else if (scanId == 6U) { negInputRegMask = _ADC_SCANNEGSEL_INPUT6NEGSEL_MASK; negInputRegShift = _ADC_SCANNEGSEL_INPUT6NEGSEL_SHIFT; EFM_ASSERT((unsigned)inputGroup == 0U); } else if (scanId == 9U) { negInputRegMask = _ADC_SCANNEGSEL_INPUT9NEGSEL_MASK; negInputRegShift = _ADC_SCANNEGSEL_INPUT9NEGSEL_SHIFT; EFM_ASSERT((unsigned)inputGroup == 1U); } else if (scanId == 11U) { negInputRegMask = _ADC_SCANNEGSEL_INPUT11NEGSEL_MASK; negInputRegShift = _ADC_SCANNEGSEL_INPUT11NEGSEL_SHIFT; EFM_ASSERT((unsigned)inputGroup == 1U); } else if (scanId == 13U) { negInputRegMask = _ADC_SCANNEGSEL_INPUT13NEGSEL_MASK; negInputRegShift = _ADC_SCANNEGSEL_INPUT13NEGSEL_SHIFT; EFM_ASSERT((unsigned)inputGroup == 1U); } else if (scanId == 15U) { negInputRegMask = _ADC_SCANNEGSEL_INPUT15NEGSEL_MASK; negInputRegShift = _ADC_SCANNEGSEL_INPUT15NEGSEL_SHIFT; EFM_ASSERT((unsigned)inputGroup == 1U); } else { /* The positive input does not have a negative input option (negInput is posInput + 1). */ EFM_ASSERT(false); } /* Find ADC_SCANNEGSEL_CHxNSEL value for positive input 0, 2, 4, and 6. */ if ((unsigned)inputGroup == 0U) { switch (negInput) { case adcScanNegInput1: negInputRegVal = _ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT1; break; case adcScanNegInput3: negInputRegVal = _ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT3; break; case adcScanNegInput5: negInputRegVal = _ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT5; break; case adcScanNegInput7: negInputRegVal = _ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT7; break; default: /* An invalid selection. Options are input 1, 3, 5 and 7. */ EFM_ASSERT(false); break; } } else { /* inputGroup == 1 */ /* Find ADC_SCANNEGSEL_CHxNSEL value for positive input 9, 11, 13, and 15. */ switch (negInput) { case adcScanNegInput8: negInputRegVal = _ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT8; break; case adcScanNegInput10: negInputRegVal = _ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT10; break; case adcScanNegInput12: negInputRegVal = _ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT12; break; case adcScanNegInput14: negInputRegVal = _ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT14; break; default: /* Invalid selection. Options are input 8, 10, 12, and 14. */ EFM_ASSERT(false); break; } } /* Update configuration. */ scanInit->scanInputConfig.scanNegSel &= ~negInputRegMask; scanInit->scanInputConfig.scanNegSel |= negInputRegVal << negInputRegShift; } return scanId; } #endif /***************************************************************************//** * @brief * Initialize the ADC scan sequence. * * @details * See ADC_Start() for starting a scan sequence. * * When selecting an external reference, the gain and offset calibration * must be set explicitly (CAL register). For other references, the * calibration is updated with values defined during manufacturing. * For ADC architectures with the ADCn->SCANINPUTSEL register, use * @ref ADC_ScanSingleEndedInputAdd() to configure single-ended scan inputs or * @ref ADC_ScanDifferentialInputAdd() to configure differential scan inputs. * @ref ADC_ScanInputClear() is also provided for applications that need to update * the input configuration. * * @note * This function will stop any ongoing scan sequence. * * @param[in] adc * A pointer to the ADC peripheral register block. * * @param[in] init * A pointer to the ADC initialization structure. ******************************************************************************/ void ADC_InitScan(ADC_TypeDef *adc, const ADC_InitScan_TypeDef *init) { uint32_t tmp; EFM_ASSERT(ADC_REF_VALID(adc)); /* Make sure scan sequence is not in progress. */ adc->CMD = ADC_CMD_SCANSTOP; /* Load calibration data for a selected reference. */ ADC_LoadDevinfoCal(adc, init->reference, true); tmp = 0UL #if defined (_ADC_SCANCTRL_PRSSEL_MASK) | ((uint32_t)init->prsSel << _ADC_SCANCTRL_PRSSEL_SHIFT) #endif | ((uint32_t)init->acqTime << _ADC_SCANCTRL_AT_SHIFT) #if defined (_ADC_SCANCTRL_INPUTMASK_MASK) | init->input #endif | ((uint32_t)init->resolution << _ADC_SCANCTRL_RES_SHIFT); if (init->prsEnable) { tmp |= ADC_SCANCTRL_PRSEN; } if (init->leftAdjust) { tmp |= ADC_SCANCTRL_ADJ_LEFT; } #if defined(_ADC_SCANCTRL_INPUTMASK_MASK) if (init->diff) #elif defined(_ADC_SCANINPUTSEL_MASK) if (init->diff) #endif { tmp |= ADC_SCANCTRL_DIFF; } if (init->rep) { #if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) /* Scan repeat mode does not work on EFM32JG1, EFM32PG1, or EFR32xG1x devices. * The errata is called ADC_E211 in the errata document. */ EFM_ASSERT(false); #endif tmp |= ADC_SCANCTRL_REP; } /* Set scan reference. Check if the reference configuration is extended to SCANCTRLX. */ #if defined (_ADC_SCANCTRLX_VREFSEL_MASK) if (((uint32_t)init->reference & ADC_CTRLX_VREFSEL_REG) != 0UL) { /* Select the extension register. */ tmp |= ADC_SCANCTRL_REF_CONF; } else { tmp |= (uint32_t)init->reference << _ADC_SCANCTRL_REF_SHIFT; } #else tmp |= init->reference << _ADC_SCANCTRL_REF_SHIFT; #endif #if defined(_ADC_SCANCTRL_INPUTMASK_MASK) tmp |= init->input; #endif adc->SCANCTRL = tmp; /* Update SINGLECTRLX for reference select and PRS select. */ #if defined (_ADC_SCANCTRLX_MASK) tmp = adc->SCANCTRLX & ~(_ADC_SCANCTRLX_VREFSEL_MASK | _ADC_SCANCTRLX_PRSSEL_MASK | _ADC_SCANCTRLX_FIFOOFACT_MASK); if (((uint32_t)init->reference & ADC_CTRLX_VREFSEL_REG) != 0UL) { tmp |= ((uint32_t)init->reference & ~ADC_CTRLX_VREFSEL_REG) << _ADC_SCANCTRLX_VREFSEL_SHIFT; } tmp |= (uint32_t)init->prsSel << _ADC_SCANCTRLX_PRSSEL_SHIFT; if (init->fifoOverwrite) { tmp |= ADC_SCANCTRLX_FIFOOFACT_OVERWRITE; } adc->SCANCTRLX = tmp; #endif #if defined(_ADC_CTRL_SCANDMAWU_MASK) BUS_RegBitWrite(&adc->CTRL, _ADC_CTRL_SCANDMAWU_SHIFT, (uint32_t)init->scanDmaEm2Wu); #endif /* Write the scan input configuration. */ #if defined(_ADC_SCANINPUTSEL_MASK) /* Check for valid scan input configuration. Use @ref ADC_ScanInputClear(), @ref ADC_ScanSingleEndedInputAdd(), and @ref ADC_ScanDifferentialInputAdd() to set the scan input configuration. */ EFM_ASSERT(init->scanInputConfig.scanInputSel != ADC_SCANINPUTSEL_NONE); adc->SCANINPUTSEL = init->scanInputConfig.scanInputSel; adc->SCANMASK = init->scanInputConfig.scanInputEn; adc->SCANNEGSEL = init->scanInputConfig.scanNegSel; #endif /* Assert for any APORT bus conflicts programming errors. */ #if defined(_ADC_BUSCONFLICT_MASK) tmp = adc->BUSREQ; EFM_ASSERT(!(tmp & adc->BUSCONFLICT)); EFM_ASSERT(!(adc->STATUS & _ADC_STATUS_PROGERR_MASK)); #endif } /***************************************************************************//** * @brief * Initialize the single ADC sample conversion. * * @details * See ADC_Start() for starting a single conversion. * * When selecting an external reference, the gain and offset calibration * must be set explicitly (CAL register). For other references, the * calibration is updated with values defined during manufacturing. * * @note * This function will stop any ongoing single conversion. * * @cond DOXYDOC_P2_DEVICE * @note * This function will set the BIASPROG_GPBIASACC bit when selecting the * internal temperature sensor and clear the bit otherwise. Any * application that depends on the state of the BIASPROG_GPBIASACC bit should * modify it after a call to this function. * @endcond * * @param[in] adc * A pointer to the ADC peripheral register block. * * @param[in] init * A pointer to the ADC initialization structure. ******************************************************************************/ void ADC_InitSingle(ADC_TypeDef *adc, const ADC_InitSingle_TypeDef *init) { uint32_t tmp; EFM_ASSERT(ADC_REF_VALID(adc)); /* Make sure single conversion is not in progress. */ adc->CMD = ADC_CMD_SINGLESTOP; /* Load calibration data for selected reference. */ ADC_LoadDevinfoCal(adc, init->reference, false); tmp = 0UL #if defined(_ADC_SINGLECTRL_PRSSEL_MASK) | ((uint32_t)init->prsSel << _ADC_SINGLECTRL_PRSSEL_SHIFT) #endif | ((uint32_t)init->acqTime << _ADC_SINGLECTRL_AT_SHIFT) #if defined(_ADC_SINGLECTRL_INPUTSEL_MASK) | (init->input << _ADC_SINGLECTRL_INPUTSEL_SHIFT) #endif #if defined(_ADC_SINGLECTRL_POSSEL_MASK) | ((uint32_t)init->posSel << _ADC_SINGLECTRL_POSSEL_SHIFT) #endif #if defined(_ADC_SINGLECTRL_NEGSEL_MASK) | ((uint32_t)init->negSel << _ADC_SINGLECTRL_NEGSEL_SHIFT) #endif | ((uint32_t)(init->resolution) << _ADC_SINGLECTRL_RES_SHIFT); if (init->prsEnable) { tmp |= ADC_SINGLECTRL_PRSEN; } if (init->leftAdjust) { tmp |= ADC_SINGLECTRL_ADJ_LEFT; } if (init->diff) { tmp |= ADC_SINGLECTRL_DIFF; } if (init->rep) { tmp |= ADC_SINGLECTRL_REP; } #if defined(_ADC_SINGLECTRL_POSSEL_TEMP) /* Force at least 8 cycle acquisition time when reading the internal temperature * sensor with 1.25 V reference */ if ((init->posSel == adcPosSelTEMP) && (init->reference == adcRef1V25) && (init->acqTime < adcAcqTime8)) { tmp = (tmp & ~_ADC_SINGLECTRL_AT_MASK) | ((uint32_t)adcAcqTime8 << _ADC_SINGLECTRL_AT_SHIFT); } #endif /* Set a single reference. Check if the reference configuration is extended to SINGLECTRLX. */ #if defined (_ADC_SINGLECTRLX_MASK) if (((uint32_t)init->reference & ADC_CTRLX_VREFSEL_REG) != 0UL) { /* Select the extension register. */ tmp |= ADC_SINGLECTRL_REF_CONF; } else { tmp |= (uint32_t)init->reference << _ADC_SINGLECTRL_REF_SHIFT; } #else tmp |= (uint32_t)init->reference << _ADC_SINGLECTRL_REF_SHIFT; #endif adc->SINGLECTRL = tmp; /* Update SINGLECTRLX for reference select and PRS select. */ #if defined (_ADC_SINGLECTRLX_VREFSEL_MASK) tmp = adc->SINGLECTRLX & ~(_ADC_SINGLECTRLX_VREFSEL_MASK | _ADC_SINGLECTRLX_PRSSEL_MASK | _ADC_SINGLECTRLX_FIFOOFACT_MASK); if (((uint32_t)init->reference & ADC_CTRLX_VREFSEL_REG) != 0UL) { tmp |= ((uint32_t)init->reference & ~ADC_CTRLX_VREFSEL_REG) << _ADC_SINGLECTRLX_VREFSEL_SHIFT; } tmp |= (uint32_t)init->prsSel << _ADC_SINGLECTRLX_PRSSEL_SHIFT; if (init->fifoOverwrite) { tmp |= ADC_SINGLECTRLX_FIFOOFACT_OVERWRITE; } adc->SINGLECTRLX = tmp; #endif /* Set DMA availability in EM2. */ #if defined(_ADC_CTRL_SINGLEDMAWU_MASK) BUS_RegBitWrite(&adc->CTRL, _ADC_CTRL_SINGLEDMAWU_SHIFT, (uint32_t)init->singleDmaEm2Wu); #endif #if defined(_ADC_BIASPROG_GPBIASACC_MASK) && defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) if (init->posSel == adcPosSelTEMP) { /* ADC should always use low accuracy setting when reading the internal * temperature sensor on EFR32xG1. Using high * accuracy setting can introduce a glitch. */ BUS_RegBitWrite(&adc->BIASPROG, _ADC_BIASPROG_GPBIASACC_SHIFT, 1); } else { BUS_RegBitWrite(&adc->BIASPROG, _ADC_BIASPROG_GPBIASACC_SHIFT, 0); } #endif /* Assert for any APORT bus conflicts programming errors. */ #if defined(_ADC_BUSCONFLICT_MASK) tmp = adc->BUSREQ; EFM_ASSERT(!(tmp & adc->BUSCONFLICT)); EFM_ASSERT(!(adc->STATUS & _ADC_STATUS_PROGERR_MASK)); #endif } #if defined(_ADC_SCANDATAX_MASK) /***************************************************************************//** * @brief * Get a scan result and scan select ID. * * @note * Only use if scan data valid. This function does not check the DV flag. * The return value is meant to be used as an index for the scan select ID. * * @param[in] adc * A pointer to the ADC peripheral register block. * * @param[out] scanId * A scan select ID of the first data in the scan FIFO. * * @return * The first scan data in the scan FIFO. ******************************************************************************/ uint32_t ADC_DataIdScanGet(ADC_TypeDef *adc, uint32_t *scanId) { uint32_t scanData; /* Pop data FIFO with scan ID */ scanData = adc->SCANDATAX; *scanId = (scanData & _ADC_SCANDATAX_SCANINPUTID_MASK) >> _ADC_SCANDATAX_SCANINPUTID_SHIFT; return (scanData & _ADC_SCANDATAX_DATA_MASK) >> _ADC_SCANDATAX_DATA_SHIFT; } #endif /***************************************************************************//** * @brief * Calculate the prescaler value used to determine the ADC clock. * * @details * The ADC clock is given by: (HFPERCLK or HFPERCCLK) / (prescale + 1). * * @note * The return value is clamped to the maximum prescaler value that the hardware supports. * * @param[in] adcFreq ADC frequency wanted. The frequency will automatically * be adjusted to a valid range according to the reference manual. * * @param[in] hfperFreq Frequency in Hz of reference HFPER/HFPERC clock. * Set to 0 to use currently defined HFPER/HFPERC clock setting. * * @return * A prescaler value to use for ADC in order to achieve a clock value * <= @p adcFreq. ******************************************************************************/ uint8_t ADC_PrescaleCalc(uint32_t adcFreq, uint32_t hfperFreq) { uint32_t ret; /* Make sure that the selected ADC clock is within a valid range. */ if (adcFreq > ADC_MAX_CLOCK) { adcFreq = ADC_MAX_CLOCK; } else if (adcFreq < ADC_MIN_CLOCK) { adcFreq = ADC_MIN_CLOCK; } else { /* Valid frequency. */ } /* Use current HFPERCLK / HFPERCCLK frequency. */ if (hfperFreq == 0UL) { #if defined(_CMU_HFPERPRESCC_MASK) hfperFreq = CMU_ClockFreqGet(cmuClock_HFPERC); #else hfperFreq = CMU_ClockFreqGet(cmuClock_HFPER); #endif } ret = (hfperFreq + adcFreq - 1U) / adcFreq; if (ret > 0U) { ret--; } if (ret > (_ADC_CTRL_PRESC_MASK >> _ADC_CTRL_PRESC_SHIFT)) { ret = _ADC_CTRL_PRESC_MASK >> _ADC_CTRL_PRESC_SHIFT; } return (uint8_t)ret; } /***************************************************************************//** * @brief * Reset ADC to a state that it was in after a hardware reset. * * @note * The ROUTE register is NOT reset by this function to allow * a centralized setup of this feature. * * @param[in] adc * A pointer to ADC peripheral register block. ******************************************************************************/ void ADC_Reset(ADC_TypeDef *adc) { /* Stop conversions, before resetting other registers. */ adc->CMD = ADC_CMD_SINGLESTOP | ADC_CMD_SCANSTOP; adc->SINGLECTRL = _ADC_SINGLECTRL_RESETVALUE; #if defined(_ADC_SINGLECTRLX_MASK) adc->SINGLECTRLX = _ADC_SINGLECTRLX_RESETVALUE; #endif adc->SCANCTRL = _ADC_SCANCTRL_RESETVALUE; #if defined(_ADC_SCANCTRLX_MASK) adc->SCANCTRLX = _ADC_SCANCTRLX_RESETVALUE; #endif adc->CTRL = _ADC_CTRL_RESETVALUE; adc->IEN = _ADC_IEN_RESETVALUE; adc->IFC = _ADC_IFC_MASK; adc->BIASPROG = _ADC_BIASPROG_RESETVALUE; #if defined(_ADC_SCANMASK_MASK) adc->SCANMASK = _ADC_SCANMASK_RESETVALUE; #endif #if defined(_ADC_SCANINPUTSEL_MASK) adc->SCANINPUTSEL = _ADC_SCANINPUTSEL_RESETVALUE; #endif #if defined(_ADC_SCANNEGSEL_MASK) adc->SCANNEGSEL = _ADC_SCANNEGSEL_RESETVALUE; #endif /* Clear data FIFOs. */ #if defined(_ADC_SINGLEFIFOCLEAR_MASK) adc->SINGLEFIFOCLEAR |= ADC_SINGLEFIFOCLEAR_SINGLEFIFOCLEAR; adc->SCANFIFOCLEAR |= ADC_SCANFIFOCLEAR_SCANFIFOCLEAR; #endif /* Load calibration values for the 1V25 internal reference. */ ADC_LoadDevinfoCal(adc, adcRef1V25, false); ADC_LoadDevinfoCal(adc, adcRef1V25, true); #if defined(_ADC_SCANINPUTSEL_MASK) /* Do not reset route register, setting should be done independently. */ #endif } /***************************************************************************//** * @brief * Calculate a timebase value to get a timebase providing at least 1 us. * * @param[in] hfperFreq Frequency in Hz of the reference HFPER/HFPERC clock. * Set to 0 to use currently defined HFPER/HFPERC clock setting. * * @return * A timebase value to use for ADC to achieve at least 1 us. ******************************************************************************/ uint8_t ADC_TimebaseCalc(uint32_t hfperFreq) { if (hfperFreq == 0UL) { #if defined(_CMU_HFPERPRESCC_MASK) hfperFreq = CMU_ClockFreqGet(cmuClock_HFPERC); #else hfperFreq = CMU_ClockFreqGet(cmuClock_HFPER); #endif /* Make sure that the frequency is not 0 in below calculation. */ if (hfperFreq == 0UL) { hfperFreq = 1UL; } } #if defined(_SILICON_LABS_32B_SERIES_0) \ && (defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)) /* Handle errata on Giant Gecko, maximum TIMEBASE is 5 bits wide or max 0x1F */ /* cycles. This will give a warm up time of e.g., 0.645 us, not the */ /* required 1 us when operating at 48 MHz. One must also increase acqTime */ /* to compensate for the missing clock cycles, adding up to 1 us total.*/ /* See reference manual for details. */ if ( hfperFreq > 32000000UL ) { hfperFreq = 32000000UL; } #endif /* Determine the number of HFPERCLK / HFPERCCLK cycle >= 1 us. */ hfperFreq += 999999UL; hfperFreq /= 1000000UL; /* Return timebase value (N+1 format). */ return (uint8_t)(hfperFreq - 1UL); } /** @} (end addtogroup ADC) */ /** @} (end addtogroup emlib) */ #endif /* defined(ADC_COUNT) && (ADC_COUNT > 0) */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/emlib/src/em_assert.c.
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/***************************************************************************//** * @file * @brief Assert API * @version 5.7.0 ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * SPDX-License-Identifier: Zlib * * The licensor of this software is Silicon Laboratories Inc. * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be * appreciated but is not required. * 2. Altered source versions must be plainly marked as such, and must not be * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * ******************************************************************************/ #include "em_assert.h" #include <stdbool.h> /***************************************************************************//** * @addtogroup emlib * @{ ******************************************************************************/ /***************************************************************************//** * @addtogroup ASSERT * @details * This module contains functions to control the ASSERT peripheral of Silicon * Labs 32-bit MCUs and SoCs. * @{ ******************************************************************************/ #if defined(DEBUG_EFM) /***************************************************************************//** * @brief * EFM internal assert handling. * * This function is invoked through EFM_ASSERT() macro usage only and should * not be used explicitly. * * This implementation enters an indefinite loop, allowing * the use of a debugger to determine a cause of failure. By defining * DEBUG_EFM_USER to the preprocessor for all files, a user-defined version * of this function must be defined and will be invoked instead, possibly * providing output of assertion location. * * @note * This function is not used unless @ref DEBUG_EFM is defined * during preprocessing of EFM_ASSERT() usage. * * @param[in] file * Name of the source file where assertion failed. * * @param[in] line * A line number in the source file where assertion failed. ******************************************************************************/ void assertEFM(const char *file, int line) { (void)file; /* Unused parameter */ (void)line; /* Unused parameter */ while (true) { } } #endif /* DEBUG_EFM */ /** @} (end addtogroup ASSERT) */ /** @} (end addtogroup emlib) */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/emlib/src/em_burtc.c.
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/***************************************************************************//** * @file * @brief Backup Real Time Counter (BURTC) Peripheral API * @version 5.7.0 ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * SPDX-License-Identifier: Zlib * * The licensor of this software is Silicon Laboratories Inc. * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be * appreciated but is not required. * 2. Altered source versions must be plainly marked as such, and must not be * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * ******************************************************************************/ #include "em_burtc.h" #if defined(BURTC_PRESENT) /***************************************************************************//** * @addtogroup emlib * @{ ******************************************************************************/ /***************************************************************************//** * @addtogroup BURTC * @brief Backup Real Time Counter (BURTC) Peripheral API * @details * This module contains functions to control the BURTC peripheral of Silicon * Labs 32-bit MCUs. The Backup Real Time Counter allows timekeeping in all * energy modes. The Backup RTC is also available when the system is in backup * mode. * @{ ******************************************************************************/ /******************************************************************************* ******************************* DEFINES *********************************** ******************************************************************************/ /******************************************************************************* ************************** LOCAL FUNCTIONS ******************************** ******************************************************************************/ /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ /***************************************************************************//** * @brief Convert dividend to a prescaler logarithmic value. Only works for even * numbers equal to 2^n. * @param[in] div Unscaled dividend, * @return Base 2 logarithm of input, as used by fixed prescalers. ******************************************************************************/ __STATIC_INLINE uint32_t divToLog2(uint32_t div) { uint32_t log2; /* Prescaler accepts an argument of 128 or less, valid values being 2^n. */ EFM_ASSERT((div > 0) && (div <= 32768)); /* Count leading zeroes and "reverse" result, Cortex-M3 intrinsic. */ log2 = (31 - __CLZ(div)); return log2; } /***************************************************************************//** * @brief * Wait for an ongoing sync of register(s) to low frequency domain to complete. * * @param[in] mask * A bitmask corresponding to SYNCBUSY register defined bits, indicating * registers that must complete any ongoing synchronization. ******************************************************************************/ __STATIC_INLINE void regSync(uint32_t mask) { #if defined(_BURTC_FREEZE_MASK) /* Avoid deadlock if modifying the same register twice when freeze mode is activated or when a clock is not selected for the BURTC. If a clock is not selected, then the sync is done once the clock source is set. */ if ((BURTC->FREEZE & BURTC_FREEZE_REGFREEZE) || ((BURTC->CTRL & _BURTC_CTRL_CLKSEL_MASK) == BURTC_CTRL_CLKSEL_NONE) || ((BURTC->CTRL & _BURTC_CTRL_RSTEN_MASK) == BURTC_CTRL_RSTEN)) { return; } #endif /* Wait for any pending previous write operation to complete */ /* in low frequency domain. This is only required for the Gecko Family. */ while ((BURTC->SYNCBUSY & mask) != 0U) ; } /** @endcond */ /******************************************************************************* ************************** GLOBAL FUNCTIONS ******************************* ******************************************************************************/ /***************************************************************************//** * @brief Initialize BURTC. * * @details * Configures the BURTC peripheral. * * @note * Before initialization, BURTC module must first be enabled by clearing the * reset bit in the RMU, i.e., * @verbatim * RMU_ResetControl(rmuResetBU, rmuResetModeClear); * @endverbatim * Compare channel 0 must be configured outside this function, before * initialization if enable is set to true. The counter will always be reset. * * @param[in] burtcInit * A pointer to the BURTC initialization structure. ******************************************************************************/ void BURTC_Init(const BURTC_Init_TypeDef *burtcInit) { #if defined(_SILICON_LABS_32B_SERIES_0) uint32_t ctrl; uint32_t presc; /* Check initializer structure integrity. */ EFM_ASSERT(burtcInit != (BURTC_Init_TypeDef *) 0); /* Clock divider must be between 1 and 128, really on the form 2^n. */ EFM_ASSERT((burtcInit->clkDiv >= 1) && (burtcInit->clkDiv <= 128)); /* Ignored compare bits during low power operation must be less than 7. */ /* Note! Giant Gecko revision C errata, do NOT use LPCOMP=7. */ EFM_ASSERT(burtcInit->lowPowerComp <= 6); /* You cannot enable the BURTC if mode is set to disabled. */ EFM_ASSERT((burtcInit->enable == false) || ((burtcInit->enable == true) && (burtcInit->mode != burtcModeDisable))); /* Low power mode is only available with LFRCO or LFXO as clock source. */ EFM_ASSERT((burtcInit->clkSel != burtcClkSelULFRCO) || ((burtcInit->clkSel == burtcClkSelULFRCO) && (burtcInit->lowPowerMode == burtcLPDisable))); /* Calculate a prescaler value from the clock divider input. */ /* Note! If clock select (clkSel) is ULFRCO, a clock divisor (clkDiv) of value 1 will select a 2 kHz ULFRCO clock, while any other value will select a 1 kHz ULFRCO clock source. */ presc = divToLog2(burtcInit->clkDiv); /* Make sure all registers are updated simultaneously. */ if (burtcInit->enable) { BURTC_FreezeEnable(true); } /* Modification of LPMODE register requires sync with potential ongoing * register updates in LF domain. */ regSync(BURTC_SYNCBUSY_LPMODE); /* Configure low power mode. */ BURTC->LPMODE = (uint32_t) (burtcInit->lowPowerMode); /* New configuration. */ ctrl = (BURTC_CTRL_RSTEN | (burtcInit->mode) | (burtcInit->debugRun << _BURTC_CTRL_DEBUGRUN_SHIFT) | (burtcInit->compare0Top << _BURTC_CTRL_COMP0TOP_SHIFT) | (burtcInit->lowPowerComp << _BURTC_CTRL_LPCOMP_SHIFT) | (presc << _BURTC_CTRL_PRESC_SHIFT) | (burtcInit->clkSel) | (burtcInit->timeStamp << _BURTC_CTRL_BUMODETSEN_SHIFT)); /* Clear interrupts. */ BURTC_IntClear(0xFFFFFFFF); /* Set the new configuration. */ BURTC->CTRL = ctrl; /* Enable BURTC and counter. */ if (burtcInit->enable) { /* To enable BURTC counter, disable reset. */ BURTC_Enable(true); /* Clear freeze. */ BURTC_FreezeEnable(false); } #elif defined(_SILICON_LABS_32B_SERIES_2) uint32_t presc; presc = divToLog2(burtcInit->clkDiv); if (BURTC->EN != 0U) { BURTC_SyncWait(); } BURTC->EN_CLR = BURTC_EN_EN; regSync(BURTC_SYNCBUSY_EN); BURTC->CFG = (presc << _BURTC_CFG_CNTPRESC_SHIFT) | ((burtcInit->compare0Top ? 1U : 0U) << _BURTC_CFG_COMPTOP_SHIFT) | ((burtcInit->debugRun ? 1U : 0U) << _BURTC_CFG_DEBUGRUN_SHIFT); BURTC->EM4WUEN = ((burtcInit->em4comp ? 1U : 0U) << _BURTC_EM4WUEN_COMPEM4WUEN_SHIFT) | ((burtcInit->em4overflow ? 1U : 0U) << _BURTC_EM4WUEN_OFEM4WUEN_SHIFT); BURTC->EN_SET = BURTC_EN_EN; if (burtcInit->start) { BURTC_Start(); } #endif } #if defined(_SILICON_LABS_32B_SERIES_2) /***************************************************************************//** * @brief * Enable or Disable BURTC peripheral. * * @param[in] enable * true to enable, false to disable. ******************************************************************************/ void BURTC_Enable(bool enable) { regSync(BURTC_SYNCBUSY_EN); if ((BURTC->EN == 0U) && !enable) { /* Trying to disable BURTC when it's already disabled */ return; } if (BURTC->EN != 0U) { /* Modifying the enable bit while synchronization is active will BusFault */ BURTC_SyncWait(); } if (enable) { BURTC->EN_SET = BURTC_EN_EN; } else { BURTC_Stop(); BURTC_SyncWait(); /* Wait for the stop to synchronize */ BURTC->EN_CLR = BURTC_EN_EN; } } #elif defined(_SILICON_LABS_32B_SERIES_0) /***************************************************************************//** * @brief * Enable or Disable BURTC peripheral reset and start counter * @param[in] enable * If true; asserts reset to BURTC, halts counter, if false; deassert reset ******************************************************************************/ void BURTC_Enable(bool enable) { /* Note! If mode is disabled, BURTC counter will not start */ EFM_ASSERT(((enable == true) && ((BURTC->CTRL & _BURTC_CTRL_MODE_MASK) != BURTC_CTRL_MODE_DISABLE)) || (enable == false)); BUS_RegBitWrite(&BURTC->CTRL, _BURTC_CTRL_RSTEN_SHIFT, (uint32_t) !enable); } #endif /***************************************************************************//** * @brief Set BURTC compare channel. * * @param[in] comp Compare the channel index, must be 0 for current devices. * * @param[in] value New compare value. ******************************************************************************/ void BURTC_CompareSet(unsigned int comp, uint32_t value) { (void) comp; /* Unused parameter when EFM_ASSERT is undefined. */ EFM_ASSERT(comp == 0U); #if defined(_BURTC_COMP0_MASK) /* Modification of COMP0 register requires sync with potential ongoing * register updates in LF domain. */ regSync(BURTC_SYNCBUSY_COMP0); /* Configure compare channel 0/. */ BURTC->COMP0 = value; #else /* Wait for last potential write to complete. */ regSync(BURTC_SYNCBUSY_COMP); /* Configure compare channel 0 */ BURTC->COMP = value; regSync(BURTC_SYNCBUSY_COMP); #endif } /***************************************************************************//** * @brief Get the BURTC compare value. * * @param[in] comp Compare the channel index value, must be 0 for Giant/Leopard Gecko. * * @return The currently configured value for this compare channel. ******************************************************************************/ uint32_t BURTC_CompareGet(unsigned int comp) { (void) comp; /* Unused parameter when EFM_ASSERT is undefined. */ EFM_ASSERT(comp == 0U); #if defined(_BURTC_COMP0_MASK) return BURTC->COMP0; #else return BURTC->COMP; #endif } /***************************************************************************//** * @brief Reset counter ******************************************************************************/ void BURTC_CounterReset(void) { #if defined(_BURTC_CTRL_MASK) /* Set and clear reset bit */ BUS_RegBitWrite(&BURTC->CTRL, _BURTC_CTRL_RSTEN_SHIFT, 1U); BUS_RegBitWrite(&BURTC->CTRL, _BURTC_CTRL_RSTEN_SHIFT, 0U); #else BURTC_Stop(); BURTC->CNT = 0U; BURTC_Start(); #endif } /***************************************************************************//** * @brief * Restore BURTC to reset state. * @note * Before accessing the BURTC, BURSTEN in RMU->CTRL must be cleared. * LOCK will not be reset to default value, as this will disable access * to core BURTC registers. ******************************************************************************/ void BURTC_Reset(void) { #if defined(_SILICON_LABS_32B_SERIES_0) bool buResetState; /* Read reset state, set reset, and restore state. */ buResetState = BUS_RegBitRead(&RMU->CTRL, _RMU_CTRL_BURSTEN_SHIFT); BUS_RegBitWrite(&RMU->CTRL, _RMU_CTRL_BURSTEN_SHIFT, 1); BUS_RegBitWrite(&RMU->CTRL, _RMU_CTRL_BURSTEN_SHIFT, buResetState); #elif defined(_SILICON_LABS_32B_SERIES_2) if (BURTC->EN != 0U) { BURTC_SyncWait(); } BURTC->EN_SET = BURTC_EN_EN; BURTC_Stop(); BURTC->CNT = 0x0; BURTC->PRECNT = 0x0; BURTC->COMP = 0x0; BURTC->EM4WUEN = _BURTC_EM4WUEN_RESETVALUE; BURTC->IEN = _BURTC_IEN_RESETVALUE; BURTC->IF_CLR = _BURTC_IF_MASK; /* Wait for all values to synchronize. BusFaults can happen if we don't * do this before the enable bit is cleared. */ BURTC_SyncWait(); BURTC->EN_CLR = BURTC_EN_EN; BURTC_SyncWait(); BURTC->CFG = _BURTC_CFG_RESETVALUE; #endif } #if defined(_BURTC_CTRL_MASK) /***************************************************************************//** * @brief * Get the clock frequency of the BURTC. * * @return * The current frequency in Hz. ******************************************************************************/ uint32_t BURTC_ClockFreqGet(void) { uint32_t clkSel; uint32_t clkDiv; uint32_t frequency; clkSel = BURTC->CTRL & _BURTC_CTRL_CLKSEL_MASK; clkDiv = (BURTC->CTRL & _BURTC_CTRL_PRESC_MASK) >> _BURTC_CTRL_PRESC_SHIFT; switch (clkSel) { /** Ultra-low frequency (1 kHz) clock. */ case BURTC_CTRL_CLKSEL_ULFRCO: if (_BURTC_CTRL_PRESC_DIV1 == clkDiv) { frequency = 2000; /* 2 kHz when clock divisor is 1. */ } else { frequency = SystemULFRCOClockGet(); /* 1 kHz when divisor is different from 1. */ } break; /** Low-frequency RC oscillator. */ case BURTC_CTRL_CLKSEL_LFRCO: frequency = SystemLFRCOClockGet() / (1 << clkDiv); /* freq=32768/2^clkDiv */ break; /** Low-frequency crystal oscillator. */ case BURTC_CTRL_CLKSEL_LFXO: frequency = SystemLFXOClockGet() / (1 << clkDiv); /* freq=32768/2^clkDiv */ break; default: /* No clock selected for BURTC. */ frequency = 0; } return frequency; } #endif /** @} (end addtogroup BURTC) */ /** @} (end addtogroup emlib) */ #endif /* BURTC_PRESENT */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/emlib/src/em_cmu.c.
> > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > 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/***************************************************************************//** * @file * @brief Clock management unit (CMU) Peripheral API * @version 5.7.0 ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * SPDX-License-Identifier: Zlib * * The licensor of this software is Silicon Laboratories Inc. * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be * appreciated but is not required. * 2. Altered source versions must be plainly marked as such, and must not be * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * ******************************************************************************/ #include "em_cmu.h" #if defined(CMU_PRESENT) #include <stddef.h> #include <limits.h> #include "em_assert.h" #include "em_bus.h" #include "em_cmu.h" #include "em_common.h" #include "em_emu.h" #include "em_gpio.h" #include "em_system.h" /***************************************************************************//** * @addtogroup emlib * @{ ******************************************************************************/ /***************************************************************************//** * @addtogroup CMU * @brief Clock management unit (CMU) Peripheral API * @details * This module contains functions to control the CMU peripheral of Silicon * Labs 32-bit MCUs and SoCs. The CMU controls oscillators and clocks. * @{ ******************************************************************************/ #if defined(_SILICON_LABS_32B_SERIES_2) /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ /******************************************************************************* ****************************** DEFINES ************************************ ******************************************************************************/ // Maximum allowed core frequency vs. wait-states on flash accesses. #define CMU_MAX_FLASHREAD_FREQ_0WS 39000000UL #define CMU_MAX_FLASHREAD_FREQ_1WS 80000000UL // Maximum allowed core frequency vs. wait-states on sram accesses. #define CMU_MAX_SRAM_FREQ_0WS 50000000UL #define CMU_MAX_SRAM_FREQ_1WS 80000000UL // Maximum allowed PCLK frequency. #define CMU_MAX_PCLK_FREQ 50000000UL /******************************************************************************* ************************** LOCAL VARIABLES ******************************** ******************************************************************************/ // Table of HFRCOCAL values and their associated min/max frequencies and // optional band enumerator. static const struct hfrcoCalTableElement{ uint32_t minFreq; uint32_t maxFreq; uint32_t value; CMU_HFRCODPLLFreq_TypeDef band; } hfrcoCalTable[] = // TODO: Get confirmation on min/max freq limits { // minFreq maxFreq HFRCOCAL value band { 860000UL, 1050000UL, 0x82401F00UL, cmuHFRCODPLLFreq_1M0Hz }, { 1050000UL, 1280000UL, 0xA2411F3AUL, (CMU_HFRCODPLLFreq_TypeDef)0 }, { 1280000UL, 1480000UL, 0xA2421F3AUL, (CMU_HFRCODPLLFreq_TypeDef)0 }, { 1480000UL, 1800000UL, 0xB6439F3AUL, (CMU_HFRCODPLLFreq_TypeDef)0 }, { 1800000UL, 2110000UL, 0x81401F00UL, cmuHFRCODPLLFreq_2M0Hz }, { 2110000UL, 2560000UL, 0xA1411F3AUL, (CMU_HFRCODPLLFreq_TypeDef)0 }, { 2560000UL, 2970000UL, 0xA1421F3AUL, (CMU_HFRCODPLLFreq_TypeDef)0 }, { 2970000UL, 3600000UL, 0xB5439F3AUL, (CMU_HFRCODPLLFreq_TypeDef)0 }, { 3600000UL, 4220000UL, 0x80401F00UL, cmuHFRCODPLLFreq_4M0Hz }, { 4220000UL, 5120000UL, 0xA0411F3AUL, (CMU_HFRCODPLLFreq_TypeDef)0 }, { 5120000UL, 5930000UL, 0xA0421F3AUL, (CMU_HFRCODPLLFreq_TypeDef)0 }, { 5930000UL, 7520000UL, 0xB4439F00UL, cmuHFRCODPLLFreq_7M0Hz }, { 7520000UL, 9520000UL, 0xB4449F3AUL, (CMU_HFRCODPLLFreq_TypeDef)0 }, { 9520000UL, 11800000UL, 0xB4459F3AUL, (CMU_HFRCODPLLFreq_TypeDef)0 }, { 11800000UL, 14400000UL, 0xB4669F00UL, cmuHFRCODPLLFreq_13M0Hz }, { 14400000UL, 17200000UL, 0xB4679F00UL, cmuHFRCODPLLFreq_16M0Hz }, { 17200000UL, 19700000UL, 0xA8689F00UL, cmuHFRCODPLLFreq_19M0Hz }, { 19700000UL, 23800000UL, 0xB8899F3AUL, (CMU_HFRCODPLLFreq_TypeDef)0 }, { 23800000UL, 28700000UL, 0xB88A9F00UL, cmuHFRCODPLLFreq_26M0Hz }, { 28700000UL, 34800000UL, 0xB8AB9F00UL, cmuHFRCODPLLFreq_32M0Hz }, { 34800000UL, 42800000UL, 0xA8CC9F00UL, cmuHFRCODPLLFreq_38M0Hz }, { 42800000UL, 51600000UL, 0xACED9F00UL, cmuHFRCODPLLFreq_48M0Hz }, { 51600000UL, 60500000UL, 0xBCEE9F00UL, cmuHFRCODPLLFreq_56M0Hz }, { 60500000UL, 72600000UL, 0xBCEF9F00UL, cmuHFRCODPLLFreq_64M0Hz }, { 72600000UL, 80000000UL, 0xCCF09F00UL, cmuHFRCODPLLFreq_80M0Hz } }; #define HFRCOCALTABLE_ENTRIES (sizeof(hfrcoCalTable) \ / sizeof(struct hfrcoCalTableElement)) /******************************************************************************* ************************** LOCAL PROTOTYPES ******************************* ******************************************************************************/ static void dpllRefClkGet(uint32_t *freq, CMU_Select_TypeDef *sel); static void em01GrpaClkGet(uint32_t *freq, CMU_Select_TypeDef *sel); static void em23GrpaClkGet(uint32_t *freq, CMU_Select_TypeDef *sel); static void em4GrpaClkGet(uint32_t *freq, CMU_Select_TypeDef *sel); static uint32_t HFRCODPLLDevinfoGet(CMU_HFRCODPLLFreq_TypeDef freq); static uint32_t HFRCOEM23DevinfoGet(CMU_HFRCOEM23Freq_TypeDef freq); static void iadcClkGet(uint32_t *freq, CMU_Select_TypeDef *sel); static void pclkDivMax(void); static void pclkDivOptimize(void); static void rtccClkGet(uint32_t *freq, CMU_Select_TypeDef *sel); static void traceClkGet(uint32_t *freq, CMU_Select_TypeDef *sel); static void waitStateMax(void); static void waitStateSet(uint32_t coreFreq); static void wdog0ClkGet(uint32_t *freq, CMU_Select_TypeDef *sel); static void wdog1ClkGet(uint32_t *freq, CMU_Select_TypeDef *sel); /** @endcond */ /******************************************************************************* ************************** GLOBAL FUNCTIONS ******************************* ******************************************************************************/ /***************************************************************************//** * @brief * Calibrate an oscillator. * * @details * Run a calibration of a selectable reference clock againt HCLK. Please * refer to the reference manual, CMU chapter, for further details. * * @note * This function will not return until calibration measurement is completed. * * @param[in] cycles * The number of HCLK cycles to run calibration. Increasing this number * increases precision, but the calibration will take more time. * * @param[in] ref * The reference clock used to compare against HCLK. * * @return * The number of ticks the selected reference clock ticked while running * cycles ticks of the HCLK clock. ******************************************************************************/ uint32_t CMU_Calibrate(uint32_t cycles, CMU_Select_TypeDef ref) { // Check for cycle count overflow EFM_ASSERT(cycles <= (_CMU_CALCTRL_CALTOP_MASK >> _CMU_CALCTRL_CALTOP_SHIFT)); CMU_CalibrateConfig(cycles, cmuSelect_HCLK, ref); CMU_CalibrateStart(); return CMU_CalibrateCountGet(); } /***************************************************************************//** * @brief * Configure clock calibration. * * @details * Configure a calibration for a selectable clock source against another * selectable reference clock. * Refer to the reference manual, CMU chapter, for further details. * * @note * After configuration, a call to @ref CMU_CalibrateStart() is required, and * the resulting calibration value can be read with the * @ref CMU_CalibrateCountGet() function call. * * @param[in] downCycles * The number of downSel clock cycles to run calibration. Increasing this * number increases precision, but the calibration will take more time. * * @param[in] downSel * The clock which will be counted down downCycles cycles. * * @param[in] upSel * The reference clock, the number of cycles generated by this clock will * be counted and added up, the result can be given with the * @ref CMU_CalibrateCountGet() function call. ******************************************************************************/ void CMU_CalibrateConfig(uint32_t downCycles, CMU_Select_TypeDef downSel, CMU_Select_TypeDef upSel) { // Keep untouched configuration settings uint32_t calCtrl = CMU->CALCTRL & ~(_CMU_CALCTRL_UPSEL_MASK | _CMU_CALCTRL_DOWNSEL_MASK | _CMU_CALCTRL_CALTOP_MASK); // Check for cycle count overflow EFM_ASSERT(downCycles <= (_CMU_CALCTRL_CALTOP_MASK >> _CMU_CALCTRL_CALTOP_SHIFT)); calCtrl |= downCycles; // Set down counting clock source selector switch (downSel) { case cmuSelect_HCLK: calCtrl |= CMU_CALCTRL_DOWNSEL_HCLK; break; case cmuSelect_PRS: calCtrl |= CMU_CALCTRL_DOWNSEL_PRS; break; case cmuSelect_HFXO: calCtrl |= CMU_CALCTRL_DOWNSEL_HFXO; break; case cmuSelect_LFXO: calCtrl |= CMU_CALCTRL_DOWNSEL_LFXO; break; case cmuSelect_HFRCODPLL: calCtrl |= CMU_CALCTRL_DOWNSEL_HFRCODPLL; break; case cmuSelect_HFRCOEM23: calCtrl |= CMU_CALCTRL_DOWNSEL_HFRCOEM23; break; case cmuSelect_FSRCO: calCtrl |= CMU_CALCTRL_DOWNSEL_FSRCO; break; case cmuSelect_LFRCO: calCtrl |= CMU_CALCTRL_DOWNSEL_LFRCO; break; case cmuSelect_ULFRCO: calCtrl |= CMU_CALCTRL_DOWNSEL_ULFRCO; break; case cmuSelect_Disabled: break; default: EFM_ASSERT(false); break; } // Set up counting clock source selector switch (upSel) { case cmuSelect_PRS: calCtrl |= CMU_CALCTRL_UPSEL_PRS; break; case cmuSelect_HFXO: calCtrl |= CMU_CALCTRL_UPSEL_HFXO; break; case cmuSelect_LFXO: calCtrl |= CMU_CALCTRL_UPSEL_LFXO; break; case cmuSelect_HFRCODPLL: calCtrl |= CMU_CALCTRL_UPSEL_HFRCODPLL; break; case cmuSelect_HFRCOEM23: calCtrl |= CMU_CALCTRL_UPSEL_HFRCOEM23; break; case cmuSelect_FSRCO: calCtrl |= CMU_CALCTRL_UPSEL_FSRCO; break; case cmuSelect_LFRCO: calCtrl |= CMU_CALCTRL_UPSEL_LFRCO; break; case cmuSelect_ULFRCO: calCtrl |= CMU_CALCTRL_UPSEL_ULFRCO; break; case cmuSelect_Disabled: break; default: EFM_ASSERT(false); break; } CMU->CALCTRL = calCtrl; } /***************************************************************************//** * @brief * Get calibration count value. * * @note * If continuous calibrartion mode is active, calibration busy will almost * always be off, and we just need to read the value, where the normal case * would be that this function call has been triggered by the CALRDY * interrupt flag. * * @return * Calibration count, the number of UPSEL clocks (see @ref CMU_CalibrateConfig()) * in the period of DOWNSEL oscillator clock cycles configured by a previous * write operation to CMU->CALCNT. ******************************************************************************/ uint32_t CMU_CalibrateCountGet(void) { // Wait until calibration completes, UNLESS continuous calibration mode is on if ((CMU->CALCTRL & CMU_CALCTRL_CONT) == 0UL) { // Wait until calibration completes while ((CMU->STATUS & CMU_STATUS_CALRDY) == 0UL) { } } return CMU->CALCNT; } /***************************************************************************//** * @brief * Direct a clock to a GPIO pin. * * @param[in] clkNo * Selects between CLKOUT0, CLKOUT1 or CLKOUT2 outputs. Use values 0,1or 2. * * @param[in] sel * Select clock source. * * @param[in] clkDiv * Select a clock divisor (1..32). Only applicable when cmuSelect_EXPCLK is * slexted as clock source. * * @param[in] port * GPIO port. * * @param[in] pin * GPIO pin. * * @note * Refer to the reference manual and the datasheet for details on which * GPIO port/pins that are available. ******************************************************************************/ void CMU_ClkOutPinConfig(uint32_t clkNo, CMU_Select_TypeDef sel, CMU_ClkDiv_TypeDef clkDiv, GPIO_Port_TypeDef port, unsigned int pin) { uint32_t tmp = 0U, mask; EFM_ASSERT(clkNo <= 2U); EFM_ASSERT(clkDiv <= 32U); EFM_ASSERT(port <= 3U); EFM_ASSERT(pin <= 15U); switch (sel) { case cmuSelect_Disabled: tmp = CMU_EXPORTCLKCTRL_CLKOUTSEL0_DISABLED; break; case cmuSelect_FSRCO: tmp = CMU_EXPORTCLKCTRL_CLKOUTSEL0_FSRCO; break; case cmuSelect_HFXO: tmp = CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFXO; break; case cmuSelect_HFRCODPLL: tmp = CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFRCODPLL; break; case cmuSelect_HFRCOEM23: tmp = CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFRCOEM23; break; case cmuSelect_EXPCLK: tmp = CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFEXPCLK; break; case cmuSelect_LFXO: tmp = CMU_EXPORTCLKCTRL_CLKOUTSEL0_LFXO; break; case cmuSelect_LFRCO: tmp = CMU_EXPORTCLKCTRL_CLKOUTSEL0_LFRCO; break; case cmuSelect_ULFRCO: tmp = CMU_EXPORTCLKCTRL_CLKOUTSEL0_ULFRCO; break; case cmuSelect_HCLK: tmp = CMU_EXPORTCLKCTRL_CLKOUTSEL0_HCLK; break; default: EFM_ASSERT(false); break; } mask = _CMU_EXPORTCLKCTRL_CLKOUTSEL0_MASK << (clkNo * _CMU_EXPORTCLKCTRL_CLKOUTSEL1_SHIFT); tmp <<= clkNo * _CMU_EXPORTCLKCTRL_CLKOUTSEL1_SHIFT; if (sel == cmuSelect_EXPCLK) { tmp |= (clkDiv - 1U) << _CMU_EXPORTCLKCTRL_PRESC_SHIFT; mask |= _CMU_EXPORTCLKCTRL_PRESC_MASK; } CMU->EXPORTCLKCTRL = (CMU->EXPORTCLKCTRL & ~mask) | tmp; if (sel == cmuSelect_Disabled) { GPIO->CMUROUTE_CLR.ROUTEEN = GPIO_CMU_ROUTEEN_CLKOUT0PEN << clkNo; GPIO_PinModeSet(port, pin, gpioModeDisabled, 0); } else { GPIO->CMUROUTE_SET.ROUTEEN = GPIO_CMU_ROUTEEN_CLKOUT0PEN << clkNo; if (clkNo == 0U) { GPIO->CMUROUTE.CLKOUT0ROUTE = (port << _GPIO_CMU_CLKOUT0ROUTE_PORT_SHIFT) | (pin << _GPIO_CMU_CLKOUT0ROUTE_PIN_SHIFT); } else if (clkNo == 1) { GPIO->CMUROUTE.CLKOUT1ROUTE = (port << _GPIO_CMU_CLKOUT1ROUTE_PORT_SHIFT) | (pin << _GPIO_CMU_CLKOUT1ROUTE_PIN_SHIFT); } else { GPIO->CMUROUTE.CLKOUT2ROUTE = (port << _GPIO_CMU_CLKOUT2ROUTE_PORT_SHIFT) | (pin << _GPIO_CMU_CLKOUT2ROUTE_PIN_SHIFT); } GPIO_PinModeSet(port, pin, gpioModePushPull, 0); } } /***************************************************************************//** * @brief * Get clock divisor. * * @param[in] clock * Clock point to get divisor for. Notice that not all clock points * have a divisors. Please refer to CMU overview in reference manual. * * @return * The current clock point divisor. 1 is returned * if @p clock specifies a clock point without divisor. ******************************************************************************/ CMU_ClkDiv_TypeDef CMU_ClockDivGet(CMU_Clock_TypeDef clock) { uint32_t ret = 0U; switch (clock) { case cmuClock_HCLK: case cmuClock_CORE: ret = (CMU->SYSCLKCTRL & _CMU_SYSCLKCTRL_HCLKPRESC_MASK) >> _CMU_SYSCLKCTRL_HCLKPRESC_SHIFT; if (ret == 2U ) { // Unused value, illegal prescaler EFM_ASSERT(false); } break; case cmuClock_EXPCLK: ret = (CMU->EXPORTCLKCTRL & _CMU_EXPORTCLKCTRL_PRESC_MASK) >> _CMU_EXPORTCLKCTRL_PRESC_SHIFT; break; case cmuClock_PCLK: ret = (CMU->SYSCLKCTRL & _CMU_SYSCLKCTRL_PCLKPRESC_MASK) >> _CMU_SYSCLKCTRL_PCLKPRESC_SHIFT; break; default: EFM_ASSERT(false); break; } return 1U + ret; } /***************************************************************************//** * @brief * Set clock divisor. * * @param[in] clock * Clock point to set divisor for. Notice that not all clock points * have a divisor, please refer to CMU overview in the reference * manual. * * @param[in] div * The clock divisor to use. ******************************************************************************/ void CMU_ClockDivSet(CMU_Clock_TypeDef clock, CMU_ClkDiv_TypeDef div) { switch (clock) { case cmuClock_HCLK: case cmuClock_CORE: EFM_ASSERT((div == 1U) || (div == 2U) || (div == 4U)); // Set max wait-states and PCLK divisor while changing core clock waitStateMax(); pclkDivMax(); // Set new divisor CMU->SYSCLKCTRL = (CMU->SYSCLKCTRL & ~_CMU_SYSCLKCTRL_HCLKPRESC_MASK) | ((div - 1U) << _CMU_SYSCLKCTRL_HCLKPRESC_SHIFT); // Update CMSIS core clock variable and set optimum wait-states CMU_UpdateWaitStates(SystemCoreClockGet(), 0); // Set optimal PCLK divisor pclkDivOptimize(); break; case cmuClock_EXPCLK: EFM_ASSERT((div >= 1U) && (div <= 32U)); CMU->EXPORTCLKCTRL = (CMU->EXPORTCLKCTRL & ~_CMU_EXPORTCLKCTRL_PRESC_MASK) | ((div - 1U) << _CMU_EXPORTCLKCTRL_PRESC_SHIFT); break; case cmuClock_PCLK: EFM_ASSERT((div == 1U) || (div == 2U)); CMU->SYSCLKCTRL = (CMU->SYSCLKCTRL & ~_CMU_SYSCLKCTRL_PCLKPRESC_MASK) | ((div - 1U) << _CMU_SYSCLKCTRL_PCLKPRESC_SHIFT); break; default: EFM_ASSERT(false); break; } } /***************************************************************************//** * @brief * Get clock frequency for a clock point. * * @param[in] clock * Clock point to fetch frequency for. * * @return * The current frequency in Hz. ******************************************************************************/ uint32_t CMU_ClockFreqGet(CMU_Clock_TypeDef clock) { uint32_t ret = 0U; switch (clock) { case cmuClock_SYSCLK: ret = SystemSYSCLKGet(); break; case cmuClock_CORE: case cmuClock_HCLK: case cmuClock_LDMA: case cmuClock_GPCRC: ret = SystemHCLKGet(); break; case cmuClock_EXPCLK: ret = SystemSYSCLKGet() / CMU_ClockDivGet(cmuClock_EXPCLK); break; case cmuClock_I2C1: case cmuClock_PRS: case cmuClock_PCLK: case cmuClock_GPIO: case cmuClock_USART0: case cmuClock_USART1: case cmuClock_USART2: ret = SystemHCLKGet() / CMU_ClockDivGet(cmuClock_PCLK); break; case cmuClock_I2C0: case cmuClock_LSPCLK: ret = SystemHCLKGet() / CMU_ClockDivGet(cmuClock_PCLK) / 2U; break; case cmuClock_IADC0: case cmuClock_IADCCLK: iadcClkGet(&ret, NULL); break; case cmuClock_TIMER0: case cmuClock_TIMER1: case cmuClock_TIMER2: case cmuClock_TIMER3: case cmuClock_EM01GRPACLK: em01GrpaClkGet(&ret, NULL); break; case cmuClock_SYSTICK: case cmuClock_LETIMER0: case cmuClock_EM23GRPACLK: em23GrpaClkGet(&ret, NULL); break; case cmuClock_BURTC: case cmuClock_EM4GRPACLK: em4GrpaClkGet(&ret, NULL); break; case cmuClock_WDOG0: case cmuClock_WDOG0CLK: wdog0ClkGet(&ret, NULL); break; case cmuClock_WDOG1: case cmuClock_WDOG1CLK: wdog1ClkGet(&ret, NULL); break; case cmuClock_DPLLREFCLK: dpllRefClkGet(&ret, NULL); break; case cmuClock_TRACECLK: traceClkGet(&ret, NULL); break; case cmuClock_RTCC: case cmuClock_RTCCCLK: rtccClkGet(&ret, NULL); break; default: EFM_ASSERT(false); break; } return ret; } /***************************************************************************//** * @brief * Get currently selected reference clock used for a clock branch. * * @param[in] clock * Clock branch to fetch selected ref. clock for. * * @return * Reference clock used for clocking selected branch, #cmuSelect_Error if * invalid @p clock provided. ******************************************************************************/ CMU_Select_TypeDef CMU_ClockSelectGet(CMU_Clock_TypeDef clock) { CMU_Select_TypeDef ret = cmuSelect_Error; switch (clock) { // ----------------------------------------------------------------------------- case cmuClock_SYSCLK: switch (CMU->SYSCLKCTRL & _CMU_SYSCLKCTRL_CLKSEL_MASK) { case _CMU_SYSCLKCTRL_CLKSEL_HFRCODPLL: ret = cmuSelect_HFRCODPLL; break; case _CMU_SYSCLKCTRL_CLKSEL_HFXO: ret = cmuSelect_HFXO; break; case _CMU_SYSCLKCTRL_CLKSEL_CLKIN0: ret = cmuSelect_CLKIN0; break; case _CMU_SYSCLKCTRL_CLKSEL_FSRCO: ret = cmuSelect_FSRCO; break; default: ret = cmuSelect_Error; EFM_ASSERT(false); break; } break; // ----------------------------------------------------------------------------- case cmuClock_IADC0: case cmuClock_IADCCLK: iadcClkGet(NULL, &ret); break; // ----------------------------------------------------------------------------- case cmuClock_TIMER0: case cmuClock_TIMER1: case cmuClock_TIMER2: case cmuClock_TIMER3: case cmuClock_EM01GRPACLK: em01GrpaClkGet(NULL, &ret); break; // ----------------------------------------------------------------------------- case cmuClock_SYSTICK: case cmuClock_LETIMER0: case cmuClock_EM23GRPACLK: em23GrpaClkGet(NULL, &ret); break; // ----------------------------------------------------------------------------- case cmuClock_BURTC: case cmuClock_EM4GRPACLK: em4GrpaClkGet(NULL, &ret); break; // ----------------------------------------------------------------------------- case cmuClock_WDOG0: case cmuClock_WDOG0CLK: wdog0ClkGet(NULL, &ret); break; // ----------------------------------------------------------------------------- case cmuClock_WDOG1: case cmuClock_WDOG1CLK: wdog1ClkGet(NULL, &ret); break; // ----------------------------------------------------------------------------- case cmuClock_DPLLREFCLK: dpllRefClkGet(NULL, &ret); break; // ----------------------------------------------------------------------------- case cmuClock_TRACECLK: traceClkGet(NULL, &ret); break; // ----------------------------------------------------------------------------- case cmuClock_RTCC: case cmuClock_RTCCCLK: rtccClkGet(NULL, &ret); break; // ----------------------------------------------------------------------------- default: EFM_ASSERT(false); break; } return ret; } /***************************************************************************//** * @brief * Select reference clock/oscillator used for a clock branch. * * @param[in] clock * Clock branch to select reference clock for. * * @param[in] ref * Reference selected for clocking, please refer to reference manual for * for details on which reference is available for a specific clock branch. ******************************************************************************/ void CMU_ClockSelectSet(CMU_Clock_TypeDef clock, CMU_Select_TypeDef ref) { uint32_t tmp = 0U; bool oscForceEnStatus = false; switch (clock) { // ----------------------------------------------------------------------------- case cmuClock_SYSCLK: switch (ref) { case cmuSelect_HFRCODPLL: tmp = CMU_SYSCLKCTRL_CLKSEL_HFRCODPLL; break; case cmuSelect_HFXO: tmp = CMU_SYSCLKCTRL_CLKSEL_HFXO; // Make sure HFXO is enabled oscForceEnStatus = (HFXO0->CTRL & HFXO_CTRL_DISONDEMAND) != 0; HFXO0->CTRL_SET = HFXO_CTRL_FORCEEN; break; case cmuSelect_CLKIN0: tmp = CMU_SYSCLKCTRL_CLKSEL_CLKIN0; break; case cmuSelect_FSRCO: tmp = CMU_SYSCLKCTRL_CLKSEL_FSRCO; break; default: EFM_ASSERT(false); break; } // Set max wait-states and PCLK divisor while changing core clock waitStateMax(); pclkDivMax(); // Switch to selected oscillator CMU->SYSCLKCTRL = (CMU->SYSCLKCTRL & ~_CMU_SYSCLKCTRL_CLKSEL_MASK) | tmp; // Update CMSIS core clock variable and set optimum wait-states CMU_UpdateWaitStates(SystemCoreClockGet(), 0); // Set optimal PCLK divisor pclkDivOptimize(); if (oscForceEnStatus == false) { switch (ref) { case cmuSelect_HFXO: HFXO0->CTRL_CLR = HFXO_CTRL_FORCEEN; break; default: break; } } break; // ----------------------------------------------------------------------------- case cmuClock_IADC0: case cmuClock_IADCCLK: switch (ref) { case cmuSelect_EM01GRPACLK: tmp = CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK; break; case cmuSelect_HFRCOEM23: tmp = CMU_IADCCLKCTRL_CLKSEL_HFRCOEM23; break; case cmuSelect_FSRCO: tmp = CMU_IADCCLKCTRL_CLKSEL_FSRCO; break; default: EFM_ASSERT(false); break; } CMU->IADCCLKCTRL = (CMU->IADCCLKCTRL & ~_CMU_IADCCLKCTRL_CLKSEL_MASK) | tmp; break; // ----------------------------------------------------------------------------- case cmuClock_TIMER0: case cmuClock_TIMER1: case cmuClock_TIMER2: case cmuClock_TIMER3: case cmuClock_EM01GRPACLK: switch (ref) { case cmuSelect_HFRCODPLL: tmp = CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLL; break; case cmuSelect_HFXO: tmp = CMU_EM01GRPACLKCTRL_CLKSEL_HFXO; break; case cmuSelect_HFRCOEM23: tmp = CMU_EM01GRPACLKCTRL_CLKSEL_HFRCOEM23; break; case cmuSelect_FSRCO: tmp = CMU_EM01GRPACLKCTRL_CLKSEL_FSRCO; break; default: EFM_ASSERT(false); break; } CMU->EM01GRPACLKCTRL = (CMU->EM01GRPACLKCTRL & ~_CMU_EM01GRPACLKCTRL_CLKSEL_MASK) | tmp; break; // ----------------------------------------------------------------------------- case cmuClock_SYSTICK: case cmuClock_LETIMER0: case cmuClock_EM23GRPACLK: switch (ref) { case cmuSelect_LFRCO: tmp = CMU_EM23GRPACLKCTRL_CLKSEL_LFRCO; break; case cmuSelect_LFXO: tmp = CMU_EM23GRPACLKCTRL_CLKSEL_LFXO; break; case cmuSelect_ULFRCO: tmp = CMU_EM23GRPACLKCTRL_CLKSEL_ULFRCO; break; default: EFM_ASSERT(false); break; } CMU->EM23GRPACLKCTRL = (CMU->EM23GRPACLKCTRL & ~_CMU_EM23GRPACLKCTRL_CLKSEL_MASK) | tmp; break; // ----------------------------------------------------------------------------- case cmuClock_BURTC: case cmuClock_EM4GRPACLK: switch (ref) { case cmuSelect_LFRCO: tmp = CMU_EM4GRPACLKCTRL_CLKSEL_LFRCO; break; case cmuSelect_LFXO: tmp = CMU_EM4GRPACLKCTRL_CLKSEL_LFXO; break; case cmuSelect_ULFRCO: tmp = CMU_EM4GRPACLKCTRL_CLKSEL_ULFRCO; break; default: EFM_ASSERT(false); break; } CMU->EM4GRPACLKCTRL = (CMU->EM4GRPACLKCTRL & ~_CMU_EM4GRPACLKCTRL_CLKSEL_MASK) | tmp; break; // ----------------------------------------------------------------------------- case cmuClock_WDOG0: case cmuClock_WDOG0CLK: switch (ref) { case cmuSelect_LFRCO: tmp = CMU_WDOG0CLKCTRL_CLKSEL_LFRCO; break; case cmuSelect_LFXO: tmp = CMU_WDOG0CLKCTRL_CLKSEL_LFXO; break; case cmuSelect_ULFRCO: tmp = CMU_WDOG0CLKCTRL_CLKSEL_ULFRCO; break; case cmuSelect_HCLKDIV1024: tmp = CMU_WDOG0CLKCTRL_CLKSEL_HCLKDIV1024; break; default: EFM_ASSERT(false); break; } CMU->WDOG0CLKCTRL = (CMU->WDOG0CLKCTRL & ~_CMU_WDOG0CLKCTRL_CLKSEL_MASK) | tmp; break; // ----------------------------------------------------------------------------- case cmuClock_WDOG1: case cmuClock_WDOG1CLK: switch (ref) { case cmuSelect_LFRCO: tmp = CMU_WDOG1CLKCTRL_CLKSEL_LFRCO; break; case cmuSelect_LFXO: tmp = CMU_WDOG1CLKCTRL_CLKSEL_LFXO; break; case cmuSelect_ULFRCO: tmp = CMU_WDOG1CLKCTRL_CLKSEL_ULFRCO; break; case cmuSelect_HCLKDIV1024: tmp = CMU_WDOG1CLKCTRL_CLKSEL_HCLKDIV1024; break; default: EFM_ASSERT(false); break; } CMU->WDOG1CLKCTRL = (CMU->WDOG1CLKCTRL & ~_CMU_WDOG1CLKCTRL_CLKSEL_MASK) | tmp; break; // ----------------------------------------------------------------------------- case cmuClock_DPLLREFCLK: switch (ref) { case cmuSelect_HFXO: tmp = CMU_DPLLREFCLKCTRL_CLKSEL_HFXO; break; case cmuSelect_LFXO: tmp = CMU_DPLLREFCLKCTRL_CLKSEL_LFXO; break; case cmuSelect_CLKIN0: tmp = CMU_DPLLREFCLKCTRL_CLKSEL_CLKIN0; break; case cmuSelect_Disabled: tmp = CMU_DPLLREFCLKCTRL_CLKSEL_DISABLED; break; default: EFM_ASSERT(false); break; } CMU->DPLLREFCLKCTRL = (CMU->DPLLREFCLKCTRL & ~_CMU_DPLLREFCLKCTRL_CLKSEL_MASK) | tmp; break; // ----------------------------------------------------------------------------- case cmuClock_TRACECLK: switch (ref) { case cmuSelect_HCLK: tmp = CMU_TRACECLKCTRL_CLKSEL_HCLK; break; case cmuSelect_HFRCOEM23: tmp = CMU_TRACECLKCTRL_CLKSEL_HFRCOEM23; break; default: EFM_ASSERT(false); break; } CMU->TRACECLKCTRL = (CMU->TRACECLKCTRL & ~_CMU_TRACECLKCTRL_CLKSEL_MASK) | tmp; break; // ----------------------------------------------------------------------------- case cmuClock_RTCC: case cmuClock_RTCCCLK: switch (ref) { case cmuSelect_LFRCO: tmp = CMU_RTCCCLKCTRL_CLKSEL_LFRCO; break; case cmuSelect_LFXO: tmp = CMU_RTCCCLKCTRL_CLKSEL_LFXO; break; case cmuSelect_ULFRCO: tmp = CMU_RTCCCLKCTRL_CLKSEL_ULFRCO; break; default: EFM_ASSERT(false); break; } CMU->RTCCCLKCTRL = (CMU->RTCCCLKCTRL & ~_CMU_RTCCCLKCTRL_CLKSEL_MASK) | tmp; break; // ----------------------------------------------------------------------------- default: EFM_ASSERT(false); break; } } /**************************************************************************//** * @brief * Lock the DPLL to a given frequency. * The frequency is given by: Fout = Fref * (N+1) / (M+1). * * @note * This function does not check if the given N & M values will actually * produce the desired target frequency. @n * N & M limitations: @n * 300 < N <= 4095 @n * 0 <= M <= 4095 @n * Any peripheral running off HFRCODPLL should be switched to a lower * frequency clock (if possible) prior to calling this function to avoid * over-clocking. * * @param[in] init * DPLL setup parameter struct. * * @return * Returns false on invalid target frequency or DPLL locking error. *****************************************************************************/ bool CMU_DPLLLock(const CMU_DPLLInit_TypeDef *init) { int index = 0; unsigned int i; bool hclkDivIncreased = false; uint32_t hfrcoCalVal, lockStatus, hclkDiv = 0, sysFreq; EFM_ASSERT(init->frequency >= hfrcoCalTable[0].minFreq); EFM_ASSERT(init->frequency <= hfrcoCalTable[HFRCOCALTABLE_ENTRIES - 1U].maxFreq); EFM_ASSERT(init->n > 300U); EFM_ASSERT(init->n <= (_DPLL_CFG1_N_MASK >> _DPLL_CFG1_N_SHIFT)); EFM_ASSERT(init->m <= (_DPLL_CFG1_M_MASK >> _DPLL_CFG1_M_SHIFT)); // Find correct HFRCODPLL band, and retrieve a HFRCOCAL value. for (i = 0; i < HFRCOCALTABLE_ENTRIES; i++) { if ((init->frequency >= hfrcoCalTable[i].minFreq) && (init->frequency <= hfrcoCalTable[i].maxFreq)) { index = (int)i; // Correct band found break; } } if ((uint32_t)index == HFRCOCALTABLE_ENTRIES) { EFM_ASSERT(false); return false; // Target frequency out of spec. } hfrcoCalVal = hfrcoCalTable[index].value; // Check if we have a calibrated HFRCOCAL.TUNING value in device DI page. if (hfrcoCalTable[index].band != (CMU_HFRCODPLLFreq_TypeDef)0) { uint32_t tuning; tuning = (HFRCODPLLDevinfoGet(hfrcoCalTable[index].band) & _HFRCO_CAL_TUNING_MASK) >> _HFRCO_CAL_TUNING_SHIFT; hfrcoCalVal |= tuning << _HFRCO_CAL_TUNING_SHIFT; } // Update CMSIS HFRCODPLL frequency. SystemHFRCODPLLClockSet(init->frequency); if (CMU_ClockSelectGet(cmuClock_SYSCLK) == cmuSelect_HFRCODPLL) { // Set max wait-states and PCLK divisor while changing core clock waitStateMax(); pclkDivMax(); // Increase HCLK divider value (if possible) while locking DPLL to // avoid over-clocking. hclkDiv = CMU_ClockDivGet(cmuClock_HCLK); hclkDivIncreased = true; if (hclkDiv == 1U) { CMU_ClockDivSet(cmuClock_HCLK, 2U); } else if (hclkDiv == 2U) { CMU_ClockDivSet(cmuClock_HCLK, 4U); } else { hclkDivIncreased = false; } } // Make sure DPLL is disabled before configuring DPLL0->EN_CLR = DPLL_EN_EN; while ((DPLL0->STATUS & (DPLL_STATUS_ENS | DPLL_STATUS_RDY)) != 0UL) { } DPLL0->IF_CLR = DPLL_IF_LOCK | DPLL_IF_LOCKFAILLOW | DPLL_IF_LOCKFAILHIGH; DPLL0->CFG1 = ((uint32_t)init->n << _DPLL_CFG1_N_SHIFT) | ((uint32_t)init->m << _DPLL_CFG1_M_SHIFT); HFRCO0->CAL = hfrcoCalVal; CMU_ClockSelectSet(cmuClock_DPLLREFCLK, init->refClk); DPLL0->CFG = ((init->autoRecover ? 1UL : 0UL) << _DPLL_CFG_AUTORECOVER_SHIFT) | ((init->ditherEn ? 1UL : 0UL) << _DPLL_CFG_DITHEN_SHIFT) | ((uint32_t)init->edgeSel << _DPLL_CFG_EDGESEL_SHIFT) | ((uint32_t)init->lockMode << _DPLL_CFG_MODE_SHIFT); // Lock DPLL DPLL0->EN_SET = DPLL_EN_EN; while ((lockStatus = (DPLL0->IF & (DPLL_IF_LOCK | DPLL_IF_LOCKFAILLOW | DPLL_IF_LOCKFAILHIGH))) == 0UL) { } if (CMU_ClockSelectGet(cmuClock_SYSCLK) == cmuSelect_HFRCODPLL) { if (hclkDivIncreased) { // Restore original HCLK divider CMU_ClockDivSet(cmuClock_HCLK, hclkDiv); } // Call @ref SystemCoreClockGet() to update CMSIS core clock variable. sysFreq = SystemCoreClockGet(); EFM_ASSERT(sysFreq <= init->frequency); EFM_ASSERT(sysFreq <= SystemHFRCODPLLClockGet()); EFM_ASSERT(init->frequency == SystemHFRCODPLLClockGet()); // Set optimal wait-states and PCLK divisor CMU_UpdateWaitStates(sysFreq, 0); pclkDivOptimize(); } if (lockStatus == DPLL_IF_LOCK) { return true; } return false; } /***************************************************************************//** * @brief * Get HFRCODPLL band in use. * * @return * HFRCODPLL band in use. ******************************************************************************/ CMU_HFRCODPLLFreq_TypeDef CMU_HFRCODPLLBandGet(void) { return (CMU_HFRCODPLLFreq_TypeDef)SystemHFRCODPLLClockGet(); } /***************************************************************************//** * @brief * Set HFRCODPLL band and the tuning value based on the value in the * calibration table made during production. * * @param[in] freq * HFRCODPLL frequency band to activate. ******************************************************************************/ void CMU_HFRCODPLLBandSet(CMU_HFRCODPLLFreq_TypeDef freq) { uint32_t freqCal, sysFreq; // Get calibration data from DEVINFO freqCal = HFRCODPLLDevinfoGet(freq); EFM_ASSERT((freqCal != 0UL) && (freqCal != UINT_MAX)); // Make sure DPLL is disabled before configuring if (DPLL0->EN_CLR == DPLL_EN_EN) { DPLL0->EN_CLR = DPLL_EN_EN; while ((DPLL0->STATUS & (DPLL_STATUS_ENS | DPLL_STATUS_RDY)) != 0UL) { } } // Update CMSIS HFRCODPLL frequency. SystemHFRCODPLLClockSet(freq); // Set max wait-states and PCLK divisor while changing core clock if (CMU_ClockSelectGet(cmuClock_SYSCLK) == cmuSelect_HFRCODPLL) { waitStateMax(); pclkDivMax(); } // Set divider for 1, 2 and 4MHz bands freqCal &= ~_HFRCO_CAL_CLKDIV_MASK; switch (freq) { case cmuHFRCODPLLFreq_1M0Hz: freqCal |= HFRCO_CAL_CLKDIV_DIV4; break; case cmuHFRCODPLLFreq_2M0Hz: freqCal |= HFRCO_CAL_CLKDIV_DIV2; break; default: break; } // Activate new band selection HFRCO0->CAL = freqCal; // If HFRCODPLL is selected as SYSCLK (and HCLK), optimize flash access // wait-state configuration and PCLK divisor for this frequency. if (CMU_ClockSelectGet(cmuClock_SYSCLK) == cmuSelect_HFRCODPLL) { // Call @ref SystemCoreClockGet() to update CMSIS core clock variable. sysFreq = SystemCoreClockGet(); EFM_ASSERT(sysFreq <= (uint32_t)freq); CMU_UpdateWaitStates(sysFreq, 0); pclkDivOptimize(); } } /***************************************************************************//** * @brief * Get HFRCOEM23 band in use. * * @return * HFRCOEM23 band in use. ******************************************************************************/ CMU_HFRCOEM23Freq_TypeDef CMU_HFRCOEM23BandGet(void) { return (CMU_HFRCOEM23Freq_TypeDef)SystemHFRCOEM23ClockGet(); } /***************************************************************************//** * @brief * Set HFRCOEM23 band and the tuning value based on the value in the * calibration table made during production. * * @param[in] freq * HFRCOEM23 frequency band to activate. ******************************************************************************/ void CMU_HFRCOEM23BandSet(CMU_HFRCOEM23Freq_TypeDef freq) { uint32_t freqCal; // Get calibration data from DEVINFO freqCal = HFRCOEM23DevinfoGet(freq); EFM_ASSERT((freqCal != 0UL) && (freqCal != UINT_MAX)); // Set divider for 1, 2 and 4MHz bands freqCal &= ~_HFRCO_CAL_CLKDIV_MASK; switch (freq) { case cmuHFRCOEM23Freq_1M0Hz: freqCal |= HFRCO_CAL_CLKDIV_DIV4; break; case cmuHFRCOEM23Freq_2M0Hz: freqCal |= HFRCO_CAL_CLKDIV_DIV2; break; default: break; } // Activate new band selection HFRCOEM23->CAL = freqCal; } /**************************************************************************//** * @brief * Initialize all HFXO control registers. * * @note * HFXO configuration should be obtained from a configuration tool, * app note or xtal datasheet. This function returns early if HFXO is * already selected as SYSCLK. * * @param[in] hfxoInit * HFXO setup parameters. *****************************************************************************/ void CMU_HFXOInit(const CMU_HFXOInit_TypeDef *hfxoInit) { // Check all initialization structure members which may overflow target // bitfield. EFM_ASSERT(hfxoInit->timeoutCbLsb <= (_HFXO_XTALCFG_TIMEOUTCBLSB_MASK >> _HFXO_XTALCFG_TIMEOUTCBLSB_SHIFT)); EFM_ASSERT(hfxoInit->timeoutSteadyFirstLock <= (_HFXO_XTALCFG_TIMEOUTSTEADY_MASK >> _HFXO_XTALCFG_TIMEOUTSTEADY_SHIFT)); EFM_ASSERT(hfxoInit->timeoutSteady <= (_HFXO_XTALCFG_TIMEOUTSTEADY_MASK >> _HFXO_XTALCFG_TIMEOUTSTEADY_SHIFT)); EFM_ASSERT(hfxoInit->ctuneXoStartup <= (_HFXO_XTALCFG_CTUNEXOSTARTUP_MASK >> _HFXO_XTALCFG_CTUNEXOSTARTUP_SHIFT)); EFM_ASSERT(hfxoInit->ctuneXiStartup <= (_HFXO_XTALCFG_CTUNEXISTARTUP_MASK >> _HFXO_XTALCFG_CTUNEXISTARTUP_SHIFT)); EFM_ASSERT(hfxoInit->coreBiasStartup <= (_HFXO_XTALCFG_COREBIASSTARTUP_MASK >> _HFXO_XTALCFG_COREBIASSTARTUP_SHIFT)); EFM_ASSERT(hfxoInit->imCoreBiasStartup <= (_HFXO_XTALCFG_COREBIASSTARTUPI_MASK >> _HFXO_XTALCFG_COREBIASSTARTUPI_SHIFT)); EFM_ASSERT(hfxoInit->coreDegenAna <= (_HFXO_XTALCTRL_COREDGENANA_MASK >> _HFXO_XTALCTRL_COREDGENANA_SHIFT)); EFM_ASSERT(hfxoInit->ctuneFixAna <= (_HFXO_XTALCTRL_CTUNEFIXANA_MASK >> _HFXO_XTALCTRL_CTUNEFIXANA_SHIFT)); EFM_ASSERT(hfxoInit->mode <= (_HFXO_CFG_MODE_MASK >> _HFXO_CFG_MODE_SHIFT)); // Return early if HFXO is already selected as SYSCLK. if (CMU_ClockSelectGet(cmuClock_SYSCLK) == cmuSelect_HFXO) { return; } // Unlock register interface HFXO0->LOCK = HFXO_LOCK_LOCKKEY_UNLOCK; // Disable HFXO HFXO0->CTRL_SET = HFXO_CTRL_DISONDEMAND; HFXO0->CTRL_CLR = HFXO_CTRL_FORCEEN; while ((HFXO0->STATUS & _HFXO_STATUS_ENS_MASK) != 0U) { } // Configure HFXO as specified in initialization struct, use // timeoutSteadyFirstLock as TIMEOUTSTEADY value HFXO0->XTALCFG = (hfxoInit->timeoutCbLsb << _HFXO_XTALCFG_TIMEOUTCBLSB_SHIFT) | (hfxoInit->timeoutSteadyFirstLock << _HFXO_XTALCFG_TIMEOUTSTEADY_SHIFT) | (hfxoInit->ctuneXoStartup << _HFXO_XTALCFG_CTUNEXOSTARTUP_SHIFT) | (hfxoInit->ctuneXiStartup << _HFXO_XTALCFG_CTUNEXISTARTUP_SHIFT) | (hfxoInit->coreBiasStartup << _HFXO_XTALCFG_COREBIASSTARTUP_SHIFT) | (hfxoInit->imCoreBiasStartup << _HFXO_XTALCFG_COREBIASSTARTUPI_SHIFT); HFXO0->XTALCTRL = (hfxoInit->coreDegenAna << _HFXO_XTALCTRL_COREDGENANA_SHIFT) | (hfxoInit->ctuneFixAna << _HFXO_XTALCTRL_CTUNEFIXANA_SHIFT) | (hfxoInit->ctuneXoAna << _HFXO_XTALCTRL_CTUNEXOANA_SHIFT) | (hfxoInit->ctuneXiAna << _HFXO_XTALCTRL_CTUNEXIANA_SHIFT) | (hfxoInit->coreBiasAna << _HFXO_XTALCTRL_COREBIASANA_SHIFT); HFXO0->CFG = (HFXO0->CFG & ~(_HFXO_CFG_SQBUFSCHTRGANA_MASK | _HFXO_CFG_ENXIDCBIASANA_MASK | _HFXO_CFG_MODE_MASK)) | ((hfxoInit->mode == cmuHfxoOscMode_Crystal) ? 0 : HFXO_CFG_SQBUFSCHTRGANA) | (hfxoInit->enXiDcBiasAna << _HFXO_CFG_ENXIDCBIASANA_SHIFT) | (hfxoInit->mode << _HFXO_CFG_MODE_SHIFT); if (hfxoInit->mode == cmuHfxoOscMode_Crystal) { // Lock HFXO with FORCEEN bit set and DISONDEMAND bit cleared HFXO0->CTRL = (HFXO0->CTRL & ~(_HFXO_CTRL_FORCEXO2GNDANA_MASK | _HFXO_CTRL_FORCEXI2GNDANA_MASK | _HFXO_CTRL_DISONDEMAND_MASK | _HFXO_CTRL_FORCEEN_MASK)) | (hfxoInit->forceXo2GndAna << _HFXO_CTRL_FORCEXO2GNDANA_SHIFT) | (hfxoInit->forceXi2GndAna << _HFXO_CTRL_FORCEXI2GNDANA_SHIFT) | HFXO_CTRL_FORCEEN; // Wait for HFXO lock and core bias algorithm to complete while ((HFXO0->STATUS & (HFXO_STATUS_RDY | HFXO_STATUS_COREBIASOPTRDY | HFXO_STATUS_ENS | HFXO_STATUS_FSMLOCK)) != (HFXO_STATUS_RDY | HFXO_STATUS_COREBIASOPTRDY | HFXO_STATUS_ENS | HFXO_STATUS_FSMLOCK)) { } // We must set DISONDEMAND to be able to enter new values for use on // subsequent locks HFXO0->CTRL_SET = HFXO_CTRL_DISONDEMAND; while ((HFXO0->STATUS & HFXO_STATUS_FSMLOCK) != 0) { } // Set new TIMEOUTSTEADY value for use on subsequent locks HFXO0->XTALCFG = (HFXO0->XTALCFG & ~_HFXO_XTALCFG_TIMEOUTSTEADY_MASK) | (hfxoInit->timeoutSteady << _HFXO_XTALCFG_TIMEOUTSTEADY_SHIFT); // Skip core bias algorithm on subsequent locks HFXO0->XTALCTRL_SET = HFXO_XTALCTRL_SKIPCOREBIASOPT; if (hfxoInit->disOnDemand == false) { HFXO0->CTRL_CLR = HFXO_CTRL_DISONDEMAND; } if (hfxoInit->forceEn == false) { HFXO0->CTRL_CLR = HFXO_CTRL_FORCEEN; } } else { // Lock HFXO in EXTERNAL SINE mode HFXO0->CTRL = (HFXO0->CTRL & ~(_HFXO_CTRL_FORCEXO2GNDANA_MASK | _HFXO_CTRL_FORCEXI2GNDANA_MASK | _HFXO_CTRL_DISONDEMAND_MASK | _HFXO_CTRL_FORCEEN_MASK)) | (hfxoInit->forceXo2GndAna << _HFXO_CTRL_FORCEXO2GNDANA_SHIFT) | (hfxoInit->forceXi2GndAna << _HFXO_CTRL_FORCEXI2GNDANA_SHIFT) | (hfxoInit->disOnDemand << _HFXO_CTRL_DISONDEMAND_SHIFT) | (hfxoInit->forceEn << _HFXO_CTRL_FORCEEN_SHIFT); } if (hfxoInit->regLock) { HFXO0->LOCK = ~HFXO_LOCK_LOCKKEY_UNLOCK; } } /**************************************************************************//** * @brief * Initialize LFXO control registers. * * @note * LFXO configuration should be obtained from a configuration tool, * app note or xtal datasheet. This function disables the LFXO to ensure * a valid state before update. * * @param[in] lfxoInit * LFXO setup parameters *****************************************************************************/ void CMU_LFXOInit(const CMU_LFXOInit_TypeDef *lfxoInit) { EFM_ASSERT(lfxoInit->timeout <= (_LFXO_CFG_TIMEOUT_MASK >> _LFXO_CFG_TIMEOUT_SHIFT)); EFM_ASSERT(lfxoInit->mode <= (_LFXO_CFG_MODE_MASK >> _LFXO_CFG_MODE_SHIFT)); EFM_ASSERT(lfxoInit->gain <= (_LFXO_CAL_GAIN_MASK >> _LFXO_CAL_GAIN_SHIFT)); EFM_ASSERT(lfxoInit->capTune <= (_LFXO_CAL_CAPTUNE_MASK >> _LFXO_CAL_CAPTUNE_SHIFT)); // Max internal capacitance tuning value is 0x4F (20 pF) uint8_t ctune = SL_MIN(0x4FU, lfxoInit->capTune); // Unlock register interface LFXO->LOCK = LFXO_LOCK_LOCKKEY_UNLOCK; // Disable LFXO LFXO->CTRL_SET = LFXO_CTRL_DISONDEMAND; LFXO->CTRL_CLR = LFXO_CTRL_FORCEEN; while ((LFXO->STATUS & _LFXO_STATUS_ENS_MASK) != 0U) { } // Configure LFXO as specified LFXO->CAL = (lfxoInit->gain << _LFXO_CAL_GAIN_SHIFT) | (ctune << _LFXO_CAL_CAPTUNE_SHIFT); LFXO->CFG = (lfxoInit->timeout << _LFXO_CFG_TIMEOUT_SHIFT) | (lfxoInit->mode << _LFXO_CFG_MODE_SHIFT) | (lfxoInit->highAmplitudeEn << _LFXO_CFG_HIGHAMPL_SHIFT) | (lfxoInit->agcEn << _LFXO_CFG_AGC_SHIFT); LFXO->CTRL = (lfxoInit->failDetEM4WUEn << _LFXO_CTRL_FAILDETEM4WUEN_SHIFT) | (lfxoInit->failDetEn << _LFXO_CTRL_FAILDETEN_SHIFT) | (lfxoInit->disOnDemand << _LFXO_CTRL_DISONDEMAND_SHIFT) | (lfxoInit->forceEn << _LFXO_CTRL_FORCEEN_SHIFT); if (lfxoInit->regLock) { LFXO->LOCK = ~LFXO_LOCK_LOCKKEY_UNLOCK; } } /***************************************************************************//** * @brief * Get oscillator frequency tuning setting. * * @param[in] osc * Oscillator to get tuning value for. * * @return * The oscillator frequency tuning setting in use. ******************************************************************************/ uint32_t CMU_OscillatorTuningGet(CMU_Osc_TypeDef osc) { uint32_t ret = 0U; switch (osc) { case cmuOsc_LFRCO: ret = (LFRCO->CAL & _LFRCO_CAL_FREQTRIM_MASK) >> _LFRCO_CAL_FREQTRIM_SHIFT; break; case cmuOsc_HFRCODPLL: ret = (HFRCO0->CAL & _HFRCO_CAL_TUNING_MASK) >> _HFRCO_CAL_TUNING_SHIFT; break; case cmuOsc_HFRCOEM23: ret = (HFRCOEM23->CAL & _HFRCO_CAL_TUNING_MASK) >> _HFRCO_CAL_TUNING_SHIFT; break; default: EFM_ASSERT(false); break; } return ret; } /***************************************************************************//** * @brief * Set the oscillator frequency tuning control. * * @note * Oscillator tuning is done during production, and the tuning value is * automatically loaded after a reset. Changing the tuning value from the * calibrated value is for more advanced use. Certain oscillators also have * build-in tuning optimization. * * @param[in] osc * Oscillator to set tuning value for. * * @param[in] val * The oscillator frequency tuning setting to use. ******************************************************************************/ void CMU_OscillatorTuningSet(CMU_Osc_TypeDef osc, uint32_t val) { switch (osc) { case cmuOsc_LFRCO: EFM_ASSERT(val <= (_LFRCO_CAL_FREQTRIM_MASK >> _LFRCO_CAL_FREQTRIM_SHIFT)); val &= _LFRCO_CAL_FREQTRIM_MASK >> _LFRCO_CAL_FREQTRIM_SHIFT; LFRCO->CAL = (LFRCO->CAL & ~_LFRCO_CAL_FREQTRIM_MASK) | (val << _LFRCO_CAL_FREQTRIM_SHIFT); break; case cmuOsc_HFRCODPLL: EFM_ASSERT(val <= (_HFRCO_CAL_TUNING_MASK >> _HFRCO_CAL_TUNING_SHIFT)); val &= _HFRCO_CAL_TUNING_MASK >> _HFRCO_CAL_TUNING_SHIFT; while ((HFRCO0->STATUS & HFRCO_STATUS_SYNCBUSY) != 0UL) { } HFRCO0->CAL = (HFRCO0->CAL & ~_HFRCO_CAL_TUNING_MASK) | (val << _HFRCO_CAL_TUNING_SHIFT); break; case cmuOsc_HFRCOEM23: EFM_ASSERT(val <= (_HFRCO_CAL_TUNING_MASK >> _HFRCO_CAL_TUNING_SHIFT)); val &= _HFRCO_CAL_TUNING_MASK >> _HFRCO_CAL_TUNING_SHIFT; while ((HFRCOEM23->STATUS & HFRCO_STATUS_SYNCBUSY) != 0UL) { } HFRCOEM23->CAL = (HFRCOEM23->CAL & ~_HFRCO_CAL_TUNING_MASK) | (val << _HFRCO_CAL_TUNING_SHIFT); break; default: EFM_ASSERT(false); break; } } /***************************************************************************//** * @brief * Configure wait state settings necessary to switch to a given core clock * frequency. * * @details * This function will setup the necessary flash and RAM wait states. * Updating the wait state configuration must be done before * increasing the clock frequency, and it must be done after decreasing the * clock frequency. * * @param[in] freq * Core clock frequency to configure wait-states for. ******************************************************************************/ void CMU_UpdateWaitStates(uint32_t freq, int vscale) { (void)vscale; waitStateSet(freq); } /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ /******************************************************************************* ************************** LOCAL FUNCTIONS ******************************** ******************************************************************************/ /***************************************************************************//** * @brief * Get calibrated HFRCODPLL tuning value from Device information (DI) page * for a given frequency. Calibration value is not available for all frequency * bands. * * @param[in] freq * HFRCODPLL frequency band ******************************************************************************/ static uint32_t HFRCODPLLDevinfoGet(CMU_HFRCODPLLFreq_TypeDef freq) { uint32_t ret = 0U; switch (freq) { // 1, 2 and 4MHz share the same calibration word case cmuHFRCODPLLFreq_1M0Hz: case cmuHFRCODPLLFreq_2M0Hz: case cmuHFRCODPLLFreq_4M0Hz: ret = DEVINFO->HFRCODPLLCAL[0].HFRCODPLLCAL; break; case cmuHFRCODPLLFreq_7M0Hz: ret = DEVINFO->HFRCODPLLCAL[3].HFRCODPLLCAL; break; case cmuHFRCODPLLFreq_13M0Hz: ret = DEVINFO->HFRCODPLLCAL[6].HFRCODPLLCAL; break; case cmuHFRCODPLLFreq_16M0Hz: ret = DEVINFO->HFRCODPLLCAL[7].HFRCODPLLCAL; break; case cmuHFRCODPLLFreq_19M0Hz: ret = DEVINFO->HFRCODPLLCAL[8].HFRCODPLLCAL; break; case cmuHFRCODPLLFreq_26M0Hz: ret = DEVINFO->HFRCODPLLCAL[10].HFRCODPLLCAL; break; case cmuHFRCODPLLFreq_32M0Hz: ret = DEVINFO->HFRCODPLLCAL[11].HFRCODPLLCAL; break; case cmuHFRCODPLLFreq_38M0Hz: ret = DEVINFO->HFRCODPLLCAL[12].HFRCODPLLCAL; break; case cmuHFRCODPLLFreq_48M0Hz: ret = DEVINFO->HFRCODPLLCAL[13].HFRCODPLLCAL; break; case cmuHFRCODPLLFreq_56M0Hz: ret = DEVINFO->HFRCODPLLCAL[14].HFRCODPLLCAL; break; case cmuHFRCODPLLFreq_64M0Hz: ret = DEVINFO->HFRCODPLLCAL[15].HFRCODPLLCAL; break; case cmuHFRCODPLLFreq_80M0Hz: ret = DEVINFO->HFRCODPLLCAL[16].HFRCODPLLCAL; break; case cmuHFRCODPLLFreq_UserDefined: break; default: EFM_ASSERT(false); break; } return ret; } /***************************************************************************//** * @brief * Get calibrated HFRCOEM23 tuning value from Device information (DI) page * for a given frequency. Calibration value is not available for all frequency * bands. * * @param[in] freq * HFRCOEM23 frequency band ******************************************************************************/ static uint32_t HFRCOEM23DevinfoGet(CMU_HFRCOEM23Freq_TypeDef freq) { uint32_t ret = 0U; switch (freq) { // 1, 2 and 4MHz share the same calibration word case cmuHFRCOEM23Freq_1M0Hz: case cmuHFRCOEM23Freq_2M0Hz: case cmuHFRCOEM23Freq_4M0Hz: ret = DEVINFO->HFRCOEM23CAL[0].HFRCOEM23CAL; break; case cmuHFRCOEM23Freq_13M0Hz: ret = DEVINFO->HFRCOEM23CAL[6].HFRCOEM23CAL; break; case cmuHFRCOEM23Freq_16M0Hz: ret = DEVINFO->HFRCOEM23CAL[7].HFRCOEM23CAL; break; case cmuHFRCOEM23Freq_19M0Hz: ret = DEVINFO->HFRCOEM23CAL[8].HFRCOEM23CAL; break; case cmuHFRCOEM23Freq_26M0Hz: ret = DEVINFO->HFRCOEM23CAL[10].HFRCOEM23CAL; break; case cmuHFRCOEM23Freq_32M0Hz: ret = DEVINFO->HFRCOEM23CAL[11].HFRCOEM23CAL; break; case cmuHFRCOEM23Freq_40M0Hz: ret = DEVINFO->HFRCOEM23CAL[12].HFRCOEM23CAL; break; case cmuHFRCOEM23Freq_UserDefined: break; default: EFM_ASSERT(false); break; } return ret; } /***************************************************************************//** * @brief * Get selected oscillator and frequency for @ref cmuClock_DPLLREFCLK * clock tree. * * @param[out] freq * The frequency. * * @param[out] sel * The selected oscillator. ******************************************************************************/ static void dpllRefClkGet(uint32_t *freq, CMU_Select_TypeDef *sel) { uint32_t f = 0U; CMU_Select_TypeDef s; switch (CMU->DPLLREFCLKCTRL & _CMU_DPLLREFCLKCTRL_CLKSEL_MASK) { case _CMU_DPLLREFCLKCTRL_CLKSEL_HFXO: f = SystemHFXOClockGet(); s = cmuSelect_HFXO; break; case _CMU_DPLLREFCLKCTRL_CLKSEL_LFXO: f = SystemLFXOClockGet(); s = cmuSelect_LFXO; break; case _CMU_DPLLREFCLKCTRL_CLKSEL_CLKIN0: f = SystemCLKIN0Get(); s = cmuSelect_CLKIN0; break; case _CMU_DPLLREFCLKCTRL_CLKSEL_DISABLED: s = cmuSelect_Disabled; break; default: s = cmuSelect_Error; EFM_ASSERT(false); break; } if (freq != NULL) { *freq = f; } if (sel != NULL) { *sel = s; } } /***************************************************************************//** * @brief * Get selected oscillator and frequency for @ref cmuClock_EM01GRPACLK * clock tree. * * @param[out] freq * The frequency. * * @param[out] sel * The selected oscillator. ******************************************************************************/ static void em01GrpaClkGet(uint32_t *freq, CMU_Select_TypeDef *sel) { uint32_t f = 0U; CMU_Select_TypeDef s; switch (CMU->EM01GRPACLKCTRL & _CMU_EM01GRPACLKCTRL_CLKSEL_MASK) { case _CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLL: f = SystemHFRCODPLLClockGet(); s = cmuSelect_HFRCODPLL; break; case _CMU_EM01GRPACLKCTRL_CLKSEL_HFXO: f = SystemHFXOClockGet(); s = cmuSelect_HFXO; break; case _CMU_EM01GRPACLKCTRL_CLKSEL_HFRCOEM23: f = SystemHFRCOEM23ClockGet(); s = cmuSelect_HFRCOEM23; break; case _CMU_EM01GRPACLKCTRL_CLKSEL_FSRCO: f = SystemFSRCOClockGet(); s = cmuSelect_FSRCO; break; default: s = cmuSelect_Error; EFM_ASSERT(false); break; } if (freq != NULL) { *freq = f; } if (sel != NULL) { *sel = s; } } /***************************************************************************//** * @brief * Get selected oscillator and frequency for @ref cmuClock_EM23GRPACLK * clock tree. * * @param[out] freq * The frequency. * * @param[out] sel * The selected oscillator. ******************************************************************************/ static void em23GrpaClkGet(uint32_t *freq, CMU_Select_TypeDef *sel) { uint32_t f = 0U; CMU_Select_TypeDef s; switch (CMU->EM23GRPACLKCTRL & _CMU_EM23GRPACLKCTRL_CLKSEL_MASK) { case _CMU_EM23GRPACLKCTRL_CLKSEL_LFRCO: f = SystemLFRCOClockGet(); s = cmuSelect_LFRCO; break; case _CMU_EM23GRPACLKCTRL_CLKSEL_LFXO: f = SystemLFXOClockGet(); s = cmuSelect_LFXO; break; case _CMU_EM23GRPACLKCTRL_CLKSEL_ULFRCO: f = SystemULFRCOClockGet(); s = cmuSelect_ULFRCO; break; default: s = cmuSelect_Error; EFM_ASSERT(false); break; } if (freq != NULL) { *freq = f; } if (sel != NULL) { *sel = s; } } /***************************************************************************//** * @brief * Get selected oscillator and frequency for @ref cmuClock_EM4GRPACLK * clock tree. * * @param[out] freq * The frequency. * * @param[out] sel * The selected oscillator. ******************************************************************************/ static void em4GrpaClkGet(uint32_t *freq, CMU_Select_TypeDef *sel) { uint32_t f = 0U; CMU_Select_TypeDef s; switch (CMU->EM4GRPACLKCTRL & _CMU_EM4GRPACLKCTRL_CLKSEL_MASK) { case _CMU_EM4GRPACLKCTRL_CLKSEL_LFRCO: f = SystemLFRCOClockGet(); s = cmuSelect_LFRCO; break; case _CMU_EM4GRPACLKCTRL_CLKSEL_LFXO: f = SystemLFXOClockGet(); s = cmuSelect_LFXO; break; case _CMU_EM4GRPACLKCTRL_CLKSEL_ULFRCO: f = SystemULFRCOClockGet(); s = cmuSelect_ULFRCO; break; default: s = cmuSelect_Error; EFM_ASSERT(false); break; } if (freq != NULL) { *freq = f; } if (sel != NULL) { *sel = s; } } /***************************************************************************//** * @brief * Get selected oscillator and frequency for @ref cmuClock_IADCCLK * clock tree. * * @param[out] freq * The frequency. * * @param[out] sel * The selected oscillator. ******************************************************************************/ static void iadcClkGet(uint32_t *freq, CMU_Select_TypeDef *sel) { uint32_t f = 0U; CMU_Select_TypeDef s; switch (CMU->IADCCLKCTRL & _CMU_IADCCLKCTRL_CLKSEL_MASK) { case _CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK: em01GrpaClkGet(&f, NULL); s = cmuSelect_EM01GRPACLK; break; case _CMU_IADCCLKCTRL_CLKSEL_HFRCOEM23: f = SystemHFRCOEM23ClockGet(); s = cmuSelect_HFRCOEM23; break; case _CMU_IADCCLKCTRL_CLKSEL_FSRCO: f = SystemFSRCOClockGet(); s = cmuSelect_FSRCO; break; default: s = cmuSelect_Error; EFM_ASSERT(false); break; } if (freq != NULL) { *freq = f; } if (sel != NULL) { *sel = s; } } /***************************************************************************//** * @brief * Set maximum allowed divisor for @ref cmuClock_PCLK clock tree. ******************************************************************************/ static void pclkDivMax(void) { // Set largest divisor for PCLK clock tree CMU_ClockDivSet(cmuClock_PCLK, 2U); } /***************************************************************************//** * @brief * Set @ref cmuClock_PCLK clock tree divisor to achieve highest possible * frequency and still be within spec. ******************************************************************************/ static void pclkDivOptimize(void) { CMU_ClkDiv_TypeDef div = 2U; if (CMU_ClockFreqGet(cmuClock_HCLK) <= CMU_MAX_PCLK_FREQ) { div = 1U; } CMU_ClockDivSet(cmuClock_PCLK, div); } /***************************************************************************//** * @brief * Get selected oscillator and frequency for @ref cmuClock_RTCCCLK * clock tree. * * @param[out] freq * The frequency. * * @param[out] sel * The selected oscillator. ******************************************************************************/ static void rtccClkGet(uint32_t *freq, CMU_Select_TypeDef *sel) { uint32_t f = 0U; CMU_Select_TypeDef s; switch (CMU->RTCCCLKCTRL & _CMU_RTCCCLKCTRL_CLKSEL_MASK) { case _CMU_RTCCCLKCTRL_CLKSEL_LFRCO: f = SystemLFRCOClockGet(); s = cmuSelect_LFRCO; break; case _CMU_RTCCCLKCTRL_CLKSEL_LFXO: f = SystemLFXOClockGet(); s = cmuSelect_LFXO; break; case _CMU_RTCCCLKCTRL_CLKSEL_ULFRCO: f = SystemULFRCOClockGet(); s = cmuSelect_ULFRCO; break; default: s = cmuSelect_Error; EFM_ASSERT(false); break; } if (freq != NULL) { *freq = f; } if (sel != NULL) { *sel = s; } } /***************************************************************************//** * @brief * Get selected oscillator and frequency for @ref cmuClock_TRACECLK * clock tree. * * @param[out] freq * The frequency. * * @param[out] sel * The selected oscillator. ******************************************************************************/ static void traceClkGet(uint32_t *freq, CMU_Select_TypeDef *sel) { uint32_t f = 0U; CMU_Select_TypeDef s; switch (CMU->TRACECLKCTRL & _CMU_TRACECLKCTRL_CLKSEL_MASK) { case _CMU_TRACECLKCTRL_CLKSEL_PCLK: f = SystemHCLKGet() / CMU_ClockDivGet(cmuClock_PCLK); s = cmuSelect_PCLK; break; case _CMU_TRACECLKCTRL_CLKSEL_HCLK: f = SystemHCLKGet(); s = cmuSelect_HCLK; break; case _CMU_TRACECLKCTRL_CLKSEL_HFRCOEM23: f = SystemHFRCOEM23ClockGet(); s = cmuSelect_HFRCOEM23; break; default: s = cmuSelect_Error; EFM_ASSERT(false); break; } if (freq != NULL) { *freq = f; } if (sel != NULL) { *sel = s; } } /***************************************************************************//** * @brief * Set wait-states to values valid for maximum allowable core clock frequency. ******************************************************************************/ static void waitStateMax(void) { waitStateSet(SystemMaxCoreClockGet()); } /***************************************************************************//** * @brief * Set wait-state settings valid for a given core clock frequency. * * @param[out] coreFreq * Core clock frequency. ******************************************************************************/ static void waitStateSet(uint32_t coreFreq) { uint32_t mode; bool mscLocked; // Make sure the MSC is unlocked mscLocked = (MSC->STATUS & _MSC_STATUS_REGLOCK_MASK) == MSC_STATUS_REGLOCK_LOCKED; MSC->LOCK = MSC_LOCK_LOCKKEY_UNLOCK; // Get current flash read setting mode = MSC->READCTRL & ~_MSC_READCTRL_MODE_MASK; // Set new mode based on the core clock frequency if (coreFreq <= CMU_MAX_FLASHREAD_FREQ_0WS) { mode |= MSC_READCTRL_MODE_WS0; } else { mode |= MSC_READCTRL_MODE_WS1; } MSC->READCTRL = mode; // Get current sram read setting mode = SYSCFG->DMEM0RAMCTRL & ~_SYSCFG_DMEM0RAMCTRL_RAMWSEN_MASK; // Set new mode based on the core clock frequency if (coreFreq > CMU_MAX_SRAM_FREQ_0WS) { mode |= 1 << _SYSCFG_DMEM0RAMCTRL_RAMWSEN_SHIFT; } SYSCFG->DMEM0RAMCTRL = mode; if (mscLocked) { MSC->LOCK = MSC_LOCK_LOCKKEY_LOCK; } } /***************************************************************************//** * @brief * Get selected oscillator and frequency for @ref cmuClock_WDOG0CLK * clock tree. * * @param[out] freq * The frequency. * * @param[out] sel * The selected oscillator. ******************************************************************************/ static void wdog0ClkGet(uint32_t *freq, CMU_Select_TypeDef *sel) { uint32_t f = 0U; CMU_Select_TypeDef s; switch (CMU->WDOG0CLKCTRL & _CMU_WDOG0CLKCTRL_CLKSEL_MASK) { case _CMU_WDOG0CLKCTRL_CLKSEL_LFRCO: f = SystemLFRCOClockGet(); s = cmuSelect_LFRCO; break; case _CMU_WDOG0CLKCTRL_CLKSEL_LFXO: f = SystemLFXOClockGet(); s = cmuSelect_LFXO; break; case _CMU_WDOG0CLKCTRL_CLKSEL_ULFRCO: f = SystemULFRCOClockGet(); s = cmuSelect_ULFRCO; break; case _CMU_WDOG0CLKCTRL_CLKSEL_HCLKDIV1024: f = SystemHCLKGet() / 1024U; s = cmuSelect_HCLKDIV1024; break; default: s = cmuSelect_Error; EFM_ASSERT(false); break; } if (freq != NULL) { *freq = f; } if (sel != NULL) { *sel = s; } } /***************************************************************************//** * @brief * Get selected oscillator and frequency for @ref cmuClock_WDOG1CLK * clock tree. * * @param[out] freq * The frequency. * * @param[out] sel * The selected oscillator. ******************************************************************************/ static void wdog1ClkGet(uint32_t *freq, CMU_Select_TypeDef *sel) { uint32_t f = 0U; CMU_Select_TypeDef s; switch (CMU->WDOG1CLKCTRL & _CMU_WDOG1CLKCTRL_CLKSEL_MASK) { case _CMU_WDOG1CLKCTRL_CLKSEL_LFRCO: f = SystemLFRCOClockGet(); s = cmuSelect_LFRCO; break; case _CMU_WDOG1CLKCTRL_CLKSEL_LFXO: f = SystemLFXOClockGet(); s = cmuSelect_LFXO; break; case _CMU_WDOG1CLKCTRL_CLKSEL_ULFRCO: f = SystemULFRCOClockGet(); s = cmuSelect_ULFRCO; break; case _CMU_WDOG1CLKCTRL_CLKSEL_HCLKDIV1024: f = SystemHCLKGet() / 1024U; s = cmuSelect_HCLKDIV1024; break; default: s = cmuSelect_Error; EFM_ASSERT(false); break; } if (freq != NULL) { *freq = f; } if (sel != NULL) { *sel = s; } } /** @endcond */ #else // defined(_SILICON_LABS_32B_SERIES_2) /******************************************************************************* ****************************** DEFINES ************************************ ******************************************************************************/ /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ #if defined(_SILICON_LABS_32B_SERIES_0) /** The maximum allowed core frequency when using 0 wait-states on flash access. */ #define CMU_MAX_FREQ_0WS 16000000 /** The maximum allowed core frequency when using 1 wait-states on flash access */ #define CMU_MAX_FREQ_1WS 32000000 #elif (_SILICON_LABS_GECKO_INTERNAL_SDID == 80) // EFR32xG1x and EFM32xG1x #define CMU_MAX_FREQ_0WS_1V2 25000000 #define CMU_MAX_FREQ_1WS_1V2 40000000 #elif (_SILICON_LABS_GECKO_INTERNAL_SDID == 84) // EFR32xG12x and EFM32xG12x #define CMU_MAX_FREQ_0WS_1V2 25000000 #define CMU_MAX_FREQ_1WS_1V2 40000000 #define CMU_MAX_FREQ_0WS_1V1 21330000 #define CMU_MAX_FREQ_1WS_1V1 32000000 #define CMU_MAX_FREQ_0WS_1V0 7000000 #define CMU_MAX_FREQ_1WS_1V0 14000000 #define CMU_MAX_FREQ_2WS_1V0 20000000 #elif (_SILICON_LABS_GECKO_INTERNAL_SDID == 89) // EFR32xG13x and EFM32xG13x #define CMU_MAX_FREQ_0WS_1V2 25000000 #define CMU_MAX_FREQ_1WS_1V2 40000000 #define CMU_MAX_FREQ_0WS_1V0 7000000 #define CMU_MAX_FREQ_1WS_1V0 14000000 #define CMU_MAX_FREQ_2WS_1V0 20000000 #elif (_SILICON_LABS_GECKO_INTERNAL_SDID == 95) // EFR32xG14x and EFM32xG14x #define CMU_MAX_FREQ_0WS_1V2 25000000 #define CMU_MAX_FREQ_1WS_1V2 40000000 #define CMU_MAX_FREQ_0WS_1V0 7000000 #define CMU_MAX_FREQ_1WS_1V0 14000000 #define CMU_MAX_FREQ_2WS_1V0 20000000 #elif (_SILICON_LABS_GECKO_INTERNAL_SDID == 100) // EFM32GG11x #define CMU_MAX_FREQ_0WS_1V2 18000000 #define CMU_MAX_FREQ_1WS_1V2 36000000 #define CMU_MAX_FREQ_2WS_1V2 54000000 #define CMU_MAX_FREQ_3WS_1V2 72000000 #define CMU_MAX_FREQ_0WS_1V0 7000000 #define CMU_MAX_FREQ_1WS_1V0 14000000 #define CMU_MAX_FREQ_2WS_1V0 20000000 #elif (_SILICON_LABS_GECKO_INTERNAL_SDID == 103) // EFM32TG11x #define CMU_MAX_FREQ_0WS_1V2 25000000 #define CMU_MAX_FREQ_1WS_1V2 48000000 #define CMU_MAX_FREQ_0WS_1V0 10000000 #define CMU_MAX_FREQ_1WS_1V0 21000000 #define CMU_MAX_FREQ_2WS_1V0 20000000 #elif (_SILICON_LABS_GECKO_INTERNAL_SDID == 106) // EFM32GG12x #define CMU_MAX_FREQ_0WS_1V2 18000000 #define CMU_MAX_FREQ_1WS_1V2 36000000 #define CMU_MAX_FREQ_2WS_1V2 54000000 #define CMU_MAX_FREQ_3WS_1V2 72000000 #define CMU_MAX_FREQ_0WS_1V0 7000000 #define CMU_MAX_FREQ_1WS_1V0 14000000 #define CMU_MAX_FREQ_2WS_1V0 20000000 #else #error "Max Flash wait-state frequencies are not defined for this platform." #endif /** The maximum frequency for the HFLE interface. */ #if defined(CMU_CTRL_HFLE) /** The maximum HFLE frequency for series 0 EFM32 and EZR32 Wonder Gecko. */ #if defined(_SILICON_LABS_32B_SERIES_0) \ && (defined(_EFM32_WONDER_FAMILY) \ || defined(_EZR32_WONDER_FAMILY)) #define CMU_MAX_FREQ_HFLE 24000000UL /** The maximum HFLE frequency for other series 0 parts with maximum core clock higher than 32 MHz. */ #elif defined(_SILICON_LABS_32B_SERIES_0) \ && (defined(_EFM32_GIANT_FAMILY) \ || defined(_EZR32_LEOPARD_FAMILY)) #define CMU_MAX_FREQ_HFLE maxFreqHfle() #endif #elif defined(CMU_CTRL_WSHFLE) /** The maximum HFLE frequency for series 1 parts. */ #define CMU_MAX_FREQ_HFLE 32000000UL #endif #if defined(CMU_STATUS_HFXOSHUNTOPTRDY) #define HFXO_TUNING_READY_FLAGS (CMU_STATUS_HFXOPEAKDETRDY | CMU_STATUS_HFXOSHUNTOPTRDY) #define HFXO_TUNING_MODE_AUTO (_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_AUTOCMD) #define HFXO_TUNING_MODE_CMD (_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_CMD) #elif defined(CMU_STATUS_HFXOPEAKDETRDY) #define HFXO_TUNING_READY_FLAGS (CMU_STATUS_HFXOPEAKDETRDY) #define HFXO_TUNING_MODE_AUTO (_CMU_HFXOCTRL_PEAKDETMODE_AUTOCMD) #define HFXO_TUNING_MODE_CMD (_CMU_HFXOCTRL_PEAKDETMODE_CMD) #endif #if defined(CMU_HFXOCTRL_MODE_EXTCLK) /** HFXO external clock mode is renamed from EXTCLK to DIGEXTCLK. */ #define CMU_HFXOCTRL_MODE_DIGEXTCLK CMU_HFXOCTRL_MODE_EXTCLK #endif #if defined(_EMU_CMD_EM01VSCALE0_MASK) #define VSCALE_DEFAULT (EMU_VScaleGet()) #else #define VSCALE_DEFAULT 0 #endif /******************************************************************************* ************************** LOCAL VARIABLES ******************************** ******************************************************************************/ #if defined(_CMU_AUXHFRCOCTRL_FREQRANGE_MASK) static CMU_AUXHFRCOFreq_TypeDef auxHfrcoFreq = cmuAUXHFRCOFreq_19M0Hz; #endif #if defined(_CMU_STATUS_HFXOSHUNTOPTRDY_MASK) #define HFXO_INVALID_TRIM (~_CMU_HFXOTRIMSTATUS_MASK) #endif #if defined(CMU_OSCENCMD_DPLLEN) /** A table of HFRCOCTRL values and their associated minimum/maximum frequencies and an optional band enumerator. */ static const struct hfrcoCtrlTableElement{ uint32_t minFreq; uint32_t maxFreq; uint32_t value; CMU_HFRCOFreq_TypeDef band; } hfrcoCtrlTable[] = { // minFreq maxFreq HFRCOCTRL value band { 860000UL, 1050000UL, 0xBC601F00UL, cmuHFRCOFreq_1M0Hz }, { 1050000UL, 1280000UL, 0xBC611F35UL, (CMU_HFRCOFreq_TypeDef)0 }, { 1280000UL, 1480000UL, 0xBCA21F35UL, (CMU_HFRCOFreq_TypeDef)0 }, { 1480000UL, 1800000UL, 0xAD231F35UL, (CMU_HFRCOFreq_TypeDef)0 }, { 1800000UL, 2110000UL, 0xBA601F00UL, cmuHFRCOFreq_2M0Hz }, { 2110000UL, 2560000UL, 0xBA611F35UL, (CMU_HFRCOFreq_TypeDef)0 }, { 2560000UL, 2970000UL, 0xBAA21F35UL, (CMU_HFRCOFreq_TypeDef)0 }, { 2970000UL, 3600000UL, 0xAB231F35UL, (CMU_HFRCOFreq_TypeDef)0 }, { 3600000UL, 4220000UL, 0xB8601F00UL, cmuHFRCOFreq_4M0Hz }, { 4220000UL, 5120000UL, 0xB8611F35UL, (CMU_HFRCOFreq_TypeDef)0 }, { 5120000UL, 5930000UL, 0xB8A21F35UL, (CMU_HFRCOFreq_TypeDef)0 }, { 5930000UL, 7520000UL, 0xA9231F00UL, cmuHFRCOFreq_7M0Hz }, { 7520000UL, 9520000UL, 0x99241F35UL, (CMU_HFRCOFreq_TypeDef)0 }, { 9520000UL, 11800000UL, 0x99251F35UL, (CMU_HFRCOFreq_TypeDef)0 }, { 11800000UL, 14400000UL, 0x99261F00UL, cmuHFRCOFreq_13M0Hz }, { 14400000UL, 17200000UL, 0x99271F00UL, cmuHFRCOFreq_16M0Hz }, { 17200000UL, 19700000UL, 0x99481F00UL, cmuHFRCOFreq_19M0Hz }, { 19700000UL, 23800000UL, 0x99491F35UL, (CMU_HFRCOFreq_TypeDef)0 }, { 23800000UL, 28700000UL, 0x994A1F00UL, cmuHFRCOFreq_26M0Hz }, { 28700000UL, 34800000UL, 0x996B1F00UL, cmuHFRCOFreq_32M0Hz }, #if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_84) \ || defined(_SILICON_LABS_GECKO_INTERNAL_SDID_89) \ || defined(_SILICON_LABS_GECKO_INTERNAL_SDID_95) { 34800000UL, 40000000UL, 0x996C1F00UL, cmuHFRCOFreq_38M0Hz } #elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_100) \ || defined(_SILICON_LABS_GECKO_INTERNAL_SDID_106) { 34800000UL, 42800000UL, 0x996C1F00UL, cmuHFRCOFreq_38M0Hz }, { 42800000UL, 51600000UL, 0x996D1F00UL, cmuHFRCOFreq_48M0Hz }, { 51600000UL, 60500000UL, 0x998E1F00UL, cmuHFRCOFreq_56M0Hz }, { 60500000UL, 72000000UL, 0xA98F1F00UL, cmuHFRCOFreq_64M0Hz } #elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_103) { 34800000UL, 42800000UL, 0x996C1F00UL, cmuHFRCOFreq_38M0Hz }, { 42800000UL, 48000000UL, 0x996D1F00UL, cmuHFRCOFreq_48M0Hz } #else #error "HFRCOCTRL values not set for this platform." #endif }; #define HFRCOCTRLTABLE_ENTRIES (sizeof(hfrcoCtrlTable) \ / sizeof(struct hfrcoCtrlTableElement)) #endif // CMU_OSCENCMD_DPLLEN #if defined(_SILICON_LABS_32B_SERIES_1) && defined(_EMU_STATUS_VSCALE_MASK) /* Devices with Voltage Scaling needs extra handling of wait states. */ static const struct flashWsTableElement{ uint32_t maxFreq; uint8_t vscale; uint8_t ws; } flashWsTable[] = { #if (_SILICON_LABS_GECKO_INTERNAL_SDID == 100 || _SILICON_LABS_GECKO_INTERNAL_SDID == 106) { CMU_MAX_FREQ_0WS_1V2, 0, 0 }, /* 0 wait states at max frequency 18 MHz and 1.2V */ { CMU_MAX_FREQ_1WS_1V2, 0, 1 }, /* 1 wait states at max frequency 36 MHz and 1.2V */ { CMU_MAX_FREQ_2WS_1V2, 0, 2 }, /* 2 wait states at max frequency 54 MHz and 1.2V */ { CMU_MAX_FREQ_3WS_1V2, 0, 3 }, /* 3 wait states at max frequency 72 MHz and 1.2V */ { CMU_MAX_FREQ_0WS_1V0, 2, 0 }, /* 0 wait states at max frequency 7 MHz and 1.0V */ { CMU_MAX_FREQ_1WS_1V0, 2, 1 }, /* 1 wait states at max frequency 14 MHz and 1.0V */ { CMU_MAX_FREQ_2WS_1V0, 2, 2 }, /* 2 wait states at max frequency 21 MHz and 1.0V */ #else { CMU_MAX_FREQ_0WS_1V2, 0, 0 }, /* 0 wait states at 1.2V */ { CMU_MAX_FREQ_1WS_1V2, 0, 1 }, /* 1 wait states at 1.2V */ { CMU_MAX_FREQ_0WS_1V0, 2, 0 }, /* 0 wait states at 1.0V */ { CMU_MAX_FREQ_1WS_1V0, 2, 1 }, /* 1 wait states at 1.0V */ { CMU_MAX_FREQ_2WS_1V0, 2, 2 }, /* 2 wait states at 1.0V */ #endif }; #define FLASH_WS_TABLE_ENTRIES (sizeof(flashWsTable) / sizeof(flashWsTable[0])) #endif #if defined(_CMU_USHFRCOCTRL_FREQRANGE_MASK) \ || defined(_CMU_USHFRCOTUNE_MASK) #ifndef EFM32_USHFRCO_STARTUP_FREQ #define EFM32_USHFRCO_STARTUP_FREQ (48000000UL) #endif static uint32_t ushfrcoFreq = EFM32_USHFRCO_STARTUP_FREQ; #endif /******************************************************************************* ************************** LOCAL PROTOTYPES ******************************* ******************************************************************************/ #if defined(_CMU_HFRCOCTRL_FREQRANGE_MASK) static uint32_t CMU_HFRCODevinfoGet(CMU_HFRCOFreq_TypeDef freq); #endif #if defined(_CMU_USHFRCOCTRL_FREQRANGE_MASK) static uint32_t CMU_USHFRCODevinfoGet(CMU_USHFRCOFreq_TypeDef freq); #endif static void hfperClkSafePrescaler(void); static void hfperClkOptimizedPrescaler(void); /** @endcond */ /******************************************************************************* ************************** LOCAL FUNCTIONS ******************************** ******************************************************************************/ /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ #if defined(_SILICON_LABS_32B_SERIES_0) \ && (defined(_EFM32_GIANT_FAMILY) \ || defined(_EZR32_LEOPARD_FAMILY)) /***************************************************************************//** * @brief * Return maximum allowed frequency for low energy peripherals. ******************************************************************************/ static uint32_t maxFreqHfle(void) { uint16_t majorMinorRev; switch (SYSTEM_GetFamily()) { case systemPartFamilyEfm32Leopard: case systemPartFamilyEzr32Leopard: /* CHIP MAJOR bit [5:0] */ majorMinorRev = (((ROMTABLE->PID0 & _ROMTABLE_PID0_REVMAJOR_MASK) >> _ROMTABLE_PID0_REVMAJOR_SHIFT) << 8); /* CHIP MINOR bit [7:4] */ majorMinorRev |= (((ROMTABLE->PID2 & _ROMTABLE_PID2_REVMINORMSB_MASK) >> _ROMTABLE_PID2_REVMINORMSB_SHIFT) << 4); /* CHIP MINOR bit [3:0] */ majorMinorRev |= ((ROMTABLE->PID3 & _ROMTABLE_PID3_REVMINORLSB_MASK) >> _ROMTABLE_PID3_REVMINORLSB_SHIFT); if (majorMinorRev >= 0x0204) { return 24000000; } else { return 32000000; } case systemPartFamilyEfm32Giant: return 32000000; default: /* Invalid device family. */ EFM_ASSERT(false); return 0; } } #endif #if defined(CMU_MAX_FREQ_HFLE) /* Unified definitions for the HFLE wait-state and prescaler fields. */ #if defined(CMU_CTRL_HFLE) #define _GENERIC_HFLE_WS_MASK _CMU_CTRL_HFLE_MASK #define _GENERIC_HFLE_WS_SHIFT _CMU_CTRL_HFLE_SHIFT #define GENERIC_HFLE_PRESC_REG CMU->HFCORECLKDIV #define _GENERIC_HFLE_PRESC_MASK _CMU_HFCORECLKDIV_HFCORECLKLEDIV_MASK #define _GENERIC_HFLE_PRESC_SHIFT _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT #elif defined(CMU_CTRL_WSHFLE) #define _GENERIC_HFLE_WS_MASK _CMU_CTRL_WSHFLE_MASK #define _GENERIC_HFLE_WS_SHIFT _CMU_CTRL_WSHFLE_SHIFT #define GENERIC_HFLE_PRESC_REG CMU->HFPRESC #define _GENERIC_HFLE_PRESC_MASK _CMU_HFPRESC_HFCLKLEPRESC_MASK #define _GENERIC_HFLE_PRESC_SHIFT _CMU_HFPRESC_HFCLKLEPRESC_SHIFT #endif /***************************************************************************//** * @brief * Set HFLE wait-states and HFCLKLE prescaler. * * @param[in] maxLeFreq * The maximum LE frequency. ******************************************************************************/ static void setHfLeConfig(uint32_t hfFreq) { unsigned int hfleWs; uint32_t hflePresc; /* Check for 1 bit fields. @ref BUS_RegBitWrite() below are going to fail if the fields are changed to more than 1 bit. */ EFM_ASSERT((_GENERIC_HFLE_WS_MASK >> _GENERIC_HFLE_WS_SHIFT) == 0x1U); /* - Enable HFLE wait-state to allow access to LE peripherals when HFBUSCLK is above maxLeFreq. - Set HFLE prescaler. Allowed HFLE clock frequency is maxLeFreq. */ hfleWs = 1; if (hfFreq <= CMU_MAX_FREQ_HFLE) { hfleWs = 0; hflePresc = 0; } else if (hfFreq <= (2UL * CMU_MAX_FREQ_HFLE)) { hflePresc = 1; } else { hflePresc = 2; } BUS_RegBitWrite(&CMU->CTRL, _GENERIC_HFLE_WS_SHIFT, hfleWs); GENERIC_HFLE_PRESC_REG = (GENERIC_HFLE_PRESC_REG & ~_GENERIC_HFLE_PRESC_MASK) | (hflePresc << _GENERIC_HFLE_PRESC_SHIFT); } #if defined(_CMU_CTRL_HFLE_MASK) /***************************************************************************//** * @brief * Get HFLE wait-state configuration. * * @return * The current wait-state configuration. ******************************************************************************/ static uint32_t getHfLeConfig(void) { uint32_t ws = BUS_RegBitRead(&CMU->CTRL, _GENERIC_HFLE_WS_SHIFT); return ws; } #endif #endif /***************************************************************************//** * @brief * Get the AUX clock frequency. Used by MSC flash programming and LESENSE, * by default also as a debug clock. * * @return * AUX Frequency in Hz. ******************************************************************************/ static uint32_t auxClkGet(void) { uint32_t ret; #if defined(_CMU_AUXHFRCOCTRL_FREQRANGE_MASK) ret = (uint32_t)auxHfrcoFreq; #elif defined(_CMU_AUXHFRCOCTRL_BAND_MASK) /* All series 0 families except EFM32G */ switch (CMU->AUXHFRCOCTRL & _CMU_AUXHFRCOCTRL_BAND_MASK) { case CMU_AUXHFRCOCTRL_BAND_1MHZ: if ( SYSTEM_GetProdRev() >= 19 ) { ret = 1200000; } else { ret = 1000000; } break; case CMU_AUXHFRCOCTRL_BAND_7MHZ: if ( SYSTEM_GetProdRev() >= 19 ) { ret = 6600000; } else { ret = 7000000; } break; case CMU_AUXHFRCOCTRL_BAND_11MHZ: ret = 11000000; break; case CMU_AUXHFRCOCTRL_BAND_14MHZ: ret = 14000000; break; case CMU_AUXHFRCOCTRL_BAND_21MHZ: ret = 21000000; break; #if defined(_CMU_AUXHFRCOCTRL_BAND_28MHZ) case CMU_AUXHFRCOCTRL_BAND_28MHZ: ret = 28000000; break; #endif default: ret = 0; EFM_ASSERT(false); break; } #else /* Gecko has a fixed 14 MHz AUXHFRCO clock. */ ret = 14000000; #endif return ret; } #if defined (_CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK) \ || defined (_CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK) /***************************************************************************//** * @brief * Get the HFSRCCLK frequency. * * @return * HFSRCCLK Frequency in Hz. ******************************************************************************/ static uint32_t hfSrcClkGet(void) { uint32_t ret; ret = SystemHFClockGet(); return ret * (1U + ((CMU->HFPRESC & _CMU_HFPRESC_PRESC_MASK) >> _CMU_HFPRESC_PRESC_SHIFT)); } #endif /***************************************************************************//** * @brief * Get the Debug Trace clock frequency. * * @return * Debug Trace frequency in Hz. ******************************************************************************/ static uint32_t dbgClkGet(void) { uint32_t ret; CMU_Select_TypeDef clk; /* Get selected clock source */ clk = CMU_ClockSelectGet(cmuClock_DBG); switch (clk) { case cmuSelect_HFCLK: ret = SystemHFClockGet(); break; case cmuSelect_AUXHFRCO: ret = auxClkGet(); break; default: ret = 0; EFM_ASSERT(false); break; } return ret; } #if defined(_CMU_ADCCTRL_ADC0CLKSEL_MASK) /***************************************************************************//** * @brief * Get the ADC n asynchronous clock frequency. * * @return * ADC n asynchronous frequency in Hz. ******************************************************************************/ static uint32_t adcAsyncClkGet(uint32_t adc) { uint32_t ret; CMU_Select_TypeDef clk; /* Get the selected clock source. */ switch (adc) { case 0: clk = CMU_ClockSelectGet(cmuClock_ADC0ASYNC); break; #if defined(_CMU_ADCCTRL_ADC1CLKSEL_MASK) case 1: clk = CMU_ClockSelectGet(cmuClock_ADC1ASYNC); break; #endif default: EFM_ASSERT(false); return 0; } switch (clk) { case cmuSelect_Disabled: ret = 0; break; case cmuSelect_AUXHFRCO: ret = auxClkGet(); break; case cmuSelect_HFXO: ret = SystemHFXOClockGet(); break; case cmuSelect_HFSRCCLK: ret = hfSrcClkGet(); break; default: ret = 0; EFM_ASSERT(false); break; } return ret; } #endif #if defined(_CMU_SDIOCTRL_MASK) /***************************************************************************//** * @brief * Get the SDIO reference clock frequency. * * @return * SDIO reference clock frequency in Hz. ******************************************************************************/ static uint32_t sdioRefClkGet(void) { uint32_t ret; CMU_Select_TypeDef clk; /* Get the selected clock source. */ clk = CMU_ClockSelectGet(cmuClock_SDIOREF); switch (clk) { case cmuSelect_HFRCO: ret = SystemHfrcoFreq; break; case cmuSelect_HFXO: ret = SystemHFXOClockGet(); break; case cmuSelect_AUXHFRCO: ret = auxClkGet(); break; case cmuSelect_USHFRCO: ret = ushfrcoFreq; break; default: ret = 0; EFM_ASSERT(false); break; } return ret; } #endif #if defined(_CMU_QSPICTRL_MASK) /***************************************************************************//** * @brief * Get the QSPI n reference clock frequency. * * @return * QSPI n reference clock frequency in Hz. ******************************************************************************/ static uint32_t qspiRefClkGet(uint32_t qspi) { uint32_t ret; CMU_Select_TypeDef clk; /* Get the selected clock source. */ switch (qspi) { case 0: clk = CMU_ClockSelectGet(cmuClock_QSPI0REF); break; default: EFM_ASSERT(false); return 0; } switch (clk) { case cmuSelect_HFRCO: ret = SystemHfrcoFreq; break; case cmuSelect_HFXO: ret = SystemHFXOClockGet(); break; case cmuSelect_AUXHFRCO: ret = auxClkGet(); break; case cmuSelect_USHFRCO: ret = ushfrcoFreq; break; default: ret = 0; EFM_ASSERT(false); break; } return ret; } #endif #if defined(_CMU_PDMCTRL_MASK) /***************************************************************************//** * @brief * Get the PDM reference clock frequency. * * @return * PDM reference clock frequency in Hz. ******************************************************************************/ static uint32_t pdmRefClkGet(void) { uint32_t ret; CMU_Select_TypeDef clk; /* Get the selected clock source. */ clk = CMU_ClockSelectGet(cmuClock_PDMREF); switch (clk) { case cmuSelect_HFRCO: ret = SystemHfrcoFreq; break; case cmuSelect_HFXO: ret = SystemHFXOClockGet(); break; case cmuSelect_USHFRCO: ret = ushfrcoFreq; break; default: ret = 0; EFM_ASSERT(false); break; } return ret; } #endif #if defined(USBR_CLOCK_PRESENT) /***************************************************************************//** * @brief * Get the USB rate clock frequency. * * @return * USB rate clock frequency in Hz. ******************************************************************************/ static uint32_t usbRateClkGet(void) { uint32_t ret; CMU_Select_TypeDef clk; clk = CMU_ClockSelectGet(cmuClock_USBR); switch (clk) { case cmuSelect_USHFRCO: ret = ushfrcoFreq; break; case cmuSelect_HFXO: ret = SystemHFXOClockGet(); break; case cmuSelect_HFXOX2: ret = 2u * SystemHFXOClockGet(); break; case cmuSelect_HFRCO: ret = SystemHfrcoFreq; break; case cmuSelect_LFXO: ret = SystemLFXOClockGet(); break; case cmuSelect_LFRCO: ret = SystemLFRCOClockGet(); break; default: ret = 0; EFM_ASSERT(false); break; } return ret; } #endif /***************************************************************************//** * @brief * Configure flash access wait states to support the given core clock * frequency. * * @param[in] coreFreq * The core clock frequency to configure flash wait-states. * * @param[in] vscale * Voltage Scale level. Supported levels are 0 and 2 where 0 is the default. ******************************************************************************/ static void flashWaitStateControl(uint32_t coreFreq, int vscale) { uint32_t mode; #if defined(MSC_READCTRL_MODE_WS0SCBTP) bool scbtpEn; /* Suppressed Conditional Branch Target Prefetch setting. */ #endif (void) vscale; /* vscale parameter is only used on some devices. */ /* Get mode and SCBTP enable. */ mode = MSC->READCTRL & _MSC_READCTRL_MODE_MASK; #if defined(_SILICON_LABS_32B_SERIES_0) #if defined(MSC_READCTRL_MODE_WS0SCBTP) /* Devices with MODE and SCBTP in the same register field. */ switch (mode) { case MSC_READCTRL_MODE_WS0: case MSC_READCTRL_MODE_WS1: #if defined(MSC_READCTRL_MODE_WS2) case MSC_READCTRL_MODE_WS2: #endif scbtpEn = false; break; default: /* WSxSCBTP */ scbtpEn = true; break; } /* Set mode based on the core clock frequency and SCBTP enable. */ if (false) { } #if defined(MSC_READCTRL_MODE_WS2) else if (coreFreq > CMU_MAX_FREQ_1WS) { mode = (scbtpEn ? MSC_READCTRL_MODE_WS2SCBTP : MSC_READCTRL_MODE_WS2); } #endif else if ((coreFreq <= CMU_MAX_FREQ_1WS) && (coreFreq > CMU_MAX_FREQ_0WS)) { mode = (scbtpEn ? MSC_READCTRL_MODE_WS1SCBTP : MSC_READCTRL_MODE_WS1); } else { mode = (scbtpEn ? MSC_READCTRL_MODE_WS0SCBTP : MSC_READCTRL_MODE_WS0); } #else /* defined(MSC_READCTRL_MODE_WS0SCBTP) */ if (coreFreq <= CMU_MAX_FREQ_0WS) { mode = 0; } else if (coreFreq <= CMU_MAX_FREQ_1WS) { mode = 1; } #endif /* defined(MSC_READCTRL_MODE_WS0SCBTP) */ // End defined(_SILICON_LABS_32B_SERIES_0) #elif defined(_SILICON_LABS_32B_SERIES_1) #if defined(_EMU_STATUS_VSCALE_MASK) /* These devices have specific requirements on the supported flash wait state * depending on the frequency and voltage scale level. */ uint32_t i; for (i = 0; i < FLASH_WS_TABLE_ENTRIES; i++) { if ((flashWsTable[i].vscale == (uint8_t)vscale) && (coreFreq <= flashWsTable[i].maxFreq)) { break; // Found a matching entry. } } if (i == FLASH_WS_TABLE_ENTRIES) { mode = 3; // Worst case flash wait state for unsupported cases. EFM_ASSERT(false); } else { mode = flashWsTable[i].ws; } mode = mode << _MSC_READCTRL_MODE_SHIFT; #else /* Devices where MODE and SCBTP are in separate fields and where the device * either does not support voltage scale or where the voltage scale does * not impact the flash wait state configuration. */ if (coreFreq <= CMU_MAX_FREQ_0WS_1V2) { mode = 0; } else if (coreFreq <= CMU_MAX_FREQ_1WS_1V2) { mode = 1; } #if defined(MSC_READCTRL_MODE_WS2) else if (coreFreq <= CMU_MAX_FREQ_2WS) { mode = 2; } #endif #if defined(MSC_READCTRL_MODE_WS3) else if (coreFreq <= CMU_MAX_FREQ_3WS) { mode = 3; } #endif mode = mode << _MSC_READCTRL_MODE_SHIFT; #endif // End defined(_SILICON_LABS_32B_SERIES_1) #else #error "Undefined 32B SERIES!" #endif /* BUS_RegMaskedWrite cannot be used as it would temporarily set the mode field to WS0. */ MSC->READCTRL = (MSC->READCTRL & ~_MSC_READCTRL_MODE_MASK) | mode; } /***************************************************************************//** * @brief * Configure flash access wait states to the most conservative setting for * this target. Retain SCBTP (Suppressed Conditional Branch Target Prefetch) * setting. ******************************************************************************/ static void flashWaitStateMax(void) { /* Make sure the MSC is unlocked */ bool mscLocked = MSC->LOCK != 0UL; MSC->LOCK = MSC_UNLOCK_CODE; flashWaitStateControl(SystemMaxCoreClockGet(), 0); if (mscLocked) { MSC->LOCK = 0; } } #if defined(_MSC_RAMCTRL_RAMWSEN_MASK) /***************************************************************************//** * @brief * Configure RAM access wait states to support the given core clock * frequency. * * @param[in] coreFreq * The core clock frequency to configure RAM wait-states. * * @param[in] vscale * A voltage scale level. Supported levels are 0 and 2 where 0 is the default. ******************************************************************************/ static void setRamWaitState(uint32_t coreFreq, int vscale) { uint32_t limit = 38000000; if (vscale == 2) { limit = 16000000; } if (coreFreq > limit) { BUS_RegMaskedSet(&MSC->RAMCTRL, (MSC_RAMCTRL_RAMWSEN | MSC_RAMCTRL_RAM1WSEN | MSC_RAMCTRL_RAM2WSEN)); } else { BUS_RegMaskedClear(&MSC->RAMCTRL, (MSC_RAMCTRL_RAMWSEN | MSC_RAMCTRL_RAM1WSEN | MSC_RAMCTRL_RAM2WSEN)); } } #endif #if defined(_MSC_CTRL_WAITMODE_MASK) /***************************************************************************//** * @brief * Configure the wait state for peripheral accesses over the bus to support * the given bus clock frequency. * * @param[in] busFreq * A peripheral bus clock frequency to configure wait-states. * * @param[in] vscale * The voltage scale to configure wait-states. Expected values are * 0 or 2. * * @li 0 = 1.2 V (VSCALE2) * @li 2 = 1.0 V (VSCALE0) * ******************************************************************************/ static void setBusWaitState(uint32_t busFreq, int vscale) { if ((busFreq > 50000000) && (vscale == 0)) { BUS_RegMaskedSet(&MSC->CTRL, MSC_CTRL_WAITMODE_WS1); } else { BUS_RegMaskedClear(&MSC->CTRL, MSC_CTRL_WAITMODE_WS1); } } #endif /***************************************************************************//** * @brief * Configure various wait states to switch to a certain frequency * and a certain voltage scale. * * @details * This function will set up the necessary flash, bus, and RAM wait states. * Updating the wait state configuration must be done before * increasing the clock frequency and it must be done after decreasing the * clock frequency. Updating the wait state configuration must be done before * core voltage is decreased and it must be done after a core voltage is * increased. * * @param[in] coreFreq * The core clock frequency to configure wait-states. * * @param[in] vscale * The voltage scale to configure wait-states. Expected values are * 0 or 2, higher number is lower voltage. * * @li 0 = 1.2 V (VSCALE2) * @li 2 = 1.0 V (VSCALE0) * ******************************************************************************/ void CMU_UpdateWaitStates(uint32_t freq, int vscale) { /* Make sure the MSC is unlocked */ bool mscLocked = MSC->LOCK != 0UL; MSC->LOCK = MSC_UNLOCK_CODE; flashWaitStateControl(freq, vscale); #if defined(_MSC_RAMCTRL_RAMWSEN_MASK) setRamWaitState(freq, vscale); #endif #if defined(_MSC_CTRL_WAITMODE_MASK) setBusWaitState(freq, vscale); #endif if (mscLocked) { MSC->LOCK = 0; } } #if defined(_CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_MASK) /***************************************************************************//** * @brief * Return the upper value for CMU_HFXOSTEADYSTATECTRL_REGISH. ******************************************************************************/ static uint32_t getRegIshUpperVal(uint32_t steadyStateRegIsh) { uint32_t regIshUpper; const uint32_t upperMax = _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_MASK >> _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_SHIFT; /* Add 3 as specified in the register description for CMU_HFXOSTEADYSTATECTRL_REGISHUPPER. */ regIshUpper = SL_MIN(steadyStateRegIsh + 3UL, upperMax); regIshUpper <<= _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_SHIFT; return regIshUpper; } #endif #if defined(_CMU_HFXOCTRL_MASK) /***************************************************************************//** * @brief * Get the HFXO tuning mode. * * @return * The current HFXO tuning mode from the HFXOCTRL register. ******************************************************************************/ __STATIC_INLINE uint32_t getHfxoTuningMode(void) { #if defined(_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK) return (CMU->HFXOCTRL & _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK) >> _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_SHIFT; #else return (CMU->HFXOCTRL & _CMU_HFXOCTRL_PEAKDETMODE_MASK) >> _CMU_HFXOCTRL_PEAKDETMODE_SHIFT; #endif } /***************************************************************************//** * @brief * Set the HFXO tuning mode. * * @param[in] mode * The new HFXO tuning mode. This can be HFXO_TUNING_MODE_AUTO or * HFXO_TUNING_MODE_CMD. ******************************************************************************/ __STATIC_INLINE void setHfxoTuningMode(uint32_t mode) { #if defined(_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK) CMU->HFXOCTRL = (CMU->HFXOCTRL & ~_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK) | (mode << _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_SHIFT); #else CMU->HFXOCTRL = (CMU->HFXOCTRL & ~_CMU_HFXOCTRL_PEAKDETMODE_MASK) | (mode << _CMU_HFXOCTRL_PEAKDETMODE_SHIFT); #endif } #endif /***************************************************************************//** * @brief * Get the LFnCLK frequency based on the current configuration. * * @param[in] lfClkBranch * Selected LF branch. * * @return * The LFnCLK frequency in Hz. If no LFnCLK is selected (disabled), 0 is * returned. ******************************************************************************/ static uint32_t lfClkGet(CMU_Clock_TypeDef lfClkBranch) { uint32_t sel; uint32_t ret = 0; switch (lfClkBranch) { case cmuClock_LFA: case cmuClock_LFB: #if defined(_CMU_LFCCLKEN0_MASK) case cmuClock_LFC: #endif #if defined(_CMU_LFECLKSEL_MASK) case cmuClock_LFE: #endif break; default: EFM_ASSERT(false); break; } sel = (uint32_t)CMU_ClockSelectGet(lfClkBranch); /* Get clock select field */ switch (lfClkBranch) { case cmuClock_LFA: #if defined(_CMU_LFCLKSEL_MASK) sel = (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFA_MASK) >> _CMU_LFCLKSEL_LFA_SHIFT; #elif defined(_CMU_LFACLKSEL_MASK) sel = (CMU->LFACLKSEL & _CMU_LFACLKSEL_LFA_MASK) >> _CMU_LFACLKSEL_LFA_SHIFT; #else EFM_ASSERT(false); #endif break; case cmuClock_LFB: #if defined(_CMU_LFCLKSEL_MASK) sel = (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFB_MASK) >> _CMU_LFCLKSEL_LFB_SHIFT; #elif defined(_CMU_LFBCLKSEL_MASK) sel = (CMU->LFBCLKSEL & _CMU_LFBCLKSEL_LFB_MASK) >> _CMU_LFBCLKSEL_LFB_SHIFT; #else EFM_ASSERT(false); #endif break; #if defined(_CMU_LFCCLKEN0_MASK) case cmuClock_LFC: #if defined(_CMU_LFCLKSEL_LFC_MASK) sel = (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFC_MASK) >> _CMU_LFCLKSEL_LFC_SHIFT; #elif defined(_CMU_LFCCLKSEL_LFC_MASK) sel = (CMU->LFCCLKSEL & _CMU_LFCCLKSEL_LFC_MASK) >> _CMU_LFCCLKSEL_LFC_SHIFT; #else EFM_ASSERT(false); #endif break; #endif #if defined(_CMU_LFECLKSEL_MASK) case cmuClock_LFE: sel = (CMU->LFECLKSEL & _CMU_LFECLKSEL_LFE_MASK) >> _CMU_LFECLKSEL_LFE_SHIFT; break; #endif default: EFM_ASSERT(false); break; } /* Get the clock frequency. */ #if defined(_CMU_LFCLKSEL_MASK) switch (sel) { case _CMU_LFCLKSEL_LFA_LFRCO: ret = SystemLFRCOClockGet(); break; case _CMU_LFCLKSEL_LFA_LFXO: ret = SystemLFXOClockGet(); break; #if defined(_CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2) case _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2: #if defined(CMU_MAX_FREQ_HFLE) /* HFLE bit is or'ed by hardware with HFCORECLKLEDIV to reduce the * frequency of CMU_HFCORECLKLEDIV2. */ ret = SystemCoreClockGet() / (1U << (getHfLeConfig() + 1)); #else ret = SystemCoreClockGet() / 2U; #endif break; #endif case _CMU_LFCLKSEL_LFA_DISABLED: ret = 0; #if defined(CMU_LFCLKSEL_LFAE) /* Check LF Extended bit setting for LFA or LFB ULFRCO clock. */ if ((lfClkBranch == cmuClock_LFA) || (lfClkBranch == cmuClock_LFB)) { if (CMU->LFCLKSEL >> (lfClkBranch == cmuClock_LFA ? _CMU_LFCLKSEL_LFAE_SHIFT : _CMU_LFCLKSEL_LFBE_SHIFT)) { ret = SystemULFRCOClockGet(); } } #endif break; default: ret = 0U; EFM_ASSERT(false); break; } #endif /* _CMU_LFCLKSEL_MASK */ #if defined(_CMU_LFACLKSEL_MASK) switch (sel) { case _CMU_LFACLKSEL_LFA_LFRCO: ret = SystemLFRCOClockGet(); break; case _CMU_LFACLKSEL_LFA_LFXO: ret = SystemLFXOClockGet(); break; case _CMU_LFACLKSEL_LFA_ULFRCO: ret = SystemULFRCOClockGet(); break; #if defined(_CMU_LFACLKSEL_LFA_HFCLKLE) case _CMU_LFACLKSEL_LFA_HFCLKLE: ret = SystemCoreClockGet() / CMU_Log2ToDiv(((CMU->HFPRESC & _CMU_HFPRESC_HFCLKLEPRESC_MASK) >> _CMU_HFPRESC_HFCLKLEPRESC_SHIFT) + 1); break; #elif defined(_CMU_LFBCLKSEL_LFB_HFCLKLE) case _CMU_LFBCLKSEL_LFB_HFCLKLE: ret = SystemCoreClockGet() / CMU_Log2ToDiv(((CMU->HFPRESC & _CMU_HFPRESC_HFCLKLEPRESC_MASK) >> _CMU_HFPRESC_HFCLKLEPRESC_SHIFT) + 1UL); break; #endif case _CMU_LFACLKSEL_LFA_DISABLED: ret = 0; break; default: ret = 0U; EFM_ASSERT(false); break; } #endif return ret; } /***************************************************************************//** * @brief * Wait for an ongoing sync of register(s) to low-frequency domain to complete. * * @param[in] mask * A bitmask corresponding to SYNCBUSY register defined bits, indicating * registers that must complete any ongoing synchronization. ******************************************************************************/ __STATIC_INLINE void syncReg(uint32_t mask) { /* Avoid a deadlock if modifying the same register twice when freeze mode is */ /* activated. */ if ((CMU->FREEZE & CMU_FREEZE_REGFREEZE) != 0UL) { return; } /* Wait for any pending previous write operation to complete */ /* in low-frequency domain. */ while ((CMU->SYNCBUSY & mask) != 0UL) { } } #if defined(USBC_CLOCK_PRESENT) /***************************************************************************//** * @brief * Get the USBC frequency. * * @return * USBC frequency in Hz. ******************************************************************************/ static uint32_t usbCClkGet(void) { uint32_t ret; CMU_Select_TypeDef clk; /* Get the selected clock source. */ clk = CMU_ClockSelectGet(cmuClock_USBC); switch (clk) { case cmuSelect_LFXO: ret = SystemLFXOClockGet(); break; case cmuSelect_LFRCO: ret = SystemLFRCOClockGet(); break; #if defined (_CMU_USHFRCOCTRL_MASK) case cmuSelect_USHFRCO: ret = ushfrcoFreq; break; #endif case cmuSelect_HFCLK: ret = SystemHFClockGet(); break; default: /* Clock is not enabled */ ret = 0; break; } return ret; } #endif /***************************************************************************//** * @brief * Set HFPER clock tree prescalers to safe values. * * @note * This function applies to EFM32GG11B. There are 3 HFPER clock trees with * these frequency limits: * HFPERCLK (A-tree): 20MHz in VSCALE0 mode, 50MHz in VSCALE2 mode. * HFPERBCLK (B-tree): 20MHz in VSCALE0 mode, 72MHz in VSCALE2 mode. * HFPERCCLK (C-tree): 20MHz in VSCALE0 mode, 50MHz in VSCALE2 mode. ******************************************************************************/ static void hfperClkSafePrescaler(void) { #if defined(_CMU_HFPERPRESC_MASK) && defined(_CMU_HFPERPRESCB_MASK) \ && defined(_CMU_HFPERPRESCC_MASK) // Assuming a max. HFCLK of 72MHz, we need to set prescalers to DIV4. CMU_ClockPrescSet(cmuClock_HFPER, 3U); CMU_ClockPrescSet(cmuClock_HFPERB, 3U); CMU_ClockPrescSet(cmuClock_HFPERC, 3U); #endif } /***************************************************************************//** * @brief * Set HFPER clock tree prescalers to give highest possible clock node * frequency while still beeing within spec. * * @note * This function applies to EFM32GG11B. There are 3 HFPER clock trees with * these frequency limits: * HFPERCLK (A-tree): 20MHz in VSCALE0 mode, 50MHz in VSCALE2 mode. * HFPERBCLK (B-tree): 20MHz in VSCALE0 mode, 72MHz in VSCALE2 mode. * HFPERCCLK (C-tree): 20MHz in VSCALE0 mode, 50MHz in VSCALE2 mode. ******************************************************************************/ static void hfperClkOptimizedPrescaler(void) { #if defined(_CMU_HFPERPRESC_MASK) && defined(_CMU_HFPERPRESCB_MASK) \ && defined(_CMU_HFPERPRESCC_MASK) uint32_t hfClkFreq, divisor; hfClkFreq = SystemHFClockGet(); if ( EMU_VScaleGet() == emuVScaleEM01_LowPower) { divisor = (hfClkFreq + 20000000U - 1U) / 20000000U; // ceil(x) if (divisor > 0U) { divisor--; // Convert to prescaler } CMU_ClockPrescSet(cmuClock_HFPER, divisor); CMU_ClockPrescSet(cmuClock_HFPERB, divisor); CMU_ClockPrescSet(cmuClock_HFPERC, divisor); } else { divisor = (hfClkFreq + 50000000U - 1U) / 50000000U; if (divisor > 0U) { divisor--; } CMU_ClockPrescSet(cmuClock_HFPER, divisor); CMU_ClockPrescSet(cmuClock_HFPERC, divisor); divisor = (hfClkFreq + 72000000U - 1U) / 72000000U; if (divisor > 0U) { divisor--; } CMU_ClockPrescSet(cmuClock_HFPERB, divisor); } #endif } /** @endcond */ /******************************************************************************* ************************** GLOBAL FUNCTIONS ******************************* ******************************************************************************/ #if defined(_CMU_AUXHFRCOCTRL_BAND_MASK) /***************************************************************************//** * @brief * Get the AUXHFRCO band in use. * * @return * AUXHFRCO band in use. ******************************************************************************/ CMU_AUXHFRCOBand_TypeDef CMU_AUXHFRCOBandGet(void) { return (CMU_AUXHFRCOBand_TypeDef)((CMU->AUXHFRCOCTRL & _CMU_AUXHFRCOCTRL_BAND_MASK) >> _CMU_AUXHFRCOCTRL_BAND_SHIFT); } #endif /* _CMU_AUXHFRCOCTRL_BAND_MASK */ #if defined(_CMU_AUXHFRCOCTRL_BAND_MASK) /***************************************************************************//** * @brief * Set the AUXHFRCO band and the tuning value based on the value in the * calibration table made during production. * * @param[in] band * AUXHFRCO band to activate. ******************************************************************************/ void CMU_AUXHFRCOBandSet(CMU_AUXHFRCOBand_TypeDef band) { uint32_t tuning; /* Read a tuning value from the calibration table. */ switch (band) { case cmuAUXHFRCOBand_1MHz: tuning = (DEVINFO->AUXHFRCOCAL0 & _DEVINFO_AUXHFRCOCAL0_BAND1_MASK) >> _DEVINFO_AUXHFRCOCAL0_BAND1_SHIFT; break; case cmuAUXHFRCOBand_7MHz: tuning = (DEVINFO->AUXHFRCOCAL0 & _DEVINFO_AUXHFRCOCAL0_BAND7_MASK) >> _DEVINFO_AUXHFRCOCAL0_BAND7_SHIFT; break; case cmuAUXHFRCOBand_11MHz: tuning = (DEVINFO->AUXHFRCOCAL0 & _DEVINFO_AUXHFRCOCAL0_BAND11_MASK) >> _DEVINFO_AUXHFRCOCAL0_BAND11_SHIFT; break; case cmuAUXHFRCOBand_14MHz: tuning = (DEVINFO->AUXHFRCOCAL0 & _DEVINFO_AUXHFRCOCAL0_BAND14_MASK) >> _DEVINFO_AUXHFRCOCAL0_BAND14_SHIFT; break; case cmuAUXHFRCOBand_21MHz: tuning = (DEVINFO->AUXHFRCOCAL1 & _DEVINFO_AUXHFRCOCAL1_BAND21_MASK) >> _DEVINFO_AUXHFRCOCAL1_BAND21_SHIFT; break; #if defined(_CMU_AUXHFRCOCTRL_BAND_28MHZ) case cmuAUXHFRCOBand_28MHz: tuning = (DEVINFO->AUXHFRCOCAL1 & _DEVINFO_AUXHFRCOCAL1_BAND28_MASK) >> _DEVINFO_AUXHFRCOCAL1_BAND28_SHIFT; break; #endif default: EFM_ASSERT(false); return; } /* Set band/tuning. */ CMU->AUXHFRCOCTRL = (CMU->AUXHFRCOCTRL & ~(_CMU_AUXHFRCOCTRL_BAND_MASK | _CMU_AUXHFRCOCTRL_TUNING_MASK)) | (band << _CMU_AUXHFRCOCTRL_BAND_SHIFT) | (tuning << _CMU_AUXHFRCOCTRL_TUNING_SHIFT); } #endif /* _CMU_AUXHFRCOCTRL_BAND_MASK */ #if defined(_CMU_AUXHFRCOCTRL_FREQRANGE_MASK) /**************************************************************************//** * @brief * Get the AUXHFRCO frequency calibration word in DEVINFO. * * @param[in] freq * Frequency in Hz. * * @return * AUXHFRCO calibration word for a given frequency. *****************************************************************************/ static uint32_t CMU_AUXHFRCODevinfoGet(CMU_AUXHFRCOFreq_TypeDef freq) { switch (freq) { /* 1, 2, and 4 MHz share the same calibration word. */ case cmuAUXHFRCOFreq_1M0Hz: case cmuAUXHFRCOFreq_2M0Hz: case cmuAUXHFRCOFreq_4M0Hz: return DEVINFO->AUXHFRCOCAL0; case cmuAUXHFRCOFreq_7M0Hz: return DEVINFO->AUXHFRCOCAL3; case cmuAUXHFRCOFreq_13M0Hz: return DEVINFO->AUXHFRCOCAL6; case cmuAUXHFRCOFreq_16M0Hz: return DEVINFO->AUXHFRCOCAL7; case cmuAUXHFRCOFreq_19M0Hz: return DEVINFO->AUXHFRCOCAL8; case cmuAUXHFRCOFreq_26M0Hz: return DEVINFO->AUXHFRCOCAL10; case cmuAUXHFRCOFreq_32M0Hz: return DEVINFO->AUXHFRCOCAL11; case cmuAUXHFRCOFreq_38M0Hz: return DEVINFO->AUXHFRCOCAL12; #if defined(_DEVINFO_AUXHFRCOCAL13_MASK) case cmuAUXHFRCOFreq_48M0Hz: return DEVINFO->AUXHFRCOCAL13; #endif #if defined(_DEVINFO_AUXHFRCOCAL14_MASK) case cmuAUXHFRCOFreq_50M0Hz: return DEVINFO->AUXHFRCOCAL14; #endif default: /* cmuAUXHFRCOFreq_UserDefined */ return 0; } } #endif /* _CMU_AUXHFRCOCTRL_FREQRANGE_MASK */ #if defined(_CMU_AUXHFRCOCTRL_FREQRANGE_MASK) /***************************************************************************//** * @brief * Get the current AUXHFRCO frequency. * * @return * AUXHFRCO frequency. ******************************************************************************/ CMU_AUXHFRCOFreq_TypeDef CMU_AUXHFRCOBandGet(void) { return auxHfrcoFreq; } #endif /* _CMU_AUXHFRCOCTRL_FREQRANGE_MASK */ #if defined(_CMU_AUXHFRCOCTRL_FREQRANGE_MASK) /***************************************************************************//** * @brief * Set AUXHFRCO calibration for the selected target frequency. * * @param[in] setFreq * AUXHFRCO frequency to set ******************************************************************************/ void CMU_AUXHFRCOBandSet(CMU_AUXHFRCOFreq_TypeDef setFreq) { uint32_t freqCal; /* Get DEVINFO index and set global auxHfrcoFreq. */ freqCal = CMU_AUXHFRCODevinfoGet(setFreq); EFM_ASSERT((freqCal != 0UL) && (freqCal != UINT_MAX)); auxHfrcoFreq = setFreq; /* Wait for any previous sync to complete, then set calibration data for the selected frequency. */ while (BUS_RegBitRead(&CMU->SYNCBUSY, _CMU_SYNCBUSY_AUXHFRCOBSY_SHIFT) != 0UL) { } /* Set a divider in AUXHFRCOCTRL for 1, 2, and 4 MHz. */ switch (setFreq) { case cmuAUXHFRCOFreq_1M0Hz: freqCal = (freqCal & ~_CMU_AUXHFRCOCTRL_CLKDIV_MASK) | CMU_AUXHFRCOCTRL_CLKDIV_DIV4; break; case cmuAUXHFRCOFreq_2M0Hz: freqCal = (freqCal & ~_CMU_AUXHFRCOCTRL_CLKDIV_MASK) | CMU_AUXHFRCOCTRL_CLKDIV_DIV2; break; case cmuAUXHFRCOFreq_4M0Hz: freqCal = (freqCal & ~_CMU_AUXHFRCOCTRL_CLKDIV_MASK) | CMU_AUXHFRCOCTRL_CLKDIV_DIV1; break; default: break; } CMU->AUXHFRCOCTRL = freqCal; } #endif /* _CMU_AUXHFRCOCTRL_FREQRANGE_MASK */ /***************************************************************************//** * @brief * Calibrate the clock. * * @details * Run a calibration for HFCLK against a selectable reference clock. * See the reference manual, CMU chapter, for more details. * * @note * This function will not return until the calibration measurement is completed. * * @param[in] HFCycles * The number of HFCLK cycles to run the calibration. Increasing this number * increases precision but the calibration will take more time. * * @param[in] ref * The reference clock used to compare HFCLK. * * @return * The number of ticks the reference clock after HFCycles ticks on the HF * clock. ******************************************************************************/ uint32_t CMU_Calibrate(uint32_t HFCycles, CMU_Osc_TypeDef reference) { EFM_ASSERT(HFCycles <= (_CMU_CALCNT_CALCNT_MASK >> _CMU_CALCNT_CALCNT_SHIFT)); /* Set the reference clock source. */ switch (reference) { case cmuOsc_LFXO: CMU->CALCTRL = CMU_CALCTRL_UPSEL_LFXO; break; case cmuOsc_LFRCO: CMU->CALCTRL = CMU_CALCTRL_UPSEL_LFRCO; break; case cmuOsc_HFXO: CMU->CALCTRL = CMU_CALCTRL_UPSEL_HFXO; break; case cmuOsc_HFRCO: CMU->CALCTRL = CMU_CALCTRL_UPSEL_HFRCO; break; case cmuOsc_AUXHFRCO: CMU->CALCTRL = CMU_CALCTRL_UPSEL_AUXHFRCO; break; #if defined (_CMU_USHFRCOCTRL_MASK) case cmuOsc_USHFRCO: CMU->CALCTRL = CMU_CALCTRL_UPSEL_USHFRCO; break; #endif default: EFM_ASSERT(false); return 0; } /* Set the top value. */ CMU->CALCNT = HFCycles; /* Start the calibration. */ CMU->CMD = CMU_CMD_CALSTART; #if defined(CMU_STATUS_CALRDY) /* Wait until calibration completes. */ while (BUS_RegBitRead(&CMU->STATUS, _CMU_STATUS_CALRDY_SHIFT) == 0UL) { } #else /* Wait until calibration completes. */ while (BUS_RegBitRead(&CMU->STATUS, _CMU_STATUS_CALBSY_SHIFT) != 0UL) { } #endif return CMU->CALCNT; } #if defined(_CMU_CALCTRL_UPSEL_MASK) && defined(_CMU_CALCTRL_DOWNSEL_MASK) /***************************************************************************//** * @brief * Configure the clock calibration. * * @details * Configure a calibration for a selectable clock source against another * selectable reference clock. * See the reference manual, CMU chapter, for more details. * * @note * After configuration, a call to @ref CMU_CalibrateStart() is required and * the resulting calibration value can be read out with the * @ref CMU_CalibrateCountGet() function call. * * @param[in] downCycles * The number of downSel clock cycles to run the calibration. Increasing this * number increases precision but the calibration will take more time. * * @param[in] downSel * The clock, which will be counted down downCycles. * * @param[in] upSel * The reference clock; the number of cycles generated by this clock will * be counted and added up and the result can be given with the * @ref CMU_CalibrateCountGet() function call. ******************************************************************************/ void CMU_CalibrateConfig(uint32_t downCycles, CMU_Osc_TypeDef downSel, CMU_Osc_TypeDef upSel) { /* Keep configuration settings untouched. */ uint32_t calCtrl = CMU->CALCTRL & ~(_CMU_CALCTRL_UPSEL_MASK | _CMU_CALCTRL_DOWNSEL_MASK); /* 20 bits of precision to calibration count register. */ EFM_ASSERT(downCycles <= (_CMU_CALCNT_CALCNT_MASK >> _CMU_CALCNT_CALCNT_SHIFT)); /* Set down counting clock source - down counter. */ switch (downSel) { case cmuOsc_LFXO: calCtrl |= CMU_CALCTRL_DOWNSEL_LFXO; break; case cmuOsc_LFRCO: calCtrl |= CMU_CALCTRL_DOWNSEL_LFRCO; break; case cmuOsc_HFXO: calCtrl |= CMU_CALCTRL_DOWNSEL_HFXO; break; case cmuOsc_HFRCO: calCtrl |= CMU_CALCTRL_DOWNSEL_HFRCO; break; case cmuOsc_AUXHFRCO: calCtrl |= CMU_CALCTRL_DOWNSEL_AUXHFRCO; break; #if defined (_CMU_USHFRCOCTRL_MASK) case cmuOsc_USHFRCO: calCtrl |= CMU_CALCTRL_DOWNSEL_USHFRCO; break; #endif default: EFM_ASSERT(false); break; } /* Set the top value to be counted down by the downSel clock. */ CMU->CALCNT = downCycles; /* Set the reference clock source - up counter. */ switch (upSel) { case cmuOsc_LFXO: calCtrl |= CMU_CALCTRL_UPSEL_LFXO; break; case cmuOsc_LFRCO: calCtrl |= CMU_CALCTRL_UPSEL_LFRCO; break; case cmuOsc_HFXO: calCtrl |= CMU_CALCTRL_UPSEL_HFXO; break; case cmuOsc_HFRCO: calCtrl |= CMU_CALCTRL_UPSEL_HFRCO; break; case cmuOsc_AUXHFRCO: calCtrl |= CMU_CALCTRL_UPSEL_AUXHFRCO; break; #if defined (_CMU_USHFRCOCTRL_MASK) case cmuOsc_USHFRCO: calCtrl |= CMU_CALCTRL_UPSEL_USHFRCO; break; #endif default: EFM_ASSERT(false); break; } CMU->CALCTRL = calCtrl; } #endif /***************************************************************************//** * @brief * Get the calibration count register. * @note * If continuous calibration mode is active, calibration busy will almost * always be off and only the value needs to be read. In a normal case, * this function call is triggered by the CALRDY * interrupt flag. * @return * The calibration count, the number of UPSEL clocks (see @ref CMU_CalibrateConfig()) * in the period of DOWNSEL oscillator clock cycles configured by a previous * write operation to CMU->CALCNT. ******************************************************************************/ uint32_t CMU_CalibrateCountGet(void) { /* Wait until calibration completes, UNLESS continuous calibration mode is */ /* active. */ #if defined(CMU_CALCTRL_CONT) if (BUS_RegBitRead(&CMU->CALCTRL, _CMU_CALCTRL_CONT_SHIFT) == 0UL) { #if defined(CMU_STATUS_CALRDY) /* Wait until calibration completes */ while (BUS_RegBitRead(&CMU->STATUS, _CMU_STATUS_CALRDY_SHIFT) == 0UL) { } #else /* Wait until calibration completes */ while (BUS_RegBitRead(&CMU->STATUS, _CMU_STATUS_CALBSY_SHIFT) != 0UL) { } #endif } #else while (BUS_RegBitRead(&CMU->STATUS, _CMU_STATUS_CALBSY_SHIFT) != 0UL) { } #endif return CMU->CALCNT; } /***************************************************************************//** * @brief * Get the clock divisor/prescaler. * * @param[in] clock * A clock point to get the divisor/prescaler for. Notice that not all clock points * have a divisor/prescaler. See the CMU overview in the reference manual. * * @return * The current clock point divisor/prescaler. 1 is returned * if @p clock specifies a clock point without a divisor/prescaler. ******************************************************************************/ CMU_ClkDiv_TypeDef CMU_ClockDivGet(CMU_Clock_TypeDef clock) { #if defined(_SILICON_LABS_32B_SERIES_1) return 1UL + (uint32_t)CMU_ClockPrescGet(clock); #elif defined(_SILICON_LABS_32B_SERIES_0) uint32_t divReg; CMU_ClkDiv_TypeDef ret; /* Get divisor reg ID. */ divReg = (clock >> CMU_DIV_REG_POS) & CMU_DIV_REG_MASK; switch (divReg) { #if defined(_CMU_CTRL_HFCLKDIV_MASK) case CMU_HFCLKDIV_REG: ret = 1 + ((CMU->CTRL & _CMU_CTRL_HFCLKDIV_MASK) >> _CMU_CTRL_HFCLKDIV_SHIFT); break; #endif case CMU_HFPERCLKDIV_REG: ret = (CMU_ClkDiv_TypeDef)((CMU->HFPERCLKDIV & _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK) >> _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT); ret = CMU_Log2ToDiv(ret); break; case CMU_HFCORECLKDIV_REG: ret = (CMU_ClkDiv_TypeDef)((CMU->HFCORECLKDIV & _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK) >> _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT); ret = CMU_Log2ToDiv(ret); break; case CMU_LFAPRESC0_REG: switch (clock) { case cmuClock_RTC: ret = (CMU_ClkDiv_TypeDef)((CMU->LFAPRESC0 & _CMU_LFAPRESC0_RTC_MASK) >> _CMU_LFAPRESC0_RTC_SHIFT); ret = CMU_Log2ToDiv(ret); break; #if defined(_CMU_LFAPRESC0_LETIMER0_MASK) case cmuClock_LETIMER0: ret = (CMU_ClkDiv_TypeDef)((CMU->LFAPRESC0 & _CMU_LFAPRESC0_LETIMER0_MASK) >> _CMU_LFAPRESC0_LETIMER0_SHIFT); ret = CMU_Log2ToDiv(ret); break; #endif #if defined(_CMU_LFAPRESC0_LCD_MASK) case cmuClock_LCDpre: ret = (CMU_ClkDiv_TypeDef)(((CMU->LFAPRESC0 & _CMU_LFAPRESC0_LCD_MASK) >> _CMU_LFAPRESC0_LCD_SHIFT) + CMU_DivToLog2(cmuClkDiv_16)); ret = CMU_Log2ToDiv(ret); break; #endif #if defined(_CMU_LFAPRESC0_LESENSE_MASK) case cmuClock_LESENSE: ret = (CMU_ClkDiv_TypeDef)((CMU->LFAPRESC0 & _CMU_LFAPRESC0_LESENSE_MASK) >> _CMU_LFAPRESC0_LESENSE_SHIFT); ret = CMU_Log2ToDiv(ret); break; #endif default: ret = cmuClkDiv_1; EFM_ASSERT(false); break; } break; case CMU_LFBPRESC0_REG: switch (clock) { #if defined(_CMU_LFBPRESC0_LEUART0_MASK) case cmuClock_LEUART0: ret = (CMU_ClkDiv_TypeDef)((CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART0_MASK) >> _CMU_LFBPRESC0_LEUART0_SHIFT); ret = CMU_Log2ToDiv(ret); break; #endif #if defined(_CMU_LFBPRESC0_LEUART1_MASK) case cmuClock_LEUART1: ret = (CMU_ClkDiv_TypeDef)((CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART1_MASK) >> _CMU_LFBPRESC0_LEUART1_SHIFT); ret = CMU_Log2ToDiv(ret); break; #endif default: ret = cmuClkDiv_1; EFM_ASSERT(false); break; } break; default: ret = cmuClkDiv_1; EFM_ASSERT(false); break; } return ret; #endif } /***************************************************************************//** * @brief * Set the clock divisor/prescaler. * * @note * If setting an LF clock prescaler, synchronization into the low-frequency * domain is required. If the same register is modified before a previous * update has completed, this function will stall until the previous * synchronization has completed. See @ref CMU_FreezeEnable() for * a suggestion on how to reduce the stalling time in some use cases. * * HFCLKLE prescaler is automatically modified when peripherals with clock * domain HFBUSCLK is chosen based on the maximum HFLE frequency allowed. * * @param[in] clock * Clock point to set divisor/prescaler for. Notice that not all clock points * have a divisor/prescaler. See the CMU overview in the reference * manual. * * @param[in] div * The clock divisor to use (<= cmuClkDiv_512). ******************************************************************************/ void CMU_ClockDivSet(CMU_Clock_TypeDef clock, CMU_ClkDiv_TypeDef div) { #if defined(_SILICON_LABS_32B_SERIES_1) CMU_ClockPrescSet(clock, (CMU_ClkPresc_TypeDef)(div - 1U)); #elif defined(_SILICON_LABS_32B_SERIES_0) uint32_t freq; uint32_t divReg; /* Get the divisor reg ID. */ divReg = (clock >> CMU_DIV_REG_POS) & CMU_DIV_REG_MASK; switch (divReg) { #if defined(_CMU_CTRL_HFCLKDIV_MASK) case CMU_HFCLKDIV_REG: EFM_ASSERT((div >= cmuClkDiv_1) && (div <= cmuClkDiv_8)); /* Configure worst case wait states for flash access before setting divisor. */ flashWaitStateMax(); /* Set the divider. */ CMU->CTRL = (CMU->CTRL & ~_CMU_CTRL_HFCLKDIV_MASK) | ((div - 1) << _CMU_CTRL_HFCLKDIV_SHIFT); /* Update the CMSIS core clock variable. */ /* (The function will update the global variable). */ freq = SystemCoreClockGet(); /* Optimize flash access wait state setting for the current core clk. */ CMU_UpdateWaitStates(freq, (int)VSCALE_DEFAULT); break; #endif case CMU_HFPERCLKDIV_REG: EFM_ASSERT((div >= cmuClkDiv_1) && (div <= cmuClkDiv_512)); /* Convert to the correct scale. */ div = CMU_DivToLog2(div); CMU->HFPERCLKDIV = (CMU->HFPERCLKDIV & ~_CMU_HFPERCLKDIV_HFPERCLKDIV_MASK) | (div << _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT); break; case CMU_HFCORECLKDIV_REG: EFM_ASSERT((div >= cmuClkDiv_1) && (div <= cmuClkDiv_512)); /* Configure worst case wait states for flash access before setting the divisor. */ flashWaitStateMax(); #if defined(CMU_MAX_FREQ_HFLE) setHfLeConfig(SystemHFClockGet() / div); #endif /* Convert to the correct scale. */ div = CMU_DivToLog2(div); CMU->HFCORECLKDIV = (CMU->HFCORECLKDIV & ~_CMU_HFCORECLKDIV_HFCORECLKDIV_MASK) | (div << _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT); /* Update the CMSIS core clock variable. */ /* (The function will update the global variable). */ freq = SystemCoreClockGet(); /* Optimize wait state setting for the current core clk. */ CMU_UpdateWaitStates(freq, (int)VSCALE_DEFAULT); break; case CMU_LFAPRESC0_REG: switch (clock) { case cmuClock_RTC: EFM_ASSERT(div <= cmuClkDiv_32768); /* LF register about to be modified requires sync. busy check. */ syncReg(CMU_SYNCBUSY_LFAPRESC0); /* Convert to the correct scale. */ div = CMU_DivToLog2(div); CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_RTC_MASK) | (div << _CMU_LFAPRESC0_RTC_SHIFT); break; #if defined(_CMU_LFAPRESC0_LETIMER0_MASK) case cmuClock_LETIMER0: EFM_ASSERT(div <= cmuClkDiv_32768); /* LF register about to be modified requires sync. busy check. */ syncReg(CMU_SYNCBUSY_LFAPRESC0); /* Convert to the correct scale. */ div = CMU_DivToLog2(div); CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_LETIMER0_MASK) | (div << _CMU_LFAPRESC0_LETIMER0_SHIFT); break; #endif #if defined(LCD_PRESENT) case cmuClock_LCDpre: EFM_ASSERT((div >= cmuClkDiv_16) && (div <= cmuClkDiv_128)); /* LF register about to be modified requires sync. busy check. */ syncReg(CMU_SYNCBUSY_LFAPRESC0); /* Convert to the correct scale. */ div = CMU_DivToLog2(div); CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_LCD_MASK) | ((div - CMU_DivToLog2(cmuClkDiv_16)) << _CMU_LFAPRESC0_LCD_SHIFT); break; #endif /* defined(LCD_PRESENT) */ #if defined(LESENSE_PRESENT) case cmuClock_LESENSE: EFM_ASSERT(div <= cmuClkDiv_8); /* LF register about to be modified requires sync. busy check. */ syncReg(CMU_SYNCBUSY_LFAPRESC0); /* Convert to the correct scale. */ div = CMU_DivToLog2(div); CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_LESENSE_MASK) | (div << _CMU_LFAPRESC0_LESENSE_SHIFT); break; #endif /* defined(LESENSE_PRESENT) */ default: EFM_ASSERT(false); break; } break; case CMU_LFBPRESC0_REG: switch (clock) { #if defined(_CMU_LFBPRESC0_LEUART0_MASK) case cmuClock_LEUART0: EFM_ASSERT(div <= cmuClkDiv_8); /* LF register about to be modified requires sync. busy check. */ syncReg(CMU_SYNCBUSY_LFBPRESC0); /* Convert to the correct scale. */ div = CMU_DivToLog2(div); CMU->LFBPRESC0 = (CMU->LFBPRESC0 & ~_CMU_LFBPRESC0_LEUART0_MASK) | (((uint32_t)div) << _CMU_LFBPRESC0_LEUART0_SHIFT); break; #endif #if defined(_CMU_LFBPRESC0_LEUART1_MASK) case cmuClock_LEUART1: EFM_ASSERT(div <= cmuClkDiv_8); /* LF register about to be modified requires sync. busy check. */ syncReg(CMU_SYNCBUSY_LFBPRESC0); /* Convert to the correct scale. */ div = CMU_DivToLog2(div); CMU->LFBPRESC0 = (CMU->LFBPRESC0 & ~_CMU_LFBPRESC0_LEUART1_MASK) | (((uint32_t)div) << _CMU_LFBPRESC0_LEUART1_SHIFT); break; #endif default: EFM_ASSERT(false); break; } break; default: EFM_ASSERT(false); break; } #endif } /***************************************************************************//** * @brief * Enable/disable a clock. * * @details * In general, module clocking is disabled after a reset. If a module * clock is disabled, the registers of that module are not accessible and * reading from such registers may return undefined values. Writing to * registers of clock-disabled modules has no effect. * Avoid accessing module registers of a module with a disabled clock. * * @note * If enabling/disabling an LF clock, synchronization into the low-frequency * domain is required. If the same register is modified before a previous * update has completed, this function will stall until the previous * synchronization has completed. See @ref CMU_FreezeEnable() for * a suggestion on how to reduce the stalling time in some use cases. * * HFCLKLE prescaler is automatically modified when peripherals with clock * domain HFBUSCLK is chosen based on the maximum HFLE frequency allowed. * * @param[in] clock * The clock to enable/disable. Notice that not all defined clock * points have separate enable/disable control. See the CMU overview * in the reference manual. * * @param[in] enable * @li true - enable specified clock. * @li false - disable specified clock. ******************************************************************************/ void CMU_ClockEnable(CMU_Clock_TypeDef clock, bool enable) { volatile uint32_t *reg; uint32_t bit; uint32_t sync = 0; /* Identify enable register */ switch (((unsigned)clock >> CMU_EN_REG_POS) & CMU_EN_REG_MASK) { #if defined(_CMU_CTRL_HFPERCLKEN_MASK) case CMU_CTRL_EN_REG: reg = &CMU->CTRL; break; #endif #if defined(_CMU_HFCORECLKEN0_MASK) case CMU_HFCORECLKEN0_EN_REG: reg = &CMU->HFCORECLKEN0; #if defined(CMU_MAX_FREQ_HFLE) setHfLeConfig(CMU_ClockFreqGet(cmuClock_HFLE)); #endif break; #endif #if defined(_CMU_HFBUSCLKEN0_MASK) case CMU_HFBUSCLKEN0_EN_REG: reg = &CMU->HFBUSCLKEN0; break; #endif #if defined(_CMU_HFPERCLKDIV_MASK) case CMU_HFPERCLKDIV_EN_REG: reg = &CMU->HFPERCLKDIV; break; #endif case CMU_HFPERCLKEN0_EN_REG: reg = &CMU->HFPERCLKEN0; break; #if defined(_CMU_HFPERCLKEN1_MASK) case CMU_HFPERCLKEN1_EN_REG: reg = &CMU->HFPERCLKEN1; break; #endif case CMU_LFACLKEN0_EN_REG: reg = &CMU->LFACLKEN0; sync = CMU_SYNCBUSY_LFACLKEN0; break; case CMU_LFBCLKEN0_EN_REG: reg = &CMU->LFBCLKEN0; sync = CMU_SYNCBUSY_LFBCLKEN0; break; #if defined(_CMU_LFCCLKEN0_MASK) case CMU_LFCCLKEN0_EN_REG: reg = &CMU->LFCCLKEN0; sync = CMU_SYNCBUSY_LFCCLKEN0; break; #endif #if defined(_CMU_LFECLKEN0_MASK) case CMU_LFECLKEN0_EN_REG: reg = &CMU->LFECLKEN0; sync = CMU_SYNCBUSY_LFECLKEN0; break; #endif #if defined(_CMU_SDIOCTRL_MASK) case CMU_SDIOREF_EN_REG: reg = &CMU->SDIOCTRL; enable = !enable; break; #endif #if defined(_CMU_QSPICTRL_MASK) case CMU_QSPI0REF_EN_REG: reg = &CMU->QSPICTRL; enable = !enable; break; #endif #if defined(_CMU_USBCTRL_MASK) case CMU_USBRCLK_EN_REG: reg = &CMU->USBCTRL; break; #endif #if defined(_CMU_PDMCTRL_MASK) case CMU_PDMREF_EN_REG: reg = &CMU->PDMCTRL; break; #endif case CMU_PCNT_EN_REG: reg = &CMU->PCNTCTRL; break; default: /* Cannot enable/disable a clock point. */ EFM_ASSERT(false); return; } /* Get the bit position used to enable/disable. */ bit = ((unsigned)clock >> CMU_EN_BIT_POS) & CMU_EN_BIT_MASK; /* LF synchronization required. */ if (sync > 0UL) { syncReg(sync); } /* Set/clear bit as requested. */ BUS_RegBitWrite(reg, bit, (uint32_t)enable); } /***************************************************************************//** * @brief * Get the clock frequency for a clock point. * * @param[in] clock * A clock point to fetch the frequency for. * * @return * The current frequency in Hz. ******************************************************************************/ uint32_t CMU_ClockFreqGet(CMU_Clock_TypeDef clock) { uint32_t ret; switch ((unsigned)clock & (CMU_CLK_BRANCH_MASK << CMU_CLK_BRANCH_POS)) { case (CMU_HF_CLK_BRANCH << CMU_CLK_BRANCH_POS): ret = SystemHFClockGet(); break; case (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS): ret = SystemHFClockGet(); /* Calculate frequency after HFPER divider. */ #if defined(_CMU_HFPERCLKDIV_HFPERCLKDIV_MASK) ret >>= (CMU->HFPERCLKDIV & _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK) >> _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT; #endif #if defined(_CMU_HFPERPRESC_PRESC_MASK) ret /= 1U + ((CMU->HFPERPRESC & _CMU_HFPERPRESC_PRESC_MASK) >> _CMU_HFPERPRESC_PRESC_SHIFT); #endif break; #if defined(_CMU_HFPERPRESCB_MASK) case (CMU_HFPERB_CLK_BRANCH << CMU_CLK_BRANCH_POS): ret = SystemHFClockGet(); /* Calculate frequency after HFPERB prescaler. */ ret /= 1U + ((CMU->HFPERPRESCB & _CMU_HFPERPRESCB_PRESC_MASK) >> _CMU_HFPERPRESCB_PRESC_SHIFT); break; #endif #if defined(_CMU_HFPERPRESCC_MASK) case (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS): ret = SystemHFClockGet(); /* Calculate frequency after HFPERC prescaler. */ ret /= 1U + ((CMU->HFPERPRESCC & _CMU_HFPERPRESCC_PRESC_MASK) >> _CMU_HFPERPRESCC_PRESC_SHIFT); break; #endif #if defined(_SILICON_LABS_32B_SERIES_1) #if defined(CRYPTO_PRESENT) \ || defined(LDMA_PRESENT) \ || defined(GPCRC_PRESENT) \ || defined(PRS_PRESENT) \ || defined(GPIO_PRESENT) case (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS): ret = SystemHFClockGet(); #if defined(_CMU_HFBUSPRESC_MASK) ret /= 1U + ((CMU->HFBUSPRESC & _CMU_HFBUSPRESC_MASK) >> _CMU_HFBUSPRESC_PRESC_SHIFT); #endif break; #endif case (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS): ret = SystemHFClockGet(); ret /= 1U + ((CMU->HFCOREPRESC & _CMU_HFCOREPRESC_PRESC_MASK) >> _CMU_HFCOREPRESC_PRESC_SHIFT); break; case (CMU_HFEXP_CLK_BRANCH << CMU_CLK_BRANCH_POS): ret = SystemHFClockGet(); ret /= 1U + ((CMU->HFEXPPRESC & _CMU_HFEXPPRESC_PRESC_MASK) >> _CMU_HFEXPPRESC_PRESC_SHIFT); break; #endif #if defined(_SILICON_LABS_32B_SERIES_0) #if defined(AES_PRESENT) \ || defined(DMA_PRESENT) \ || defined(EBI_PRESENT) \ || defined(USB_PRESENT) case (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS): { ret = SystemCoreClockGet(); } break; #endif #endif case (CMU_LFA_CLK_BRANCH << CMU_CLK_BRANCH_POS): ret = lfClkGet(cmuClock_LFA); break; #if defined(_CMU_LFACLKEN0_RTC_MASK) case (CMU_RTC_CLK_BRANCH << CMU_CLK_BRANCH_POS): ret = lfClkGet(cmuClock_LFA); ret >>= (CMU->LFAPRESC0 & _CMU_LFAPRESC0_RTC_MASK) >> _CMU_LFAPRESC0_RTC_SHIFT; break; #endif #if defined(_CMU_LFECLKEN0_RTCC_MASK) case (CMU_RTCC_CLK_BRANCH << CMU_CLK_BRANCH_POS): ret = lfClkGet(cmuClock_LFE); ret >>= (CMU->LFEPRESC0 & _CMU_LFEPRESC0_RTCC_MASK) >> _CMU_LFEPRESC0_RTCC_SHIFT; break; #endif #if defined(_CMU_LFACLKEN0_LETIMER0_MASK) case (CMU_LETIMER0_CLK_BRANCH << CMU_CLK_BRANCH_POS): ret = lfClkGet(cmuClock_LFA); #if defined(_SILICON_LABS_32B_SERIES_0) ret >>= (CMU->LFAPRESC0 & _CMU_LFAPRESC0_LETIMER0_MASK) >> _CMU_LFAPRESC0_LETIMER0_SHIFT; #else ret /= CMU_Log2ToDiv((CMU->LFAPRESC0 & _CMU_LFAPRESC0_LETIMER0_MASK) >> _CMU_LFAPRESC0_LETIMER0_SHIFT); #endif break; #endif #if defined(_CMU_LFACLKEN0_LETIMER1_MASK) case (CMU_LETIMER1_CLK_BRANCH << CMU_CLK_BRANCH_POS): ret = lfClkGet(cmuClock_LFA); #if defined(_SILICON_LABS_32B_SERIES_0) ret >>= (CMU->LFAPRESC0 & _CMU_LFAPRESC0_LETIMER1_MASK) >> _CMU_LFAPRESC0_LETIMER1_SHIFT; #else ret /= CMU_Log2ToDiv((CMU->LFAPRESC0 & _CMU_LFAPRESC0_LETIMER1_MASK) >> _CMU_LFAPRESC0_LETIMER1_SHIFT); #endif break; #endif #if defined(_CMU_LFACLKEN0_LCD_MASK) case (CMU_LCDPRE_CLK_BRANCH << CMU_CLK_BRANCH_POS): ret = lfClkGet(cmuClock_LFA); #if defined(_SILICON_LABS_32B_SERIES_0) ret >>= ((CMU->LFAPRESC0 & _CMU_LFAPRESC0_LCD_MASK) >> _CMU_LFAPRESC0_LCD_SHIFT) + CMU_DivToLog2(cmuClkDiv_16); #else ret /= CMU_Log2ToDiv((CMU->LFAPRESC0 & _CMU_LFAPRESC0_LCD_MASK) >> _CMU_LFAPRESC0_LCD_SHIFT); #endif break; #if defined(_CMU_LCDCTRL_MASK) case (CMU_LCD_CLK_BRANCH << CMU_CLK_BRANCH_POS): ret = lfClkGet(cmuClock_LFA); ret >>= (CMU->LFAPRESC0 & _CMU_LFAPRESC0_LCD_MASK) >> _CMU_LFAPRESC0_LCD_SHIFT; ret /= 1U + ((CMU->LCDCTRL & _CMU_LCDCTRL_FDIV_MASK) >> _CMU_LCDCTRL_FDIV_SHIFT); break; #endif #endif #if defined(_CMU_LFACLKEN0_LESENSE_MASK) case (CMU_LESENSE_CLK_BRANCH << CMU_CLK_BRANCH_POS): ret = lfClkGet(cmuClock_LFA); ret >>= (CMU->LFAPRESC0 & _CMU_LFAPRESC0_LESENSE_MASK) >> _CMU_LFAPRESC0_LESENSE_SHIFT; break; #endif case (CMU_LFB_CLK_BRANCH << CMU_CLK_BRANCH_POS): ret = lfClkGet(cmuClock_LFB); break; #if defined(_CMU_LFBCLKEN0_LEUART0_MASK) case (CMU_LEUART0_CLK_BRANCH << CMU_CLK_BRANCH_POS): ret = lfClkGet(cmuClock_LFB); #if defined(_SILICON_LABS_32B_SERIES_0) ret >>= (CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART0_MASK) >> _CMU_LFBPRESC0_LEUART0_SHIFT; #else ret /= CMU_Log2ToDiv((CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART0_MASK) >> _CMU_LFBPRESC0_LEUART0_SHIFT); #endif break; #endif #if defined(_CMU_LFBCLKEN0_LEUART1_MASK) case (CMU_LEUART1_CLK_BRANCH << CMU_CLK_BRANCH_POS): ret = lfClkGet(cmuClock_LFB); #if defined(_SILICON_LABS_32B_SERIES_0) ret >>= (CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART1_MASK) >> _CMU_LFBPRESC0_LEUART1_SHIFT; #else ret /= CMU_Log2ToDiv((CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART1_MASK) >> _CMU_LFBPRESC0_LEUART1_SHIFT); #endif break; #endif #if defined(_CMU_LFBCLKEN0_CSEN_MASK) case (CMU_CSEN_LF_CLK_BRANCH << CMU_CLK_BRANCH_POS): ret = lfClkGet(cmuClock_LFB); ret /= CMU_Log2ToDiv(((CMU->LFBPRESC0 & _CMU_LFBPRESC0_CSEN_MASK) >> _CMU_LFBPRESC0_CSEN_SHIFT) + 4UL); break; #endif #if defined(CMU_LFCCLKEN0_USB) case (CMU_USBLE_CLK_BRANCH << CMU_CLK_BRANCH_POS): ret = lfClkGet(cmuClock_LFC); break; #endif #if defined(_SILICON_LABS_32B_SERIES_1) case (CMU_LFE_CLK_BRANCH << CMU_CLK_BRANCH_POS): ret = lfClkGet(cmuClock_LFE); break; #endif case (CMU_DBG_CLK_BRANCH << CMU_CLK_BRANCH_POS): ret = dbgClkGet(); break; case (CMU_AUX_CLK_BRANCH << CMU_CLK_BRANCH_POS): ret = auxClkGet(); break; #if defined(USBC_CLOCK_PRESENT) case (CMU_USBC_CLK_BRANCH << CMU_CLK_BRANCH_POS): ret = usbCClkGet(); break; #endif #if defined(_CMU_ADCCTRL_ADC0CLKSEL_MASK) case (CMU_ADC0ASYNC_CLK_BRANCH << CMU_CLK_BRANCH_POS): ret = adcAsyncClkGet(0); #if defined(_CMU_ADCCTRL_ADC0CLKDIV_MASK) ret /= 1U + ((CMU->ADCCTRL & _CMU_ADCCTRL_ADC0CLKDIV_MASK) >> _CMU_ADCCTRL_ADC0CLKDIV_SHIFT); #endif break; #endif #if defined(_CMU_ADCCTRL_ADC1CLKSEL_MASK) case (CMU_ADC1ASYNC_CLK_BRANCH << CMU_CLK_BRANCH_POS): ret = adcAsyncClkGet(1); #if defined(_CMU_ADCCTRL_ADC1CLKDIV_MASK) ret /= 1U + ((CMU->ADCCTRL & _CMU_ADCCTRL_ADC1CLKDIV_MASK) >> _CMU_ADCCTRL_ADC1CLKDIV_SHIFT); #endif break; #endif #if defined(_CMU_SDIOCTRL_SDIOCLKSEL_MASK) case (CMU_SDIOREF_CLK_BRANCH << CMU_CLK_BRANCH_POS): ret = sdioRefClkGet(); break; #endif #if defined(_CMU_QSPICTRL_QSPI0CLKSEL_MASK) case (CMU_QSPI0REF_CLK_BRANCH << CMU_CLK_BRANCH_POS): ret = qspiRefClkGet(0); break; #endif #if defined(USBR_CLOCK_PRESENT) case (CMU_USBR_CLK_BRANCH << CMU_CLK_BRANCH_POS): ret = usbRateClkGet(); break; #endif #if defined(_CMU_PDMCTRL_PDMCLKSEL_MASK) case (CMU_PDMREF_CLK_BRANCH << CMU_CLK_BRANCH_POS): ret = pdmRefClkGet(); break; #endif default: ret = 0; EFM_ASSERT(false); break; } return ret; } #if defined(_SILICON_LABS_32B_SERIES_1) /***************************************************************************//** * @brief * Get the clock prescaler. * * @param[in] clock * A clock point to get the prescaler for. Notice that not all clock points * have a prescaler. See the CMU overview in the reference manual. * * @return * The prescaler value of the current clock point. 0 is returned * if @p clock specifies a clock point without a prescaler. ******************************************************************************/ uint32_t CMU_ClockPrescGet(CMU_Clock_TypeDef clock) { uint32_t prescReg; uint32_t ret; /* Get the prescaler register ID. */ prescReg = ((unsigned)clock >> CMU_PRESC_REG_POS) & CMU_PRESC_REG_MASK; switch (prescReg) { case CMU_HFPRESC_REG: ret = (CMU->HFPRESC & _CMU_HFPRESC_PRESC_MASK) >> _CMU_HFPRESC_PRESC_SHIFT; break; case CMU_HFEXPPRESC_REG: ret = (CMU->HFEXPPRESC & _CMU_HFEXPPRESC_PRESC_MASK) >> _CMU_HFEXPPRESC_PRESC_SHIFT; break; case CMU_HFCLKLEPRESC_REG: ret = (CMU->HFPRESC & _CMU_HFPRESC_HFCLKLEPRESC_MASK) >> _CMU_HFPRESC_HFCLKLEPRESC_SHIFT; break; case CMU_HFPERPRESC_REG: ret = (CMU->HFPERPRESC & _CMU_HFPERPRESC_PRESC_MASK) >> _CMU_HFPERPRESC_PRESC_SHIFT; break; #if defined(_CMU_HFPERPRESCB_MASK) case CMU_HFPERPRESCB_REG: ret = (CMU->HFPERPRESCB & _CMU_HFPERPRESCB_PRESC_MASK) >> _CMU_HFPERPRESCB_PRESC_SHIFT; break; #endif #if defined(_CMU_HFPERPRESCC_MASK) case CMU_HFPERPRESCC_REG: ret = (CMU->HFPERPRESCC & _CMU_HFPERPRESCC_PRESC_MASK) >> _CMU_HFPERPRESCC_PRESC_SHIFT; break; #endif case CMU_HFCOREPRESC_REG: ret = (CMU->HFCOREPRESC & _CMU_HFCOREPRESC_PRESC_MASK) >> _CMU_HFCOREPRESC_PRESC_SHIFT; break; case CMU_LFAPRESC0_REG: switch (clock) { #if defined(_CMU_LFAPRESC0_LETIMER0_MASK) case cmuClock_LETIMER0: ret = (CMU->LFAPRESC0 & _CMU_LFAPRESC0_LETIMER0_MASK) >> _CMU_LFAPRESC0_LETIMER0_SHIFT; /* Convert the exponent to a prescaler value. */ ret = CMU_Log2ToDiv(ret) - 1U; break; #endif #if defined(_CMU_LFAPRESC0_LESENSE_MASK) case cmuClock_LESENSE: ret = (CMU->LFAPRESC0 & _CMU_LFAPRESC0_LESENSE_MASK) >> _CMU_LFAPRESC0_LESENSE_SHIFT; /* Convert the exponent to a prescaler value. */ ret = CMU_Log2ToDiv(ret) - 1U; break; #endif #if defined(_CMU_LFAPRESC0_LETIMER1_MASK) case cmuClock_LETIMER1: ret = (CMU->LFAPRESC0 & _CMU_LFAPRESC0_LETIMER1_MASK) >> _CMU_LFAPRESC0_LETIMER1_SHIFT; ret = CMU_Log2ToDiv(ret) - 1U; break; #endif #if defined(_CMU_LFAPRESC0_LCD_MASK) case cmuClock_LCD: case cmuClock_LCDpre: ret = (CMU->LFAPRESC0 & _CMU_LFAPRESC0_LCD_MASK) >> _CMU_LFAPRESC0_LCD_SHIFT; ret = CMU_Log2ToDiv(ret) - 1U; break; #endif #if defined(_CMU_LFAPRESC0_RTC_MASK) case cmuClock_RTC: ret = (CMU->LFAPRESC0 & _CMU_LFAPRESC0_RTC_MASK) >> _CMU_LFAPRESC0_RTC_SHIFT; ret = CMU_Log2ToDiv(ret) - 1U; break; #endif default: ret = 0U; EFM_ASSERT(false); break; } break; case CMU_LFBPRESC0_REG: switch (clock) { #if defined(_CMU_LFBPRESC0_LEUART0_MASK) case cmuClock_LEUART0: ret = (CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART0_MASK) >> _CMU_LFBPRESC0_LEUART0_SHIFT; /* Convert the exponent to a prescaler value. */ ret = CMU_Log2ToDiv(ret) - 1U; break; #endif #if defined(_CMU_LFBPRESC0_LEUART1_MASK) case cmuClock_LEUART1: ret = (CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART1_MASK) >> _CMU_LFBPRESC0_LEUART1_SHIFT; /* Convert the exponent to a prescaler value. */ ret = CMU_Log2ToDiv(ret) - 1U; break; #endif #if defined(_CMU_LFBPRESC0_CSEN_MASK) case cmuClock_CSEN_LF: ret = (CMU->LFBPRESC0 & _CMU_LFBPRESC0_CSEN_MASK) >> _CMU_LFBPRESC0_CSEN_SHIFT; /* Convert the exponent to a prescaler value. */ ret = CMU_Log2ToDiv(ret + 4U) - 1U; break; #endif default: ret = 0U; EFM_ASSERT(false); break; } break; case CMU_LFEPRESC0_REG: switch (clock) { #if defined(RTCC_PRESENT) case cmuClock_RTCC: ret = (CMU->LFEPRESC0 & _CMU_LFEPRESC0_RTCC_MASK) >> _CMU_LFEPRESC0_RTCC_SHIFT; break; default: ret = 0U; EFM_ASSERT(false); break; #endif } break; #if defined(_CMU_ADCCTRL_ADC0CLKDIV_MASK) \ || defined(_CMU_ADCCTRL_ADC1CLKDIV_MASK) case CMU_ADCASYNCDIV_REG: switch (clock) { #if defined(_CMU_ADCCTRL_ADC0CLKDIV_MASK) case cmuClock_ADC0ASYNC: ret = (CMU->ADCCTRL & _CMU_ADCCTRL_ADC0CLKDIV_MASK) >> _CMU_ADCCTRL_ADC0CLKDIV_SHIFT; break; #endif #if defined(_CMU_ADCCTRL_ADC1CLKDIV_MASK) case cmuClock_ADC1ASYNC: ret = (CMU->ADCCTRL & _CMU_ADCCTRL_ADC1CLKDIV_MASK) >> _CMU_ADCCTRL_ADC1CLKDIV_SHIFT; break; #endif default: ret = 0U; EFM_ASSERT(false); break; } break; #endif #if defined(_CMU_HFBUSPRESC_MASK) case CMU_HFBUSPRESC_REG: ret = (CMU->HFBUSPRESC & _CMU_HFBUSPRESC_MASK) >> _CMU_HFBUSPRESC_PRESC_SHIFT; break; #endif default: ret = 0U; EFM_ASSERT(false); break; } return ret; } #endif #if defined(_SILICON_LABS_32B_SERIES_1) /***************************************************************************//** * @brief * Set the clock prescaler. * * @note * If setting an LF clock prescaler, synchronization into the low-frequency * domain is required. If the same register is modified before a previous * update has completed, this function will stall until the previous * synchronization has completed. See @ref CMU_FreezeEnable() for * a suggestion on how to reduce the stalling time in some use cases. * * HFCLKLE prescaler is automatically modified when peripherals with clock * domain HFBUSCLK is chosen based on the maximum HFLE frequency allowed. * * @param[in] clock * A clock point to set the prescaler for. Notice that not all clock points * have a prescaler. See the CMU overview in the reference manual. * * @param[in] presc * The clock prescaler. ******************************************************************************/ void CMU_ClockPrescSet(CMU_Clock_TypeDef clock, CMU_ClkPresc_TypeDef presc) { uint32_t freq; uint32_t prescReg; /* Get the divisor reg ID. */ prescReg = ((unsigned)clock >> CMU_PRESC_REG_POS) & CMU_PRESC_REG_MASK; switch (prescReg) { case CMU_HFPRESC_REG: EFM_ASSERT(presc < 32U); /* Configure worst case wait-states for flash and HFLE, set safe HFPER clock-tree prescalers. */ flashWaitStateMax(); setHfLeConfig(CMU_MAX_FREQ_HFLE + 1UL); hfperClkSafePrescaler(); CMU->HFPRESC = (CMU->HFPRESC & ~_CMU_HFPRESC_PRESC_MASK) | (presc << _CMU_HFPRESC_PRESC_SHIFT); /* Update the CMSIS core clock variable (this function updates the global variable). */ freq = SystemCoreClockGet(); /* Optimize flash and HFLE wait states and set optimized HFPER clock-tree prescalers. */ CMU_UpdateWaitStates(freq, (int)VSCALE_DEFAULT); setHfLeConfig(CMU_ClockFreqGet(cmuClock_HFLE)); hfperClkOptimizedPrescaler(); break; case CMU_HFEXPPRESC_REG: EFM_ASSERT(presc < 32U); CMU->HFEXPPRESC = (CMU->HFEXPPRESC & ~_CMU_HFEXPPRESC_PRESC_MASK) | (presc << _CMU_HFEXPPRESC_PRESC_SHIFT); break; case CMU_HFPERPRESC_REG: EFM_ASSERT(presc < 512U); CMU->HFPERPRESC = (CMU->HFPERPRESC & ~_CMU_HFPERPRESC_PRESC_MASK) | (presc << _CMU_HFPERPRESC_PRESC_SHIFT); break; #if defined(_CMU_HFPERPRESCB_MASK) case CMU_HFPERPRESCB_REG: EFM_ASSERT(presc < 512U); CMU->HFPERPRESCB = (CMU->HFPERPRESCB & ~_CMU_HFPERPRESCB_PRESC_MASK) | (presc << _CMU_HFPERPRESCB_PRESC_SHIFT); break; #endif #if defined(_CMU_HFPERPRESCC_MASK) case CMU_HFPERPRESCC_REG: EFM_ASSERT(presc < 512U); CMU->HFPERPRESCC = (CMU->HFPERPRESCC & ~_CMU_HFPERPRESCC_PRESC_MASK) | (presc << _CMU_HFPERPRESCC_PRESC_SHIFT); break; #endif case CMU_HFCOREPRESC_REG: EFM_ASSERT(presc < 512U); /* Configure worst case wait-states for flash and HFLE. */ flashWaitStateMax(); setHfLeConfig(CMU_MAX_FREQ_HFLE + 1UL); CMU->HFCOREPRESC = (CMU->HFCOREPRESC & ~_CMU_HFCOREPRESC_PRESC_MASK) | (presc << _CMU_HFCOREPRESC_PRESC_SHIFT); /* Update the CMSIS core clock variable (this function updates the global variable). Optimize flash and HFLE wait states. */ freq = SystemCoreClockGet(); CMU_UpdateWaitStates(freq, (int)VSCALE_DEFAULT); setHfLeConfig(CMU_ClockFreqGet(cmuClock_HFLE)); break; case CMU_LFAPRESC0_REG: switch (clock) { #if defined(RTC_PRESENT) case cmuClock_RTC: EFM_ASSERT(presc <= 32768U); /* Convert the prescaler value to a DIV exponent scale. */ presc = CMU_PrescToLog2(presc); /* LF register about to be modified requires sync. Busy check. */ syncReg(CMU_SYNCBUSY_LFAPRESC0); CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_RTC_MASK) | (presc << _CMU_LFAPRESC0_RTC_SHIFT); break; #endif #if defined(RTCC_PRESENT) case cmuClock_RTCC: #if defined(_CMU_LFEPRESC0_RTCC_MASK) #if defined(_CMU_LFEPRESC0_RTCC_DIV4) EFM_ASSERT(presc <= _CMU_LFEPRESC0_RTCC_DIV4); #elif defined(_CMU_LFEPRESC0_RTCC_DIV2) EFM_ASSERT(presc <= _CMU_LFEPRESC0_RTCC_DIV2); #else EFM_ASSERT(presc <= 0U); #endif /* LF register about to be modified requires sync. Busy check. */ syncReg(CMU_SYNCBUSY_LFEPRESC0); CMU->LFEPRESC0 = (CMU->LFEPRESC0 & ~_CMU_LFEPRESC0_RTCC_MASK) | (presc << _CMU_LFEPRESC0_RTCC_SHIFT); #else EFM_ASSERT(presc <= 32768U); /* Convert the prescaler value to a DIV exponent scale. */ presc = CMU_PrescToLog2(presc); /* LF register about to be modified requires sync. Busy check. */ syncReg(CMU_SYNCBUSY_LFAPRESC0); CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_RTCC_MASK) | (presc << _CMU_LFAPRESC0_RTCC_SHIFT); #endif break; #endif #if defined(_CMU_LFAPRESC0_LETIMER0_MASK) case cmuClock_LETIMER0: EFM_ASSERT(presc <= 32768U); /* Convert the prescaler value to a DIV exponent scale. */ presc = CMU_PrescToLog2(presc); /* LF register about to be modified requires sync. Busy check. */ syncReg(CMU_SYNCBUSY_LFAPRESC0); CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_LETIMER0_MASK) | (presc << _CMU_LFAPRESC0_LETIMER0_SHIFT); break; #endif #if defined(_CMU_LFAPRESC0_LETIMER1_MASK) case cmuClock_LETIMER1: EFM_ASSERT(presc <= 32768U); /* Convert the prescaler value to a DIV exponent scale. */ presc = CMU_PrescToLog2(presc); /* LF register about to be modified requires sync. Busy check. */ syncReg(CMU_SYNCBUSY_LFAPRESC0); CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_LETIMER1_MASK) | (presc << _CMU_LFAPRESC0_LETIMER1_SHIFT); break; #endif #if defined(_CMU_LFAPRESC0_LESENSE_MASK) case cmuClock_LESENSE: EFM_ASSERT(presc <= 8U); /* Convert the prescaler value to a DIV exponent scale. */ presc = CMU_PrescToLog2(presc); /* LF register about to be modified requires sync. Busy check. */ syncReg(CMU_SYNCBUSY_LFAPRESC0); CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_LESENSE_MASK) | (presc << _CMU_LFAPRESC0_LESENSE_SHIFT); break; #endif #if defined(_CMU_LFAPRESC0_LCD_MASK) case cmuClock_LCDpre: case cmuClock_LCD: EFM_ASSERT(presc <= 32768U); /* Convert the prescaler value to a DIV exponent scale. */ presc = CMU_PrescToLog2(presc); /* LF register about to be modified requires sync. Busy check. */ syncReg(CMU_SYNCBUSY_LFAPRESC0); CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_LCD_MASK) | (presc << _CMU_LFAPRESC0_LCD_SHIFT); break; #endif default: EFM_ASSERT(false); break; } break; case CMU_LFBPRESC0_REG: switch (clock) { #if defined(_CMU_LFBPRESC0_LEUART0_MASK) case cmuClock_LEUART0: EFM_ASSERT(presc <= 8U); /* Convert the prescaler value to a DIV exponent scale. */ presc = CMU_PrescToLog2(presc); /* LF register about to be modified requires sync. Busy check. */ syncReg(CMU_SYNCBUSY_LFBPRESC0); CMU->LFBPRESC0 = (CMU->LFBPRESC0 & ~_CMU_LFBPRESC0_LEUART0_MASK) | (presc << _CMU_LFBPRESC0_LEUART0_SHIFT); break; #endif #if defined(_CMU_LFBPRESC0_LEUART1_MASK) case cmuClock_LEUART1: EFM_ASSERT(presc <= 8U); /* Convert the prescaler value to a DIV exponent scale. */ presc = CMU_PrescToLog2(presc); /* LF register about to be modified requires sync. Busy check. */ syncReg(CMU_SYNCBUSY_LFBPRESC0); CMU->LFBPRESC0 = (CMU->LFBPRESC0 & ~_CMU_LFBPRESC0_LEUART1_MASK) | (presc << _CMU_LFBPRESC0_LEUART1_SHIFT); break; #endif #if defined(_CMU_LFBPRESC0_CSEN_MASK) case cmuClock_CSEN_LF: EFM_ASSERT((presc <= 127U) && (presc >= 15U)); /* Convert the prescaler value to a DIV exponent scale. * DIV16 is the lowest supported prescaler. */ presc = CMU_PrescToLog2(presc) - 4U; /* LF register about to be modified requires sync. Busy check. */ syncReg(CMU_SYNCBUSY_LFBPRESC0); CMU->LFBPRESC0 = (CMU->LFBPRESC0 & ~_CMU_LFBPRESC0_CSEN_MASK) | (presc << _CMU_LFBPRESC0_CSEN_SHIFT); break; #endif default: EFM_ASSERT(false); break; } break; case CMU_LFEPRESC0_REG: switch (clock) { #if defined(_CMU_LFEPRESC0_RTCC_MASK) case cmuClock_RTCC: #if defined(_CMU_LFEPRESC0_RTCC_DIV4) EFM_ASSERT(presc <= _CMU_LFEPRESC0_RTCC_DIV4); #elif defined(_CMU_LFEPRESC0_RTCC_DIV2) EFM_ASSERT(presc <= _CMU_LFEPRESC0_RTCC_DIV2); #else EFM_ASSERT(presc <= 0U); #endif /* LF register about to be modified requires sync. Busy check. */ syncReg(CMU_SYNCBUSY_LFEPRESC0); CMU->LFEPRESC0 = (CMU->LFEPRESC0 & ~_CMU_LFEPRESC0_RTCC_MASK) | (presc << _CMU_LFEPRESC0_RTCC_SHIFT); break; #endif default: EFM_ASSERT(false); break; } break; #if defined(_CMU_ADCCTRL_ADC0CLKDIV_MASK) \ || defined(_CMU_ADCCTRL_ADC1CLKDIV_MASK) case CMU_ADCASYNCDIV_REG: switch (clock) { #if defined(_CMU_ADCCTRL_ADC0CLKDIV_MASK) case cmuClock_ADC0ASYNC: EFM_ASSERT(presc <= 3); CMU->ADCCTRL = (CMU->ADCCTRL & ~_CMU_ADCCTRL_ADC0CLKDIV_MASK) | (presc << _CMU_ADCCTRL_ADC0CLKDIV_SHIFT); break; #endif #if defined(_CMU_ADCCTRL_ADC1CLKDIV_MASK) case cmuClock_ADC1ASYNC: EFM_ASSERT(presc <= 3); CMU->ADCCTRL = (CMU->ADCCTRL & ~_CMU_ADCCTRL_ADC1CLKDIV_MASK) | (presc << _CMU_ADCCTRL_ADC1CLKDIV_SHIFT); break; #endif default: EFM_ASSERT(false); break; } break; #endif #if defined(_CMU_HFBUSPRESC_MASK) case CMU_HFBUSPRESC_REG: EFM_ASSERT(presc <= _CMU_HFBUSPRESC_MASK >> _CMU_HFBUSPRESC_PRESC_SHIFT); CMU->HFBUSPRESC = (CMU->HFBUSPRESC & ~_CMU_HFBUSPRESC_MASK) | (presc << _CMU_HFBUSPRESC_PRESC_SHIFT); break; #endif default: EFM_ASSERT(false); break; } } #endif /***************************************************************************//** * @brief * Get the currently selected reference clock used for a clock branch. * * @param[in] clock * Clock branch to fetch selected ref. clock for. One of: * @li #cmuClock_HF * @li #cmuClock_LFA * @li #cmuClock_LFB @if _CMU_LFCLKSEL_LFAE_ULFRCO * @li #cmuClock_LFC * @endif @if _SILICON_LABS_32B_SERIES_1 * @li #cmuClock_LFE * @endif * @li #cmuClock_DBG @if DOXYDOC_USB_PRESENT * @li #cmuClock_USBC * @endif * * @return * The reference clock used for clocking the selected branch, #cmuSelect_Error if * invalid @p clock provided. ******************************************************************************/ CMU_Select_TypeDef CMU_ClockSelectGet(CMU_Clock_TypeDef clock) { CMU_Select_TypeDef ret = cmuSelect_Disabled; uint32_t selReg; selReg = ((unsigned)clock >> CMU_SEL_REG_POS) & CMU_SEL_REG_MASK; switch (selReg) { case CMU_HFCLKSEL_REG: #if defined(_CMU_HFCLKSTATUS_MASK) switch (CMU->HFCLKSTATUS & _CMU_HFCLKSTATUS_SELECTED_MASK) { case CMU_HFCLKSTATUS_SELECTED_LFXO: ret = cmuSelect_LFXO; break; case CMU_HFCLKSTATUS_SELECTED_LFRCO: ret = cmuSelect_LFRCO; break; case CMU_HFCLKSTATUS_SELECTED_HFXO: ret = cmuSelect_HFXO; break; #if defined(CMU_HFCLKSTATUS_SELECTED_HFRCODIV2) case CMU_HFCLKSTATUS_SELECTED_HFRCODIV2: ret = cmuSelect_HFRCODIV2; break; #endif #if defined(CMU_HFCLKSTATUS_SELECTED_CLKIN0) case CMU_HFCLKSTATUS_SELECTED_CLKIN0: ret = cmuSelect_CLKIN0; break; #endif #if defined(CMU_HFCLKSTATUS_SELECTED_USHFRCO) case CMU_HFCLKSTATUS_SELECTED_USHFRCO: ret = cmuSelect_USHFRCO; break; #endif default: ret = cmuSelect_HFRCO; break; } #else switch (CMU->STATUS & (CMU_STATUS_HFRCOSEL | CMU_STATUS_HFXOSEL | CMU_STATUS_LFRCOSEL #if defined(CMU_STATUS_USHFRCODIV2SEL) | CMU_STATUS_USHFRCODIV2SEL #endif | CMU_STATUS_LFXOSEL)) { case CMU_STATUS_LFXOSEL: ret = cmuSelect_LFXO; break; case CMU_STATUS_LFRCOSEL: ret = cmuSelect_LFRCO; break; case CMU_STATUS_HFXOSEL: ret = cmuSelect_HFXO; break; #if defined(CMU_STATUS_USHFRCODIV2SEL) case CMU_STATUS_USHFRCODIV2SEL: ret = cmuSelect_USHFRCODIV2; break; #endif default: ret = cmuSelect_HFRCO; break; } #endif break; #if defined(_CMU_LFCLKSEL_MASK) || defined(_CMU_LFACLKSEL_MASK) case CMU_LFACLKSEL_REG: #if defined(_CMU_LFCLKSEL_MASK) switch (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFA_MASK) { case CMU_LFCLKSEL_LFA_LFRCO: ret = cmuSelect_LFRCO; break; case CMU_LFCLKSEL_LFA_LFXO: ret = cmuSelect_LFXO; break; #if defined(CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2) case CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2: ret = cmuSelect_HFCLKLE; break; #endif default: #if defined(CMU_LFCLKSEL_LFAE) if (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFAE_MASK) { ret = cmuSelect_ULFRCO; break; } #else ret = cmuSelect_Disabled; #endif break; } #elif defined(_CMU_LFACLKSEL_MASK) switch (CMU->LFACLKSEL & _CMU_LFACLKSEL_LFA_MASK) { case CMU_LFACLKSEL_LFA_LFRCO: ret = cmuSelect_LFRCO; break; case CMU_LFACLKSEL_LFA_LFXO: ret = cmuSelect_LFXO; break; case CMU_LFACLKSEL_LFA_ULFRCO: ret = cmuSelect_ULFRCO; break; #if defined(_CMU_LFACLKSEL_LFA_HFCLKLE) case CMU_LFACLKSEL_LFA_HFCLKLE: ret = cmuSelect_HFCLKLE; break; #endif default: ret = cmuSelect_Disabled; break; } #endif break; #endif /* _CMU_LFCLKSEL_MASK || _CMU_LFACLKSEL_MASK */ #if defined(_CMU_LFCLKSEL_MASK) || defined(_CMU_LFBCLKSEL_MASK) case CMU_LFBCLKSEL_REG: #if defined(_CMU_LFCLKSEL_MASK) switch (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFB_MASK) { case CMU_LFCLKSEL_LFB_LFRCO: ret = cmuSelect_LFRCO; break; case CMU_LFCLKSEL_LFB_LFXO: ret = cmuSelect_LFXO; break; #if defined(CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2) case CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2: ret = cmuSelect_HFCLKLE; break; #endif #if defined(CMU_LFCLKSEL_LFB_HFCLKLE) case CMU_LFCLKSEL_LFB_HFCLKLE: ret = cmuSelect_HFCLKLE; break; #endif default: #if defined(CMU_LFCLKSEL_LFBE) if (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFBE_MASK) { ret = cmuSelect_ULFRCO; break; } #else ret = cmuSelect_Disabled; #endif break; } #elif defined(_CMU_LFBCLKSEL_MASK) switch (CMU->LFBCLKSEL & _CMU_LFBCLKSEL_LFB_MASK) { case CMU_LFBCLKSEL_LFB_LFRCO: ret = cmuSelect_LFRCO; break; case CMU_LFBCLKSEL_LFB_LFXO: ret = cmuSelect_LFXO; break; case CMU_LFBCLKSEL_LFB_ULFRCO: ret = cmuSelect_ULFRCO; break; case CMU_LFBCLKSEL_LFB_HFCLKLE: ret = cmuSelect_HFCLKLE; break; default: ret = cmuSelect_Disabled; break; } #endif break; #endif /* _CMU_LFCLKSEL_MASK || _CMU_LFBCLKSEL_MASK */ #if defined(_CMU_LFCLKSEL_LFC_MASK) case CMU_LFCCLKSEL_REG: switch (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFC_MASK) { case CMU_LFCLKSEL_LFC_LFRCO: ret = cmuSelect_LFRCO; break; case CMU_LFCLKSEL_LFC_LFXO: ret = cmuSelect_LFXO; break; default: ret = cmuSelect_Disabled; break; } break; #endif #if defined(_CMU_LFECLKSEL_LFE_MASK) case CMU_LFECLKSEL_REG: switch (CMU->LFECLKSEL & _CMU_LFECLKSEL_LFE_MASK) { case CMU_LFECLKSEL_LFE_LFRCO: ret = cmuSelect_LFRCO; break; case CMU_LFECLKSEL_LFE_LFXO: ret = cmuSelect_LFXO; break; case CMU_LFECLKSEL_LFE_ULFRCO: ret = cmuSelect_ULFRCO; break; #if defined (_CMU_LFECLKSEL_LFE_HFCLKLE) case CMU_LFECLKSEL_LFE_HFCLKLE: ret = cmuSelect_HFCLKLE; break; #endif default: ret = cmuSelect_Disabled; break; } break; #endif /* CMU_LFECLKSEL_REG */ #if defined(_CMU_LFCCLKSEL_LFC_MASK) case CMU_LFCCLKSEL_REG: switch (CMU->LFCCLKSEL & _CMU_LFCCLKSEL_LFC_MASK) { case CMU_LFCCLKSEL_LFC_LFRCO: ret = cmuSelect_LFRCO; break; case CMU_LFCCLKSEL_LFC_LFXO: ret = cmuSelect_LFXO; break; case CMU_LFCCLKSEL_LFC_ULFRCO: ret = cmuSelect_ULFRCO; break; default: ret = cmuSelect_Disabled; break; } break; #endif /* CMU_LFCCLKSEL_REG */ case CMU_DBGCLKSEL_REG: #if defined(_CMU_DBGCLKSEL_DBG_MASK) switch (CMU->DBGCLKSEL & _CMU_DBGCLKSEL_DBG_MASK) { case CMU_DBGCLKSEL_DBG_HFCLK: ret = cmuSelect_HFCLK; break; case CMU_DBGCLKSEL_DBG_AUXHFRCO: ret = cmuSelect_AUXHFRCO; break; default: ret = cmuSelect_Disabled; break; } #elif defined(_CMU_CTRL_DBGCLK_MASK) switch (CMU->CTRL & _CMU_CTRL_DBGCLK_MASK) { case CMU_CTRL_DBGCLK_AUXHFRCO: ret = cmuSelect_AUXHFRCO; break; case CMU_CTRL_DBGCLK_HFCLK: ret = cmuSelect_HFCLK; break; } #else ret = cmuSelect_AUXHFRCO; #endif break; #if defined(USBC_CLOCK_PRESENT) case CMU_USBCCLKSEL_REG: switch (CMU->STATUS & (CMU_STATUS_USBCLFXOSEL #if defined(_CMU_STATUS_USBCHFCLKSEL_MASK) | CMU_STATUS_USBCHFCLKSEL #endif #if defined(_CMU_STATUS_USBCUSHFRCOSEL_MASK) | CMU_STATUS_USBCUSHFRCOSEL #endif | CMU_STATUS_USBCLFRCOSEL)) { #if defined(_CMU_STATUS_USBCHFCLKSEL_MASK) case CMU_STATUS_USBCHFCLKSEL: ret = cmuSelect_HFCLK; break; #endif #if defined(_CMU_STATUS_USBCUSHFRCOSEL_MASK) case CMU_STATUS_USBCUSHFRCOSEL: ret = cmuSelect_USHFRCO; break; #endif case CMU_STATUS_USBCLFXOSEL: ret = cmuSelect_LFXO; break; case CMU_STATUS_USBCLFRCOSEL: ret = cmuSelect_LFRCO; break; default: ret = cmuSelect_Disabled; break; } break; #endif #if defined(_CMU_ADCCTRL_ADC0CLKSEL_MASK) case CMU_ADC0ASYNCSEL_REG: switch (CMU->ADCCTRL & _CMU_ADCCTRL_ADC0CLKSEL_MASK) { case CMU_ADCCTRL_ADC0CLKSEL_DISABLED: ret = cmuSelect_Disabled; break; case CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO: ret = cmuSelect_AUXHFRCO; break; case CMU_ADCCTRL_ADC0CLKSEL_HFXO: ret = cmuSelect_HFXO; break; case CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK: ret = cmuSelect_HFSRCCLK; break; default: ret = cmuSelect_Disabled; break; } break; #endif #if defined(_CMU_ADCCTRL_ADC1CLKSEL_MASK) case CMU_ADC1ASYNCSEL_REG: switch (CMU->ADCCTRL & _CMU_ADCCTRL_ADC1CLKSEL_MASK) { case CMU_ADCCTRL_ADC1CLKSEL_DISABLED: ret = cmuSelect_Disabled; break; case CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO: ret = cmuSelect_AUXHFRCO; break; case CMU_ADCCTRL_ADC1CLKSEL_HFXO: ret = cmuSelect_HFXO; break; case CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK: ret = cmuSelect_HFSRCCLK; break; } break; #endif #if defined(_CMU_SDIOCTRL_SDIOCLKSEL_MASK) case CMU_SDIOREFSEL_REG: switch (CMU->SDIOCTRL & _CMU_SDIOCTRL_SDIOCLKSEL_MASK) { case CMU_SDIOCTRL_SDIOCLKSEL_HFRCO: ret = cmuSelect_HFRCO; break; case CMU_SDIOCTRL_SDIOCLKSEL_HFXO: ret = cmuSelect_HFXO; break; case CMU_SDIOCTRL_SDIOCLKSEL_AUXHFRCO: ret = cmuSelect_AUXHFRCO; break; case CMU_SDIOCTRL_SDIOCLKSEL_USHFRCO: ret = cmuSelect_USHFRCO; break; } break; #endif #if defined(_CMU_QSPICTRL_QSPI0CLKSEL_MASK) case CMU_QSPI0REFSEL_REG: switch (CMU->QSPICTRL & _CMU_QSPICTRL_QSPI0CLKSEL_MASK) { case CMU_QSPICTRL_QSPI0CLKSEL_HFRCO: ret = cmuSelect_HFRCO; break; case CMU_QSPICTRL_QSPI0CLKSEL_HFXO: ret = cmuSelect_HFXO; break; case CMU_QSPICTRL_QSPI0CLKSEL_AUXHFRCO: ret = cmuSelect_AUXHFRCO; break; case CMU_QSPICTRL_QSPI0CLKSEL_USHFRCO: ret = cmuSelect_USHFRCO; break; } break; #endif #if defined(_CMU_USBCTRL_USBCLKSEL_MASK) case CMU_USBRCLKSEL_REG: switch (CMU->USBCTRL & _CMU_USBCTRL_USBCLKSEL_MASK) { case CMU_USBCTRL_USBCLKSEL_USHFRCO: ret = cmuSelect_USHFRCO; break; case CMU_USBCTRL_USBCLKSEL_HFXO: ret = cmuSelect_HFXO; break; case CMU_USBCTRL_USBCLKSEL_HFXOX2: ret = cmuSelect_HFXOX2; break; case CMU_USBCTRL_USBCLKSEL_HFRCO: ret = cmuSelect_HFRCO; break; case CMU_USBCTRL_USBCLKSEL_LFXO: ret = cmuSelect_LFXO; break; case CMU_USBCTRL_USBCLKSEL_LFRCO: ret = cmuSelect_LFRCO; break; } break; #endif #if defined(_CMU_PDMCTRL_PDMCLKSEL_MASK) case CMU_PDMREFSEL_REG: switch (CMU->PDMCTRL & _CMU_PDMCTRL_PDMCLKSEL_MASK) { case CMU_PDMCTRL_PDMCLKSEL_USHFRCO: ret = cmuSelect_USHFRCO; break; case CMU_PDMCTRL_PDMCLKSEL_HFXO: ret = cmuSelect_HFXO; break; case CMU_PDMCTRL_PDMCLKSEL_HFRCO: ret = cmuSelect_HFRCO; break; } break; #endif default: ret = cmuSelect_Error; EFM_ASSERT(false); break; } return ret; } /***************************************************************************//** * @brief * Select the reference clock/oscillator used for a clock branch. * * @details * Notice that if a selected reference is not enabled prior to selecting its * use, it will be enabled and this function will wait for the selected * oscillator to be stable. It will however NOT be disabled if another * reference clock is selected later. * * This feature is particularly important if selecting a new reference * clock for the clock branch clocking the core. Otherwise, the system * may halt. * * @note * HFCLKLE prescaler is automatically modified when peripherals with clock * domain HFBUSCLK is chosen based on the maximum HFLE frequency allowed. * * @param[in] clock * A clock branch to select reference clock for. One of: * @li #cmuClock_HF * @li #cmuClock_LFA * @li #cmuClock_LFB * @if _CMU_LFCCLKEN0_MASK * @li #cmuClock_LFC * @endif * @if _CMU_LFECLKEN0_MASK * @li #cmuClock_LFE * @endif * @li #cmuClock_DBG * @if _CMU_CMD_USBCLKSEL_MASK * @li #cmuClock_USBC * @endif * @if _CMU_USBCTRL_MASK * @li #cmuClock_USBR * @endif * * @param[in] ref * A reference selected for clocking. See the reference manual * for details about references available for a specific clock branch. * @li #cmuSelect_HFRCO * @li #cmuSelect_LFRCO * @li #cmuSelect_HFXO * @if _CMU_HFXOCTRL_HFXOX2EN_MASK * @li #cmuSelect_HFXOX2 * @endif * @li #cmuSelect_LFXO * @li #cmuSelect_HFCLKLE * @li #cmuSelect_AUXHFRCO * @if _CMU_USHFRCOCTRL_MASK * @li #cmuSelect_USHFRCO * @endif * @li #cmuSelect_HFCLK * @ifnot DOXYDOC_EFM32_GECKO_FAMILY * @li #cmuSelect_ULFRCO * @endif ******************************************************************************/ void CMU_ClockSelectSet(CMU_Clock_TypeDef clock, CMU_Select_TypeDef ref) { uint32_t select = (uint32_t)cmuOsc_HFRCO; CMU_Osc_TypeDef osc = cmuOsc_HFRCO; uint32_t freq; uint32_t tmp; uint32_t selRegId; #if defined(_SILICON_LABS_32B_SERIES_1) volatile uint32_t *selReg = NULL; #endif #if defined(CMU_LFCLKSEL_LFAE_ULFRCO) uint32_t lfExtended = 0; #endif #if defined(_EMU_CMD_EM01VSCALE0_MASK) uint32_t vScaleFrequency = 0; /* Use default. */ /* Start voltage upscaling before the clock is set. */ if (clock == cmuClock_HF) { if (ref == cmuSelect_HFXO) { vScaleFrequency = SystemHFXOClockGet(); } else if ((ref == cmuSelect_HFRCO) && ((uint32_t)CMU_HFRCOBandGet() > CMU_VSCALEEM01_LOWPOWER_VOLTAGE_CLOCK_MAX)) { vScaleFrequency = (uint32_t)CMU_HFRCOBandGet(); } else { /* Use the default frequency. */ } if (vScaleFrequency != 0UL) { EMU_VScaleEM01ByClock(vScaleFrequency, false); } } #endif selRegId = ((unsigned)clock >> CMU_SEL_REG_POS) & CMU_SEL_REG_MASK; switch (selRegId) { case CMU_HFCLKSEL_REG: switch (ref) { case cmuSelect_LFXO: #if defined(_SILICON_LABS_32B_SERIES_1) select = CMU_HFCLKSEL_HF_LFXO; #elif defined(_SILICON_LABS_32B_SERIES_0) select = CMU_CMD_HFCLKSEL_LFXO; #endif osc = cmuOsc_LFXO; break; case cmuSelect_LFRCO: #if defined(_SILICON_LABS_32B_SERIES_1) select = CMU_HFCLKSEL_HF_LFRCO; #elif defined(_SILICON_LABS_32B_SERIES_0) select = CMU_CMD_HFCLKSEL_LFRCO; #endif osc = cmuOsc_LFRCO; break; case cmuSelect_HFXO: #if defined(CMU_HFCLKSEL_HF_HFXO) select = CMU_HFCLKSEL_HF_HFXO; #elif defined(CMU_CMD_HFCLKSEL_HFXO) select = CMU_CMD_HFCLKSEL_HFXO; #endif osc = cmuOsc_HFXO; #if defined(CMU_MAX_FREQ_HFLE) /* Set 1 HFLE wait-state until the new HFCLKLE frequency is known. This is known after 'select' is written below. */ setHfLeConfig(CMU_MAX_FREQ_HFLE + 1UL); #endif #if defined(CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ) /* Adjust HFXO buffer current for frequencies above 32 MHz. */ if (SystemHFXOClockGet() > 32000000) { CMU->CTRL = (CMU->CTRL & ~_CMU_CTRL_HFXOBUFCUR_MASK) | CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ; } else { CMU->CTRL = (CMU->CTRL & ~_CMU_CTRL_HFXOBUFCUR_MASK) | CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ; } #endif break; case cmuSelect_HFRCO: #if defined(_SILICON_LABS_32B_SERIES_1) select = CMU_HFCLKSEL_HF_HFRCO; #elif defined(_SILICON_LABS_32B_SERIES_0) select = CMU_CMD_HFCLKSEL_HFRCO; #endif osc = cmuOsc_HFRCO; #if defined(CMU_MAX_FREQ_HFLE) /* Set 1 HFLE wait-state until the new HFCLKLE frequency is known. This is known after 'select' is written below. */ setHfLeConfig(CMU_MAX_FREQ_HFLE + 1UL); #endif break; #if defined(CMU_CMD_HFCLKSEL_USHFRCODIV2) case cmuSelect_USHFRCODIV2: select = CMU_CMD_HFCLKSEL_USHFRCODIV2; osc = cmuOsc_USHFRCO; break; #endif #if defined(CMU_HFCLKSTATUS_SELECTED_HFRCODIV2) case cmuSelect_HFRCODIV2: select = CMU_HFCLKSEL_HF_HFRCODIV2; osc = cmuOsc_HFRCO; break; #endif #if defined(CMU_HFCLKSTATUS_SELECTED_CLKIN0) case cmuSelect_CLKIN0: select = CMU_HFCLKSEL_HF_CLKIN0; osc = cmuOsc_CLKIN0; break; #endif #if defined(CMU_HFCLKSTATUS_SELECTED_USHFRCO) case cmuSelect_USHFRCO: select = CMU_HFCLKSEL_HF_USHFRCO; osc = cmuOsc_USHFRCO; break; #endif #if defined(CMU_LFCLKSEL_LFAE_ULFRCO) || defined(CMU_LFACLKSEL_LFA_ULFRCO) case cmuSelect_ULFRCO: /* ULFRCO cannot be used as HFCLK. */ EFM_ASSERT(false); return; #endif default: EFM_ASSERT(false); return; } /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ #if defined(CMU_HFCLKSTATUS_SELECTED_CLKIN0) if (osc != cmuOsc_CLKIN0) { CMU_OscillatorEnable(osc, true, true); } #else CMU_OscillatorEnable(osc, true, true); #endif /* Configure worst case wait-states for flash and set safe HFPER clock-tree prescalers. */ flashWaitStateMax(); hfperClkSafePrescaler(); #if defined(_EMU_CMD_EM01VSCALE0_MASK) /* Wait for voltage upscaling to complete before the clock is set. */ if (vScaleFrequency != 0UL) { EMU_VScaleWait(); } #endif /* Switch to the selected oscillator. */ #if defined(_CMU_HFCLKSEL_MASK) CMU->HFCLKSEL = select; #else CMU->CMD = select; #endif #if defined(CMU_MAX_FREQ_HFLE) /* Update the HFLE configuration after 'select' is set. Note that the HFCLKLE clock is connected differently on platforms 1 and 2. */ setHfLeConfig(CMU_ClockFreqGet(cmuClock_HFLE)); #endif /* Update the CMSIS core clock variable. */ /* (The function will update the global variable). */ freq = SystemCoreClockGet(); /* Optimize flash access wait state setting for the currently selected core clk. */ CMU_UpdateWaitStates(freq, (int)VSCALE_DEFAULT); #if defined(_EMU_CMD_EM01VSCALE0_MASK) /* Keep EMU module informed on the source HF clock frequency. This will apply voltage downscaling after clock is set if downscaling is configured. */ if (vScaleFrequency == 0UL) { EMU_VScaleEM01ByClock(0, true); } #endif /* Set optimized HFPER clock-tree prescalers. */ hfperClkOptimizedPrescaler(); break; #if defined(_SILICON_LABS_32B_SERIES_1) case CMU_LFACLKSEL_REG: selReg = &CMU->LFACLKSEL; #if !defined(_CMU_LFACLKSEL_LFA_HFCLKLE) /* HFCLKCLE can't be used as LFACLK. */ EFM_ASSERT(ref != cmuSelect_HFCLKLE); #endif SL_FALLTHROUGH /* Fall through and select the clock source. */ #if defined(_CMU_LFCCLKSEL_MASK) case CMU_LFCCLKSEL_REG: selReg = (selReg == NULL) ? &CMU->LFCCLKSEL : selReg; #if !defined(_CMU_LFCCLKSEL_LFC_HFCLKLE) /* HFCLKCLE can't be used as LFCCLK. */ EFM_ASSERT(ref != cmuSelect_HFCLKLE); #endif SL_FALLTHROUGH #endif /* Fall through and select the clock source. */ case CMU_LFECLKSEL_REG: selReg = (selReg == NULL) ? &CMU->LFECLKSEL : selReg; #if !defined(_CMU_LFECLKSEL_LFE_HFCLKLE) /* HFCLKCLE can't be used as LFECLK. */ EFM_ASSERT(ref != cmuSelect_HFCLKLE); #endif SL_FALLTHROUGH /* Fall through and select the clock source. */ case CMU_LFBCLKSEL_REG: selReg = (selReg == NULL) ? &CMU->LFBCLKSEL : selReg; switch (ref) { case cmuSelect_Disabled: tmp = _CMU_LFACLKSEL_LFA_DISABLED; break; case cmuSelect_LFXO: /* Ensure that thes elected oscillator is enabled, waiting for it to stabilize. */ CMU_OscillatorEnable(cmuOsc_LFXO, true, true); tmp = _CMU_LFACLKSEL_LFA_LFXO; break; case cmuSelect_LFRCO: /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); tmp = _CMU_LFACLKSEL_LFA_LFRCO; break; case cmuSelect_HFCLKLE: /* Ensure the correct HFLE wait-states and enable HFCLK to LE.*/ setHfLeConfig(SystemCoreClockGet()); BUS_RegBitWrite(&CMU->HFBUSCLKEN0, _CMU_HFBUSCLKEN0_LE_SHIFT, 1); tmp = _CMU_LFBCLKSEL_LFB_HFCLKLE; break; case cmuSelect_ULFRCO: /* ULFRCO is always on, there is no need to enable it. */ tmp = _CMU_LFACLKSEL_LFA_ULFRCO; break; default: EFM_ASSERT(false); return; } *selReg = tmp; break; #elif defined(_SILICON_LABS_32B_SERIES_0) case CMU_LFACLKSEL_REG: case CMU_LFBCLKSEL_REG: switch (ref) { case cmuSelect_Disabled: tmp = _CMU_LFCLKSEL_LFA_DISABLED; break; case cmuSelect_LFXO: /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ CMU_OscillatorEnable(cmuOsc_LFXO, true, true); tmp = _CMU_LFCLKSEL_LFA_LFXO; break; case cmuSelect_LFRCO: /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); tmp = _CMU_LFCLKSEL_LFA_LFRCO; break; case cmuSelect_HFCLKLE: #if defined(CMU_MAX_FREQ_HFLE) /* Set the HFLE wait-state and divider. */ freq = SystemCoreClockGet(); setHfLeConfig(freq); #endif /* Ensure HFCORE to LE clocking is enabled. */ BUS_RegBitWrite(&CMU->HFCORECLKEN0, _CMU_HFCORECLKEN0_LE_SHIFT, 1); tmp = _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2; break; #if defined(CMU_LFCLKSEL_LFAE_ULFRCO) case cmuSelect_ULFRCO: /* ULFRCO is always enabled. */ tmp = _CMU_LFCLKSEL_LFA_DISABLED; lfExtended = 1; break; #endif default: /* An illegal clock source for LFA/LFB selected. */ EFM_ASSERT(false); return; } /* Apply select. */ if (selRegId == CMU_LFACLKSEL_REG) { #if defined(_CMU_LFCLKSEL_LFAE_MASK) CMU->LFCLKSEL = (CMU->LFCLKSEL & ~(_CMU_LFCLKSEL_LFA_MASK | _CMU_LFCLKSEL_LFAE_MASK)) | (tmp << _CMU_LFCLKSEL_LFA_SHIFT) | (lfExtended << _CMU_LFCLKSEL_LFAE_SHIFT); #else CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFA_MASK) | (tmp << _CMU_LFCLKSEL_LFA_SHIFT); #endif } else { #if defined(_CMU_LFCLKSEL_LFBE_MASK) CMU->LFCLKSEL = (CMU->LFCLKSEL & ~(_CMU_LFCLKSEL_LFB_MASK | _CMU_LFCLKSEL_LFBE_MASK)) | (tmp << _CMU_LFCLKSEL_LFB_SHIFT) | (lfExtended << _CMU_LFCLKSEL_LFBE_SHIFT); #else CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFB_MASK) | (tmp << _CMU_LFCLKSEL_LFB_SHIFT); #endif } break; #if defined(_CMU_LFCLKSEL_LFC_MASK) case CMU_LFCCLKSEL_REG: switch (ref) { case cmuSelect_Disabled: tmp = _CMU_LFCLKSEL_LFA_DISABLED; break; case cmuSelect_LFXO: /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ CMU_OscillatorEnable(cmuOsc_LFXO, true, true); tmp = _CMU_LFCLKSEL_LFC_LFXO; break; case cmuSelect_LFRCO: /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); tmp = _CMU_LFCLKSEL_LFC_LFRCO; break; default: /* An illegal clock source for LFC selected. */ EFM_ASSERT(false); return; } /* Apply select. */ CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFC_MASK) | (tmp << _CMU_LFCLKSEL_LFC_SHIFT); break; #endif #endif #if defined(_CMU_DBGCLKSEL_DBG_MASK) || defined(CMU_CTRL_DBGCLK) case CMU_DBGCLKSEL_REG: switch (ref) { #if defined(_CMU_DBGCLKSEL_DBG_MASK) case cmuSelect_AUXHFRCO: /* Select AUXHFRCO as a debug clock. */ CMU->DBGCLKSEL = CMU_DBGCLKSEL_DBG_AUXHFRCO; break; case cmuSelect_HFCLK: /* Select divided HFCLK as a debug clock. */ CMU->DBGCLKSEL = CMU_DBGCLKSEL_DBG_HFCLK; break; #endif #if defined(CMU_CTRL_DBGCLK) case cmuSelect_AUXHFRCO: /* Select AUXHFRCO as a debug clock. */ CMU->CTRL = (CMU->CTRL & ~(_CMU_CTRL_DBGCLK_MASK)) | CMU_CTRL_DBGCLK_AUXHFRCO; break; case cmuSelect_HFCLK: /* Select divided HFCLK as a debug clock. */ CMU->CTRL = (CMU->CTRL & ~(_CMU_CTRL_DBGCLK_MASK)) | CMU_CTRL_DBGCLK_HFCLK; break; #endif default: /* An illegal clock source for debug selected. */ EFM_ASSERT(false); return; } break; #endif #if defined(USBC_CLOCK_PRESENT) case CMU_USBCCLKSEL_REG: switch (ref) { case cmuSelect_LFXO: /* Select LFXO as a clock source for USB. It can only be used in sleep mode. */ /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ CMU_OscillatorEnable(cmuOsc_LFXO, true, true); /* Switch the oscillator. */ CMU->CMD = CMU_CMD_USBCCLKSEL_LFXO; /* Wait until the clock is activated. */ while ((CMU->STATUS & CMU_STATUS_USBCLFXOSEL) == 0) { } break; case cmuSelect_LFRCO: /* Select LFRCO as a clock source for USB. It can only be used in sleep mode. */ /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); /* Switch the oscillator. */ CMU->CMD = CMU_CMD_USBCCLKSEL_LFRCO; /* Wait until the clock is activated. */ while ((CMU->STATUS & CMU_STATUS_USBCLFRCOSEL) == 0) { } break; #if defined(CMU_STATUS_USBCHFCLKSEL) case cmuSelect_HFCLK: /* Select undivided HFCLK as a clock source for USB. */ /* The oscillator must already be enabled to avoid a core lockup. */ CMU->CMD = CMU_CMD_USBCCLKSEL_HFCLKNODIV; /* Wait until the clock is activated. */ while ((CMU->STATUS & CMU_STATUS_USBCHFCLKSEL) == 0) { } break; #endif #if defined(CMU_CMD_USBCCLKSEL_USHFRCO) case cmuSelect_USHFRCO: /* Select USHFRCO as a clock source for USB. */ /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ CMU_OscillatorEnable(cmuOsc_USHFRCO, true, true); /* Switch the oscillator. */ CMU->CMD = CMU_CMD_USBCCLKSEL_USHFRCO; /* Wait until the clock is activated. */ while ((CMU->STATUS & CMU_STATUS_USBCUSHFRCOSEL) == 0) { } break; #endif default: /* An illegal clock source for USB. */ EFM_ASSERT(false); return; } break; #endif #if defined(_CMU_ADCCTRL_ADC0CLKSEL_MASK) case CMU_ADC0ASYNCSEL_REG: switch (ref) { case cmuSelect_Disabled: tmp = _CMU_ADCCTRL_ADC0CLKSEL_DISABLED; break; case cmuSelect_AUXHFRCO: /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ CMU_OscillatorEnable(cmuOsc_AUXHFRCO, true, true); tmp = _CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO; break; case cmuSelect_HFXO: /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ CMU_OscillatorEnable(cmuOsc_HFXO, true, true); tmp = _CMU_ADCCTRL_ADC0CLKSEL_HFXO; break; case cmuSelect_HFSRCCLK: tmp = _CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK; break; default: /* An illegal clock source for ADC0ASYNC selected. */ EFM_ASSERT(false); return; } /* Apply select. */ CMU->ADCCTRL = (CMU->ADCCTRL & ~_CMU_ADCCTRL_ADC0CLKSEL_MASK) | (tmp << _CMU_ADCCTRL_ADC0CLKSEL_SHIFT); break; #endif #if defined(_CMU_ADCCTRL_ADC1CLKSEL_MASK) case CMU_ADC1ASYNCSEL_REG: switch (ref) { case cmuSelect_Disabled: tmp = _CMU_ADCCTRL_ADC1CLKSEL_DISABLED; break; case cmuSelect_AUXHFRCO: /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ CMU_OscillatorEnable(cmuOsc_AUXHFRCO, true, true); tmp = _CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO; break; case cmuSelect_HFXO: /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ CMU_OscillatorEnable(cmuOsc_HFXO, true, true); tmp = _CMU_ADCCTRL_ADC1CLKSEL_HFXO; break; case cmuSelect_HFSRCCLK: tmp = _CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK; break; default: /* An illegal clock source for ADC1ASYNC selected. */ EFM_ASSERT(false); return; } /* Apply select. */ CMU->ADCCTRL = (CMU->ADCCTRL & ~_CMU_ADCCTRL_ADC1CLKSEL_MASK) | (tmp << _CMU_ADCCTRL_ADC1CLKSEL_SHIFT); break; #endif #if defined(_CMU_SDIOCTRL_SDIOCLKSEL_MASK) case CMU_SDIOREFSEL_REG: switch (ref) { case cmuSelect_HFRCO: /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ CMU_OscillatorEnable(cmuOsc_HFRCO, true, true); tmp = _CMU_SDIOCTRL_SDIOCLKSEL_HFRCO; break; case cmuSelect_HFXO: /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ CMU_OscillatorEnable(cmuOsc_HFXO, true, true); tmp = _CMU_SDIOCTRL_SDIOCLKSEL_HFXO; break; case cmuSelect_AUXHFRCO: /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ CMU_OscillatorEnable(cmuOsc_AUXHFRCO, true, true); tmp = _CMU_SDIOCTRL_SDIOCLKSEL_AUXHFRCO; break; case cmuSelect_USHFRCO: /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ CMU_OscillatorEnable(cmuOsc_USHFRCO, true, true); tmp = _CMU_SDIOCTRL_SDIOCLKSEL_USHFRCO; break; default: /* An illegal clock source for SDIOREF selected. */ EFM_ASSERT(false); return; } /* Apply select. */ CMU->SDIOCTRL = (CMU->SDIOCTRL & ~_CMU_SDIOCTRL_SDIOCLKSEL_MASK) | (tmp << _CMU_SDIOCTRL_SDIOCLKSEL_SHIFT); break; #endif #if defined(_CMU_QSPICTRL_QSPI0CLKSEL_MASK) case CMU_QSPI0REFSEL_REG: switch (ref) { case cmuSelect_HFRCO: /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ CMU_OscillatorEnable(cmuOsc_HFRCO, true, true); tmp = _CMU_QSPICTRL_QSPI0CLKSEL_HFRCO; break; case cmuSelect_HFXO: /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ CMU_OscillatorEnable(cmuOsc_HFXO, true, true); tmp = _CMU_QSPICTRL_QSPI0CLKSEL_HFXO; break; case cmuSelect_AUXHFRCO: /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ CMU_OscillatorEnable(cmuOsc_AUXHFRCO, true, true); tmp = _CMU_QSPICTRL_QSPI0CLKSEL_AUXHFRCO; break; case cmuSelect_USHFRCO: /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ CMU_OscillatorEnable(cmuOsc_USHFRCO, true, true); tmp = _CMU_QSPICTRL_QSPI0CLKSEL_USHFRCO; break; default: /* An illegal clock source for QSPI0REF selected. */ EFM_ASSERT(false); return; } /* Apply select. */ CMU->QSPICTRL = (CMU->QSPICTRL & ~_CMU_QSPICTRL_QSPI0CLKSEL_MASK) | (tmp << _CMU_QSPICTRL_QSPI0CLKSEL_SHIFT); break; #endif #if defined(_CMU_USBCTRL_USBCLKSEL_MASK) case CMU_USBRCLKSEL_REG: switch (ref) { case cmuSelect_USHFRCO: /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ CMU_OscillatorEnable(cmuOsc_USHFRCO, true, true); tmp = _CMU_USBCTRL_USBCLKSEL_USHFRCO; break; case cmuSelect_HFXO: /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ CMU_OscillatorEnable(cmuOsc_HFXO, true, true); tmp = _CMU_USBCTRL_USBCLKSEL_HFXO; break; case cmuSelect_HFXOX2: /* Only allowed for HFXO frequencies up to 25 MHz. */ EFM_ASSERT(SystemHFXOClockGet() <= 25000000u); /* Enable HFXO X2. */ CMU->HFXOCTRL |= CMU_HFXOCTRL_HFXOX2EN; /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ CMU_OscillatorEnable(cmuOsc_HFXO, true, true); tmp = _CMU_USBCTRL_USBCLKSEL_HFXOX2; break; case cmuSelect_HFRCO: /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ CMU_OscillatorEnable(cmuOsc_HFRCO, true, true); tmp = _CMU_USBCTRL_USBCLKSEL_HFRCO; break; case cmuSelect_LFXO: /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ CMU_OscillatorEnable(cmuOsc_LFXO, true, true); tmp = _CMU_USBCTRL_USBCLKSEL_LFXO; break; case cmuSelect_LFRCO: /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); tmp = _CMU_USBCTRL_USBCLKSEL_LFRCO; break; default: /* An illegal clock source for USBR selected. */ EFM_ASSERT(false); return; } /* Apply select. */ CMU->USBCTRL = (CMU->USBCTRL & ~_CMU_USBCTRL_USBCLKSEL_MASK) | (tmp << _CMU_USBCTRL_USBCLKSEL_SHIFT); break; #endif #if defined(_CMU_PDMCTRL_PDMCLKSEL_MASK) case CMU_PDMREFSEL_REG: switch (ref) { case cmuSelect_USHFRCO: /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ CMU_OscillatorEnable(cmuOsc_USHFRCO, true, true); tmp = _CMU_PDMCTRL_PDMCLKSEL_USHFRCO; break; case cmuSelect_HFXO: /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ CMU_OscillatorEnable(cmuOsc_HFXO, true, true); tmp = _CMU_PDMCTRL_PDMCLKSEL_HFXO; break; case cmuSelect_HFRCO: /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ CMU_OscillatorEnable(cmuOsc_HFRCO, true, true); tmp = _CMU_PDMCTRL_PDMCLKSEL_HFRCO; break; default: /* An illegal clock source for PDMREF selected. */ EFM_ASSERT(false); return; } /* Apply select. */ CMU->PDMCTRL = (CMU->PDMCTRL & ~_CMU_PDMCTRL_PDMCLKSEL_MASK) | (tmp << _CMU_PDMCTRL_PDMCLKSEL_SHIFT); break; #endif default: EFM_ASSERT(false); break; } } #if defined(CMU_OSCENCMD_DPLLEN) /**************************************************************************//** * @brief * Lock the DPLL to a given frequency. * * The frequency is given by: Fout = Fref * (N+1) / (M+1). * * @note * This function does not check if the given N & M values will actually * produce the desired target frequency. @n * N & M limitations: @n * 300 < N <= 4095 @n * 0 <= M <= 4095 @n * Any peripheral running off HFRCO should be switched to HFRCODIV2 prior to * calling this function to avoid over-clocking. * * HFCLKLE prescaler is automatically modified before updating HFRCO * based on the maximum HFLE frequency allowed. * * @param[in] init * DPLL setup parameters. * * @return * Returns false on invalid target frequency or DPLL locking error. *****************************************************************************/ bool CMU_DPLLLock(const CMU_DPLLInit_TypeDef *init) { int index = 0; unsigned int i; bool hfrcoDiv2override = false; uint32_t hfrcoCtrlVal, lockStatus, sysFreq; EFM_ASSERT(init->frequency >= hfrcoCtrlTable[0].minFreq); EFM_ASSERT(init->frequency <= hfrcoCtrlTable[HFRCOCTRLTABLE_ENTRIES - 1U].maxFreq); EFM_ASSERT(init->n > 300U); EFM_ASSERT(init->n <= (_CMU_DPLLCTRL1_N_MASK >> _CMU_DPLLCTRL1_N_SHIFT)); EFM_ASSERT(init->m <= (_CMU_DPLLCTRL1_M_MASK >> _CMU_DPLLCTRL1_M_SHIFT)); EFM_ASSERT(init->ssInterval <= (_CMU_HFRCOSS_SSINV_MASK >> _CMU_HFRCOSS_SSINV_SHIFT)); EFM_ASSERT(init->ssAmplitude <= (_CMU_HFRCOSS_SSAMP_MASK >> _CMU_HFRCOSS_SSAMP_SHIFT)); #if defined(_EMU_STATUS_VSCALE_MASK) if ((EMU_VScaleGet() == emuVScaleEM01_LowPower) && (init->frequency > CMU_VSCALEEM01_LOWPOWER_VOLTAGE_CLOCK_MAX)) { EFM_ASSERT(false); return false; } #endif // Find the correct HFRCO band and retrieve a HFRCOCTRL value. for (i = 0; i < HFRCOCTRLTABLE_ENTRIES; i++) { if ((init->frequency >= hfrcoCtrlTable[i].minFreq) && (init->frequency <= hfrcoCtrlTable[i].maxFreq)) { index = (int)i; // Correct band found break; } } if ((uint32_t)index == HFRCOCTRLTABLE_ENTRIES) { EFM_ASSERT(false); return false; // Target frequency out of spec. } hfrcoCtrlVal = hfrcoCtrlTable[index].value; // Check if a calibrated HFRCOCTRL.TUNING value is in device DI page. if (hfrcoCtrlTable[index].band != (CMU_HFRCOFreq_TypeDef)0) { uint32_t tuning; tuning = (CMU_HFRCODevinfoGet(hfrcoCtrlTable[index].band) & _CMU_HFRCOCTRL_TUNING_MASK) >> _CMU_HFRCOCTRL_TUNING_SHIFT; // When HFRCOCTRL.FINETUNINGEN is enabled, the center frequency // of the band shifts down by 5.8%. 9 is subtracted to compensate. if (tuning > 9UL) { tuning -= 9UL; } else { tuning = 0UL; } hfrcoCtrlVal |= tuning << _CMU_HFRCOCTRL_TUNING_SHIFT; } // Update the CMSIS frequency SystemHfrcoFreq value. SystemHfrcoFreq = init->frequency; // Set maximum wait-states while changing the core clock. if (CMU_ClockSelectGet(cmuClock_HF) == cmuSelect_HFRCO) { flashWaitStateMax(); } // Update the HFLE configuration before updating HFRCO, use new DPLL frequency. if (CMU_ClockSelectGet(cmuClock_HF) == cmuSelect_HFRCO) { setHfLeConfig(init->frequency); // Switch to HFRCO/2 before setting DPLL to avoid over-clocking. hfrcoDiv2override = true; CMU->HFCLKSEL = CMU_HFCLKSEL_HF_HFRCODIV2; } CMU->OSCENCMD = CMU_OSCENCMD_DPLLDIS; while ((CMU->STATUS & (CMU_STATUS_DPLLENS | CMU_STATUS_DPLLRDY)) != 0UL) { } CMU->IFC = CMU_IFC_DPLLRDY | CMU_IFC_DPLLLOCKFAILLOW | CMU_IFC_DPLLLOCKFAILHIGH; CMU->DPLLCTRL1 = ((uint32_t)init->n << _CMU_DPLLCTRL1_N_SHIFT) | ((uint32_t)init->m << _CMU_DPLLCTRL1_M_SHIFT); CMU->HFRCOCTRL = hfrcoCtrlVal; CMU->DPLLCTRL = ((uint32_t)init->refClk << _CMU_DPLLCTRL_REFSEL_SHIFT) | ((init->autoRecover ? 1UL : 0UL) << _CMU_DPLLCTRL_AUTORECOVER_SHIFT) | ((uint32_t)init->edgeSel << _CMU_DPLLCTRL_EDGESEL_SHIFT) | ((uint32_t)init->lockMode << _CMU_DPLLCTRL_MODE_SHIFT); CMU->OSCENCMD = CMU_OSCENCMD_DPLLEN; while ((lockStatus = (CMU->IF & (CMU_IF_DPLLRDY | CMU_IF_DPLLLOCKFAILLOW | CMU_IF_DPLLLOCKFAILHIGH))) == 0UL) { } // Restore to HFRCO if ((CMU_ClockSelectGet(cmuClock_HF) == cmuSelect_HFRCODIV2) && (hfrcoDiv2override == true)) { CMU->HFCLKSEL = CMU_HFCLKSEL_HF_HFRCO; } // If HFRCO is selected as an HF clock, optimize the flash access wait-state // configuration for this frequency and update the CMSIS core clock variable. if (CMU_ClockSelectGet(cmuClock_HF) == cmuSelect_HFRCO) { // Call @ref SystemCoreClockGet() to update the CMSIS core clock variable. sysFreq = SystemCoreClockGet(); EFM_ASSERT(sysFreq <= init->frequency); EFM_ASSERT(sysFreq <= SystemHfrcoFreq); EFM_ASSERT(init->frequency == SystemHfrcoFreq); CMU_UpdateWaitStates(sysFreq, (int)VSCALE_DEFAULT); } // Reduce HFLE frequency if possible. setHfLeConfig(CMU_ClockFreqGet(cmuClock_HFLE)); #if defined(_EMU_CMD_EM01VSCALE0_MASK) // Update voltage scaling. EMU_VScaleEM01ByClock(0, true); #endif if (lockStatus == CMU_IF_DPLLRDY) { return true; } return false; } #endif // CMU_OSCENCMD_DPLLEN /**************************************************************************//** * @brief * CMU low frequency register synchronization freeze control. * * @details * Some CMU registers require synchronization into the low-frequency (LF) * domain. The freeze feature allows for several such registers to be * modified before passing them to the LF domain simultaneously (which * takes place when the freeze mode is disabled). * * Another use case for this feature is using an API (such * as the CMU API) for modifying several bit fields consecutively in the * same register. If freeze mode is enabled during this sequence, stalling * can be avoided. * * @note * When enabling freeze mode, this function will wait for all current * ongoing CMU synchronization to LF domain to complete (normally * synchronization will not be in progress.) However, for this reason, when * using freeze mode, modifications of registers requiring LF synchronization * should be done within one freeze enable/disable block to avoid unnecessary * stalling. * * @param[in] enable * @li true - enable freeze, modified registers are not propagated to the * LF domain * @li false - disable freeze, modified registers are propagated to the LF * domain *****************************************************************************/ void CMU_FreezeEnable(bool enable) { if (enable) { /* Wait for any ongoing LF synchronizations to complete. This */ /* protects against the rare case when a user */ /* - modifies a register requiring LF sync */ /* - then enables freeze before LF sync completed */ /* - then modifies the same register again */ /* since modifying a register while it is in sync progress should be */ /* avoided. */ while (CMU->SYNCBUSY != 0UL) { } CMU->FREEZE = CMU_FREEZE_REGFREEZE; } else { CMU->FREEZE = 0; } } #if defined(_CMU_HFRCOCTRL_BAND_MASK) /***************************************************************************//** * @brief * Get HFRCO band in use. * * @return * HFRCO band in use. ******************************************************************************/ CMU_HFRCOBand_TypeDef CMU_HFRCOBandGet(void) { return (CMU_HFRCOBand_TypeDef)((CMU->HFRCOCTRL & _CMU_HFRCOCTRL_BAND_MASK) >> _CMU_HFRCOCTRL_BAND_SHIFT); } #endif /* _CMU_HFRCOCTRL_BAND_MASK */ #if defined(_CMU_HFRCOCTRL_BAND_MASK) /***************************************************************************//** * @brief * Set HFRCO band and the tuning value based on the value in the calibration * table made during production. * * @note * HFCLKLE prescaler is automatically modified based on the maximum * HFLE frequency allowed. * * @param[in] band * HFRCO band to activate. ******************************************************************************/ void CMU_HFRCOBandSet(CMU_HFRCOBand_TypeDef band) { uint32_t tuning; uint32_t freq; CMU_Select_TypeDef osc; /* Read the tuning value from the calibration table. */ switch (band) { case cmuHFRCOBand_1MHz: tuning = (DEVINFO->HFRCOCAL0 & _DEVINFO_HFRCOCAL0_BAND1_MASK) >> _DEVINFO_HFRCOCAL0_BAND1_SHIFT; break; case cmuHFRCOBand_7MHz: tuning = (DEVINFO->HFRCOCAL0 & _DEVINFO_HFRCOCAL0_BAND7_MASK) >> _DEVINFO_HFRCOCAL0_BAND7_SHIFT; break; case cmuHFRCOBand_11MHz: tuning = (DEVINFO->HFRCOCAL0 & _DEVINFO_HFRCOCAL0_BAND11_MASK) >> _DEVINFO_HFRCOCAL0_BAND11_SHIFT; break; case cmuHFRCOBand_14MHz: tuning = (DEVINFO->HFRCOCAL0 & _DEVINFO_HFRCOCAL0_BAND14_MASK) >> _DEVINFO_HFRCOCAL0_BAND14_SHIFT; break; case cmuHFRCOBand_21MHz: tuning = (DEVINFO->HFRCOCAL1 & _DEVINFO_HFRCOCAL1_BAND21_MASK) >> _DEVINFO_HFRCOCAL1_BAND21_SHIFT; break; #if defined(_CMU_HFRCOCTRL_BAND_28MHZ) case cmuHFRCOBand_28MHz: tuning = (DEVINFO->HFRCOCAL1 & _DEVINFO_HFRCOCAL1_BAND28_MASK) >> _DEVINFO_HFRCOCAL1_BAND28_SHIFT; break; #endif default: EFM_ASSERT(false); return; } /* If HFRCO is used for the core clock, flash access WS has to be considered. */ osc = CMU_ClockSelectGet(cmuClock_HF); if (osc == cmuSelect_HFRCO) { /* Configure worst case wait states for flash access before setting the divider. */ flashWaitStateMax(); } /* Set band/tuning. */ CMU->HFRCOCTRL = (CMU->HFRCOCTRL & ~(_CMU_HFRCOCTRL_BAND_MASK | _CMU_HFRCOCTRL_TUNING_MASK)) | (band << _CMU_HFRCOCTRL_BAND_SHIFT) | (tuning << _CMU_HFRCOCTRL_TUNING_SHIFT); /* If HFRCO is used for the core clock, optimize flash WS. */ if (osc == cmuSelect_HFRCO) { /* Call @ref SystemCoreClockGet() to update the CMSIS core clock variable. */ freq = SystemCoreClockGet(); CMU_UpdateWaitStates(freq, (int)VSCALE_DEFAULT); } #if defined(CMU_MAX_FREQ_HFLE) /* Reduce HFLE frequency if possible. */ setHfLeConfig(CMU_ClockFreqGet(cmuClock_HFLE)); #endif } #endif /* _CMU_HFRCOCTRL_BAND_MASK */ #if defined(_CMU_HFRCOCTRL_FREQRANGE_MASK) /**************************************************************************//** * @brief * Get the HFRCO frequency calibration word in DEVINFO. * * @param[in] freq * Frequency in Hz. * * @return * HFRCO calibration word for a given frequency. *****************************************************************************/ static uint32_t CMU_HFRCODevinfoGet(CMU_HFRCOFreq_TypeDef freq) { switch (freq) { /* 1, 2, and 4 MHz share the same calibration word. */ case cmuHFRCOFreq_1M0Hz: case cmuHFRCOFreq_2M0Hz: case cmuHFRCOFreq_4M0Hz: return DEVINFO->HFRCOCAL0; case cmuHFRCOFreq_7M0Hz: return DEVINFO->HFRCOCAL3; case cmuHFRCOFreq_13M0Hz: return DEVINFO->HFRCOCAL6; case cmuHFRCOFreq_16M0Hz: return DEVINFO->HFRCOCAL7; case cmuHFRCOFreq_19M0Hz: return DEVINFO->HFRCOCAL8; case cmuHFRCOFreq_26M0Hz: return DEVINFO->HFRCOCAL10; case cmuHFRCOFreq_32M0Hz: return DEVINFO->HFRCOCAL11; case cmuHFRCOFreq_38M0Hz: return DEVINFO->HFRCOCAL12; #if defined(_DEVINFO_HFRCOCAL13_MASK) case cmuHFRCOFreq_48M0Hz: return DEVINFO->HFRCOCAL13; #endif #if defined(_DEVINFO_HFRCOCAL14_MASK) case cmuHFRCOFreq_56M0Hz: return DEVINFO->HFRCOCAL14; #endif #if defined(_DEVINFO_HFRCOCAL15_MASK) case cmuHFRCOFreq_64M0Hz: return DEVINFO->HFRCOCAL15; #endif #if defined(_DEVINFO_HFRCOCAL16_MASK) case cmuHFRCOFreq_72M0Hz: return DEVINFO->HFRCOCAL16; #endif default: /* cmuHFRCOFreq_UserDefined */ return 0; } } /***************************************************************************//** * @brief * Get the current HFRCO frequency. * * @return * HFRCO frequency. ******************************************************************************/ CMU_HFRCOFreq_TypeDef CMU_HFRCOBandGet(void) { return (CMU_HFRCOFreq_TypeDef)SystemHfrcoFreq; } /***************************************************************************//** * @brief * Set the HFRCO calibration for the selected target frequency. * * @note * HFCLKLE prescaler is automatically modified based on the maximum * HFLE frequency allowed. * * @param[in] setFreq * HFRCO frequency to set. ******************************************************************************/ void CMU_HFRCOBandSet(CMU_HFRCOFreq_TypeDef setFreq) { uint32_t freqCal; uint32_t sysFreq; uint32_t prevFreq; /* Get the DEVINFO index and set the CMSIS frequency SystemHfrcoFreq. */ freqCal = CMU_HFRCODevinfoGet(setFreq); EFM_ASSERT((freqCal != 0UL) && (freqCal != UINT_MAX)); prevFreq = SystemHfrcoFreq; SystemHfrcoFreq = (uint32_t)setFreq; /* Set maximum wait-states and set safe HFPER clock-tree prescalers while changing the core clock. */ if (CMU_ClockSelectGet(cmuClock_HF) == cmuSelect_HFRCO) { flashWaitStateMax(); hfperClkSafePrescaler(); } /* Wait for any previous sync to complete and set calibration data for the selected frequency. */ while (BUS_RegBitRead(&CMU->SYNCBUSY, _CMU_SYNCBUSY_HFRCOBSY_SHIFT) != 0UL) { } /* Check for valid calibration data. */ EFM_ASSERT(freqCal != UINT_MAX); /* Set divider in HFRCOCTRL for 1, 2, and 4 MHz. */ switch (setFreq) { case cmuHFRCOFreq_1M0Hz: freqCal = (freqCal & ~_CMU_HFRCOCTRL_CLKDIV_MASK) | CMU_HFRCOCTRL_CLKDIV_DIV4; break; case cmuHFRCOFreq_2M0Hz: freqCal = (freqCal & ~_CMU_HFRCOCTRL_CLKDIV_MASK) | CMU_HFRCOCTRL_CLKDIV_DIV2; break; case cmuHFRCOFreq_4M0Hz: freqCal = (freqCal & ~_CMU_HFRCOCTRL_CLKDIV_MASK) | CMU_HFRCOCTRL_CLKDIV_DIV1; break; default: break; } /* Update HFLE configuration before updating HFRCO. Use the new set frequency. */ if (CMU_ClockSelectGet(cmuClock_HF) == cmuSelect_HFRCO) { /* setFreq is worst-case as dividers may reduce the HFLE frequency. */ setHfLeConfig((uint32_t)setFreq); } if ((uint32_t)setFreq > prevFreq) { #if defined(_EMU_CMD_EM01VSCALE0_MASK) /* When increasing frequency voltage scale must be done before the change. */ EMU_VScaleEM01ByClock((uint32_t)setFreq, true); #endif } CMU->HFRCOCTRL = freqCal; /* If HFRCO is selected as an HF clock, optimize the flash access wait-state configuration for this frequency and update the CMSIS core clock variable. */ if (CMU_ClockSelectGet(cmuClock_HF) == cmuSelect_HFRCO) { /* Call @ref SystemCoreClockGet() to update the CMSIS core clock variable. */ sysFreq = SystemCoreClockGet(); EFM_ASSERT(sysFreq <= (uint32_t)setFreq); EFM_ASSERT(sysFreq <= SystemHfrcoFreq); EFM_ASSERT((uint32_t)setFreq == SystemHfrcoFreq); CMU_UpdateWaitStates(sysFreq, (int)VSCALE_DEFAULT); } /* Reduce HFLE frequency if possible. */ setHfLeConfig(CMU_ClockFreqGet(cmuClock_HFLE)); if ((uint32_t)setFreq <= prevFreq) { #if defined(_EMU_CMD_EM01VSCALE0_MASK) /* When decreasing frequency voltage scale must be done after the change */ EMU_VScaleEM01ByClock(0, true); #endif } if (CMU_ClockSelectGet(cmuClock_HF) == cmuSelect_HFRCO) { /* Set optimized HFPER clock-tree prescalers. */ hfperClkOptimizedPrescaler(); } } #endif /* _CMU_HFRCOCTRL_FREQRANGE_MASK */ #if defined(_CMU_HFRCOCTRL_SUDELAY_MASK) /***************************************************************************//** * @brief * Get the HFRCO startup delay. * * @details * See the reference manual for more details. * * @return * The startup delay in use. ******************************************************************************/ uint32_t CMU_HFRCOStartupDelayGet(void) { return (CMU->HFRCOCTRL & _CMU_HFRCOCTRL_SUDELAY_MASK) >> _CMU_HFRCOCTRL_SUDELAY_SHIFT; } /***************************************************************************//** * @brief * Set the HFRCO startup delay. * * @details * See the reference manual for more details. * * @param[in] delay * The startup delay to set (<= 31). ******************************************************************************/ void CMU_HFRCOStartupDelaySet(uint32_t delay) { EFM_ASSERT(delay <= 31); delay &= _CMU_HFRCOCTRL_SUDELAY_MASK >> _CMU_HFRCOCTRL_SUDELAY_SHIFT; CMU->HFRCOCTRL = (CMU->HFRCOCTRL & ~(_CMU_HFRCOCTRL_SUDELAY_MASK)) | (delay << _CMU_HFRCOCTRL_SUDELAY_SHIFT); } #endif #if defined(_CMU_USHFRCOCTRL_FREQRANGE_MASK) /**************************************************************************//** * @brief * Get the USHFRCO frequency calibration word in DEVINFO. * * @param[in] freq * Frequency in Hz. * * @return * USHFRCO calibration word for a given frequency. *****************************************************************************/ static uint32_t CMU_USHFRCODevinfoGet(CMU_USHFRCOFreq_TypeDef freq) { switch (freq) { case cmuUSHFRCOFreq_16M0Hz: return DEVINFO->USHFRCOCAL7; case cmuUSHFRCOFreq_32M0Hz: return DEVINFO->USHFRCOCAL11; case cmuUSHFRCOFreq_48M0Hz: return DEVINFO->USHFRCOCAL13; case cmuUSHFRCOFreq_50M0Hz: return DEVINFO->USHFRCOCAL14; default: /* cmuUSHFRCOFreq_UserDefined */ return 0; } } /***************************************************************************//** * @brief * Get the current USHFRCO frequency. * * @return * HFRCO frequency. ******************************************************************************/ CMU_USHFRCOFreq_TypeDef CMU_USHFRCOBandGet(void) { return (CMU_USHFRCOFreq_TypeDef) ushfrcoFreq; } /***************************************************************************//** * @brief * Get USHFRCO frequency. * * @return * USHFRCO frequency. ******************************************************************************/ uint32_t CMU_USHFRCOFreqGet(void) { return ushfrcoFreq; } /***************************************************************************//** * @brief * Set the USHFRCO calibration for the selected target frequency. * * @param[in] setFreq * USHFRCO frequency to set. ******************************************************************************/ void CMU_USHFRCOBandSet(CMU_USHFRCOFreq_TypeDef setFreq) { uint32_t freqCal; /* Get DEVINFO calibration values. */ freqCal = CMU_USHFRCODevinfoGet(setFreq); EFM_ASSERT((freqCal != 0) && (freqCal != UINT_MAX)); ushfrcoFreq = (uint32_t)setFreq; /* Wait for any previous sync to complete and set calibration data for the selected frequency. */ while (BUS_RegBitRead(&CMU->SYNCBUSY, _CMU_SYNCBUSY_USHFRCOBSY_SHIFT)) ; CMU->USHFRCOCTRL = freqCal; } #endif /* _CMU_USHFRCOCTRL_FREQRANGE_MASK */ #if defined(_CMU_HFXOCTRL_AUTOSTARTEM0EM1_MASK) /***************************************************************************//** * @brief * Enable or disable HFXO autostart. * * @param[in] userSel * Additional user specified enable bit. * * @param[in] enEM0EM1Start * If true, HFXO is automatically started upon entering EM0/EM1 entry from * EM2/EM3. HFXO selection has to be handled by the user. * If false, HFXO is not started automatically when entering EM0/EM1. * * @param[in] enEM0EM1StartSel * If true, HFXO is automatically started and immediately selected upon * entering EM0/EM1 entry from EM2/EM3. Note that this option stalls the use of * HFSRCCLK until HFXO becomes ready. HFCLKLE prescaler is also automatically * modified if userSel is specified. * If false, HFXO is not started or selected automatically when entering * EM0/EM1. ******************************************************************************/ void CMU_HFXOAutostartEnable(uint32_t userSel, bool enEM0EM1Start, bool enEM0EM1StartSel) { uint32_t hfxoFreq; uint32_t hfxoCtrl; #if defined(_EMU_CTRL_EM23VSCALE_MASK) if (enEM0EM1StartSel) { /* Voltage scaling is not compatible with HFXO auto start and select. */ EFM_ASSERT((EMU->CTRL & _EMU_CTRL_EM23VSCALE_MASK) == EMU_CTRL_EM23VSCALE_VSCALE2); } #endif /* Mask supported enable bits. */ #if defined(_CMU_HFXOCTRL_AUTOSTARTRDYSELRAC_MASK) userSel &= _CMU_HFXOCTRL_AUTOSTARTRDYSELRAC_MASK; #else userSel = 0; #endif hfxoCtrl = CMU->HFXOCTRL & ~(userSel | _CMU_HFXOCTRL_AUTOSTARTEM0EM1_MASK | _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_MASK); hfxoCtrl |= userSel | (enEM0EM1Start ? CMU_HFXOCTRL_AUTOSTARTEM0EM1 : 0UL) | (enEM0EM1StartSel ? CMU_HFXOCTRL_AUTOSTARTSELEM0EM1 : 0UL); hfxoFreq = SystemHFXOClockGet(); #if defined(_EMU_CMD_EM01VSCALE0_MASK) // Update voltage scaling. EMU_VScaleEM01ByClock(hfxoFreq, true); #endif /* Set wait-states for HFXO if automatic start and select is configured. */ if ((userSel > 0UL) || enEM0EM1StartSel) { CMU_UpdateWaitStates(hfxoFreq, (int)VSCALE_DEFAULT); setHfLeConfig(hfxoFreq); } if (enEM0EM1Start || enEM0EM1StartSel) { /* Enable the HFXO once in order to finish first time calibrations. */ CMU_OscillatorEnable(cmuOsc_HFXO, true, true); } /* Update HFXOCTRL after wait-states are updated as HF may automatically switch to HFXO when automatic select is enabled . */ CMU->HFXOCTRL = hfxoCtrl; } #endif /**************************************************************************//** * @brief * Set HFXO control registers. * * @note * HFXO configuration should be obtained from a configuration tool, * app note, or xtal data sheet. This function disables the HFXO to ensure * a valid state before update. * * @param[in] hfxoInit * HFXO setup parameters. *****************************************************************************/ void CMU_HFXOInit(const CMU_HFXOInit_TypeDef *hfxoInit) { /* Do not disable HFXO if it is currently selected as the HF/Core clock. */ EFM_ASSERT(CMU_ClockSelectGet(cmuClock_HF) != cmuSelect_HFXO); /* HFXO must be disabled before reconfiguration. */ CMU_OscillatorEnable(cmuOsc_HFXO, false, true); #if defined(_SILICON_LABS_32B_SERIES_1) \ && (_SILICON_LABS_GECKO_INTERNAL_SDID >= 100) uint32_t tmp = CMU_HFXOCTRL_MODE_XTAL; switch (hfxoInit->mode) { case cmuOscMode_Crystal: tmp = CMU_HFXOCTRL_MODE_XTAL; break; case cmuOscMode_External: tmp = CMU_HFXOCTRL_MODE_DIGEXTCLK; break; case cmuOscMode_AcCoupled: tmp = CMU_HFXOCTRL_MODE_ACBUFEXTCLK; break; default: EFM_ASSERT(false); /* Unsupported configuration */ break; } CMU->HFXOCTRL = (CMU->HFXOCTRL & ~_CMU_HFXOCTRL_MODE_MASK) | tmp; #if defined(CMU_HFXOCTRL_HFXOX2EN) /* HFXO Doubler can only be enabled on crystals up to max 25 MHz. */ tmp = 0; if (SystemHFXOClockGet() <= 25000000) { tmp |= CMU_HFXOCTRL_HFXOX2EN; } CMU->HFXOCTRL = (CMU->HFXOCTRL & ~_CMU_HFXOCTRL_HFXOX2EN_MASK) | tmp; #endif /* Set tuning for startup and steady state. */ CMU->HFXOSTARTUPCTRL = (hfxoInit->ctuneStartup << _CMU_HFXOSTARTUPCTRL_CTUNE_SHIFT) | (hfxoInit->xoCoreBiasTrimStartup << _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_SHIFT); CMU->HFXOSTEADYSTATECTRL = (CMU->HFXOSTEADYSTATECTRL & ~(_CMU_HFXOSTEADYSTATECTRL_CTUNE_MASK | _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_MASK)) | (hfxoInit->ctuneSteadyState << _CMU_HFXOSTEADYSTATECTRL_CTUNE_SHIFT) | (hfxoInit->xoCoreBiasTrimSteadyState << _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_SHIFT); /* Set timeouts */ CMU->HFXOTIMEOUTCTRL = (hfxoInit->timeoutPeakDetect << _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_SHIFT) | (hfxoInit->timeoutSteady << _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_SHIFT) | (hfxoInit->timeoutStartup << _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_SHIFT); #elif defined(_CMU_HFXOCTRL_MASK) /* Verify that the deprecated autostart fields are not used, * @ref CMU_HFXOAutostartEnable must be used instead. */ EFM_ASSERT(!(hfxoInit->autoStartEm01 || hfxoInit->autoSelEm01 || hfxoInit->autoStartSelOnRacWakeup)); uint32_t tmp = CMU_HFXOCTRL_MODE_XTAL; /* AC coupled external clock not supported. */ EFM_ASSERT(hfxoInit->mode != cmuOscMode_AcCoupled); if (hfxoInit->mode == cmuOscMode_External) { tmp = CMU_HFXOCTRL_MODE_DIGEXTCLK; } /* Apply control settings. */ CMU->HFXOCTRL = (CMU->HFXOCTRL & ~_CMU_HFXOCTRL_MODE_MASK) | tmp; BUS_RegBitWrite(&CMU->HFXOCTRL, _CMU_HFXOCTRL_LOWPOWER_SHIFT, (unsigned)hfxoInit->lowPowerMode); /* Set XTAL tuning parameters. */ #if defined(_CMU_HFXOCTRL1_PEAKDETTHR_MASK) /* Set peak detection threshold. */ CMU->HFXOCTRL1 = (CMU->HFXOCTRL1 & ~_CMU_HFXOCTRL1_PEAKDETTHR_MASK) | (hfxoInit->thresholdPeakDetect << _CMU_HFXOCTRL1_PEAKDETTHR_SHIFT); #endif /* Set tuning for startup and steady state. */ CMU->HFXOSTARTUPCTRL = ((uint32_t)hfxoInit->ctuneStartup << _CMU_HFXOSTARTUPCTRL_CTUNE_SHIFT) | ((uint32_t)hfxoInit->xoCoreBiasTrimStartup << _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_SHIFT); CMU->HFXOSTEADYSTATECTRL = (CMU->HFXOSTEADYSTATECTRL & ~(_CMU_HFXOSTEADYSTATECTRL_CTUNE_MASK | _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_MASK | _CMU_HFXOSTEADYSTATECTRL_REGISH_MASK | _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_MASK)) | ((uint32_t)hfxoInit->ctuneSteadyState << _CMU_HFXOSTEADYSTATECTRL_CTUNE_SHIFT) | ((uint32_t)hfxoInit->xoCoreBiasTrimSteadyState << _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_SHIFT) | ((uint32_t)hfxoInit->regIshSteadyState << _CMU_HFXOSTEADYSTATECTRL_REGISH_SHIFT) | getRegIshUpperVal(hfxoInit->regIshSteadyState); /* Set timeouts. */ CMU->HFXOTIMEOUTCTRL = ((uint32_t)hfxoInit->timeoutPeakDetect << _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_SHIFT) | ((uint32_t)hfxoInit->timeoutSteady << _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_SHIFT) | ((uint32_t)hfxoInit->timeoutStartup << _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_SHIFT) | ((uint32_t)hfxoInit->timeoutShuntOptimization << _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_SHIFT); #else CMU->CTRL = (CMU->CTRL & ~(_CMU_CTRL_HFXOTIMEOUT_MASK | _CMU_CTRL_HFXOBOOST_MASK | _CMU_CTRL_HFXOMODE_MASK | _CMU_CTRL_HFXOGLITCHDETEN_MASK)) | (hfxoInit->timeout << _CMU_CTRL_HFXOTIMEOUT_SHIFT) | (hfxoInit->boost << _CMU_CTRL_HFXOBOOST_SHIFT) | (hfxoInit->mode << _CMU_CTRL_HFXOMODE_SHIFT) | (hfxoInit->glitchDetector ? CMU_CTRL_HFXOGLITCHDETEN : 0); #endif } /***************************************************************************//** * @brief * Get the LCD framerate divisor (FDIV) setting. * * @return * The LCD framerate divisor. ******************************************************************************/ uint32_t CMU_LCDClkFDIVGet(void) { #if defined(LCD_PRESENT) && defined(_CMU_LCDCTRL_MASK) return (CMU->LCDCTRL & _CMU_LCDCTRL_FDIV_MASK) >> _CMU_LCDCTRL_FDIV_SHIFT; #else return 0; #endif /* defined(LCD_PRESENT) */ } /***************************************************************************//** * @brief * Set the LCD framerate divisor (FDIV) setting. * * @note * The FDIV field (CMU LCDCTRL register) should only be modified while the * LCD module is clock disabled (CMU LFACLKEN0.LCD bit is 0). This function * will NOT modify FDIV if the LCD module clock is enabled. See * @ref CMU_ClockEnable() for disabling/enabling LCD clock. * * @param[in] div * The FDIV setting to use. ******************************************************************************/ void CMU_LCDClkFDIVSet(uint32_t div) { #if defined(LCD_PRESENT) && defined(_CMU_LCDCTRL_MASK) EFM_ASSERT(div <= cmuClkDiv_128); /* Do not allow modification if LCD clock enabled. */ if (CMU->LFACLKEN0 & CMU_LFACLKEN0_LCD) { return; } div <<= _CMU_LCDCTRL_FDIV_SHIFT; div &= _CMU_LCDCTRL_FDIV_MASK; CMU->LCDCTRL = (CMU->LCDCTRL & ~_CMU_LCDCTRL_FDIV_MASK) | div; #else (void)div; /* Unused parameter. */ #endif /* defined(LCD_PRESENT) */ } /**************************************************************************//** * @brief * Set LFXO control registers. * * @note * LFXO configuration should be obtained from a configuration tool, * app note, or xtal data sheet. This function disables the LFXO when * necessary to ensure a valid state before update. * * @param[in] lfxoInit * LFXO setup parameters. *****************************************************************************/ void CMU_LFXOInit(const CMU_LFXOInit_TypeDef *lfxoInit) { /* Do not disable LFXO if it is currently selected as the HF/Core clock. */ EFM_ASSERT(CMU_ClockSelectGet(cmuClock_HF) != cmuSelect_LFXO); #if defined(_SILICON_LABS_32B_SERIES_1) uint32_t reg = (CMU->LFXOCTRL & ~(_CMU_LFXOCTRL_TUNING_MASK | _CMU_LFXOCTRL_GAIN_MASK | _CMU_LFXOCTRL_TIMEOUT_MASK | _CMU_LFXOCTRL_MODE_MASK)) | ((uint32_t)lfxoInit->ctune << _CMU_LFXOCTRL_TUNING_SHIFT) | ((uint32_t)lfxoInit->gain << _CMU_LFXOCTRL_GAIN_SHIFT) | ((uint32_t)lfxoInit->timeout << _CMU_LFXOCTRL_TIMEOUT_SHIFT) | ((uint32_t)lfxoInit->mode << _CMU_LFXOCTRL_MODE_SHIFT); /* If LFXO already contains the correct configuration then there is no need * to stop the oscillator and apply new settings. The LFXO can be running out * of reset, in which case we don't want to disable it unless necessary. */ if (reg != CMU->LFXOCTRL) { CMU_OscillatorEnable(cmuOsc_LFXO, false, true); CMU->LFXOCTRL = reg; } #elif defined(_SILICON_LABS_32B_SERIES_0) /* LFXO must be disabled before reconfiguration. */ CMU_OscillatorEnable(cmuOsc_LFXO, false, true); bool cmuBoost = (lfxoInit->boost & 0x2); BUS_RegMaskedWrite(&CMU->CTRL, _CMU_CTRL_LFXOTIMEOUT_MASK | _CMU_CTRL_LFXOBOOST_MASK | _CMU_CTRL_LFXOMODE_MASK, ((uint32_t)lfxoInit->timeout << _CMU_CTRL_LFXOTIMEOUT_SHIFT) | ((cmuBoost ? 1 : 0) << _CMU_CTRL_LFXOBOOST_SHIFT) | ((uint32_t)lfxoInit->mode << _CMU_CTRL_LFXOMODE_SHIFT)); #if defined(_EMU_AUXCTRL_REDLFXOBOOST_MASK) /* EFM32GG has a "reduce startup boost" field in the EMU */ bool emuReduce = (lfxoInit->boost & 0x1); BUS_RegBitWrite(&EMU->AUXCTRL, _EMU_AUXCTRL_REDLFXOBOOST_SHIFT, emuReduce ? 1 : 0); #endif #endif } /***************************************************************************//** * @brief * Enable/disable oscillator. * * @note * WARNING: When this function is called to disable either cmuOsc_LFXO or * cmuOsc_HFXO, the LFXOMODE or HFXOMODE fields of the CMU_CTRL register * are reset to the reset value. In other words, if external clock sources are selected * in either LFXOMODE or HFXOMODE fields, the configuration will be cleared * and needs to be reconfigured if needed later. * * @param[in] osc * The oscillator to enable/disable. * * @param[in] enable * @li true - enable specified oscillator. * @li false - disable specified oscillator. * * @param[in] wait * Only used if @p enable is true. * @li true - wait for oscillator start-up time to timeout before returning. * @li false - do not wait for oscillator start-up time to timeout before * returning. ******************************************************************************/ void CMU_OscillatorEnable(CMU_Osc_TypeDef osc, bool enable, bool wait) { uint32_t rdyBitPos; #if defined(_SILICON_LABS_32B_SERIES_1) uint32_t ensBitPos; #endif #if defined(_CMU_STATUS_HFXOPEAKDETRDY_MASK) uint32_t hfxoTrimStatus; #endif uint32_t enBit; uint32_t disBit; switch (osc) { case cmuOsc_HFRCO: enBit = CMU_OSCENCMD_HFRCOEN; disBit = CMU_OSCENCMD_HFRCODIS; rdyBitPos = _CMU_STATUS_HFRCORDY_SHIFT; #if defined(_SILICON_LABS_32B_SERIES_1) ensBitPos = _CMU_STATUS_HFRCOENS_SHIFT; #endif break; case cmuOsc_HFXO: enBit = CMU_OSCENCMD_HFXOEN; disBit = CMU_OSCENCMD_HFXODIS; rdyBitPos = _CMU_STATUS_HFXORDY_SHIFT; #if defined(_SILICON_LABS_32B_SERIES_1) ensBitPos = _CMU_STATUS_HFXOENS_SHIFT; #endif break; case cmuOsc_AUXHFRCO: enBit = CMU_OSCENCMD_AUXHFRCOEN; disBit = CMU_OSCENCMD_AUXHFRCODIS; rdyBitPos = _CMU_STATUS_AUXHFRCORDY_SHIFT; #if defined(_SILICON_LABS_32B_SERIES_1) ensBitPos = _CMU_STATUS_AUXHFRCOENS_SHIFT; #endif break; case cmuOsc_LFRCO: enBit = CMU_OSCENCMD_LFRCOEN; disBit = CMU_OSCENCMD_LFRCODIS; rdyBitPos = _CMU_STATUS_LFRCORDY_SHIFT; #if defined(_SILICON_LABS_32B_SERIES_1) ensBitPos = _CMU_STATUS_LFRCOENS_SHIFT; #endif break; case cmuOsc_LFXO: enBit = CMU_OSCENCMD_LFXOEN; disBit = CMU_OSCENCMD_LFXODIS; rdyBitPos = _CMU_STATUS_LFXORDY_SHIFT; #if defined(_SILICON_LABS_32B_SERIES_1) ensBitPos = _CMU_STATUS_LFXOENS_SHIFT; #endif break; #if defined(_CMU_STATUS_USHFRCOENS_MASK) case cmuOsc_USHFRCO: enBit = CMU_OSCENCMD_USHFRCOEN; disBit = CMU_OSCENCMD_USHFRCODIS; rdyBitPos = _CMU_STATUS_USHFRCORDY_SHIFT; #if defined(_SILICON_LABS_32B_SERIES_1) ensBitPos = _CMU_STATUS_USHFRCOENS_SHIFT; #endif break; #endif default: /* Undefined clock source, cmuOsc_CLKIN0 or cmuOsc_ULFRCO. ULFRCO is always enabled and cannot be disabled. In other words,the definition of cmuOsc_ULFRCO is primarily intended for information: the ULFRCO is always on. */ EFM_ASSERT(false); return; } if (enable) { #if defined(_CMU_HFXOCTRL_MASK) bool firstHfxoEnable = false; /* Enabling the HFXO for the first time requires special handling. * PEAKDETSHUTOPTMODE field of the HFXOCTRL register is used to see if this is the * first time the HFXO is enabled. */ if (osc == cmuOsc_HFXO) { if (getHfxoTuningMode() == HFXO_TUNING_MODE_AUTO) { /* REGPWRSEL must be set to DVDD before the HFXO can be enabled. */ #if defined(_EMU_PWRCTRL_REGPWRSEL_MASK) EFM_ASSERT((EMU->PWRCTRL & EMU_PWRCTRL_REGPWRSEL_DVDD) != 0UL); #endif firstHfxoEnable = true; /* The first time that an external clock is enabled, switch to CMD mode to make sure that * only SCO and not PDA tuning is performed. */ if ((CMU->HFXOCTRL & (_CMU_HFXOCTRL_MODE_MASK)) == CMU_HFXOCTRL_MODE_DIGEXTCLK) { setHfxoTuningMode(HFXO_TUNING_MODE_CMD); } } } #endif CMU->OSCENCMD = enBit; #if defined(_SILICON_LABS_32B_SERIES_1) /* Always wait for ENS to go high. */ while (BUS_RegBitRead(&CMU->STATUS, ensBitPos) == 0UL) { } #endif /* Wait for the clock to become ready after enable. */ if (wait) { while (BUS_RegBitRead(&CMU->STATUS, rdyBitPos) == 0UL) { } #if defined(_SILICON_LABS_32B_SERIES_1) if ((osc == cmuOsc_HFXO) && firstHfxoEnable) { if ((CMU->HFXOCTRL & _CMU_HFXOCTRL_MODE_MASK) == CMU_HFXOCTRL_MODE_DIGEXTCLK) { #if defined(CMU_CMD_HFXOSHUNTOPTSTART) /* External clock mode should only do shunt current optimization. */ (void)CMU_OscillatorTuningOptimize(cmuOsc_HFXO, cmuHFXOTuningMode_ShuntCommand, true); #endif } else { /* Wait for the peak detection and shunt current optimization to complete. */ (void)CMU_OscillatorTuningWait(cmuOsc_HFXO, cmuHFXOTuningMode_Auto); } /* Disable the HFXO again to apply the trims. Apply trim from HFXOTRIMSTATUS when disabled. */ hfxoTrimStatus = CMU_OscillatorTuningGet(cmuOsc_HFXO); CMU_OscillatorEnable(cmuOsc_HFXO, false, true); CMU_OscillatorTuningSet(cmuOsc_HFXO, hfxoTrimStatus); /* Restart in CMD mode. */ CMU->OSCENCMD = enBit; while (BUS_RegBitRead(&CMU->STATUS, rdyBitPos) == 0UL) { } } #endif } } else { CMU->OSCENCMD = disBit; #if defined(_SILICON_LABS_32B_SERIES_1) /* Always wait for ENS to go low. */ while ((CMU->STATUS & (0x1 << ensBitPos)) != 0U) { } if (wait) { /* Wait for RDY to go low as well. */ while ((CMU->STATUS & (0x1 << rdyBitPos)) != 0U) { } } #endif } } /***************************************************************************//** * @brief * Get the oscillator frequency tuning setting. * * @param[in] osc * An oscillator to get tuning value for, one of the following: * @li #cmuOsc_LFRCO * @li #cmuOsc_HFRCO @if _CMU_USHFRCOCTRL_TUNING_MASK * @li #cmuOsc_USHFRCO * @endif * @li #cmuOsc_AUXHFRCO * @li #cmuOsc_HFXO if CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE is defined * * @return * The oscillator frequency tuning setting in use. ******************************************************************************/ uint32_t CMU_OscillatorTuningGet(CMU_Osc_TypeDef osc) { uint32_t ret; switch (osc) { case cmuOsc_LFRCO: ret = (CMU->LFRCOCTRL & _CMU_LFRCOCTRL_TUNING_MASK) >> _CMU_LFRCOCTRL_TUNING_SHIFT; break; case cmuOsc_HFRCO: ret = (CMU->HFRCOCTRL & _CMU_HFRCOCTRL_TUNING_MASK) >> _CMU_HFRCOCTRL_TUNING_SHIFT; break; #if defined (_CMU_USHFRCOCTRL_TUNING_MASK) case cmuOsc_USHFRCO: ret = (CMU->USHFRCOCTRL & _CMU_USHFRCOCTRL_TUNING_MASK) >> _CMU_USHFRCOCTRL_TUNING_SHIFT; break; #endif case cmuOsc_AUXHFRCO: ret = (CMU->AUXHFRCOCTRL & _CMU_AUXHFRCOCTRL_TUNING_MASK) >> _CMU_AUXHFRCOCTRL_TUNING_SHIFT; break; #if defined(_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK) case cmuOsc_HFXO: ret = CMU->HFXOTRIMSTATUS & (_CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_MASK #if defined(_CMU_HFXOTRIMSTATUS_REGISH_MASK) | _CMU_HFXOTRIMSTATUS_REGISH_MASK #endif ); break; #endif default: ret = 0; EFM_ASSERT(false); break; } return ret; } /***************************************************************************//** * @brief * Set the oscillator frequency tuning control. * * @note * Oscillator tuning is done during production and the tuning value is * automatically loaded after reset. Changing the tuning value from the * calibrated value is for more advanced use. Certain oscillators also have * build-in tuning optimization. * * @param[in] osc * An oscillator to set tuning value for, one of the following: * @li #cmuOsc_LFRCO * @li #cmuOsc_HFRCO @if _CMU_USHFRCOCTRL_TUNING_MASK * @li #cmuOsc_USHFRCO * @endif * @li #cmuOsc_AUXHFRCO * @li #cmuOsc_HFXO if PEAKDETSHUNTOPTMODE is available. Note that CMD mode is set. * * @param[in] val * The oscillator frequency tuning setting to use. ******************************************************************************/ void CMU_OscillatorTuningSet(CMU_Osc_TypeDef osc, uint32_t val) { #if defined(_CMU_HFXOSTEADYSTATECTRL_REGISH_MASK) uint32_t regIshUpper; #endif switch (osc) { case cmuOsc_LFRCO: EFM_ASSERT(val <= (_CMU_LFRCOCTRL_TUNING_MASK >> _CMU_LFRCOCTRL_TUNING_SHIFT)); val &= (_CMU_LFRCOCTRL_TUNING_MASK >> _CMU_LFRCOCTRL_TUNING_SHIFT); #if defined(_SILICON_LABS_32B_SERIES_1) while (BUS_RegBitRead(&CMU->SYNCBUSY, _CMU_SYNCBUSY_LFRCOBSY_SHIFT) != 0UL) { } #endif CMU->LFRCOCTRL = (CMU->LFRCOCTRL & ~(_CMU_LFRCOCTRL_TUNING_MASK)) | (val << _CMU_LFRCOCTRL_TUNING_SHIFT); break; case cmuOsc_HFRCO: EFM_ASSERT(val <= (_CMU_HFRCOCTRL_TUNING_MASK >> _CMU_HFRCOCTRL_TUNING_SHIFT)); val &= (_CMU_HFRCOCTRL_TUNING_MASK >> _CMU_HFRCOCTRL_TUNING_SHIFT); #if defined(_SILICON_LABS_32B_SERIES_1) while (BUS_RegBitRead(&CMU->SYNCBUSY, _CMU_SYNCBUSY_HFRCOBSY_SHIFT) != 0UL) { } #endif CMU->HFRCOCTRL = (CMU->HFRCOCTRL & ~(_CMU_HFRCOCTRL_TUNING_MASK)) | (val << _CMU_HFRCOCTRL_TUNING_SHIFT); break; #if defined (_CMU_USHFRCOCTRL_TUNING_MASK) case cmuOsc_USHFRCO: EFM_ASSERT(val <= (_CMU_USHFRCOCTRL_TUNING_MASK >> _CMU_USHFRCOCTRL_TUNING_SHIFT)); val &= (_CMU_USHFRCOCTRL_TUNING_MASK >> _CMU_USHFRCOCTRL_TUNING_SHIFT); #if defined(_SILICON_LABS_32B_SERIES_1) while (BUS_RegBitRead(&CMU->SYNCBUSY, _CMU_SYNCBUSY_USHFRCOBSY_SHIFT)) { } #endif CMU->USHFRCOCTRL = (CMU->USHFRCOCTRL & ~(_CMU_USHFRCOCTRL_TUNING_MASK)) | (val << _CMU_USHFRCOCTRL_TUNING_SHIFT); break; #endif case cmuOsc_AUXHFRCO: EFM_ASSERT(val <= (_CMU_AUXHFRCOCTRL_TUNING_MASK >> _CMU_AUXHFRCOCTRL_TUNING_SHIFT)); val &= (_CMU_AUXHFRCOCTRL_TUNING_MASK >> _CMU_AUXHFRCOCTRL_TUNING_SHIFT); #if defined(_SILICON_LABS_32B_SERIES_1) while (BUS_RegBitRead(&CMU->SYNCBUSY, _CMU_SYNCBUSY_AUXHFRCOBSY_SHIFT) != 0UL) { } #endif CMU->AUXHFRCOCTRL = (CMU->AUXHFRCOCTRL & ~(_CMU_AUXHFRCOCTRL_TUNING_MASK)) | (val << _CMU_AUXHFRCOCTRL_TUNING_SHIFT); break; #if defined(_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK) case cmuOsc_HFXO: /* Do set PEAKDETSHUNTOPTMODE or HFXOSTEADYSTATECTRL if HFXO is enabled. */ EFM_ASSERT((CMU->STATUS & CMU_STATUS_HFXOENS) == 0UL); /* Switch to command mode. Automatic SCO and PDA calibration is not done at the next enable. Set user REGISH, REGISHUPPER, and IBTRIMXOCORE. */ CMU->HFXOCTRL = (CMU->HFXOCTRL & ~_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK) | CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_CMD; #if defined(_CMU_HFXOSTEADYSTATECTRL_REGISH_MASK) regIshUpper = getRegIshUpperVal((val & _CMU_HFXOSTEADYSTATECTRL_REGISH_MASK) >> _CMU_HFXOSTEADYSTATECTRL_REGISH_SHIFT); CMU->HFXOSTEADYSTATECTRL = (CMU->HFXOSTEADYSTATECTRL & ~(_CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_MASK | _CMU_HFXOSTEADYSTATECTRL_REGISH_MASK | _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_MASK)) | val | regIshUpper; #else CMU->HFXOSTEADYSTATECTRL = (CMU->HFXOSTEADYSTATECTRL & ~_CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_MASK) | val; #endif break; #endif default: EFM_ASSERT(false); break; } } #if defined(_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK) || defined(_CMU_HFXOCTRL_PEAKDETMODE_MASK) /***************************************************************************//** * @brief * Wait for the oscillator tuning optimization. * * @param[in] osc * An oscillator to set tuning value for, one of the following: * @li #cmuOsc_HFXO * * @param[in] mode * Tuning optimization mode. * * @return * Returns false on invalid parameters or oscillator error status. ******************************************************************************/ bool CMU_OscillatorTuningWait(CMU_Osc_TypeDef osc, CMU_HFXOTuningMode_TypeDef mode) { uint32_t waitFlags; EFM_ASSERT(osc == cmuOsc_HFXO); /* Currently implemented for HFXO with PEAKDETSHUNTOPTMODE only. */ (void)osc; if (getHfxoTuningMode() == HFXO_TUNING_MODE_AUTO) { waitFlags = HFXO_TUNING_READY_FLAGS; } else { /* Set wait flags for each command and wait. */ switch (mode) { #if defined(_CMU_STATUS_HFXOSHUNTOPTRDY_MASK) case cmuHFXOTuningMode_ShuntCommand: waitFlags = CMU_STATUS_HFXOSHUNTOPTRDY; break; #endif case cmuHFXOTuningMode_Auto: waitFlags = HFXO_TUNING_READY_FLAGS; break; #if defined(CMU_CMD_HFXOSHUNTOPTSTART) case cmuHFXOTuningMode_PeakShuntCommand: waitFlags = HFXO_TUNING_READY_FLAGS; break; #endif default: waitFlags = _CMU_STATUS_MASK; EFM_ASSERT(false); break; } } while ((CMU->STATUS & waitFlags) != waitFlags) { } #if defined(CMU_IF_HFXOPEAKDETERR) /* Check error flags. */ if ((waitFlags & CMU_STATUS_HFXOPEAKDETRDY) != 0UL) { return (CMU->IF & CMU_IF_HFXOPEAKDETERR) != 0UL ? true : false; } #endif return true; } /***************************************************************************//** * @brief * Start and optionally wait for the oscillator tuning optimization. * * @param[in] osc * An oscillator to set tuning value for, one of the following: * @li #cmuOsc_HFXO * * @param[in] mode * Tuning optimization mode. * * @param[in] wait * Wait for tuning optimization to complete. * true - wait for tuning optimization to complete. * false - return without waiting. * * @return * Returns false on invalid parameters or oscillator error status. ******************************************************************************/ bool CMU_OscillatorTuningOptimize(CMU_Osc_TypeDef osc, CMU_HFXOTuningMode_TypeDef mode, bool wait) { switch (osc) { case cmuOsc_HFXO: if ((unsigned)mode != 0U) { #if defined(CMU_IF_HFXOPEAKDETERR) /* Clear the error flag before command write. */ CMU->IFC = CMU_IFC_HFXOPEAKDETERR; #endif CMU->CMD = (uint32_t)mode; } if (wait) { return CMU_OscillatorTuningWait(osc, mode); } break; default: EFM_ASSERT(false); break; } return true; } #endif /**************************************************************************//** * @brief * Determine if the currently selected PCNTn clock used is external or LFBCLK. * * @param[in] instance * PCNT instance number to get currently selected clock source for. * * @return * @li true - selected clock is external clock. * @li false - selected clock is LFBCLK. *****************************************************************************/ bool CMU_PCNTClockExternalGet(unsigned int instance) { uint32_t setting; switch (instance) { #if defined(_CMU_PCNTCTRL_PCNT0CLKEN_MASK) case 0: setting = CMU->PCNTCTRL & CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0; break; #if defined(_CMU_PCNTCTRL_PCNT1CLKEN_MASK) case 1: setting = CMU->PCNTCTRL & CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0; break; #if defined(_CMU_PCNTCTRL_PCNT2CLKEN_MASK) case 2: setting = CMU->PCNTCTRL & CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0; break; #endif #endif #endif default: setting = 0; break; } return setting > 0UL ? true : false; } /**************************************************************************//** * @brief * Select the PCNTn clock. * * @param[in] instance * PCNT instance number to set selected clock source for. * * @param[in] external * Set to true to select the external clock, false to select LFBCLK. *****************************************************************************/ void CMU_PCNTClockExternalSet(unsigned int instance, bool external) { #if defined(PCNT_PRESENT) uint32_t setting = 0; EFM_ASSERT(instance < (unsigned)PCNT_COUNT); if (external) { setting = 1; } BUS_RegBitWrite(&(CMU->PCNTCTRL), (instance * 2U) + 1U, setting); #else (void)instance; /* An unused parameter */ (void)external; /* An unused parameter */ #endif } #if defined(_CMU_USHFRCOCONF_BAND_MASK) /***************************************************************************//** * @brief * Get USHFRCO band in use. * * @return * USHFRCO band in use. ******************************************************************************/ CMU_USHFRCOBand_TypeDef CMU_USHFRCOBandGet(void) { return (CMU_USHFRCOBand_TypeDef)((CMU->USHFRCOCONF & _CMU_USHFRCOCONF_BAND_MASK) >> _CMU_USHFRCOCONF_BAND_SHIFT); } /***************************************************************************//** * @brief * Get USHFRCO frequency. * * @return * USHFRCO frequency. ******************************************************************************/ uint32_t CMU_USHFRCOFreqGet(void) { return ushfrcoFreq; } #endif #if defined(_CMU_USHFRCOCONF_BAND_MASK) /***************************************************************************//** * @brief * Set the USHFRCO band to use. * * @param[in] band * USHFRCO band to activate. ******************************************************************************/ void CMU_USHFRCOBandSet(CMU_USHFRCOBand_TypeDef band) { uint32_t tuning; uint32_t fineTuning; /* Cannot switch band if USHFRCO is already selected as HF clock. */ EFM_ASSERT(CMU_ClockSelectGet(cmuClock_HF) != cmuSelect_USHFRCO); /* Read tuning value from calibration table. */ switch (band) { case cmuUSHFRCOBand_24MHz: tuning = (DEVINFO->USHFRCOCAL0 & _DEVINFO_USHFRCOCAL0_BAND24_TUNING_MASK) >> _DEVINFO_USHFRCOCAL0_BAND24_TUNING_SHIFT; fineTuning = (DEVINFO->USHFRCOCAL0 & _DEVINFO_USHFRCOCAL0_BAND24_FINETUNING_MASK) >> _DEVINFO_USHFRCOCAL0_BAND24_FINETUNING_SHIFT; ushfrcoFreq = 24000000UL; break; case cmuUSHFRCOBand_48MHz: tuning = (DEVINFO->USHFRCOCAL0 & _DEVINFO_USHFRCOCAL0_BAND48_TUNING_MASK) >> _DEVINFO_USHFRCOCAL0_BAND48_TUNING_SHIFT; fineTuning = (DEVINFO->USHFRCOCAL0 & _DEVINFO_USHFRCOCAL0_BAND48_FINETUNING_MASK) >> _DEVINFO_USHFRCOCAL0_BAND48_FINETUNING_SHIFT; /* Enable the clock divider before switching the band from 24 to 48 MHz */ BUS_RegBitWrite(&CMU->USHFRCOCONF, _CMU_USHFRCOCONF_USHFRCODIV2DIS_SHIFT, 0); ushfrcoFreq = 48000000UL; break; default: EFM_ASSERT(false); return; } /* Set band and tuning. */ CMU->USHFRCOCONF = (CMU->USHFRCOCONF & ~_CMU_USHFRCOCONF_BAND_MASK) | (band << _CMU_USHFRCOCONF_BAND_SHIFT); CMU->USHFRCOCTRL = (CMU->USHFRCOCTRL & ~_CMU_USHFRCOCTRL_TUNING_MASK) | (tuning << _CMU_USHFRCOCTRL_TUNING_SHIFT); CMU->USHFRCOTUNE = (CMU->USHFRCOTUNE & ~_CMU_USHFRCOTUNE_FINETUNING_MASK) | (fineTuning << _CMU_USHFRCOTUNE_FINETUNING_SHIFT); /* Disable the clock divider after switching the band from 48 to 24 MHz. */ if (band == cmuUSHFRCOBand_24MHz) { BUS_RegBitWrite(&CMU->USHFRCOCONF, _CMU_USHFRCOCONF_USHFRCODIV2DIS_SHIFT, 1); } } #endif #endif // defined(_SILICON_LABS_32B_SERIES_2) /** @} (end addtogroup CMU) */ /** @} (end addtogroup emlib) */ #endif /* defined(CMU_PRESENT) */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/emlib/src/em_core.c.
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/***************************************************************************//** * @file * @brief Core interrupt handling API * @version 5.7.0 ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * SPDX-License-Identifier: Zlib * * The licensor of this software is Silicon Laboratories Inc. * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be * appreciated but is not required. * 2. Altered source versions must be plainly marked as such, and must not be * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * ******************************************************************************/ #include "em_core.h" #include "em_assert.h" #if defined(EMLIB_USER_CONFIG) #include "emlib_config.h" #endif /***************************************************************************//** * @addtogroup emlib * @{ ******************************************************************************/ /* *INDENT-OFF* */ /***************************************************************************//** @addtogroup CORE @brief Core interrupt handling API @li @ref core_intro @li @ref core_conf @li @ref core_macro_api @li @ref core_reimplementation @li @ref core_vector_tables @li @ref core_examples @li @ref core_porting @n @section core_intro Introduction CORE interrupt API provides a simple and safe means to disable and enable interrupts to protect sections of code. This is often referred to as "critical sections". This module provides support for three types of critical sections, each with different interrupt blocking capabilities. @li <b>CRITICAL</b> section: Inside a critical section, all interrupts are disabled (except for fault handlers). The PRIMASK register is always used for interrupt disable/enable. @li <b>ATOMIC</b> section: This type of section is configurable and the default method is to use PRIMASK. With BASEPRI configuration, interrupts with priority equal to or lower than a given configurable level are disabled. The interrupt disable priority level is defined at compile time. The BASEPRI register is not available for all architectures. @li <b>NVIC mask</b> section: Disable NVIC (external interrupts) on an individual manner. em_core also has an API for manipulating RAM-based interrupt vector tables. @n @section core_conf Compile-time Configuration The following @htmlonly #defines @endhtmlonly are used to configure em_core: @verbatim // The interrupt priority level used inside ATOMIC sections. #define CORE_ATOMIC_BASE_PRIORITY_LEVEL 3 // A method used for interrupt disable/enable within ATOMIC sections. #define CORE_ATOMIC_METHOD CORE_ATOMIC_METHOD_PRIMASK @endverbatim If the default values do not support your needs, they can be overridden by supplying -D compiler flags on the compiler command line or by collecting all macro redefinitions in a file named @em emlib_config.h and then supplying -DEMLIB_USER_CONFIG on a compiler command line. @note The default emlib configuration for ATOMIC section interrupt disable method is using PRIMASK, i.e., ATOMIC sections are implemented as CRITICAL sections. @note Due to architectural limitations Cortex-M0+ devices do not support ATOMIC type critical sections using the BASEPRI register. On M0+ devices ATOMIC section helper macros are available but they are implemented as CRITICAL sections using PRIMASK register. @n @section core_macro_api Macro API The primary em_core API is the macro API. Macro API will map to correct CORE functions according to the selected @ref CORE_ATOMIC_METHOD and similar configurations (the full CORE API is of course also available). The most useful macros are as follows: @ref CORE_DECLARE_IRQ_STATE @n @ref CORE_ENTER_ATOMIC() @n @ref CORE_EXIT_ATOMIC()@n Used together to implement an ATOMIC section. @verbatim { CORE_DECLARE_IRQ_STATE; // Storage for saving IRQ state prior to // atomic section entry. CORE_ENTER_ATOMIC(); // Enter atomic section. ... ... your code goes here ... ... CORE_EXIT_ATOMIC(); // Exit atomic section, IRQ state is restored. } @endverbatim @n @ref CORE_ATOMIC_SECTION(yourcode)@n A concatenation of all three macros above. @verbatim { CORE_ATOMIC_SECTION( ... ... your code goes here ... ... ) } @endverbatim @n @ref CORE_DECLARE_IRQ_STATE @n @ref CORE_ENTER_CRITICAL() @n @ref CORE_EXIT_CRITICAL() @n @ref CORE_CRITICAL_SECTION(yourcode)@n These macros implement CRITICAL sections in a similar fashion as described above for ATOMIC sections. @n @ref CORE_DECLARE_NVIC_STATE @n @ref CORE_ENTER_NVIC() @n @ref CORE_EXIT_NVIC() @n @ref CORE_NVIC_SECTION(yourcode)@n These macros implement NVIC mask sections in a similar fashion as described above for ATOMIC sections. See @ref core_examples for an example. Refer to @em Macros or <em>Macro Definition Documentation</em> below for a full list of macros. @n @section core_reimplementation API reimplementation Most of the functions in the API are implemented as weak functions. This means that it is easy to reimplement when special needs arise. Shown below is a reimplementation of CRITICAL sections suitable if FreeRTOS OS is used: @verbatim CORE_irqState_t CORE_EnterCritical(void) { vPortEnterCritical(); return 0; } void CORE_ExitCritical(CORE_irqState_t irqState) { (void)irqState; vPortExitCritical(); } @endverbatim Also note that CORE_Enter/ExitCritical() are not implemented as inline functions. As a result, reimplementations will be possible even when original implementations are inside a linked library. Some RTOSes must be notified on interrupt handler entry and exit. Macros @ref CORE_INTERRUPT_ENTRY() and @ref CORE_INTERRUPT_EXIT() are suitable placeholders for inserting such code. Insert these macros in all your interrupt handlers and then override the default macro implementations. This is an example if uC/OS is used: @verbatim // In emlib_config.h: #define CORE_INTERRUPT_ENTRY() OSIntEnter() #define CORE_INTERRUPT_EXIT() OSIntExit() @endverbatim @n @section core_vector_tables Interrupt vector tables When using RAM based interrupt vector tables it is the user's responsibility to allocate the table space correctly. The tables must be aligned as specified in the CPU reference manual. @ref CORE_InitNvicVectorTable()@n Initialize a RAM based vector table by copying table entries from a source vector table to a target table. VTOR is set to the address of the target vector table. @n @ref CORE_GetNvicRamTableHandler() @n @ref CORE_SetNvicRamTableHandler()@n Use these functions to get or set the interrupt handler for a specific IRQn. They both use the interrupt vector table defined by the current VTOR register value. @n @section core_examples Examples Implement an NVIC critical section: @verbatim { CORE_DECLARE_NVIC_ZEROMASK(mask); // A zero initialized NVIC disable mask // Set mask bits for IRQs to block in the NVIC critical section. // In many cases, you can create the disable mask once upon application // startup and use the mask globally throughout the application lifetime. CORE_NvicMaskSetIRQ(LEUART0_IRQn, &mask); CORE_NvicMaskSetIRQ(VCMP_IRQn, &mask); // Enter NVIC critical section with the disable mask CORE_NVIC_SECTION(&mask, ... ... your code goes here ... ... ) } @endverbatim @n @section core_porting Porting from em_int Existing code using INT_Enable() and INT_Disable() must be ported to the em_core API. While em_int used, a global counter to store the interrupt state, em_core uses a local variable. Any usage of INT_Disable(), therefore, needs to be replaced with a declaration of the interrupt state variable before entering the critical section. Since the state variable is in local scope, the critical section exit needs to occur within the scope of the variable. If multiple nested critical sections are used, each needs to have its own state variable in its own scope. In many cases, completely disabling all interrupts using CRITICAL sections might be more heavy-handed than needed. When porting, consider whether other types of sections, such as ATOMIC or NVIC mask, can be used to only disable a subset of the interrupts. Replacing em_int calls with em_core function calls: @verbatim void func(void) { // INT_Disable(); CORE_DECLARE_IRQ_STATE; CORE_ENTER_ATOMIC(); . . . // INT_Enable(); CORE_EXIT_ATOMIC(); } @endverbatim * @{ ******************************************************************************/ /* *INDENT-ON* */ /******************************************************************************* ******************************* DEFINES *********************************** ******************************************************************************/ #if !defined(CORE_ATOMIC_BASE_PRIORITY_LEVEL) /** The interrupt priority level disabled within ATOMIC regions. Interrupts * with priority level equal to or lower than this definition will be disabled * within ATOMIC regions. */ #define CORE_ATOMIC_BASE_PRIORITY_LEVEL 3 #endif #if !defined(CORE_ATOMIC_METHOD) /** Specify which method to use when implementing ATOMIC sections. You can * select between BASEPRI or PRIMASK method. * @note On Cortex-M0+ devices only PRIMASK can be used. */ #define CORE_ATOMIC_METHOD CORE_ATOMIC_METHOD_PRIMASK #endif #if !defined(CORE_INTERRUPT_ENTRY) // Some RTOSes must be notified on interrupt entry (and exit). // Use this macro at the start of all your interrupt handlers. // Reimplement the macro in emlib_config.h to suit the needs of your RTOS. /** Placeholder for optional interrupt handler entry code. This might be needed * when working with an RTOS. */ #define CORE_INTERRUPT_ENTRY() #endif #if !defined(CORE_INTERRUPT_EXIT) /** Placeholder for optional interrupt handler exit code. This might be needed * when working with an RTOS. */ #define CORE_INTERRUPT_EXIT() #endif // Compile time sanity check. #if (CORE_ATOMIC_METHOD != CORE_ATOMIC_METHOD_PRIMASK) \ && (CORE_ATOMIC_METHOD != CORE_ATOMIC_METHOD_BASEPRI) #error "em_core: Undefined ATOMIC IRQ handling strategy." #endif /******************************************************************************* ****************************** FUNCTIONS ********************************** ******************************************************************************/ /***************************************************************************//** * @brief * Disable interrupts. * * Disable all interrupts by setting PRIMASK. * (Fault exception handlers will still be enabled). ******************************************************************************/ SL_WEAK void CORE_CriticalDisableIrq(void) { __disable_irq(); } /***************************************************************************//** * @brief * Enable interrupts. * * Enable interrupts by clearing PRIMASK. ******************************************************************************/ SL_WEAK void CORE_CriticalEnableIrq(void) { __enable_irq(); } /***************************************************************************//** * @brief * Enter a CRITICAL section. * * When a CRITICAL section is entered, all interrupts (except fault handlers) * are disabled. * * @return * The value of PRIMASK register prior to the CRITICAL section entry. ******************************************************************************/ SL_WEAK CORE_irqState_t CORE_EnterCritical(void) { CORE_irqState_t irqState = __get_PRIMASK(); __disable_irq(); return irqState; } /***************************************************************************//** * @brief * Exit a CRITICAL section. * * @param[in] irqState * The interrupt priority blocking level to restore to PRIMASK when exiting * the CRITICAL section. This value is usually the one returned by a prior * call to @ref CORE_EnterCritical(). ******************************************************************************/ SL_WEAK void CORE_ExitCritical(CORE_irqState_t irqState) { if (irqState == 0U) { __enable_irq(); } } /***************************************************************************//** * @brief * Brief interrupt enable/disable sequence to allow handling of * pending interrupts. * * @note * Usually used within a CRITICAL section. ******************************************************************************/ SL_WEAK void CORE_YieldCritical(void) { if ((__get_PRIMASK() & 1U) != 0U) { __enable_irq(); __ISB(); __disable_irq(); } } /***************************************************************************//** * @brief * Disable interrupts. * * Disable interrupts with a priority lower or equal to * @ref CORE_ATOMIC_BASE_PRIORITY_LEVEL. Sets core BASEPRI register * to CORE_ATOMIC_BASE_PRIORITY_LEVEL. * * @note * If @ref CORE_ATOMIC_METHOD is @ref CORE_ATOMIC_METHOD_PRIMASK, this * function is identical to @ref CORE_CriticalDisableIrq(). ******************************************************************************/ SL_WEAK void CORE_AtomicDisableIrq(void) { #if (CORE_ATOMIC_METHOD == CORE_ATOMIC_METHOD_BASEPRI) __set_BASEPRI(CORE_ATOMIC_BASE_PRIORITY_LEVEL << (8 - __NVIC_PRIO_BITS)); #else __disable_irq(); #endif // (CORE_ATOMIC_METHOD == CORE_ATOMIC_METHOD_BASEPRI) } /***************************************************************************//** * @brief * Enable interrupts. * * Enable interrupts by setting core BASEPRI register to 0. * * @note * If @ref CORE_ATOMIC_METHOD is @ref CORE_ATOMIC_METHOD_BASEPRI and PRIMASK * is set (CPU is inside a CRITICAL section), interrupts will still be * disabled after calling this function. * * @note * If @ref CORE_ATOMIC_METHOD is @ref CORE_ATOMIC_METHOD_PRIMASK, this * function is identical to @ref CORE_CriticalEnableIrq(). ******************************************************************************/ SL_WEAK void CORE_AtomicEnableIrq(void) { #if (CORE_ATOMIC_METHOD == CORE_ATOMIC_METHOD_BASEPRI) __set_BASEPRI(0); #else __enable_irq(); #endif // (CORE_ATOMIC_METHOD == CORE_ATOMIC_METHOD_BASEPRI) } /***************************************************************************//** * @brief * Enter an ATOMIC section. * * When an ATOMIC section is entered, interrupts with priority lower or equal * to @ref CORE_ATOMIC_BASE_PRIORITY_LEVEL are disabled. * * @note * If @ref CORE_ATOMIC_METHOD is @ref CORE_ATOMIC_METHOD_PRIMASK, this * function is identical to @ref CORE_EnterCritical(). * * @return * The value of BASEPRI register prior to ATOMIC section entry. ******************************************************************************/ SL_WEAK CORE_irqState_t CORE_EnterAtomic(void) { #if (CORE_ATOMIC_METHOD == CORE_ATOMIC_METHOD_BASEPRI) CORE_irqState_t irqState = __get_BASEPRI(); __set_BASEPRI(CORE_ATOMIC_BASE_PRIORITY_LEVEL << (8 - __NVIC_PRIO_BITS)); return irqState; #else CORE_irqState_t irqState = __get_PRIMASK(); __disable_irq(); return irqState; #endif // (CORE_ATOMIC_METHOD == CORE_ATOMIC_METHOD_BASEPRI) } /***************************************************************************//** * @brief * Exit an ATOMIC section. * * @param[in] irqState * The interrupt priority blocking level to restore to BASEPRI when exiting * the ATOMIC section. This value is usually the one returned by a prior * call to @ref CORE_EnterAtomic(). * * @note * If @ref CORE_ATOMIC_METHOD is set to @ref CORE_ATOMIC_METHOD_PRIMASK, this * function is identical to @ref CORE_ExitCritical(). ******************************************************************************/ SL_WEAK void CORE_ExitAtomic(CORE_irqState_t irqState) { #if (CORE_ATOMIC_METHOD == CORE_ATOMIC_METHOD_BASEPRI) __set_BASEPRI(irqState); #else if (irqState == 0U) { __enable_irq(); } #endif // (CORE_ATOMIC_METHOD == CORE_ATOMIC_METHOD_BASEPRI) } /***************************************************************************//** * @brief * Brief interrupt enable/disable sequence to allow handling of * pending interrupts. * * @note * Usully used within an ATOMIC section. * * @note * If @ref CORE_ATOMIC_METHOD is @ref CORE_ATOMIC_METHOD_PRIMASK, this * function is identical to @ref CORE_YieldCritical(). ******************************************************************************/ SL_WEAK void CORE_YieldAtomic(void) { #if (CORE_ATOMIC_METHOD == CORE_ATOMIC_METHOD_BASEPRI) CORE_irqState_t basepri = __get_BASEPRI(); if (basepri >= (CORE_ATOMIC_BASE_PRIORITY_LEVEL << (8 - __NVIC_PRIO_BITS))) { __set_BASEPRI(0); __ISB(); __set_BASEPRI(basepri); } #else if ((__get_PRIMASK() & 1U) != 0U) { __enable_irq(); __ISB(); __disable_irq(); } #endif // (CORE_ATOMIC_METHOD == CORE_ATOMIC_METHOD_BASEPRI) } /***************************************************************************//** * @brief * Enter a NVIC mask section. * * When a NVIC mask section is entered, specified NVIC interrupts * are disabled. * * @param[out] nvicState * Return NVIC interrupts enable mask prior to section entry. * * @param[in] disable * A mask specifying which NVIC interrupts to disable within the section. ******************************************************************************/ void CORE_EnterNvicMask(CORE_nvicMask_t *nvicState, const CORE_nvicMask_t *disable) { CORE_CRITICAL_SECTION( *nvicState = *(CORE_nvicMask_t*)((uint32_t)&NVIC->ICER[0]); *(CORE_nvicMask_t*)((uint32_t)&NVIC->ICER[0]) = *disable; ) } /***************************************************************************//** * @brief * Disable NVIC interrupts. * * @param[in] disable * A mask specifying which NVIC interrupts to disable. ******************************************************************************/ void CORE_NvicDisableMask(const CORE_nvicMask_t *disable) { CORE_CRITICAL_SECTION( *(CORE_nvicMask_t*)((uint32_t)&NVIC->ICER[0]) = *disable; ) } /***************************************************************************//** * @brief * Set current NVIC interrupt enable mask. * * @param[out] enable * A mask specifying which NVIC interrupts are currently enabled. ******************************************************************************/ void CORE_NvicEnableMask(const CORE_nvicMask_t *enable) { CORE_CRITICAL_SECTION( *(CORE_nvicMask_t*)((uint32_t)&NVIC->ISER[0]) = *enable; ) } /***************************************************************************//** * @brief * Brief NVIC interrupt enable/disable sequence to allow handling of * pending interrupts. * * @param[in] enable * A mask specifying which NVIC interrupts to briefly enable. * * @note * Usually used within an NVIC mask section. ******************************************************************************/ void CORE_YieldNvicMask(const CORE_nvicMask_t *enable) { CORE_nvicMask_t nvicMask; // Get current NVIC enable mask. CORE_CRITICAL_SECTION( nvicMask = *(CORE_nvicMask_t*)((uint32_t)&NVIC->ISER[0]); ) // Make a mask with bits set for those interrupts that are currently // disabled but are set in the enable mask. #if (CORE_NVIC_REG_WORDS == 1) nvicMask.a[0] &= enable->a[0]; nvicMask.a[0] = ~nvicMask.a[0] & enable->a[0]; if (nvicMask.a[0] != 0) { #elif (CORE_NVIC_REG_WORDS == 2) nvicMask.a[0] &= enable->a[0]; nvicMask.a[1] &= enable->a[1]; nvicMask.a[0] = ~nvicMask.a[0] & enable->a[0]; nvicMask.a[1] = ~nvicMask.a[1] & enable->a[1]; if ((nvicMask.a[0] != 0U) || (nvicMask.a[1] != 0U)) { #elif (CORE_NVIC_REG_WORDS == 3) nvicMask.a[0] &= enable->a[0]; nvicMask.a[1] &= enable->a[1]; nvicMask.a[2] &= enable->a[2]; nvicMask.a[0] = ~nvicMask.a[0] & enable->a[0]; nvicMask.a[1] = ~nvicMask.a[1] & enable->a[1]; nvicMask.a[2] = ~nvicMask.a[2] & enable->a[2]; if ((nvicMask.a[0] != 0) || (nvicMask.a[1] != 0) || (nvicMask.a[2] != 0)) { #endif // Enable previously disabled interrupts. *(CORE_nvicMask_t*)((uint32_t)&NVIC->ISER[0]) = nvicMask; // Disable those interrupts again. *(CORE_nvicMask_t*)((uint32_t)&NVIC->ICER[0]) = nvicMask; } } /***************************************************************************//** * @brief * Utility function to set an IRQn bit in a NVIC enable/disable mask. * * @param[in] irqN * The @ref IRQn_Type enumerator for the interrupt. * * @param[in,out] mask * The mask to set the interrupt bit in. ******************************************************************************/ void CORE_NvicMaskSetIRQ(IRQn_Type irqN, CORE_nvicMask_t *mask) { EFM_ASSERT(((int)irqN >= 0) && ((int)irqN < EXT_IRQ_COUNT)); mask->a[(unsigned)irqN >> 5] |= 1UL << ((unsigned)irqN & 0x1FUL); } /***************************************************************************//** * @brief * Utility function to clear an IRQn bit in a NVIC enable/disable mask. * * @param[in] irqN * The @ref IRQn_Type enumerator for the interrupt. * * @param[in,out] mask * The mask to clear the interrupt bit in. ******************************************************************************/ void CORE_NvicMaskClearIRQ(IRQn_Type irqN, CORE_nvicMask_t *mask) { EFM_ASSERT(((int)irqN >= 0) && ((int)irqN < EXT_IRQ_COUNT)); mask->a[(unsigned)irqN >> 5] &= ~(1UL << ((unsigned)irqN & 0x1FUL)); } /***************************************************************************//** * @brief * Check whether the current CPU operation mode is handler mode. * * @return * True if the CPU is in handler mode (currently executing an interrupt handler). * @n False if the CPU is in thread mode. ******************************************************************************/ SL_WEAK bool CORE_InIrqContext(void) { return (SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk) != 0U; } /***************************************************************************//** * @brief * Check if a specific interrupt is disabled or blocked. * * @param[in] irqN * The @ref IRQn_Type enumerator for the interrupt to check. * * @return * True if the interrupt is disabled or blocked. ******************************************************************************/ SL_WEAK bool CORE_IrqIsBlocked(IRQn_Type irqN) { uint32_t irqPri, activeIrq; #if (__CORTEX_M >= 3) uint32_t basepri; EFM_ASSERT((irqN >= MemoryManagement_IRQn) && (irqN < (IRQn_Type)EXT_IRQ_COUNT)); #else EFM_ASSERT((irqN >= SVCall_IRQn) && ((IRQn_Type)irqN < EXT_IRQ_COUNT)); #endif if ((__get_PRIMASK() & 1U) != 0U) { return true; // All IRQs are disabled. } if (CORE_NvicIRQDisabled(irqN)) { return true; // The IRQ in question is disabled. } irqPri = NVIC_GetPriority(irqN); #if (__CORTEX_M >= 3) basepri = __get_BASEPRI(); if ((basepri != 0U) && (irqPri >= (basepri >> (8 - __NVIC_PRIO_BITS)))) { return true; // The IRQ in question has too low } // priority vs. BASEPRI. #endif // Check if already in an interrupt handler. If so, an interrupt with a // higher priority (lower priority value) can preempt. activeIrq = (SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk) >> SCB_ICSR_VECTACTIVE_Pos; if (activeIrq != 0U) { if (irqPri >= NVIC_GetPriority((IRQn_Type)(activeIrq - 16U))) { return true; // The IRQ in question has too low } // priority vs. current active IRQ } return false; } /***************************************************************************//** * @brief * Check if interrupts are disabled. * * @return * True if interrupts are disabled. ******************************************************************************/ SL_WEAK bool CORE_IrqIsDisabled(void) { #if (CORE_ATOMIC_METHOD == CORE_ATOMIC_METHOD_PRIMASK) return (__get_PRIMASK() & 1U) == 1U; #elif (CORE_ATOMIC_METHOD == CORE_ATOMIC_METHOD_BASEPRI) return ((__get_PRIMASK() & 1U) == 1U) || (__get_BASEPRI() >= (CORE_ATOMIC_BASE_PRIORITY_LEVEL << (8 - __NVIC_PRIO_BITS))); #endif } /***************************************************************************//** * @brief * Get the current NVIC enable mask state. * * @param[out] mask * The current NVIC enable mask. ******************************************************************************/ void CORE_GetNvicEnabledMask(CORE_nvicMask_t *mask) { CORE_CRITICAL_SECTION( *mask = *(CORE_nvicMask_t*)((uint32_t)&NVIC->ISER[0]); ) } /***************************************************************************//** * @brief * Get NVIC disable state for a given mask. * * @param[in] mask * An NVIC mask to check. * * @return * True if all NVIC interrupt mask bits are clear. ******************************************************************************/ bool CORE_GetNvicMaskDisableState(const CORE_nvicMask_t *mask) { CORE_nvicMask_t nvicMask; CORE_CRITICAL_SECTION( nvicMask = *(CORE_nvicMask_t*)((uint32_t)&NVIC->ISER[0]); ) #if (CORE_NVIC_REG_WORDS == 1) return (mask->a[0] & nvicMask.a[0]) == 0U; #elif (CORE_NVIC_REG_WORDS == 2) return ((mask->a[0] & nvicMask.a[0]) == 0U) && ((mask->a[1] & nvicMask.a[1]) == 0U); #elif (CORE_NVIC_REG_WORDS == 3) return ((mask->a[0] & nvicMask.a[0]) == 0U) && ((mask->a[1] & nvicMask.a[1]) == 0U) && ((mask->a[2] & nvicMask.a[2]) == 0U); #endif } /***************************************************************************//** * @brief * Check if an NVIC interrupt is disabled. * * @param[in] irqN * The @ref IRQn_Type enumerator for the interrupt to check. * * @return * True if the interrupt is disabled. ******************************************************************************/ bool CORE_NvicIRQDisabled(IRQn_Type irqN) { CORE_nvicMask_t *mask; EFM_ASSERT(((int)irqN >= 0) && ((int)irqN < EXT_IRQ_COUNT)); mask = (CORE_nvicMask_t*)((uint32_t)&NVIC->ISER[0]); return (mask->a[(unsigned)irqN >> 5U] & (1UL << ((unsigned)irqN & 0x1FUL))) == 0UL; } /***************************************************************************//** * @brief * Utility function to get the handler for a specific interrupt. * * @param[in] irqN * The @ref IRQn_Type enumerator for the interrupt. * * @return * The handler address. * * @note * Uses the interrupt vector table defined by the current VTOR register value. ******************************************************************************/ void *CORE_GetNvicRamTableHandler(IRQn_Type irqN) { EFM_ASSERT(((int)irqN >= -16) && ((int)irqN < EXT_IRQ_COUNT)); return (void*)((uint32_t*)(((uint32_t*)SCB->VTOR)[(int)irqN + 16])); } /***************************************************************************//** * @brief * Utility function to set the handler for a specific interrupt. * * @param[in] irqN * The @ref IRQn_Type enumerator for the interrupt. * * @param[in] handler * The handler address. * * @note * Uses the interrupt vector table defined by the current VTOR register value. ******************************************************************************/ void CORE_SetNvicRamTableHandler(IRQn_Type irqN, void *handler) { EFM_ASSERT(((int)irqN >= -16) && ((int)irqN < EXT_IRQ_COUNT)); ((uint32_t*)SCB->VTOR)[(int)irqN + 16] = (uint32_t)((uint32_t*)handler); } /***************************************************************************//** * @brief * Initialize an interrupt vector table by copying table entries from a * source to a target table. * * @note This function will set a new VTOR register value. * * @param[in] sourceTable * The address of the source vector table. * * @param[in] sourceSize * A number of entries in the source vector table. * * @param[in] targetTable * The address of the target (new) vector table. * * @param[in] targetSize * A number of entries in the target vector table. * * @param[in] defaultHandler * An address of the interrupt handler used for target entries for which where there * is no corresponding source entry (i.e., the target table is larger than the source * table). * * @param[in] overwriteActive * When true, a target table entry is always overwritten with the * corresponding source entry. If false, a target table entry is only * overwritten if it is zero. This makes it possible for an application * to partly initialize a target table before passing it to this function. * ******************************************************************************/ void CORE_InitNvicVectorTable(uint32_t *sourceTable, uint32_t sourceSize, uint32_t *targetTable, uint32_t targetSize, void *defaultHandler, bool overwriteActive) { uint32_t i; // ASSERT on non SRAM-based target table. EFM_ASSERT(((uint32_t)targetTable >= SRAM_BASE) && ((uint32_t)targetTable < (SRAM_BASE + SRAM_SIZE))); // ASSERT if misaligned with respect to the VTOR register implementation. #if defined(SCB_VTOR_TBLBASE_Msk) EFM_ASSERT(((uint32_t)targetTable & ~(SCB_VTOR_TBLOFF_Msk | SCB_VTOR_TBLBASE_Msk)) == 0U); #else EFM_ASSERT(((uint32_t)targetTable & ~SCB_VTOR_TBLOFF_Msk) == 0U); #endif // ASSERT if misaligned with respect to the vector table size. // The vector table address must be aligned at its size rounded up to nearest 2^n. EFM_ASSERT(((uint32_t)targetTable & ((1UL << (32UL - __CLZ((targetSize * 4UL) - 1UL))) - 1UL)) == 0UL); for (i = 0; i < targetSize; i++) { if (overwriteActive) { // Overwrite target entries. if (i < sourceSize) { // targetSize <= sourceSize targetTable[i] = sourceTable[i]; } else { // targetSize > sourceSize targetTable[i] = (uint32_t)((uint32_t*)defaultHandler); } } else { // Overwrite target entries which are 0. if (i < sourceSize) { // targetSize <= sourceSize if (targetTable[i] == 0U) { targetTable[i] = sourceTable[i]; } } else { // targetSize > sourceSize if (targetTable[i] == 0U) { targetTable[i] = (uint32_t)((uint32_t*)defaultHandler); } } } } SCB->VTOR = (uint32_t)targetTable; } /** @} (end addtogroup CORE) */ /** @} (end addtogroup emlib) */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/emlib/src/em_cryotimer.c.
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/***************************************************************************//** * @file * @brief Ultra Low Energy Timer/Counter (CRYOTIMER) peripheral API * @version 5.7.0 ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * SPDX-License-Identifier: Zlib * * The licensor of this software is Silicon Laboratories Inc. * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be * appreciated but is not required. * 2. Altered source versions must be plainly marked as such, and must not be * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * ******************************************************************************/ #include "em_cryotimer.h" #include "em_bus.h" #if defined(CRYOTIMER_PRESENT) && (CRYOTIMER_COUNT == 1) /***************************************************************************//** * @brief * Initialize the CRYOTIMER. * * @details * Use this function to initialize the CRYOTIMER. * Select a prescaler setting and select a low-frequency oscillator. * See the configuration structure @ref CRYOTIMER_Init_TypeDef for more * details. * * @param[in] init * A pointer to the initialization structure. ******************************************************************************/ void CRYOTIMER_Init(const CRYOTIMER_Init_TypeDef *init) { CRYOTIMER->PERIODSEL = (uint32_t)init->period & _CRYOTIMER_PERIODSEL_MASK; CRYOTIMER->CTRL = ((init->enable ? 1UL : 0UL) << _CRYOTIMER_CTRL_EN_SHIFT) | ((init->debugRun ? 1UL : 0UL) << _CRYOTIMER_CTRL_DEBUGRUN_SHIFT) | ((uint32_t)init->osc << _CRYOTIMER_CTRL_OSCSEL_SHIFT) | ((uint32_t)init->presc << _CRYOTIMER_CTRL_PRESC_SHIFT); CRYOTIMER_EM4WakeupEnable(init->em4Wakeup); } #endif /* defined(CRYOTIMER_PRESENT) && (CRYOTIMER_COUNT > 0) */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/emlib/src/em_crypto.c.
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/***************************************************************************//** * @file * @brief Cryptography accelerator peripheral API * @version 5.7.0 ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * SPDX-License-Identifier: Zlib * * The licensor of this software is Silicon Laboratories Inc. * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be * appreciated but is not required. * 2. Altered source versions must be plainly marked as such, and must not be * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * ******************************************************************************/ #include "em_device.h" #if defined(CRYPTO_COUNT) && (CRYPTO_COUNT > 0) #include "em_crypto.h" #include "em_assert.h" #include <stddef.h> #include <string.h> /***************************************************************************//** * @addtogroup emlib * @{ ******************************************************************************/ /***************************************************************************//** * @addtogroup CRYPTO * @{ ******************************************************************************/ /******************************************************************************* ******************************* DEFINES *********************************** ******************************************************************************/ /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ #define CRYPTO_INSTRUCTIONS_PER_REG (4UL) #define CRYPTO_INSTRUCTIONS_MAX (12UL) #define CRYPTO_INSTRUCTION_REGS (CRYPTO_INSTRUCTIONS_MAX / CRYPTO_INSTRUCTIONS_PER_REG) #define CRYPTO_SHA1_BLOCK_SIZE_IN_BITS (512UL) #define CRYPTO_SHA1_BLOCK_SIZE_IN_BYTES (CRYPTO_SHA1_BLOCK_SIZE_IN_BITS / 8UL) #define CRYPTO_SHA1_BLOCK_SIZE_IN_32BIT_WORDS (CRYPTO_SHA1_BLOCK_SIZE_IN_BYTES / sizeof(uint32_t)) #define CRYPTO_SHA1_DIGEST_SIZE_IN_32BIT_WORDS (CRYPTO_SHA1_DIGEST_SIZE_IN_BYTES / sizeof(uint32_t)) #define CRYPTO_SHA256_BLOCK_SIZE_IN_BITS (512UL) #define CRYPTO_SHA256_BLOCK_SIZE_IN_BYTES (CRYPTO_SHA256_BLOCK_SIZE_IN_BITS / 8UL) #define CRYPTO_SHA256_BLOCK_SIZE_IN_32BIT_WORDS (CRYPTO_SHA256_BLOCK_SIZE_IN_BYTES / sizeof(uint32_t)) #define CRYPTO_SHA256_DIGEST_SIZE_IN_32BIT_WORDS (CRYPTO_SHA256_DIGEST_SIZE_IN_BYTES / sizeof(uint32_t)) #define PARTIAL_OPERAND_WIDTH_LOG2 (7UL) /* 2^7 = 128 */ #define PARTIAL_OPERAND_WIDTH (1UL << PARTIAL_OPERAND_WIDTH_LOG2) #define PARTIAL_OPERAND_WIDTH_MASK (PARTIAL_OPERAND_WIDTH - 1UL) #define PARTIAL_OPERAND_WIDTH_IN_BYTES (PARTIAL_OPERAND_WIDTH / 8UL) #define PARTIAL_OPERAND_WIDTH_IN_32BIT_WORDS (PARTIAL_OPERAND_WIDTH_IN_BYTES / sizeof(uint32_t)) #define SWAP32(x) (__REV(x)) #define CRYPTO_AES_BLOCKSIZE (16UL) /******************************************************************************* *********************** STATIC FUNCTIONS ********************************** ******************************************************************************/ __STATIC_INLINE void CRYPTO_AES_ProcessLoop(CRYPTO_TypeDef *crypto, uint32_t len, CRYPTO_DataReg_TypeDef inReg, const uint8_t * in, CRYPTO_DataReg_TypeDef outReg, uint8_t * out); static void CRYPTO_AES_CBCx(CRYPTO_TypeDef *crypto, uint8_t * out, const uint8_t * in, unsigned int len, const uint8_t * key, const uint8_t * iv, bool encrypt, CRYPTO_KeyWidth_TypeDef keyWidth); static void CRYPTO_AES_CFBx(CRYPTO_TypeDef *crypto, uint8_t * out, const uint8_t * in, unsigned int len, const uint8_t * key, const uint8_t * iv, bool encrypt, CRYPTO_KeyWidth_TypeDef keyWidth); static void CRYPTO_AES_CTRx(CRYPTO_TypeDef *crypto, uint8_t * out, const uint8_t * in, unsigned int len, const uint8_t * key, uint8_t * ctr, CRYPTO_AES_CtrFuncPtr_TypeDef ctrFunc, CRYPTO_KeyWidth_TypeDef keyWidth); static void CRYPTO_AES_ECBx(CRYPTO_TypeDef *crypto, uint8_t * out, const uint8_t * in, unsigned int len, const uint8_t * key, bool encrypt, CRYPTO_KeyWidth_TypeDef keyWidth); static void CRYPTO_AES_OFBx(CRYPTO_TypeDef *crypto, uint8_t * out, const uint8_t * in, unsigned int len, const uint8_t * key, const uint8_t * iv, CRYPTO_KeyWidth_TypeDef keyWidth); __STATIC_INLINE void CRYPTO_DataReadUnaligned(volatile uint32_t * reg, uint8_t * val); __STATIC_INLINE void CRYPTO_DataWriteUnaligned(volatile uint32_t * reg, const uint8_t * val); __STATIC_INLINE void CRYPTO_KeyBufWriteUnaligned(CRYPTO_TypeDef *crypto, const uint8_t * val, CRYPTO_KeyWidth_TypeDef keyWidth); #ifdef USE_VARIABLE_SIZED_DATA_LOADS /***************************************************************************//** * @brief * Write variable sized 32 bit data array (max 128 bits) to a DATAX register. * * @details * Write variable sized 32 bit array (max 128 bits / 4 words) to a DATAX * register in the CRYPTO module. * * @param[in] dataReg The 128 bits DATA register. * @param[in] val Value of the data to write to the DATA register. * @param[in] valSize Size of @ref val in number of 32 bit words. ******************************************************************************/ __STATIC_INLINE void CRYPTO_DataWriteVariableSize(CRYPTO_DataReg_TypeDef dataReg, const CRYPTO_Data_TypeDef val, int valSize) { int i; volatile uint32_t * reg = (volatile uint32_t *) dataReg; if (valSize < 4) { /* Non optimal write of data. */ for (i = 0; i < valSize; i++) { *reg = *val++; } for (; i < 4; i++) { *reg = 0; } } else { CRYPTO_BurstToCrypto(reg, &val[0]); } } #endif /** @endcond */ /******************************************************************************* ************************** GLOBAL FUNCTIONS ******************************* ******************************************************************************/ /***************************************************************************//** * @brief * Set the modulus used for wide modular operations. * * @details * This function sets the modulus to be used by the modular instructions * of the CRYPTO module. * * @param[in] crypto * A pointer to the CRYPTO peripheral register block. * * @param[in] modulusId * A modulus identifier. ******************************************************************************/ void CRYPTO_ModulusSet(CRYPTO_TypeDef * crypto, CRYPTO_ModulusId_TypeDef modulusId) { uint32_t temp = crypto->WAC & (~(_CRYPTO_WAC_MODULUS_MASK | _CRYPTO_WAC_MODOP_MASK)); switch (modulusId) { case cryptoModulusBin256: case cryptoModulusBin128: case cryptoModulusGcmBin128: case cryptoModulusEccB233: case cryptoModulusEccB163: #ifdef _CRYPTO_WAC_MODULUS_ECCBIN233N case cryptoModulusEccB233Order: case cryptoModulusEccB233KOrder: case cryptoModulusEccB163Order: case cryptoModulusEccB163KOrder: #endif crypto->WAC = temp | (uint32_t)modulusId | CRYPTO_WAC_MODOP_BINARY; break; case cryptoModulusEccP256: case cryptoModulusEccP224: case cryptoModulusEccP192: #ifdef _CRYPTO_WAC_MODULUS_ECCPRIME256P case cryptoModulusEccP256Order: case cryptoModulusEccP224Order: case cryptoModulusEccP192Order: #endif crypto->WAC = temp | (uint32_t)modulusId | CRYPTO_WAC_MODOP_REGULAR; break; default: /* Unknown modulus identifier. */ EFM_ASSERT(false); break; } } /***************************************************************************//** * @brief * Read the key value currently used by the CRYPTO module. * * @details * Read 128 bits or 256 bits from the KEY register in the CRYPTO module. * * @param[in] crypto * A pointer to the CRYPTO peripheral register block. * * @param[in] val * A value of the data to write to the KEYBUF register. * * @param[in] keyWidth * Key width - 128 or 256 bits ******************************************************************************/ void CRYPTO_KeyRead(CRYPTO_TypeDef * crypto, CRYPTO_KeyBuf_TypeDef val, CRYPTO_KeyWidth_TypeDef keyWidth) { EFM_ASSERT(&val[0] != NULL); CRYPTO_BurstFromCrypto(&crypto->KEY, &val[0]); if (keyWidth == cryptoKey256Bits) { CRYPTO_BurstFromCrypto(&crypto->KEY, &val[4]); } } /***************************************************************************//** * @brief * Perform a SHA-1 hash operation on a message. * * @details * This function performs a SHA-1 hash operation on the message specified by * msg with length msgLen and returns the message digest in msgDigest. * * @param[in] crypto * A pointer to the CRYPTO peripheral register block. * * @param[in] msg * Message to hash. * * @param[in] msgLen * Length of message in bytes. * * @param[out] msgDigest * A message digest. ******************************************************************************/ void CRYPTO_SHA_1(CRYPTO_TypeDef * crypto, const uint8_t * msg, uint64_t msgLen, CRYPTO_SHA1_Digest_TypeDef msgDigest) { uint32_t temp; uint32_t len; int blockLen; uint32_t shaBlock[CRYPTO_SHA1_BLOCK_SIZE_IN_32BIT_WORDS]; uint8_t * p8ShaBlock = (uint8_t *) shaBlock; /* Initialize the CRYPTO module to do SHA-1. */ crypto->CTRL = CRYPTO_CTRL_SHA_SHA1; crypto->SEQCTRL = 0; crypto->SEQCTRLB = 0; /* Set the result width of the MADD32 operation. */ CRYPTO_ResultWidthSet(crypto, cryptoResult256Bits); /* Write the initialization value to DDATA1. */ crypto->DDATA1 = 0x67452301UL; crypto->DDATA1 = 0xefcdab89UL; crypto->DDATA1 = 0x98badcfeUL; crypto->DDATA1 = 0x10325476UL; crypto->DDATA1 = 0xc3d2e1f0UL; crypto->DDATA1 = 0x00000000UL; crypto->DDATA1 = 0x00000000UL; crypto->DDATA1 = 0x00000000UL; /* Copy data to DDATA0 and select DDATA0 and DDATA1 for SHA operation. */ CRYPTO_EXECUTE_2(crypto, CRYPTO_CMD_INSTR_DDATA1TODDATA0, CRYPTO_CMD_INSTR_SELDDATA0DDATA1); len = (uint32_t)msgLen; while (len >= CRYPTO_SHA1_BLOCK_SIZE_IN_BYTES) { /* Write block to QDATA1. */ CRYPTO_QDataWrite(&crypto->QDATA1BIG, (uint32_t *) msg); /* Execute SHA. */ CRYPTO_EXECUTE_3(crypto, CRYPTO_CMD_INSTR_SHA, CRYPTO_CMD_INSTR_MADD32, CRYPTO_CMD_INSTR_DDATA0TODDATA1); len -= CRYPTO_SHA1_BLOCK_SIZE_IN_BYTES; msg += CRYPTO_SHA1_BLOCK_SIZE_IN_BYTES; } blockLen = 0; /* Build the last (or second to last) block. */ for (; len > 0U; len--) { p8ShaBlock[blockLen++] = *msg++; } /* Append the '1' bit. */ p8ShaBlock[blockLen++] = 0x80; /* If the length is currently above 56 bytes, zeros are appended * then compressed. Then, zeros are padded and length * encoded like normal. */ if (blockLen > 56) { while (blockLen < 64) { p8ShaBlock[blockLen++] = 0; } /* Write block to QDATA1BIG. */ CRYPTO_QDataWrite(&crypto->QDATA1BIG, shaBlock); /* Execute SH. */ CRYPTO_EXECUTE_3(crypto, CRYPTO_CMD_INSTR_SHA, CRYPTO_CMD_INSTR_MADD32, CRYPTO_CMD_INSTR_DDATA0TODDATA1); blockLen = 0; } /* Pad up to 56 bytes of zeros. */ while (blockLen < 56) { p8ShaBlock[blockLen++] = 0; } /* Finally, encode the message length. */ { uint64_t msgLenInBits = msgLen << 3U; temp = (uint32_t)(msgLenInBits >> 32U); *(uint32_t*)&p8ShaBlock[56] = SWAP32(temp); temp = (uint32_t)msgLenInBits & 0xFFFFFFFFUL; *(uint32_t*)&p8ShaBlock[60] = SWAP32(temp); } /* Write block to QDATA1BIG. */ CRYPTO_QDataWrite(&crypto->QDATA1BIG, shaBlock); /* Execute SHA. */ CRYPTO_EXECUTE_3(crypto, CRYPTO_CMD_INSTR_SHA, CRYPTO_CMD_INSTR_MADD32, CRYPTO_CMD_INSTR_DDATA0TODDATA1); /* Read the resulting message digest from DDATA0BIG. */ ((uint32_t*)msgDigest)[0] = crypto->DDATA0BIG; ((uint32_t*)msgDigest)[1] = crypto->DDATA0BIG; ((uint32_t*)msgDigest)[2] = crypto->DDATA0BIG; ((uint32_t*)msgDigest)[3] = crypto->DDATA0BIG; ((uint32_t*)msgDigest)[4] = crypto->DDATA0BIG; crypto->DDATA0BIG; crypto->DDATA0BIG; crypto->DDATA0BIG; } /***************************************************************************//** * @brief * Perform a SHA-256 hash operation on a message. * * @details * This function performs a SHA-256 hash operation on the message specified * by msg with length msgLen and returns the message digest in msgDigest. * * @param[in] crypto * A pointer to the CRYPTO peripheral register block. * * @param[in] msg * A message to hash. * * @param[in] msgLen * The length of message in bytes. * * @param[out] msgDigest * A message digest. ******************************************************************************/ void CRYPTO_SHA_256(CRYPTO_TypeDef * crypto, const uint8_t * msg, uint64_t msgLen, CRYPTO_SHA256_Digest_TypeDef msgDigest) { uint32_t temp; uint32_t len; int blockLen; uint32_t shaBlock[CRYPTO_SHA256_BLOCK_SIZE_IN_32BIT_WORDS]; uint8_t * p8ShaBlock = (uint8_t *) shaBlock; /* Initial values */ shaBlock[0] = 0x6a09e667UL; shaBlock[1] = 0xbb67ae85UL; shaBlock[2] = 0x3c6ef372UL; shaBlock[3] = 0xa54ff53aUL; shaBlock[4] = 0x510e527fUL; shaBlock[5] = 0x9b05688cUL; shaBlock[6] = 0x1f83d9abUL; shaBlock[7] = 0x5be0cd19UL; /* Initialize the CRYPTO module to do SHA-256 (SHA-2). */ crypto->CTRL = CRYPTO_CTRL_SHA_SHA2; crypto->SEQCTRL = 0; crypto->SEQCTRLB = 0; /* Set the result width of the MADD32 operation. */ CRYPTO_ResultWidthSet(crypto, cryptoResult256Bits); /* Write the initialization value to DDATA1. */ CRYPTO_DDataWrite(&crypto->DDATA1, shaBlock); /* Copy data ot DDATA0 and select DDATA0 and DDATA1 for SHA operation. */ CRYPTO_EXECUTE_2(crypto, CRYPTO_CMD_INSTR_DDATA1TODDATA0, CRYPTO_CMD_INSTR_SELDDATA0DDATA1); len = (uint32_t)msgLen; while (len >= CRYPTO_SHA256_BLOCK_SIZE_IN_BYTES) { /* Write block to QDATA1BIG. */ CRYPTO_QDataWrite(&crypto->QDATA1BIG, (uint32_t *) msg); /* Execute SHA. */ CRYPTO_EXECUTE_3(crypto, CRYPTO_CMD_INSTR_SHA, CRYPTO_CMD_INSTR_MADD32, CRYPTO_CMD_INSTR_DDATA0TODDATA1); len -= CRYPTO_SHA256_BLOCK_SIZE_IN_BYTES; msg += CRYPTO_SHA256_BLOCK_SIZE_IN_BYTES; } blockLen = 0; /* Build the last (or second to last) block. */ for (; len > 0U; len--) { p8ShaBlock[blockLen++] = *msg++; } /* Append the '1' bit. */ p8ShaBlock[blockLen++] = 0x80; /* If the length is currently above 56 bytes, zeros are appended * then compressed. Then, zeros are padded and length * encoded like normal. */ if (blockLen > 56) { while (blockLen < 64) { p8ShaBlock[blockLen++] = 0; } /* Write block to QDATA1BIG. */ CRYPTO_QDataWrite(&crypto->QDATA1BIG, shaBlock); /* Execute SHA. */ CRYPTO_EXECUTE_3(crypto, CRYPTO_CMD_INSTR_SHA, CRYPTO_CMD_INSTR_MADD32, CRYPTO_CMD_INSTR_DDATA0TODDATA1); blockLen = 0; } /* Pad up to 56 bytes of zeros. */ while (blockLen < 56) { p8ShaBlock[blockLen++] = 0; } /* Finally, encode the message length. */ { uint64_t msgLenInBits = msgLen << 3; temp = (uint32_t)(msgLenInBits >> 32); *(uint32_t *)&p8ShaBlock[56] = SWAP32(temp); temp = (uint32_t)msgLenInBits & 0xFFFFFFFFUL; *(uint32_t *)&p8ShaBlock[60] = SWAP32(temp); } /* Write the final block to QDATA1BIG. */ CRYPTO_QDataWrite(&crypto->QDATA1BIG, shaBlock); /* Execute SHA. */ CRYPTO_EXECUTE_3(crypto, CRYPTO_CMD_INSTR_SHA, CRYPTO_CMD_INSTR_MADD32, CRYPTO_CMD_INSTR_DDATA0TODDATA1); /* Read the resulting message digest from DDATA0BIG. */ CRYPTO_DDataRead(&crypto->DDATA0BIG, (uint32_t *)msgDigest); } /***************************************************************************//** * @brief * Set the 32 bit word array to zero. * * @param[in] words32bits A pointer to the 32 bit word array. * @param[in] num32bitWords A number of 32 bit words in array. ******************************************************************************/ __STATIC_INLINE void cryptoBigintZeroize(uint32_t * words32bits, unsigned num32bitWords) { while (num32bitWords > 0UL) { num32bitWords--; *words32bits++ = 0; } } /***************************************************************************//** * @brief * Increment value of 32bit word array by one. * * @param[in] words32bits Pointer to 32bit word array * @param[in] num32bitWords Number of 32bit words in array ******************************************************************************/ __STATIC_INLINE void cryptoBigintIncrement(uint32_t * words32bits, unsigned num32bitWords) { unsigned i; for (i = 0; i < num32bitWords; i++) { if (++words32bits[i] != 0UL) { break; } } return; } /***************************************************************************//** * @brief * Multiply two big integers. * * @details * This function uses the CRYPTO unit to multiply two big integer operands. * If USE_VARIABLE_SIZED_DATA_LOADS is defined, the sizes of the operands * may be any multiple of 32 bits. If USE_VARIABLE_SIZED_DATA_LOADS is _not_ * defined, the sizes of the operands must be a multiple of 128 bits. * * @param[in] A An operand A * @param[in] aSize The size of the operand A in bits * @param[in] B An operand B * @param[in] bSize The size of the operand B in bits * @param[out] R The result of multiplication * @param[in] rSize The size of the result buffer R in bits ******************************************************************************/ void CRYPTO_Mul(CRYPTO_TypeDef * crypto, uint32_t * A, int aSize, uint32_t * B, int bSize, uint32_t * R, int rSize) { unsigned i, j; /**************** Initializations ******************/ #ifdef USE_VARIABLE_SIZED_DATA_LOADS unsigned numWordsLastOperandA = ((unsigned)aSize & PARTIAL_OPERAND_WIDTH_MASK) >> 5; unsigned numPartialOperandsA = numWordsLastOperandA ? ((unsigned)aSize >> PARTIAL_OPERAND_WIDTH_LOG2) + 1 : (unsigned)aSize >> PARTIAL_OPERAND_WIDTH_LOG2; unsigned numWordsLastOperandB = ((unsigned)bSize & PARTIAL_OPERAND_WIDTH_MASK) >> 5; unsigned numPartialOperandsB = numWordsLastOperandB ? ((unsigned)bSize >> PARTIAL_OPERAND_WIDTH_LOG2) + 1 : (unsigned)bSize >> PARTIAL_OPERAND_WIDTH_LOG2; unsigned numWordsLastOperandR = ((unsigned)rSize & PARTIAL_OPERAND_WIDTH_MASK) >> 5; unsigned numPartialOperandsR = numWordsLastOperandR ? ((unsigned)rSize >> PARTIAL_OPERAND_WIDTH_LOG2) + 1 : (unsigned)rSize >> PARTIAL_OPERAND_WIDTH_LOG2; EFM_ASSERT(numPartialOperandsA + numPartialOperandsB <= numPartialOperandsR); #else unsigned numPartialOperandsA = (unsigned)aSize >> PARTIAL_OPERAND_WIDTH_LOG2; unsigned numPartialOperandsB = (unsigned)bSize >> PARTIAL_OPERAND_WIDTH_LOG2; EFM_ASSERT(((unsigned)aSize & PARTIAL_OPERAND_WIDTH_MASK) == 0UL); EFM_ASSERT(((unsigned)bSize & PARTIAL_OPERAND_WIDTH_MASK) == 0UL); #endif EFM_ASSERT(aSize + bSize <= rSize); /* Set R to zero. */ cryptoBigintZeroize(R, (unsigned)rSize >> 5); /* Set the multiplication width. */ crypto->WAC = CRYPTO_WAC_MULWIDTH_MUL128 | CRYPTO_WAC_RESULTWIDTH_256BIT; /* Set up DMA request signaling for MCU to run in parallel with the CRYPTO instruction sequence execution and prepare data loading which can take place immediately when CRYPTO is ready inside the instruction sequence. */ crypto->CTRL = CRYPTO_CTRL_DMA0RSEL_DATA0 | CRYPTO_CTRL_DMA0MODE_FULL | CRYPTO_CTRL_DMA1RSEL_DATA1 | CRYPTO_CTRL_DMA1MODE_FULL; CRYPTO_EXECUTE_4(crypto, CRYPTO_CMD_INSTR_CCLR, /* Carry = 0 */ CRYPTO_CMD_INSTR_CLR, /* DDATA0 = 0 */ /* clear result accumulation register */ CRYPTO_CMD_INSTR_DDATA0TODDATA2, CRYPTO_CMD_INSTR_SELDDATA1DDATA3); /* register map: DDATA0: working register DDATA1: B(j) DDATA2: R(i+j+1) and R(i+j), combined with DMA entry for B(j) DDATA3: A(i) */ CRYPTO_SEQ_LOAD_10(crypto, /* Temporarily load the partial operand B(j) to DATA0. */ /* R(i+j+1) is still in DATA1 */ CRYPTO_CMD_INSTR_DMA0TODATA, /* Move B(j) to DDATA1. */ CRYPTO_CMD_INSTR_DDATA2TODDATA1, /* Restore the previous partial result (now R(i+j)). */ CRYPTO_CMD_INSTR_DATA1TODATA0, /* Load the next partial result R(i+j+1). */ CRYPTO_CMD_INSTR_DMA1TODATA, /* Execute the partial multiplication A(i)inDDATA1 * B(j)inDDATA3.*/ CRYPTO_CMD_INSTR_MULO, /* Add the result to the previous partial result. */ /* AND take the previous carry value into account */ /* at the right place (bit 128, ADDIC instruction. */ CRYPTO_CMD_INSTR_SELDDATA0DDATA2, CRYPTO_CMD_INSTR_ADDIC, /* Save the new partial result (lower half). */ CRYPTO_CMD_INSTR_DDATA0TODDATA2, CRYPTO_CMD_INSTR_DATATODMA0, /* Reset the operand selector for next.*/ CRYPTO_CMD_INSTR_SELDDATA2DDATA3 ); /**************** End Initializations ******************/ for (i = 0; i < numPartialOperandsA; i++) { /* Load the partial operand #1 A>>(i*PARTIAL_OPERAND_WIDTH) to DDATA1. */ #ifdef USE_VARIABLE_SIZED_DATA_LOADS if ( (numWordsLastOperandA != 0) && (i == numPartialOperandsA - 1) ) { CRYPTO_DataWriteVariableSize(&crypto->DATA2, &A[i * PARTIAL_OPERAND_WIDTH_IN_32BIT_WORDS], numWordsLastOperandA); } else { CRYPTO_DataWrite(&crypto->DATA2, &A[i * PARTIAL_OPERAND_WIDTH_IN_32BIT_WORDS]); } #else CRYPTO_DataWrite(&crypto->DATA2, &A[i * PARTIAL_OPERAND_WIDTH_IN_32BIT_WORDS]); #endif /* Load the partial result in R>>(i*PARTIAL_OPERAND_WIDTH) to DATA1. */ #ifdef USE_VARIABLE_SIZED_DATA_LOADS if ( (numWordsLastOperandR != 0) && (i == numPartialOperandsR - 1) ) { CRYPTO_DataWriteVariableSize(&crypto->DATA1, &R[i * PARTIAL_OPERAND_WIDTH_IN_32BIT_WORDS], numWordsLastOperandR); } else { CRYPTO_DataWrite(&crypto->DATA1, &R[i * PARTIAL_OPERAND_WIDTH_IN_32BIT_WORDS]); } #else CRYPTO_DataWrite(&crypto->DATA1, &R[i * PARTIAL_OPERAND_WIDTH_IN_32BIT_WORDS]); #endif /* Clear carry. */ crypto->CMD = CRYPTO_CMD_INSTR_CCLR; /* Set up the number of sequence iterations and block size. */ crypto->SEQCTRL = CRYPTO_SEQCTRL_BLOCKSIZE_16BYTES | (PARTIAL_OPERAND_WIDTH_IN_BYTES * numPartialOperandsB); /* Execute the MULtiply instruction sequence. */ CRYPTO_InstructionSequenceExecute(crypto); for (j = 0; j < numPartialOperandsB; j++) { /* Load the partial operand 2 B>>(j*`PARTIAL_OPERAND_WIDTH) to DDATA2 (via DATA0). */ #ifdef USE_VARIABLE_SIZED_DATA_LOADS if ( (numWordsLastOperandB != 0) && (j == numPartialOperandsB - 1) ) { CRYPTO_DataWriteVariableSize(&crypto->DATA0, &B[j * PARTIAL_OPERAND_WIDTH_IN_32BIT_WORDS], numWordsLastOperandB); } else { CRYPTO_DataWrite(&crypto->DATA0, &B[j * PARTIAL_OPERAND_WIDTH_IN_32BIT_WORDS]); } #else CRYPTO_DataWrite(&crypto->DATA0, &B[j * PARTIAL_OPERAND_WIDTH_IN_32BIT_WORDS]); #endif /* Load the most significant partial result R>>((i+j+1)*`PARTIAL_OPERAND_WIDTH) into DATA1. */ #ifdef USE_VARIABLE_SIZED_DATA_LOADS if ( (numWordsLastOperandR != 0) && ( (i + j + 1U) == numPartialOperandsR - 1U) ) { CRYPTO_DataWriteVariableSize(&crypto->DATA1, &R[(i + j + 1U) * PARTIAL_OPERAND_WIDTH_IN_32BIT_WORDS], numWordsLastOperandR); } else { CRYPTO_DataWrite(&crypto->DATA1, &R[(i + j + 1U) * PARTIAL_OPERAND_WIDTH_IN_32BIT_WORDS]); } #else CRYPTO_DataWrite(&crypto->DATA1, &R[(i + j + 1U) * PARTIAL_OPERAND_WIDTH_IN_32BIT_WORDS]); #endif /* Store the least significant partial result. */ CRYPTO_DataRead(&crypto->DATA0, &R[(i + j) * PARTIAL_OPERAND_WIDTH_IN_32BIT_WORDS]); } /* for (j=0; j<numPartialOperandsB; j++) */ /* Handle carry at the end of the inner loop. */ if (CRYPTO_CarryIsSet(crypto)) { cryptoBigintIncrement(&R[(i + numPartialOperandsB + 1U) * PARTIAL_OPERAND_WIDTH_IN_32BIT_WORDS], (numPartialOperandsA - i - 1U) * PARTIAL_OPERAND_WIDTH_IN_32BIT_WORDS); } CRYPTO_DataRead(&crypto->DATA1, &R[(i + numPartialOperandsB) * PARTIAL_OPERAND_WIDTH_IN_32BIT_WORDS]); } /* for (i=0; i<numPartialOperandsA; i++) */ } /***************************************************************************//** * @brief * AES Cipher-block chaining (CBC) cipher mode encryption/decryption, 128 bit key. * * @details * Encryption: * @verbatim * Plaintext Plaintext * | | * V V * InitVector ->XOR +-------------->XOR * | | | * V | V * +--------------+ | +--------------+ * Key ->| Block cipher | | Key ->| Block cipher | * | encryption | | | encryption | * +--------------+ | +--------------+ * |---------+ | * V V * Ciphertext Ciphertext * @endverbatim * Decryption: * @verbatim * Ciphertext Ciphertext * |----------+ | * V | V * +--------------+ | +--------------+ * Key ->| Block cipher | | Key ->| Block cipher | * | decryption | | | decryption | * +--------------+ | +--------------+ * | | | * V | V * InitVector ->XOR +-------------->XOR * | | * V V * Plaintext Plaintext * @endverbatim * See general comments on layout and byte ordering of parameters. * * @param[in] crypto * A pointer to the CRYPTO peripheral register block. * * @param[out] out * A buffer to place encrypted/decrypted data. Must be at least @p len long. It * may be set equal to @p in, in which case the input buffer is overwritten. * * @param[in] in * A buffer holding data to encrypt/decrypt. Must be at least @p len long. * * @param[in] len * A number of bytes to encrypt/decrypt. Must be a multiple of 16. * * @param[in] key * When encrypting, this is the 128 bit encryption key. When * decrypting, this is the 128 bit decryption key. The decryption key may * be generated from the encryption key with CRYPTO_AES_DecryptKey128(). * If this argument is null, the key will not be loaded, as it is assumed * the key has been loaded into KEYHA previously. * * @param[in] iv * 128 bit initialization vector to use. * * @param[in] encrypt * Set to true to encrypt, false to decrypt. ******************************************************************************/ void CRYPTO_AES_CBC128(CRYPTO_TypeDef * crypto, uint8_t * out, const uint8_t * in, unsigned int len, const uint8_t * key, const uint8_t * iv, bool encrypt) { crypto->CTRL = CRYPTO_CTRL_AES_AES128; CRYPTO_AES_CBCx(crypto, out, in, len, key, iv, encrypt, cryptoKey128Bits); } /***************************************************************************//** * @brief * AES Cipher-block chaining (CBC) cipher mode encryption/decryption, 256 bit * key. * * @details * See CRYPTO_AES_CBC128() for the CBC figure. * * See general comments on layout and byte ordering of parameters. * * @param[in] crypto * A pointer to the CRYPTO peripheral register block. * * @param[out] out * A buffer to place encrypted/decrypted data. Must be at least @p len long. It * may be set equal to @p in, in which case the input buffer is overwritten. * * @param[in] in * A buffer holding data to encrypt/decrypt. Must be at least @p len long. * * @param[in] len * A number of bytes to encrypt/decrypt. Must be a multiple of 16. * * @param[in] key * When encrypting, this is the 256 bit encryption key. When * decrypting, this is the 256 bit decryption key. The decryption key may * be generated from the encryption key with CRYPTO_AES_DecryptKey256(). * * @param[in] iv * 128 bit initialization vector to use. * * @param[in] encrypt * Set to true to encrypt, false to decrypt. ******************************************************************************/ void CRYPTO_AES_CBC256(CRYPTO_TypeDef * crypto, uint8_t * out, const uint8_t * in, unsigned int len, const uint8_t * key, const uint8_t * iv, bool encrypt) { crypto->CTRL = CRYPTO_CTRL_AES_AES256; CRYPTO_AES_CBCx(crypto, out, in, len, key, iv, encrypt, cryptoKey256Bits); } /***************************************************************************//** * @brief * AES Cipher feedback (CFB) cipher mode encryption/decryption, 128 bit key. * * @details * Encryption: * @verbatim * InitVector +----------------+ * | | | * V | V * +--------------+ | +--------------+ * Key ->| Block cipher | | Key ->| Block cipher | * | encryption | | | encryption | * +--------------+ | +--------------+ * | | | * V | V * Plaintext ->XOR | Plaintext ->XOR * |---------+ | * V V * Ciphertext Ciphertext * @endverbatim * Decryption: * @verbatim * InitVector +----------------+ * | | | * V | V * +--------------+ | +--------------+ * Key ->| Block cipher | | Key ->| Block cipher | * | encryption | | | encryption | * +--------------+ | +--------------+ * | | | * V | V * XOR<- Ciphertext XOR<- Ciphertext * | | * V V * Plaintext Plaintext * @endverbatim * See general comments on layout and byte ordering of parameters. * * @param[in] crypto * A pointer to the CRYPTO peripheral register block. * * @param[out] out * A buffer to place encrypted/decrypted data. Must be at least @p len long. It * may be set equal to @p in, in which case the input buffer is overwritten. * * @param[in] in * A buffer holding data to encrypt/decrypt. Must be at least @p len long. * * @param[in] len * A number of bytes to encrypt/decrypt. Must be a multiple of 16. * * @param[in] key * 128 bit encryption key is used for both encryption and decryption modes. * * @param[in] iv * 128 bit initialization vector to use. * * @param[in] encrypt * Set to true to encrypt, false to decrypt. ******************************************************************************/ void CRYPTO_AES_CFB128(CRYPTO_TypeDef * crypto, uint8_t * out, const uint8_t * in, unsigned int len, const uint8_t * key, const uint8_t * iv, bool encrypt) { crypto->CTRL = CRYPTO_CTRL_AES_AES128; CRYPTO_AES_CFBx(crypto, out, in, len, key, iv, encrypt, cryptoKey128Bits); } /***************************************************************************//** * @brief * AES Cipher feedback (CFB) cipher mode encryption/decryption, 256 bit key. * * @details * See CRYPTO_AES_CFB128() for the CFB figure. * * See general comments on layout and byte ordering of parameters. * * @param[in] crypto * A pointer to the CRYPTO peripheral register block. * * @param[out] out * A buffer to place encrypted/decrypted data. Must be at least @p len long. It * may be set equal to @p in, in which case the input buffer is overwritten. * * @param[in] in * A buffer holding data to encrypt/decrypt. Must be at least @p len long. * * @param[in] len * A number of bytes to encrypt/decrypt. Must be a multiple of 16. * * @param[in] key * 256 bit encryption key is used for both encryption and decryption modes. * * @param[in] iv * 128 bit initialization vector to use. * * @param[in] encrypt * Set to true to encrypt, false to decrypt. ******************************************************************************/ void CRYPTO_AES_CFB256(CRYPTO_TypeDef * crypto, uint8_t * out, const uint8_t * in, unsigned int len, const uint8_t * key, const uint8_t * iv, bool encrypt) { crypto->CTRL = CRYPTO_CTRL_AES_AES256; CRYPTO_AES_CFBx(crypto, out, in, len, key, iv, encrypt, cryptoKey256Bits); } /***************************************************************************//** * @brief * AES Counter (CTR) cipher mode encryption/decryption, 128 bit key. * * @details * Encryption: * @verbatim * Counter Counter * | | * V V * +--------------+ +--------------+ * Key ->| Block cipher | Key ->| Block cipher | * | encryption | | encryption | * +--------------+ +--------------+ * | | * Plaintext ->XOR Plaintext ->XOR * | | * V V * Ciphertext Ciphertext * @endverbatim * Decryption: * @verbatim * Counter Counter * | | * V V * +--------------+ +--------------+ * Key ->| Block cipher | Key ->| Block cipher | * | encryption | | encryption | * +--------------+ +--------------+ * | | * Ciphertext ->XOR Ciphertext ->XOR * | | * V V * Plaintext Plaintext * @endverbatim * See general comments on layout and byte ordering of parameters. * * @param[in] crypto * A pointer to CRYPTO peripheral register block. * * @param[out] out * A buffer to place encrypted/decrypted data. Must be at least @p len long. It * may be set equal to @p in, in which case the input buffer is overwritten. * * @param[in] in * A buffer holding data to encrypt/decrypt. Must be at least @p len long. * * @param[in] len * A number of bytes to encrypt/decrypt. Must be a multiple of 16. * * @param[in] key * 128 bit encryption key. * If this argument is null, the key will not be loaded, as it is assumed * the key has been loaded into KEYHA previously. * * @param[in,out] ctr * 128 bit initial counter value. The counter is updated after each AES * block encoding through use of @p ctrFunc. * * @param[in] ctrFunc * A function used to update the counter value. Not supported by CRYPTO. * This parameter is included for backwards compatibility with * the EFM32 em_aes.h API. ******************************************************************************/ void CRYPTO_AES_CTR128(CRYPTO_TypeDef * crypto, uint8_t * out, const uint8_t * in, unsigned int len, const uint8_t * key, uint8_t * ctr, CRYPTO_AES_CtrFuncPtr_TypeDef ctrFunc) { crypto->CTRL = CRYPTO_CTRL_AES_AES128; CRYPTO_AES_CTRx(crypto, out, in, len, key, ctr, ctrFunc, cryptoKey128Bits); } /***************************************************************************//** * @brief * AES Counter (CTR) cipher mode encryption/decryption, 256 bit key. * * @details * See CRYPTO_AES_CTR128() for CTR figure. * * See general comments on layout and byte ordering of parameters. * * @param[in] crypto * A pointer to the CRYPTO peripheral register block. * * @param[out] out * A buffer to place encrypted/decrypted data. Must be at least @p len long. It * may be set equal to @p in, in which case the input buffer is overwritten. * * @param[in] in * A buffer holding data to encrypt/decrypt. Must be at least @p len long. * * @param[in] len * A number of bytes to encrypt/decrypt. Must be a multiple of 16. * * @param[in] key * 256 bit encryption key. * * @param[in,out] ctr * 128 bit initial counter value. The counter is updated after each AES * block encoding through use of @p ctrFunc. * * @param[in] ctrFunc * A function used to update counter value. Not supported by CRYPTO. * This parameter is included in order for backwards compatibility with * the EFM32 em_aes.h API. ******************************************************************************/ void CRYPTO_AES_CTR256(CRYPTO_TypeDef * crypto, uint8_t * out, const uint8_t * in, unsigned int len, const uint8_t * key, uint8_t * ctr, CRYPTO_AES_CtrFuncPtr_TypeDef ctrFunc) { crypto->CTRL = CRYPTO_CTRL_AES_AES256; CRYPTO_AES_CTRx(crypto, out, in, len, key, ctr, ctrFunc, cryptoKey256Bits); } /***************************************************************************//** * @brief * Update the last 32 bits of 128 bit counter by incrementing with 1. * * @details * Notice that no special consideration is given to the possible wrap around. If * 32 least significant bits are 0xFFFFFFFF, they will be updated to 0x00000000, * ignoring overflow. * * See general comments on layout and byte ordering of parameters. * * @param[in,out] ctr * A buffer holding 128 bit counter to be updated. ******************************************************************************/ void CRYPTO_AES_CTRUpdate32Bit(uint8_t * ctr) { uint32_t * _ctr = (uint32_t *) ctr; _ctr[3] = __REV(__REV(_ctr[3]) + 1U); } /***************************************************************************//** * @brief * Generate 128 bit AES decryption key from 128 bit encryption key. The * decryption key is used for some cipher modes when decrypting. * * @details * See general comments on layout and byte ordering of parameters. * * @param[in] crypto * A pointer to the CRYPTO peripheral register block. * * @param[out] out * A buffer to place 128 bit decryption key. Must be at least 16 bytes long. It * may be set equal to @p in, in which case the input buffer is overwritten. * * @param[in] in * A buffer holding 128 bit encryption key. Must be at least 16 bytes long. ******************************************************************************/ void CRYPTO_AES_DecryptKey128(CRYPTO_TypeDef * crypto, uint8_t * out, const uint8_t * in) { /* Setup CRYPTO in AES-128 mode. */ crypto->CTRL = CRYPTO_CTRL_AES_AES128; /* Load key */ CRYPTO_DataWriteUnaligned(&crypto->KEYBUF, in); /* Do dummy encryption to generate decrypt key */ crypto->CMD = CRYPTO_CMD_INSTR_AESENC; /* Save decryption key */ CRYPTO_DataReadUnaligned(&crypto->KEY, out); } /***************************************************************************//** * @brief * Generate 256 bit AES decryption key from 256 bit encryption key. The * decryption key is used for some cipher modes when decrypting. * * @details * See general comments on layout and byte ordering of parameters. * * @param[in] crypto * A pointer to the CRYPTO peripheral register block. * * @param[out] out * A buffer to place 256 bit decryption key. Must be at least 32 bytes long. It * may be set equal to @p in, in which case the input buffer is overwritten. * * @param[in] in * A buffer holding 256 bit encryption key. Must be at least 32 bytes long. ******************************************************************************/ void CRYPTO_AES_DecryptKey256(CRYPTO_TypeDef * crypto, uint8_t * out, const uint8_t * in) { /* Set up CRYPTO in AES-256 mode. */ crypto->CTRL = CRYPTO_CTRL_AES_AES256; /* Load the key. */ CRYPTO_DataWriteUnaligned(&crypto->KEYBUF, in); CRYPTO_DataWriteUnaligned(&crypto->KEYBUF, &in[16]); /* Do dummy encryption to generate a decrypt key. */ crypto->CMD = CRYPTO_CMD_INSTR_AESENC; /* Save the decryption key. */ CRYPTO_DataReadUnaligned(&crypto->KEY, out); CRYPTO_DataReadUnaligned(&crypto->KEY, &out[16]); } /***************************************************************************//** * @brief * AES Electronic Codebook (ECB) cipher mode encryption/decryption, * 128 bit key. * * @details * Encryption: * @verbatim * Plaintext Plaintext * | | * V V * +--------------+ +--------------+ * Key ->| Block cipher | Key ->| Block cipher | * | encryption | | encryption | * +--------------+ +--------------+ * | | * V V * Ciphertext Ciphertext * @endverbatim * Decryption: * @verbatim * Ciphertext Ciphertext * | | * V V * +--------------+ +--------------+ * Key ->| Block cipher | Key ->| Block cipher | * | decryption | | decryption | * +--------------+ +--------------+ * | | * V V * Plaintext Plaintext * @endverbatim * See general comments on layout and byte ordering of parameters. * * @param[in] crypto * A pointer to the CRYPTO peripheral register block. * * @param[out] out * A buffer to place encrypted/decrypted data. Must be at least @p len long. It * may be set equal to @p in, in which case the input buffer is overwritten. * * @param[in] in * A buffer holding data to encrypt/decrypt. Must be at least @p len long. * * @param[in] len * A number of bytes to encrypt/decrypt. Must be a multiple of 16. * * @param[in] key * When encrypting, this is the 128 bit encryption key. When * decrypting, this is the 128 bit decryption key. The decryption key may * be generated from the encryption key with CRYPTO_AES_DecryptKey128(). * * @param[in] encrypt * Set to true to encrypt, false to decrypt. ******************************************************************************/ void CRYPTO_AES_ECB128(CRYPTO_TypeDef * crypto, uint8_t * out, const uint8_t * in, unsigned int len, const uint8_t * key, bool encrypt) { crypto->CTRL = CRYPTO_CTRL_AES_AES128; CRYPTO_AES_ECBx(crypto, out, in, len, key, encrypt, cryptoKey128Bits); } /***************************************************************************//** * @brief * AES Electronic Codebook (ECB) cipher mode encryption/decryption, * 256 bit key. * * @details * See CRYPTO_AES_ECB128() for ECB figure. * * See general comments on layout and byte ordering of parameters. * * @param[in] crypto * A pointer to the CRYPTO peripheral register block. * * @param[out] out * A buffer to place encrypted/decrypted data. Must be at least @p len long. It * may be set equal to @p in, in which case the input buffer is overwritten. * * @param[in] in * A buffer holding data to encrypt/decrypt. Must be at least @p len long. * * @param[in] len * A number of bytes to encrypt/decrypt. Must be a multiple of 16. * * @param[in] key * When encrypting, this is the 256 bit encryption key. When * decrypting, this is the 256 bit decryption key. The decryption key may * be generated from the encryption key with CRYPTO_AES_DecryptKey256(). * * @param[in] encrypt * Set to true to encrypt, false to decrypt. ******************************************************************************/ void CRYPTO_AES_ECB256(CRYPTO_TypeDef * crypto, uint8_t * out, const uint8_t * in, unsigned int len, const uint8_t * key, bool encrypt) { crypto->CTRL = CRYPTO_CTRL_AES_AES256; CRYPTO_AES_ECBx(crypto, out, in, len, key, encrypt, cryptoKey256Bits); } /***************************************************************************//** * @brief * AES Output feedback (OFB) cipher mode encryption/decryption, 128 bit key. * * @details * Encryption: * @verbatim * InitVector +----------------+ * | | | * V | V * +--------------+ | +--------------+ * Key ->| Block cipher | | Key ->| Block cipher | * | encryption | | | encryption | * +--------------+ | +--------------+ * | | | * |---------+ | * V V * Plaintext ->XOR Plaintext ->XOR * | | * V V * Ciphertext Ciphertext * @endverbatim * Decryption: * @verbatim * InitVector +----------------+ * | | | * V | V * +--------------+ | +--------------+ * Key ->| Block cipher | | Key ->| Block cipher | * | encryption | | | encryption | * +--------------+ | +--------------+ * | | | * |---------+ | * V V * Ciphertext ->XOR Ciphertext ->XOR * | | * V V * Plaintext Plaintext * @endverbatim * See general comments on layout and byte ordering of parameters. * * @param[in] crypto * A pointer to the CRYPTO peripheral register block. * * @param[out] out * A buffer to place encrypted/decrypted data. Must be at least @p len long. It * may be set equal to @p in, in which case the input buffer is overwritten. * * @param[in] in * A buffer holding data to encrypt/decrypt. Must be at least @p len long. * * @param[in] len * A number of bytes to encrypt/decrypt. Must be a multiple of 16. * * @param[in] key * 128 bit encryption key. * * @param[in] iv * 128 bit initialization vector to use. ******************************************************************************/ void CRYPTO_AES_OFB128(CRYPTO_TypeDef * crypto, uint8_t * out, const uint8_t * in, unsigned int len, const uint8_t * key, const uint8_t * iv) { crypto->CTRL = CRYPTO_CTRL_AES_AES128; CRYPTO_AES_OFBx(crypto, out, in, len, key, iv, cryptoKey128Bits); } /***************************************************************************//** * @brief * AES Output feedback (OFB) cipher mode encryption/decryption, 256 bit key. * * @details * See CRYPTO_AES_OFB128() for OFB figure. * * See general comments on layout and byte ordering of parameters. * * @param[in] crypto * A pointer to CRYPTO peripheral register block. * * @param[out] out * A buffer to place encrypted/decrypted data. Must be at least @p len long. It * may be set equal to @p in, in which case the input buffer is overwritten. * * @param[in] in * A buffer holding data to encrypt/decrypt. Must be at least @p len long. * * @param[in] len * A number of bytes to encrypt/decrypt. Must be a multiple of 16. * * @param[in] key * 256 bit encryption key. * * @param[in] iv * 128 bit initialization vector to use. ******************************************************************************/ void CRYPTO_AES_OFB256(CRYPTO_TypeDef * crypto, uint8_t * out, const uint8_t * in, unsigned int len, const uint8_t * key, const uint8_t * iv) { crypto->CTRL = CRYPTO_CTRL_AES_AES256; CRYPTO_AES_OFBx(crypto, out, in, len, key, iv, cryptoKey256Bits); } /******************************************************************************* ************************** LOCAL FUNCTIONS ******************************* ******************************************************************************/ /***************************************************************************//** * @brief * Read 128 bits of data from a DATAX register in the CRYPTO module. * * @param[in] dataReg The 128 bit DATA register. * @param[out] val Location where to store the value in memory. ******************************************************************************/ __STATIC_INLINE void CRYPTO_DataReadUnaligned(volatile uint32_t * reg, uint8_t * val) { /* Check data is 32bit aligned, if not, read into temporary buffer and then move to user buffer. */ if ((uint32_t)val & 0x3) { uint32_t temp[4]; CRYPTO_DataRead(reg, temp); memcpy(val, temp, 16); } else { CRYPTO_DataRead(reg, (uint32_t *)val); } } /***************************************************************************//** * @brief * Write 128 bits of data to a DATAX register in the CRYPTO module. * * @param[in] dataReg The 128 bit DATA register. * @param[in] val Pointer to value to write to the DATA register. ******************************************************************************/ __STATIC_INLINE void CRYPTO_DataWriteUnaligned(volatile uint32_t * reg, const uint8_t * val) { /* Check data is 32bit aligned, if not move to temporary buffer before writing.*/ if ((uint32_t)val & 0x3) { uint32_t temp[4]; memcpy(temp, val, 16); CRYPTO_DataWrite(reg, temp); } else { CRYPTO_DataWrite(reg, (const uint32_t *)val); } } /***************************************************************************//** * @brief * Set the key value to be used by the CRYPTO module. * * @details * Write 128 or 256 bit key to the KEYBUF register in the crypto module. * * @param[in] crypto * A pointer to the CRYPTO peripheral register block. * * @param[in] val * Pointer to value to write to the KEYBUF register. * * @param[in] keyWidth * Key width - 128 or 256 bits. ******************************************************************************/ __STATIC_INLINE void CRYPTO_KeyBufWriteUnaligned(CRYPTO_TypeDef *crypto, const uint8_t * val, CRYPTO_KeyWidth_TypeDef keyWidth) { /* Check if key val buffer is 32bit aligned, if not move to temporary aligned buffer before writing.*/ if ((uint32_t)val & 0x3) { CRYPTO_KeyBuf_TypeDef temp; if (keyWidth == cryptoKey128Bits) { memcpy(temp, val, 16); } else { memcpy(temp, val, 32); } CRYPTO_KeyBufWrite(crypto, temp, keyWidth); } else { CRYPTO_KeyBufWrite(crypto, (uint32_t*)val, keyWidth); } } /***************************************************************************//** * @brief * Cipher-block chaining (CBC) cipher mode encryption/decryption, 128/256 bit key. * * @details * See CRYPTO_AES_CBC128() for CBC figure. * * See general comments on layout and byte ordering of parameters. * * @param[in] crypto * A pointer to the CRYPTO peripheral register block. * * @param[out] out * A buffer to place encrypted/decrypted data. Must be at least @p len long. It * may be set equal to @p in, in which case the input buffer is overwritten. * * @param[in] in * A buffer holding data to encrypt/decrypt. Must be at least @p len long. * * @param[in] len * A number of bytes to encrypt/decrypt. Must be a multiple of 16. * * @param[in] key * When encrypting, this is the 256 bit encryption key. When * decrypting, this is the 256 bit decryption key. The decryption key may * be generated from the encryption key with CRYPTO_AES_DecryptKey256(). * * @param[in] iv * 128 bit initialization vector to use. * * @param[in] encrypt * Set to true to encrypt, false to decrypt. * * @param[in] keyWidth * Set to cryptoKey128Bits or cryptoKey256Bits. ******************************************************************************/ static void CRYPTO_AES_CBCx(CRYPTO_TypeDef * crypto, uint8_t * out, const uint8_t * in, unsigned int len, const uint8_t * key, const uint8_t * iv, bool encrypt, CRYPTO_KeyWidth_TypeDef keyWidth) { EFM_ASSERT((len % CRYPTO_AES_BLOCKSIZE) == 0U); /* Initialize control registers. */ crypto->WAC = 0; CRYPTO_KeyBufWriteUnaligned(crypto, key, keyWidth); if (encrypt) { CRYPTO_DataWriteUnaligned(&crypto->DATA0, iv); crypto->SEQ0 = CRYPTO_CMD_INSTR_DATA1TODATA0XOR << _CRYPTO_SEQ0_INSTR0_SHIFT | CRYPTO_CMD_INSTR_AESENC << _CRYPTO_SEQ0_INSTR1_SHIFT; CRYPTO_AES_ProcessLoop(crypto, len, &crypto->DATA1, in, &crypto->DATA0, out); } else { CRYPTO_DataWriteUnaligned(&crypto->DATA2, iv); crypto->SEQ0 = CRYPTO_CMD_INSTR_DATA1TODATA0 << _CRYPTO_SEQ0_INSTR0_SHIFT | CRYPTO_CMD_INSTR_AESDEC << _CRYPTO_SEQ0_INSTR1_SHIFT | CRYPTO_CMD_INSTR_DATA2TODATA0XOR << _CRYPTO_SEQ0_INSTR2_SHIFT | CRYPTO_CMD_INSTR_DATA1TODATA2 << _CRYPTO_SEQ0_INSTR3_SHIFT; crypto->SEQ1 = 0; /* The following call is equivalent to the last call in the 'if( encrypt )' branch. However moving this call outside the conditional scope results in slightly poorer performance for some compiler optimizations. */ CRYPTO_AES_ProcessLoop(crypto, len, &crypto->DATA1, in, &crypto->DATA0, out); } } /***************************************************************************//** * @brief * Cipher feedback (CFB) cipher mode encryption/decryption, 128/256 bit key. * * @details * See CRYPTO_AES_CFB128() for CFB figure. * * See general comments on layout and byte ordering of parameters. * * @param[in] crypto * A pointer to the CRYPTO peripheral register block. * * @param[out] out * A buffer to place encrypted/decrypted data. Must be at least @p len long. It * may be set equal to @p in, in which case the input buffer is overwritten. * * @param[in] in * A buffer holding data to encrypt/decrypt. Must be at least @p len long. * * @param[in] len * A number of bytes to encrypt/decrypt. Must be a multiple of 16. * * @param[in] key * 256 bit encryption key is used for both encryption and decryption modes. * * @param[in] iv * 128 bit initialization vector to use. * * @param[in] encrypt * Set to true to encrypt, false to decrypt. * * @param[in] keyWidth * Set to cryptoKey128Bits or cryptoKey256Bits. ******************************************************************************/ static void CRYPTO_AES_CFBx(CRYPTO_TypeDef * crypto, uint8_t * out, const uint8_t * in, unsigned int len, const uint8_t * key, const uint8_t * iv, bool encrypt, CRYPTO_KeyWidth_TypeDef keyWidth) { EFM_ASSERT((len % CRYPTO_AES_BLOCKSIZE) == 0U); /* Initialize control registers. */ crypto->WAC = 0; /* Load the key. */ CRYPTO_KeyBufWriteUnaligned(crypto, key, keyWidth); /* Load instructions to the CRYPTO sequencer. */ if (encrypt) { /* Load IV */ CRYPTO_DataWriteUnaligned(&crypto->DATA0, iv); crypto->SEQ0 = CRYPTO_CMD_INSTR_AESENC << _CRYPTO_SEQ0_INSTR0_SHIFT | CRYPTO_CMD_INSTR_DATA1TODATA0XOR << _CRYPTO_SEQ0_INSTR1_SHIFT; CRYPTO_AES_ProcessLoop(crypto, len, &crypto->DATA1, in, &crypto->DATA0, out ); } else { /* Load IV */ CRYPTO_DataWriteUnaligned(&crypto->DATA2, iv); crypto->SEQ0 = CRYPTO_CMD_INSTR_DATA2TODATA0 << _CRYPTO_SEQ0_INSTR0_SHIFT | CRYPTO_CMD_INSTR_AESENC << _CRYPTO_SEQ0_INSTR1_SHIFT | CRYPTO_CMD_INSTR_DATA1TODATA0XOR << _CRYPTO_SEQ0_INSTR2_SHIFT | CRYPTO_CMD_INSTR_DATA1TODATA2 << _CRYPTO_SEQ0_INSTR3_SHIFT; crypto->SEQ1 = 0; CRYPTO_AES_ProcessLoop(crypto, len, &crypto->DATA1, in, &crypto->DATA0, out ); } } /***************************************************************************//** * @brief * Counter (CTR) cipher mode encryption/decryption, 128/256 bit key. * * @details * See CRYPTO_AES_CTR128() for CTR figure. * * See general comments on layout and byte ordering of parameters. * * @param[in] crypto * A pointer to the CRYPTO peripheral register block. * * @param[out] out * A buffer to place encrypted/decrypted data. Must be at least @p len long. It * may be set equal to @p in, in which case the input buffer is overwritten. * * @param[in] in * A buffer holding data to encrypt/decrypt. Must be at least @p len long. * * @param[in] len * A number of bytes to encrypt/decrypt. Must be a multiple of 16. * * @param[in] key * 256 bit encryption key. * * @param[in,out] ctr * 128 bit initial counter value. The counter is updated after each AES * block encoding through use of @p ctrFunc. * * @param[in] ctrFunc * A function used to update counter value. Not supported by CRYPTO. * This parameter is included for backwards compatibility with * the EFM32 em_aes.h API. * * @param[in] keyWidth * Set to cryptoKey128Bits or cryptoKey256Bits. ******************************************************************************/ static void CRYPTO_AES_CTRx(CRYPTO_TypeDef * crypto, uint8_t * out, const uint8_t * in, unsigned int len, const uint8_t * key, uint8_t * ctr, CRYPTO_AES_CtrFuncPtr_TypeDef ctrFunc, CRYPTO_KeyWidth_TypeDef keyWidth) { (void) ctrFunc; EFM_ASSERT((len % CRYPTO_AES_BLOCKSIZE) == 0U); /* Initialize control registers. */ crypto->CTRL |= CRYPTO_CTRL_INCWIDTH_INCWIDTH4; crypto->WAC = 0; CRYPTO_KeyBufWriteUnaligned(crypto, key, keyWidth); CRYPTO_DataWriteUnaligned(&crypto->DATA1, ctr); crypto->SEQ0 = CRYPTO_CMD_INSTR_DATA1TODATA0 << _CRYPTO_SEQ0_INSTR0_SHIFT | CRYPTO_CMD_INSTR_AESENC << _CRYPTO_SEQ0_INSTR1_SHIFT | CRYPTO_CMD_INSTR_DATA0TODATA3 << _CRYPTO_SEQ0_INSTR2_SHIFT | CRYPTO_CMD_INSTR_DATA1INC << _CRYPTO_SEQ0_INSTR3_SHIFT; crypto->SEQ1 = CRYPTO_CMD_INSTR_DATA2TODATA0XOR << _CRYPTO_SEQ1_INSTR4_SHIFT; CRYPTO_AES_ProcessLoop(crypto, len, &crypto->DATA2, in, &crypto->DATA0, out); CRYPTO_DataReadUnaligned(&crypto->DATA1, ctr); } /***************************************************************************//** * @brief * Electronic Codebook (ECB) cipher mode encryption/decryption, 128/256 bit key. * * @details * See CRYPTO_AES_ECB128() for ECB figure. * * See general comments on layout and byte ordering of parameters. * * @param[in] crypto * A pointer to the CRYPTO peripheral register block. * * @param[out] out * A buffer to place encrypted/decrypted data. Must be at least @p len long. It * may be set equal to @p in, in which case the input buffer is overwritten. * * @param[in] in * A buffer holding data to encrypt/decrypt. Must be at least @p len long. * * @param[in] len * A number of bytes to encrypt/decrypt. Must be a multiple of 16. * * @param[in] key * When encrypting, this is the 256 bit encryption key. When * decrypting, this is the 256 bit decryption key. The decryption key may * be generated from the encryption key with CRYPTO_AES_DecryptKey256(). * * @param[in] encrypt * Set to true to encrypt, false to decrypt. * * @param[in] keyWidth * Set to cryptoKey128Bits or cryptoKey256Bits. ******************************************************************************/ static void CRYPTO_AES_ECBx(CRYPTO_TypeDef * crypto, uint8_t * out, const uint8_t * in, unsigned int len, const uint8_t * key, bool encrypt, CRYPTO_KeyWidth_TypeDef keyWidth) { EFM_ASSERT((len % CRYPTO_AES_BLOCKSIZE) == 0U); crypto->WAC = 0; CRYPTO_KeyBufWriteUnaligned(crypto, key, keyWidth); if (encrypt) { crypto->SEQ0 = CRYPTO_CMD_INSTR_AESENC << _CRYPTO_SEQ0_INSTR0_SHIFT | CRYPTO_CMD_INSTR_DATA0TODATA1 << _CRYPTO_SEQ0_INSTR1_SHIFT; } else { crypto->SEQ0 = CRYPTO_CMD_INSTR_AESDEC << _CRYPTO_SEQ0_INSTR0_SHIFT | CRYPTO_CMD_INSTR_DATA0TODATA1 << _CRYPTO_SEQ0_INSTR1_SHIFT; } CRYPTO_AES_ProcessLoop(crypto, len, &crypto->DATA0, in, &crypto->DATA1, out); } /***************************************************************************//** * @brief * Output feedback (OFB) cipher mode encryption/decryption, 128/256 bit key. * * @details * See CRYPTO_AES_OFB128() for OFB figure. * * See general comments on layout and byte ordering of parameters. * * @param[in] crypto * A pointer to CRYPTO peripheral register block. * * @param[out] out * A buffer to place encrypted/decrypted data. Must be at least @p len long. It * may be set equal to @p in, in which case the input buffer is overwritten. * * @param[in] in * A buffer holding data to encrypt/decrypt. Must be at least @p len long. * * @param[in] len * A number of bytes to encrypt/decrypt. Must be a multiple of 16. * * @param[in] key * 256 bit encryption key. * * @param[in] iv * 128 bit initialization vector to use. * * @param[in] keyWidth * Set to cryptoKey128Bits or cryptoKey256Bits. ******************************************************************************/ static void CRYPTO_AES_OFBx(CRYPTO_TypeDef * crypto, uint8_t * out, const uint8_t * in, unsigned int len, const uint8_t * key, const uint8_t * iv, CRYPTO_KeyWidth_TypeDef keyWidth) { EFM_ASSERT((len % CRYPTO_AES_BLOCKSIZE) == 0U); crypto->WAC = 0; CRYPTO_KeyBufWriteUnaligned(crypto, key, keyWidth); CRYPTO_DataWriteUnaligned(&crypto->DATA2, iv); crypto->SEQ0 = CRYPTO_CMD_INSTR_DATA0TODATA1 << _CRYPTO_SEQ0_INSTR0_SHIFT | CRYPTO_CMD_INSTR_DATA2TODATA0 << _CRYPTO_SEQ0_INSTR1_SHIFT | CRYPTO_CMD_INSTR_AESENC << _CRYPTO_SEQ0_INSTR2_SHIFT | CRYPTO_CMD_INSTR_DATA0TODATA2 << _CRYPTO_SEQ0_INSTR3_SHIFT; crypto->SEQ1 = CRYPTO_CMD_INSTR_DATA1TODATA0XOR << _CRYPTO_SEQ1_INSTR4_SHIFT | CRYPTO_CMD_INSTR_DATA0TODATA1 << _CRYPTO_SEQ1_INSTR5_SHIFT; CRYPTO_AES_ProcessLoop(crypto, len, &crypto->DATA0, in, &crypto->DATA1, out); } /***************************************************************************//** * @brief * Perform generic AES loop. * * @details * Function loads given register with provided input data. Triggers CRYPTO to * perform sequence of instructions and read specified output register to * output buffer. * * @param[in] crypto * A pointer to the CRYPTO peripheral register block. * * @param[in] len * A number of bytes to encrypt/decrypt. Must be a multiple of 16. * * @param[in] inReg * An input register - one of DATA0,DATA1,DATA2,DATA3 * * @param[in] in * A buffer holding data to encrypt/decrypt. Must be at least @p len long. * * @param[in] outReg * An output register - one of DATA0,DATA1,DATA2,DATA3 * * @param[out] out * A buffer to place encrypted/decrypted data. Must be at least @p len long. It * may be set equal to @p in, in which case the input buffer is overwritten. ******************************************************************************/ __STATIC_INLINE void CRYPTO_AES_ProcessLoop(CRYPTO_TypeDef * crypto, uint32_t len, CRYPTO_DataReg_TypeDef inReg, const uint8_t * in, CRYPTO_DataReg_TypeDef outReg, uint8_t * out) { len /= CRYPTO_AES_BLOCKSIZE; crypto->SEQCTRL = 16UL << _CRYPTO_SEQCTRL_LENGTHA_SHIFT; while (len > 0UL) { len--; /* Load data and trigger encryption. */ CRYPTO_DataWriteUnaligned(inReg, in); crypto->CMD = CRYPTO_CMD_SEQSTART; /* Save encrypted/decrypted data. */ CRYPTO_DataReadUnaligned(outReg, out); out += 16; in += 16; } } /** @} (end addtogroup CRYPTO) */ /** @} (end addtogroup emlib) */ #endif /* defined(CRYPTO_COUNT) && (CRYPTO_COUNT > 0) */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/emlib/src/em_emu.c.
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/***************************************************************************//** * @file * @brief Energy Management Unit (EMU) Peripheral API * @version 5.7.0 ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * SPDX-License-Identifier: Zlib * * The licensor of this software is Silicon Laboratories Inc. * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be * appreciated but is not required. * 2. Altered source versions must be plainly marked as such, and must not be * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * ******************************************************************************/ #include <limits.h> #include "em_emu.h" #if defined(EMU_PRESENT) && (EMU_COUNT > 0) #include "em_assert.h" #include "em_cmu.h" #include "em_common.h" #include "em_system.h" /***************************************************************************//** * @addtogroup emlib * @{ ******************************************************************************/ /***************************************************************************//** * @addtogroup EMU * @brief Energy Management Unit (EMU) Peripheral API * @details * This module contains functions to control the EMU peripheral of Silicon * Labs 32-bit MCUs and SoCs. The EMU handles the different low energy modes * in Silicon Labs microcontrollers. * @{ ******************************************************************************/ /* Consistency check, since restoring assumes similar bit positions in */ /* CMU OSCENCMD and STATUS regs. */ #if (CMU_STATUS_AUXHFRCOENS != CMU_OSCENCMD_AUXHFRCOEN) #error Conflict in AUXHFRCOENS and AUXHFRCOEN bitpositions #endif #if (CMU_STATUS_HFXOENS != CMU_OSCENCMD_HFXOEN) #error Conflict in HFXOENS and HFXOEN bitpositions #endif #if (CMU_STATUS_LFRCOENS != CMU_OSCENCMD_LFRCOEN) #error Conflict in LFRCOENS and LFRCOEN bitpositions #endif #if (CMU_STATUS_LFXOENS != CMU_OSCENCMD_LFXOEN) #error Conflict in LFXOENS and LFXOEN bitpositions #endif /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ #if defined(_SILICON_LABS_32B_SERIES_0) /* Fix for errata EMU_E107 - non-WIC interrupt masks. * Zero Gecko and future families are not affected by errata EMU_E107. */ #if defined(_EFM32_GECKO_FAMILY) #define ERRATA_FIX_EMU_E107_ENABLE #define NON_WIC_INT_MASK_0 (~(0x0dfc0323U)) #define NON_WIC_INT_MASK_1 (~(0x0U)) #elif defined(_EFM32_TINY_FAMILY) #define ERRATA_FIX_EMU_E107_ENABLE #define NON_WIC_INT_MASK_0 (~(0x001be323U)) #define NON_WIC_INT_MASK_1 (~(0x0U)) #elif defined(_EFM32_GIANT_FAMILY) #define ERRATA_FIX_EMU_E107_ENABLE #define NON_WIC_INT_MASK_0 (~(0xff020e63U)) #define NON_WIC_INT_MASK_1 (~(0x00000046U)) #elif defined(_EFM32_WONDER_FAMILY) #define ERRATA_FIX_EMU_E107_ENABLE #define NON_WIC_INT_MASK_0 (~(0xff020e63U)) #define NON_WIC_INT_MASK_1 (~(0x00000046U)) #endif #endif #if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_74) \ || (defined(_SILICON_LABS_32B_SERIES_0) \ && (defined(_EFM32_HAPPY_FAMILY) || defined(_EFM32_ZERO_FAMILY))) // Fix for errata EMU_E110 - Potential Hard Fault when Exiting EM2. #include "em_core.h" #include "em_ramfunc.h" #define ERRATA_FIX_EMU_E110_ENABLE #endif /* Fix for errata EMU_E108 - High Current Consumption on EM4 Entry. */ #if defined(_SILICON_LABS_32B_SERIES_0) && defined(_EFM32_HAPPY_FAMILY) #define ERRATA_FIX_EMU_E108_ENABLE #endif /* Fix for errata EMU_E208 - Occasional Full Reset After Exiting EM4H. */ #if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) #define ERRATA_FIX_EMU_E208_ENABLE #endif /* Enable FETCNT tuning errata fix. */ #if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) #define ERRATA_FIX_DCDC_FETCNT_SET_ENABLE #endif /* Enable LN handshake errata fix. */ #if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) #define ERRATA_FIX_DCDC_LNHS_BLOCK_ENABLE typedef enum { errataFixDcdcHsInit, errataFixDcdcHsTrimSet, errataFixDcdcHsBypassLn, errataFixDcdcHsLnWaitDone } errataFixDcdcHs_TypeDef; static errataFixDcdcHs_TypeDef errataFixDcdcHsState = errataFixDcdcHsInit; #endif /* Fix for errata for EFM32GG11 and EFM32TG11. If a device is entering EM4S * while powering the analog peripherals from DVDD, firmware must switch * over to powering the analog peripherals from AVDD and delay the EM4S entry * with 30 us. */ #if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_100) \ || defined(_SILICON_LABS_GECKO_INTERNAL_SDID_103) #define ERRATA_FIX_EM4S_DELAY_ENTRY #endif /* Used to figure out if a memory address is inside or outside of a RAM block. * A memory address is inside a RAM block if the address is greater than the * RAM block address. */ #define ADDRESS_NOT_IN_BLOCK(addr, block) ((addr) <= (block) ? 1UL : 0UL) /* RAM Block layout for various device families. Note that some devices * have special layout in RAM0 and some devices have a special RAM block * at the end of their block layout. */ #if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_84) #define RAM1_BLOCKS 2U #define RAM1_BLOCK_SIZE 0x10000U // 64 kB blocks #define RAM2_BLOCKS 1U #define RAM2_BLOCK_SIZE 0x800U // 2 kB block #elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_89) #define RAM0_BLOCKS 2U #define RAM0_BLOCK_SIZE 0x4000U #define RAM1_BLOCKS 2U #define RAM1_BLOCK_SIZE 0x4000U // 16 kB blocks #define RAM2_BLOCKS 1U #define RAM2_BLOCK_SIZE 0x800U // 2 kB block #elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_95) #define RAM0_BLOCKS 1U #define RAM0_BLOCK_SIZE 0x4000U // 16 kB block #define RAM1_BLOCKS 1U #define RAM1_BLOCK_SIZE 0x4000U // 16 kB block #define RAM2_BLOCKS 1U #define RAM2_BLOCK_SIZE 0x800U // 2 kB block #elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_103) #define RAM0_BLOCKS 4U #define RAM0_BLOCK_SIZE 0x2000U // 8 kB blocks #elif defined(_SILICON_LABS_32B_SERIES_0) && defined(_EFM32_GIANT_FAMILY) #define RAM0_BLOCKS 4U #define RAM0_BLOCK_SIZE 0x8000U // 32 kB blocks #elif defined(_SILICON_LABS_32B_SERIES_0) && defined(_EFM32_GECKO_FAMILY) #define RAM0_BLOCKS 4U #define RAM0_BLOCK_SIZE 0x1000U // 4 kB blocks #elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_100) #define RAM0_BLOCKS 8U #define RAM0_BLOCK_SIZE 0x4000U // 16 kB blocks #define RAM1_BLOCKS 8U #define RAM1_BLOCK_SIZE 0x4000U // 16 kB blocks #define RAM2_BLOCKS 4U #define RAM2_BLOCK_SIZE 0x10000U // 64 kB blocks #elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_106) #define RAM0_BLOCKS 4U #define RAM0_BLOCK_SIZE 0x4000U // 16 kB blocks #define RAM1_BLOCKS 4U #define RAM1_BLOCK_SIZE 0x4000U // 16 kB blocks #define RAM2_BLOCKS 4U #define RAM2_BLOCK_SIZE 0x4000U // 16 kB blocks #elif defined(_SILICON_LABS_32B_SERIES_2) #define RAM0_BLOCKS 6U #define RAM0_BLOCK_SIZE 0x4000U // 16 kB blocks #endif #if defined(_SILICON_LABS_32B_SERIES_0) /* RAM_MEM_END on Gecko devices have a value larger than the SRAM_SIZE. */ #define RAM0_END (SRAM_BASE + SRAM_SIZE - 1) #else #define RAM0_END RAM_MEM_END #endif #if defined(CMU_STATUS_HFXOSHUNTOPTRDY) #define HFXO_STATUS_READY_FLAGS (CMU_STATUS_HFXOPEAKDETRDY | CMU_STATUS_HFXOSHUNTOPTRDY) #elif defined(CMU_STATUS_HFXOPEAKDETRDY) #define HFXO_STATUS_READY_FLAGS (CMU_STATUS_HFXOPEAKDETRDY) #endif /** @endcond */ #if defined(_EMU_DCDCCTRL_MASK) /* DCDCTODVDD output range minimum/maximum. */ #if !defined(PWRCFG_DCDCTODVDD_VMIN) #define PWRCFG_DCDCTODVDD_VMIN 1800U #endif #if !defined(PWRCFG_DCDCTODVDD_VMAX) #define PWRCFG_DCDCTODVDD_VMAX 3000U #endif #endif /******************************************************************************* *************************** LOCAL VARIABLES ******************************** ******************************************************************************/ /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ /* Static user configuration. */ #if defined(_EMU_DCDCCTRL_MASK) static uint16_t dcdcMaxCurrent_mA; static uint16_t dcdcEm01LoadCurrent_mA; static EMU_DcdcLnReverseCurrentControl_TypeDef dcdcReverseCurrentControl; #endif #if defined(EMU_VSCALE_PRESENT) static EMU_EM01Init_TypeDef vScaleEM01Config = { false }; #endif /** @endcond */ /******************************************************************************* ************************** LOCAL FUNCTIONS ******************************** ******************************************************************************/ /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ #if defined(EMU_VSCALE_PRESENT) /* Convert from level to EM0 and 1 command bit */ __STATIC_INLINE uint32_t vScaleEM01Cmd(EMU_VScaleEM01_TypeDef level) { return EMU_CMD_EM01VSCALE0 << (_EMU_STATUS_VSCALE_VSCALE0 - (uint32_t)level); } #endif #if defined(ERRATA_FIX_EMU_E110_ENABLE) SL_RAMFUNC_DECLARATOR static void __attribute__ ((noinline)) ramWFI(void); SL_RAMFUNC_DEFINITION_BEGIN static void __attribute__ ((noinline)) ramWFI(void) { __WFI(); // Enter EM2 or EM3 *(volatile uint32_t*)4; // Clear faulty read data after wakeup } SL_RAMFUNC_DEFINITION_END #endif /***************************************************************************//** * @brief * Save/restore/update oscillator, core clock and voltage scaling configuration on * EM2 or EM3 entry/exit. * * @details * Hardware may automatically change the oscillator and the voltage scaling configuration * when going into or out of an energy mode. Static data in this function keeps track of * such configuration bits and is used to restore state if needed. * ******************************************************************************/ typedef enum { emState_Save, /* Save EMU and CMU state. */ emState_Restore, /* Restore and unlock. */ } emState_TypeDef; static void emState(emState_TypeDef action) { #if defined(_SILICON_LABS_32B_SERIES_2) /* Series-2 devices automatically save and restore clock state */ (void) action; #else uint32_t oscEnCmd; uint32_t cmuLocked; static uint32_t cmuStatus; static CMU_Select_TypeDef hfClock; #if defined(EMU_VSCALE_PRESENT) static uint8_t vScaleStatus; static uint32_t hfrcoCtrl; #endif /* Save or update state. */ if (action == emState_Save) { /* Save configuration. */ cmuStatus = CMU->STATUS; hfClock = CMU_ClockSelectGet(cmuClock_HF); #if defined(EMU_VSCALE_PRESENT) /* Save vscale. */ EMU_VScaleWait(); vScaleStatus = (uint8_t)((EMU->STATUS & _EMU_STATUS_VSCALE_MASK) >> _EMU_STATUS_VSCALE_SHIFT); hfrcoCtrl = CMU->HFRCOCTRL; #endif } else { /* Restore state. */ /* Apply saved configuration. */ #if defined(EMU_VSCALE_PRESENT) /* Restore EM0 and 1 voltage scaling level. @ref EMU_VScaleWait() is called later, just before HF clock select is set. */ EMU->CMD = vScaleEM01Cmd((EMU_VScaleEM01_TypeDef)vScaleStatus); #endif /* CMU registers may be locked. */ cmuLocked = CMU->LOCK & CMU_LOCK_LOCKKEY_LOCKED; CMU_Unlock(); #if defined(_CMU_OSCENCMD_MASK) /* AUXHFRCO are automatically disabled (except if using debugger). */ /* HFRCO, USHFRCO and HFXO are automatically disabled. */ /* LFRCO/LFXO may be disabled by SW in EM3. */ /* Restore according to status prior to entering energy mode. */ oscEnCmd = 0; oscEnCmd |= (cmuStatus & CMU_STATUS_HFRCOENS) != 0U ? CMU_OSCENCMD_HFRCOEN : 0U; oscEnCmd |= (cmuStatus & CMU_STATUS_AUXHFRCOENS) != 0U ? CMU_OSCENCMD_AUXHFRCOEN : 0U; oscEnCmd |= (cmuStatus & CMU_STATUS_LFRCOENS) != 0U ? CMU_OSCENCMD_LFRCOEN : 0U; oscEnCmd |= (cmuStatus & CMU_STATUS_HFXOENS) != 0U ? CMU_OSCENCMD_HFXOEN : 0U; oscEnCmd |= (cmuStatus & CMU_STATUS_LFXOENS) != 0U ? CMU_OSCENCMD_LFXOEN : 0U; #if defined(_CMU_STATUS_USHFRCOENS_MASK) oscEnCmd |= (cmuStatus & CMU_STATUS_USHFRCOENS) != 0U ? CMU_OSCENCMD_USHFRCOEN : 0U; #endif CMU->OSCENCMD = oscEnCmd; #endif #if defined(_EMU_STATUS_VSCALE_MASK) /* Wait for upscale to complete and then restore selected clock. */ EMU_VScaleWait(); if ((EMU->CTRL & _EMU_CTRL_EM23VSCALEAUTOWSEN_MASK) != 0U) { /* Restore HFRCO frequency which was automatically adjusted by hardware. */ while ((CMU->SYNCBUSY & CMU_SYNCBUSY_HFRCOBSY) != 0U) { } CMU->HFRCOCTRL = hfrcoCtrl; if (hfClock == cmuSelect_HFRCO) { /* Optimize wait state after EM2/EM3 wakeup because hardware has * modified them. */ CMU_UpdateWaitStates(SystemHfrcoFreq, EMU_VScaleGet()); } } #endif if (hfClock != cmuSelect_HFRCO) { CMU_ClockSelectSet(cmuClock_HF, hfClock); } #if defined(_CMU_OSCENCMD_MASK) /* If HFRCO was disabled before entering Energy Mode, turn it off again */ /* as it is automatically enabled by wake up */ if ((cmuStatus & CMU_STATUS_HFRCOENS) == 0U) { CMU->OSCENCMD = CMU_OSCENCMD_HFRCODIS; } #endif /* Restore CMU register locking */ if (cmuLocked != 0U) { CMU_Lock(); } } #endif } #if defined(ERRATA_FIX_EMU_E107_ENABLE) /* Get enable conditions for errata EMU_E107 fix. */ __STATIC_INLINE bool getErrataFixEmuE107En(void) { /* SYSTEM_ChipRevisionGet could have been used here, but we would like a * faster implementation in this case. */ uint16_t majorMinorRev; /* CHIP MAJOR bit [3:0]. */ majorMinorRev = ((ROMTABLE->PID0 & _ROMTABLE_PID0_REVMAJOR_MASK) >> _ROMTABLE_PID0_REVMAJOR_SHIFT) << 8; /* CHIP MINOR bit [7:4]. */ majorMinorRev |= ((ROMTABLE->PID2 & _ROMTABLE_PID2_REVMINORMSB_MASK) >> _ROMTABLE_PID2_REVMINORMSB_SHIFT) << 4; /* CHIP MINOR bit [3:0]. */ majorMinorRev |= (ROMTABLE->PID3 & _ROMTABLE_PID3_REVMINORLSB_MASK) >> _ROMTABLE_PID3_REVMINORLSB_SHIFT; #if defined(_EFM32_GECKO_FAMILY) return (majorMinorRev <= 0x0103); #elif defined(_EFM32_TINY_FAMILY) return (majorMinorRev <= 0x0102); #elif defined(_EFM32_GIANT_FAMILY) return (majorMinorRev <= 0x0103) || (majorMinorRev == 0x0204); #elif defined(_EFM32_WONDER_FAMILY) return (majorMinorRev == 0x0100); #else /* Zero Gecko and future families are not affected by errata EMU_E107. */ return false; #endif } #endif /* LP prepare / LN restore P/NFET count. */ #define DCDC_LP_PFET_CNT 7 #define DCDC_LP_NFET_CNT 7 #if defined(ERRATA_FIX_DCDC_FETCNT_SET_ENABLE) static void currentLimitersUpdate(void); static void dcdcFetCntSet(bool lpModeSet) { uint32_t tmp; static uint32_t emuDcdcMiscCtrlReg; if (lpModeSet) { emuDcdcMiscCtrlReg = EMU->DCDCMISCCTRL; tmp = EMU->DCDCMISCCTRL & ~(_EMU_DCDCMISCCTRL_PFETCNT_MASK | _EMU_DCDCMISCCTRL_NFETCNT_MASK); tmp |= (DCDC_LP_PFET_CNT << _EMU_DCDCMISCCTRL_PFETCNT_SHIFT) | (DCDC_LP_NFET_CNT << _EMU_DCDCMISCCTRL_NFETCNT_SHIFT); EMU->DCDCMISCCTRL = tmp; currentLimitersUpdate(); } else { EMU->DCDCMISCCTRL = emuDcdcMiscCtrlReg; currentLimitersUpdate(); } } #endif #if defined(ERRATA_FIX_DCDC_LNHS_BLOCK_ENABLE) static void dcdcHsFixLnBlock(void) { #define EMU_DCDCSTATUS (*(volatile uint32_t *)(EMU_BASE + 0x7C)) if ((errataFixDcdcHsState == errataFixDcdcHsTrimSet) || (errataFixDcdcHsState == errataFixDcdcHsBypassLn)) { /* Wait for LNRUNNING */ if ((EMU->DCDCCTRL & _EMU_DCDCCTRL_DCDCMODE_MASK) == EMU_DCDCCTRL_DCDCMODE_LOWNOISE) { while (!(EMU_DCDCSTATUS & (0x1 << 16))) { } } errataFixDcdcHsState = errataFixDcdcHsLnWaitDone; } } #endif #if defined(_EMU_CTRL_EM23VSCALE_MASK) /* Configure EMU and CMU for EM2 and 3 voltage downscale. */ static void vScaleDownEM23Setup(void) { /* Wait until previous scaling is done. */ EMU_VScaleWait(); uint32_t em23vs = (EMU->CTRL & _EMU_CTRL_EM23VSCALE_MASK) >> _EMU_CTRL_EM23VSCALE_SHIFT; uint32_t em01vs = (EMU->STATUS & _EMU_STATUS_VSCALE_MASK) >> _EMU_STATUS_VSCALE_SHIFT; /* Inverse coding. */ if (em23vs > em01vs) { EMU->CTRL |= EMU_CTRL_EM23VSCALEAUTOWSEN; #if defined(_MSC_RAMCTRL_RAMWSEN_MASK) /* Set RAM wait states for safe EM2 wakeup. */ BUS_RegMaskedSet(&MSC->RAMCTRL, (MSC_RAMCTRL_RAMWSEN | MSC_RAMCTRL_RAM1WSEN | MSC_RAMCTRL_RAM2WSEN)); #endif } else { EMU->CTRL &= ~EMU_CTRL_EM23VSCALEAUTOWSEN; } } /* Handle automatic HFRCO adjustment that may have occurred during EM2/EM3. */ static void vScaleAfterWakeup(void) { if ((EMU->CTRL & EMU_CTRL_EM23VSCALEAUTOWSEN) != 0U) { /* The hardware may have updated the HFRCOCTRL register during EM2/EM3 * entry if voltage scaling in EM2/EM3 is enabled. The hardware would * then update the HFRCO frequency to 19 MHz automatically. */ uint32_t freqRange = (CMU->HFRCOCTRL & _CMU_HFRCOCTRL_FREQRANGE_MASK) >> _CMU_HFRCOCTRL_FREQRANGE_SHIFT; if (freqRange == 0x08U) { SystemHfrcoFreq = 19000000; } } } #endif /** @endcond */ /******************************************************************************* ************************** GLOBAL FUNCTIONS ******************************* ******************************************************************************/ /***************************************************************************//** * @brief * Enter energy mode 2 (EM2). * * @details * When entering EM2, high-frequency clocks are disabled, i.e., HFXO, HFRCO * and AUXHFRCO (for AUXHFRCO, see exception note below). When re-entering * EM0, HFRCO is re-enabled and the core will be clocked by the configured * HFRCO band. This ensures a quick wakeup from EM2. * * However, prior to entering EM2, the core may have been using another * oscillator than HFRCO. The @p restore parameter gives the user the option * to restore all HF oscillators according to state prior to entering EM2, * as well as the clock used to clock the core. This restore procedure is * handled by SW. However, since handled by SW, it will not be restored * before completing the interrupt function(s) waking up the core! * * @note * If restoring core clock to use the HFXO oscillator, which has been * disabled during EM2 mode, this function will stall until the oscillator * has stabilized. Stalling time can be reduced by adding interrupt * support detecting stable oscillator, and an asynchronous switch to the * original oscillator. See CMU documentation. Such a feature is however * outside the scope of the implementation in this function. * @note * If ERRATA_FIX_EMU_E110_ENABLE is active, the core's SLEEPONEXIT feature * can not be used. * @par * If HFXO is re-enabled by this function, and NOT used to clock the core, * this function will not wait for HFXO to stabilize. This must be considered * by the application if trying to use features relying on that oscillator * upon return. * @par * If a debugger is attached, the AUXHFRCO will not be disabled if enabled * upon entering EM2. It will thus remain enabled when returning to EM0 * regardless of the @p restore parameter. * @par * If HFXO autostart and select is enabled by using @ref CMU_HFXOAutostartEnable(), * the starting and selecting of the core clocks will be identical to the user * independently of the value of the @p restore parameter when waking up on * the wakeup sources corresponding to the autostart and select setting. * @par * If voltage scaling is supported, the restore parameter is true and the EM0 * voltage scaling level is set higher than the EM2 level, then the EM0 level is * also restored. * * Note that the hardware will automatically update the HFRCO frequency in the * case where voltage scaling is used in EM2/EM3 and not in EM0/EM1. When the * restore argument to this function is true then software will restore the * original HFRCO frequency after EM2/EM3 wake up. If the restore argument is * false then the HFRCO frequency is 19 MHz when coming out of EM2/EM3 and * all wait states are at a safe value. * * @param[in] restore * @li true - save and restore oscillators, clocks and voltage scaling, see * function details. * @li false - do not save and restore oscillators and clocks, see function * details. * @par * The @p restore option should only be used if all clock control is done * via the CMU API. ******************************************************************************/ void EMU_EnterEM2(bool restore) { #if defined(ERRATA_FIX_EMU_E107_ENABLE) bool errataFixEmuE107En; uint32_t nonWicIntEn[2]; #endif /* Only save EMU and CMU state if restored on wake-up. */ if (restore) { emState(emState_Save); } #if defined(_EMU_CTRL_EM23VSCALE_MASK) vScaleDownEM23Setup(); #endif /* Enter Cortex deep sleep mode. */ SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; /* Fix for errata EMU_E107 - store non-WIC interrupt enable flags. Disable the enabled non-WIC interrupts. */ #if defined(ERRATA_FIX_EMU_E107_ENABLE) errataFixEmuE107En = getErrataFixEmuE107En(); if (errataFixEmuE107En) { nonWicIntEn[0] = NVIC->ISER[0] & NON_WIC_INT_MASK_0; NVIC->ICER[0] = nonWicIntEn[0]; #if (NON_WIC_INT_MASK_1 != (~(0x0U))) nonWicIntEn[1] = NVIC->ISER[1] & NON_WIC_INT_MASK_1; NVIC->ICER[1] = nonWicIntEn[1]; #endif } #endif #if defined(ERRATA_FIX_DCDC_FETCNT_SET_ENABLE) dcdcFetCntSet(true); #endif #if defined(ERRATA_FIX_DCDC_LNHS_BLOCK_ENABLE) dcdcHsFixLnBlock(); #endif #if defined(ERRATA_FIX_EMU_E110_ENABLE) CORE_CRITICAL_SECTION(ramWFI(); ) #else __WFI(); #endif #if defined(ERRATA_FIX_DCDC_FETCNT_SET_ENABLE) dcdcFetCntSet(false); #endif /* Fix for errata EMU_E107 - restore state of non-WIC interrupt enable flags. */ #if defined(ERRATA_FIX_EMU_E107_ENABLE) if (errataFixEmuE107En) { NVIC->ISER[0] = nonWicIntEn[0]; #if (NON_WIC_INT_MASK_1 != (~(0x0U))) NVIC->ISER[1] = nonWicIntEn[1]; #endif } #endif /* Restore oscillators/clocks and voltage scaling if supported. */ if (restore) { emState(emState_Restore); } else { #if defined(_EMU_CTRL_EM23VSCALE_MASK) vScaleAfterWakeup(); #endif /* If not restoring, and original clock was not HFRCO, we have to */ /* update CMSIS core clock variable since HF clock has changed */ /* to HFRCO. */ SystemCoreClockUpdate(); } } /***************************************************************************//** * @brief * Enter energy mode 3 (EM3). * * @details * When entering EM3, the high-frequency clocks are disabled by hardware, i.e., HFXO, * HFRCO, and AUXHFRCO (for AUXHFRCO, see exception note below). In addition, * the low-frequency clocks, i.e., LFXO and LFRCO are disabled by software. When * re-entering EM0, HFRCO is re-enabled and the core will be clocked by the * configured HFRCO band. This ensures a quick wakeup from EM3. * * However, prior to entering EM3, the core may have been using an * oscillator other than HFRCO. The @p restore parameter gives the user the option * to restore all HF/LF oscillators according to state prior to entering EM3, * as well as the clock used to clock the core. This restore procedure is * handled by software. However, since it is handled by software, it will not be restored * before completing the interrupt function(s) waking up the core! * * @note * If restoring core clock to use an oscillator other than HFRCO, this * function will stall until the oscillator has stabilized. Stalling time * can be reduced by adding interrupt support detecting stable oscillator, * and an asynchronous switch to the original oscillator. See CMU * documentation. This feature is, however, outside the scope of the * implementation in this function. * @note * If ERRATA_FIX_EMU_E110_ENABLE is active, the core's SLEEPONEXIT feature * can't be used. * @par * If HFXO/LFXO/LFRCO are re-enabled by this function, and NOT used to clock * the core, this function will not wait for those oscillators to stabilize. * This must be considered by the application if trying to use features * relying on those oscillators upon return. * @par * If a debugger is attached, the AUXHFRCO will not be disabled if enabled * upon entering EM3. It will, therefore, remain enabled when returning to EM0 * regardless of the @p restore parameter. * @par * If voltage scaling is supported, the restore parameter is true and the EM0 * voltage scaling level is set higher than the EM3 level, then the EM0 level is * also restored. * * @param[in] restore * @li true - save and restore oscillators, clocks and voltage scaling, see * function details. * @li false - do not save and restore oscillators and clocks, see function * details. * @par * The @p restore option should only be used if all clock control is done * via the CMU API. ******************************************************************************/ void EMU_EnterEM3(bool restore) { uint32_t cmuLocked; #if defined(ERRATA_FIX_EMU_E107_ENABLE) bool errataFixEmuE107En; uint32_t nonWicIntEn[2]; #endif /* Only save EMU and CMU state if restored on wake-up. */ if (restore) { emState(emState_Save); } #if defined(EMU_VSCALE_PRESENT) vScaleDownEM23Setup(); #endif /* CMU registers may be locked. */ #if defined(CMU_STATUS_LOCK) cmuLocked = (CMU->STATUS & _CMU_STATUS_LOCK_MASK) == CMU_STATUS_LOCK_LOCKED; #else cmuLocked = CMU->LOCK & CMU_LOCK_LOCKKEY_LOCKED; #endif CMU_Unlock(); #if defined(_CMU_OSENCMD_MASK) /* Disable LF oscillators. */ CMU->OSCENCMD = CMU_OSCENCMD_LFXODIS | CMU_OSCENCMD_LFRCODIS; #endif /* Restore CMU register locking. */ if (cmuLocked != 0U) { CMU_Lock(); } /* Enter Cortex deep sleep mode. */ SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; /* Fix for errata EMU_E107 - store non-WIC interrupt enable flags. Disable the enabled non-WIC interrupts. */ #if defined(ERRATA_FIX_EMU_E107_ENABLE) errataFixEmuE107En = getErrataFixEmuE107En(); if (errataFixEmuE107En) { nonWicIntEn[0] = NVIC->ISER[0] & NON_WIC_INT_MASK_0; NVIC->ICER[0] = nonWicIntEn[0]; #if (NON_WIC_INT_MASK_1 != (~(0x0U))) nonWicIntEn[1] = NVIC->ISER[1] & NON_WIC_INT_MASK_1; NVIC->ICER[1] = nonWicIntEn[1]; #endif } #endif #if defined(ERRATA_FIX_DCDC_FETCNT_SET_ENABLE) dcdcFetCntSet(true); #endif #if defined(ERRATA_FIX_DCDC_LNHS_BLOCK_ENABLE) dcdcHsFixLnBlock(); #endif #if defined(ERRATA_FIX_EMU_E110_ENABLE) CORE_CRITICAL_SECTION(ramWFI(); ) #else __WFI(); #endif #if defined(ERRATA_FIX_DCDC_FETCNT_SET_ENABLE) dcdcFetCntSet(false); #endif /* Fix for errata EMU_E107 - restore state of non-WIC interrupt enable flags. */ #if defined(ERRATA_FIX_EMU_E107_ENABLE) if (errataFixEmuE107En) { NVIC->ISER[0] = nonWicIntEn[0]; #if (NON_WIC_INT_MASK_1 != (~(0x0U))) NVIC->ISER[1] = nonWicIntEn[1]; #endif } #endif /* Restore oscillators/clocks and voltage scaling if supported. */ if (restore) { emState(emState_Restore); } else { #if defined(_EMU_CTRL_EM23VSCALE_MASK) vScaleAfterWakeup(); #endif /* If not restoring, and original clock was not HFRCO. */ /* As a result, he CMSIS core clock variable must be updated. */ /* to HFRCO. */ SystemCoreClockUpdate(); } } /***************************************************************************//** * @brief * Save the CMU HF clock select state, oscillator enable, and voltage scaling * (if available) before @ref EMU_EnterEM2() or @ref EMU_EnterEM3() are called * with the restore parameter set to false. Calling this function is * equivalent to calling @ref EMU_EnterEM2() or @ref EMU_EnterEM3() with the * restore parameter set to true, but it allows the state to be saved without * going to sleep. The state can be restored manually by calling * @ref EMU_Restore(). ******************************************************************************/ void EMU_Save(void) { emState(emState_Save); } /***************************************************************************//** * @brief * Restore CMU HF clock select state, oscillator enable, and voltage scaling * (if available) after @ref EMU_EnterEM2() or @ref EMU_EnterEM3() are called * with the restore parameter set to false. Calling this function is * equivalent to calling @ref EMU_EnterEM2() or @ref EMU_EnterEM3() with the * restore parameter set to true, but it allows the application to evaluate the * wakeup reason before restoring state. ******************************************************************************/ void EMU_Restore(void) { emState(emState_Restore); } /***************************************************************************//** * @brief * Enter energy mode 4 (EM4). * * @note * Only a power on reset or external reset pin can wake the device from EM4. ******************************************************************************/ void EMU_EnterEM4(void) { int i; #if defined(_EMU_EM4CTRL_EM4ENTRY_SHIFT) uint32_t em4seq2 = (EMU->EM4CTRL & ~_EMU_EM4CTRL_EM4ENTRY_MASK) | (2U << _EMU_EM4CTRL_EM4ENTRY_SHIFT); uint32_t em4seq3 = (EMU->EM4CTRL & ~_EMU_EM4CTRL_EM4ENTRY_MASK) | (3U << _EMU_EM4CTRL_EM4ENTRY_SHIFT); #else uint32_t em4seq2 = (EMU->CTRL & ~_EMU_CTRL_EM4CTRL_MASK) | (2U << _EMU_CTRL_EM4CTRL_SHIFT); uint32_t em4seq3 = (EMU->CTRL & ~_EMU_CTRL_EM4CTRL_MASK) | (3U << _EMU_CTRL_EM4CTRL_SHIFT); #endif /* Make sure that the register write lock is disabled. */ EMU_Unlock(); #if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) /* The DCDC is not supported in EM4S. EFM32xG1 and EFR32xG1 devices should * switch to bypass mode before entering EM4S. Other devices handle this * automatically at the hardware level. */ if ((EMU->EM4CTRL & _EMU_EM4CTRL_EM4STATE_MASK) == EMU_EM4CTRL_EM4STATE_EM4S) { uint32_t dcdcMode = EMU->DCDCCTRL & _EMU_DCDCCTRL_DCDCMODE_MASK; if (dcdcMode == EMU_DCDCCTRL_DCDCMODE_LOWNOISE || dcdcMode == EMU_DCDCCTRL_DCDCMODE_LOWPOWER) { EMU_DCDCModeSet(emuDcdcMode_Bypass); } } #endif #if defined(_EMU_EM4CTRL_MASK) && defined(ERRATA_FIX_EMU_E208_ENABLE) if (EMU->EM4CTRL & EMU_EM4CTRL_EM4STATE_EM4H) { /* Fix for errata EMU_E208 - Occasional Full Reset After Exiting EM4H. * Full description of errata fix can be found in the errata document. */ __disable_irq(); *(volatile uint32_t *)(EMU_BASE + 0x190UL) = 0x0000ADE8UL; *(volatile uint32_t *)(EMU_BASE + 0x198UL) |= (0x1UL << 7); *(volatile uint32_t *)(EMU_BASE + 0x88UL) |= (0x1UL << 8); } #endif #if defined(ERRATA_FIX_EMU_E108_ENABLE) /* Fix for errata EMU_E108 - High Current Consumption on EM4 Entry. */ __disable_irq(); *(volatile uint32_t *)0x400C80E4 = 0; #endif #if defined(ERRATA_FIX_DCDC_FETCNT_SET_ENABLE) dcdcFetCntSet(true); #endif #if defined(ERRATA_FIX_DCDC_LNHS_BLOCK_ENABLE) dcdcHsFixLnBlock(); #endif #if defined(ERRATA_FIX_EM4S_DELAY_ENTRY) /* Fix for errata where firmware must clear ANASW and delay EM4S entry by 30 us. */ if ((EMU->EM4CTRL & _EMU_EM4CTRL_EM4STATE_MASK) == EMU_EM4CTRL_EM4STATE_EM4S) { if ((EMU->PWRCTRL & _EMU_PWRCTRL_ANASW_MASK) == EMU_PWRCTRL_ANASW_DVDD) { BUS_RegMaskedClear(&EMU->PWRCTRL, _EMU_PWRCTRL_ANASW_MASK); /* Switch to 1 MHz HFRCO. This delays enough to meet the 30 us requirement * before entering EM4. */ uint32_t freqCal = (DEVINFO->HFRCOCAL0 & ~_CMU_HFRCOCTRL_CLKDIV_MASK) | CMU_HFRCOCTRL_CLKDIV_DIV4; while ((CMU->SYNCBUSY & CMU_SYNCBUSY_HFRCOBSY) != 0UL) { } CMU->HFRCOCTRL = freqCal; CMU->OSCENCMD = CMU_OSCENCMD_HFRCOEN; while ((CMU->STATUS & CMU_STATUS_HFRCORDY) == 0U) { } CMU->HFCLKSEL = CMU_HFCLKSEL_HF_HFRCO; __NOP(); } } #endif for (i = 0; i < 4; i++) { #if defined(_EMU_EM4CTRL_EM4ENTRY_SHIFT) EMU->EM4CTRL = em4seq2; EMU->EM4CTRL = em4seq3; } EMU->EM4CTRL = em4seq2; #else EMU->CTRL = em4seq2; EMU->CTRL = em4seq3; } EMU->CTRL = em4seq2; #endif } #if defined(_EMU_EM4CTRL_MASK) /***************************************************************************//** * @brief * Enter energy mode 4 hibernate (EM4H). * * @note * Retention of clocks and GPIO in EM4 can be configured using * @ref EMU_EM4Init before calling this function. ******************************************************************************/ void EMU_EnterEM4H(void) { #if defined(_EMU_EM4CTRL_EM4STATE_MASK) BUS_RegBitWrite(&EMU->EM4CTRL, _EMU_EM4CTRL_EM4STATE_SHIFT, 1); #endif EMU_EnterEM4(); } /***************************************************************************//** * @brief * Enter energy mode 4 shutoff (EM4S). * * @note * Retention of clocks and GPIO in EM4 can be configured using * @ref EMU_EM4Init before calling this function. ******************************************************************************/ void EMU_EnterEM4S(void) { #if defined(_EMU_EM4CTRL_EM4STATE_MASK) BUS_RegBitWrite(&EMU->EM4CTRL, _EMU_EM4CTRL_EM4STATE_SHIFT, 0); #endif EMU_EnterEM4(); } #endif /***************************************************************************//** * @brief * Power down memory block. * * @param[in] blocks * Specifies a logical OR of bits indicating memory blocks to power down. * Bit 0 selects block 1, bit 1 selects block 2, and so on. Memory block 0 cannot * be disabled. See the reference manual for available * memory blocks for a device. * * @note * Only a POR reset can power up the specified memory block(s) after power down. * * @deprecated * This function is deprecated, use @ref EMU_RamPowerDown() instead which * maps a user provided memory range into RAM blocks to power down. ******************************************************************************/ void EMU_MemPwrDown(uint32_t blocks) { #if defined(_EMU_MEMCTRL_MASK) EMU->MEMCTRL = blocks & _EMU_MEMCTRL_MASK; #elif defined(_EMU_RAM0CTRL_MASK) EMU->RAM0CTRL = blocks & _EMU_RAM0CTRL_MASK; #else (void)blocks; #endif } /***************************************************************************//** * @brief * Power down RAM memory blocks. * * @details * This function will power down all the RAM blocks that are within a given * range. The RAM block layout is different between device families, so this * function can be used in a generic way to power down a RAM memory region * which is known to be unused. * * This function will only power down blocks which are completely enclosed * by the memory range given by [start, end). * * This is an example to power down all RAM blocks except the first * one. The first RAM block is special in that it cannot be powered down * by the hardware. The size of the first RAM block is device-specific. * See the reference manual to find the RAM block sizes. * * @code * EMU_RamPowerDown(SRAM_BASE, SRAM_BASE + SRAM_SIZE); * @endcode * * @note * Only a reset can power up the specified memory block(s) after power down * on a series 0 device. * * @param[in] start * The start address of the RAM region to power down. This address is * inclusive. * * @param[in] end * The end address of the RAM region to power down. This address is * exclusive. If this parameter is 0, all RAM blocks contained in the * region from start to the upper RAM address will be powered down. ******************************************************************************/ void EMU_RamPowerDown(uint32_t start, uint32_t end) { uint32_t mask = 0; if (end == 0U) { end = SRAM_BASE + SRAM_SIZE; } // Check to see if something in RAM0 can be powered down. if (end > RAM0_END) { #if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_84) // EFM32xG12 and EFR32xG12 // Block 0 is 16 kB and cannot be powered off. mask |= ADDRESS_NOT_IN_BLOCK(start, 0x20004000UL) << 0; // Block 1, 16 kB mask |= ADDRESS_NOT_IN_BLOCK(start, 0x20008000UL) << 1; // Block 2, 16 kB mask |= ADDRESS_NOT_IN_BLOCK(start, 0x2000C000UL) << 2; // Block 3, 16 kB mask |= ADDRESS_NOT_IN_BLOCK(start, 0x20010000UL) << 3; // Block 4, 64 kB #elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) // EFM32xG1 and EFR32xG1 // Block 0 is 4 kB and cannot be powered off. mask |= ADDRESS_NOT_IN_BLOCK(start, 0x20001000UL) << 0; // Block 1, 4 kB mask |= ADDRESS_NOT_IN_BLOCK(start, 0x20002000UL) << 1; // Block 2, 8 kB mask |= ADDRESS_NOT_IN_BLOCK(start, 0x20004000UL) << 2; // Block 3, 8 kB mask |= ADDRESS_NOT_IN_BLOCK(start, 0x20006000UL) << 3; // Block 4, 7 kB #elif defined(RAM0_BLOCKS) // These platforms have equally-sized RAM blocks. for (unsigned i = 1; i < RAM0_BLOCKS; i++) { mask |= ADDRESS_NOT_IN_BLOCK(start, RAM_MEM_BASE + (i * RAM0_BLOCK_SIZE)) << (i - 1U); } #endif } // Power down the selected blocks. #if defined(_EMU_MEMCTRL_MASK) EMU->MEMCTRL = EMU->MEMCTRL | mask; #elif defined(_EMU_RAM0CTRL_MASK) EMU->RAM0CTRL = EMU->RAM0CTRL | mask; #elif defined(_SILICON_LABS_32B_SERIES_2) SYSCFG->DMEM0RETNCTRL = SYSCFG->DMEM0RETNCTRL | mask; #else // These devices are unable to power down RAM blocks. (void) mask; (void) start; #endif #if defined(RAM1_MEM_END) mask = 0; if (end > RAM1_MEM_END) { for (unsigned i = 0; i < RAM1_BLOCKS; i++) { mask |= ADDRESS_NOT_IN_BLOCK(start, RAM1_MEM_BASE + (i * RAM1_BLOCK_SIZE)) << i; } } EMU->RAM1CTRL |= mask; #endif #if defined(RAM2_MEM_END) mask = 0; if (end > RAM2_MEM_END) { for (unsigned i = 0; i < RAM2_BLOCKS; i++) { mask |= ADDRESS_NOT_IN_BLOCK(start, RAM2_MEM_BASE + (i * RAM2_BLOCK_SIZE)) << i; } } EMU->RAM2CTRL |= mask; #endif } /***************************************************************************//** * @brief * Power up all available RAM memory blocks. * * @details * This function will power up all the RAM blocks on a device, this means * that the RAM blocks are retained in EM2/EM3. Note that this functionality * is not supported on Series 0 devices. Only a reset will power up the RAM * blocks on a series 0 device. ******************************************************************************/ void EMU_RamPowerUp(void) { #if defined(_EMU_RAM0CTRL_MASK) EMU->RAM0CTRL = 0x0; #endif #if defined(_EMU_RAM1CTRL_MASK) EMU->RAM1CTRL = 0x0; #endif #if defined(_EMU_RAM2CTRL_MASK) EMU->RAM2CTRL = 0x0; #endif } #if defined(_EMU_EM23PERNORETAINCTRL_MASK) /***************************************************************************//** * @brief * Set EM2 3 peripheral retention control. * * @param[in] periMask * A peripheral select mask. Use | operator to select multiple peripherals, for example * @ref emuPeripheralRetention_LEUART0 | @ref emuPeripheralRetention_VDAC0. * @param[in] enable * Peripheral retention enable (true) or disable (false). * * * @note * Only peripheral retention disable is currently supported. Peripherals are * enabled by default and can only be disabled. ******************************************************************************/ void EMU_PeripheralRetention(EMU_PeripheralRetention_TypeDef periMask, bool enable) { EFM_ASSERT(!enable); EMU->EM23PERNORETAINCTRL = (uint32_t)periMask & (uint32_t)emuPeripheralRetention_ALL; } #endif /***************************************************************************//** * @brief * Update EMU module with CMU oscillator selection/enable status. * * @deprecated * Oscillator status is saved in @ref EMU_EnterEM2() and @ref EMU_EnterEM3(). ******************************************************************************/ void EMU_UpdateOscConfig(void) { emState(emState_Save); } #if defined(EMU_VSCALE_PRESENT) /***************************************************************************//** * @brief * Voltage scale in EM0 and 1 by clock frequency. * * @param[in] clockFrequency * Use CMSIS HF clock if 0 or override to custom clock. Providing a * custom clock frequency is required if using a non-standard HFXO * frequency. * @param[in] wait * Wait for scaling to complete. * * @note * This function is primarily needed by the @ref CMU module. ******************************************************************************/ void EMU_VScaleEM01ByClock(uint32_t clockFrequency, bool wait) { uint32_t hfSrcClockFrequency; uint32_t hfPresc = 1U + ((CMU->HFPRESC & _CMU_HFPRESC_PRESC_MASK) >> _CMU_HFPRESC_PRESC_SHIFT); /* VSCALE frequency is HFSRCCLK. */ if (clockFrequency == 0U) { hfSrcClockFrequency = SystemHFClockGet() * hfPresc; } else { hfSrcClockFrequency = clockFrequency; } /* Apply EM0 and 1 voltage scaling command. */ if (vScaleEM01Config.vScaleEM01LowPowerVoltageEnable && (hfSrcClockFrequency < CMU_VSCALEEM01_LOWPOWER_VOLTAGE_CLOCK_MAX)) { EMU_VScaleEM01(emuVScaleEM01_LowPower, wait); } else { EMU_VScaleEM01(emuVScaleEM01_HighPerformance, wait); } } #endif #if defined(EMU_VSCALE_PRESENT) /***************************************************************************//** * @brief * Force voltage scaling in EM0 and 1 to a specific voltage level. * * @param[in] voltage * Target VSCALE voltage level. * @param[in] wait * Wait for scaling to complete. * * @note * This function is useful for upscaling before programming Flash from @ref MSC * and downscaling after programming is done. Flash programming is only supported * at @ref emuVScaleEM01_HighPerformance. * * @note * This function ignores @ref vScaleEM01LowPowerVoltageEnable set from @ref * EMU_EM01Init(). ******************************************************************************/ void EMU_VScaleEM01(EMU_VScaleEM01_TypeDef voltage, bool wait) { uint32_t hfSrcClockFrequency; uint32_t hfPresc = 1U + ((CMU->HFPRESC & _CMU_HFPRESC_PRESC_MASK) >> _CMU_HFPRESC_PRESC_SHIFT); uint32_t hfFreq = SystemHFClockGet(); EMU_VScaleEM01_TypeDef current = EMU_VScaleGet(); if (current == voltage) { /* Voltage is already at the correct level. */ return; } hfSrcClockFrequency = hfFreq * hfPresc; if (voltage == emuVScaleEM01_LowPower) { EFM_ASSERT(hfSrcClockFrequency <= CMU_VSCALEEM01_LOWPOWER_VOLTAGE_CLOCK_MAX); /* Update wait states before scaling down voltage. */ CMU_UpdateWaitStates(hfFreq, (int)emuVScaleEM01_LowPower); } EMU->CMD = vScaleEM01Cmd(voltage); if (wait) { EMU_VScaleWait(); } if (voltage == emuVScaleEM01_HighPerformance) { /* Update wait states after scaling up voltage. */ CMU_UpdateWaitStates(hfFreq, (int)emuVScaleEM01_HighPerformance); } } #endif #if defined(EMU_VSCALE_PRESENT) /***************************************************************************//** * @brief * Update the EMU module with Energy Mode 0 and 1 configuration. * * @param[in] em01Init * Energy Mode 0 and 1 configuration structure. ******************************************************************************/ void EMU_EM01Init(const EMU_EM01Init_TypeDef *em01Init) { vScaleEM01Config.vScaleEM01LowPowerVoltageEnable = em01Init->vScaleEM01LowPowerVoltageEnable; EMU_VScaleEM01ByClock(0, true); } #endif /***************************************************************************//** * @brief * Update the EMU module with Energy Mode 2 and 3 configuration. * * @param[in] em23Init * Energy Mode 2 and 3 configuration structure. ******************************************************************************/ void EMU_EM23Init(const EMU_EM23Init_TypeDef *em23Init) { #if defined(_EMU_CTRL_EMVREG_MASK) EMU->CTRL = em23Init->em23VregFullEn ? (EMU->CTRL | EMU_CTRL_EMVREG) : (EMU->CTRL & ~EMU_CTRL_EMVREG); #elif defined(_EMU_CTRL_EM23VREG_MASK) EMU->CTRL = em23Init->em23VregFullEn ? (EMU->CTRL | EMU_CTRL_EM23VREG) : (EMU->CTRL & ~EMU_CTRL_EM23VREG); #else (void)em23Init; #endif #if defined(_EMU_CTRL_EM23VSCALE_MASK) EMU->CTRL = (EMU->CTRL & ~_EMU_CTRL_EM23VSCALE_MASK) | ((uint32_t)em23Init->vScaleEM23Voltage << _EMU_CTRL_EM23VSCALE_SHIFT); if (em23Init->vScaleEM23Voltage == emuVScaleEM23_LowPower) { /* Voltage scaling is not compatible with HFXO auto start and select. */ EFM_ASSERT((CMU->HFXOCTRL & CMU_HFXOCTRL_AUTOSTARTSELEM0EM1) == 0U); } #endif } #if defined(_EMU_EM4CONF_MASK) || defined(_EMU_EM4CTRL_MASK) /***************************************************************************//** * @brief * Update the EMU module with Energy Mode 4 configuration. * * @param[in] em4Init * Energy Mode 4 configuration structure. ******************************************************************************/ void EMU_EM4Init(const EMU_EM4Init_TypeDef *em4Init) { #if defined(_EMU_EM4CONF_MASK) /* Initialization for platforms with EMU->EM4CONF register. */ uint32_t em4conf = EMU->EM4CONF; /* Clear fields that will be reconfigured. */ em4conf &= ~(_EMU_EM4CONF_LOCKCONF_MASK | _EMU_EM4CONF_OSC_MASK | _EMU_EM4CONF_BURTCWU_MASK | _EMU_EM4CONF_VREGEN_MASK | _EMU_EM4CONF_BUBODRSTDIS_MASK); /* Configure new settings. */ em4conf |= (em4Init->lockConfig << _EMU_EM4CONF_LOCKCONF_SHIFT) | (em4Init->osc) | (em4Init->buRtcWakeup << _EMU_EM4CONF_BURTCWU_SHIFT) | (em4Init->vreg << _EMU_EM4CONF_VREGEN_SHIFT) | (em4Init->buBodRstDis << _EMU_EM4CONF_BUBODRSTDIS_SHIFT); /* Apply configuration. Note that lock can be set after this stage. */ EMU->EM4CONF = em4conf; #elif defined(_EMU_EM4CTRL_EM4STATE_MASK) /* Initialization for platforms with EMU->EM4CTRL register and EM4H and EM4S. */ uint32_t em4ctrl = EMU->EM4CTRL; em4ctrl &= ~(_EMU_EM4CTRL_RETAINLFXO_MASK | _EMU_EM4CTRL_RETAINLFRCO_MASK | _EMU_EM4CTRL_RETAINULFRCO_MASK | _EMU_EM4CTRL_EM4STATE_MASK | _EMU_EM4CTRL_EM4IORETMODE_MASK); em4ctrl |= (em4Init->retainLfxo ? EMU_EM4CTRL_RETAINLFXO : 0U) | (em4Init->retainLfrco ? EMU_EM4CTRL_RETAINLFRCO : 0U) | (em4Init->retainUlfrco ? EMU_EM4CTRL_RETAINULFRCO : 0U) | (em4Init->em4State == emuEM4Hibernate ? EMU_EM4CTRL_EM4STATE_EM4H : 0U) | ((uint32_t)em4Init->pinRetentionMode); EMU->EM4CTRL = em4ctrl; #elif defined(_EMU_EM4CTRL_MASK) EMU->EM4CTRL = (EMU->EM4CTRL & ~_EMU_EM4CTRL_EM4IORETMODE_MASK) | (uint32_t)em4Init->pinRetentionMode; #endif #if defined(_EMU_CTRL_EM4HVSCALE_MASK) EMU->CTRL = (EMU->CTRL & ~_EMU_CTRL_EM4HVSCALE_MASK) | ((uint32_t)em4Init->vScaleEM4HVoltage << _EMU_CTRL_EM4HVSCALE_SHIFT); #endif } #endif #if defined(BU_PRESENT) && defined(_SILICON_LABS_32B_SERIES_0) /***************************************************************************//** * @brief * Configure Backup Power Domain settings. * * @param[in] bupdInit * Backup power domain initialization structure. ******************************************************************************/ void EMU_BUPDInit(const EMU_BUPDInit_TypeDef *bupdInit) { uint32_t reg; /* Set the power connection configuration. */ reg = EMU->PWRCONF & ~(_EMU_PWRCONF_PWRRES_MASK | _EMU_PWRCONF_VOUTSTRONG_MASK | _EMU_PWRCONF_VOUTMED_MASK | _EMU_PWRCONF_VOUTWEAK_MASK); reg |= bupdInit->resistor | (bupdInit->voutStrong << _EMU_PWRCONF_VOUTSTRONG_SHIFT) | (bupdInit->voutMed << _EMU_PWRCONF_VOUTMED_SHIFT) | (bupdInit->voutWeak << _EMU_PWRCONF_VOUTWEAK_SHIFT); EMU->PWRCONF = reg; /* Set the backup domain inactive mode configuration. */ reg = EMU->BUINACT & ~(_EMU_BUINACT_PWRCON_MASK); reg |= (bupdInit->inactivePower); EMU->BUINACT = reg; /* Set the backup domain active mode configuration. */ reg = EMU->BUACT & ~(_EMU_BUACT_PWRCON_MASK); reg |= (bupdInit->activePower); EMU->BUACT = reg; /* Set the power control configuration */ reg = EMU->BUCTRL & ~(_EMU_BUCTRL_PROBE_MASK | _EMU_BUCTRL_BODCAL_MASK | _EMU_BUCTRL_STATEN_MASK | _EMU_BUCTRL_EN_MASK); /* Note the use of ->enable to enable BUPD. Use BU_VIN pin input and release reset. */ reg |= bupdInit->probe | (bupdInit->bodCal << _EMU_BUCTRL_BODCAL_SHIFT) | (bupdInit->statusPinEnable << _EMU_BUCTRL_STATEN_SHIFT) | (bupdInit->enable << _EMU_BUCTRL_EN_SHIFT); /* Enable configuration. */ EMU->BUCTRL = reg; /* If enable is true, enable BU_VIN input power pin. If not, disable it. */ EMU_BUPinEnable(bupdInit->enable); /* If enable is true, release BU reset. If not, keep reset asserted. */ BUS_RegBitWrite(&(RMU->CTRL), _RMU_CTRL_BURSTEN_SHIFT, !bupdInit->enable); } /***************************************************************************//** * @brief * Configure the Backup Power Domain BOD Threshold value. * @note * These values are precalibrated. * @param[in] mode Active or Inactive mode * @param[in] value ******************************************************************************/ void EMU_BUThresholdSet(EMU_BODMode_TypeDef mode, uint32_t value) { EFM_ASSERT(value < 8); EFM_ASSERT(value <= (_EMU_BUACT_BUEXTHRES_MASK >> _EMU_BUACT_BUEXTHRES_SHIFT)); switch (mode) { case emuBODMode_Active: EMU->BUACT = (EMU->BUACT & ~_EMU_BUACT_BUEXTHRES_MASK) | (value << _EMU_BUACT_BUEXTHRES_SHIFT); break; case emuBODMode_Inactive: EMU->BUINACT = (EMU->BUINACT & ~_EMU_BUINACT_BUENTHRES_MASK) | (value << _EMU_BUINACT_BUENTHRES_SHIFT); break; } } /***************************************************************************//** * @brief * Configure the Backup Power Domain BOD Threshold Range. * @note * These values are precalibrated. * @param[in] mode Active or Inactive mode * @param[in] value ******************************************************************************/ void EMU_BUThresRangeSet(EMU_BODMode_TypeDef mode, uint32_t value) { EFM_ASSERT(value < 4); EFM_ASSERT(value <= (_EMU_BUACT_BUEXRANGE_MASK >> _EMU_BUACT_BUEXRANGE_SHIFT)); switch (mode) { case emuBODMode_Active: EMU->BUACT = (EMU->BUACT & ~_EMU_BUACT_BUEXRANGE_MASK) | (value << _EMU_BUACT_BUEXRANGE_SHIFT); break; case emuBODMode_Inactive: EMU->BUINACT = (EMU->BUINACT & ~_EMU_BUINACT_BUENRANGE_MASK) | (value << _EMU_BUINACT_BUENRANGE_SHIFT); break; } } #endif #if defined(BU_PRESENT) && defined(_SILICON_LABS_32B_SERIES_1) /***************************************************************************//** * @brief * Configure Backup Power Domain settings. * * @param[in] buInit * Backup power domain initialization structure. ******************************************************************************/ void EMU_BUInit(const EMU_BUInit_TypeDef *buInit) { uint32_t reg = 0; /* Set the backup power configuration. */ reg |= (buInit->disMaxComp << _EMU_BUCTRL_DISMAXCOMP_SHIFT); reg |= (uint32_t)(buInit->inactivePwrCon); reg |= (uint32_t)(buInit->activePwrCon); reg |= (uint32_t)(buInit->pwrRes); reg |= (uint32_t)(buInit->voutRes); reg |= (buInit->buVinProbeEn << _EMU_BUCTRL_BUVINPROBEEN_SHIFT); reg |= (buInit->staEn << _EMU_BUCTRL_STATEN_SHIFT); reg |= (buInit->enable << _EMU_BUCTRL_EN_SHIFT); EMU->BUCTRL = reg; } #endif #if defined(_EMU_BUCTRL_DISMAXCOMP_MASK) void EMU_BUDisMaxCompSet(bool disableMainBuComparator) { uint32_t reg; reg = EMU->BUCTRL & ~(_EMU_BUCTRL_DISMAXCOMP_MASK); reg |= (disableMainBuComparator << _EMU_BUCTRL_DISMAXCOMP_SHIFT); EMU->BUCTRL = reg; } #endif #if defined(_EMU_BUCTRL_BUINACTPWRCON_MASK) void EMU_BUBuInactPwrConSet(EMU_BUBuInactPwrCon_TypeDef inactPwrCon) { uint32_t reg; reg = EMU->BUCTRL & ~(_EMU_BUCTRL_BUINACTPWRCON_MASK); reg |= (uint32_t)(inactPwrCon); EMU->BUCTRL = reg; } #endif #if defined(_EMU_BUCTRL_BUACTPWRCON_MASK) void EMU_BUBuActPwrConSet(EMU_BUBuActPwrCon_TypeDef actPwrCon) { uint32_t reg; reg = EMU->BUCTRL & ~(_EMU_BUCTRL_BUACTPWRCON_MASK); reg |= (uint32_t)(actPwrCon); EMU->BUCTRL = reg; } #endif #if defined(_EMU_BUCTRL_PWRRES_MASK) void EMU_BUPwrResSet(EMU_BUPwrRes_TypeDef pwrRes) { uint32_t reg; reg = EMU->BUCTRL & ~(_EMU_BUCTRL_PWRRES_MASK); reg |= (uint32_t)(pwrRes); EMU->BUCTRL = reg; } #endif #if defined(_EMU_BUCTRL_VOUTRES_MASK) void EMU_BUVoutResSet(EMU_BUVoutRes_TypeDef resistorSel) { uint32_t reg; reg = EMU->BUCTRL & ~(_EMU_BUCTRL_VOUTRES_MASK); reg |= (uint32_t)(resistorSel); EMU->BUCTRL = reg; } #endif #if defined(_EMU_BUCTRL_BUVINPROBEEN_MASK) void EMU_BUBuVinProbeEnSet(bool enable) { uint32_t reg; reg = EMU->BUCTRL & ~(_EMU_BUCTRL_BUVINPROBEEN_MASK); reg |= (enable << _EMU_BUCTRL_BUVINPROBEEN_SHIFT); EMU->BUCTRL = reg; } #endif #if defined(_EMU_BUCTRL_STATEN_MASK) void EMU_BUStatEnSet(bool enable) { uint32_t reg; reg = EMU->BUCTRL & ~(_EMU_BUCTRL_STATEN_MASK); reg |= (enable << _EMU_BUCTRL_STATEN_SHIFT); EMU->BUCTRL = reg; } #endif #if defined(_EMU_BUCTRL_EN_MASK) void EMU_BUEnableSet(bool enable) { uint32_t reg; reg = EMU->BUCTRL & ~(_EMU_BUCTRL_EN_MASK); reg |= (enable << _EMU_BUCTRL_EN_SHIFT); EMU->BUCTRL = reg; } #endif /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ #if defined(_EMU_DCDCCTRL_MASK) /* Translate fields with different names across platform generations to common names. */ #if defined(_EMU_DCDCMISCCTRL_LPCMPBIAS_MASK) #define _GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_MASK _EMU_DCDCMISCCTRL_LPCMPBIAS_MASK #define _GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT _EMU_DCDCMISCCTRL_LPCMPBIAS_SHIFT #elif defined(_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_MASK) #define _GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_MASK _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_MASK #define _GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT #endif #if defined(_EMU_DCDCLPCTRL_LPCMPHYSSEL_MASK) #define _GENERIC_DCDCLPCTRL_LPCMPHYSSELEM234H_MASK _EMU_DCDCLPCTRL_LPCMPHYSSEL_MASK #define _GENERIC_DCDCLPCTRL_LPCMPHYSSELEM234H_SHIFT _EMU_DCDCLPCTRL_LPCMPHYSSEL_SHIFT #elif defined(_EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_MASK) #define _GENERIC_DCDCLPCTRL_LPCMPHYSSELEM234H_MASK _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_MASK #define _GENERIC_DCDCLPCTRL_LPCMPHYSSELEM234H_SHIFT _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_SHIFT #endif /* Internal DCDC trim modes. */ typedef enum { dcdcTrimMode_EM234H_LP = 0, #if defined(_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK) dcdcTrimMode_EM01_LP, #endif dcdcTrimMode_LN, } dcdcTrimMode_TypeDef; /***************************************************************************//** * @brief * Load DCDC calibration constants from the DI page. A constant means that calibration * data that does not change depending on other configuration parameters. * * @return * False if calibration registers are locked. ******************************************************************************/ static bool dcdcConstCalibrationLoad(void) { #if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) uint32_t val; volatile uint32_t *reg; /* DI calibration data in Flash. */ volatile uint32_t* const diCal_EMU_DCDCLNFREQCTRL = (volatile uint32_t *)(0x0FE08038); volatile uint32_t* const diCal_EMU_DCDCLNVCTRL = (volatile uint32_t *)(0x0FE08040); volatile uint32_t* const diCal_EMU_DCDCLPCTRL = (volatile uint32_t *)(0x0FE08048); volatile uint32_t* const diCal_EMU_DCDCLPVCTRL = (volatile uint32_t *)(0x0FE08050); volatile uint32_t* const diCal_EMU_DCDCTRIM0 = (volatile uint32_t *)(0x0FE08058); volatile uint32_t* const diCal_EMU_DCDCTRIM1 = (volatile uint32_t *)(0x0FE08060); if (DEVINFO->DCDCLPVCTRL0 != UINT_MAX) { val = *(diCal_EMU_DCDCLNFREQCTRL + 1); reg = (volatile uint32_t *)*diCal_EMU_DCDCLNFREQCTRL; *reg = val; val = *(diCal_EMU_DCDCLNVCTRL + 1); reg = (volatile uint32_t *)*diCal_EMU_DCDCLNVCTRL; *reg = val; val = *(diCal_EMU_DCDCLPCTRL + 1); reg = (volatile uint32_t *)*diCal_EMU_DCDCLPCTRL; *reg = val; val = *(diCal_EMU_DCDCLPVCTRL + 1); reg = (volatile uint32_t *)*diCal_EMU_DCDCLPVCTRL; *reg = val; val = *(diCal_EMU_DCDCTRIM0 + 1); reg = (volatile uint32_t *)*diCal_EMU_DCDCTRIM0; *reg = val; val = *(diCal_EMU_DCDCTRIM1 + 1); reg = (volatile uint32_t *)*diCal_EMU_DCDCTRIM1; *reg = val; return true; } EFM_ASSERT(false); /* Return when assertions are disabled. */ return false; #else return true; #endif } /***************************************************************************//** * @brief * Set recommended and validated current optimization and timing settings. * ******************************************************************************/ static void dcdcValidatedConfigSet(void) { /* Disable LP mode hysteresis in the state machine control. */ #define EMU_DCDCMISCCTRL_LPCMPHYSDIS (0x1UL << 1) /* Comparator threshold on the high side. */ #define EMU_DCDCMISCCTRL_LPCMPHYSHI (0x1UL << 2) #define EMU_DCDCSMCTRL (*(volatile uint32_t *)(EMU_BASE + 0x44)) uint32_t lnForceCcm; #if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) uint32_t dcdcTiming; SYSTEM_ChipRevision_TypeDef rev; #endif /* Enable duty cycling of the bias. */ EMU->DCDCLPCTRL |= EMU_DCDCLPCTRL_LPVREFDUTYEN; /* Set low-noise RCO for LNFORCECCM configuration. * LNFORCECCM is default 1 for EFR32 * LNFORCECCM is default 0 for EFM32 */ lnForceCcm = BUS_RegBitRead(&EMU->DCDCMISCCTRL, _EMU_DCDCMISCCTRL_LNFORCECCM_SHIFT); if (lnForceCcm != 0U) { /* 7 MHz is recommended for LNFORCECCM = 1. */ EMU_DCDCLnRcoBandSet(emuDcdcLnRcoBand_7MHz); } else { /* 3 MHz is recommended for LNFORCECCM = 0. */ EMU_DCDCLnRcoBandSet(emuDcdcLnRcoBand_3MHz); } #if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) EMU->DCDCTIMING &= ~_EMU_DCDCTIMING_DUTYSCALE_MASK; EMU->DCDCMISCCTRL |= EMU_DCDCMISCCTRL_LPCMPHYSDIS | EMU_DCDCMISCCTRL_LPCMPHYSHI; SYSTEM_ChipRevisionGet(&rev); if ((rev.major == 1) && (rev.minor < 3) && (errataFixDcdcHsState == errataFixDcdcHsInit)) { /* LPCMPWAITDIS = 1 */ EMU_DCDCSMCTRL |= 1; dcdcTiming = EMU->DCDCTIMING; dcdcTiming &= ~(_EMU_DCDCTIMING_LPINITWAIT_MASK | _EMU_DCDCTIMING_LNWAIT_MASK | _EMU_DCDCTIMING_BYPWAIT_MASK); dcdcTiming |= ((180 << _EMU_DCDCTIMING_LPINITWAIT_SHIFT) | (12 << _EMU_DCDCTIMING_LNWAIT_SHIFT) | (180 << _EMU_DCDCTIMING_BYPWAIT_SHIFT)); EMU->DCDCTIMING = dcdcTiming; errataFixDcdcHsState = errataFixDcdcHsTrimSet; } #endif } /***************************************************************************//** * @brief * Compute current limiters: * LNCLIMILIMSEL: LN current limiter threshold * LPCLIMILIMSEL: LP current limiter threshold * DCDCZDETCTRL: zero detector limiter threshold ******************************************************************************/ static void currentLimitersUpdate(void) { uint32_t lncLimSel; uint32_t zdetLimSel; uint32_t pFetCnt; uint16_t maxReverseCurrent_mA; /* 80 mA as recommended peak in Application Note AN0948. The peak current is the average current plus 50% of the current ripple. Hence, a 14 mA average current is recommended in LP mode. Since LP PFETCNT is also a constant, lpcLimImSel = 1. The following calculation is provided for documentation only. */ const uint32_t lpcLim = (((14 + 40) + ((14 + 40) / 2)) / (5 * (DCDC_LP_PFET_CNT + 1))) - 1; const uint32_t lpcLimSel = lpcLim << _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_SHIFT; /* Get enabled PFETs. */ pFetCnt = (EMU->DCDCMISCCTRL & _EMU_DCDCMISCCTRL_PFETCNT_MASK) >> _EMU_DCDCMISCCTRL_PFETCNT_SHIFT; /* Compute the LN current limiter threshold from the nominal user input current and LN PFETCNT as described in the register description for EMU_DCDCMISCCTRL_LNCLIMILIMSEL. */ lncLimSel = ((((uint32_t)dcdcMaxCurrent_mA + 40U) + (((uint32_t)dcdcMaxCurrent_mA + 40U) / 2U)) / (5U * (pFetCnt + 1U))) - 1U; /* Saturate the register field value. */ lncLimSel = SL_MIN(lncLimSel, _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_MASK >> _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_SHIFT); lncLimSel <<= _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_SHIFT; /* Check for overflow. */ EFM_ASSERT((lncLimSel & ~_EMU_DCDCMISCCTRL_LNCLIMILIMSEL_MASK) == 0x0U); EFM_ASSERT((lpcLimSel & ~_EMU_DCDCMISCCTRL_LPCLIMILIMSEL_MASK) == 0x0U); EMU->DCDCMISCCTRL = (EMU->DCDCMISCCTRL & ~(_EMU_DCDCMISCCTRL_LNCLIMILIMSEL_MASK | _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_MASK)) | (lncLimSel | lpcLimSel); /* Compute the reverse current limit threshold for the zero detector from the user input maximum reverse current and LN PFETCNT as described in the register description for EMU_DCDCZDETCTRL_ZDETILIMSEL. */ if (dcdcReverseCurrentControl >= 0) { /* If dcdcReverseCurrentControl < 0, EMU_DCDCZDETCTRL_ZDETILIMSEL is "don't care". */ maxReverseCurrent_mA = (uint16_t)dcdcReverseCurrentControl; zdetLimSel = ((((uint32_t)maxReverseCurrent_mA + 40U) + (((uint32_t)maxReverseCurrent_mA + 40U) / 2U)) / ((2U * (pFetCnt + 1U)) + ((pFetCnt + 1U) / 2U))); /* Saturate the register field value. */ zdetLimSel = SL_MIN(zdetLimSel, _EMU_DCDCZDETCTRL_ZDETILIMSEL_MASK >> _EMU_DCDCZDETCTRL_ZDETILIMSEL_SHIFT); zdetLimSel <<= _EMU_DCDCZDETCTRL_ZDETILIMSEL_SHIFT; /* Check for overflow. */ EFM_ASSERT((zdetLimSel & ~_EMU_DCDCZDETCTRL_ZDETILIMSEL_MASK) == 0x0U); EMU->DCDCZDETCTRL = (EMU->DCDCZDETCTRL & ~_EMU_DCDCZDETCTRL_ZDETILIMSEL_MASK) | zdetLimSel; } } /***************************************************************************//** * @brief * Set static variables that hold the user set maximum peak current * and reverse current. Update limiters. * * @param[in] maxCurrent_mA * Set the maximum peak current that the DCDC can draw from the power source. * @param[in] reverseCurrentControl * Reverse the current control as defined by * @ref EMU_DcdcLnReverseCurrentControl_TypeDef. Positive values have unit mA. ******************************************************************************/ static void userCurrentLimitsSet(uint32_t maxCurrent_mA, EMU_DcdcLnReverseCurrentControl_TypeDef reverseCurrentControl) { dcdcMaxCurrent_mA = (uint16_t)maxCurrent_mA; dcdcReverseCurrentControl = reverseCurrentControl; } /***************************************************************************//** * @brief * Set DCDC low noise compensator control register. * * @param[in] comp * Low-noise mode compensator trim setpoint. ******************************************************************************/ static void compCtrlSet(EMU_DcdcLnCompCtrl_TypeDef comp) { switch (comp) { case emuDcdcLnCompCtrl_1u0F: EMU->DCDCLNCOMPCTRL = 0x57204077UL; break; case emuDcdcLnCompCtrl_4u7F: EMU->DCDCLNCOMPCTRL = 0xB7102137UL; break; default: EFM_ASSERT(false); break; } } /***************************************************************************//** * @brief * Load EMU_DCDCLPCTRL_LPCMPHYSSEL depending on LP bias, LP feedback * attenuation, and DEVINFOREV. * * @param[in] lpAttenuation * LP feedback attenuation. * @param[in] lpCmpBias * lpCmpBias selection. * @param[in] trimMode * DCDC trim mode. ******************************************************************************/ static bool lpCmpHystCalibrationLoad(bool lpAttenuation, uint8_t lpCmpBias, dcdcTrimMode_TypeDef trimMode) { uint32_t lpcmpHystSel; #if !defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) (void)lpAttenuation; #endif /* Get calibration data revision. */ #if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) uint8_t devinfoRev = SYSTEM_GetDevinfoRev(); /* Load LPATT indexed calibration data. */ if (devinfoRev < 4) { lpcmpHystSel = DEVINFO->DCDCLPCMPHYSSEL0; if (lpAttenuation) { lpcmpHystSel = (lpcmpHystSel & _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT1_MASK) >> _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT1_SHIFT; } else { lpcmpHystSel = (lpcmpHystSel & _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT0_MASK) >> _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT0_SHIFT; } } else #endif { /* devinfoRev >= 4: load LPCMPBIAS indexed calibration data. */ lpcmpHystSel = DEVINFO->DCDCLPCMPHYSSEL1; switch (lpCmpBias) { case 0: lpcmpHystSel = (lpcmpHystSel & _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS0_MASK) >> _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS0_SHIFT; break; case 1: lpcmpHystSel = (lpcmpHystSel & _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS1_MASK) >> _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS1_SHIFT; break; case 2: lpcmpHystSel = (lpcmpHystSel & _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS2_MASK) >> _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS2_SHIFT; break; case 3: lpcmpHystSel = (lpcmpHystSel & _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS3_MASK) >> _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS3_SHIFT; break; default: EFM_ASSERT(false); /* Return when assertions are disabled. */ return false; } } /* Set trims. */ if (trimMode == dcdcTrimMode_EM234H_LP) { /* Make sure the sel value is within the field range. */ lpcmpHystSel <<= _GENERIC_DCDCLPCTRL_LPCMPHYSSELEM234H_SHIFT; if ((lpcmpHystSel & ~_GENERIC_DCDCLPCTRL_LPCMPHYSSELEM234H_MASK) != 0U) { EFM_ASSERT(false); /* Return when assertions are disabled. */ return false; } EMU->DCDCLPCTRL = (EMU->DCDCLPCTRL & ~_GENERIC_DCDCLPCTRL_LPCMPHYSSELEM234H_MASK) | lpcmpHystSel; } #if defined(_EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_MASK) if (trimMode == dcdcTrimMode_EM01_LP) { /* Make sure the sel value is within the field range. */ lpcmpHystSel <<= _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_SHIFT; if ((lpcmpHystSel & ~_EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_MASK) != 0U) { EFM_ASSERT(false); /* Return when assertions are disabled. */ return false; } EMU->DCDCLPEM01CFG = (EMU->DCDCLPEM01CFG & ~_EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_MASK) | lpcmpHystSel; } #endif return true; } /***************************************************************************//** * @brief * Load LPVREF low and high from DEVINFO. * * @param[out] vrefL * LPVREF low from DEVINFO. * @param[out] vrefH * LPVREF high from DEVINFO. * @param[in] lpAttenuation * LP feedback attenuation. * @param[in] lpcmpBias * lpcmpBias to look up in DEVINFO. ******************************************************************************/ static void lpGetDevinfoVrefLowHigh(uint32_t *vrefL, uint32_t *vrefH, bool lpAttenuation, uint8_t lpcmpBias) { uint32_t vrefLow = 0; uint32_t vrefHigh = 0; /* Find VREF high and low in DEVINFO indexed by LPCMPBIAS (lpcmpBias) and LPATT (lpAttenuation) */ uint32_t switchVal = ((uint32_t)lpcmpBias << 8) | (lpAttenuation ? 1U : 0U); switch (switchVal) { case ((0 << 8) | 1): vrefLow = DEVINFO->DCDCLPVCTRL2; vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS0_MASK) >> _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS0_SHIFT; vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS0_MASK) >> _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS0_SHIFT; break; case ((1 << 8) | 1): vrefLow = DEVINFO->DCDCLPVCTRL2; vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS1_MASK) >> _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS1_SHIFT; vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS1_MASK) >> _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS1_SHIFT; break; case ((2 << 8) | 1): vrefLow = DEVINFO->DCDCLPVCTRL3; vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS2_MASK) >> _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS2_SHIFT; vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS2_MASK) >> _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS2_SHIFT; break; case ((3 << 8) | 1): vrefLow = DEVINFO->DCDCLPVCTRL3; vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS3_MASK) >> _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS3_SHIFT; vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS3_MASK) >> _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS3_SHIFT; break; case ((0 << 8) | 0): vrefLow = DEVINFO->DCDCLPVCTRL0; vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS0_MASK) >> _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS0_SHIFT; vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS0_MASK) >> _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS0_SHIFT; break; case ((1 << 8) | 0): vrefLow = DEVINFO->DCDCLPVCTRL0; vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS1_MASK) >> _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS1_SHIFT; vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS1_MASK) >> _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS1_SHIFT; break; case ((2 << 8) | 0): vrefLow = DEVINFO->DCDCLPVCTRL1; vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS2_MASK) >> _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS2_SHIFT; vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS2_MASK) >> _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS2_SHIFT; break; case ((3 << 8) | 0): vrefLow = DEVINFO->DCDCLPVCTRL1; vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS3_MASK) >> _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS3_SHIFT; vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS3_MASK) >> _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS3_SHIFT; break; default: EFM_ASSERT(false); break; } *vrefL = vrefLow; *vrefH = vrefHigh; } /***************************************************************************//** * @brief * Set DCDC regulator operating mode. * * @param[in] dcdcMode * DCDC mode. ******************************************************************************/ void EMU_DCDCModeSet(EMU_DcdcMode_TypeDef dcdcMode) { uint32_t currentDcdcMode; /* Wait for any previous write sync to complete and read DCDC mode. */ while ((EMU->DCDCSYNC & EMU_DCDCSYNC_DCDCCTRLBUSY) != 0U) { } currentDcdcMode = (EMU->DCDCCTRL & _EMU_DCDCCTRL_DCDCMODE_MASK); /* Enable bypass current limiter when not in bypass mode to prevent excessive current between VREGVDD and DVDD supplies when reentering bypass mode. */ if (currentDcdcMode != EMU_DCDCCTRL_DCDCMODE_BYPASS) { BUS_RegBitWrite(&EMU->DCDCCLIMCTRL, _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT, 1); } if ((EMU_DcdcMode_TypeDef)currentDcdcMode == dcdcMode) { /* Mode already set. If already in bypass, make sure the bypass current limiter is disabled. */ if (dcdcMode == emuDcdcMode_Bypass) { BUS_RegBitWrite(&EMU->DCDCCLIMCTRL, _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT, 0); } return; } #if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) /* Fix for errata DCDC_E203. */ if ((currentDcdcMode == EMU_DCDCCTRL_DCDCMODE_BYPASS) && (dcdcMode == emuDcdcMode_LowNoise)) { errataFixDcdcHsState = errataFixDcdcHsBypassLn; } #else /* Fix for errata DCDC_E204. */ if (((currentDcdcMode == EMU_DCDCCTRL_DCDCMODE_OFF) || (currentDcdcMode == EMU_DCDCCTRL_DCDCMODE_BYPASS)) && ((dcdcMode == emuDcdcMode_LowPower) || (dcdcMode == emuDcdcMode_LowNoise))) { /* Always start in LOWNOISE. Switch to LOWPOWER mode once LOWNOISE startup is complete. */ EMU_IntClear(EMU_IFC_DCDCLNRUNNING); while ((EMU->DCDCSYNC & EMU_DCDCSYNC_DCDCCTRLBUSY) != 0U) { } EMU->DCDCCTRL = (EMU->DCDCCTRL & ~_EMU_DCDCCTRL_DCDCMODE_MASK) | EMU_DCDCCTRL_DCDCMODE_LOWNOISE; while ((EMU_IntGet() & EMU_IF_DCDCLNRUNNING) == 0U) { } } #endif /* Set user-requested mode. */ while ((EMU->DCDCSYNC & EMU_DCDCSYNC_DCDCCTRLBUSY) != 0UL) { } EMU->DCDCCTRL = (EMU->DCDCCTRL & ~_EMU_DCDCCTRL_DCDCMODE_MASK) | (uint32_t)dcdcMode; /* Disable bypass current limiter after bypass mode is entered. Enable the limiter if any other mode is entered. */ while ((EMU->DCDCSYNC & EMU_DCDCSYNC_DCDCCTRLBUSY) != 0U) { } BUS_RegBitWrite(&EMU->DCDCCLIMCTRL, _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT, dcdcMode == emuDcdcMode_Bypass ? 0U : 1U); } /***************************************************************************//** * @brief * Set DCDC LN regulator conduction mode. * * @param[in] conductionMode * DCDC LN conduction mode. * @param[in] rcoDefaultSet * The default DCDC RCO band for the conductionMode will be used if true. * Otherwise, the current RCO configuration is used. ******************************************************************************/ void EMU_DCDCConductionModeSet(EMU_DcdcConductionMode_TypeDef conductionMode, bool rcoDefaultSet) { EMU_DcdcMode_TypeDef currentDcdcMode = (EMU_DcdcMode_TypeDef)((uint32_t) (EMU->DCDCCTRL & _EMU_DCDCCTRL_DCDCMODE_MASK)); EMU_DcdcLnRcoBand_TypeDef rcoBand = (EMU_DcdcLnRcoBand_TypeDef)((uint32_t) ((EMU->DCDCLNFREQCTRL & _EMU_DCDCLNFREQCTRL_RCOBAND_MASK) >> _EMU_DCDCLNFREQCTRL_RCOBAND_SHIFT)); /* Set bypass mode and wait for bypass mode to settle before EMU_DCDCMISCCTRL_LNFORCECCM is set. Restore current DCDC mode. */ EMU_IntClear(EMU_IFC_DCDCINBYPASS); EMU_DCDCModeSet(emuDcdcMode_Bypass); while ((EMU->DCDCSYNC & EMU_DCDCSYNC_DCDCCTRLBUSY) != 0U) { } while ((EMU_IntGet() & EMU_IF_DCDCINBYPASS) == 0U) { } if (conductionMode == emuDcdcConductionMode_DiscontinuousLN) { EMU->DCDCMISCCTRL &= ~EMU_DCDCMISCCTRL_LNFORCECCM; if (rcoDefaultSet) { EMU_DCDCLnRcoBandSet(emuDcdcLnRcoBand_3MHz); } else { /* emuDcdcConductionMode_DiscontinuousLN supports up to 4MHz LN RCO. */ EFM_ASSERT(rcoBand <= emuDcdcLnRcoBand_4MHz); } } else { EMU->DCDCMISCCTRL |= EMU_DCDCMISCCTRL_LNFORCECCM; if (rcoDefaultSet) { EMU_DCDCLnRcoBandSet(emuDcdcLnRcoBand_7MHz); } } EMU_DCDCModeSet(currentDcdcMode); /* Update slice configuration as it depends on conduction mode and RCO band.*/ EMU_DCDCOptimizeSlice(dcdcEm01LoadCurrent_mA); } /***************************************************************************//** * @brief * Configure the DCDC regulator. * * @note * Do not call this function if the power circuit is configured for NODCDC as * described in the Power Configurations section of the Reference Manual. * Instead, call @ref EMU_DCDCPowerOff(). * * @param[in] dcdcInit * The DCDC initialization structure. * * @return * True if initialization parameters are valid. ******************************************************************************/ bool EMU_DCDCInit(const EMU_DCDCInit_TypeDef *dcdcInit) { uint32_t lpCmpBiasSelEM234H; #if defined(_EMU_PWRCFG_MASK) /* Set the external power configuration. This enables writing to the other DCDC registers. */ EMU->PWRCFG = EMU_PWRCFG_PWRCFG_DCDCTODVDD; /* EMU->PWRCFG is write-once and POR reset only. Check that the desired power configuration was set. */ if ((EMU->PWRCFG & _EMU_PWRCFG_PWRCFG_MASK) != EMU_PWRCFG_PWRCFG_DCDCTODVDD) { /* If this assert triggers unexpectedly, power cycle the kit to reset the power configuration. */ EFM_ASSERT(false); /* Return when assertions are disabled. */ return false; } #endif /* Load DCDC calibration data from the DI page. */ (void)dcdcConstCalibrationLoad(); /* Check current parameters */ EFM_ASSERT(dcdcInit->maxCurrent_mA <= 200U); EFM_ASSERT(dcdcInit->em01LoadCurrent_mA <= dcdcInit->maxCurrent_mA); EFM_ASSERT(dcdcInit->reverseCurrentControl <= 200); if (dcdcInit->dcdcMode == emuDcdcMode_LowNoise) { /* DCDC low-noise supports max 200 mA. */ EFM_ASSERT(dcdcInit->em01LoadCurrent_mA <= 200U); } #if (_SILICON_LABS_GECKO_INTERNAL_SDID != 80) else if (dcdcInit->dcdcMode == emuDcdcMode_LowPower) { /* Up to 10 mA is supported for EM01-LP mode. */ EFM_ASSERT(dcdcInit->em01LoadCurrent_mA <= 10U); } #endif else { /* No need to check the EM01 load limit. */ } /* EM2/3/4 current above 10 mA is not supported. */ EFM_ASSERT(dcdcInit->em234LoadCurrent_uA <= 10000U); if (dcdcInit->em234LoadCurrent_uA < 75U) { lpCmpBiasSelEM234H = 0; } else if (dcdcInit->em234LoadCurrent_uA < 500U) { lpCmpBiasSelEM234H = 1U << _GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT; } else if (dcdcInit->em234LoadCurrent_uA < 2500U) { lpCmpBiasSelEM234H = 2U << _GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT; } else { lpCmpBiasSelEM234H = 3U << _GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT; } /* ==== THESE NEXT STEPS ARE STRONGLY ORDER DEPENDENT ==== */ /* Set DCDC low-power mode comparator bias selection. */ /* 1. Set DCDC low-power mode comparator bias selection and forced CCM. => Updates DCDCMISCCTRL_LNFORCECCM */ EMU->DCDCMISCCTRL = (EMU->DCDCMISCCTRL & ~(_GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_MASK | _EMU_DCDCMISCCTRL_LNFORCECCM_MASK)) | ((uint32_t)lpCmpBiasSelEM234H | (dcdcInit->reverseCurrentControl >= 0 ? EMU_DCDCMISCCTRL_LNFORCECCM : 0U)); #if defined(_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK) /* Only 10 mA EM01-LP current is supported. */ EMU->DCDCLPEM01CFG = (EMU->DCDCLPEM01CFG & ~_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK) | EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3; #endif /* 2. Set recommended and validated current optimization settings. <= Depends on LNFORCECCM => Updates DCDCLNFREQCTRL_RCOBAND */ dcdcValidatedConfigSet(); /* 3. Updated static currents and limits user data. Limiters are updated in @ref EMU_DCDCOptimizeSlice(). */ userCurrentLimitsSet(dcdcInit->maxCurrent_mA, dcdcInit->reverseCurrentControl); dcdcEm01LoadCurrent_mA = dcdcInit->em01LoadCurrent_mA; /* 4. Optimize LN slice based on the given user input load current. <= Depends on DCDCMISCCTRL_LNFORCECCM and DCDCLNFREQCTRL_RCOBAND <= Depends on dcdcInit->maxCurrent_mA and dcdcInit->reverseCurrentControl => Updates DCDCMISCCTRL_P/NFETCNT => Updates DCDCMISCCTRL_LNCLIMILIMSEL and DCDCMISCCTRL_LPCLIMILIMSEL => Updates DCDCZDETCTRL_ZDETILIMSEL */ EMU_DCDCOptimizeSlice(dcdcInit->em01LoadCurrent_mA); /* ======================================================= */ /* Set DCDC low noise mode compensator control register. */ compCtrlSet(dcdcInit->dcdcLnCompCtrl); /* Set DCDC output voltage. */ if (!EMU_DCDCOutputVoltageSet(dcdcInit->mVout, true, true)) { EFM_ASSERT(false); /* Return when assertions are disabled. */ return false; } #if (_SILICON_LABS_GECKO_INTERNAL_SDID == 80) /* Select analog peripheral power supply. This must be done before DCDC mode is set for all EFM32xG1 and EFR32xG1 devices. */ BUS_RegBitWrite(&EMU->PWRCTRL, _EMU_PWRCTRL_ANASW_SHIFT, dcdcInit->anaPeripheralPower ? 1 : 0); #endif #if defined(_EMU_PWRCTRL_REGPWRSEL_MASK) /* Select DVDD as input to the digital regulator. The switch to DVDD will take effect once the DCDC output is stable. */ EMU->PWRCTRL |= EMU_PWRCTRL_REGPWRSEL_DVDD; #endif /* Set EM0 DCDC operating mode. Output voltage set in @ref EMU_DCDCOutputVoltageSet() above takes effect if mode is changed from bypass/off mode. */ EMU_DCDCModeSet(dcdcInit->dcdcMode); #if (_SILICON_LABS_GECKO_INTERNAL_SDID != 80) /* Select the analog peripheral power supply. This must be done after DCDC mode is set for all devices other than EFM32xG1 and EFR32xG1. */ BUS_RegBitWrite(&EMU->PWRCTRL, _EMU_PWRCTRL_ANASW_SHIFT, dcdcInit->anaPeripheralPower == emuDcdcAnaPeripheralPower_DCDC ? 1U : 0U); #endif return true; } /***************************************************************************//** * @brief * Set the DCDC output voltage. * * @param[in] mV * Target DCDC output voltage in mV. * * @return * True if the mV parameter is valid. ******************************************************************************/ bool EMU_DCDCOutputVoltageSet(uint32_t mV, bool setLpVoltage, bool setLnVoltage) { #if defined(_DEVINFO_DCDCLNVCTRL0_3V0LNATT1_MASK) #define DCDC_TRIM_MODES ((uint8_t)dcdcTrimMode_LN + 1) bool validOutVoltage; bool attenuationSet; uint32_t mVlow = 0; uint32_t mVhigh = 0; uint32_t mVdiff; uint32_t vrefVal[DCDC_TRIM_MODES] = { 0 }; uint32_t vrefLow[DCDC_TRIM_MODES] = { 0 }; uint32_t vrefHigh[DCDC_TRIM_MODES] = { 0 }; uint8_t lpcmpBias[DCDC_TRIM_MODES] = { 0 }; /* Check that the set voltage is within valid range. Voltages are obtained from the data sheet. */ validOutVoltage = (mV >= PWRCFG_DCDCTODVDD_VMIN) && (mV <= PWRCFG_DCDCTODVDD_VMAX); if (!validOutVoltage) { EFM_ASSERT(false); /* Return when assertions are disabled. */ return false; } /* Set attenuation to use and low/high range. */ attenuationSet = mV > 1800U; if (attenuationSet) { mVlow = 1800; mVhigh = 3000; mVdiff = mVhigh - mVlow; } else { mVlow = 1200; mVhigh = 1800; mVdiff = mVhigh - mVlow; } /* Get 2-point calibration data from DEVINFO. */ /* LN mode */ if (attenuationSet) { vrefLow[dcdcTrimMode_LN] = DEVINFO->DCDCLNVCTRL0; vrefHigh[dcdcTrimMode_LN] = (vrefLow[dcdcTrimMode_LN] & _DEVINFO_DCDCLNVCTRL0_3V0LNATT1_MASK) >> _DEVINFO_DCDCLNVCTRL0_3V0LNATT1_SHIFT; vrefLow[dcdcTrimMode_LN] = (vrefLow[dcdcTrimMode_LN] & _DEVINFO_DCDCLNVCTRL0_1V8LNATT1_MASK) >> _DEVINFO_DCDCLNVCTRL0_1V8LNATT1_SHIFT; } else { vrefLow[dcdcTrimMode_LN] = DEVINFO->DCDCLNVCTRL0; vrefHigh[dcdcTrimMode_LN] = (vrefLow[dcdcTrimMode_LN] & _DEVINFO_DCDCLNVCTRL0_1V8LNATT0_MASK) >> _DEVINFO_DCDCLNVCTRL0_1V8LNATT0_SHIFT; vrefLow[dcdcTrimMode_LN] = (vrefLow[dcdcTrimMode_LN] & _DEVINFO_DCDCLNVCTRL0_1V2LNATT0_MASK) >> _DEVINFO_DCDCLNVCTRL0_1V2LNATT0_SHIFT; } /* LP EM234H mode */ lpcmpBias[dcdcTrimMode_EM234H_LP] = (uint8_t) ((EMU->DCDCMISCCTRL & _GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_MASK) >> _GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT); lpGetDevinfoVrefLowHigh(&vrefLow[dcdcTrimMode_EM234H_LP], &vrefHigh[dcdcTrimMode_EM234H_LP], attenuationSet, lpcmpBias[dcdcTrimMode_EM234H_LP]); #if defined(_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK) /* LP EM01 mode */ lpcmpBias[dcdcTrimMode_EM01_LP] = (uint8_t) ((EMU->DCDCLPEM01CFG & _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK) >> _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_SHIFT); lpGetDevinfoVrefLowHigh(&vrefLow[dcdcTrimMode_EM01_LP], &vrefHigh[dcdcTrimMode_EM01_LP], attenuationSet, lpcmpBias[dcdcTrimMode_EM01_LP]); #endif /* Calculate output voltage trims. */ vrefVal[dcdcTrimMode_LN] = ((mV - mVlow) * (vrefHigh[dcdcTrimMode_LN] - vrefLow[dcdcTrimMode_LN])) / mVdiff; vrefVal[dcdcTrimMode_LN] += vrefLow[dcdcTrimMode_LN]; vrefVal[dcdcTrimMode_EM234H_LP] = ((mV - mVlow) * (vrefHigh[dcdcTrimMode_EM234H_LP] - vrefLow[dcdcTrimMode_EM234H_LP])) / mVdiff; vrefVal[dcdcTrimMode_EM234H_LP] += vrefLow[dcdcTrimMode_EM234H_LP]; #if defined(_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK) vrefVal[dcdcTrimMode_EM01_LP] = ((mV - mVlow) * (vrefHigh[dcdcTrimMode_EM01_LP] - vrefLow[dcdcTrimMode_EM01_LP])) / mVdiff; vrefVal[dcdcTrimMode_EM01_LP] += vrefLow[dcdcTrimMode_EM01_LP]; #endif /* Range checks */ if ((vrefVal[dcdcTrimMode_LN] > vrefHigh[dcdcTrimMode_LN]) || (vrefVal[dcdcTrimMode_LN] < vrefLow[dcdcTrimMode_LN]) #if defined(_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK) || (vrefVal[dcdcTrimMode_EM01_LP] > vrefHigh[dcdcTrimMode_EM01_LP]) || (vrefVal[dcdcTrimMode_EM01_LP] < vrefLow[dcdcTrimMode_EM01_LP]) #endif || (vrefVal[dcdcTrimMode_EM234H_LP] > vrefHigh[dcdcTrimMode_EM234H_LP]) || (vrefVal[dcdcTrimMode_EM234H_LP] < vrefLow[dcdcTrimMode_EM234H_LP])) { EFM_ASSERT(false); /* Return when assertions are disabled. */ return false; } /* Update output voltage tuning for LN and LP modes. */ if (setLnVoltage) { EMU->DCDCLNVCTRL = (EMU->DCDCLNVCTRL & ~(_EMU_DCDCLNVCTRL_LNVREF_MASK | _EMU_DCDCLNVCTRL_LNATT_MASK)) | (vrefVal[dcdcTrimMode_LN] << _EMU_DCDCLNVCTRL_LNVREF_SHIFT) | (attenuationSet ? EMU_DCDCLNVCTRL_LNATT : 0U); } if (setLpVoltage) { /* Load LP EM234H comparator hysteresis calibration. */ if (!(lpCmpHystCalibrationLoad(attenuationSet, lpcmpBias[dcdcTrimMode_EM234H_LP], dcdcTrimMode_EM234H_LP))) { EFM_ASSERT(false); /* Return when assertions are disabled. */ return false; } #if defined(_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK) /* Load LP EM234H comparator hysteresis calibration. */ if (!(lpCmpHystCalibrationLoad(attenuationSet, lpcmpBias[dcdcTrimMode_EM01_LP], dcdcTrimMode_EM01_LP))) { EFM_ASSERT(false); /* Return when assertions are disabled. */ return false; } /* LP VREF is that maximum of trims for EM01 and EM234H. */ vrefVal[dcdcTrimMode_EM234H_LP] = SL_MAX(vrefVal[dcdcTrimMode_EM234H_LP], vrefVal[dcdcTrimMode_EM01_LP]); #endif /* Don't exceed the maximum available code as specified in the reference manual for EMU_DCDCLPVCTRL. */ vrefVal[dcdcTrimMode_EM234H_LP] = SL_MIN(vrefVal[dcdcTrimMode_EM234H_LP], 0xE7U); EMU->DCDCLPVCTRL = (EMU->DCDCLPVCTRL & ~(_EMU_DCDCLPVCTRL_LPVREF_MASK | _EMU_DCDCLPVCTRL_LPATT_MASK)) | (vrefVal[dcdcTrimMode_EM234H_LP] << _EMU_DCDCLPVCTRL_LPVREF_SHIFT) | (attenuationSet ? EMU_DCDCLPVCTRL_LPATT : 0U); } #endif return true; } /***************************************************************************//** * @brief * Optimize the DCDC slice count based on the estimated average load current * in EM0. * * @param[in] em0LoadCurrent_mA * Estimated average EM0 load current in mA. ******************************************************************************/ void EMU_DCDCOptimizeSlice(uint32_t em0LoadCurrentmA) { uint32_t sliceCount = 0; uint32_t rcoBand = (EMU->DCDCLNFREQCTRL & _EMU_DCDCLNFREQCTRL_RCOBAND_MASK) >> _EMU_DCDCLNFREQCTRL_RCOBAND_SHIFT; /* Set the recommended slice count. */ if (((EMU->DCDCMISCCTRL & _EMU_DCDCMISCCTRL_LNFORCECCM_MASK) != 0U) && (rcoBand >= (uint32_t)emuDcdcLnRcoBand_5MHz)) { if (em0LoadCurrentmA < 20U) { sliceCount = 4; } else if ((em0LoadCurrentmA >= 20U) && (em0LoadCurrentmA < 40U)) { sliceCount = 8; } else { sliceCount = 16; } } else if (((EMU->DCDCMISCCTRL & _EMU_DCDCMISCCTRL_LNFORCECCM_MASK) == 0U) && (rcoBand <= (uint32_t)emuDcdcLnRcoBand_4MHz)) { if (em0LoadCurrentmA < 10U) { sliceCount = 4; } else if ((em0LoadCurrentmA >= 10U) && (em0LoadCurrentmA < 20U)) { sliceCount = 8; } else { sliceCount = 16; } } else if (((EMU->DCDCMISCCTRL & _EMU_DCDCMISCCTRL_LNFORCECCM_MASK) != 0U) && (rcoBand <= (uint32_t)emuDcdcLnRcoBand_4MHz)) { if (em0LoadCurrentmA < 40U) { sliceCount = 8; } else { sliceCount = 16; } } else { /* This configuration is not recommended. @ref EMU_DCDCInit() applies a recommended configuration. */ EFM_ASSERT(false); } /* The selected slices are PSLICESEL + 1. */ sliceCount--; /* Apply slice count to both N and P slice. */ sliceCount = (sliceCount << _EMU_DCDCMISCCTRL_PFETCNT_SHIFT | sliceCount << _EMU_DCDCMISCCTRL_NFETCNT_SHIFT); EMU->DCDCMISCCTRL = (EMU->DCDCMISCCTRL & ~(_EMU_DCDCMISCCTRL_PFETCNT_MASK | _EMU_DCDCMISCCTRL_NFETCNT_MASK)) | sliceCount; /* Update the current limiters. */ currentLimitersUpdate(); } /***************************************************************************//** * @brief * Set DCDC Low-noise RCO band. * * @param[in] band * RCO band to set. ******************************************************************************/ void EMU_DCDCLnRcoBandSet(EMU_DcdcLnRcoBand_TypeDef band) { uint32_t forcedCcm; forcedCcm = BUS_RegBitRead(&EMU->DCDCMISCCTRL, _EMU_DCDCMISCCTRL_LNFORCECCM_SHIFT); /* DCM mode supports up to 4 MHz LN RCO. */ EFM_ASSERT(((forcedCcm == 0U) && band <= emuDcdcLnRcoBand_4MHz) || (forcedCcm != 0U)); EMU->DCDCLNFREQCTRL = (EMU->DCDCLNFREQCTRL & ~_EMU_DCDCLNFREQCTRL_RCOBAND_MASK) | ((uint32_t)band << _EMU_DCDCLNFREQCTRL_RCOBAND_SHIFT); /* Update slice configuration as this depends on the RCO band. */ EMU_DCDCOptimizeSlice(dcdcEm01LoadCurrent_mA); } /***************************************************************************//** * @brief * Power off the DCDC regulator. * * @details * This function powers off the DCDC controller. This function should only be * used if the external power circuit is wired for no DCDC. If the external power * circuit is wired for DCDC usage, use @ref EMU_DCDCInit() and set the * DCDC in bypass mode to disable DCDC. * * @return * Return false if the DCDC could not be disabled. ******************************************************************************/ bool EMU_DCDCPowerOff(void) { bool dcdcModeSet; #if defined(_EMU_PWRCFG_MASK) /* Set DCDCTODVDD only to enable write access to EMU->DCDCCTRL. */ EMU->PWRCFG = EMU_PWRCFG_PWRCFG_DCDCTODVDD; #endif /* Select DVDD as input to the digital regulator. */ #if defined(EMU_PWRCTRL_IMMEDIATEPWRSWITCH) EMU->PWRCTRL |= EMU_PWRCTRL_REGPWRSEL_DVDD | EMU_PWRCTRL_IMMEDIATEPWRSWITCH; #elif defined(EMU_PWRCTRL_REGPWRSEL_DVDD) EMU->PWRCTRL |= EMU_PWRCTRL_REGPWRSEL_DVDD; #endif /* Set DCDC to OFF and disable LP in EM2/3/4. Verify that the required mode could be set. */ while ((EMU->DCDCSYNC & EMU_DCDCSYNC_DCDCCTRLBUSY) != 0U) { } EMU->DCDCCTRL = EMU_DCDCCTRL_DCDCMODE_OFF; dcdcModeSet = (EMU->DCDCCTRL == EMU_DCDCCTRL_DCDCMODE_OFF); EFM_ASSERT(dcdcModeSet); return dcdcModeSet; } #endif /** @endcond */ #if defined(EMU_STATUS_VMONRDY) /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ /***************************************************************************//** * @brief * Get the calibrated threshold value. * * @details * All VMON channels have two calibration fields in the DI page that * describes the threshold at 1.86 V and 2.98 V. This function will convert * the uncalibrated input voltage threshold in millivolts into a calibrated * threshold. * * @param[in] channel * A VMON channel. * * @param[in] threshold * A desired threshold in millivolts. * * @return * A calibrated threshold value to use. The first digit of the return value is placed * in the "fine" register fields while the next digits are placed in the * "coarse" register fields. ******************************************************************************/ static uint32_t vmonCalibratedThreshold(EMU_VmonChannel_TypeDef channel, int threshold) { uint32_t tLow = 0; uint32_t tHigh = 0; uint32_t calReg; /* Get calibration values for 1.86 V and 2.98 V */ switch (channel) { case emuVmonChannel_AVDD: calReg = DEVINFO->VMONCAL0; tLow = (10U * ((calReg & _DEVINFO_VMONCAL0_AVDD1V86THRESCOARSE_MASK) >> _DEVINFO_VMONCAL0_AVDD1V86THRESCOARSE_SHIFT)) + ((calReg & _DEVINFO_VMONCAL0_AVDD1V86THRESFINE_MASK) >> _DEVINFO_VMONCAL0_AVDD1V86THRESFINE_SHIFT); tHigh = (10U * ((calReg & _DEVINFO_VMONCAL0_AVDD2V98THRESCOARSE_MASK) >> _DEVINFO_VMONCAL0_AVDD2V98THRESCOARSE_SHIFT)) + ((calReg & _DEVINFO_VMONCAL0_AVDD2V98THRESFINE_MASK) >> _DEVINFO_VMONCAL0_AVDD2V98THRESFINE_SHIFT); break; case emuVmonChannel_ALTAVDD: calReg = DEVINFO->VMONCAL0; tLow = (10U * ((calReg & _DEVINFO_VMONCAL0_ALTAVDD1V86THRESCOARSE_MASK) >> _DEVINFO_VMONCAL0_ALTAVDD1V86THRESCOARSE_SHIFT)) + ((calReg & _DEVINFO_VMONCAL0_ALTAVDD1V86THRESFINE_MASK) >> _DEVINFO_VMONCAL0_ALTAVDD1V86THRESFINE_SHIFT); tHigh = (10U * ((calReg & _DEVINFO_VMONCAL0_ALTAVDD2V98THRESCOARSE_MASK) >> _DEVINFO_VMONCAL0_ALTAVDD2V98THRESCOARSE_SHIFT)) + ((calReg & _DEVINFO_VMONCAL0_ALTAVDD2V98THRESFINE_MASK) >> _DEVINFO_VMONCAL0_ALTAVDD2V98THRESFINE_SHIFT); break; case emuVmonChannel_DVDD: calReg = DEVINFO->VMONCAL1; tLow = (10U * ((calReg & _DEVINFO_VMONCAL1_DVDD1V86THRESCOARSE_MASK) >> _DEVINFO_VMONCAL1_DVDD1V86THRESCOARSE_SHIFT)) + ((calReg & _DEVINFO_VMONCAL1_DVDD1V86THRESFINE_MASK) >> _DEVINFO_VMONCAL1_DVDD1V86THRESFINE_SHIFT); tHigh = (10U * ((calReg & _DEVINFO_VMONCAL1_DVDD2V98THRESCOARSE_MASK) >> _DEVINFO_VMONCAL1_DVDD2V98THRESCOARSE_SHIFT)) + ((calReg & _DEVINFO_VMONCAL1_DVDD2V98THRESFINE_MASK) >> _DEVINFO_VMONCAL1_DVDD2V98THRESFINE_SHIFT); break; case emuVmonChannel_IOVDD0: calReg = DEVINFO->VMONCAL1; tLow = (10U * ((calReg & _DEVINFO_VMONCAL1_IO01V86THRESCOARSE_MASK) >> _DEVINFO_VMONCAL1_IO01V86THRESCOARSE_SHIFT)) + ((calReg & _DEVINFO_VMONCAL1_IO01V86THRESFINE_MASK) >> _DEVINFO_VMONCAL1_IO01V86THRESFINE_SHIFT); tHigh = (10U * ((calReg & _DEVINFO_VMONCAL1_IO02V98THRESCOARSE_MASK) >> _DEVINFO_VMONCAL1_IO02V98THRESCOARSE_SHIFT)) + ((calReg & _DEVINFO_VMONCAL1_IO02V98THRESFINE_MASK) >> _DEVINFO_VMONCAL1_IO02V98THRESFINE_SHIFT); break; #if defined(_EMU_VMONIO1CTRL_EN_MASK) case emuVmonChannel_IOVDD1: calReg = DEVINFO->VMONCAL2; tLow = (10U * ((calReg & _DEVINFO_VMONCAL2_IO11V86THRESCOARSE_MASK) >> _DEVINFO_VMONCAL2_IO11V86THRESCOARSE_SHIFT)) + ((calReg & _DEVINFO_VMONCAL2_IO11V86THRESFINE_MASK) >> _DEVINFO_VMONCAL2_IO11V86THRESFINE_SHIFT); tHigh = (10U * ((calReg & _DEVINFO_VMONCAL2_IO12V98THRESCOARSE_MASK) >> _DEVINFO_VMONCAL2_IO12V98THRESCOARSE_SHIFT)) + ((calReg & _DEVINFO_VMONCAL2_IO12V98THRESFINE_MASK) >> _DEVINFO_VMONCAL2_IO12V98THRESFINE_SHIFT); break; #endif #if defined(_EMU_VMONBUVDDCTRL_EN_MASK) case emuVmonChannel_BUVDD: calReg = DEVINFO->VMONCAL2; tLow = (10U * ((calReg & _DEVINFO_VMONCAL2_BUVDD1V86THRESCOARSE_MASK) >> _DEVINFO_VMONCAL2_BUVDD1V86THRESCOARSE_SHIFT)) + ((calReg & _DEVINFO_VMONCAL2_BUVDD1V86THRESFINE_MASK) >> _DEVINFO_VMONCAL2_BUVDD1V86THRESFINE_SHIFT); tHigh = (10U * ((calReg & _DEVINFO_VMONCAL2_BUVDD2V98THRESCOARSE_MASK) >> _DEVINFO_VMONCAL2_BUVDD2V98THRESCOARSE_SHIFT)) + ((calReg & _DEVINFO_VMONCAL2_BUVDD2V98THRESFINE_MASK) >> _DEVINFO_VMONCAL2_BUVDD2V98THRESFINE_SHIFT); break; #endif default: EFM_ASSERT(false); break; } if (tLow < tHigh) { /* Calculate threshold. * * Note that volt is used in the reference manual. However, the results * should be in millivolts. The precision of Va and Vb are increased in the * calculation instead of using floating points. */ uint32_t va = (1120U * 100U) / (tHigh - tLow); uint32_t vb = (1860U * 100U) - (va * tLow); // If (tHigh - tLow) is large, Va could be zero. Caught by CSTAT. if (va != 0) { /* Round the threshold to the nearest integer value. */ return (((uint32_t)threshold * 100U) - vb + (va / 2U)) / va; } } /* Uncalibrated device guard. */ return (uint32_t)threshold; } /** @endcond */ /***************************************************************************//** * @brief * Initialize a VMON channel. * * @details * Initialize a VMON channel without hysteresis. If the channel supports * separate rise and fall triggers, both thresholds will be set to the same * value. The threshold will be converted to a register field value based * on calibration values from the DI page. * * @param[in] vmonInit * The VMON initialization structure. ******************************************************************************/ void EMU_VmonInit(const EMU_VmonInit_TypeDef *vmonInit) { uint32_t thresholdCoarse, thresholdFine; uint32_t threshold; EFM_ASSERT((vmonInit->threshold >= 1620) && (vmonInit->threshold <= 3400)); threshold = vmonCalibratedThreshold(vmonInit->channel, vmonInit->threshold); thresholdFine = threshold % 10U; thresholdCoarse = threshold / 10U; /* Saturate the threshold to maximum values. */ if (thresholdCoarse > 0xFU) { thresholdCoarse = 0xF; thresholdFine = 9; } switch (vmonInit->channel) { case emuVmonChannel_AVDD: EMU->VMONAVDDCTRL = (thresholdCoarse << _EMU_VMONAVDDCTRL_RISETHRESCOARSE_SHIFT) | (thresholdFine << _EMU_VMONAVDDCTRL_RISETHRESFINE_SHIFT) | (thresholdCoarse << _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_SHIFT) | (thresholdFine << _EMU_VMONAVDDCTRL_FALLTHRESFINE_SHIFT) | (vmonInit->riseWakeup ? EMU_VMONAVDDCTRL_RISEWU : 0U) | (vmonInit->fallWakeup ? EMU_VMONAVDDCTRL_FALLWU : 0U) | (vmonInit->enable ? EMU_VMONAVDDCTRL_EN : 0U); break; case emuVmonChannel_ALTAVDD: EMU->VMONALTAVDDCTRL = (thresholdCoarse << _EMU_VMONALTAVDDCTRL_THRESCOARSE_SHIFT) | (thresholdFine << _EMU_VMONALTAVDDCTRL_THRESFINE_SHIFT) | (vmonInit->riseWakeup ? EMU_VMONALTAVDDCTRL_RISEWU : 0U) | (vmonInit->fallWakeup ? EMU_VMONALTAVDDCTRL_FALLWU : 0U) | (vmonInit->enable ? EMU_VMONALTAVDDCTRL_EN : 0U); break; case emuVmonChannel_DVDD: EMU->VMONDVDDCTRL = (thresholdCoarse << _EMU_VMONDVDDCTRL_THRESCOARSE_SHIFT) | (thresholdFine << _EMU_VMONDVDDCTRL_THRESFINE_SHIFT) | (vmonInit->riseWakeup ? EMU_VMONDVDDCTRL_RISEWU : 0U) | (vmonInit->fallWakeup ? EMU_VMONDVDDCTRL_FALLWU : 0U) | (vmonInit->enable ? EMU_VMONDVDDCTRL_EN : 0U); break; case emuVmonChannel_IOVDD0: EMU->VMONIO0CTRL = (thresholdCoarse << _EMU_VMONIO0CTRL_THRESCOARSE_SHIFT) | (thresholdFine << _EMU_VMONIO0CTRL_THRESFINE_SHIFT) | (vmonInit->retDisable ? EMU_VMONIO0CTRL_RETDIS : 0U) | (vmonInit->riseWakeup ? EMU_VMONIO0CTRL_RISEWU : 0U) | (vmonInit->fallWakeup ? EMU_VMONIO0CTRL_FALLWU : 0U) | (vmonInit->enable ? EMU_VMONIO0CTRL_EN : 0U); break; #if defined(_EMU_VMONIO1CTRL_EN_MASK) case emuVmonChannel_IOVDD1: EMU->VMONIO1CTRL = (thresholdCoarse << _EMU_VMONIO1CTRL_THRESCOARSE_SHIFT) | (thresholdFine << _EMU_VMONIO1CTRL_THRESFINE_SHIFT) | (vmonInit->retDisable ? EMU_VMONIO1CTRL_RETDIS : 0U) | (vmonInit->riseWakeup ? EMU_VMONIO1CTRL_RISEWU : 0U) | (vmonInit->fallWakeup ? EMU_VMONIO1CTRL_FALLWU : 0U) | (vmonInit->enable ? EMU_VMONIO1CTRL_EN : 0U); break; #endif #if defined(_EMU_VMONBUVDDCTRL_EN_MASK) case emuVmonChannel_BUVDD: EMU->VMONBUVDDCTRL = (thresholdCoarse << _EMU_VMONBUVDDCTRL_THRESCOARSE_SHIFT) | (thresholdFine << _EMU_VMONBUVDDCTRL_THRESFINE_SHIFT) | (vmonInit->riseWakeup ? EMU_VMONBUVDDCTRL_RISEWU : 0U) | (vmonInit->fallWakeup ? EMU_VMONBUVDDCTRL_FALLWU : 0U) | (vmonInit->enable ? EMU_VMONBUVDDCTRL_EN : 0U); break; #endif default: EFM_ASSERT(false); return; } } /***************************************************************************//** * @brief * Initialize a VMON channel with hysteresis (separate rise and fall triggers). * * @details * Initialize a VMON channel which supports hysteresis. The AVDD channel is * the only channel to support separate rise and fall triggers. The rise and * fall thresholds will be converted to a register field value based on the * calibration values from the DI page. * * @param[in] vmonInit * The VMON hysteresis initialization structure. ******************************************************************************/ void EMU_VmonHystInit(const EMU_VmonHystInit_TypeDef *vmonInit) { uint32_t riseThreshold; uint32_t fallThreshold; /* VMON supports voltages between 1620 mV and 3400 mV (inclusive). */ EFM_ASSERT((vmonInit->riseThreshold >= 1620) && (vmonInit->riseThreshold <= 3400)); EFM_ASSERT((vmonInit->fallThreshold >= 1620) && (vmonInit->fallThreshold <= 3400)); /* The fall threshold has to be lower than rise threshold. */ EFM_ASSERT(vmonInit->fallThreshold <= vmonInit->riseThreshold); riseThreshold = vmonCalibratedThreshold(vmonInit->channel, vmonInit->riseThreshold); fallThreshold = vmonCalibratedThreshold(vmonInit->channel, vmonInit->fallThreshold); switch (vmonInit->channel) { case emuVmonChannel_AVDD: EMU->VMONAVDDCTRL = ((riseThreshold / 10U) << _EMU_VMONAVDDCTRL_RISETHRESCOARSE_SHIFT) | ((riseThreshold % 10U) << _EMU_VMONAVDDCTRL_RISETHRESFINE_SHIFT) | ((fallThreshold / 10U) << _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_SHIFT) | ((fallThreshold % 10U) << _EMU_VMONAVDDCTRL_FALLTHRESFINE_SHIFT) | (vmonInit->riseWakeup ? EMU_VMONAVDDCTRL_RISEWU : 0U) | (vmonInit->fallWakeup ? EMU_VMONAVDDCTRL_FALLWU : 0U) | (vmonInit->enable ? EMU_VMONAVDDCTRL_EN : 0U); break; default: EFM_ASSERT(false); return; } } /***************************************************************************//** * @brief * Enable or disable a VMON channel. * * @param[in] channel * A VMON channel to enable/disable. * * @param[in] enable * Indicates whether to enable or disable. ******************************************************************************/ void EMU_VmonEnable(EMU_VmonChannel_TypeDef channel, bool enable) { uint32_t volatile * reg; uint32_t bit; switch (channel) { case emuVmonChannel_AVDD: reg = &(EMU->VMONAVDDCTRL); bit = _EMU_VMONAVDDCTRL_EN_SHIFT; break; case emuVmonChannel_ALTAVDD: reg = &(EMU->VMONALTAVDDCTRL); bit = _EMU_VMONALTAVDDCTRL_EN_SHIFT; break; case emuVmonChannel_DVDD: reg = &(EMU->VMONDVDDCTRL); bit = _EMU_VMONDVDDCTRL_EN_SHIFT; break; case emuVmonChannel_IOVDD0: reg = &(EMU->VMONIO0CTRL); bit = _EMU_VMONIO0CTRL_EN_SHIFT; break; #if defined(_EMU_VMONIO1CTRL_EN_MASK) case emuVmonChannel_IOVDD1: reg = &(EMU->VMONIO1CTRL); bit = _EMU_VMONIO1CTRL_EN_SHIFT; break; #endif #if defined(_EMU_VMONBUVDDCTRL_EN_MASK) case emuVmonChannel_BUVDD: reg = &(EMU->VMONBUVDDCTRL); bit = _EMU_VMONBUVDDCTRL_EN_SHIFT; break; #endif default: EFM_ASSERT(false); return; } BUS_RegBitWrite(reg, bit, (uint32_t)enable); } /***************************************************************************//** * @brief * Get the status of a voltage monitor channel. * * @param[in] channel * A VMON channel to get the status for. * * @return * A status of the selected VMON channel. True if the channel is triggered. ******************************************************************************/ bool EMU_VmonChannelStatusGet(EMU_VmonChannel_TypeDef channel) { uint32_t bit; switch (channel) { case emuVmonChannel_AVDD: bit = _EMU_STATUS_VMONAVDD_SHIFT; break; case emuVmonChannel_ALTAVDD: bit = _EMU_STATUS_VMONALTAVDD_SHIFT; break; case emuVmonChannel_DVDD: bit = _EMU_STATUS_VMONDVDD_SHIFT; break; case emuVmonChannel_IOVDD0: bit = _EMU_STATUS_VMONIO0_SHIFT; break; #if defined(_EMU_VMONIO1CTRL_EN_MASK) case emuVmonChannel_IOVDD1: bit = _EMU_STATUS_VMONIO1_SHIFT; break; #endif #if defined(_EMU_VMONBUVDDCTRL_EN_MASK) case emuVmonChannel_BUVDD: bit = _EMU_STATUS_VMONBUVDD_SHIFT; break; #endif default: bit = 0; EFM_ASSERT(false); break; } return BUS_RegBitRead(&EMU->STATUS, bit) != 0U; } #endif /* EMU_STATUS_VMONRDY */ #if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) /***************************************************************************//** * @brief * Adjust the bias refresh rate. * * @details * This function is only meant to be used under high-temperature operation on * EFR32xG1 and EFM32xG1 devices. Adjusting the bias mode will * increase the typical current consumption. See application note 1027 * and errata documents for more details. * * @param [in] mode * The new bias refresh rate. ******************************************************************************/ void EMU_SetBiasMode(EMU_BiasMode_TypeDef mode) { #define EMU_TESTLOCK (*(volatile uint32_t *) (EMU_BASE + 0x190)) #define EMU_BIASCONF (*(volatile uint32_t *) (EMU_BASE + 0x164)) #define EMU_BIASTESTCTRL (*(volatile uint32_t *) (EMU_BASE + 0x19C)) #define CMU_ULFRCOCTRL (*(volatile uint32_t *) (CMU_BASE + 0x03C)) uint32_t freq = 0x2u; bool emuTestLocked = false; if (mode == emuBiasMode_1KHz) { freq = 0x0u; } if (EMU_TESTLOCK == 0x1u) { emuTestLocked = true; EMU_TESTLOCK = 0xADE8u; } if (mode == emuBiasMode_Continuous) { EMU_BIASCONF &= ~0x74u; } else { EMU_BIASCONF |= 0x74u; } EMU_BIASTESTCTRL |= 0x8u; CMU_ULFRCOCTRL = (CMU_ULFRCOCTRL & ~0xC00u) | ((freq & 0x3u) << 10u); EMU_BIASTESTCTRL &= ~0x8u; if (emuTestLocked) { EMU_TESTLOCK = 0u; } } #endif /** @} (end addtogroup EMU) */ /** @} (end addtogroup emlib) */ #endif /* __EM_EMU_H */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/emlib/src/em_gpio.c.
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/***************************************************************************//** * @file * @brief General Purpose IO (GPIO) peripheral API * devices. * @version 5.7.0 ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * SPDX-License-Identifier: Zlib * * The licensor of this software is Silicon Laboratories Inc. * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be * appreciated but is not required. * 2. Altered source versions must be plainly marked as such, and must not be * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * ******************************************************************************/ #include "em_gpio.h" #if defined(GPIO_COUNT) && (GPIO_COUNT > 0) /***************************************************************************//** * @addtogroup emlib * @{ ******************************************************************************/ /***************************************************************************//** * @addtogroup GPIO * @brief General Purpose Input/Output (GPIO) API * @details * This module contains functions to control the GPIO peripheral of Silicon * Labs 32-bit MCUs and SoCs. The GPIO peripheral is used for pin configuration * and direct pin manipulation and sensing as well as routing for peripheral * pin connections. * @{ ******************************************************************************/ /******************************************************************************* ******************************* DEFINES *********************************** ******************************************************************************/ /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ /** Validation of the pin typically usable in assert statements. */ #define GPIO_DRIVEMODE_VALID(mode) ((mode) <= 3) #define GPIO_STRENGTH_VALID(strength) (!((strength) \ & ~(_GPIO_P_CTRL_DRIVESTRENGTH_MASK \ | _GPIO_P_CTRL_DRIVESTRENGTHALT_MASK))) /** @endcond */ /******************************************************************************* ************************** GLOBAL FUNCTIONS ******************************* ******************************************************************************/ /***************************************************************************//** * @brief * Sets the pin location of the debug pins (Serial Wire interface). * * @note * Changing the pins used for debugging uncontrolled, may result in a lockout. * * @param[in] location * The debug pin location to use (0-3). ******************************************************************************/ void GPIO_DbgLocationSet(unsigned int location) { #if defined (_GPIO_ROUTE_SWLOCATION_MASK) EFM_ASSERT(location < AFCHANLOC_MAX); GPIO->ROUTE = (GPIO->ROUTE & ~_GPIO_ROUTE_SWLOCATION_MASK) | (location << _GPIO_ROUTE_SWLOCATION_SHIFT); #elif defined (_GPIO_ROUTELOC0_SWVLOC_MASK) EFM_ASSERT(location < AFCHANLOC_MAX); GPIO->ROUTELOC0 = (GPIO->ROUTELOC0 & ~_GPIO_ROUTELOC0_SWVLOC_MASK) | (location << _GPIO_ROUTELOC0_SWVLOC_SHIFT); #else (void)location; #endif } #if defined (_GPIO_P_CTRL_DRIVEMODE_MASK) /***************************************************************************//** * @brief * Sets drive mode for a GPIO port. * * @param[in] port * The GPIO port to access. * * @param[in] mode * Drive mode to use for the port. ******************************************************************************/ void GPIO_DriveModeSet(GPIO_Port_TypeDef port, GPIO_DriveMode_TypeDef mode) { EFM_ASSERT(GPIO_PORT_VALID(port) && GPIO_DRIVEMODE_VALID(mode)); GPIO->P[port].CTRL = (GPIO->P[port].CTRL & ~(_GPIO_P_CTRL_DRIVEMODE_MASK)) | (mode << _GPIO_P_CTRL_DRIVEMODE_SHIFT); } #endif #if defined (_GPIO_P_CTRL_DRIVESTRENGTH_MASK) /***************************************************************************//** * @brief * Sets the drive strength for a GPIO port. * * @param[in] port * The GPIO port to access. * * @param[in] strength * The drive strength to use for the port. ******************************************************************************/ void GPIO_DriveStrengthSet(GPIO_Port_TypeDef port, GPIO_DriveStrength_TypeDef strength) { EFM_ASSERT(GPIO_PORT_VALID(port) && GPIO_STRENGTH_VALID(strength)); BUS_RegMaskedWrite(&GPIO->P[port].CTRL, _GPIO_P_CTRL_DRIVESTRENGTH_MASK | _GPIO_P_CTRL_DRIVESTRENGTHALT_MASK, strength); } #endif /***************************************************************************//** * @brief * Configure the GPIO external pin interrupt. * * @details * It is recommended to disable interrupts before configuring the GPIO pin interrupt. * See @ref GPIO_IntDisable() for more information. * * The GPIO interrupt handler must be in place before enabling the * interrupt. * * Notice that any pending interrupt for the selected interrupt is cleared * by this function. * * @note * On series 0 devices, the pin number parameter is not used. The * pin number used on these devices is hardwired to the interrupt with the * same number. @n * On series 1 devices, the pin number can be selected freely within a group. * Interrupt numbers are divided into 4 groups (intNo / 4) and valid pin * number within the interrupt groups are: * 0: pins 0-3 (interrupt number 0-3) * 1: pins 4-7 (interrupt number 4-7) * 2: pins 8-11 (interrupt number 8-11) * 3: pins 12-15 (interrupt number 12-15) * * @param[in] port * The port to associate with the @p pin. * * @param[in] pin * The pin number on the port. * * @param[in] intNo * The interrupt number to trigger. * * @param[in] risingEdge * Set to true if the interrupt will be enabled on the rising edge. Otherwise, false. * * @param[in] fallingEdge * Set to true if the interrupt will be enabled on the falling edge. Otherwise, false. * * @param[in] enable * Set to true if the interrupt will be enabled after the configuration is complete. * False to leave disabled. See @ref GPIO_IntDisable() and @ref GPIO_IntEnable(). ******************************************************************************/ void GPIO_ExtIntConfig(GPIO_Port_TypeDef port, unsigned int pin, unsigned int intNo, bool risingEdge, bool fallingEdge, bool enable) { #if defined (_GPIO_EXTIPSELH_MASK) uint32_t tmp = 0; #endif #if !defined(_GPIO_EXTIPINSELL_MASK) (void)pin; #endif EFM_ASSERT(GPIO_PORT_PIN_VALID(port, pin)); #if defined(_GPIO_EXTIPINSELL_MASK) EFM_ASSERT(GPIO_INTNO_PIN_VALID(intNo, pin)); #endif /* The EXTIPSELL register controls pins 0-7 and EXTIPSELH controls * pins 8-15 of the interrupt configuration. */ if (intNo < 8) { BUS_RegMaskedWrite(&GPIO->EXTIPSELL, _GPIO_EXTIPSELL_EXTIPSEL0_MASK << (_GPIO_EXTIPSELL_EXTIPSEL1_SHIFT * intNo), port << (_GPIO_EXTIPSELL_EXTIPSEL1_SHIFT * intNo)); } else { #if defined(_GPIO_EXTIPSELH_MASK) && !defined(_SILICON_LABS_32B_SERIES_2) tmp = intNo - 8; BUS_RegMaskedWrite(&GPIO->EXTIPSELH, _GPIO_EXTIPSELH_EXTIPSEL8_MASK << (_GPIO_EXTIPSELH_EXTIPSEL9_SHIFT * tmp), port << (_GPIO_EXTIPSELH_EXTIPSEL9_SHIFT * tmp)); #endif } #if defined(_GPIO_EXTIPINSELL_MASK) /* The EXTIPINSELL register controls interrupt 0-7 and EXTIPINSELH controls * interrupt 8-15 of the interrupt/pin number mapping. */ if (intNo < 8) { BUS_RegMaskedWrite(&GPIO->EXTIPINSELL, _GPIO_EXTIPINSELL_EXTIPINSEL0_MASK << (_GPIO_EXTIPINSELL_EXTIPINSEL1_SHIFT * intNo), ((pin % 4) & _GPIO_EXTIPINSELL_EXTIPINSEL0_MASK) << (_GPIO_EXTIPINSELL_EXTIPINSEL1_SHIFT * intNo)); } else { #if defined (_GPIO_EXTIPINSELH_MASK) && !defined(_SILICON_LABS_32B_SERIES_2) BUS_RegMaskedWrite(&GPIO->EXTIPINSELH, _GPIO_EXTIPINSELH_EXTIPINSEL8_MASK << (_GPIO_EXTIPINSELH_EXTIPINSEL9_SHIFT * tmp), ((pin % 4) & _GPIO_EXTIPINSELH_EXTIPINSEL8_MASK) << (_GPIO_EXTIPSELH_EXTIPSEL9_SHIFT * tmp)); #endif } #endif /* Enable/disable the rising edge interrupt. */ BUS_RegBitWrite(&(GPIO->EXTIRISE), intNo, risingEdge); /* Enable/disable the falling edge interrupt. */ BUS_RegBitWrite(&(GPIO->EXTIFALL), intNo, fallingEdge); /* Clear any pending interrupt. */ GPIO_IntClear(1 << intNo); /* Finally enable/disable interrupt. */ BUS_RegBitWrite(&(GPIO->IEN), intNo, enable); } /***************************************************************************//** * @brief * Set the mode for a GPIO pin. * * @param[in] port * The GPIO port to access. * * @param[in] pin * The pin number in the port. * * @param[in] mode * The desired pin mode. * * @param[in] out * A value to set for the pin in the DOUT register. The DOUT setting is important for * some input mode configurations to determine the pull-up/down direction. ******************************************************************************/ void GPIO_PinModeSet(GPIO_Port_TypeDef port, unsigned int pin, GPIO_Mode_TypeDef mode, unsigned int out) { EFM_ASSERT(GPIO_PORT_PIN_VALID(port, pin)); /* If disabling a pin, do not modify DOUT to reduce the chance of */ /* a glitch/spike (may not be sufficient precaution in all use cases). */ if (mode != gpioModeDisabled) { if (out) { GPIO_PinOutSet(port, pin); } else { GPIO_PinOutClear(port, pin); } } /* There are two registers controlling the pins for each port. The MODEL * register controls pins 0-7 and MODEH controls pins 8-15. */ if (pin < 8) { GPIO->P[port].MODEL = (GPIO->P[port].MODEL & ~(0xFu << (pin * 4))) | (mode << (pin * 4)); } else { GPIO->P[port].MODEH = (GPIO->P[port].MODEH & ~(0xFu << ((pin - 8) * 4))) | (mode << ((pin - 8) * 4)); } if (mode == gpioModeDisabled) { if (out) { GPIO_PinOutSet(port, pin); } else { GPIO_PinOutClear(port, pin); } } } /***************************************************************************//** * @brief * Get the mode for a GPIO pin. * * @param[in] port * The GPIO port to access. * * @param[in] pin * The pin number in the port. * * @return * The pin mode. ******************************************************************************/ GPIO_Mode_TypeDef GPIO_PinModeGet(GPIO_Port_TypeDef port, unsigned int pin) { EFM_ASSERT(GPIO_PORT_PIN_VALID(port, pin)); if (pin < 8) { return (GPIO_Mode_TypeDef) ((GPIO->P[port].MODEL >> (pin * 4)) & 0xF); } else { return (GPIO_Mode_TypeDef) ((GPIO->P[port].MODEH >> ((pin - 8) * 4)) & 0xF); } } #if defined(_GPIO_EM4WUEN_MASK) /**************************************************************************//** * @brief * Enable GPIO pin wake-up from EM4. When the function exits, * EM4 mode can be safely entered. * * @note * It is assumed that the GPIO pin modes are set correctly. * Valid modes are @ref gpioModeInput and @ref gpioModeInputPull. * * @param[in] pinmask * A bitmask containing the bitwise logic OR of which GPIO pin(s) to enable. * See Reference Manuals for a pinmask to the GPIO port/pin mapping. * @param[in] polaritymask * A bitmask containing the bitwise logic OR of GPIO pin(s) wake-up polarity. * See Reference Manuals for pinmask-to-GPIO port/pin mapping. *****************************************************************************/ void GPIO_EM4EnablePinWakeup(uint32_t pinmask, uint32_t polaritymask) { EFM_ASSERT((pinmask & ~_GPIO_EM4WUEN_MASK) == 0); #if defined(_GPIO_EM4WUPOL_MASK) EFM_ASSERT((polaritymask & ~_GPIO_EM4WUPOL_MASK) == 0); GPIO->EM4WUPOL &= ~pinmask; /* Set the wakeup polarity. */ GPIO->EM4WUPOL |= pinmask & polaritymask; #elif defined(_GPIO_EXTILEVEL_MASK) EFM_ASSERT((polaritymask & ~_GPIO_EXTILEVEL_MASK) == 0); GPIO->EXTILEVEL &= ~pinmask; GPIO->EXTILEVEL |= pinmask & polaritymask; #endif GPIO->EM4WUEN |= pinmask; /* Enable wakeup. */ GPIO_EM4SetPinRetention(true); /* Enable the pin retention. */ #if defined(_GPIO_CMD_EM4WUCLR_MASK) GPIO->CMD = GPIO_CMD_EM4WUCLR; /* Clear the wake-up logic. */ #elif defined(_GPIO_IF_EM4WU_MASK) GPIO_IntClear(pinmask); #endif } #endif /** @} (end addtogroup GPIO) */ /** @} (end addtogroup emlib) */ #endif /* defined(GPIO_COUNT) && (GPIO_COUNT > 0) */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/emlib/src/em_i2c.c.
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/***************************************************************************//** * @file * @brief Inter-integrated Circuit (I2C) Peripheral API * @version 5.7.0 ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * SPDX-License-Identifier: Zlib * * The licensor of this software is Silicon Laboratories Inc. * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be * appreciated but is not required. * 2. Altered source versions must be plainly marked as such, and must not be * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * ******************************************************************************/ #include "em_i2c.h" #if defined(I2C_COUNT) && (I2C_COUNT > 0) #include "em_cmu.h" #include "em_bus.h" #include "em_assert.h" #include <limits.h> /***************************************************************************//** * @addtogroup emlib * @{ ******************************************************************************/ /***************************************************************************//** * @addtogroup I2C * @brief Inter-integrated Circuit (I2C) Peripheral API * @details * This module contains functions to control the I2C peripheral of Silicon * Labs 32-bit MCUs and SoCs. The I2C interface allows communication on I2C * buses with the lowest energy consumption possible. * @{ ******************************************************************************/ /******************************************************************************* ******************************* DEFINES *********************************** ******************************************************************************/ /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ /** Validation of the I2C register block pointer reference for assert statements. */ #if (I2C_COUNT == 1) #define I2C_REF_VALID(ref) ((ref) == I2C0) #elif (I2C_COUNT == 2) #define I2C_REF_VALID(ref) (((ref) == I2C0) || ((ref) == I2C1)) #elif (I2C_COUNT == 3) #define I2C_REF_VALID(ref) (((ref) == I2C0) || ((ref) == I2C1) || ((ref) == I2C2)) #endif /** Error flags indicating that the I2C transfer has failed. */ /* Notice that I2C_IF_TXOF (transmit overflow) is not really possible with */ /* the software-supporting master mode. Likewise, for I2C_IF_RXUF (receive underflow) */ /* RXUF is only likely to occur with the software if using a debugger peeking into */ /* the RXDATA register. Therefore, those types of faults are ignored. */ #define I2C_IF_ERRORS (I2C_IF_BUSERR | I2C_IF_ARBLOST) #define I2C_IEN_ERRORS (I2C_IEN_BUSERR | I2C_IEN_ARBLOST) /* Maximum I2C transmission rate constant. */ #if defined(_SILICON_LABS_32B_SERIES_0) #define I2C_CR_MAX 4 #elif defined(_SILICON_LABS_32B_SERIES_1) #define I2C_CR_MAX 8 #elif defined(_SILICON_LABS_32B_SERIES_2) #define I2C_CR_MAX 8 #else #warning "Max I2C transmission rate constant is not defined" #endif /** @endcond */ /******************************************************************************* ******************************** ENUMS ************************************ ******************************************************************************/ /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ /** Master mode transfer states. */ typedef enum { i2cStateStartAddrSend, /**< Send start + (first part of) address. */ i2cStateAddrWFAckNack, /**< Wait for ACK/NACK on (the first part of) address. */ i2cStateAddrWF2ndAckNack, /**< Wait for ACK/NACK on the second part of a 10 bit address. */ i2cStateRStartAddrSend, /**< Send a repeated start + (first part of) address. */ i2cStateRAddrWFAckNack, /**< Wait for ACK/NACK on an address sent after a repeated start. */ i2cStateDataSend, /**< Send data. */ i2cStateDataWFAckNack, /**< Wait for ACK/NACK on data sent. */ i2cStateWFData, /**< Wait for data. */ i2cStateWFStopSent, /**< Wait for STOP to have been transmitted. */ i2cStateDone /**< Transfer completed successfully. */ } I2C_TransferState_TypeDef; /** @endcond */ /******************************************************************************* ******************************* STRUCTS *********************************** ******************************************************************************/ /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ /** Structure used to store state information on an ongoing master mode transfer. */ typedef struct { /** Current state. */ I2C_TransferState_TypeDef state; /** Result return code. */ I2C_TransferReturn_TypeDef result; /** Offset in the current sequence buffer. */ uint16_t offset; /* Index to the current sequence buffer in use. */ uint8_t bufIndx; /** Reference to the I2C transfer sequence definition provided by the user. */ I2C_TransferSeq_TypeDef *seq; } I2C_Transfer_TypeDef; /** @endcond */ /******************************************************************************* ***************************** LOCAL DATA *******^************************** ******************************************************************************/ /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ /** * Lookup table for Nlow + Nhigh setting defined by CLHR. Set the undefined * index (0x3) to reflect a default setting just in case. */ static const uint8_t i2cNSum[] = { 4 + 4, 6 + 3, 11 + 6, 4 + 4 }; /** A transfer state information for an ongoing master mode transfer. */ static I2C_Transfer_TypeDef i2cTransfer[I2C_COUNT]; /** @endcond */ /******************************************************************************* ************************** LOCAL FUNCTIONS ******************************* ******************************************************************************/ /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ /***************************************************************************//** * @brief * Empty received data buffer. ******************************************************************************/ static void flushRx(I2C_TypeDef *i2c) { while (i2c->STATUS & I2C_STATUS_RXDATAV) { i2c->RXDATA; } #if defined(_SILICON_LABS_32B_SERIES_2) /* SW needs to clear RXDATAV IF on Series 2 devices. Flag is kept high by HW if buffer is not empty. */ I2C_IntClear(i2c, I2C_IF_RXDATAV); #endif } /** @endcond */ /******************************************************************************* ************************** GLOBAL FUNCTIONS ******************************* ******************************************************************************/ /***************************************************************************//** * @brief * Get the current configured I2C bus frequency. * * @details * This frequency is only relevant when acting as master. * * @note * The actual frequency is a real number, this function returns a rounded * down (truncated) integer value. * * @param[in] i2c * A pointer to the I2C peripheral register block. * * @return * The current I2C frequency in Hz. ******************************************************************************/ uint32_t I2C_BusFreqGet(I2C_TypeDef *i2c) { uint32_t freqHfper = 0; uint32_t n; /* Maximum frequency is given by freqScl = freqHfper/((Nlow + Nhigh)(DIV + 1) + I2C_CR_MAX) * For more details, see the reference manual * I2C Clock Generation chapter. */ if (i2c == I2C0) { freqHfper = CMU_ClockFreqGet(cmuClock_I2C0); #if defined(I2C1) } else if (i2c == I2C1) { freqHfper = CMU_ClockFreqGet(cmuClock_I2C1); #endif #if defined(I2C2) } else if (i2c == I2C2) { freqHfper = CMU_ClockFreqGet(cmuClock_I2C2); #endif } else { EFM_ASSERT(false); } /* n = Nlow + Nhigh */ n = (uint32_t)i2cNSum[(i2c->CTRL & _I2C_CTRL_CLHR_MASK) >> _I2C_CTRL_CLHR_SHIFT]; return freqHfper / ((n * (i2c->CLKDIV + 1)) + I2C_CR_MAX); } /***************************************************************************//** * @brief * Set the I2C bus frequency. * * @details * The bus frequency is only relevant when acting as master. The bus * frequency should not be set higher than the maximum frequency accepted by the * slowest device on the bus. * * Notice that, due to asymmetric requirements on low and high I2C clock * cycles in the I2C specification, the maximum frequency allowed * to comply with the specification may be somewhat lower than expected. * * See the reference manual, details on I2C clock generation, * for maximum allowed theoretical frequencies for different modes. * * @param[in] i2c * A pointer to the I2C peripheral register block. * * @param[in] freqRef * An I2C reference clock frequency in Hz that will be used. If set to 0, * HFPERCLK / HFPERCCLK clock is used. Setting it to a higher than actual * configured value has the consequence of reducing the real I2C frequency. * * @param[in] freqScl * A bus frequency to set (bus speed may be lower due to integer * prescaling). Safe (according to the I2C specification) maximum frequencies for * standard fast and fast+ modes are available using I2C_FREQ_ defines. * (Using I2C_FREQ_ defines requires corresponding setting of @p type.) * The slowest slave device on a bus must always be considered. * * @param[in] i2cMode * A clock low-to-high ratio type to use. If not using i2cClockHLRStandard, * make sure all devices on the bus support the specified mode. Using a * non-standard ratio is useful to achieve a higher bus clock in fast and * fast+ modes. ******************************************************************************/ void I2C_BusFreqSet(I2C_TypeDef *i2c, uint32_t freqRef, uint32_t freqScl, I2C_ClockHLR_TypeDef i2cMode) { uint32_t n, minFreq, denominator; int32_t div; /* Avoid dividing by 0. */ EFM_ASSERT(freqScl); if (!freqScl) { return; } /* Ensure mode is valid */ i2cMode &= _I2C_CTRL_CLHR_MASK >> _I2C_CTRL_CLHR_SHIFT; /* Set the CLHR (clock low-to-high ratio). */ i2c->CTRL &= ~_I2C_CTRL_CLHR_MASK; BUS_RegMaskedWrite(&i2c->CTRL, _I2C_CTRL_CLHR_MASK, i2cMode << _I2C_CTRL_CLHR_SHIFT); if (freqRef == 0) { if (i2c == I2C0) { freqRef = CMU_ClockFreqGet(cmuClock_I2C0); #if defined(I2C1) } else if (i2c == I2C1) { freqRef = CMU_ClockFreqGet(cmuClock_I2C1); #endif #if defined(I2C2) } else if (i2c == I2C2) { freqRef = CMU_ClockFreqGet(cmuClock_I2C2); #endif } else { EFM_ASSERT(false); } } /* Check the minumum HF peripheral clock. */ minFreq = UINT_MAX; if (i2c->CTRL & I2C_CTRL_SLAVE) { switch (i2cMode) { case i2cClockHLRStandard: #if defined(_SILICON_LABS_32B_SERIES_0) minFreq = 4200000; break; #elif defined(_SILICON_LABS_32B_SERIES_1) minFreq = 2000000; break; #elif defined(_SILICON_LABS_32B_SERIES_2) minFreq = 2000000; break; #endif case i2cClockHLRAsymetric: #if defined(_SILICON_LABS_32B_SERIES_0) minFreq = 11000000; break; #elif defined(_SILICON_LABS_32B_SERIES_1) minFreq = 5000000; break; #elif defined(_SILICON_LABS_32B_SERIES_2) minFreq = 5000000; break; #endif case i2cClockHLRFast: #if defined(_SILICON_LABS_32B_SERIES_0) minFreq = 24400000; break; #elif defined(_SILICON_LABS_32B_SERIES_1) minFreq = 14000000; break; #elif defined(_SILICON_LABS_32B_SERIES_2) minFreq = 14000000; break; #endif default: /* MISRA requires the default case. */ break; } } else { /* For master mode, platform 1 and 2 share the same minimum frequencies. */ switch (i2cMode) { case i2cClockHLRStandard: minFreq = 2000000; break; case i2cClockHLRAsymetric: minFreq = 9000000; break; case i2cClockHLRFast: minFreq = 20000000; break; default: /* MISRA requires default case */ break; } } /* Frequency most be larger-than. */ EFM_ASSERT(freqRef > minFreq); /* SCL frequency is given by: * freqScl = freqRef/((Nlow + Nhigh) * (DIV + 1) + I2C_CR_MAX) * * Therefore, * DIV = ((freqRef - (I2C_CR_MAX * freqScl))/((Nlow + Nhigh) * freqScl)) - 1 * * For more details, see the reference manual * I2C Clock Generation chapter. */ /* n = Nlow + Nhigh */ n = (uint32_t)i2cNSum[i2cMode]; denominator = n * freqScl; /* Explicitly ensure denominator is never zero. */ if (denominator == 0) { EFM_ASSERT(0); return; } /* Perform integer division so that div is rounded up. */ div = ((freqRef - (I2C_CR_MAX * freqScl) + denominator - 1) / denominator) - 1; EFM_ASSERT(div >= 0); EFM_ASSERT((uint32_t)div <= _I2C_CLKDIV_DIV_MASK); /* The clock divisor must be at least 1 in slave mode according to the reference */ /* manual (in which case there is normally no need to set the bus frequency). */ if ((i2c->CTRL & I2C_CTRL_SLAVE) && (div == 0)) { div = 1; } i2c->CLKDIV = (uint32_t)div; } /***************************************************************************//** * @brief * Enable/disable I2C. * * @note * After enabling the I2C (from being disabled), the I2C is in BUSY state. * * @param[in] i2c * A pointer to the I2C peripheral register block. * * @param[in] enable * True to enable counting, false to disable. ******************************************************************************/ void I2C_Enable(I2C_TypeDef *i2c, bool enable) { EFM_ASSERT(I2C_REF_VALID(i2c)); #if defined (_I2C_EN_MASK) BUS_RegBitWrite(&(i2c->EN), _I2C_EN_EN_SHIFT, enable); #else BUS_RegBitWrite(&(i2c->CTRL), _I2C_CTRL_EN_SHIFT, enable); #endif } /***************************************************************************//** * @brief * Initialize I2C. * * @param[in] i2c * A pointer to the I2C peripheral register block. * * @param[in] init * A pointer to the I2C initialization structure. ******************************************************************************/ void I2C_Init(I2C_TypeDef *i2c, const I2C_Init_TypeDef *init) { EFM_ASSERT(I2C_REF_VALID(i2c)); i2c->IEN = 0; I2C_IntClear(i2c, _I2C_IF_MASK); /* Set SLAVE select mode. */ BUS_RegBitWrite(&(i2c->CTRL), _I2C_CTRL_SLAVE_SHIFT, init->master ? 0 : 1); I2C_BusFreqSet(i2c, init->refFreq, init->freq, init->clhr); I2C_Enable(i2c, init->enable); } /***************************************************************************//** * @brief * Reset I2C to the same state that it was in after a hardware reset. * * @note * The ROUTE register is NOT reset by this function to allow for * centralized setup of this feature. * * @param[in] i2c * A pointer to the I2C peripheral register block. ******************************************************************************/ void I2C_Reset(I2C_TypeDef *i2c) { // Cancel ongoing operations and clear TX buffer i2c->CMD = I2C_CMD_CLEARPC | I2C_CMD_CLEARTX | I2C_CMD_ABORT; i2c->CTRL = _I2C_CTRL_RESETVALUE; i2c->CLKDIV = _I2C_CLKDIV_RESETVALUE; i2c->SADDR = _I2C_SADDR_RESETVALUE; i2c->SADDRMASK = _I2C_SADDRMASK_RESETVALUE; i2c->IEN = _I2C_IEN_RESETVALUE; #if defined (_I2C_EN_EN_MASK) i2c->EN = _I2C_EN_RESETVALUE; #endif // Empty received data buffer flushRx(i2c); I2C_IntClear(i2c, _I2C_IF_MASK); /* Do not reset the route register; setting should be done independently. */ } /***************************************************************************//** * @brief * Continue an initiated I2C transfer (single master mode only). * * @details * This function is used repeatedly after a I2C_TransferInit() to * complete a transfer. It may be used in polled mode as the below example * shows: * @verbatim * I2C_TransferReturn_TypeDef ret; * * // Do a polled transfer * ret = I2C_TransferInit(I2C0, seq); * while (ret == i2cTransferInProgress) * { * ret = I2C_Transfer(I2C0); * } * @endverbatim * It may also be used in interrupt driven mode, where this function is invoked * from the interrupt handler. Notice that, if used in interrupt mode, NVIC * interrupts must be configured and enabled for the I2C bus used. I2C * peripheral specific interrupts are managed by this software. * * @note * Only single master mode is supported. * * @param[in] i2c * A pointer to the I2C peripheral register block. * * @return * Returns status for an ongoing transfer. * @li #i2cTransferInProgress - indicates that transfer not finished. * @li #i2cTransferDone - transfer completed successfully. * @li otherwise some sort of error has occurred. * ******************************************************************************/ I2C_TransferReturn_TypeDef I2C_Transfer(I2C_TypeDef *i2c) { uint32_t tmp; uint32_t pending; I2C_Transfer_TypeDef *transfer; I2C_TransferSeq_TypeDef *seq; EFM_ASSERT(I2C_REF_VALID(i2c)); /* Support up to 2 I2C buses. */ if (i2c == I2C0) { transfer = i2cTransfer; } #if (I2C_COUNT > 1) else if (i2c == I2C1) { transfer = i2cTransfer + 1; } #endif #if (I2C_COUNT > 2) else if (i2c == I2C2) { transfer = i2cTransfer + 2; } #endif else { return i2cTransferUsageFault; } seq = transfer->seq; for (;; ) { pending = i2c->IF; /* If some sort of fault, abort transfer. */ if (pending & I2C_IF_ERRORS) { if (pending & I2C_IF_ARBLOST) { /* If an arbitration fault, indicates either a slave device */ /* not responding as expected, or other master which is not */ /* supported by this software. */ transfer->result = i2cTransferArbLost; } else if (pending & I2C_IF_BUSERR) { /* A bus error indicates a misplaced start or stop, which should */ /* not occur in master mode controlled by this software. */ transfer->result = i2cTransferBusErr; } /* Ifan error occurs, it is difficult to know */ /* an exact cause and how to resolve. It will be up to a wrapper */ /* to determine how to handle a fault/recovery if possible. */ transfer->state = i2cStateDone; goto done; } switch (transfer->state) { /***************************************************/ /* Send the first start+address (first byte if 10 bit). */ /***************************************************/ case i2cStateStartAddrSend: if (seq->flags & I2C_FLAG_10BIT_ADDR) { tmp = (((uint32_t)(seq->addr) >> 8) & 0x06) | 0xf0; /* In 10 bit address mode, the address following the first */ /* start always indicates write. */ } else { tmp = (uint32_t)(seq->addr) & 0xfe; if (seq->flags & I2C_FLAG_READ) { /* Indicate read request */ tmp |= 1; } } transfer->state = i2cStateAddrWFAckNack; i2c->TXDATA = tmp;/* Data not transmitted until the START is sent. */ i2c->CMD = I2C_CMD_START; goto done; /*******************************************************/ /* Wait for ACK/NACK on the address (first byte if 10 bit). */ /*******************************************************/ case i2cStateAddrWFAckNack: if (pending & I2C_IF_NACK) { I2C_IntClear(i2c, I2C_IF_NACK); transfer->result = i2cTransferNack; transfer->state = i2cStateWFStopSent; i2c->CMD = I2C_CMD_STOP; } else if (pending & I2C_IF_ACK) { I2C_IntClear(i2c, I2C_IF_ACK); /* If a 10 bit address, send the 2nd byte of the address. */ if (seq->flags & I2C_FLAG_10BIT_ADDR) { transfer->state = i2cStateAddrWF2ndAckNack; i2c->TXDATA = (uint32_t)(seq->addr) & 0xff; } else { /* Determine whether receiving or sending data. */ if (seq->flags & I2C_FLAG_READ) { transfer->state = i2cStateWFData; if (seq->buf[transfer->bufIndx].len == 1) { i2c->CMD = I2C_CMD_NACK; } } else { transfer->state = i2cStateDataSend; continue; } } } goto done; /******************************************************/ /* Wait for ACK/NACK on the second byte of a 10 bit address. */ /******************************************************/ case i2cStateAddrWF2ndAckNack: if (pending & I2C_IF_NACK) { I2C_IntClear(i2c, I2C_IF_NACK); transfer->result = i2cTransferNack; transfer->state = i2cStateWFStopSent; i2c->CMD = I2C_CMD_STOP; } else if (pending & I2C_IF_ACK) { I2C_IntClear(i2c, I2C_IF_ACK); /* If using a plain read sequence with a 10 bit address, switch to send */ /* a repeated start. */ if (seq->flags & I2C_FLAG_READ) { transfer->state = i2cStateRStartAddrSend; } /* Otherwise, expected to write 0 or more bytes. */ else { transfer->state = i2cStateDataSend; } continue; } goto done; /*******************************/ /* Send a repeated start+address */ /*******************************/ case i2cStateRStartAddrSend: if (seq->flags & I2C_FLAG_10BIT_ADDR) { tmp = ((seq->addr >> 8) & 0x06) | 0xf0; } else { tmp = seq->addr & 0xfe; } /* If this is a write+read combined sequence, read is about to start. */ if (seq->flags & I2C_FLAG_WRITE_READ) { /* Indicate a read request. */ tmp |= 1; } transfer->state = i2cStateRAddrWFAckNack; /* The START command has to be written first since repeated start. Otherwise, */ /* data would be sent first. */ i2c->CMD = I2C_CMD_START; i2c->TXDATA = tmp; goto done; /**********************************************************************/ /* Wait for ACK/NACK on the repeated start+address (first byte if 10 bit) */ /**********************************************************************/ case i2cStateRAddrWFAckNack: if (pending & I2C_IF_NACK) { I2C_IntClear(i2c, I2C_IF_NACK); transfer->result = i2cTransferNack; transfer->state = i2cStateWFStopSent; i2c->CMD = I2C_CMD_STOP; } else if (pending & I2C_IF_ACK) { I2C_IntClear(i2c, I2C_IF_ACK); /* Determine whether receiving or sending data. */ if (seq->flags & I2C_FLAG_WRITE_READ) { transfer->state = i2cStateWFData; } else { transfer->state = i2cStateDataSend; continue; } } goto done; /*****************************/ /* Send a data byte to the slave */ /*****************************/ case i2cStateDataSend: /* Reached end of data buffer. */ if (transfer->offset >= seq->buf[transfer->bufIndx].len) { /* Move to the next message part. */ transfer->offset = 0; transfer->bufIndx++; /* Send a repeated start when switching to read mode on the 2nd buffer. */ if (seq->flags & I2C_FLAG_WRITE_READ) { transfer->state = i2cStateRStartAddrSend; continue; } /* Only writing from one buffer or finished both buffers. */ if ((seq->flags & I2C_FLAG_WRITE) || (transfer->bufIndx > 1)) { transfer->state = i2cStateWFStopSent; i2c->CMD = I2C_CMD_STOP; goto done; } /* Reprocess in case the next buffer is empty. */ continue; } /* Send byte. */ i2c->TXDATA = (uint32_t)(seq->buf[transfer->bufIndx].data[transfer->offset++]); transfer->state = i2cStateDataWFAckNack; goto done; /*********************************************************/ /* Wait for ACK/NACK from the slave after sending data to it. */ /*********************************************************/ case i2cStateDataWFAckNack: if (pending & I2C_IF_NACK) { I2C_IntClear(i2c, I2C_IF_NACK); transfer->result = i2cTransferNack; transfer->state = i2cStateWFStopSent; i2c->CMD = I2C_CMD_STOP; } else if (pending & I2C_IF_ACK) { I2C_IntClear(i2c, I2C_IF_ACK); transfer->state = i2cStateDataSend; continue; } goto done; /****************************/ /* Wait for data from slave */ /****************************/ case i2cStateWFData: if (pending & I2C_IF_RXDATAV) { uint8_t data; unsigned int rxLen = seq->buf[transfer->bufIndx].len; /* Must read out data not to block further progress. */ data = (uint8_t)(i2c->RXDATA); /* SW needs to clear RXDATAV IF on Series 2 devices. Flag is kept high by HW if buffer is not empty. */ #if defined(_SILICON_LABS_32B_SERIES_2) I2C_IntClear(i2c, I2C_IF_RXDATAV); #endif /* Make sure that there is no storing beyond the end of the buffer (just in case). */ if (transfer->offset < rxLen) { seq->buf[transfer->bufIndx].data[transfer->offset++] = data; } /* If all requested data is read, the sequence should end. */ if (transfer->offset >= rxLen) { /* If receiving only one byte, transmit the NACK now before stopping. */ if (1 == rxLen) { i2c->CMD = I2C_CMD_NACK; } transfer->state = i2cStateWFStopSent; i2c->CMD = I2C_CMD_STOP; } else { /* Send ACK and wait for the next byte. */ i2c->CMD = I2C_CMD_ACK; if ( (1 < rxLen) && (transfer->offset == (rxLen - 1)) ) { /* If receiving more than one byte and this is the next to last byte, transmit the NACK now before receiving the last byte. */ i2c->CMD = I2C_CMD_NACK; } } } goto done; /***********************************/ /* Wait for STOP to have been sent */ /***********************************/ case i2cStateWFStopSent: if (pending & I2C_IF_MSTOP) { I2C_IntClear(i2c, I2C_IF_MSTOP); transfer->state = i2cStateDone; } goto done; /******************************/ /* An unexpected state, software fault */ /******************************/ default: transfer->result = i2cTransferSwFault; transfer->state = i2cStateDone; goto done; } } done: if (transfer->state == i2cStateDone) { /* Disable interrupt sources when done. */ i2c->IEN = 0; /* Update the result unless a fault has already occurred. */ if (transfer->result == i2cTransferInProgress) { transfer->result = i2cTransferDone; } } /* Until transfer is done, keep returning i2cTransferInProgress. */ else { return i2cTransferInProgress; } return transfer->result; } /***************************************************************************//** * @brief * Prepare and start an I2C transfer (single master mode only). * * @details * This function must be invoked to start an I2C transfer * sequence. To complete the transfer, I2C_Transfer() must * be used either in polled mode or by adding a small driver wrapper using * interrupts. * * @note * Only single master mode is supported. * * @param[in] i2c * A pointer to the I2C peripheral register block. * * @param[in] seq * A pointer to the sequence structure defining the I2C transfer to take place. The * referenced structure must exist until the transfer has fully completed. * * @return * Returns the status for an ongoing transfer: * @li #i2cTransferInProgress - indicates that the transfer is not finished. * @li Otherwise, an error has occurred. ******************************************************************************/ I2C_TransferReturn_TypeDef I2C_TransferInit(I2C_TypeDef *i2c, I2C_TransferSeq_TypeDef *seq) { I2C_Transfer_TypeDef *transfer; EFM_ASSERT(I2C_REF_VALID(i2c)); EFM_ASSERT(seq); /* Support up to 2 I2C buses. */ if (i2c == I2C0) { transfer = i2cTransfer; } #if (I2C_COUNT > 1) else if (i2c == I2C1) { transfer = i2cTransfer + 1; } #endif #if (I2C_COUNT > 2) else if (i2c == I2C2) { transfer = i2cTransfer + 2; } #endif else { return i2cTransferUsageFault; } /* Check if in a busy state. Since this software assumes a single master, */ /* issue an abort. The BUSY state is normal after a reset. */ if (i2c->STATE & I2C_STATE_BUSY) { i2c->CMD = I2C_CMD_ABORT; } /* Do not try to read 0 bytes. It is not */ /* possible according to the I2C spec, since the slave will always start */ /* sending the first byte ACK on an address. The read operation can */ /* only be stopped by NACKing a received byte, i.e., minimum 1 byte. */ if (((seq->flags & I2C_FLAG_READ) && !(seq->buf[0].len)) || ((seq->flags & I2C_FLAG_WRITE_READ) && !(seq->buf[1].len)) ) { return i2cTransferUsageFault; } /* Prepare for a transfer. */ transfer->state = i2cStateStartAddrSend; transfer->result = i2cTransferInProgress; transfer->offset = 0; transfer->bufIndx = 0; transfer->seq = seq; /* Ensure buffers are empty. */ i2c->CMD = I2C_CMD_CLEARPC | I2C_CMD_CLEARTX; flushRx(i2c); /* Clear all pending interrupts prior to starting a transfer. */ I2C_IntClear(i2c, _I2C_IF_MASK); /* Enable relevant interrupts. */ /* Notice that the I2C interrupt must also be enabled in the NVIC, but */ /* that is left for an additional driver wrapper. */ i2c->IEN |= I2C_IEN_NACK | I2C_IEN_ACK | I2C_IEN_MSTOP | I2C_IEN_RXDATAV | I2C_IEN_ERRORS; /* Start a transfer. */ return I2C_Transfer(i2c); } /** @} (end addtogroup I2C) */ /** @} (end addtogroup emlib) */ #endif /* defined(I2C_COUNT) && (I2C_COUNT > 0) */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/emlib/src/em_ldma.c.
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/***************************************************************************//** * @file * @brief Direct memory access (LDMA) module peripheral API * @version 5.7.0 ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * SPDX-License-Identifier: Zlib * * The licensor of this software is Silicon Laboratories Inc. * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be * appreciated but is not required. * 2. Altered source versions must be plainly marked as such, and must not be * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * ******************************************************************************/ #include "em_ldma.h" #if defined(LDMA_PRESENT) && (LDMA_COUNT == 1) #include <stddef.h> #include "em_assert.h" #include "em_bus.h" #include "em_cmu.h" #include "em_core.h" /***************************************************************************//** * @addtogroup emlib * @{ ******************************************************************************/ /***************************************************************************//** * @addtogroup LDMA * @{ ******************************************************************************/ #if defined(LDMA_IRQ_HANDLER_TEMPLATE) /***************************************************************************//** * @brief * A template for an LDMA IRQ handler. ******************************************************************************/ void LDMA_IRQHandler(void) { uint32_t ch; /* Get all pending and enabled interrupts. */ uint32_t pending = LDMA_IntGetEnabled(); /* Loop on an LDMA error to enable debugging. */ while (pending & LDMA_IF_ERROR) { } /* Iterate over all LDMA channels. */ for (ch = 0; ch < DMA_CHAN_COUNT; ch++) { uint32_t mask = 0x1 << ch; if (pending & mask) { /* Clear the interrupt flag. */ LDMA->IFC = mask; /* Perform more actions here, execute callbacks, and so on. */ } } } #endif /***************************************************************************//** * @brief * De-initialize the LDMA controller. * * LDMA interrupts are disabled and the LDMA clock is stopped. ******************************************************************************/ void LDMA_DeInit(void) { NVIC_DisableIRQ(LDMA_IRQn); LDMA->IEN = 0; #if defined(_LDMA_CHDIS_MASK) LDMA->CHDIS = _LDMA_CHEN_MASK; #else LDMA->CHEN = 0; #endif #if defined(LDMA_EN_EN) LDMA->EN = 0; #endif #if !defined(_SILICON_LABS_32B_SERIES_2) CMU_ClockEnable(cmuClock_LDMA, false); #endif } /***************************************************************************//** * @brief * Enable or disable an LDMA channel request. * * @details * Use this function to enable or disable an LDMA channel request. This will * prevent the LDMA from proceeding after its current transaction if disabled. * * @param[in] channel * LDMA channel to enable or disable requests. * * @param[in] enable * If 'true', the request will be enabled. If 'false', the request will be disabled. ******************************************************************************/ void LDMA_EnableChannelRequest(int ch, bool enable) { EFM_ASSERT(ch < (int)DMA_CHAN_COUNT); BUS_RegBitWrite(&LDMA->REQDIS, ch, !enable); } /***************************************************************************//** * @brief * Initialize the LDMA controller. * * @details * This function will disable all the LDMA channels and enable the LDMA bus * clock in the CMU. This function will also enable the LDMA IRQ in the NVIC * and set the LDMA IRQ priority to a user-configurable priority. The LDMA * interrupt priority is configured using the @ref LDMA_Init_t structure. * * @note * Since this function enables the LDMA IRQ, always add a custom * LDMA_IRQHandler to the application to handle any interrupts * from LDMA. * * @param[in] init * A pointer to the initialization structure used to configure the LDMA. ******************************************************************************/ void LDMA_Init(const LDMA_Init_t *init) { uint32_t ldmaCtrlVal; EFM_ASSERT(init != NULL); EFM_ASSERT(!(((uint32_t)init->ldmaInitCtrlNumFixed << _LDMA_CTRL_NUMFIXED_SHIFT) & ~_LDMA_CTRL_NUMFIXED_MASK)); #if defined(_LDMA_CTRL_SYNCPRSCLREN_SHIFT) && defined (_LDMA_CTRL_SYNCPRSSETEN_SHIFT) EFM_ASSERT(!(((uint32_t)init->ldmaInitCtrlSyncPrsClrEn << _LDMA_CTRL_SYNCPRSCLREN_SHIFT) & ~_LDMA_CTRL_SYNCPRSCLREN_MASK)); EFM_ASSERT(!(((uint32_t)init->ldmaInitCtrlSyncPrsSetEn << _LDMA_CTRL_SYNCPRSSETEN_SHIFT) & ~_LDMA_CTRL_SYNCPRSSETEN_MASK)); #endif #if defined(_LDMA_SYNCHWEN_SYNCCLREN_SHIFT) && defined (_LDMA_SYNCHWEN_SYNCSETEN_SHIFT) EFM_ASSERT(!(((uint32_t)init->ldmaInitCtrlSyncPrsClrEn << _LDMA_SYNCHWEN_SYNCCLREN_SHIFT) & ~_LDMA_SYNCHWEN_SYNCCLREN_MASK)); EFM_ASSERT(!(((uint32_t)init->ldmaInitCtrlSyncPrsSetEn << _LDMA_SYNCHWEN_SYNCSETEN_SHIFT) & ~_LDMA_SYNCHWEN_SYNCSETEN_MASK)); #endif EFM_ASSERT(init->ldmaInitIrqPriority < (1 << __NVIC_PRIO_BITS)); #if defined(LDMA_EN_EN) LDMA->EN = LDMA_EN_EN; #endif #if !defined(_SILICON_LABS_32B_SERIES_2) CMU_ClockEnable(cmuClock_LDMA, true); #endif ldmaCtrlVal = init->ldmaInitCtrlNumFixed << _LDMA_CTRL_NUMFIXED_SHIFT; #if defined(_LDMA_CTRL_SYNCPRSCLREN_SHIFT) && defined (_LDMA_CTRL_SYNCPRSSETEN_SHIFT) ldmaCtrlVal |= (init->ldmaInitCtrlSyncPrsClrEn << _LDMA_CTRL_SYNCPRSCLREN_SHIFT) | (init->ldmaInitCtrlSyncPrsSetEn << _LDMA_CTRL_SYNCPRSSETEN_SHIFT); #endif LDMA->CTRL = ldmaCtrlVal; #if defined(_LDMA_SYNCHWEN_SYNCCLREN_SHIFT) && defined (_LDMA_SYNCHWEN_SYNCSETEN_SHIFT) LDMA->SYNCHWEN = (init->ldmaInitCtrlSyncPrsClrEn << _LDMA_SYNCHWEN_SYNCCLREN_SHIFT) | (init->ldmaInitCtrlSyncPrsSetEn << _LDMA_SYNCHWEN_SYNCSETEN_SHIFT); #endif #if defined(_LDMA_CHDIS_MASK) LDMA->CHDIS = _LDMA_CHEN_MASK; #else LDMA->CHEN = 0; #endif LDMA->DBGHALT = 0; LDMA->REQDIS = 0; /* Enable the LDMA error interrupt. */ #if defined (LDMA_IEN_ERRORIEN) LDMA->IEN = LDMA_IEN_ERRORIEN; #elif defined (LDMA_IEN_ERROR) LDMA->IEN = LDMA_IEN_ERROR; #else #error "IEN register not defined!!!" #endif #if defined (LDMA_HAS_SET_CLEAR) LDMA->IF_CLR = 0xFFFFFFFFU; #else LDMA->IFC = 0xFFFFFFFFU; #endif NVIC_ClearPendingIRQ(LDMA_IRQn); /* Range is 0-7, where 0 is the highest priority. */ NVIC_SetPriority(LDMA_IRQn, init->ldmaInitIrqPriority); NVIC_EnableIRQ(LDMA_IRQn); } /***************************************************************************//** * @brief * Start a DMA transfer. * * @param[in] ch * A DMA channel. * * @param[in] transfer * The initialization structure used to configure the transfer. * * @param[in] descriptor * The transfer descriptor, which can be an array of descriptors linked together. ******************************************************************************/ void LDMA_StartTransfer(int ch, const LDMA_TransferCfg_t *transfer, const LDMA_Descriptor_t *descriptor) { #if !(defined (_LDMA_SYNCHWEN_SYNCCLREN_SHIFT) && defined (_LDMA_SYNCHWEN_SYNCSETEN_SHIFT)) uint32_t tmp; #endif CORE_DECLARE_IRQ_STATE; uint32_t chMask = 1UL << (uint8_t)ch; EFM_ASSERT(ch < (int)DMA_CHAN_COUNT); EFM_ASSERT(transfer != NULL); #if defined (_LDMAXBAR_CH_REQSEL_MASK) EFM_ASSERT(!(transfer->ldmaReqSel & ~_LDMAXBAR_CH_REQSEL_MASK)); #elif defined (_LDMA_CH_REQSEL_MASK) EFM_ASSERT(!(transfer->ldmaReqSel & ~_LDMA_CH_REQSEL_MASK)); #endif #if defined (_LDMA_SYNCHWEN_SYNCCLREN_SHIFT) && defined (_LDMA_SYNCHWEN_SYNCSETEN_SHIFT) EFM_ASSERT(!(((uint32_t)transfer->ldmaCtrlSyncPrsClrOff << _LDMA_SYNCHWEN_SYNCCLREN_SHIFT) & ~_LDMA_SYNCHWEN_SYNCCLREN_MASK)); EFM_ASSERT(!(((uint32_t)transfer->ldmaCtrlSyncPrsClrOn << _LDMA_SYNCHWEN_SYNCCLREN_SHIFT) & ~_LDMA_SYNCHWEN_SYNCCLREN_MASK)); EFM_ASSERT(!(((uint32_t)transfer->ldmaCtrlSyncPrsSetOff << _LDMA_SYNCHWEN_SYNCSETEN_SHIFT) & ~_LDMA_SYNCHWEN_SYNCSETEN_MASK)); EFM_ASSERT(!(((uint32_t)transfer->ldmaCtrlSyncPrsSetOn << _LDMA_SYNCHWEN_SYNCSETEN_SHIFT) & ~_LDMA_SYNCHWEN_SYNCSETEN_MASK)); #elif defined (_LDMA_CTRL_SYNCPRSCLREN_SHIFT) && defined (_LDMA_CTRL_SYNCPRSSETEN_SHIFT) EFM_ASSERT(!(((uint32_t)transfer->ldmaCtrlSyncPrsClrOff << _LDMA_CTRL_SYNCPRSCLREN_SHIFT) & ~_LDMA_CTRL_SYNCPRSCLREN_MASK)); EFM_ASSERT(!(((uint32_t)transfer->ldmaCtrlSyncPrsClrOn << _LDMA_CTRL_SYNCPRSCLREN_SHIFT) & ~_LDMA_CTRL_SYNCPRSCLREN_MASK)); EFM_ASSERT(!(((uint32_t)transfer->ldmaCtrlSyncPrsSetOff << _LDMA_CTRL_SYNCPRSSETEN_SHIFT) & ~_LDMA_CTRL_SYNCPRSSETEN_MASK)); EFM_ASSERT(!(((uint32_t)transfer->ldmaCtrlSyncPrsSetOn << _LDMA_CTRL_SYNCPRSSETEN_SHIFT) & ~_LDMA_CTRL_SYNCPRSSETEN_MASK)); #endif EFM_ASSERT(!(((uint32_t)transfer->ldmaCfgArbSlots << _LDMA_CH_CFG_ARBSLOTS_SHIFT) & ~_LDMA_CH_CFG_ARBSLOTS_MASK)); EFM_ASSERT(!(((uint32_t)transfer->ldmaCfgSrcIncSign << _LDMA_CH_CFG_SRCINCSIGN_SHIFT) & ~_LDMA_CH_CFG_SRCINCSIGN_MASK)); EFM_ASSERT(!(((uint32_t)transfer->ldmaCfgDstIncSign << _LDMA_CH_CFG_DSTINCSIGN_SHIFT) & ~_LDMA_CH_CFG_DSTINCSIGN_MASK)); EFM_ASSERT(!(((uint32_t)transfer->ldmaLoopCnt << _LDMA_CH_LOOP_LOOPCNT_SHIFT) & ~_LDMA_CH_LOOP_LOOPCNT_MASK)); #if defined(LDMAXBAR) LDMAXBAR->CH[ch].REQSEL = transfer->ldmaReqSel; #else LDMA->CH[ch].REQSEL = transfer->ldmaReqSel; #endif LDMA->CH[ch].LOOP = transfer->ldmaLoopCnt << _LDMA_CH_LOOP_LOOPCNT_SHIFT; LDMA->CH[ch].CFG = (transfer->ldmaCfgArbSlots << _LDMA_CH_CFG_ARBSLOTS_SHIFT) | (transfer->ldmaCfgSrcIncSign << _LDMA_CH_CFG_SRCINCSIGN_SHIFT) | (transfer->ldmaCfgDstIncSign << _LDMA_CH_CFG_DSTINCSIGN_SHIFT); /* Set the descriptor address. */ LDMA->CH[ch].LINK = (uint32_t)descriptor & _LDMA_CH_LINK_LINKADDR_MASK; /* Clear the pending channel interrupt. */ #if defined (LDMA_HAS_SET_CLEAR) LDMA->IF_CLR = chMask; #else LDMA->IFC = chMask; #endif /* A critical region. */ CORE_ENTER_ATOMIC(); /* Enable the channel interrupt. */ LDMA->IEN |= chMask; if (transfer->ldmaReqDis) { LDMA->REQDIS |= chMask; } if (transfer->ldmaDbgHalt) { LDMA->DBGHALT |= chMask; } #if defined (_LDMA_SYNCHWEN_SYNCCLREN_SHIFT) && defined (_LDMA_SYNCHWEN_SYNCSETEN_SHIFT) LDMA->SYNCHWEN_CLR = ((transfer->ldmaCtrlSyncPrsClrOff << _LDMA_SYNCHWEN_SYNCCLREN_SHIFT) | (transfer->ldmaCtrlSyncPrsSetOff << _LDMA_SYNCHWEN_SYNCSETEN_SHIFT)) & _LDMA_SYNCHWEN_MASK; LDMA->SYNCHWEN_SET = ((transfer->ldmaCtrlSyncPrsClrOn << _LDMA_SYNCHWEN_SYNCCLREN_SHIFT) | (transfer->ldmaCtrlSyncPrsSetOn << _LDMA_SYNCHWEN_SYNCSETEN_SHIFT)) & _LDMA_SYNCHWEN_MASK; #elif defined (_LDMA_CTRL_SYNCPRSCLREN_SHIFT) && defined (_LDMA_CTRL_SYNCPRSSETEN_SHIFT) tmp = LDMA->CTRL; if (transfer->ldmaCtrlSyncPrsClrOff) { tmp &= ~_LDMA_CTRL_SYNCPRSCLREN_MASK | (~transfer->ldmaCtrlSyncPrsClrOff << _LDMA_CTRL_SYNCPRSCLREN_SHIFT); } if (transfer->ldmaCtrlSyncPrsClrOn) { tmp |= transfer->ldmaCtrlSyncPrsClrOn << _LDMA_CTRL_SYNCPRSCLREN_SHIFT; } if (transfer->ldmaCtrlSyncPrsSetOff) { tmp &= ~_LDMA_CTRL_SYNCPRSSETEN_MASK | (~transfer->ldmaCtrlSyncPrsSetOff << _LDMA_CTRL_SYNCPRSSETEN_SHIFT); } if (transfer->ldmaCtrlSyncPrsSetOn) { tmp |= transfer->ldmaCtrlSyncPrsSetOn << _LDMA_CTRL_SYNCPRSSETEN_SHIFT; } LDMA->CTRL = tmp; #else #error "SYNC Set and SYNC Clear not defined" #endif BUS_RegMaskedClear(&LDMA->CHDONE, chMask); /* Clear the done flag. */ LDMA->LINKLOAD = chMask; /* Start a transfer by loading the descriptor. */ /* A critical region end. */ CORE_EXIT_ATOMIC(); } /***************************************************************************//** * @brief * Stop a DMA transfer. * * @note * The DMA will complete the current AHB burst transfer before stopping. * * @param[in] ch * A DMA channel to stop. ******************************************************************************/ void LDMA_StopTransfer(int ch) { uint32_t chMask = 1UL << (uint8_t)ch; EFM_ASSERT(ch < (int)DMA_CHAN_COUNT); CORE_ATOMIC_SECTION( LDMA->IEN &= ~chMask; #if defined(_LDMA_CHDIS_MASK) LDMA->CHDIS = chMask; #else BUS_RegMaskedClear(&LDMA->CHEN, chMask); #endif ) } /***************************************************************************//** * @brief * Check if a DMA transfer has completed. * * @param[in] ch * A DMA channel to check. * * @return * True if transfer has completed, false if not. ******************************************************************************/ bool LDMA_TransferDone(int ch) { bool retVal = false; uint32_t chMask = 1UL << (uint8_t)ch; EFM_ASSERT(ch < (int)DMA_CHAN_COUNT); CORE_ATOMIC_SECTION( if ( #if defined(_LDMA_CHSTATUS_MASK) ((LDMA->CHSTATUS & chMask) == 0) #else ((LDMA->CHEN & chMask) == 0) #endif && ((LDMA->CHDONE & chMask) == chMask)) { retVal = true; } ) return retVal; } /***************************************************************************//** * @brief * Get the number of items remaining in a transfer. * * @note * This function does not take into account that a DMA transfer with * a chain of linked transfers might be ongoing. It will only check the * count for the current transfer. * * @param[in] ch * The channel number of the transfer to check. * * @return * A number of items remaining in the transfer. ******************************************************************************/ uint32_t LDMA_TransferRemainingCount(int ch) { uint32_t remaining, done, iflag; uint32_t chMask = 1UL << (uint8_t)ch; EFM_ASSERT(ch < (int)DMA_CHAN_COUNT); CORE_ATOMIC_SECTION( iflag = LDMA->IF; done = LDMA->CHDONE; remaining = LDMA->CH[ch].CTRL; ) iflag &= chMask; done &= chMask; remaining = (remaining & _LDMA_CH_CTRL_XFERCNT_MASK) >> _LDMA_CH_CTRL_XFERCNT_SHIFT; if (done || ((remaining == 0) && iflag)) { return 0; } return remaining + 1; } /** @} (end addtogroup LDMA) */ /** @} (end addtogroup emlib) */ #endif /* defined( LDMA_PRESENT ) && ( LDMA_COUNT == 1 ) */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/emlib/src/em_letimer.c.
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/***************************************************************************//** * @file * @brief Low Energy Timer (LETIMER) Peripheral API * @version 5.7.0 ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * SPDX-License-Identifier: Zlib * * The licensor of this software is Silicon Laboratories Inc. * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be * appreciated but is not required. * 2. Altered source versions must be plainly marked as such, and must not be * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * ******************************************************************************/ #include "em_letimer.h" #if defined(LETIMER_COUNT) && (LETIMER_COUNT > 0) #include "em_cmu.h" #include "em_assert.h" /***************************************************************************//** * @addtogroup emlib * @{ ******************************************************************************/ /***************************************************************************//** * @addtogroup LETIMER * @brief Low Energy Timer (LETIMER) Peripheral API * @details * This module contains functions to control the LETIMER peripheral of Silicon * Labs 32-bit MCUs and SoCs. The LETIMER is a down-counter that can keep track * of time and output configurable waveforms. * @{ ******************************************************************************/ /******************************************************************************* ******************************* DEFINES *********************************** ******************************************************************************/ /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ /** A validation of the valid comparator register for assert statements. */ #define LETIMER_COMP_REG_VALID(reg) (((reg) <= 1)) /** A validation of the LETIMER register block pointer reference for assert statements. */ #if (LETIMER_COUNT == 1) #define LETIMER_REF_VALID(ref) ((ref) == LETIMER0) #elif (LETIMER_COUNT == 2) #define LETIMER_REF_VALID(ref) (((ref) == LETIMER0) || ((ref) == LETIMER1)) #else #error Undefined number of analog comparators (ACMP). #endif /** A validation of the valid repeat counter register for assert statements. */ #define LETIMER_REP_REG_VALID(reg) (((reg) <= 1)) /** @endcond */ /******************************************************************************* ************************** LOCAL FUNCTIONS ******************************** ******************************************************************************/ /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ #if defined(_EFM32_GECKO_FAMILY) /***************************************************************************//** * @brief * Wait for an ongoing sync of register(s) to the low-frequency domain to complete. * * @note * This only applies to the Gecko Family. See the reference manual * chapter about Access to Low Energy Peripherals (Asynchronos Registers) * for details. * * @param[in] letimer * A pointer to the LETIMER peripheral register block. * * @param[in] mask * A bitmask corresponding to SYNCBUSY register defined bits, indicating * registers that must complete any ongoing synchronization. ******************************************************************************/ __STATIC_INLINE void regSync(LETIMER_TypeDef *letimer, uint32_t mask) { #if defined(_LETIMER_FREEZE_MASK) /* Avoid a deadlock if modifying the same register twice when freeze mode is */ /* activated. */ if (letimer->FREEZE & LETIMER_FREEZE_REGFREEZE) { return; } #endif /* Wait for any pending previous write operation to complete */ /* in the low-frequency domain. This is only required for the Gecko Family of devices. */ while (letimer->SYNCBUSY & mask) { } } #endif /** @endcond */ /******************************************************************************* ************************** GLOBAL FUNCTIONS ******************************* ******************************************************************************/ /***************************************************************************//** * @brief * Get the LETIMER compare register value. * * @param[in] letimer * A pointer to the LETIMER peripheral register block. * * @param[in] comp * A compare register to get, either 0 or 1. * * @return * A compare register value, 0 if invalid register selected. ******************************************************************************/ uint32_t LETIMER_CompareGet(LETIMER_TypeDef *letimer, unsigned int comp) { uint32_t ret; EFM_ASSERT(LETIMER_REF_VALID(letimer) && LETIMER_COMP_REG_VALID(comp)); /* Initialize the selected compare value. */ switch (comp) { case 0: ret = letimer->COMP0; break; case 1: ret = letimer->COMP1; break; default: /* An unknown compare register selected. */ ret = 0; break; } return(ret); } /***************************************************************************//** * @brief * Set the LETIMER compare register value. * * @note * The setting of a compare register requires synchronization into the * low frequency domain. If the same register is modified before a previous * update has completed, this function will stall until the previous * synchronization has completed. This only applies to the Gecko Family. See * comments in the LETIMER_Sync() internal function call. * * @param[in] letimer * A pointer to the LETIMER peripheral register block. * * @param[in] comp * A compare register to set, either 0 or 1. * * @param[in] value * An initialization value (<= 0x0000ffff). ******************************************************************************/ void LETIMER_CompareSet(LETIMER_TypeDef *letimer, unsigned int comp, uint32_t value) { volatile uint32_t *compReg; EFM_ASSERT(LETIMER_REF_VALID(letimer) && LETIMER_COMP_REG_VALID(comp) && ((value & ~(_LETIMER_COMP0_COMP0_MASK >> _LETIMER_COMP0_COMP0_SHIFT)) == 0)); /* Initialize the selected compare value. */ switch (comp) { case 0: compReg = &(letimer->COMP0); break; case 1: compReg = &(letimer->COMP1); break; default: /* An unknown compare register selected, abort. */ return; } #if defined(_EFM32_GECKO_FAMILY) /* LF register about to be modified requires sync; busy check. */ regSync(letimer, comp ? LETIMER_SYNCBUSY_COMP1 : LETIMER_SYNCBUSY_COMP0); #endif *compReg = value; } /***************************************************************************//** * @brief * Start/stop LETIMER. * * @note * The enabling/disabling of the LETIMER modifies the LETIMER CMD register * which requires synchronization into the low-frequency domain. If this * register is modified before a previous update to the same register has * completed, this function will stall until the previous synchronization has * completed. This only applies to the Gecko Family. See comments in the * LETIMER_Sync() internal function call. * * @param[in] letimer * A pointer to the LETIMER peripheral register block. * * @param[in] enable * True to enable counting, false to disable. ******************************************************************************/ void LETIMER_Enable(LETIMER_TypeDef *letimer, bool enable) { EFM_ASSERT(LETIMER_REF_VALID(letimer)); #if defined(_EFM32_GECKO_FAMILY) /* LF register about to be modified requires sync; busy check. */ regSync(letimer, LETIMER_SYNCBUSY_CMD); #elif defined (LETIMER_SYNCBUSY_START) && defined (LETIMER_SYNCBUSY_STOP) uint32_t syncBusyMask = LETIMER_SYNCBUSY_STOP | LETIMER_SYNCBUSY_START; while (letimer->SYNCBUSY & syncBusyMask) { } #endif if (enable) { letimer->CMD = LETIMER_CMD_START; } else { letimer->CMD = LETIMER_CMD_STOP; } } #if defined(_LETIMER_FREEZE_MASK) /***************************************************************************//** * @brief * LETIMER register synchronization freeze control. * * @details * Some LETIMER registers require synchronization into the low-frequency (LF) * domain. The freeze feature allows for several such registers to be * modified before passing them to the LF domain simultaneously (which * takes place when the freeze mode is disabled). * * @note * When enabling freeze mode, this function will wait for all current * ongoing LETIMER synchronization to the LF domain to complete (Normally * synchronization will not be in progress.) However, for this reason, when * using freeze mode, modifications of registers requiring the LF synchronization * should be done within one freeze enable/disable block to avoid unecessary * stalling. * * @param[in] letimer * A pointer to the LETIMER peripheral register block. * * @param[in] enable * @li True - enable freeze, modified registers are not propagated to the * LF domain * @li False - disables freeze, modified registers are propagated to the LF * domain ******************************************************************************/ void LETIMER_FreezeEnable(LETIMER_TypeDef *letimer, bool enable) { if (enable) { /* * Wait for any ongoing LF synchronization to complete to * protect against the rare case when a user * - modifies a register requiring LF sync * - then enables freeze before LF sync completed * - then modifies the same register again * since modifying a register while it is in sync progress should be * avoided. */ while (letimer->SYNCBUSY) { } letimer->FREEZE = LETIMER_FREEZE_REGFREEZE; } else { letimer->FREEZE = 0; } } #endif /* defined(_LETIMER_FREEZE_MASK) */ /***************************************************************************//** * @brief * Initialize LETIMER. * * @details * Note that the compare/repeat values must be set separately with * LETIMER_CompareSet() and LETIMER_RepeatSet(). That should probably be done * prior using this function if configuring the LETIMER to start when * initialization is complete. * * @note * The initialization of the LETIMER modifies the LETIMER CTRL/CMD registers * which require synchronization into the low-frequency domain. If any of those * registers are modified before a previous update to the same register has * completed, this function will stall until the previous synchronization has * completed. This only applies to the Gecko Family. See comments in the * LETIMER_Sync() internal function call. * * @param[in] letimer * A pointer to the LETIMER peripheral register block. * * @param[in] init * A pointer to the LETIMER initialization structure. ******************************************************************************/ void LETIMER_Init(LETIMER_TypeDef *letimer, const LETIMER_Init_TypeDef *init) { uint32_t tmp = 0; EFM_ASSERT(LETIMER_REF_VALID(letimer)); #if defined (LETIMER_EN_EN) letimer->EN_SET = LETIMER_EN_EN; #endif /* Stop the timer if specified to be disabled and running. */ if (!(init->enable) && (letimer->STATUS & LETIMER_STATUS_RUNNING)) { #if defined(_EFM32_GECKO_FAMILY) /* LF register about to be modified requires sync; busy check. */ regSync(letimer, LETIMER_SYNCBUSY_CMD); #elif defined(LETIMER_SYNCBUSY_STOP) while (letimer->SYNCBUSY & LETIMER_SYNCBUSY_STOP) { } #endif letimer->CMD = LETIMER_CMD_STOP; } /* Configure the DEBUGRUN flag, which sets whether or not the counter should be * updated when the debugger is active. */ if (init->debugRun) { tmp |= LETIMER_CTRL_DEBUGRUN; } #if defined(LETIMER_CTRL_RTCC0TEN) if (init->rtcComp0Enable) { tmp |= LETIMER_CTRL_RTCC0TEN; } if (init->rtcComp1Enable) { tmp |= LETIMER_CTRL_RTCC1TEN; } #endif if ((init->comp0Top) || (init->topValue != 0U)) { #if defined (LETIMER_CTRL_COMP0TOP) tmp |= LETIMER_CTRL_COMP0TOP; letimer->COMP0 = init->topValue; #elif defined (LETIMER_CTRL_CNTTOPEN) tmp |= LETIMER_CTRL_CNTTOPEN; letimer->TOP = init->topValue; #endif } if (init->bufTop) { tmp |= LETIMER_CTRL_BUFTOP; } if (init->out0Pol) { tmp |= LETIMER_CTRL_OPOL0; } if (init->out1Pol) { tmp |= LETIMER_CTRL_OPOL1; } tmp |= init->ufoa0 << _LETIMER_CTRL_UFOA0_SHIFT; tmp |= init->ufoa1 << _LETIMER_CTRL_UFOA1_SHIFT; tmp |= init->repMode << _LETIMER_CTRL_REPMODE_SHIFT; #if defined(_EFM32_GECKO_FAMILY) /* LF register about to be modified requires sync; busy check. */ regSync(letimer, LETIMER_SYNCBUSY_CTRL); #endif letimer->CTRL = tmp; /* Start the timer if specified to be enabled and not already running. */ if (init->enable && !(letimer->STATUS & LETIMER_STATUS_RUNNING)) { #if defined(_EFM32_GECKO_FAMILY) /* LF register about to be modified requires sync; busy check. */ regSync(letimer, LETIMER_SYNCBUSY_CMD); #elif defined(LETIMER_SYNCBUSY_START) while (letimer->SYNCBUSY & LETIMER_SYNCBUSY_START) { } #endif letimer->CMD = LETIMER_CMD_START; } } /***************************************************************************//** * @brief * Get the LETIMER repeat register value. * * @param[in] letimer * A pointer to the LETIMER peripheral register block. * * @param[in] rep * Repeat register to get, either 0 or 1. * * @return * Repeat register value, 0 if invalid register selected. ******************************************************************************/ uint32_t LETIMER_RepeatGet(LETIMER_TypeDef *letimer, unsigned int rep) { uint32_t ret; EFM_ASSERT(LETIMER_REF_VALID(letimer) && LETIMER_REP_REG_VALID(rep)); /* Initialize the selected compare value. */ switch (rep) { case 0: ret = letimer->REP0; break; case 1: ret = letimer->REP1; break; default: /* An unknown compare register selected. */ ret = 0; break; } return(ret); } /***************************************************************************//** * @brief * Set the LETIMER repeat counter register value. * * @note * The setting of a repeat counter register requires synchronization into the * low-frequency domain. If the same register is modified before a previous * update has completed, this function will stall until the previous * synchronization has completed. This only applies to the Gecko Family. See * comments in the LETIMER_Sync() internal function call. * * @param[in] letimer * A pointer to the LETIMER peripheral register block. * * @param[in] rep * Repeat counter register to set, either 0 or 1. * * @param[in] value * An initialization value (<= 0x0000ffff). ******************************************************************************/ void LETIMER_RepeatSet(LETIMER_TypeDef *letimer, unsigned int rep, uint32_t value) { volatile uint32_t *repReg; #if defined(_EFM32_GECKO_FAMILY) uint32_t syncbusy; #endif EFM_ASSERT(LETIMER_REF_VALID(letimer) && LETIMER_REP_REG_VALID(rep) && ((value & ~(_LETIMER_REP0_REP0_MASK >> _LETIMER_REP0_REP0_SHIFT)) == 0)); /* Initialize the selected compare value. */ switch (rep) { case 0: repReg = &(letimer->REP0); #if defined(_EFM32_GECKO_FAMILY) syncbusy = LETIMER_SYNCBUSY_REP0; #endif break; case 1: repReg = &(letimer->REP1); #if defined(_EFM32_GECKO_FAMILY) syncbusy = LETIMER_SYNCBUSY_REP1; #endif break; default: /* An unknown compare register selected, abort. */ return; } #if defined(_EFM32_GECKO_FAMILY) /* LF register about to be modified requires sync; busy check. */ regSync(letimer, syncbusy); #endif *repReg = value; } /***************************************************************************//** * @brief * Reset LETIMER to the same state that it was in after a hardware reset. * * @note * The ROUTE register is NOT reset by this function to allow for * a centralized setup of this feature. * * @param[in] letimer * A pointer to the LETIMER peripheral register block. ******************************************************************************/ void LETIMER_Reset(LETIMER_TypeDef *letimer) { #if defined(_LETIMER_FREEZE_MASK) /* Freeze registers to avoid stalling for LF synchronization. */ LETIMER_FreezeEnable(letimer, true); #endif /* Make sure disabled first, before resetting other registers. */ letimer->CMD = LETIMER_CMD_STOP | LETIMER_CMD_CLEAR | LETIMER_CMD_CTO0 | LETIMER_CMD_CTO1; letimer->CTRL = _LETIMER_CTRL_RESETVALUE; letimer->COMP0 = _LETIMER_COMP0_RESETVALUE; letimer->COMP1 = _LETIMER_COMP1_RESETVALUE; letimer->REP0 = _LETIMER_REP0_RESETVALUE; letimer->REP1 = _LETIMER_REP1_RESETVALUE; letimer->IEN = _LETIMER_IEN_RESETVALUE; LETIMER_IntClear(letimer, _LETIMER_IF_MASK); #if defined(_LETIMER_FREEZE_MASK) /* Unfreeze registers and pass new settings to LETIMER. */ LETIMER_FreezeEnable(letimer, false); #endif #if defined(_LETIMER_SYNCBUSY_MASK) while (LETIMER0->SYNCBUSY & _LETIMER_SYNCBUSY_MASK) { } #endif #if defined (LETIMER_EN_EN) letimer->EN_CLR = LETIMER_EN_EN; #endif } /***************************************************************************//** * @brief * Wait for the LETIMER to complete all synchronization of register changes * and commands. ******************************************************************************/ void LETIMER_SyncWait(LETIMER_TypeDef *letimer) { #if defined(_SILICON_LABS_32B_SERIES_2) while ((letimer->EN != 0U) && (letimer->SYNCBUSY != 0U)) { /* Wait for previous synchronization to finish */ } #else while (letimer->SYNCBUSY != 0U) { /* Wait for previous synchronization to finish */ } #endif } /***************************************************************************//** * @brief * Set the LETIMER top value. * * @note * The LETIMER is a down-counter, so when the counter reaches 0 then the top * value will be loaded into the counter. This function can be used to set * the top value. * * If the LETIMER is not already configured to use a top value then this * function will enable that functionality for the user. * * @param[in] letimer * A pointer to the LETIMER peripheral register block. * * @param[in] value * The top value. This can be a 16 bit value on series-0 and series-1 devices * and a 24 bit value on series-2 devices. ******************************************************************************/ void LETIMER_TopSet(LETIMER_TypeDef *letimer, uint32_t value) { LETIMER_SyncWait(letimer); #if defined(_LETIMER_TOP_MASK) /* Make sure TOP value is enabled. */ if ((letimer->CTRL & LETIMER_CTRL_CNTTOPEN) == 0U) { letimer->CTRL_SET = LETIMER_CTRL_CNTTOPEN; } letimer->TOP = value; #else /* Make sure TOP value is enabled. */ if ((letimer->CTRL & LETIMER_CTRL_COMP0TOP) == 0U) { letimer->CTRL |= LETIMER_CTRL_COMP0TOP; } LETIMER_CompareSet(letimer, 0, value); #endif } /** @} (end addtogroup LETIMER) */ /** @} (end addtogroup emlib) */ #endif /* defined(LETIMER_COUNT) && (LETIMER_COUNT > 0) */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/emlib/src/em_msc.c.
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/***************************************************************************//** * @file * @brief Flash controller (MSC) Peripheral API * @version 5.7.0 ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * SPDX-License-Identifier: Zlib * * The licensor of this software is Silicon Laboratories Inc. * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be * appreciated but is not required. * 2. Altered source versions must be plainly marked as such, and must not be * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * ******************************************************************************/ #include "em_msc.h" #if defined(MSC_COUNT) && (MSC_COUNT > 0) #include "em_system.h" #if defined(_MSC_TIMEBASE_MASK) #include "em_cmu.h" #endif #include "em_assert.h" #if defined(_SILICON_LABS_32B_SERIES_2) #include "em_common.h" #endif #if defined(_MSC_ECCCTRL_MASK) || defined(_SYSCFG_DMEM0ECCCTRL_MASK) #include "em_cmu.h" #include "em_core.h" #endif /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ #if defined(__ICCARM__) /* Suppress warnings originating from use of EFM_ASSERT() with IAR: EFM_ASSERT() is implemented as a local ramfunc */ #pragma diag_suppress=Ta022 #endif #if defined(EM_MSC_RUN_FROM_FLASH) && defined(_EFM32_GECKO_FAMILY) #error "Running Flash write/erase operations from Flash is not supported on EFM32G." #endif /******************************************************************************* ****************************** DEFINES ****************************** ******************************************************************************/ #if defined(MSC_WRITECTRL_WDOUBLE) #define WORDS_PER_DATA_PHASE (FLASH_SIZE < (512 * 1024) ? 1 : 2) #else #define WORDS_PER_DATA_PHASE (1) #endif #if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) /* Fix for errata FLASH_E201 - Potential program failure after Power On */ #define ERRATA_FIX_FLASH_E201_EN #endif #define FLASH_PAGE_MASK (~(FLASH_PAGE_SIZE - 1U)) #if defined(_MSC_ECCCTRL_MASK) || defined(_SYSCFG_DMEM0ECCCTRL_MASK) #if defined(_SILICON_LABS_32B_SERIES_1_CONFIG_1) /* On Series 1 Config 1 EFM32GG11, ECC is supported for RAM0 and RAM1 banks (not RAM2). It is necessary to figure out which is biggest to calculate the number of DMA descriptors needed. */ #define ECC_RAM_SIZE_MAX (SL_MAX(RAM0_MEM_SIZE, RAM1_MEM_SIZE)) #define ECC_RAM0_MEM_BASE (RAM0_MEM_BASE) #define ECC_RAM0_MEM_SIZE (RAM0_MEM_SIZE) #define ECC_RAM1_MEM_BASE (RAM1_MEM_BASE) #define ECC_RAM1_MEM_SIZE (RAM1_MEM_SIZE) #define ECC_CTRL_REG_ADDR (&MSC->ECCCTRL) #define ECC_RAM0_WRITE_EN (_MSC_ECCCTRL_RAMECCEWEN_SHIFT) #define ECC_RAM0_CHECK_EN (_MSC_ECCCTRL_RAMECCCHKEN_SHIFT) #define ECC_RAM1_WRITE_EN (_MSC_ECCCTRL_RAM1ECCEWEN_SHIFT) #define ECC_RAM1_CHECK_EN (_MSC_ECCCTRL_RAM1ECCCHKEN_SHIFT) #define ECC_IFC_REG_ADDR (&MSC->IFC) #define ECC_IFC_MASK (MSC_IFC_RAMERR1B | MSC_IFC_RAMERR2B \ | MSC_IFC_RAM1ERR1B | MSC_IFC_RAM1ERR2B) #elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_106) /* On Series 1 Config 2 EFM32GG12, ECC is supported for RAM0, RAM1 and RAM2 banks. All banks are of equal size. */ #define ECC_RAM_SIZE_MAX (RAM0_MEM_SIZE) #define ECC_RAM0_MEM_BASE (RAM0_MEM_BASE) #define ECC_RAM0_MEM_SIZE (RAM0_MEM_SIZE) #define ECC_RAM1_MEM_BASE (RAM1_MEM_BASE) #define ECC_RAM1_MEM_SIZE (RAM1_MEM_SIZE) #define ECC_RAM2_MEM_BASE (RAM2_MEM_BASE) #define ECC_RAM2_MEM_SIZE (RAM2_MEM_SIZE) #define ECC_CTRL_REG_ADDR (&MSC->ECCCTRL) #define ECC_RAM0_WRITE_EN (_MSC_ECCCTRL_RAMECCEWEN_SHIFT) #define ECC_RAM0_CHECK_EN (_MSC_ECCCTRL_RAMECCCHKEN_SHIFT) #define ECC_RAM1_WRITE_EN (_MSC_ECCCTRL_RAM1ECCEWEN_SHIFT) #define ECC_RAM1_CHECK_EN (_MSC_ECCCTRL_RAM1ECCCHKEN_SHIFT) #define ECC_RAM2_WRITE_EN (_MSC_ECCCTRL_RAM2ECCEWEN_SHIFT) #define ECC_RAM2_CHECK_EN (_MSC_ECCCTRL_RAM2ECCCHKEN_SHIFT) #define ECC_IFC_REG_ADDR (&MSC->IFC) #define ECC_IFC_MASK (MSC_IFC_RAMERR1B | MSC_IFC_RAMERR2B \ | MSC_IFC_RAM1ERR1B | MSC_IFC_RAM1ERR2B \ | MSC_IFC_RAM2ERR1B | MSC_IFC_RAM2ERR2B) #elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) /* On Series 2 Config 1, aka EFR32XG21, ECC is supported for the main DMEM RAM banks which is controlled with one ECC encoder/decoder. */ #define ECC_RAM_SIZE_MAX (RAM_MEM_SIZE) #define ECC_RAM0_MEM_BASE (RAM_MEM_BASE) #define ECC_RAM0_MEM_SIZE (RAM_MEM_SIZE) #define ECC_CTRL_REG_ADDR (&SYSCFG->DMEM0ECCCTRL) #define ECC_RAM0_WRITE_EN (_SYSCFG_DMEM0ECCCTRL_RAMECCEWEN_SHIFT) #define ECC_RAM0_CHECK_EN (_SYSCFG_DMEM0ECCCTRL_RAMECCCHKEN_SHIFT) #define ECC_IFC_REG_ADDR (&SYSCFG->IF_CLR) #define ECC_IFC_MASK (SYSCFG_IF_RAMERR1B | SYSCFG_IF_RAMERR2B) #else #error Unknown device. #endif #define ECC_DMA_MAX_XFERCNT (_LDMA_CH_CTRL_XFERCNT_MASK \ >> _LDMA_CH_CTRL_XFERCNT_SHIFT) #define ECC_DMA_DESC_SIZE ((ECC_DMA_MAX_XFERCNT + 1) * 4) /* 4 bytes units */ #define ECC_DMA_DESCS (ECC_RAM_SIZE_MAX / ECC_DMA_DESC_SIZE) #endif /* #if defined(_MSC_ECCCTRL_MASK) */ /***************************************************************************//** * @brief * Get locked status of the MSC registers. * * @detail * MSC_IS_LOCKED() is implemented as a macro because it's used inside functions * that can be placed either in flash or in RAM. ******************************************************************************/ #if defined(_MSC_STATUS_REGLOCK_MASK) #define MSC_IS_LOCKED() ((MSC->STATUS & _MSC_STATUS_REGLOCK_MASK) != 0U) #else #define MSC_IS_LOCKED() ((MSC->LOCK & _MSC_LOCK_MASK) != 0U) #endif /******************************************************************************* ****************************** TYPEDEFS ****************************** ******************************************************************************/ typedef enum { mscWriteIntSafe, mscWriteFast, } MSC_WriteStrategy_Typedef; #if defined(_MSC_ECCCTRL_MASK) || defined(_SYSCFG_DMEM0ECCCTRL_MASK) typedef struct { volatile uint32_t *ctrlReg; uint32_t writeEnBit; uint32_t checkEnBit; volatile uint32_t *ifClearReg; uint32_t ifClearMask; uint32_t base; uint32_t size; } MSC_EccBank_Typedef; #endif /******************************************************************************* ****************************** LOCALS ******************************* ******************************************************************************/ #if defined(_MSC_ECCCTRL_MASK) || defined(_SYSCFG_DMEM0ECCCTRL_MASK) static const MSC_EccBank_Typedef eccBank[MSC_ECC_BANKS] = { { ECC_CTRL_REG_ADDR, ECC_RAM0_WRITE_EN, ECC_RAM0_CHECK_EN, ECC_IFC_REG_ADDR, ECC_IFC_MASK, ECC_RAM0_MEM_BASE, ECC_RAM0_MEM_SIZE }, #if MSC_ECC_BANKS > 1 { ECC_CTRL_REG_ADDR, ECC_RAM1_WRITE_EN, ECC_RAM1_CHECK_EN, ECC_IFC_REG_ADDR, ECC_IFC_MASK, ECC_RAM1_MEM_BASE, ECC_RAM1_MEM_SIZE }, #if MSC_ECC_BANKS > 2 { ECC_CTRL_REG_ADDR, ECC_RAM2_WRITE_EN, ECC_RAM2_CHECK_EN, ECC_IFC_REG_ADDR, ECC_IFC_MASK, ECC_RAM2_MEM_BASE, ECC_RAM2_MEM_SIZE }, #endif #endif }; #endif /******************************************************************************* ****************************** FUNCTIONS ****************************** ******************************************************************************/ MSC_RAMFUNC_DECLARATOR MSC_Status_TypeDef MSC_WriteWordI(uint32_t *address, void const *data, uint32_t numBytes, MSC_WriteStrategy_Typedef writeStrategy); MSC_RAMFUNC_DECLARATOR MSC_Status_TypeDef MSC_LoadWriteData(uint32_t* data, uint32_t numWords, MSC_WriteStrategy_Typedef writeStrategy); MSC_RAMFUNC_DECLARATOR MSC_Status_TypeDef MSC_LoadVerifyAddress(uint32_t* address); #if !defined(EM_MSC_RUN_FROM_FLASH) MSC_RAMFUNC_DECLARATOR void mscRfAssertEFM(const char *file, int line); /***************************************************************************//** * @brief * Local ramfunc assertEFM. * * A local ramfunc version of assertEFM is needed because certain MSC functions * are allocated to RAM. The Flash may get erased and code normally located in * Flash must therefore have a RAM copy. * * This function is invoked through EFM_ASSERT() macro usage only and should * not be used explicitly. * * @param[in] file * The source file where assertion failed. * * @param[in] line * A line number in the source file where assertion failed. ******************************************************************************/ MSC_RAMFUNC_DEFINITION_BEGIN void mscRfAssertEFM(const char *file, int line) { (void)file; /* Unused parameter */ (void)line; /* Unused parameter */ while (true) { } } MSC_RAMFUNC_DEFINITION_END /* Undef the define from em_assert.h and redirect to a local ramfunc version. */ #undef EFM_ASSERT #if defined(DEBUG_EFM) || defined(DEBUG_EFM_USER) #define EFM_ASSERT(expr) ((expr) ? ((void)0) : mscRfAssertEFM(__FILE__, __LINE__)) #else #define EFM_ASSERT(expr) ((void)(expr)) #endif /* defined(DEBUG_EFM) || defined(DEBUG_EFM_USER) */ #endif /* !EM_MSC_RUN_FROM_FLASH */ /** @endcond */ /***************************************************************************//** * @addtogroup emlib * @{ ******************************************************************************/ /***************************************************************************//** * @addtogroup MSC * @{ ******************************************************************************/ /******************************************************************************* ************************** GLOBAL FUNCTIONS ******************************* ******************************************************************************/ #if defined(_SILICON_LABS_32B_SERIES_2) /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ /***************************************************************************//** * @brief * Wait for a specified MSC status or timeout. * * @param[in] mask * MSC->STATUS register mask to apply when testing for specified status. * @param[in] value * The value the MSC->STATUS test is waiting to see. * @return * Returns the status of a write or erase operation, @ref MSC_Status_TypeDef * @verbatim * mscReturnOk - Specified status criterium fulfilled. * mscReturnInvalidAddr - Operation tried to write or erase a non-flash area. * flashReturnLocked - MSC registers are locked or the operation tried to * write or erase a locked area of the flash. * flashReturnTimeOut - Operation timed out. * @endverbatim ******************************************************************************/ MSC_RAMFUNC_DEFINITION_BEGIN msc_Return_TypeDef mscStatusWait(uint32_t mask, uint32_t value) { uint32_t status; int timeOut = MSC_PROGRAM_TIMEOUT; while (timeOut > 0) { // Check if any error flags are set if ((status = MSC->STATUS) & (MSC_STATUS_LOCKED | MSC_STATUS_REGLOCK | MSC_STATUS_INVADDR)) { if (status & (MSC_STATUS_LOCKED | MSC_STATUS_REGLOCK)) { return mscReturnLocked; } return mscReturnInvalidAddr; } // Test exit criterium if ((status & mask) == value) { return mscReturnOk; } timeOut--; } return mscReturnTimeOut; } MSC_RAMFUNC_DEFINITION_END /***************************************************************************//** * @brief * Writes data to flash memory. It is assumed that start address is word * aligned and that numBytes is an integer multiple of four, and that the * write operation does not cross a flash page boundary. * * @param[in] address * Pointer to the flash word to write to. Must be aligned to words. * @param[in] data * Data to write to flash. * @param[in] numBytes * Number of bytes to write to flash. NB: Must be divisable by four. * @return * Returns the status of the write operation, @ref MSC_Status_TypeDef * @verbatim * flashReturnOk - Operation completed successfully. * flashReturnInvalidAddr - Operation tried to write to a non-flash area. * flashReturnLocked - MSC registers are locked or the operation tried to * program a locked area of the flash. * flashReturnTimeOut - Operation timed out. * @endverbatim ******************************************************************************/ MSC_RAMFUNC_DEFINITION_BEGIN msc_Return_TypeDef writeBurst(uint32_t address, const uint32_t *data, uint32_t numBytes) { msc_Return_TypeDef retVal; MSC->ADDRB = address; if (MSC->STATUS & MSC_STATUS_INVADDR) { return mscReturnInvalidAddr; } MSC->WDATA = *data++; numBytes -= 4; while (numBytes) { if ((retVal = mscStatusWait(MSC_STATUS_WDATAREADY, MSC_STATUS_WDATAREADY)) != mscReturnOk) { MSC->WRITECMD = MSC_WRITECMD_WRITEEND; return retVal; } MSC->WDATA = *data++; numBytes -= 4; } MSC->WRITECMD = MSC_WRITECMD_WRITEEND; if ((retVal = mscStatusWait((MSC_STATUS_BUSY | MSC_STATUS_PENDING), 0)) == mscReturnOk) { // We need to check twice to be sure retVal = mscStatusWait((MSC_STATUS_BUSY | MSC_STATUS_PENDING), 0); } return retVal; } MSC_RAMFUNC_DEFINITION_END /** @endcond */ /***************************************************************************//** * @brief * Initialize MSC module. Puts MSC hw in a known state. ******************************************************************************/ void MSC_Init(void) { // Unlock MSC MSC->LOCK = MSC_LOCK_LOCKKEY_UNLOCK; // Disable flash write MSC->WRITECTRL_CLR = MSC_WRITECTRL_WREN; } /***************************************************************************//** * @brief * Turn off MSC flash write enable and lock MSC registers. ******************************************************************************/ void MSC_Deinit(void) { // Unlock MSC MSC->LOCK = MSC_LOCK_LOCKKEY_UNLOCK; // Disable flash write MSC->WRITECTRL_CLR = MSC_WRITECTRL_WREN; // Lock MSC MSC->LOCK = MSC_LOCK_LOCKKEY_LOCK; } /***************************************************************************//** * @brief * Set MSC code execution configuration * * @param[in] execConfig * Code execution configuration ******************************************************************************/ void MSC_ExecConfigSet(MSC_ExecConfig_TypeDef *execConfig) { uint32_t mscReadCtrl; mscReadCtrl = MSC->READCTRL & ~MSC_READCTRL_DOUTBUFEN; if (execConfig->doutBufEn) { mscReadCtrl |= MSC_READCTRL_DOUTBUFEN; } MSC->READCTRL = mscReadCtrl; } /***************************************************************************//** * @brief * Erases a page in flash memory. * @note * It is recommended to run this code from RAM. * * For IAR, Rowley, SimplicityStudio, Atollic and armgcc this will be achieved * automatically by using attributes in the function proctype. For Keil * uVision you must define a section called "ram_code" and place this manually * in your project's scatter file. * * @param[in] startAddress * Pointer to the flash page to erase. Must be aligned to beginning of page * boundary. * @return * Returns the status of erase operation, @ref MSC_Status_TypeDef * @verbatim * mscReturnOk - Operation completed successfully. * mscReturnInvalidAddr - Operation tried to erase a non-flash area. * flashReturnLocked - MSC registers are locked or the operation tried to * erase a locked area of the flash. * flashReturnTimeOut - Operation timed out. * @endverbatim ******************************************************************************/ MSC_RAMFUNC_DEFINITION_BEGIN MSC_Status_TypeDef MSC_ErasePage(uint32_t *startAddress) { MSC_Status_TypeDef retVal; bool wasLocked; // Address must be aligned to page boundary EFM_ASSERT((((uint32_t)startAddress) & (FLASH_PAGE_SIZE - 1U)) == 0); wasLocked = MSC_IS_LOCKED(); MSC->LOCK = MSC_LOCK_LOCKKEY_UNLOCK; MSC->WRITECTRL_SET = MSC_WRITECTRL_WREN; MSC->ADDRB = (uint32_t)startAddress; MSC->WRITECMD = MSC_WRITECMD_ERASEPAGE; if ((retVal = mscStatusWait((MSC_STATUS_BUSY | MSC_STATUS_PENDING), 0)) == mscReturnOk) { // We need to check twice to be sure retVal = mscStatusWait((MSC_STATUS_BUSY | MSC_STATUS_PENDING), 0); } MSC->WRITECTRL_CLR = MSC_WRITECTRL_WREN; if (wasLocked) { MSC->LOCK = MSC_LOCK_LOCKKEY_LOCK; } return retVal; } MSC_RAMFUNC_DEFINITION_END /***************************************************************************//** * @brief * Writes data to flash memory. Write data must be aligned to words and * contain a number of bytes that is divisable by four. * @note * It is recommended to erase the flash page before performing a write. * * It is recommended to run this code from RAM. * * For IAR, Rowley, SimplicityStudio, Atollic and armgcc this will be achieved * automatically by using attributes in the function proctype. For Keil * uVision you must define a section called "ram_code" and place this manually * in your project's scatter file. * * @param[in] address * Pointer to the flash word to write to. Must be aligned to words. * @param[in] data * Data to write to flash. * @param[in] numBytes * Number of bytes to write to flash. NB: Must be divisable by four. * @return * Returns the status of the write operation, @ref MSC_Status_TypeDef * @verbatim * flashReturnOk - Operation completed successfully. * flashReturnInvalidAddr - Operation tried to write to a non-flash area. * flashReturnLocked - MSC registers are locked or the operation tried to * program a locked area of the flash. * flashReturnTimeOut - Operation timed out. * @endverbatim ******************************************************************************/ MSC_RAMFUNC_DEFINITION_BEGIN MSC_Status_TypeDef MSC_WriteWord(uint32_t *address, void const *data, uint32_t numBytes) { uint32_t addr; uint8_t *pData; uint32_t burstLen; MSC_Status_TypeDef retVal = mscReturnOk; bool wasLocked; // Check alignment (must be aligned to words) EFM_ASSERT(((uint32_t)address & 0x3U) == 0); // Check number of bytes, must be divisable by four EFM_ASSERT((numBytes & 0x3U) == 0); wasLocked = MSC_IS_LOCKED(); MSC->LOCK = MSC_LOCK_LOCKKEY_UNLOCK; // Enable flash write MSC->WRITECTRL_SET = MSC_WRITECTRL_WREN; addr = (uint32_t)address; pData = (uint8_t*)data; while (numBytes) { // Max burst length is up to next flash page boundary burstLen = SL_MIN(numBytes, ((addr + FLASH_PAGE_SIZE) & FLASH_PAGE_MASK) - addr); if ((retVal = writeBurst(addr, (const uint32_t*)pData, burstLen)) != mscReturnOk) { break; } addr += burstLen; pData += burstLen; numBytes -= burstLen; } // Disable flash write MSC->WRITECTRL_CLR = MSC_WRITECTRL_WREN; if (wasLocked) { MSC->LOCK = MSC_LOCK_LOCKKEY_LOCK; } return retVal; } MSC_RAMFUNC_DEFINITION_END #if 0 // Masserase is only possible from SE, code kept for doc. purposes MSC_RAMFUNC_DEFINITION_BEGIN MSC_Status_TypeDef MSC_MassErase(void) { MSC_Status_TypeDef retVal; if (MSC_IS_LOCKED()) { return mscReturnLocked; } MSC->WRITECTRL_SET = MSC_WRITECTRL_WREN; // NOTE: Only SE can clear MELOCKBIT, so this function does not really work... MSC->MISCLOCKWORD_CLR = MSC_MISCLOCKWORD_MELOCKBIT; MSC->WRITECMD = MSC_WRITECMD_ERASEMAIN0; retVal = mscStatusWait(MSC_STATUS_BUSY, 0); MSC->MISCLOCKWORD_SET = MSC_MISCLOCKWORD_MELOCKBIT; MSC->WRITECTRL_CLR = MSC_MSC_WRITECTRL_WREN; return retVal; } MSC_RAMFUNC_DEFINITION_END #endif #else // defined(_SILICON_LABS_32B_SERIES_2) /***************************************************************************//** * @brief * Enables the flash controller for writing. * @note * This function must be called before flash operations when * AUXHFRCO clock has been changed from a default band. ******************************************************************************/ void MSC_Init(void) { #if defined(_MSC_TIMEBASE_MASK) uint32_t freq, cycles; #endif #if defined(_EMU_STATUS_VSCALE_MASK) /* VSCALE must be done. Flash erase and write requires VSCALE2. */ EFM_ASSERT(!(EMU->STATUS & _EMU_STATUS_VSCALEBUSY_MASK)); EFM_ASSERT((EMU->STATUS & _EMU_STATUS_VSCALE_MASK) == EMU_STATUS_VSCALE_VSCALE2); #endif /* Unlock the MSC module. */ MSC->LOCK = MSC_UNLOCK_CODE; /* Disable writing to the Flash. */ MSC->WRITECTRL &= ~MSC_WRITECTRL_WREN; #if defined(_MSC_TIMEBASE_MASK) /* Configure MSC->TIMEBASE according to a selected frequency. */ freq = CMU_ClockFreqGet(cmuClock_AUX); /* Timebase 5us is used for the 1/1.2 MHz band only. Note that the 1 MHz band is tuned to 1.2 MHz on newer revisions. */ if (freq > 1200000) { /* Calculate a number of clock cycles for 1 us as a base period. */ freq = (freq * 11) / 10; cycles = (freq / 1000000) + 1; /* Configure clock cycles for flash timing. */ MSC->TIMEBASE = (MSC->TIMEBASE & ~(_MSC_TIMEBASE_BASE_MASK | _MSC_TIMEBASE_PERIOD_MASK)) | MSC_TIMEBASE_PERIOD_1US | (cycles << _MSC_TIMEBASE_BASE_SHIFT); } else { /* Calculate a number of clock cycles for 5 us as a base period. */ freq = (freq * 5 * 11) / 10; cycles = (freq / 1000000) + 1; /* Configure clock cycles for flash timing */ MSC->TIMEBASE = (MSC->TIMEBASE & ~(_MSC_TIMEBASE_BASE_MASK | _MSC_TIMEBASE_PERIOD_MASK)) | MSC_TIMEBASE_PERIOD_5US | (cycles << _MSC_TIMEBASE_BASE_SHIFT); } #endif } /***************************************************************************//** * @brief * Disables the flash controller for writing. ******************************************************************************/ void MSC_Deinit(void) { /* Disable writing to the Flash. */ MSC->WRITECTRL &= ~MSC_WRITECTRL_WREN; /* Lock the MSC module.*/ MSC->LOCK = 0; } /***************************************************************************//** * @brief * Set the MSC code execution configuration. * * @param[in] execConfig * The code execution configuration. ******************************************************************************/ void MSC_ExecConfigSet(MSC_ExecConfig_TypeDef *execConfig) { uint32_t mscReadCtrl; #if defined(MSC_READCTRL_MODE_WS0SCBTP) mscReadCtrl = MSC->READCTRL & _MSC_READCTRL_MODE_MASK; if ((mscReadCtrl == MSC_READCTRL_MODE_WS0) && (execConfig->scbtEn)) { mscReadCtrl |= MSC_READCTRL_MODE_WS0SCBTP; } else if ((mscReadCtrl == MSC_READCTRL_MODE_WS1) && (execConfig->scbtEn)) { mscReadCtrl |= MSC_READCTRL_MODE_WS1SCBTP; } else if ((mscReadCtrl == MSC_READCTRL_MODE_WS0SCBTP) && (!execConfig->scbtEn)) { mscReadCtrl |= MSC_READCTRL_MODE_WS0; } else if ((mscReadCtrl == MSC_READCTRL_MODE_WS1SCBTP) && (!execConfig->scbtEn)) { mscReadCtrl |= MSC_READCTRL_MODE_WS1; } else { /* No change needed. */ } #endif mscReadCtrl = MSC->READCTRL & ~(0 #if defined(MSC_READCTRL_SCBTP) | MSC_READCTRL_SCBTP #endif #if defined(MSC_READCTRL_USEHPROT) | MSC_READCTRL_USEHPROT #endif #if defined(MSC_READCTRL_PREFETCH) | MSC_READCTRL_PREFETCH #endif #if defined(MSC_READCTRL_ICCDIS) | MSC_READCTRL_ICCDIS #endif #if defined(MSC_READCTRL_AIDIS) | MSC_READCTRL_AIDIS #endif #if defined(MSC_READCTRL_IFCDIS) | MSC_READCTRL_IFCDIS #endif ); mscReadCtrl |= (0 #if defined(MSC_READCTRL_SCBTP) | (execConfig->scbtEn ? MSC_READCTRL_SCBTP : 0) #endif #if defined(MSC_READCTRL_USEHPROT) | (execConfig->useHprot ? MSC_READCTRL_USEHPROT : 0) #endif #if defined(MSC_READCTRL_PREFETCH) | (execConfig->prefetchEn ? MSC_READCTRL_PREFETCH : 0) #endif #if defined(MSC_READCTRL_ICCDIS) | (execConfig->iccDis ? MSC_READCTRL_ICCDIS : 0) #endif #if defined(MSC_READCTRL_AIDIS) | (execConfig->aiDis ? MSC_READCTRL_AIDIS : 0) #endif #if defined(MSC_READCTRL_IFCDIS) | (execConfig->ifcDis ? MSC_READCTRL_IFCDIS : 0) #endif ); MSC->READCTRL = mscReadCtrl; } /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ /***************************************************************************//** * @brief * Perform the address phase of the flash write cycle. * @details * This function performs the address phase of a flash write operation by * writing the given flash address to the ADDRB register and issuing the * LADDRIM command to load the address. * @param[in] address * An address in flash memory. Must be aligned at a 4 byte boundary. * @return * Returns the status of the address load operation, #MSC_Status_TypeDef * @verbatim * mscReturnOk - The operation completed successfully. * mscReturnInvalidAddr - The operation tried to erase a non-flash area. * mscReturnLocked - The operation tried to erase a locked area of the Flash. * @endverbatim ******************************************************************************/ MSC_RAMFUNC_DEFINITION_BEGIN MSC_Status_TypeDef MSC_LoadVerifyAddress(uint32_t* address) { uint32_t timeOut; /* Wait for the MSC to become ready. */ timeOut = MSC_PROGRAM_TIMEOUT; while ((MSC->STATUS & MSC_STATUS_BUSY) && (timeOut != 0)) { timeOut--; } /* Check for timeout. */ if (timeOut == 0) { return mscReturnTimeOut; } /* Load the address. */ MSC->ADDRB = (uint32_t)address; MSC->WRITECMD = MSC_WRITECMD_LADDRIM; /* Check for an invalid address. */ if (MSC->STATUS & MSC_STATUS_INVADDR) { return mscReturnInvalidAddr; } return mscReturnOk; } MSC_RAMFUNC_DEFINITION_END /***************************************************************************//** * @brief * Perform a flash data write phase. * @details * This function performs the data phase of a flash write operation by loading * the given number of 32-bit words to the WDATA register. * @param[in] data * A pointer to the first data word to load. * @param[in] numWords * A number of data words (32-bit) to load. * @param[in] writeStrategy * A write strategy to apply. * @return * Returns the status of the data load operation. * @verbatim * mscReturnOk - An operation completed successfully. * mscReturnTimeOut - An operation timed out waiting for the flash operation * to complete. * @endverbatim ******************************************************************************/ MSC_RAMFUNC_DEFINITION_BEGIN MSC_Status_TypeDef MSC_LoadWriteData(uint32_t* data, uint32_t numWords, MSC_WriteStrategy_Typedef writeStrategy) { uint32_t timeOut; uint32_t wordIndex; bool useWDouble = false; MSC_Status_TypeDef retval = mscReturnOk; #if !defined(_EFM32_GECKO_FAMILY) uint32_t irqState; #endif #if defined(_MSC_WRITECTRL_LPWRITE_MASK) && defined(_MSC_WRITECTRL_WDOUBLE_MASK) /* If the LPWRITE (Low Power Write) is NOT enabled, set WDOUBLE (Write Double word). */ if (!(MSC->WRITECTRL & MSC_WRITECTRL_LPWRITE)) { #if defined(_SILICON_LABS_32B_SERIES_0) /* If the number of words to be written is odd, align by writing a single word first, before setting the WDOUBLE bit. */ if (numWords & 0x1) { /* Wait for the MSC to become ready for the next word. */ timeOut = MSC_PROGRAM_TIMEOUT; while ((!(MSC->STATUS & MSC_STATUS_WDATAREADY)) && (timeOut != 0)) { timeOut--; } /* Check for timeout. */ if (timeOut == 0) { return mscReturnTimeOut; } /* Clear the double word option to write the initial single word. */ MSC->WRITECTRL &= ~MSC_WRITECTRL_WDOUBLE; /* Write first data word. */ MSC->WDATA = *data++; MSC->WRITECMD = MSC_WRITECMD_WRITEONCE; /* Wait for the operation to finish. It may be required to change the WDOUBLE configuration after the initial write. It should not be changed while BUSY. */ timeOut = MSC_PROGRAM_TIMEOUT; while ((MSC->STATUS & MSC_STATUS_BUSY) && (timeOut != 0)) { timeOut--; } /* Check for timeout. */ if (timeOut == 0) { return mscReturnTimeOut; } /* Check for a write protected flash area. */ if (MSC->STATUS & MSC_STATUS_LOCKED) { return mscReturnLocked; } /* Subtract this initial odd word for the write loop below. */ numWords -= 1; retval = mscReturnOk; } /* Set the double word option to write two words per data phase. */ #endif MSC->WRITECTRL |= MSC_WRITECTRL_WDOUBLE; useWDouble = true; } #endif /* defined( _MSC_WRITECTRL_LPWRITE_MASK ) && defined( _MSC_WRITECTRL_WDOUBLE_MASK ) */ /* Write the rest as a double word write if wordsPerDataPhase == 2 */ if (numWords > 0) { /**** Write strategy: mscWriteIntSafe ****/ if (writeStrategy == mscWriteIntSafe) { /* Requires a system core clock at 1MHz or higher */ EFM_ASSERT(SystemCoreClock >= 1000000); wordIndex = 0; while (wordIndex < numWords) { if (!useWDouble) { MSC->WDATA = *data++; wordIndex++; MSC->WRITECMD = MSC_WRITECMD_WRITEONCE; } else { // useWDouble == true /* Trigger a double write according to flash properties. */ #if defined(_SILICON_LABS_32B_SERIES_0) && defined(_MSC_WRITECTRL_WDOUBLE_MASK) MSC->WDATA = *data++; while (!(MSC->STATUS & MSC_STATUS_WDATAREADY)) ; MSC->WDATA = *data++; wordIndex += 2; MSC->WRITECMD = MSC_WRITECMD_WRITEONCE; #elif defined(_SILICON_LABS_32B_SERIES_1) && defined(_MSC_WRITECTRL_WDOUBLE_MASK) while (!(MSC->STATUS & MSC_STATUS_WDATAREADY)) ; do { MSC->WDATA = *data++; wordIndex++; } while ((MSC->STATUS & MSC_STATUS_WDATAREADY) && (wordIndex < numWords)); MSC->WRITECMD = MSC_WRITECMD_WRITETRIG; #endif } /* Wait for the transaction to finish. */ timeOut = MSC_PROGRAM_TIMEOUT; while ((MSC->STATUS & MSC_STATUS_BUSY) && (timeOut != 0)) { timeOut--; } /* Check for a timeout. */ if (timeOut == 0) { retval = mscReturnTimeOut; break; } /* Check for a write protected flash area. */ if (MSC->STATUS & MSC_STATUS_LOCKED) { retval = mscReturnLocked; break; } #if defined(_EFM32_GECKO_FAMILY) MSC->ADDRB += 4; MSC->WRITECMD = MSC_WRITECMD_LADDRIM; #endif } } /**** Write strategy: mscWriteFast ****/ else { #if defined(_EFM32_GECKO_FAMILY) /* Gecko does not have auto-increment of ADDR. */ EFM_ASSERT(false); #else /* Requires a system core clock at 14 MHz or higher. */ EFM_ASSERT(SystemCoreClock >= 14000000); /* * Protect from interrupts to be sure to satisfy the us timing * needs of the MSC flash programming state machine. */ irqState = __get_PRIMASK(); __disable_irq(); wordIndex = 0; while (wordIndex < numWords) { /* Wait for the MSC to be ready for the next word. */ while (!(MSC->STATUS & MSC_STATUS_WDATAREADY)) { /* If the write to MSC->WDATA below missed the 30 us timeout and the following MSC_WRITECMD_WRITETRIG command arrived while MSC_STATUS_BUSY is 1, the MSC_WRITECMD_WRITETRIG could be ignored by the MSC. In this case, MSC_STATUS_WORDTIMEOUT is set to 1 and MSC_STATUS_BUSY is 0. A new trigger is therefore needed to complete write of data in MSC->WDATA. If WDATAREADY became high since entering the loop, exit and continue to the next WDATA write. */ if ((MSC->STATUS & (MSC_STATUS_WORDTIMEOUT | MSC_STATUS_BUSY | MSC_STATUS_WDATAREADY)) == MSC_STATUS_WORDTIMEOUT) { MSC->WRITECMD = MSC_WRITECMD_WRITETRIG; } } if (!useWDouble) { MSC->WDATA = *data; MSC->WRITECMD = MSC_WRITECMD_WRITETRIG; data++; wordIndex++; } else { // useWDouble == true /* Trigger double write according to flash properties. */ #if defined(_SILICON_LABS_32B_SERIES_0) MSC->WDATA = *data; if (wordIndex & 0x1) { MSC->WRITECMD = MSC_WRITECMD_WRITETRIG; } data++; wordIndex++; #elif (_SILICON_LABS_32B_SERIES_1_CONFIG >= 2) do { MSC->WDATA = *data++; wordIndex++; } while ((MSC->STATUS & MSC_STATUS_WDATAREADY) && (wordIndex < numWords)); MSC->WRITECMD = MSC_WRITECMD_WRITETRIG; #endif } } // End of: while (wordIndex < numWords) { if (irqState == 0) { /* Restore the previous interrupt state. */ __enable_irq(); } /* Wait for the transaction to finish. */ timeOut = MSC_PROGRAM_TIMEOUT; while ((MSC->STATUS & MSC_STATUS_BUSY) && (timeOut != 0)) { timeOut--; } /* Check for a timeout. */ if (timeOut == 0) { retval = mscReturnTimeOut; } /* Check for a write protected flash area. */ if (MSC->STATUS & MSC_STATUS_LOCKED) { retval = mscReturnLocked; } #endif } /* writeStrategy */ } #if defined(_MSC_WRITECTRL_WDOUBLE_MASK) /* Clear a double word option, which should not be left on when returning. */ MSC->WRITECTRL &= ~MSC_WRITECTRL_WDOUBLE; #endif return retval; } MSC_RAMFUNC_DEFINITION_END /***************************************************************************//** * @brief * An internal flash write function with the select write strategy parameter. * @param[in] address * A write address. * @param[in] data * A pointer to the first data word to load. * @param[in] numBytes * A nsumber of data bytes to load, which must be a multiple of 4 bytes. * @param[in] writeStrategy * A wWrite strategy to apply. * @return * Returns the status of the data load operation. ******************************************************************************/ MSC_RAMFUNC_DEFINITION_BEGIN MSC_Status_TypeDef MSC_WriteWordI(uint32_t *address, void const *data, uint32_t numBytes, MSC_WriteStrategy_Typedef writeStrategy) { uint32_t wordCount; uint32_t numWords; uint32_t pageWords; uint32_t* pData; bool wasLocked; MSC_Status_TypeDef retval = mscReturnOk; wasLocked = MSC_IS_LOCKED(); MSC->LOCK = MSC_LOCK_LOCKKEY_UNLOCK; /* Check alignment (must be aligned to words). */ EFM_ASSERT(((uint32_t) address & 0x3) == 0); /* Check a number of bytes. Must be divisible by four. */ EFM_ASSERT((numBytes & 0x3) == 0); #if defined(_EMU_STATUS_VSCALE_MASK) /* VSCALE must be done and flash write requires VSCALE2. */ EFM_ASSERT(!(EMU->STATUS & _EMU_STATUS_VSCALEBUSY_MASK)); EFM_ASSERT((EMU->STATUS & _EMU_STATUS_VSCALE_MASK) == EMU_STATUS_VSCALE_VSCALE2); #endif /* Enable writing to the MSC module. */ MSC->WRITECTRL |= MSC_WRITECTRL_WREN; /* Convert bytes to words. */ numWords = numBytes >> 2; EFM_ASSERT(numWords > 0); /* The following loop splits the data into chunks corresponding to flash pages. The address is loaded only once per page because the hardware automatically increments the address internally for each data load inside a page. */ for (wordCount = 0, pData = (uint32_t *)data; wordCount < numWords; ) { /* First, the address is loaded. The address is auto-incremented within a page. Therefore, the address phase is only needed once for each page. */ retval = MSC_LoadVerifyAddress(address + wordCount); if (mscReturnOk != retval) { /* Disable writing to the MSC module. */ MSC->WRITECTRL &= ~MSC_WRITECTRL_WREN; if (wasLocked) { MSC->LOCK = MSC_LOCK_LOCKKEY_LOCK; } return retval; } /* Compute the number of words to write to the current page. */ pageWords = (FLASH_PAGE_SIZE - (((uint32_t) (address + wordCount)) & (FLASH_PAGE_SIZE - 1))) / sizeof(uint32_t); if (pageWords > numWords - wordCount) { pageWords = numWords - wordCount; } /* Write the data in the current page. */ retval = MSC_LoadWriteData(pData, pageWords, writeStrategy); if (mscReturnOk != retval) { break; } wordCount += pageWords; pData += pageWords; } #if defined(ERRATA_FIX_FLASH_E201_EN) /* Fix for errata FLASH_E201 - Potential program failure after Power On. * * Check if the first word was programmed correctly. If a failure is detected, * retry programming of the first word. * * A full description of the errata is in the errata document. */ pData = (uint32_t *) data; if (*address != *pData) { retval = MSC_LoadVerifyAddress(address); if (mscReturnOk == retval) { retval = MSC_LoadWriteData(pData, 1, writeStrategy); } } #endif /* Disable writing to the MSC module. */ MSC->WRITECTRL &= ~MSC_WRITECTRL_WREN; #if defined(_MSC_WRITECTRL_WDOUBLE_MASK) #if (WORDS_PER_DATA_PHASE == 2) /* Turn off the double word write cycle support. */ MSC->WRITECTRL &= ~MSC_WRITECTRL_WDOUBLE; #endif #endif if (wasLocked) { MSC->LOCK = MSC_LOCK_LOCKKEY_LOCK; } return retval; } MSC_RAMFUNC_DEFINITION_END /** @endcond */ /***************************************************************************//** * @brief * Erases a page in flash memory. * @note * It is recommended to run this code from RAM. On the Gecko family, it is required * to run this function from RAM. * * For IAR IDE, Rowley IDE, SimplicityStudio IDE, Atollic IDE, and ARM GCC IDE, this is * achieved automatically by using attributes in the function proctype. For Keil * uVision IDE, define a section called "ram_code" and place this manually in * the project's scatter file. * * @param[in] startAddress * A pointer to the flash page to erase. Must be aligned to the beginning of the page * boundary. * @return * Returns the status of erase operation, #MSC_Status_TypeDef * @verbatim * mscReturnOk - The operation completed successfully. * mscReturnInvalidAddr - The operation tried to erase a non-flash area. * mscReturnLocked - The operation tried to erase a locked area of the flash. * mscReturnTimeOut - The operation timed out waiting for the flash operation * to complete. * @endverbatim ******************************************************************************/ MSC_RAMFUNC_DEFINITION_BEGIN MSC_Status_TypeDef MSC_ErasePage(uint32_t *startAddress) { uint32_t timeOut = MSC_PROGRAM_TIMEOUT; bool wasLocked; wasLocked = MSC_IS_LOCKED(); MSC->LOCK = MSC_LOCK_LOCKKEY_UNLOCK; /* An address must be aligned to pages. */ EFM_ASSERT((((uint32_t) startAddress) & (FLASH_PAGE_SIZE - 1)) == 0); #if defined(_EMU_STATUS_VSCALE_MASK) /* VSCALE must be done and flash erase requires VSCALE2. */ EFM_ASSERT(!(EMU->STATUS & _EMU_STATUS_VSCALEBUSY_MASK)); EFM_ASSERT((EMU->STATUS & _EMU_STATUS_VSCALE_MASK) == EMU_STATUS_VSCALE_VSCALE2); #endif /* Enable writing to the MSC module. */ MSC->WRITECTRL |= MSC_WRITECTRL_WREN; /* Load an address. */ MSC->ADDRB = (uint32_t)startAddress; MSC->WRITECMD = MSC_WRITECMD_LADDRIM; /* Check for an invalid address. */ if (MSC->STATUS & MSC_STATUS_INVADDR) { /* Disable writing to the MSC module. */ MSC->WRITECTRL &= ~MSC_WRITECTRL_WREN; if (wasLocked) { MSC->LOCK = MSC_LOCK_LOCKKEY_LOCK; } return mscReturnInvalidAddr; } /* Send erase page command. */ MSC->WRITECMD = MSC_WRITECMD_ERASEPAGE; /* Wait for the erase to complete. */ while ((MSC->STATUS & MSC_STATUS_BUSY) && (timeOut != 0)) { timeOut--; } /* Check for write protected page. */ if (MSC->STATUS & MSC_STATUS_LOCKED) { /* Disable writing to the MSC module. */ MSC->WRITECTRL &= ~MSC_WRITECTRL_WREN; if (wasLocked) { MSC->LOCK = MSC_LOCK_LOCKKEY_LOCK; } return mscReturnLocked; } if (timeOut == 0) { /* Disable writing to the MSC module. */ MSC->WRITECTRL &= ~MSC_WRITECTRL_WREN; if (wasLocked) { MSC->LOCK = MSC_LOCK_LOCKKEY_LOCK; } return mscReturnTimeOut; } /* Disable writing to the MSC module. */ MSC->WRITECTRL &= ~MSC_WRITECTRL_WREN; if (wasLocked) { MSC->LOCK = MSC_LOCK_LOCKKEY_LOCK; } return mscReturnOk; } MSC_RAMFUNC_DEFINITION_END /***************************************************************************//** * @brief * Writes data to flash memory. This function is interrupt-safe, but slower than * MSC_WriteWordFast(), which writes to flash with interrupts disabled. * Write data must be aligned to words and contain a number of bytes that is * divisible by four. * @note * It is recommended to erase the flash page before performing a write. * * It is recommended to run this code from RAM. On the Gecko family, it is required * to run this function from RAM. * * For IAR IDE, Rowley IDE, SimplicityStudio IDE, Atollic IDE, and ARM GCC IDE, * this is done automatically by using attributes in the function proctype. * For Keil uVision IDE, define a section called "ram_code" and place it * manually in the project's scatter file. * * This function requires a system core clock at 1 MHz or higher. * * @param[in] address * A pointer to the flash word to write to. Must be aligned to words. * @param[in] data * Data to write to flash. * @param[in] numBytes * A number of bytes to write from flash. NB: Must be divisible by four. * @return * Returns the status of the write operation. * @verbatim * flashReturnOk - The operation completed successfully. * flashReturnInvalidAddr - The operation tried to erase a non-flash area. * flashReturnLocked - The operation tried to erase a locked area of the Flash. * flashReturnTimeOut - The operation timed out waiting for the flash operation * to complete, or the MSC module timed out waiting for the software to write * the next word into the DWORD register. * @endverbatim ******************************************************************************/ MSC_RAMFUNC_DEFINITION_BEGIN MSC_Status_TypeDef MSC_WriteWord(uint32_t *address, void const *data, uint32_t numBytes) { return MSC_WriteWordI(address, data, numBytes, mscWriteIntSafe); } MSC_RAMFUNC_DEFINITION_END #if !defined(_EFM32_GECKO_FAMILY) /***************************************************************************//** * @brief * Writes data to flash memory. This function is faster than MSC_WriteWord(), * but it disables interrupts. Write data must be aligned to words and contain * a number of bytes that is divisible by four. * @note * It is recommended to erase the flash page before performing a write. * It is required to run this function from RAM on parts that include a * flash write buffer. * * For IAR IDE, Rowley IDE, SimplicityStudio IDE, Atollic IDE, and ARM GCC IDE, * this is done automatically by using attributes in the function proctype. * For Keil uVision IDE, define a section called "ram_code" and place this manually * in the project's scatter file. * * @param[in] address * A pointer to the flash word to write to. Must be aligned to words. * @param[in] data * Data to write to flash. * @param[in] numBytes * A number of bytes to write from the Flash. NB: Must be divisible by four. * @return * Returns the status of the write operation. * @verbatim * flashReturnOk - The operation completed successfully. * flashReturnInvalidAddr - The operation tried to erase a non-flash area. * flashReturnLocked - The operation tried to erase a locked area of the flash. * flashReturnTimeOut - The operation timed out waiting for flash operation * to complete. Or the MSC timed out waiting for the software to write * the next word into the DWORD register. * @endverbatim ******************************************************************************/ #if !defined (EM_MSC_RUN_FROM_FLASH) || (_SILICON_LABS_GECKO_INTERNAL_SDID < 84) MSC_RAMFUNC_DEFINITION_BEGIN MSC_Status_TypeDef MSC_WriteWordFast(uint32_t *address, void const *data, uint32_t numBytes) { return MSC_WriteWordI(address, data, numBytes, mscWriteFast); } MSC_RAMFUNC_DEFINITION_END #endif // !defined (EM_MSC_RUN_FROM_FLASH) || (_SILICON_LABS_GECKO_INTERNAL_SDID < 84) #endif // !defined(_EFM32_GECKO_FAMILY) #if defined(_MSC_MASSLOCK_MASK) /***************************************************************************//** * @brief * Erase the entire Flash in one operation. * * @note * This command will erase the entire contents of the device. * Use with care, both a debug session and all contents of the flash will be * lost. The lock bit, MLW will prevent this operation from executing and * might prevent a successful mass erase. ******************************************************************************/ MSC_RAMFUNC_DEFINITION_BEGIN MSC_Status_TypeDef MSC_MassErase(void) { bool wasLocked; wasLocked = MSC_IS_LOCKED(); MSC->LOCK = MSC_LOCK_LOCKKEY_UNLOCK; /* Enable writing to the MSC module. */ MSC->WRITECTRL |= MSC_WRITECTRL_WREN; /* Unlock the device mass erase. */ MSC->MASSLOCK = MSC_MASSLOCK_LOCKKEY_UNLOCK; /* Erase the first 512 K block. */ MSC->WRITECMD = MSC_WRITECMD_ERASEMAIN0; /* Waiting for erase to complete. */ while ((MSC->STATUS & MSC_STATUS_BUSY) != 0U) { } #if ((FLASH_SIZE >= (512 * 1024)) && defined(_MSC_WRITECMD_ERASEMAIN1_MASK)) /* Erase the second 512 K block. */ MSC->WRITECMD = MSC_WRITECMD_ERASEMAIN1; /* Waiting for erase to complete. */ while ((MSC->STATUS & MSC_STATUS_BUSY) != 0U) { } #endif /* Restore the mass erase lock. */ MSC->MASSLOCK = MSC_MASSLOCK_LOCKKEY_LOCK; /* Disable writing to the MSC module. */ MSC->WRITECTRL &= ~MSC_WRITECTRL_WREN; if (wasLocked) { MSC->LOCK = MSC_LOCK_LOCKKEY_LOCK; } /* This will only successfully return if calling function is also in SRAM. */ return mscReturnOk; } MSC_RAMFUNC_DEFINITION_END #endif // defined(_MSC_MASSLOCK_MASK) #endif // defined(_SILICON_LABS_32B_SERIES_2) #if defined(_MSC_ECCCTRL_MASK) || defined(_SYSCFG_DMEM0ECCCTRL_MASK) /***************************************************************************//** * @brief * DMA read and write existing values (for ECC initializaion). * * @details * This function uses DMA to read and write the existing data values in * the RAM region specified by start and size. The function will use the * 2 DMA channels specified by the channels[2] array. * * @param[in] start * Start address of address range in RAM to read/write. * * @param[in] size * Size of address range in RAM to read/write. * * @param[in] channels[2] * Array of 2 DMA channels to use. ******************************************************************************/ static void mscEccReadWriteExistingDma(uint32_t start, uint32_t size, uint32_t channels[2]) { uint32_t descCnt = 0; volatile uint32_t dmaDesc[ECC_DMA_DESCS][4]; uint32_t chMask = (1 << channels[0]) | (1 << channels[1]); /* Assert that the 2 DMA channel numbers are different. */ EFM_ASSERT(channels[0] != channels[1]); /* Make sure ECC_RAM_SIZE_MAX is a multiple of ECC_DMA_DESC_SIZE in order to match the total xfer size of the descriptor chain with the largest ECC RAM bank. */ EFM_ASSERT((ECC_RAM_SIZE_MAX % ECC_DMA_DESC_SIZE) == 0); /* Initialize LDMA descriptor chain. */ do { dmaDesc[descCnt][0] = /* DMA desc CTRL word */ LDMA_CH_CTRL_STRUCTTYPE_TRANSFER | LDMA_CH_CTRL_STRUCTREQ | _LDMA_CH_CTRL_XFERCNT_MASK | LDMA_CH_CTRL_BLOCKSIZE_ALL | LDMA_CH_CTRL_REQMODE_ALL | LDMA_CH_CTRL_SRCINC_ONE | LDMA_CH_CTRL_SIZE_WORD | LDMA_CH_CTRL_DSTINC_ONE; /* source and destination address */ dmaDesc[descCnt][1] = start; dmaDesc[descCnt][2] = start; /* link to next descriptor */ dmaDesc[descCnt][3] = LDMA_CH_LINK_LINK | (((uint32_t) &dmaDesc[descCnt + 1][0]) & _LDMA_CH_LINK_LINKADDR_MASK); start += ECC_DMA_DESC_SIZE; size -= ECC_DMA_DESC_SIZE; descCnt++; } while (size); /* Now, divide the descriptor list in two parts, one for each channel, by setting the link bit and address 0 of the descriptor in the middle to 0. */ dmaDesc[(descCnt / 2) - 1][3] = 0; /* Set last descriptor link bit and address to 0. */ dmaDesc[descCnt - 1][3] = 0; #if !defined(_SILICON_LABS_32B_SERIES_2) /* Start the LDMA clock now */ CMU_ClockEnable(cmuClock_LDMA, true); #endif /* Round robin scheduling for all channels (0 = no fixed priority channels). */ LDMA->CTRL = 0 << _LDMA_CTRL_NUMFIXED_SHIFT; #if defined(LDMA_EN_EN) LDMA->EN = LDMA_EN_EN; #endif LDMA->CHEN = 0; LDMA->DBGHALT = 0; LDMA->REQDIS = 0; /* Disable LDMA interrupts, and clear interrupt status. */ LDMA->IEN = 0; #if defined (LDMA_HAS_SET_CLEAR) LDMA->IF_CLR = chMask; #else LDMA->IFC = chMask; #endif /* Disable looping */ LDMA->CH[channels[0]].LOOP = 0; LDMA->CH[channels[1]].LOOP = 0; /* Set descriptor address for first channel. */ LDMA->CH[channels[0]].LINK = ((uint32_t)&dmaDesc[0][0]) & _LDMA_CH_LINK_LINKADDR_MASK; /* Set descriptor address for second channel. */ LDMA->CH[channels[1]].LINK = ((uint32_t)&dmaDesc[descCnt / 2][0]) & _LDMA_CH_LINK_LINKADDR_MASK; /* Clear the channel done flags. */ BUS_RegMaskedClear(&LDMA->CHDONE, chMask); /* Start transfer by loading descriptors. */ LDMA->LINKLOAD = chMask; /* Wait until finished. */ while (!(((LDMA->CHEN & chMask) == 0) && ((LDMA->CHDONE & chMask) == chMask))) { } #if !defined(_SILICON_LABS_32B_SERIES_2) /* Stop the LDMA clock now */ CMU_ClockEnable(cmuClock_LDMA, false); #endif } /***************************************************************************//** * @brief * Initialize ECC for a given memory bank. * * @brief * This function initializes ECC for a given memory bank which is specified * with the MSC_EccBank_Typedef structure input parameter. * * @param[in] eccBank * ECC memory bank device structure. * * @param[in] dmaChannels * Array of 2 DMA channels that may be used during ECC initialization. * ******************************************************************************/ static void mscEccBankInit(const MSC_EccBank_Typedef *eccBank, uint32_t dmaChannels[2]) { uint32_t ctrlReg; CORE_DECLARE_IRQ_STATE; CORE_ENTER_CRITICAL(); /* Enable ECC write. Keep ECC checking disabled during initialization. */ ctrlReg = *eccBank->ctrlReg; ctrlReg |= 1 << eccBank->writeEnBit; *eccBank->ctrlReg = ctrlReg; /* Initialize ECC syndromes by using DMA to read and write the existing data values in RAM. */ mscEccReadWriteExistingDma(eccBank->base, eccBank->size, dmaChannels); /* Clear any ECC errors that may have been reported before or during initialization. */ *eccBank->ifClearReg = eccBank->ifClearMask; /* Enable ECC decoder to detect and report ECC errors. */ ctrlReg |= 1 << eccBank->checkEnBit; *eccBank->ctrlReg = ctrlReg; CORE_EXIT_CRITICAL(); } /***************************************************************************//** * @brief * Disable ECC for a given memory bank. * * @brief * This function disables ECC for a given memory bank which is specified * with the MSC_EccBank_Typedef structure input parameter. * * @param[in] eccBank * ECC memory bank device structure. * ******************************************************************************/ static void mscEccBankDisable(const MSC_EccBank_Typedef *eccBank) { /* Disable ECC write (encoder) and checking (decoder). */ *eccBank->ctrlReg &= ~((1 << eccBank->writeEnBit) | (1 << eccBank->checkEnBit)); } /***************************************************************************//** * @brief * Configure Error Correcting Code (ECC) * * @details * This function configures ECC support according to the configuration * input parameter. If the user requests enabling ECC for a given RAM bank * this function will initialize ECC memory (syndromes) for the bank by * reading and writing the existing values in memory. I.e. all data is * preserved. The initialization process runs in a critical section * disallowing interrupts and thread scheduling, and will consume a * considerable amount of clock cycles. Therefore the user should carefully * assess where to call this function. The user can consider to increase * the clock frequency in order to reduce the execution time. * This function makes use of 2 DMA channels to move data to/from RAM in an * efficient way. The user can select which 2 DMA channels to use in order * to avoid conflicts with the application. However the user must make sure * that no other DMA operations takes place while this function is executing. * If the application has been using the DMA controller prior to calling this * function, the application will need to reinitialize DMA registers after * this function has completed. * * @note * This function protects the ECC initialization procedure from interrupts * and other threads by using a critical section (defined by em_core.h) * When running on RTOS the user may need to override CORE_EnterCritical * CORE_ExitCritical which are declared as 'SL_WEAK' in em_core.c. * * @param[in] eccConfig * ECC configuration ******************************************************************************/ void MSC_EccConfigSet(MSC_EccConfig_TypeDef *eccConfig) { unsigned int cnt; #if defined(_SILICON_LABS_32B_SERIES_1_CONFIG_1) /* On Series 1 Config 1, aka EFM32GG11, disable ECC fault enable. */ MSC->CTRL &= ~MSC_CTRL_RAMECCERRFAULTEN; #endif /* Loop through the ECC banks array, enable or disable according to the eccConfig->enableEccBank array. */ for (cnt = 0; cnt < MSC_ECC_BANKS; cnt++) { if (eccConfig->enableEccBank[cnt]) { mscEccBankInit(&eccBank[cnt], eccConfig->dmaChannels); } else { mscEccBankDisable(&eccBank[cnt]); } } } #endif /* #if defined(_MSC_ECCCTRL_MASK) */ /** @} (end addtogroup MSC) */ /** @} (end addtogroup emlib) */ #endif /* defined(MSC_COUNT) && (MSC_COUNT > 0) */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/emlib/src/em_prs.c.
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/***************************************************************************//** * @file * @brief Peripheral Reflex System (PRS) Peripheral API * @version 5.7.0 ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * SPDX-License-Identifier: Zlib * * The licensor of this software is Silicon Laboratories Inc. * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be * appreciated but is not required. * 2. Altered source versions must be plainly marked as such, and must not be * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * ******************************************************************************/ #include "em_prs.h" #if defined(PRS_COUNT) && (PRS_COUNT > 0) #include "em_assert.h" /***************************************************************************//** * @addtogroup emlib * @{ ******************************************************************************/ /***************************************************************************//** * @addtogroup PRS * @brief Peripheral Reflex System (PRS) Peripheral API * @details * This module contains functions to control the PRS peripheral of Silicon * Labs 32-bit MCUs and SoCs. The PRS allows configurable, fast, and autonomous * communication between peripherals on the MCU or SoC. * @{ ******************************************************************************/ /******************************************************************************* ************************** LOCAL FUNCTIONS ******************************** ******************************************************************************/ /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ /***************************************************************************//** * @brief * Get PRS source for a channel. * * @param[in] type * PRS channel type. This can be either @ref prsTypeAsync or * @ref prsTypeSync. * * @param[in] ch * channel number. * * @return * PRS source for the channel. ******************************************************************************/ static uint32_t getSource(unsigned int ch, PRS_ChType_t type) { uint32_t source; #if defined(_PRS_ASYNC_CH_CTRL_SOURCESEL_MASK) if (type == prsTypeAsync) { source = (PRS->ASYNC_CH[ch].CTRL & _PRS_ASYNC_CH_CTRL_SOURCESEL_MASK) >> _PRS_ASYNC_CH_CTRL_SOURCESEL_SHIFT; } else { source = (PRS->SYNC_CH[ch].CTRL & _PRS_SYNC_CH_CTRL_SOURCESEL_MASK) >> _PRS_SYNC_CH_CTRL_SOURCESEL_SHIFT; } #else (void) type; source = (PRS->CH[ch].CTRL & _PRS_CH_CTRL_SOURCESEL_MASK) >> _PRS_CH_CTRL_SOURCESEL_SHIFT; #endif return source; } #if defined(_SILICON_LABS_32B_SERIES_2) /***************************************************************************//** * @brief * Convert an async PRS source to a sync source. * * @details * This conversion must be done because the id's of the same peripheral * source is different depending on if it's used as an asynchronous PRS source * or a synchronous PRS source. * * @param[in] asyncSource * The id of the asynchronous PRS source. * * @return * The id of the corresponding synchronous PRS source or 0 if it's not found. ******************************************************************************/ static uint32_t toSyncSource(uint32_t asyncSource) { uint32_t syncSource = 0; switch (asyncSource) { case _PRS_ASYNC_CH_CTRL_SOURCESEL_IADC0: syncSource = _PRS_SYNC_CH_CTRL_SOURCESEL_IADC0; break; case _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER0: syncSource = _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER0; break; case _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER1: syncSource = _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER1; break; case _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER2: syncSource = _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER2; break; case _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER3: syncSource = _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER3; break; default: EFM_ASSERT(false); break; } return syncSource; } /***************************************************************************//** * @brief * Convert an async PRS signal to a sync signal. * * @details * PRS values for TIMER2 and TIMER3 signals differ between asynchronous and * synchronous PRS channels. This function must be used to handle the * conversion. * * @param[in] asyncSource * The id of the asynchronous PRS source. * * @param[in] asyncSignal * The id of the asynchronous PRS signal. * * @return * The id of the corresponding synchronous PRS signal. ******************************************************************************/ static uint32_t toSyncSignal(uint32_t asyncSource, uint32_t asyncSignal) { uint32_t syncSignal = asyncSignal; switch (asyncSource) { case _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER2: case _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER3: switch (asyncSignal) { case _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2UF: syncSignal = _PRS_SYNC_CH_CTRL_SIGSEL_TIMER2UF; break; case _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2OF: syncSignal = _PRS_SYNC_CH_CTRL_SIGSEL_TIMER2OF; break; case _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC0: syncSignal = _PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC0; break; case _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC1: syncSignal = _PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC1; break; case _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC2: syncSignal = _PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC2; break; default: break; } break; default: // No translation break; } return syncSignal; } #endif /** @endcond */ /******************************************************************************* ************************** GLOBAL FUNCTIONS ******************************* ******************************************************************************/ /***************************************************************************//** * @brief * Set a source and signal for a channel. * * @param[in] ch * A channel to define the signal and source for. * * @param[in] source * A source to select for the channel. Use one of PRS_CH_CTRL_SOURCESEL_x defines. * * @param[in] signal * A signal (for selected @p source) to use. Use one of PRS_CH_CTRL_SIGSEL_x * defines. * * @param[in] edge * An edge (for selected source/signal) to generate the pulse for. ******************************************************************************/ void PRS_SourceSignalSet(unsigned int ch, uint32_t source, uint32_t signal, PRS_Edge_TypeDef edge) { #if defined(_PRS_SYNC_CH_CTRL_MASK) (void) edge; EFM_ASSERT(ch < PRS_SYNC_CHAN_COUNT); PRS->SYNC_CH[ch].CTRL = (source & _PRS_SYNC_CH_CTRL_SOURCESEL_MASK) | (signal & _PRS_SYNC_CH_CTRL_SIGSEL_MASK); #else EFM_ASSERT(ch < PRS_CHAN_COUNT); PRS->CH[ch].CTRL = (source & _PRS_CH_CTRL_SOURCESEL_MASK) | (signal & _PRS_CH_CTRL_SIGSEL_MASK) | (uint32_t)edge << _PRS_CH_CTRL_EDSEL_SHIFT; #endif } #if defined(PRS_ASYNC_SUPPORTED) /***************************************************************************//** * @brief * Set the source and asynchronous signal for a channel. * * @details * Asynchronous reflexes are not clocked on HFPERCLK and can be used even in * EM2/EM3. * There is a limitation to reflexes operating in asynchronous mode in * that they can only be used by a subset of the reflex consumers. See * the PRS chapter in the reference manual for the complete list of * supported asynchronous signals and consumers. * * @note * This function is not supported on EFM32GxxxFyyy parts. * In asynchronous mode, the edge detector only works in EM0 and should * not be used. The EDSEL parameter in PRS_CHx_CTRL register is set to 0 (OFF) * by default. * * @param[in] ch * A channel to define the source and asynchronous signal for. * * @param[in] source * A source to select for the channel. Use one of PRS_CH_CTRL_SOURCESEL_x defines. * * @param[in] signal * An asynchronous signal (for selected @p source) to use. Use one of the * PRS_CH_CTRL_SIGSEL_x defines that support asynchronous operation. ******************************************************************************/ void PRS_SourceAsyncSignalSet(unsigned int ch, uint32_t source, uint32_t signal) { PRS_ConnectSignal(ch, prsTypeAsync, (PRS_Signal_t) (source | signal)); } #endif #if defined(_PRS_ROUTELOC0_MASK) || (_PRS_ROUTE_MASK) /***************************************************************************//** * @brief * Send the output of a PRS channel to a GPIO pin. * * @details * This function is used to send the output of a PRS channel to a GPIO pin. * Note that there are certain restrictions to where a PRS channel can be * routed. Consult the datasheet of the device to see if a channel can be * routed to the requested GPIO pin. * * @param[in] ch * PRS channel number. * * @param[in] loc * PRS routing location. ******************************************************************************/ void PRS_GpioOutputLocation(unsigned int ch, unsigned int location) { EFM_ASSERT(ch < PRS_CHAN_COUNT); #if defined(_PRS_ROUTE_MASK) PRS->ROUTE |= (location << _PRS_ROUTE_LOCATION_SHIFT) | (1 << ch); #else uint32_t shift = (ch % 4) * 8; uint32_t mask = location << shift; uint32_t locationGroup = ch / 4; /* Since all ROUTELOCx registers are in consecutive memory locations, we can treat them * as an array starting at ROUTELOC0 and use locationGroup to index into this array */ volatile uint32_t * routeloc = &PRS->ROUTELOC0; routeloc[locationGroup] |= mask; PRS->ROUTEPEN |= 1 << ch; #endif } #endif /***************************************************************************//** * @brief * Search for the first free PRS channel. * * @param[in] type * PRS channel type. This can be either @ref prsTypeAsync or * @ref prsTypeSync. * * @return * Channel number >= 0 if an unused PRS channel was found. If no free PRS * channel was found then -1 is returned. ******************************************************************************/ int PRS_GetFreeChannel(PRS_ChType_t type) { int ch = -1; uint32_t source; int max; if (type == prsTypeAsync) { max = PRS_ASYNC_CHAN_COUNT; } else { max = PRS_SYNC_CHAN_COUNT; } for (int i = 0; i < max; i++) { source = getSource(i, type); if (source == 0) { ch = i; break; } } return ch; } /***************************************************************************//** * @brief * Reset all PRS channels * * @details * This function will reset all the PRS channel configuration. ******************************************************************************/ void PRS_Reset(void) { unsigned int i; #if defined(_SILICON_LABS_32B_SERIES_2) PRS->ASYNC_SWLEVEL = 0; for (i = 0; i < PRS_ASYNC_CHAN_COUNT; i++) { PRS->ASYNC_CH[i].CTRL = _PRS_ASYNC_CH_CTRL_RESETVALUE; } for (i = 0; i < PRS_SYNC_CHAN_COUNT; i++) { PRS->SYNC_CH[i].CTRL = _PRS_SYNC_CH_CTRL_RESETVALUE; } #else PRS->SWLEVEL = 0x0; for (i = 0; i < PRS_CHAN_COUNT; i++) { PRS->CH[i].CTRL = _PRS_CH_CTRL_RESETVALUE; } #endif } /***************************************************************************//** * @brief * Connect a PRS signal to a channel. * * @details * This function will make the PRS signal available on the specific channel. * Only a single PRS signal can be connected to any given channel. * * @param[in] ch * PRS channel number. * * @param[in] type * PRS channel type. This can be either @ref prsTypeAsync or * @ref prsTypeSync. * * @param[in] signal * This is the PRS signal that should be placed on the channel. ******************************************************************************/ void PRS_ConnectSignal(unsigned int ch, PRS_ChType_t type, PRS_Signal_t signal) { #if defined(_PRS_ASYNC_CH_CTRL_MASK) // Series 2 devices uint32_t sourceField = ((uint32_t)signal & _PRS_ASYNC_CH_CTRL_SOURCESEL_MASK) >> _PRS_ASYNC_CH_CTRL_SOURCESEL_SHIFT; uint32_t signalField = ((uint32_t)signal & _PRS_ASYNC_CH_CTRL_SIGSEL_MASK) >> _PRS_ASYNC_CH_CTRL_SIGSEL_SHIFT; if (type == prsTypeAsync) { EFM_ASSERT(ch < PRS_ASYNC_CHAN_COUNT); PRS->ASYNC_CH[ch].CTRL = PRS_ASYNC_CH_CTRL_FNSEL_A | (sourceField << _PRS_ASYNC_CH_CTRL_SOURCESEL_SHIFT) | (signalField << _PRS_ASYNC_CH_CTRL_SIGSEL_SHIFT); } else { EFM_ASSERT(ch < PRS_SYNC_CHAN_COUNT); signalField = toSyncSignal(sourceField, signalField); sourceField = toSyncSource(sourceField); PRS->SYNC_CH[ch].CTRL = (sourceField << _PRS_SYNC_CH_CTRL_SOURCESEL_SHIFT) | (signalField << _PRS_SYNC_CH_CTRL_SIGSEL_SHIFT); } #else // Series 0 and Series 1 devices uint32_t signalField = (uint32_t) signal & (_PRS_CH_CTRL_SOURCESEL_MASK | _PRS_CH_CTRL_SIGSEL_MASK); if (type == prsTypeAsync) { #if defined(PRS_ASYNC_SUPPORTED) EFM_ASSERT(ch < PRS_ASYNC_CHAN_COUNT); PRS->CH[ch].CTRL = PRS_CH_CTRL_EDSEL_OFF | PRS_CH_CTRL_ASYNC | signalField; #endif } else { EFM_ASSERT(ch < PRS_SYNC_CHAN_COUNT); PRS->CH[ch].CTRL = PRS_CH_CTRL_EDSEL_OFF | signalField; } #endif } #if defined(_SILICON_LABS_32B_SERIES_2) /***************************************************************************//** * @brief * Connect a peripheral consumer to a PRS channel. * * @details * Different peripherals can use PRS channels as their input. This function * can be used to connect a peripheral consumer to a PRS channel. Multiple * consumers can be connected to a single PRS channel. * * @param[in] ch * PRS channel number. * * @param[in] type * PRS channel type. This can be either @ref prsTypeAsync or * @ref prsTypeSync. * * @param[in] consumer * This is the PRS consumer. ******************************************************************************/ void PRS_ConnectConsumer(unsigned int ch, PRS_ChType_t type, PRS_Consumer_t consumer) { EFM_ASSERT((uint32_t)consumer <= 0xFFF); volatile uint32_t * addr = (volatile uint32_t *) PRS; uint32_t offset = (uint32_t) consumer; addr = addr + offset / 4; if (consumer != prsConsumerNone) { if (type == prsTypeAsync) { *addr = ch << _PRS_CONSUMER_TIMER0_CC0_PRSSEL_SHIFT; } else { *addr = ch << _PRS_CONSUMER_TIMER0_CC0_SPRSSEL_SHIFT; } } } /***************************************************************************//** * @brief * Send the output of a PRS channel to a GPIO pin. * * @details * This function is used to send the output of a PRS channel to a GPIO pin. * Note that there are certain restrictions to where a PRS channel can be * routed. Consult the datasheet of the device to see if a channel can be * routed to the requested GPIO pin. Some devices for instance can only route * the async channels 0-5 on GPIO pins PAx and PBx while async channels 6-11 * can only be routed to GPIO pins PCx and PDx * * @param[in] ch * PRS channel number. * * @param[in] type * PRS channel type. This can be either @ref prsTypeAsync or * @ref prsTypeSync. * * @param[in] port * GPIO port * * @param[in] pin * GPIO pin ******************************************************************************/ void PRS_PinOutput(unsigned int ch, PRS_ChType_t type, GPIO_Port_TypeDef port, uint8_t pin) { volatile uint32_t * addr; if (type == prsTypeAsync) { addr = &GPIO->PRSROUTE[0].ASYNCH0ROUTE; } else { addr = &GPIO->PRSROUTE[0].SYNCH0ROUTE; } addr += ch; *addr = ((uint32_t)port << _GPIO_PRS_ASYNCH0ROUTE_PORT_SHIFT) | (pin << _GPIO_PRS_ASYNCH0ROUTE_PIN_SHIFT); if (type == prsTypeAsync) { GPIO->PRSROUTE[0].ROUTEEN |= 0x1 << (ch + _GPIO_PRS_ROUTEEN_ASYNCH0PEN_SHIFT); } else { GPIO->PRSROUTE[0].ROUTEEN |= 0x1 << (ch + _GPIO_PRS_ROUTEEN_SYNCH0PEN_SHIFT); } } /***************************************************************************//** * @brief * Combine two PRS channels using a logic function. * * @details * This function allows you to combine the output of one PRS channel with the * the signal of another PRS channel using various logic functions. Note that * the hardware only allows one PRS channel to be combined with the previous * channel. So for instance channel 5 can be combined only with channel 4. * * The logic function operates on two PRS channels called A and B. The output * of PRS channel B is combined with the PRS source configured for channel A * to produce an output. This output is used as the output of channel A. * * @param[in] chA * PRS Channel for the A input. * * @param[in] chB * PRS Channel for the B input. * * @param[in] logic * The logic function to use when combining the Channel A and Channel B. The * output of the logic function is the output of Channel A. Function like * AND, OR, XOR, NOT and more are available. ******************************************************************************/ void PRS_Combine(unsigned int chA, unsigned int chB, PRS_Logic_t logic) { EFM_ASSERT(chA < PRS_ASYNC_CHAN_COUNT); EFM_ASSERT(chB < PRS_ASYNC_CHAN_COUNT); EFM_ASSERT(chA == ((chB + 1) % PRS_ASYNC_CHAN_COUNT)); PRS->ASYNC_CH[chA].CTRL = (PRS->ASYNC_CH[chA].CTRL & ~_PRS_ASYNC_CH_CTRL_FNSEL_MASK) | ((uint32_t)logic << _PRS_ASYNC_CH_CTRL_FNSEL_SHIFT); } #endif /** @} (end addtogroup PRS) */ /** @} (end addtogroup emlib) */ #endif /* defined(PRS_COUNT) && (PRS_COUNT > 0) */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/emlib/src/em_rmu.c.
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/***************************************************************************//** * @file * @brief Reset Management Unit (RMU) peripheral module peripheral API * @version 5.7.0 ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * SPDX-License-Identifier: Zlib * * The licensor of this software is Silicon Laboratories Inc. * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be * appreciated but is not required. * 2. Altered source versions must be plainly marked as such, and must not be * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * ******************************************************************************/ #include "em_rmu.h" #if (defined(RMU_COUNT) && (RMU_COUNT > 0)) || (_EMU_RSTCTRL_MASK) #include "em_common.h" #include "em_emu.h" #include "em_bus.h" /***************************************************************************//** * @addtogroup emlib * @{ ******************************************************************************/ /***************************************************************************//** * @addtogroup RMU * @brief Reset Management Unit (RMU) Peripheral API * @details * This module contains functions to control the RMU peripheral of Silicon * Labs 32-bit MCUs and SoCs. RMU ensures correct reset operation and is * responsible for connecting the different reset sources to the reset lines of * the MCU or SoC. * @{ ******************************************************************************/ /******************************************************************************* ***************************** DEFINES ********************************* ******************************************************************************/ /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ #if defined(_RMU_RSTCAUSE_MASK) /** Reset cause XMASKS for series-0 and series-1 devices. Reset cause zero and "don't care" bit definitions (XMASKs). An XMASK 1 bit marks a bit that must be zero in RMU_RSTCAUSE. A 0 in XMASK is a "don't care" bit in RMU_RSTCAUSE if also 0 in resetCauseMask in @ref RMU_ResetCauseMasks_Typedef. */ /* EFM32G */ #if (_RMU_RSTCAUSE_MASK == 0x0000007FUL) #define RMU_RSTCAUSE_PORST_XMASK 0x00000000UL /** 0000000000000000 < Power On Reset */ #define RMU_RSTCAUSE_BODUNREGRST_XMASK 0x00000001UL /** 0000000000000001 < Brown Out Detector Unregulated Domain Reset */ #define RMU_RSTCAUSE_BODREGRST_XMASK 0x0000001BUL /** 0000000000011011 < Brown Out Detector Regulated Domain Reset */ #define RMU_RSTCAUSE_EXTRST_XMASK 0x00000003UL /** 0000000000000011 < External Pin Reset */ #define RMU_RSTCAUSE_WDOGRST_XMASK 0x00000003UL /** 0000000000000011 < Watchdog Reset */ #define RMU_RSTCAUSE_LOCKUPRST_XMASK 0x0000001FUL /** 0000000000011111 < LOCKUP Reset */ #define RMU_RSTCAUSE_SYSREQRST_XMASK 0x0000001FUL /** 0000000000011111 < System Request Reset */ #define NUM_RSTCAUSES 7 /* EFM32TG, EFM32HG, EZR32HG, EFM32ZG */ #elif (_RMU_RSTCAUSE_MASK == 0x000007FFUL) #define RMU_RSTCAUSE_PORST_XMASK 0x00000000UL /** 0000000000000000 < Power On Reset */ #define RMU_RSTCAUSE_BODUNREGRST_XMASK 0x00000081UL /** 0000000010000001 < Brown Out Detector Unregulated Domain Reset */ #define RMU_RSTCAUSE_BODREGRST_XMASK 0x00000091UL /** 0000000010010001 < Brown Out Detector Regulated Domain Reset */ #define RMU_RSTCAUSE_EXTRST_XMASK 0x00000001UL /** 0000000000000001 < External Pin Reset */ #define RMU_RSTCAUSE_WDOGRST_XMASK 0x00000003UL /** 0000000000000011 < Watchdog Reset */ #define RMU_RSTCAUSE_LOCKUPRST_XMASK 0x0000EFDFUL /** 1110111111011111 < LOCKUP Reset */ #define RMU_RSTCAUSE_SYSREQRST_XMASK 0x0000EF9FUL /** 1110111110011111 < System Request Reset */ #define RMU_RSTCAUSE_EM4RST_XMASK 0x00000719UL /** 0000011100011001 < EM4 Reset */ #define RMU_RSTCAUSE_EM4WURST_XMASK 0x00000619UL /** 0000011000011001 < EM4 Wake-up Reset */ #define RMU_RSTCAUSE_BODAVDD0_XMASK 0x0000041FUL /** 0000010000011111 < AVDD0 Bod Reset. */ #define RMU_RSTCAUSE_BODAVDD1_XMASK 0x0000021FUL /** 0000001000011111 < AVDD1 Bod Reset. */ #define NUM_RSTCAUSES 11 /* EFM32GG, EFM32LG, EZR32LG, EFM32WG, EZR32WG */ #elif (_RMU_RSTCAUSE_MASK == 0x0000FFFFUL) #define RMU_RSTCAUSE_PORST_XMASK 0x00000000UL /** 0000000000000000 < Power On Reset */ #define RMU_RSTCAUSE_BODUNREGRST_XMASK 0x00000081UL /** 0000000010000001 < Brown Out Detector Unregulated Domain Reset */ #define RMU_RSTCAUSE_BODREGRST_XMASK 0x00000091UL /** 0000000010010001 < Brown Out Detector Regulated Domain Reset */ #define RMU_RSTCAUSE_EXTRST_XMASK 0x00000001UL /** 0000000000000001 < External Pin Reset */ #define RMU_RSTCAUSE_WDOGRST_XMASK 0x00000003UL /** 0000000000000011 < Watchdog Reset */ #define RMU_RSTCAUSE_LOCKUPRST_XMASK 0x0000EFDFUL /** 1110111111011111 < LOCKUP Reset */ #define RMU_RSTCAUSE_SYSREQRST_XMASK 0x0000EF9FUL /** 1110111110011111 < System Request Reset */ #define RMU_RSTCAUSE_EM4RST_XMASK 0x00000719UL /** 0000011100011001 < EM4 Reset */ #define RMU_RSTCAUSE_EM4WURST_XMASK 0x00000619UL /** 0000011000011001 < EM4 Wake-up Reset */ #define RMU_RSTCAUSE_BODAVDD0_XMASK 0x0000041FUL /** 0000010000011111 < AVDD0 Bod Reset */ #define RMU_RSTCAUSE_BODAVDD1_XMASK 0x0000021FUL /** 0000001000011111 < AVDD1 Bod Reset */ #define RMU_RSTCAUSE_BUBODVDDDREG_XMASK 0x00000001UL /** 0000000000000001 < Backup Brown Out Detector, VDD_DREG */ #define RMU_RSTCAUSE_BUBODBUVIN_XMASK 0x00000001UL /** 0000000000000001 < Backup Brown Out Detector, BU_VIN */ #define RMU_RSTCAUSE_BUBODUNREG_XMASK 0x00000001UL /** 0000000000000001 < Backup Brown Out Detector Unregulated Domain */ #define RMU_RSTCAUSE_BUBODREG_XMASK 0x00000001UL /** 0000000000000001 < Backup Brown Out Detector Regulated Domain */ #define RMU_RSTCAUSE_BUMODERST_XMASK 0x00000001UL /** 0000000000000001 < Backup mode reset */ #define NUM_RSTCAUSES 16 /* EFM32xG1, EFM32xG12, EFM32xG13 */ #elif ((_RMU_RSTCAUSE_MASK & 0x0FFFFFFF) == 0x00010F1DUL) #define RMU_RSTCAUSE_PORST_XMASK 0x00000000UL /** 0000000000000000 < Power On Reset */ #define RMU_RSTCAUSE_BODAVDD_XMASK 0x00000001UL /** 0000000000000001 < AVDD BOD Reset */ #define RMU_RSTCAUSE_BODDVDD_XMASK 0x00000001UL /** 0000000000000001 < DVDD BOD Reset */ #define RMU_RSTCAUSE_BODREGRST_XMASK 0x00000001UL /** 0000000000000001 < Regulated Domain (DEC) BOD Reset */ #define RMU_RSTCAUSE_EXTRST_XMASK 0x00000001UL /** 0000000000000001 < External Pin Reset */ #define RMU_RSTCAUSE_LOCKUPRST_XMASK 0x0000001DUL /** 0000000000011101 < LOCKUP Reset */ #define RMU_RSTCAUSE_SYSREQRST_XMASK 0x0000001DUL /** 0000000000011101 < System Request Reset */ #define RMU_RSTCAUSE_WDOGRST_XMASK 0x0000001DUL /** 0000000000011101 < Watchdog Reset */ #define RMU_RSTCAUSE_EM4RST_XMASK 0x0000001DUL /** 0000000000011101 < EM4H/S Reset */ #define NUM_RSTCAUSES 9 /* EFM32GG11 */ #elif ((_RMU_RSTCAUSE_MASK & 0x0FFFFFFF) == 0x00011F1DUL) #define RMU_RSTCAUSE_PORST_XMASK 0x00000000UL /** 0000000000000000 < Power On Reset */ #define RMU_RSTCAUSE_BODAVDD_XMASK 0x00000001UL /** 0000000000000001 < AVDD BOD Reset */ #define RMU_RSTCAUSE_BODDVDD_XMASK 0x00000001UL /** 0000000000000001 < DVDD BOD Reset */ #define RMU_RSTCAUSE_BODREGRST_XMASK 0x00000001UL /** 0000000000000001 < Regulated Domain (DEC) BOD Reset */ #define RMU_RSTCAUSE_EXTRST_XMASK 0x00000001UL /** 0000000000000001 < External Pin Reset */ #define RMU_RSTCAUSE_LOCKUPRST_XMASK 0x0000001DUL /** 0000000000011101 < LOCKUP Reset */ #define RMU_RSTCAUSE_SYSREQRST_XMASK 0x0000001DUL /** 0000000000011101 < System Request Reset */ #define RMU_RSTCAUSE_WDOGRST_XMASK 0x0000001DUL /** 0000000000011101 < Watchdog Reset */ #define RMU_RSTCAUSE_BUMODERST_XMASK 0x0000001DUL /** 0000000000011101 < Backup mode reset */ #define RMU_RSTCAUSE_EM4RST_XMASK 0x0000001DUL /** 0000000000011101 < EM4H/S Reset */ #define NUM_RSTCAUSES 10 #else #error "RMU_RSTCAUSE XMASKs are not defined for this family." #endif /* Pin reset definitions. */ #define LB_CLW0 (*((volatile uint32_t *)(LOCKBITS_BASE) +122)) #define LB_CLW0_PINRESETSOFT (1 << 2) #if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) /* Fix for errata EMU_E208 - Occasional Full Reset After Exiting EM4H. */ #define ERRATA_FIX_EMU_E208_EN #endif #endif /* #if defined(_RMU_RSTCAUSE_MASK) */ /******************************************************************************* ******************************* STRUCTS *********************************** ******************************************************************************/ #if defined(_RMU_RSTCAUSE_MASK) /** Reset cause mask type for series-0 and series-1 devices. */ typedef struct { /** Reset cause 1 bits. */ uint32_t resetCauseMask; /** Reset cause 0 and "don't care" bits. */ uint32_t resetCauseZeroXMask; } RMU_ResetCauseMasks_Typedef; #endif /******************************************************************************* ******************************* TYPEDEFS ********************************** ******************************************************************************/ #if defined(_RMU_RSTCAUSE_MASK) /** Reset cause mask table. */ static const RMU_ResetCauseMasks_Typedef resetCauseMasks[NUM_RSTCAUSES] = { { RMU_RSTCAUSE_PORST, RMU_RSTCAUSE_PORST_XMASK }, #if defined(RMU_RSTCAUSE_BODUNREGRST) { RMU_RSTCAUSE_BODUNREGRST, RMU_RSTCAUSE_BODUNREGRST_XMASK }, #endif #if defined(RMU_RSTCAUSE_BODREGRST) { RMU_RSTCAUSE_BODREGRST, RMU_RSTCAUSE_BODREGRST_XMASK }, #endif #if defined(RMU_RSTCAUSE_AVDDBOD) { RMU_RSTCAUSE_AVDDBOD, RMU_RSTCAUSE_BODAVDD_XMASK }, #endif #if defined(RMU_RSTCAUSE_DVDDBOD) { RMU_RSTCAUSE_DVDDBOD, RMU_RSTCAUSE_BODDVDD_XMASK }, #endif #if defined(RMU_RSTCAUSE_DECBOD) { RMU_RSTCAUSE_DECBOD, RMU_RSTCAUSE_BODREGRST_XMASK }, #endif { RMU_RSTCAUSE_EXTRST, RMU_RSTCAUSE_EXTRST_XMASK }, { RMU_RSTCAUSE_WDOGRST, RMU_RSTCAUSE_WDOGRST_XMASK }, { RMU_RSTCAUSE_LOCKUPRST, RMU_RSTCAUSE_LOCKUPRST_XMASK }, { RMU_RSTCAUSE_SYSREQRST, RMU_RSTCAUSE_SYSREQRST_XMASK }, #if defined(RMU_RSTCAUSE_EM4RST) { RMU_RSTCAUSE_EM4RST, RMU_RSTCAUSE_EM4RST_XMASK }, #endif #if defined(RMU_RSTCAUSE_EM4WURST) { RMU_RSTCAUSE_EM4WURST, RMU_RSTCAUSE_EM4WURST_XMASK }, #endif #if defined(RMU_RSTCAUSE_BODAVDD0) { RMU_RSTCAUSE_BODAVDD0, RMU_RSTCAUSE_BODAVDD0_XMASK }, #endif #if defined(RMU_RSTCAUSE_BODAVDD1) { RMU_RSTCAUSE_BODAVDD1, RMU_RSTCAUSE_BODAVDD1_XMASK }, #endif #if defined(BU_PRESENT) && defined(_SILICON_LABS_32B_SERIES_0) { RMU_RSTCAUSE_BUBODVDDDREG, RMU_RSTCAUSE_BUBODVDDDREG_XMASK }, { RMU_RSTCAUSE_BUBODBUVIN, RMU_RSTCAUSE_BUBODBUVIN_XMASK }, { RMU_RSTCAUSE_BUBODUNREG, RMU_RSTCAUSE_BUBODUNREG_XMASK }, { RMU_RSTCAUSE_BUBODREG, RMU_RSTCAUSE_BUBODREG_XMASK }, { RMU_RSTCAUSE_BUMODERST, RMU_RSTCAUSE_BUMODERST_XMASK }, #elif defined(RMU_RSTCAUSE_BUMODERST) { RMU_RSTCAUSE_BUMODERST, RMU_RSTCAUSE_BUMODERST_XMASK }, #endif }; #endif /* #if defined(_RMU_RSTCAUSE_MASK) */ /******************************************************************************* ******************************** TEST ******************************** ******************************************************************************/ #if defined(EMLIB_REGRESSION_TEST) /* A test variable that replaces the RSTCAUSE cause register when testing the RMU_ResetCauseGet function. */ extern uint32_t rstCause; #endif /** @endcond */ /******************************************************************************* ************************** GLOBAL FUNCTIONS ******************************* ******************************************************************************/ /***************************************************************************//** * @brief * Disable/enable reset for various peripherals and signal sources. * * @param[in] reset Reset types to enable/disable.s * * @param[in] mode Reset mode. ******************************************************************************/ void RMU_ResetControl(RMU_Reset_TypeDef reset, RMU_ResetMode_TypeDef mode) { /* Note that the RMU supports bit-band access, but not peripheral bit-field set/clear. */ #if defined(_RMU_CTRL_PINRMODE_MASK) uint32_t val; #endif uint32_t shift; shift = SL_CTZ((uint32_t)reset); #if defined(_EMU_RSTCTRL_MASK) BUS_RegBitWrite(&EMU->RSTCTRL, (uint32_t)shift, mode ? 1 : 0); #elif defined(_RMU_CTRL_PINRMODE_MASK) val = (uint32_t)mode << shift; RMU->CTRL = (RMU->CTRL & ~reset) | val; #else BUS_RegBitWrite(&RMU->CTRL, (uint32_t)shift, mode ? 1 : 0); #endif } /***************************************************************************//** * @brief * Clear the reset cause register. * * @details * This function clears all the reset cause bits of the RSTCAUSE register. * The reset cause bits must be cleared by software before a new reset occurs. * Otherwise, reset causes may accumulate. See @ref RMU_ResetCauseGet(). ******************************************************************************/ void RMU_ResetCauseClear(void) { #if defined(_EMU_RSTCTRL_MASK) EMU->CMD_SET = EMU_CMD_RSTCAUSECLR; #else RMU->CMD = RMU_CMD_RCCLR; #endif #if defined(EMU_AUXCTRL_HRCCLR) { uint32_t locked; /* Clear reset causes not cleared with the RMU CMD register. */ /* (If EMU registers are locked, they must be unlocked first) */ locked = EMU->LOCK & EMU_LOCK_LOCKKEY_LOCKED; if (locked) { EMU_Unlock(); } BUS_RegBitWrite(&(EMU->AUXCTRL), _EMU_AUXCTRL_HRCCLR_SHIFT, 1); BUS_RegBitWrite(&(EMU->AUXCTRL), _EMU_AUXCTRL_HRCCLR_SHIFT, 0); if (locked) { EMU_Lock(); } } #endif } /***************************************************************************//** * @brief * Get the cause of the last reset. * * @details * To be useful, the reset cause must be cleared by software before a new * reset occurs. Otherwise, reset causes may accumulate. See @ref * RMU_ResetCauseClear(). This function call will return the main cause for * reset, which can be a bit mask (several causes) and clear away "noise". * * @return * A reset cause mask. See the reference manual for a description * of the reset cause mask. ******************************************************************************/ uint32_t RMU_ResetCauseGet(void) { #if defined(_EMU_RSTCAUSE_MASK) #if defined(EMLIB_REGRESSION_TEST) return rstCause; #else return EMU->RSTCAUSE; #endif #endif #if defined(_RMU_RSTCAUSE_MASK) #if !defined(EMLIB_REGRESSION_TEST) uint32_t rstCause = RMU->RSTCAUSE; #endif uint32_t validRstCause = 0; uint32_t zeroXMask; uint32_t i; for (i = 0; i < NUM_RSTCAUSES; i++) { zeroXMask = resetCauseMasks[i].resetCauseZeroXMask; #if defined(_SILICON_LABS_32B_SERIES_1) /* Handle soft/hard pin reset. */ if (!(LB_CLW0 & LB_CLW0_PINRESETSOFT)) { /* RSTCAUSE_EXTRST must be 0 if pin reset is configured as hard reset. */ switch (resetCauseMasks[i].resetCauseMask) { case RMU_RSTCAUSE_LOCKUPRST: /* Fallthrough */ case RMU_RSTCAUSE_SYSREQRST: /* Fallthrough */ case RMU_RSTCAUSE_WDOGRST: /* Fallthrough */ case RMU_RSTCAUSE_EM4RST: zeroXMask |= RMU_RSTCAUSE_EXTRST; break; default: /* MISRA requires a default case. */ break; } } #endif #if defined(_EMU_EM4CTRL_MASK) && defined(ERRATA_FIX_EMU_E208_EN) /* Ignore BOD flags impacted by EMU_E208. */ if (*(volatile uint32_t *)(EMU_BASE + 0x88) & (0x1 << 8)) { zeroXMask &= ~(RMU_RSTCAUSE_DECBOD | RMU_RSTCAUSE_DVDDBOD | RMU_RSTCAUSE_AVDDBOD); } #endif /* Check reset cause requirements. Note that a bit is "don't care" if 0 in both resetCauseMask and resetCauseZeroXMask. */ if ((rstCause & resetCauseMasks[i].resetCauseMask) && !(rstCause & zeroXMask)) { /* Add this reset-cause to the mask of qualified reset-causes. */ validRstCause |= resetCauseMasks[i].resetCauseMask; } } #if defined(_EMU_EM4CTRL_MASK) && defined(ERRATA_FIX_EMU_E208_EN) /* Clear BOD flags impacted by EMU_E208. */ if (validRstCause & RMU_RSTCAUSE_EM4RST) { validRstCause &= ~(RMU_RSTCAUSE_DECBOD | RMU_RSTCAUSE_DVDDBOD | RMU_RSTCAUSE_AVDDBOD); } #endif return validRstCause; #endif } /** @} (end addtogroup RMU) */ /** @} (end addtogroup emlib) */ #endif /* defined(RMU_COUNT) && (RMU_COUNT > 0) */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/emlib/src/em_rtcc.c.
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/***************************************************************************//** * @file * @brief Real Time Counter with Calendar (RTCC) Peripheral API * @version 5.7.0 ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * SPDX-License-Identifier: Zlib * * The licensor of this software is Silicon Laboratories Inc. * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be * appreciated but is not required. * 2. Altered source versions must be plainly marked as such, and must not be * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * ******************************************************************************/ #include "em_rtcc.h" #if defined(RTCC_COUNT) && (RTCC_COUNT == 1) #include "em_bus.h" /***************************************************************************//** * @addtogroup emlib * @{ ******************************************************************************/ /***************************************************************************//** * @addtogroup RTCC * @brief Real Time Counter (RTCC) Peripheral API * @details * This module contains functions to control the RTCC peripheral of Silicon * Labs 32-bit MCUs and SoCs. The RTCC ensures timekeeping in low energy modes. * The RTCC also includes a BCD calendar mode for easy time and date keeping. * @{ ******************************************************************************/ /******************************************************************************* ******************************* DEFINES *********************************** ******************************************************************************/ /******************************************************************************* ************************** LOCAL FUNCTIONS ******************************** ******************************************************************************/ /******************************************************************************* ************************** GLOBAL FUNCTIONS ******************************* ******************************************************************************/ /***************************************************************************//** * @brief * Configure the selected capture/compare channel of the RTCC. * * @details * Use this function to configure an RTCC channel. * Select capture/compare mode, match output action, overflow output action, * and PRS input configuration. * See the configuration structure @ref RTCC_CCChConf_TypeDef for more * details. * * @param[in] ch * A channel selector. * * @param[in] confPtr * A pointer to the configuration structure. ******************************************************************************/ void RTCC_ChannelInit(int ch, RTCC_CCChConf_TypeDef const *confPtr) { EFM_ASSERT(RTCC_CH_VALID(ch)); #if defined(_SILICON_LABS_32B_SERIES_1) EFM_ASSERT((uint32_t)confPtr->compMask < (_RTCC_CC_CTRL_COMPMASK_MASK >> _RTCC_CC_CTRL_COMPMASK_SHIFT) + 1U); /** Configure the selected capture/compare channel. */ RTCC->CC[ch].CTRL = ((uint32_t)confPtr->chMode << _RTCC_CC_CTRL_MODE_SHIFT) | ((uint32_t)confPtr->compMatchOutAction << _RTCC_CC_CTRL_CMOA_SHIFT) | ((uint32_t)confPtr->prsSel << _RTCC_CC_CTRL_PRSSEL_SHIFT) | ((uint32_t)confPtr->inputEdgeSel << _RTCC_CC_CTRL_ICEDGE_SHIFT) | ((uint32_t)confPtr->compBase << _RTCC_CC_CTRL_COMPBASE_SHIFT) | ((uint32_t)confPtr->compMask << _RTCC_CC_CTRL_COMPMASK_SHIFT) | ((uint32_t)confPtr->dayCompMode << _RTCC_CC_CTRL_DAYCC_SHIFT); #else /** Configure the selected capture/compare channel. */ RTCC->CC[ch].CTRL = ( (uint32_t)confPtr->chMode << _RTCC_CC_CTRL_MODE_SHIFT) | ( (uint32_t)confPtr->compMatchOutAction << _RTCC_CC_CTRL_CMOA_SHIFT) | ( (uint32_t)confPtr->inputEdgeSel << _RTCC_CC_CTRL_ICEDGE_SHIFT) | ( (uint32_t)confPtr->compBase << _RTCC_CC_CTRL_COMPBASE_SHIFT); if (confPtr->chMode == rtccCapComChModeCapture) { volatile uint32_t *reg = &PRS->CONSUMER_RTCC_CC0; reg[ch] = confPtr->prsSel; } #endif } /***************************************************************************//** * @brief * Enable/disable RTCC counting. * * @param[in] enable * True to enable RTCC counting, false to disable counting. ******************************************************************************/ void RTCC_Enable(bool enable) { #if defined (_RTCC_CTRL_ENABLE_SHIFT) /* Bitbanding the enable bit in the CTRL register (atomic). */ BUS_RegBitWrite((&RTCC->CTRL), _RTCC_CTRL_ENABLE_SHIFT, (uint32_t)enable); #elif defined (RTCC_CMD_START) /* Quick exit if we want to disable RTCC and it's already disabled. */ if ((RTCC->EN == 0U) && !enable) { return; } if (RTCC->EN != 0U) { /* Modifying the enable bit while synchronization is active will BusFault */ RTCC_SyncWait(); } if (enable) { RTCC->EN_SET = RTCC_EN_EN; RTCC_Start(); } else { RTCC_Stop(); RTCC_SyncWait(); RTCC->EN_CLR = RTCC_EN_EN; } #endif } /***************************************************************************//** * @brief * Initialize RTCC. * * @details * Note that the compare values must be set separately with RTCC_CompareSet(), * which should probably be done prior to the use of this function if * configuring the RTCC to start when initialization is completed. * * @param[in] init * A pointer to the RTCC initialization structure. ******************************************************************************/ void RTCC_Init(const RTCC_Init_TypeDef *init) { #if defined (_RTCC_CTRL_MASK) RTCC->CTRL = ((init->enable ? 1UL : 0UL) << _RTCC_CTRL_ENABLE_SHIFT) | ((init->debugRun ? 1UL : 0UL) << _RTCC_CTRL_DEBUGRUN_SHIFT) | ((init->precntWrapOnCCV0 ? 1UL : 0UL) << _RTCC_CTRL_PRECCV0TOP_SHIFT) | ((init->cntWrapOnCCV1 ? 1UL : 0UL) << _RTCC_CTRL_CCV1TOP_SHIFT) | ((uint32_t)init->presc << _RTCC_CTRL_CNTPRESC_SHIFT) | ((uint32_t)init->prescMode << _RTCC_CTRL_CNTTICK_SHIFT) #if defined(_RTCC_CTRL_BUMODETSEN_MASK) | ((uint32_t)init->enaBackupModeSet << _RTCC_CTRL_BUMODETSEN_SHIFT) #endif | ((init->enaOSCFailDetect ? 1UL : 0UL) << _RTCC_CTRL_OSCFDETEN_SHIFT) | ((uint32_t)init->cntMode << _RTCC_CTRL_CNTMODE_SHIFT) | ((init->disLeapYearCorr ? 1UL : 0UL) << _RTCC_CTRL_LYEARCORRDIS_SHIFT); #elif defined (_RTCC_CFG_MASK) if (RTCC->EN != 0U) { RTCC_SyncWait(); } RTCC->EN_CLR = RTCC_EN_EN; RTCC->CFG = ((init->debugRun ? 1UL : 0UL) << _RTCC_CFG_DEBUGRUN_SHIFT) | ( (init->precntWrapOnCCV0 ? 1UL : 0UL) << _RTCC_CFG_PRECNTCCV0TOP_SHIFT) | ( (init->cntWrapOnCCV1 ? 1UL : 0UL) << _RTCC_CFG_CNTCCV1TOP_SHIFT) | ( (uint32_t)init->presc << _RTCC_CFG_CNTPRESC_SHIFT) | ( (uint32_t)init->prescMode << _RTCC_CFG_CNTTICK_SHIFT); RTCC->EN_SET = RTCC_EN_EN; RTCC->CMD = init->enable ? RTCC_CMD_START : RTCC_CMD_STOP; #endif } /***************************************************************************//** * @brief * Restore RTCC to its reset state. ******************************************************************************/ void RTCC_Reset(void) { unsigned int i; #if defined(_RTCC_CTRL_MASK) /* Restore all RTCC registers to their default values. */ RTCC_Unlock(); RTCC->CTRL = _RTCC_CTRL_RESETVALUE; RTCC->PRECNT = _RTCC_PRECNT_RESETVALUE; RTCC->CNT = _RTCC_CNT_RESETVALUE; RTCC->TIME = _RTCC_TIME_RESETVALUE; RTCC->DATE = _RTCC_DATE_RESETVALUE; RTCC->IEN = _RTCC_IEN_RESETVALUE; RTCC->IFC = _RTCC_IFC_MASK; RTCC_StatusClear(); RTCC->EM4WUEN = _RTCC_EM4WUEN_RESETVALUE; for (i = 0; i < RTCC_CC_NUM; i++) { RTCC->CC[i].CTRL = _RTCC_CC_CTRL_RESETVALUE; RTCC->CC[i].CCV = _RTCC_CC_CCV_RESETVALUE; RTCC->CC[i].TIME = _RTCC_CC_TIME_RESETVALUE; RTCC->CC[i].DATE = _RTCC_CC_DATE_RESETVALUE; } #elif defined(_RTCC_CFG_MASK) /* Restore all RTCC registers to their default values. */ RTCC_Unlock(); RTCC->EN_SET = RTCC_EN_EN; RTCC_Stop(); RTCC_SyncWait(); RTCC->PRECNT = _RTCC_PRECNT_RESETVALUE; RTCC->CNT = _RTCC_CNT_RESETVALUE; RTCC->IEN = _RTCC_IEN_RESETVALUE; RTCC_IntClear(_RTCC_IF_MASK); RTCC_StatusClear(); for (i = 0; i < RTCC_CC_NUM; i++) { RTCC->CC[i].CTRL = _RTCC_CC_CTRL_RESETVALUE; RTCC->CC[i].OCVALUE = _RTCC_CC_OCVALUE_RESETVALUE; } RTCC_SyncWait(); RTCC->EN_CLR = RTCC_EN_EN; RTCC->CFG = _RTCC_CFG_RESETVALUE; #endif } /***************************************************************************//** * @brief * Clear the STATUS register. ******************************************************************************/ void RTCC_StatusClear(void) { #if defined (RTCC_CMD_CLRSTATUS) while ((RTCC->SYNCBUSY & RTCC_SYNCBUSY_CMD) != 0U) { // Wait for synchronization. } RTCC->CMD = RTCC_CMD_CLRSTATUS; #endif } /** @} (end addtogroup RTCC) */ /** @} (end addtogroup emlib) */ #endif /* defined( RTCC_COUNT ) && ( RTCC_COUNT == 1 ) */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/emlib/src/em_se.c.
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/***************************************************************************//** * @file * @brief Secure Element API * @version 5.7.0 ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * SPDX-License-Identifier: Zlib * * The licensor of this software is Silicon Laboratories Inc. * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be * appreciated but is not required. * 2. Altered source versions must be plainly marked as such, and must not be * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * ******************************************************************************/ #include "em_device.h" #if defined(SEMAILBOX_PRESENT) #include "em_se.h" #include "em_assert.h" /***************************************************************************//** * @addtogroup emlib * @{ ******************************************************************************/ /***************************************************************************//** * @addtogroup SE * @{ ******************************************************************************/ /******************************************************************************* ****************************** DEFINES *********************************** ******************************************************************************/ /* OTP initialization structure defines. */ #define SE_OTP_MCU_SETTINGS_FLAG_SECURE_BOOT_ENABLE (1 << 16) #define SE_OTP_MCU_SETTINGS_FLAG_SECURE_BOOT_VERIFY_CERTIFICATE (1 << 17) #define SE_OTP_MCU_SETTINGS_FLAG_SECURE_BOOT_ANTI_ROLLBACK (1 << 18) /******************************************************************************* ************************** GLOBAL FUNCTIONS ******************************* ******************************************************************************/ /***************************************************************************//** * @brief * Add input data to a command * * @details * This function adds a buffer of input data to the given SE command structure * The buffer gets appended by reference at the end of the list of already * added buffers. * * @note * Note that this function does not copy either the data buffer or the buffer * structure, so make sure to keep the data object in scope until the command * has been executed by the secure element. * * @param[in] command * Pointer to an SE command structure. * * @param[in] data * Pointer to a data transfer structure. ******************************************************************************/ void SE_addDataInput(SE_Command_t *command, SE_DataTransfer_t *data) { if (command->data_in == NULL) { command->data_in = data; } else { SE_DataTransfer_t *next = command->data_in; while (next->next != (void*)SE_DATATRANSFER_STOP) { next = (SE_DataTransfer_t*)next->next; } next->next = data; } } /***************************************************************************//** * @brief * Add output data to a command * * @details * This function adds a buffer of output data to the given SE command structure * The buffer gets appended by reference at the end of the list of already * added buffers. * * @note * Note that this function does not copy either the data buffer or the buffer * structure, so make sure to keep the data object in scope until the command * has been executed by the secure element. * * @param[in] command * Pointer to an SE command structure. * * @param[in] data * Pointer to a data transfer structure. ******************************************************************************/ void SE_addDataOutput(SE_Command_t *command, SE_DataTransfer_t *data) { if (command->data_out == NULL) { command->data_out = data; } else { SE_DataTransfer_t *next = command->data_out; while (next->next != (void*)SE_DATATRANSFER_STOP) { next = (SE_DataTransfer_t*)next->next; } next->next = data; } } /***************************************************************************//** * @brief * Add a parameter to a command * * @details * This function adds a parameter word to the passed command. * * @note * Make sure to not exceed @ref SE_MAX_PARAMETERS. * * @param[in] command * Pointer to a filled-out SE command structure. * @param[in] parameter * Parameter to add. ******************************************************************************/ void SE_addParameter(SE_Command_t *command, uint32_t parameter) { if (command->num_parameters >= SE_MAX_PARAMETERS) { EFM_ASSERT(command->num_parameters < SE_MAX_PARAMETERS); return; } command->parameters[command->num_parameters] = parameter; command->num_parameters += 1; } /***************************************************************************//** * @brief * Execute the passed command * * @details * This function starts the execution of the passed command by the secure * element. When started, wait for the RXINT interrupt flag, or call * @ref SE_waitCommandCompletion to busy-wait. After completion, you have to * call @ref SE_readCommandResponse to get the command's execution status. * * @param[in] command * Pointer to a filled-out SE command structure. ******************************************************************************/ void SE_executeCommand(SE_Command_t *command) { // Don't overflow our struct if (command->num_parameters > SE_MAX_PARAMETERS) { EFM_ASSERT(command->num_parameters <= SE_MAX_PARAMETERS); return; } // Wait for room available in the mailbox while (!(SEMAILBOX_HOST->TX_STATUS & SEMAILBOX_TX_STATUS_TXINT)) ; // Write header to start transaction SEMAILBOX_HOST->TX_HEADER = sizeof(uint32_t) * (4 + command->num_parameters); // Write command into FIFO SEMAILBOX_HOST->FIFO[0].DATA = command->command; // Write DMA descriptors into FIFO SEMAILBOX_HOST->FIFO[0].DATA = (uint32_t)command->data_in; SEMAILBOX_HOST->FIFO[0].DATA = (uint32_t)command->data_out; // Write applicable parameters into FIFO for (size_t i = 0; i < command->num_parameters; i++) { SEMAILBOX_HOST->FIFO[0].DATA = command->parameters[i]; } return; } /***************************************************************************//** * @brief * Writes data to User Data section in MTP. Write data must be aligned to words * and contain a number of bytes that is divisable by four. * @note * It is recommended to erase the flash page before performing a write. * * @param[in] offset * Offset to the flash word to write to. Must be aligned to words. * @param[in] data * Data to write to flash. * @param[in] numBytes * Number of bytes to write to flash. NB: Must be divisable by four. * @return * One of the SE_RESPONSE return codes. * @retval SE_RESPONSE_OK when the command was executed successfully or a * signature was successfully verified, * @retval SE_RESPONSE_INVALID_COMMAND when the command ID was not recognized, * @retval SE_RESPONSE_AUTHORIZATION_ERROR when the command is not authorized, * @retval SE_RESPONSE_INVALID_SIGNATURE when signature verification failed, * @retval SE_RESPONSE_BUS_ERROR when a bus error was thrown during the command, * e.g. because of conflicting Secure/Non-Secure * memory accesses, * @retval SE_RESPONSE_CRYPTO_ERROR on an internal SE failure, or * @retval SE_RESPONSE_INVALID_PARAMETER when an invalid parameter was passed ******************************************************************************/ SE_Response_t SE_writeUserData(uint32_t offset, void *data, uint32_t numBytes) { // SE command structures SE_Command_t command = SE_COMMAND_DEFAULT(SE_COMMAND_WRITE_USER_DATA); SE_DataTransfer_t userData = SE_DATATRANSFER_DEFAULT(data, numBytes); SE_addDataInput(&command, &userData); SE_addParameter(&command, offset); SE_addParameter(&command, numBytes); SE_executeCommand(&command); SE_Response_t res = SE_readCommandResponse(); return res; } /***************************************************************************//** * @brief * Erases User Data section in MTP. * @return * One of the SE_RESPONSE return codes. * @retval SE_RESPONSE_OK when the command was executed successfully or a * signature was successfully verified, * @retval SE_RESPONSE_INVALID_COMMAND when the command ID was not recognized, * @retval SE_RESPONSE_AUTHORIZATION_ERROR when the command is not authorized, * @retval SE_RESPONSE_INVALID_SIGNATURE when signature verification failed, * @retval SE_RESPONSE_BUS_ERROR when a bus error was thrown during the command, * e.g. because of conflicting Secure/Non-Secure * memory accesses, * @retval SE_RESPONSE_CRYPTO_ERROR on an internal SE failure, or * @retval SE_RESPONSE_INVALID_PARAMETER when an invalid parameter was passed ******************************************************************************/ SE_Response_t SE_eraseUserData() { // SE command structures SE_Command_t command = SE_COMMAND_DEFAULT(SE_COMMAND_ERASE_USER_DATA); SE_addParameter(&command, SE_COMMAND_OPTION_ERASE_UD); SE_executeCommand(&command); SE_Response_t res = SE_readCommandResponse(); return res; } /***************************************************************************//** * @brief * Returns the current boot status, versions and system configuration. * * @param[out] status * SE_Status_t containing current SE status. * * @return * One of the SE_RESPONSE return codes. * @retval SE_RESPONSE_OK upon command completion. Errors are encoded in the * different parts of the returned status object. ******************************************************************************/ SE_Response_t SE_getStatus(SE_Status_t *status) { volatile uint32_t output[9] = { 0 }; // SE command structures SE_Command_t command = SE_COMMAND_DEFAULT(SE_COMMAND_GET_STATUS); SE_DataTransfer_t outData = SE_DATATRANSFER_DEFAULT((void*)output, 4 * 9); SE_addDataOutput(&command, &outData); // Execute command and return response SE_executeCommand(&command); SE_Response_t res = SE_readCommandResponse(); // Update status object status->bootStatus = output[4]; status->seFwVersion = output[5]; status->hostFwVersion = output[6]; SE_DebugStatus_t debugStatus; debugStatus.debugLockEnabled = (output[7] & (1 << 0)); debugStatus.deviceEraseEnabled = (output[7] & (1 << 1)); debugStatus.secureDebugEnabled = (output[7] & (1 << 2)); status->debugStatus = debugStatus; status->secureBootEnabled = ((output[8] & 0x1) && ((output[8] & ~0x1) == 0)); return res; } /***************************************************************************//** * @brief * Read the serial number of the SE module. * * @param[out] serial * Pointer to array of size 16 bytes. * * @return * One of the SE_Response_t return codes. * @retval SE_RESPONSE_OK when serial number is returned successfully, * @retval SE_RESPONSE_INTERNAL_ERROR if not. ******************************************************************************/ SE_Response_t SE_serialNumber(void *serial) { // SE command structures SE_Command_t command = SE_COMMAND_DEFAULT(SE_COMMAND_READ_SERIAL); SE_DataTransfer_t outData = SE_DATATRANSFER_DEFAULT(serial, 16); SE_addDataOutput(&command, &outData); // Execute command and return response SE_executeCommand(&command); SE_Response_t res = SE_readCommandResponse(); return res; } /***************************************************************************//** * @brief * Read pubkey or pubkey signature. * * @details * Read out a public key stored in the SE, or its signature. The command can * be used to read: * * SE_KEY_TYPE_BOOT * * SE_KEY_TYPE_AUTH * * @param[in] key_type * ID of key type to read. * * @param[out] pubkey * Pointer to a buffer to contain the returned public key. * Must be word aligned and have a length of 64 bytes. * * @param[in] numBytes * Length of pubkey buffer (64 bytes). * * @param[in] signature * If true, read signature for the requested key type instead of the public * key. * * @return * One of the SE_RESPONSE return codes. * @retval SE_RESPONSE_OK when the command was executed successfully * @retval SE_RESPONSE_TEST_FAILED when the pubkey is not set * @retval SE_RESPONSE_INVALID_PARAMETER when an invalid type is passed ******************************************************************************/ SE_Response_t SE_readPubkey(uint32_t key_type, void *pubkey, uint32_t numBytes, bool signature) { EFM_ASSERT((key_type == SE_KEY_TYPE_BOOT) || (key_type == SE_KEY_TYPE_AUTH)); EFM_ASSERT(numBytes == 64); EFM_ASSERT(!((size_t)pubkey & 3U)); // SE command structures uint32_t commandWord = (signature) ? SE_COMMAND_READ_PUBKEY_SIGNATURE : SE_COMMAND_READ_PUBKEY; SE_Command_t command = SE_COMMAND_DEFAULT(commandWord | key_type); SE_DataTransfer_t pubkeyData = SE_DATATRANSFER_DEFAULT(pubkey, numBytes); SE_addDataOutput(&command, &pubkeyData); SE_executeCommand(&command); SE_Response_t res = SE_readCommandResponse(); return res; } /***************************************************************************//** * @brief * Init pubkey or pubkey signature. * * @details * Initialize public key stored in the SE, or its signature. The command can * be used to write: * * SE_KEY_TYPE_BOOT * * SE_KEY_TYPE_AUTH * * @note * These keys can not be overwritten, so this command can only be issued once * per key per part. * * @param[in] key_type * ID of key type to initialize. * * @param[in] pubkey * Pointer to a buffer that contains the public key or signature. * Must be word aligned and have a length of 64 bytes. * * @param[in] numBytes * Length of pubkey buffer (64 bytes). * * @param[in] signature * If true, initialize signature for the requested key type instead of the * public key. * * @return * One of the SE_RESPONSE return codes. * @retval SE_RESPONSE_OK when the command was executed successfully * @retval SE_RESPONSE_TEST_FAILED when the pubkey is not set * @retval SE_RESPONSE_INVALID_PARAMETER when an invalid type is passed ******************************************************************************/ SE_Response_t SE_initPubkey(uint32_t key_type, void *pubkey, uint32_t numBytes, bool signature) { EFM_ASSERT((key_type == SE_KEY_TYPE_BOOT) || (key_type == SE_KEY_TYPE_AUTH)); EFM_ASSERT(numBytes == 64); EFM_ASSERT(!((size_t)pubkey & 3U)); // Find parity word volatile uint32_t parity = 0; for (size_t i = 0; i < numBytes / 4; i++) { parity = parity ^ ((uint32_t *)pubkey)[i]; } // SE command structures uint32_t commandWord = (signature) ? SE_COMMAND_INIT_PUBKEY_SIGNATURE : SE_COMMAND_INIT_PUBKEY; SE_Command_t command = SE_COMMAND_DEFAULT(commandWord | key_type); SE_DataTransfer_t parityData = SE_DATATRANSFER_DEFAULT(&parity, 4); SE_addDataInput(&command, &parityData); SE_DataTransfer_t pubkeyData = SE_DATATRANSFER_DEFAULT(pubkey, numBytes); SE_addDataInput(&command, &pubkeyData); SE_executeCommand(&command); SE_Response_t res = SE_readCommandResponse(); return res; } /***************************************************************************//** * @brief * Initialize SE OTP configuration. * @return * One of the SE_RESPONSE return codes. * @retval SE_RESPONSE_OK when the command was executed successfully ******************************************************************************/ SE_Response_t SE_initOTP(SE_OTPInit_t *otp_init) { volatile uint32_t mcuSettingsFlags = 0; SE_Response_t res; if (otp_init->enableSecureBoot) { mcuSettingsFlags |= SE_OTP_MCU_SETTINGS_FLAG_SECURE_BOOT_ENABLE; uint8_t pubkey[64]; res = SE_readPubkey(SE_KEY_TYPE_BOOT, &pubkey, 64, false); if (res != SE_RESPONSE_OK) { return SE_RESPONSE_ABORT; } } if (otp_init->verifySecureBootCertificate) { mcuSettingsFlags |= SE_OTP_MCU_SETTINGS_FLAG_SECURE_BOOT_VERIFY_CERTIFICATE; } if (otp_init->enableAntiRollback) { mcuSettingsFlags |= SE_OTP_MCU_SETTINGS_FLAG_SECURE_BOOT_ANTI_ROLLBACK; } volatile struct ReservedSettings { uint8_t reserved1[16]; uint8_t reserved2[2]; uint8_t reserved3[2]; } reservedSettings = { { 0x00 }, { 0xFF }, { 0x00 } }; // Find parity word uint32_t parity = 0; parity = parity ^ mcuSettingsFlags; for (size_t i = 0; i < 5; i++) { parity = parity ^ ((uint32_t*)(&reservedSettings))[i]; } // SE command structures SE_Command_t command = SE_COMMAND_DEFAULT(SE_COMMAND_INIT_OTP); volatile uint32_t parameters[2] = { parity, sizeof(mcuSettingsFlags) + sizeof(reservedSettings) }; SE_DataTransfer_t parametersData = SE_DATATRANSFER_DEFAULT(¶meters, 8); SE_addDataInput(&command, ¶metersData); SE_DataTransfer_t mcuSettingsFlagsData = SE_DATATRANSFER_DEFAULT(&mcuSettingsFlags, sizeof(mcuSettingsFlags)); SE_addDataInput(&command, &mcuSettingsFlagsData); SE_DataTransfer_t reservedSettingsData = SE_DATATRANSFER_DEFAULT(&reservedSettings, sizeof(reservedSettings)); SE_addDataInput(&command, &reservedSettingsData); SE_executeCommand(&command); res = SE_readCommandResponse(); return res; } /***************************************************************************//** * @brief * Returns the current debug lock configuration. * @param[out] status * The command returns a DebugStatus_t with the current status of the * debug configuration. * @return * One of the SE_RESPONSE return codes. * @retval SE_RESPONSE_OK when the command was executed successfully. * @retval SE_RESPONSE_INTERNAL_ERROR if there are configuration errors. ******************************************************************************/ SE_Response_t SE_debugLockStatus(SE_DebugStatus_t *status) { SE_Response_t res; // SE command structures SE_Command_t command = SE_COMMAND_DEFAULT(SE_COMMAND_DBG_LOCK_STATUS); volatile uint32_t status_word = 0; SE_DataTransfer_t statusData = SE_DATATRANSFER_DEFAULT((void*)&status_word, 4); SE_addDataOutput(&command, &statusData); SE_executeCommand(&command); res = SE_readCommandResponse(); status->debugLockEnabled = (status_word & (1 << 0)); status->deviceEraseEnabled = (status_word & (1 << 1)); status->secureDebugEnabled = (status_word & (1 << 2)); return res; } /***************************************************************************//** * @brief * Enables the debug lock for the part. * @details * The debug port will be closed and the only way to open it is through * device erase (if enabled) or through secure debug unlock (if enabled). * @return * One of the SE_RESPONSE return codes. * @retval SE_RESPONSE_OK when the command was executed successfully. * @retval SE_RESPONSE_INTERNAL_ERROR there was a problem locking the debug port. ******************************************************************************/ SE_Response_t SE_debugLockApply() { SE_Command_t command = SE_COMMAND_DEFAULT(SE_COMMAND_DBG_LOCK_APPLY); SE_executeCommand(&command); return SE_readCommandResponse(); } /***************************************************************************//** * @brief * Enables the secure debug functionality. * @details * Enables the secure debug functionality that can be used to open a locked * debug port through the Get challenge and Open debug commands. This command * can only be executed before the debug port is locked, and after a secure * debug public key has been installed in the SE. * @return * One of the SE_RESPONSE return codes. * @retval SE_RESPONSE_OK when the command was executed successfully. * @retval SE_RESPONSE_INVALID_COMMAND if debug port is locked. * @retval SE_RESPONSE_INVALID_PARAMETER if secure debug certificates are * missing. * @retval SE_RESPONSE_INTERNAL_ERROR if there was a problem during execution. ******************************************************************************/ SE_Response_t SE_debugSecureEnable() { SE_Command_t command = SE_COMMAND_DEFAULT(SE_COMMAND_DBG_LOCK_ENABLE_SECURE); SE_executeCommand(&command); return SE_readCommandResponse(); } /***************************************************************************//** * @brief * Disables the secure debug functionality. * @details * Disables the secure debug functionality that can be used to open a * locked debug port. * @return * One of the SE_RESPONSE return codes. * @retval SE_RESPONSE_OK when the command was executed successfully. * @retval SE_RESPONSE_INTERNAL_ERROR if there was a problem during execution. ******************************************************************************/ SE_Response_t SE_debugSecureDisable() { SE_Command_t command = SE_COMMAND_DEFAULT(SE_COMMAND_DBG_LOCK_DISABLE_SECURE); SE_executeCommand(&command); return SE_readCommandResponse(); } /***************************************************************************//** * @brief * Performs a device mass erase and debug unlock. * * @details * Performs a device mass erase and resets the debug configuration to its * initial unlocked state. Only available before DEVICE_ERASE_DISABLE has * been executed. * * @note * This command clears and verifies the complete flash and ram of the * system, excluding the user data pages and one-time programmable * commissioning information in the secure element. * * @return * One of the SE_RESPONSE return codes. * @retval SE_RESPONSE_OK when the command was executed successfully. * @retval SE_RESPONSE_INVALID_COMMAND if device erase is disabled. * @retval SE_RESPONSE_INTERNAL_ERROR if there was a problem during execution. ******************************************************************************/ SE_Response_t SE_deviceErase() { SE_Command_t command = SE_COMMAND_DEFAULT(SE_COMMAND_DEVICE_ERASE); SE_executeCommand(&command); return SE_readCommandResponse(); } /***************************************************************************//** * @brief * Disabled device erase functionality. * * @details * This command disables the device erase command. It does not lock the * debug interface to the part, but it is a permanent action for the part. * If device erase is disabled and the device is debug locked, there is no * way to permanently unlock the part. If secure debug unlock is enabled, * secure debug unlock can still be used to temporarily open the debug port. * * @warning * This command permanently disables the device erase functionality! * * @return * One of the SE_RESPONSE return codes. * @retval SE_RESPONSE_OK when the command was executed successfully. * @retval SE_RESPONSE_INTERNAL_ERROR if there was a problem during execution. ******************************************************************************/ SE_Response_t SE_deviceEraseDisable() { SE_Command_t command = SE_COMMAND_DEFAULT(SE_COMMAND_DEVICE_ERASE_DISABLE); SE_executeCommand(&command); return SE_readCommandResponse(); } /** @} (end addtogroup SE) */ /** @} (end addtogroup emlib) */ #endif /* defined(SEMAILBOX_PRESENT) */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/emlib/src/em_system.c.
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/***************************************************************************//** * @file * @brief System Peripheral API * @version 5.7.0 ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * SPDX-License-Identifier: Zlib * * The licensor of this software is Silicon Laboratories Inc. * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be * appreciated but is not required. * 2. Altered source versions must be plainly marked as such, and must not be * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * ******************************************************************************/ #include "em_system.h" #include "em_assert.h" #include <stddef.h> /***************************************************************************//** * @addtogroup emlib * @{ ******************************************************************************/ /***************************************************************************//** * @addtogroup SYSTEM * @{ ******************************************************************************/ /******************************************************************************* ************************** GLOBAL FUNCTIONS ******************************* ******************************************************************************/ /***************************************************************************//** * @brief * Get a chip major/minor revision. * * @param[out] rev * A location to place the chip revision information. ******************************************************************************/ void SYSTEM_ChipRevisionGet(SYSTEM_ChipRevision_TypeDef *rev) { #if defined(_SYSCFG_CHIPREV_FAMILY_MASK) /* On series-2 (and higher) the revision info is in the SYSCFG->CHIPREV register. */ uint32_t chiprev = SYSCFG->CHIPREV; rev->family = (chiprev & _SYSCFG_CHIPREV_FAMILY_MASK) >> _SYSCFG_CHIPREV_FAMILY_SHIFT; rev->major = (chiprev & _SYSCFG_CHIPREV_MAJOR_MASK) >> _SYSCFG_CHIPREV_MAJOR_SHIFT; rev->minor = (chiprev & _SYSCFG_CHIPREV_MINOR_MASK) >> _SYSCFG_CHIPREV_MINOR_SHIFT; #else uint8_t tmp; EFM_ASSERT(rev); /* CHIP FAMILY bit [5:2] */ tmp = (uint8_t)(((ROMTABLE->PID1 & _ROMTABLE_PID1_FAMILYMSB_MASK) >> _ROMTABLE_PID1_FAMILYMSB_SHIFT) << 2); /* CHIP FAMILY bit [1:0] */ tmp |= (uint8_t)((ROMTABLE->PID0 & _ROMTABLE_PID0_FAMILYLSB_MASK) >> _ROMTABLE_PID0_FAMILYLSB_SHIFT); rev->family = tmp; /* CHIP MAJOR bit [3:0] */ rev->major = (uint8_t)((ROMTABLE->PID0 & _ROMTABLE_PID0_REVMAJOR_MASK) >> _ROMTABLE_PID0_REVMAJOR_SHIFT); /* CHIP MINOR bit [7:4] */ tmp = (uint8_t)(((ROMTABLE->PID2 & _ROMTABLE_PID2_REVMINORMSB_MASK) >> _ROMTABLE_PID2_REVMINORMSB_SHIFT) << 4); /* CHIP MINOR bit [3:0] */ tmp |= (uint8_t)((ROMTABLE->PID3 & _ROMTABLE_PID3_REVMINORLSB_MASK) >> _ROMTABLE_PID3_REVMINORLSB_SHIFT); rev->minor = tmp; #endif } /***************************************************************************//** * @brief * Get a factory calibration value for a given peripheral register. * * @param[in] regAddress * The peripheral calibration register address to get a calibration value for. If * the calibration value is found, this register is updated with the * calibration value. * * @return * True if a calibration value exists, false otherwise. ******************************************************************************/ bool SYSTEM_GetCalibrationValue(volatile uint32_t *regAddress) { SYSTEM_CalAddrVal_TypeDef * p, * end; #if defined(MSC_FLASH_CHIPCONFIG_MEM_BASE) p = (SYSTEM_CalAddrVal_TypeDef *)MSC_FLASH_CHIPCONFIG_MEM_BASE; end = (SYSTEM_CalAddrVal_TypeDef *)MSC_FLASH_CHIPCONFIG_MEM_END; #else p = (SYSTEM_CalAddrVal_TypeDef *)(DEVINFO_BASE & 0xFFFFF000U); end = (SYSTEM_CalAddrVal_TypeDef *)DEVINFO_BASE; #endif for (; p < end; p++) { if (p->address == 0) { /* p->address == 0 marks the end of the table */ return false; } if (p->address == (uint32_t)regAddress) { *regAddress = p->calValue; return true; } } /* Nothing found for regAddress. */ return false; } /** @} (end addtogroup SYSTEM) */ /** @} (end addtogroup emlib) */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/emlib/src/em_timer.c.
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/***************************************************************************//** * @file * @brief Timer/counter (TIMER) Peripheral API * @version 5.7.0 ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * SPDX-License-Identifier: Zlib * * The licensor of this software is Silicon Laboratories Inc. * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be * appreciated but is not required. * 2. Altered source versions must be plainly marked as such, and must not be * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * ******************************************************************************/ #include "em_timer.h" #if defined(TIMER_COUNT) && (TIMER_COUNT > 0) #include "em_assert.h" /***************************************************************************//** * @addtogroup emlib * @{ ******************************************************************************/ /***************************************************************************//** * @addtogroup TIMER * @brief Timer/Counter (TIMER) Peripheral API * @details * The timer module consists of three main parts: * @li General timer configuration and enable control. * @li Compare/capture control. * @li Dead time insertion control (may not be available for all timers). * @{ ******************************************************************************/ /******************************************************************************* ************************** LOCAL FUNCTIONS ******************************** ******************************************************************************/ /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ #if defined(_PRS_CONSUMER_TIMER0_CC0_MASK) /** Map TIMER reference to index of device. */ #define TIMER_DEVICE_ID(timer) ( \ (timer) == TIMER0 ? 0 \ : (timer) == TIMER1 ? 1 \ : (timer) == TIMER2 ? 2 \ : (timer) == TIMER3 ? 3 \ : -1) #define TIMER_INPUT_CHANNEL_DTI 3UL #define TIMER_INPUT_CHANNEL_DTIFS1 4UL #define TIMER_INPUT_CHANNEL_DTIFS2 5UL /** * TIMER PRS registers are moved into the PRS register space on series 2 devices. * The PRS Consumer registers for a timer consist of 6 registers. * * [0] - CC0 PRS Consumer * [1] - CC1 PRS Consumer * [2] - CC2 PRS Consumer * [3] - DTI PRS Consumer * [4] - DTIFS1 PRS Consumer * [5] - DTIFS2 PRS Consumer */ typedef struct { __IOM uint32_t CONSUMER_CH[6]; /**< TIMER PRS consumers. */ } PRS_TIMERn_Consumer_TypeDef; typedef struct { PRS_TIMERn_Consumer_TypeDef TIMER_CONSUMER[TIMER_COUNT]; } PRS_TIMERn_TypeDef; /** * @brief Configure a timer capture/compare channel to use a PRS channel as input. * * @param[in] timer * * @param[in] cc * Timer input channel. Valid input is 0-5. * 0 - CC0 * 1 - CC1 * 2 - CC2 * 3 - DTI * 4 - DTIFS1 * 5 - DTIFS2 * * @param[in] prsCh * PRS channel number. * * @param[in] async * true for asynchronous PRS channel, false for synchronous PRS channel. */ static void timerPrsConfig(TIMER_TypeDef * timer, unsigned int cc, unsigned int prsCh, bool async) { int i = TIMER_DEVICE_ID(timer); PRS_TIMERn_TypeDef * base = (PRS_TIMERn_TypeDef *) &PRS->CONSUMER_TIMER0_CC0; EFM_ASSERT(i != -1); if (async) { base->TIMER_CONSUMER[i].CONSUMER_CH[cc] = prsCh << _PRS_CONSUMER_TIMER0_CC0_PRSSEL_SHIFT; } else { base->TIMER_CONSUMER[i].CONSUMER_CH[cc] = prsCh << _PRS_CONSUMER_TIMER0_CC0_SPRSSEL_SHIFT; } } #endif /** @endcond */ /******************************************************************************* ************************** GLOBAL FUNCTIONS ******************************* ******************************************************************************/ /***************************************************************************//** * @brief * Initialize TIMER. * * @details * Notice that the counter top must be configured separately with, for instance * TIMER_TopSet(). In addition, compare/capture and dead-time insertion * initialization must be initialized separately if used, which should probably * be done prior to using this function if configuring the TIMER to * start when initialization is completed. * * @param[in] timer * A pointer to the TIMER peripheral register block. * * @param[in] init * A pointer to the TIMER initialization structure. ******************************************************************************/ void TIMER_Init(TIMER_TypeDef *timer, const TIMER_Init_TypeDef *init) { EFM_ASSERT(TIMER_REF_VALID(timer)); uint32_t ctrlRegVal = 0; #if defined (_TIMER_CFG_PRESC_SHIFT) timer->EN_CLR = TIMER_EN_EN; timer->CFG = ((uint32_t)init->prescale << _TIMER_CFG_PRESC_SHIFT) | ((uint32_t)init->clkSel << _TIMER_CFG_CLKSEL_SHIFT) | ((uint32_t)init->mode << _TIMER_CFG_MODE_SHIFT) | (init->debugRun ? TIMER_CFG_DEBUGRUN : 0) | (init->dmaClrAct ? TIMER_CFG_DMACLRACT : 0) | (init->quadModeX4 ? TIMER_CFG_QDM_X4 : 0) | (init->oneShot ? TIMER_CFG_OSMEN : 0) | (init->sync ? TIMER_CFG_SYNC : 0) | (init->ati ? TIMER_CFG_ATI : 0); timer->EN_SET = TIMER_EN_EN; #endif /* Stop the timer if specified to be disabled (doesn't hurt if already stopped). */ if (!(init->enable)) { timer->CMD = TIMER_CMD_STOP; } /* Reset the counter. */ timer->CNT = _TIMER_CNT_RESETVALUE; #if defined(_SILICON_LABS_32B_SERIES_2) ctrlRegVal = ((uint32_t)init->fallAction << _TIMER_CTRL_FALLA_SHIFT) | ((uint32_t)init->riseAction << _TIMER_CTRL_RISEA_SHIFT) | (init->count2x ? TIMER_CTRL_X2CNT : 0); #else ctrlRegVal = ((uint32_t)init->prescale << _TIMER_CTRL_PRESC_SHIFT) | ((uint32_t)init->clkSel << _TIMER_CTRL_CLKSEL_SHIFT) | ((uint32_t)init->fallAction << _TIMER_CTRL_FALLA_SHIFT) | ((uint32_t)init->riseAction << _TIMER_CTRL_RISEA_SHIFT) | ((uint32_t)init->mode << _TIMER_CTRL_MODE_SHIFT) | (init->debugRun ? TIMER_CTRL_DEBUGRUN : 0) | (init->dmaClrAct ? TIMER_CTRL_DMACLRACT : 0) | (init->quadModeX4 ? TIMER_CTRL_QDM_X4 : 0) | (init->oneShot ? TIMER_CTRL_OSMEN : 0) | (init->sync ? TIMER_CTRL_SYNC : 0); #if defined(TIMER_CTRL_X2CNT) && defined(TIMER_CTRL_ATI) ctrlRegVal |= (init->count2x ? TIMER_CTRL_X2CNT : 0) | (init->ati ? TIMER_CTRL_ATI : 0); #endif #endif timer->CTRL = ctrlRegVal; /* Start the timer if specified to be enabled (doesn't hurt if already started). */ if (init->enable) { timer->CMD = TIMER_CMD_START; } } /***************************************************************************//** * @brief * Initialize the TIMER compare/capture channel. * * @details * Notice that if operating the channel in compare mode, the CCV and CCVB register * must be set separately, as required. * * @param[in] timer * A pointer to the TIMER peripheral register block. * * @param[in] ch * A compare/capture channel to initialize for. * * @param[in] init * A pointer to the TIMER initialization structure. ******************************************************************************/ void TIMER_InitCC(TIMER_TypeDef *timer, unsigned int ch, const TIMER_InitCC_TypeDef *init) { EFM_ASSERT(TIMER_REF_VALID(timer)); EFM_ASSERT(TIMER_CH_VALID(ch)); #if defined (_TIMER_CC_CFG_MASK) timer->EN_CLR = TIMER_EN_EN; timer->CC[ch].CFG = ((uint32_t)init->mode << _TIMER_CC_CFG_MODE_SHIFT) | (init->filter ? TIMER_CC_CFG_FILT_ENABLE : 0) | (init->coist ? TIMER_CC_CFG_COIST : 0) | ((uint32_t)init->prsOutput << _TIMER_CC_CFG_PRSCONF_SHIFT); if (init->prsInput) { timer->CC[ch].CFG |= (uint32_t)init->prsInputType << _TIMER_CC_CFG_INSEL_SHIFT; bool async = (init->prsInputType != timerPrsInputSync); timerPrsConfig(timer, ch, init->prsSel, async); } else { timer->CC[ch].CFG |= TIMER_CC_CFG_INSEL_PIN; } timer->EN_SET = TIMER_EN_EN; timer->CC[ch].CTRL = ((uint32_t)init->eventCtrl << _TIMER_CC_CTRL_ICEVCTRL_SHIFT) | ((uint32_t)init->edge << _TIMER_CC_CTRL_ICEDGE_SHIFT) | ((uint32_t)init->cufoa << _TIMER_CC_CTRL_CUFOA_SHIFT) | ((uint32_t)init->cofoa << _TIMER_CC_CTRL_COFOA_SHIFT) | ((uint32_t)init->cmoa << _TIMER_CC_CTRL_CMOA_SHIFT) | (init->outInvert ? TIMER_CC_CTRL_OUTINV : 0); #else timer->CC[ch].CTRL = ((uint32_t)init->eventCtrl << _TIMER_CC_CTRL_ICEVCTRL_SHIFT) | ((uint32_t)init->edge << _TIMER_CC_CTRL_ICEDGE_SHIFT) | ((uint32_t)init->prsSel << _TIMER_CC_CTRL_PRSSEL_SHIFT) | ((uint32_t)init->cufoa << _TIMER_CC_CTRL_CUFOA_SHIFT) | ((uint32_t)init->cofoa << _TIMER_CC_CTRL_COFOA_SHIFT) | ((uint32_t)init->cmoa << _TIMER_CC_CTRL_CMOA_SHIFT) | ((uint32_t)init->mode << _TIMER_CC_CTRL_MODE_SHIFT) | (init->filter ? TIMER_CC_CTRL_FILT_ENABLE : 0) | (init->prsInput ? TIMER_CC_CTRL_INSEL_PRS : 0) | (init->coist ? TIMER_CC_CTRL_COIST : 0) | (init->outInvert ? TIMER_CC_CTRL_OUTINV : 0) #if defined(_TIMER_CC_CTRL_PRSCONF_MASK) | ((uint32_t)init->prsOutput << _TIMER_CC_CTRL_PRSCONF_SHIFT) #endif ; #endif } #if defined(_TIMER_DTCTRL_MASK) /***************************************************************************//** * @brief * Initialize the TIMER DTI unit. * * @param[in] timer * A pointer to the TIMER peripheral register block. * * @param[in] init * A pointer to the TIMER DTI initialization structure. ******************************************************************************/ void TIMER_InitDTI(TIMER_TypeDef *timer, const TIMER_InitDTI_TypeDef *init) { EFM_ASSERT(TIMER0 == timer); /* Make sure the DTI unit is disabled while initializing. */ TIMER_EnableDTI(timer, false); #if defined (_TIMER_DTCFG_MASK) timer->EN_CLR = TIMER_EN_EN; timer->DTCFG = (init->autoRestart ? TIMER_DTCFG_DTDAS : 0) | (init->enablePrsSource ? TIMER_DTCFG_DTPRSEN : 0); if (init->enablePrsSource) { timerPrsConfig(timer, TIMER_INPUT_CHANNEL_DTI, init->prsSel, true); } timer->DTTIMECFG = ((uint32_t)init->prescale << _TIMER_DTTIMECFG_DTPRESC_SHIFT) | ((uint32_t)init->riseTime << _TIMER_DTTIMECFG_DTRISET_SHIFT) | ((uint32_t)init->fallTime << _TIMER_DTTIMECFG_DTFALLT_SHIFT); timer->DTFCFG = (init->enableFaultSourceCoreLockup ? TIMER_DTFCFG_DTLOCKUPFEN : 0) | (init->enableFaultSourceDebugger ? TIMER_DTFCFG_DTDBGFEN : 0) | (init->enableFaultSourcePrsSel0 ? TIMER_DTFCFG_DTPRS0FEN : 0) | (init->enableFaultSourcePrsSel1 ? TIMER_DTFCFG_DTPRS1FEN : 0) | ((uint32_t)(init->faultAction) << _TIMER_DTFCFG_DTFA_SHIFT); if (init->enableFaultSourcePrsSel0) { timerPrsConfig(timer, TIMER_INPUT_CHANNEL_DTIFS1, init->faultSourcePrsSel0, true); } if (init->enableFaultSourcePrsSel1) { timerPrsConfig(timer, TIMER_INPUT_CHANNEL_DTIFS2, init->faultSourcePrsSel1, true); } timer->EN_SET = TIMER_EN_EN; #endif #if defined(TIMER_DTCTRL_DTDAS) /* Set up the DTCTRL register. The enable bit will be set at the end of the function if specified. */ timer->DTCTRL = (init->autoRestart ? TIMER_DTCTRL_DTDAS : 0) | (init->activeLowOut ? TIMER_DTCTRL_DTIPOL : 0) | (init->invertComplementaryOut ? TIMER_DTCTRL_DTCINV : 0) | (init->enablePrsSource ? TIMER_DTCTRL_DTPRSEN : 0) | ((uint32_t)(init->prsSel) << _TIMER_DTCTRL_DTPRSSEL_SHIFT); #endif #if defined (TIMER_DTCFG_DTDAS) timer->DTCTRL = (init->activeLowOut ? TIMER_DTCTRL_DTIPOL : 0) | (init->invertComplementaryOut ? TIMER_DTCTRL_DTCINV : 0); #endif #if defined (_TIMER_DTTIME_DTPRESC_SHIFT) /* Set up the DTTIME register. */ timer->DTTIME = ((uint32_t)init->prescale << _TIMER_DTTIME_DTPRESC_SHIFT) | ((uint32_t)init->riseTime << _TIMER_DTTIME_DTRISET_SHIFT) | ((uint32_t)init->fallTime << _TIMER_DTTIME_DTFALLT_SHIFT); #endif #if defined (TIMER_DTFC_DTLOCKUPFEN) /* Set up the DTFC register. */ timer->DTFC = (init->enableFaultSourceCoreLockup ? TIMER_DTFC_DTLOCKUPFEN : 0) | (init->enableFaultSourceDebugger ? TIMER_DTFC_DTDBGFEN : 0) | (init->enableFaultSourcePrsSel0 ? TIMER_DTFC_DTPRS0FEN : 0) | (init->enableFaultSourcePrsSel1 ? TIMER_DTFC_DTPRS1FEN : 0) | ((uint32_t)init->faultAction << _TIMER_DTFC_DTFA_SHIFT) | ((uint32_t)init->faultSourcePrsSel0 << _TIMER_DTFC_DTPRS0FSEL_SHIFT) | ((uint32_t)init->faultSourcePrsSel1 << _TIMER_DTFC_DTPRS1FSEL_SHIFT); #endif /* Set up the DTOGEN register. */ timer->DTOGEN = init->outputsEnableMask; /* Clear any previous DTI faults. */ TIMER_ClearDTIFault(timer, TIMER_GetDTIFault(timer)); /* Enable/disable before returning. */ TIMER_EnableDTI(timer, init->enable); } #endif /***************************************************************************//** * @brief * Reset the TIMER to the same state that it was in after a hardware reset. * * @note * The ROUTE register is NOT reset by this function to allow for * a centralized setup of this feature. * * @param[in] timer * A pointer to the TIMER peripheral register block. ******************************************************************************/ void TIMER_Reset(TIMER_TypeDef *timer) { int i; EFM_ASSERT(TIMER_REF_VALID(timer)); /* Make sure disabled first, before resetting other registers. */ timer->CMD = TIMER_CMD_STOP; timer->CTRL = _TIMER_CTRL_RESETVALUE; timer->IEN = _TIMER_IEN_RESETVALUE; #if defined (TIMER_HAS_SET_CLEAR) timer->IF_CLR = _TIMER_IF_MASK; #else timer->IFC = _TIMER_IFC_MASK; #endif timer->TOPB = _TIMER_TOPB_RESETVALUE; /* Write TOP after TOPB to invalidate TOPB (clear TIMER_STATUS_TOPBV). */ timer->TOP = _TIMER_TOP_RESETVALUE; timer->CNT = _TIMER_CNT_RESETVALUE; /* Do not reset the route register, setting should be done independently. */ /* Note: The ROUTE register may be locked by the DTLOCK register. */ for (i = 0; TIMER_CH_VALID(i); i++) { timer->CC[i].CTRL = _TIMER_CC_CTRL_RESETVALUE; #if defined (_TIMER_CC_CCV_RESETVALUE) && defined (_TIMER_CC_CCVB_RESETVALUE) timer->CC[i].CCV = _TIMER_CC_CCV_RESETVALUE; timer->CC[i].CCVB = _TIMER_CC_CCVB_RESETVALUE; #endif #if defined (_TIMER_CC_OC_RESETVALUE) && defined (_TIMER_CC_OCB_RESETVALUE) \ && defined (_TIMER_CC_ICF_RESETVALUE) && defined (_TIMER_CC_ICOF_RESETVALUE) timer->CC[i].OC = _TIMER_CC_OC_RESETVALUE; timer->CC[i].OCB = _TIMER_CC_OCB_RESETVALUE; #endif } /* Reset dead time insertion module, which has no effect on timers without DTI. */ #if defined(_TIMER_DTCFG_MASK) timer->DTLOCK = TIMER_DTLOCK_DTILOCKKEY_UNLOCK; timer->DTCTRL = _TIMER_DTCTRL_RESETVALUE; timer->DTOGEN = _TIMER_DTOGEN_RESETVALUE; timer->DTFAULTC = _TIMER_DTFAULTC_MASK; #elif defined(TIMER_DTLOCK_LOCKKEY_UNLOCK) /* Unlock DTI registers first if locked. */ timer->DTLOCK = TIMER_DTLOCK_LOCKKEY_UNLOCK; timer->DTCTRL = _TIMER_DTCTRL_RESETVALUE; timer->DTTIME = _TIMER_DTTIME_RESETVALUE; timer->DTFC = _TIMER_DTFC_RESETVALUE; timer->DTOGEN = _TIMER_DTOGEN_RESETVALUE; timer->DTFAULTC = _TIMER_DTFAULTC_MASK; #endif #if defined(_TIMER_CFG_MASK) /* CFG registers must be reset after the timer is disabled */ timer->EN_CLR = TIMER_EN_EN; timer->CFG = _TIMER_CFG_RESETVALUE; for (i = 0; TIMER_CH_VALID(i); i++) { timer->CC[i].CFG = _TIMER_CC_CFG_RESETVALUE; } timer->DTCFG = _TIMER_DTCFG_RESETVALUE; timer->DTFCFG = _TIMER_DTFCFG_RESETVALUE; timer->DTTIMECFG = _TIMER_DTTIMECFG_RESETVALUE; #endif } /** @} (end addtogroup TIMER) */ /** @} (end addtogroup emlib) */ #endif /* defined(TIMER_COUNT) && (TIMER_COUNT > 0) */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/emlib/src/em_usart.c.
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/***************************************************************************//** * @file * @brief Universal synchronous/asynchronous receiver/transmitter (USART/UART) * Peripheral API * @version 5.7.0 ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * SPDX-License-Identifier: Zlib * * The licensor of this software is Silicon Laboratories Inc. * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be * appreciated but is not required. * 2. Altered source versions must be plainly marked as such, and must not be * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * ******************************************************************************/ #include "em_usart.h" #if defined(USART_COUNT) && (USART_COUNT > 0) #include "em_cmu.h" #include "em_bus.h" #include "em_assert.h" #if defined(USART_CTRLX_CTSEN) #include "em_gpio.h" #endif /***************************************************************************//** * @addtogroup emlib * @{ ******************************************************************************/ /***************************************************************************//** * @addtogroup USART * @{ ******************************************************************************/ /******************************************************************************* ******************************* DEFINES *********************************** ******************************************************************************/ /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ /** Validation of USART register block pointer reference for assert statements. */ #if (USART_COUNT == 1) && defined(USART0) #define USART_REF_VALID(ref) ((ref) == USART0) #elif (USART_COUNT == 1) && defined(USART1) #define USART_REF_VALID(ref) ((ref) == USART1) #elif (USART_COUNT == 2) && defined(USART2) #define USART_REF_VALID(ref) (((ref) == USART1) || ((ref) == USART2)) #elif (USART_COUNT == 2) #define USART_REF_VALID(ref) (((ref) == USART0) || ((ref) == USART1)) #elif (USART_COUNT == 3) #define USART_REF_VALID(ref) (((ref) == USART0) || ((ref) == USART1) \ || ((ref) == USART2)) #elif (USART_COUNT == 4) #define USART_REF_VALID(ref) (((ref) == USART0) || ((ref) == USART1) \ || ((ref) == USART2) || ((ref) == USART3)) #elif (USART_COUNT == 5) #define USART_REF_VALID(ref) (((ref) == USART0) || ((ref) == USART1) \ || ((ref) == USART2) || ((ref) == USART3) \ || ((ref) == USART4)) #elif (USART_COUNT == 6) #define USART_REF_VALID(ref) (((ref) == USART0) || ((ref) == USART1) \ || ((ref) == USART2) || ((ref) == USART3) \ || ((ref) == USART4) || ((ref) == USART5)) #else #error "Undefined number of USARTs." #endif #if defined(USARTRF_COUNT) && (USARTRF_COUNT > 0) #if (USARTRF_COUNT == 1) && defined(USARTRF0) #define USARTRF_REF_VALID(ref) ((ref) == USARTRF0) #elif (USARTRF_COUNT == 1) && defined(USARTRF1) #define USARTRF_REF_VALID(ref) ((ref) == USARTRF1) #else #define USARTRF_REF_VALID(ref) (0) #endif #else #define USARTRF_REF_VALID(ref) (0) #endif #if (_SILICON_LABS_32B_SERIES == 2) #define USART_IRDA_VALID(ref) USART_REF_VALID(ref) #elif defined(_SILICON_LABS_32B_SERIES_1) #if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_100) || defined(_SILICON_LABS_GECKO_INTERNAL_SDID_103) // If GG11 or TG11 #define USART_IRDA_VALID(ref) (((ref) == USART0) || ((ref) == USART2)) #elif defined(USART3) #define USART_IRDA_VALID(ref) (((ref) == USART0) || ((ref) == USART1) || ((ref) == USART2) || ((ref) == USART3)) #elif defined(USART2) #define USART_IRDA_VALID(ref) (((ref) == USART0) || ((ref) == USART1) || ((ref) == USART2)) #else #define USART_IRDA_VALID(ref) (((ref) == USART0) || ((ref) == USART1)) #endif #elif defined(_SILICON_LABS_32B_SERIES_0) #if defined(_EZR32_HAPPY_FAMILY) #define USART_IRDA_VALID(ref) ((ref) == USART0) #elif defined(_EFM32_HAPPY_FAMILY) #define USART_IRDA_VALID(ref) (((ref) == USART0) || ((ref) == USART1)) #elif defined(USART0) #define USART_IRDA_VALID(ref) ((ref) == USART0) #elif (USART_COUNT == 1) && defined(USART1) #define USART_IRDA_VALID(ref) ((ref) == USART1) #elif defined(USARTRF0) #define USART_IRDA_VALID(ref) ((ref) == USARTRF0) #else #define USART_IRDA_VALID(ref) (0) #endif #endif #if (_SILICON_LABS_32B_SERIES == 2) #define USART_I2S_VALID(ref) USART_REF_VALID(ref) #elif defined(_SILICON_LABS_32B_SERIES_1) #if defined(USART4) #define USART_I2S_VALID(ref) (((ref) == USART1) || ((ref) == USART3) || ((ref) == USART4)) #elif defined(USART3) #define USART_I2S_VALID(ref) (((ref) == USART1) || ((ref) == USART3)) #else #define USART_I2S_VALID(ref) ((ref) == USART1) #endif #elif defined(_SILICON_LABS_32B_SERIES_0) #if defined(_EZR32_HAPPY_FAMILY) #define USART_I2S_VALID(ref) ((ref) == USART0) #elif defined(_EFM32_HAPPY_FAMILY) #define USART_I2S_VALID(ref) (((ref) == USART0) || ((ref) == USART1)) #elif defined(_EFM32_TINY_FAMILY) || defined(_EFM32_ZERO_FAMILY) #define USART_I2S_VALID(ref) ((ref) == USART1) #elif defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY) #define USART_I2S_VALID(ref) (((ref) == USART1) || ((ref) == USART2)) #endif #endif #if (UART_COUNT == 1) #define UART_REF_VALID(ref) ((ref) == UART0) #elif (UART_COUNT == 2) #define UART_REF_VALID(ref) (((ref) == UART0) || ((ref) == UART1)) #else #define UART_REF_VALID(ref) (0) #endif #if defined(_USART_CLKDIV_DIVEXT_MASK) #define CLKDIV_MASK (_USART_CLKDIV_DIV_MASK | _USART_CLKDIV_DIVEXT_MASK) #else #define CLKDIV_MASK _USART_CLKDIV_DIV_MASK #endif /** @endcond */ /******************************************************************************* ************************** LOCAL FUNCTIONS ******************************** ******************************************************************************/ #if !defined(_EFM32_GECKO_FAMILY) /***************************************************************************//** * @brief * Configure a PRS channel as USART Rx input * * @param[in] usart * A pointer to the USART/UART peripheral register block. * * @param[in] ch * PRS channel. ******************************************************************************/ static void prsRxInput(USART_TypeDef *usart, USART_PRS_Channel_t ch) { #if defined(_USART_INPUT_MASK) usart->INPUT = ((uint32_t)ch << _USART_INPUT_RXPRSSEL_SHIFT) | USART_INPUT_RXPRS; #elif defined(USART_CTRLX_RXPRSEN) if (usart == USART0) { PRS->CONSUMER_USART0_RX = ch; } else if (usart == USART1) { PRS->CONSUMER_USART1_RX = ch; } else if (usart == USART2) { PRS->CONSUMER_USART2_RX = ch; } usart->CTRLX |= USART_CTRLX_RXPRSEN; #endif } #endif /***************************************************************************//** * @brief * Configure a PRS channel as USART Ir input * * @param[in] usart * A pointer to the USART/UART peripheral register block. * * @param[in] ch * PRS channel. ******************************************************************************/ static void prsIrInput(USART_TypeDef *usart, USART_PRS_Channel_t ch) { #if defined(_USART_IRCTRL_IRPRSSEL_MASK) usart->IRCTRL |= ((uint32_t)ch << _USART_IRCTRL_IRPRSSEL_SHIFT) | USART_IRCTRL_IRPRSEN; #else if (usart == USART0) { PRS->CONSUMER_USART0_IR = ch; } else if (usart == USART1) { PRS->CONSUMER_USART1_IR = ch; } else if (usart == USART2) { PRS->CONSUMER_USART2_IR = ch; } usart->IRCTRL |= USART_IRCTRL_IRPRSEN; #endif } /***************************************************************************//** * @brief * Configure a PRS channel as USART Trigger input * * @param[in] usart * A pointer to the USART/UART peripheral register block. * * @param[in] ch * PRS channel. ******************************************************************************/ static void prsTriggerInput(USART_TypeDef *usart, USART_PRS_Channel_t ch) { #if defined(_USART_IRCTRL_IRPRSSEL_MASK) usart->TRIGCTRL = (usart->TRIGCTRL & ~_USART_TRIGCTRL_TSEL_MASK) | (ch << _USART_TRIGCTRL_TSEL_SHIFT); #else if (usart == USART0) { PRS->CONSUMER_USART0_TRIGGER = ch; } else if (usart == USART1) { PRS->CONSUMER_USART1_TRIGGER = ch; } else if (usart == USART2) { PRS->CONSUMER_USART2_TRIGGER = ch; } #endif } /******************************************************************************* ************************** GLOBAL FUNCTIONS ******************************* ******************************************************************************/ /***************************************************************************//** * @brief * Configure USART/UART operating in asynchronous mode to use a given * baudrate (or as close as possible to a specified baudrate). * * @param[in] usart * A pointer to the USART/UART peripheral register block. * * @param[in] refFreq * USART/UART reference clock frequency in Hz. If set to 0, * the currently configured reference clock is assumed. * * @param[in] baudrate * Baudrate to try to achieve for USART/UART. * * @param[in] ovs * Oversampling to be used. Normal is 16x oversampling but lower oversampling * may be used to achieve higher rates or better baudrate accuracy in some * cases. Notice that lower oversampling frequency makes the channel more * vulnerable to bit faults during reception due to clock inaccuracies * compared to the link partner. ******************************************************************************/ void USART_BaudrateAsyncSet(USART_TypeDef *usart, uint32_t refFreq, uint32_t baudrate, USART_OVS_TypeDef ovs) { uint32_t clkdiv; uint32_t oversample; /* Inhibit divide by 0 */ EFM_ASSERT(baudrate); /* * Use integer division to avoid forcing in float division * utils and yet keep rounding effect errors to a minimum. * * CLKDIV in asynchronous mode is given by: * * CLKDIV = 256 * (fHFPERCLK/(oversample * br) - 1) * or * CLKDIV = (256 * fHFPERCLK)/(oversample * br) - 256 * * The basic problem with integer division in the above formula is that * the dividend (256 * fHFPERCLK) may become higher than max 32 bit * integer. Yet, we want to evaluate the dividend first before dividing * to get as small rounding effects as possible. * Too harsh restrictions on maximum fHFPERCLK value should not be made. * * It is possible to factorize 256 and oversample/br. However, * since the last 6 or 3 bits of CLKDIV are don't care, base the * integer arithmetic on the below formula * * CLKDIV / 64 = (4 * fHFPERCLK)/(oversample * br) - 4 (3 bits dont care) * or * CLKDIV / 8 = (32 * fHFPERCLK)/(oversample * br) - 32 (6 bits dont care) * * and calculate 1/64 of CLKDIV first. This allows for fHFPERCLK * up to 1 GHz without overflowing a 32 bit value. */ /* HFPERCLK/HFPERBCLK used to clock all USART/UART peripheral modules. */ if (!refFreq) { #if defined(_SILICON_LABS_32B_SERIES_2) refFreq = CMU_ClockFreqGet(cmuClock_PCLK); #else #if defined(_CMU_HFPERPRESCB_MASK) if (usart == USART2) { refFreq = CMU_ClockFreqGet(cmuClock_HFPERB); } else { refFreq = CMU_ClockFreqGet(cmuClock_HFPER); } #else refFreq = CMU_ClockFreqGet(cmuClock_HFPER); #endif #endif } /* Map oversampling. */ switch (ovs) { case usartOVS16: EFM_ASSERT(baudrate <= (refFreq / 16)); oversample = 16; break; case usartOVS8: EFM_ASSERT(baudrate <= (refFreq / 8)); oversample = 8; break; case usartOVS6: EFM_ASSERT(baudrate <= (refFreq / 6)); oversample = 6; break; case usartOVS4: EFM_ASSERT(baudrate <= (refFreq / 4)); oversample = 4; break; default: /* Invalid input */ EFM_ASSERT(0); return; } /* Calculate and set CLKDIV with fractional bits. * The added (oversample*baudrate)/2 in the first line is to round the * divisor to the nearest fractional divisor. */ #if defined(_SILICON_LABS_32B_SERIES_0) && !defined(_EFM32_HAPPY_FAMILY) /* Devices with 2 fractional bits. CLKDIV[7:6] */ clkdiv = 4 * refFreq + (oversample * baudrate) / 2; clkdiv /= oversample * baudrate; clkdiv -= 4; clkdiv *= 64; #else /* Devices with 5 fractional bits. CLKDIV[7:3] */ clkdiv = 32 * refFreq + (oversample * baudrate) / 2; clkdiv /= oversample * baudrate; clkdiv -= 32; clkdiv *= 8; #endif /* Verify that the resulting clock divider is within limits. */ EFM_ASSERT(clkdiv <= CLKDIV_MASK); /* Make sure that reserved bits are not written to. */ clkdiv &= CLKDIV_MASK; usart->CTRL &= ~_USART_CTRL_OVS_MASK; usart->CTRL |= ovs; usart->CLKDIV = clkdiv; } /***************************************************************************//** * @brief * Calculate baudrate for USART/UART given reference frequency, clock division, * and oversampling rate (if async mode). * * @details * This function returns the baudrate that a USART/UART module will use if * configured with the given frequency, clock divisor, and mode. Notice that * this function will not use the hardware configuration. It can be used * to determine if a given configuration is sufficiently accurate for the * application. * * @param[in] refFreq * USART/UART HF peripheral frequency used. * * @param[in] clkdiv * A clock division factor to be used. * * @param[in] syncmode * @li True - synchronous mode operation. * @li False - asynchronous mode operation. * * @param[in] ovs * Oversampling used if in asynchronous mode. Not used if @p syncmode is true. * * @return * Baudrate with given settings. ******************************************************************************/ uint32_t USART_BaudrateCalc(uint32_t refFreq, uint32_t clkdiv, bool syncmode, USART_OVS_TypeDef ovs) { uint32_t oversample; uint64_t divisor; uint64_t factor; uint64_t remainder; uint64_t quotient; uint32_t br; /* Out of bound clkdiv. */ EFM_ASSERT(clkdiv <= CLKDIV_MASK); /* Mask out unused bits */ clkdiv &= CLKDIV_MASK; /* Use integer division to avoid forcing in float division */ /* utils and yet keep rounding effect errors to a minimum. */ /* Baudrate calculation depends on if synchronous or asynchronous mode. */ if (syncmode) { /* * Baudrate is given by: * * br = fHFPERCLK/(2 * (1 + (CLKDIV / 256))) * * which can be rewritten to * * br = (128 * fHFPERCLK)/(256 + CLKDIV) */ oversample = 1; /* Not used in sync mode, i.e., 1 */ factor = 128; } else { /* * Baudrate in asynchronous mode is given by: * * br = fHFPERCLK/(oversample * (1 + (CLKDIV / 256))) * * which can be rewritten to * * br = (256 * fHFPERCLK)/(oversample * (256 + CLKDIV)) * * 256 factor of the dividend is reduced with a * (part of) oversample part of the divisor. */ switch (ovs) { case usartOVS16: oversample = 1; factor = 256 / 16; break; case usartOVS8: oversample = 1; factor = 256 / 8; break; case usartOVS6: oversample = 3; factor = 256 / 2; break; default: oversample = 1; factor = 256 / 4; break; } } /* * The basic problem with integer division in the above formula is that * the dividend (factor * fHFPERCLK) may become larger than a 32 bit * integer. Yet we want to evaluate the dividend first before dividing * to get as small rounding effects as possible. Too harsh restrictions * should not be made on the maximum fHFPERCLK value either. * * For division a/b, * * a = qb + r * * where q is the quotient and r is the remainder, both integers. * * The original baudrate formula can be rewritten as * * br = xa / b = x(qb + r)/b = xq + xr/b * * where x is 'factor', a is 'refFreq' and b is 'divisor', referring to * variable names. */ /* * The divisor will never exceed max 32 bit value since * clkdiv <= _USART_CLKDIV_DIV_MASK (currently 0x1FFFC0 or 0x7FFFF8) * and 'oversample' has been reduced to <= 3. */ divisor = oversample * (256 + clkdiv); quotient = refFreq / divisor; remainder = refFreq % divisor; /* The factor <= 128 and since divisor >= 256, the below cannot exceed the maximum */ /* 32 bit value. However, factor * remainder can become larger than 32-bit */ /* because of the size of _USART_CLKDIV_DIV_MASK on some families. */ br = (uint32_t)(factor * quotient); /* * The factor <= 128 and remainder < (oversample*(256 + clkdiv)), which * means dividend (factor * remainder) worst case is * 128 * (3 * (256 + _USART_CLKDIV_DIV_MASK)) = 0x1_8001_7400. */ br += (uint32_t)((factor * remainder) / divisor); return br; } /***************************************************************************//** * @brief * Get the current baudrate for USART/UART. * * @details * This function returns the actual baudrate (not considering oscillator * inaccuracies) used by a USART/UART peripheral. * * @param[in] usart * A pointer to the USART/UART peripheral register block. * * @return * The current baudrate. ******************************************************************************/ uint32_t USART_BaudrateGet(USART_TypeDef *usart) { uint32_t freq; USART_OVS_TypeDef ovs; bool syncmode; if (usart->CTRL & USART_CTRL_SYNC) { syncmode = true; } else { syncmode = false; } /* HFPERCLK/HFPERBCLK used to clock all USART/UART peripheral modules. */ #if defined(_SILICON_LABS_32B_SERIES_2) freq = CMU_ClockFreqGet(cmuClock_PCLK); #else #if defined(_CMU_HFPERPRESCB_MASK) if (usart == USART2) { freq = CMU_ClockFreqGet(cmuClock_HFPERB); } else { freq = CMU_ClockFreqGet(cmuClock_HFPER); } #else freq = CMU_ClockFreqGet(cmuClock_HFPER); #endif #endif ovs = (USART_OVS_TypeDef)(usart->CTRL & _USART_CTRL_OVS_MASK); return USART_BaudrateCalc(freq, usart->CLKDIV, syncmode, ovs); } /***************************************************************************//** * @brief * Configure the USART operating in synchronous mode to use a given baudrate * (or as close as possible to a specified baudrate). * * @details * The configuration will be set to use a baudrate <= the specified baudrate * to ensure that the baudrate does not exceed the specified value. * * The fractional clock division is suppressed, although the hardware design allows it. * It could cause half clock cycles to exceed a specified limit and thus * potentially violate specifications for the slave device. In some special * situations, a fractional clock division may be useful even in synchronous * mode, but in those cases it must be directly adjusted, possibly assisted * by USART_BaudrateCalc(): * * @param[in] usart * A pointer to the USART peripheral register block. (Cannot be used on UART * modules.) * * @param[in] refFreq * A USART reference clock frequency in Hz that will be used. If set to 0, * the currently-configured reference clock is assumed. * * @param[in] baudrate * Baudrate to try to achieve for USART. ******************************************************************************/ void USART_BaudrateSyncSet(USART_TypeDef *usart, uint32_t refFreq, uint32_t baudrate) { uint32_t clkdiv; /* Prevent dividing by 0. */ EFM_ASSERT(baudrate); /* * CLKDIV in synchronous mode is given by: * * CLKDIV = 256 * (fHFPERCLK/(2 * br) - 1) */ /* HFPERCLK/HFPERBCLK used to clock all USART/UART peripheral modules. */ if (!refFreq) { #if defined(_SILICON_LABS_32B_SERIES_2) refFreq = CMU_ClockFreqGet(cmuClock_PCLK); #else #if defined(_CMU_HFPERPRESCB_MASK) if (usart == USART2) { refFreq = CMU_ClockFreqGet(cmuClock_HFPERB); } else { refFreq = CMU_ClockFreqGet(cmuClock_HFPER); } #else refFreq = CMU_ClockFreqGet(cmuClock_HFPER); #endif #endif } clkdiv = (refFreq - 1) / (2 * baudrate); clkdiv = clkdiv << 8; /* Verify that resulting clock divider is within limits. */ EFM_ASSERT(!(clkdiv & ~CLKDIV_MASK)); usart->CLKDIV = clkdiv; } /***************************************************************************//** * @brief * Enable/disable USART/UART receiver and/or transmitter. * * @details * Notice that this function does not do any configuration. Enabling should * normally be done after initialization (if not enabled as part * of initialization). * * @param[in] usart * A pointer to the USART/UART peripheral register block. * * @param[in] enable * Select the status for the receiver/transmitter. ******************************************************************************/ void USART_Enable(USART_TypeDef *usart, USART_Enable_TypeDef enable) { uint32_t tmp; /* Make sure the module exists on the selected chip. */ EFM_ASSERT(USART_REF_VALID(usart) || USARTRF_REF_VALID(usart) || UART_REF_VALID(usart)); #if defined(USART_EN_EN) usart->EN_SET = USART_EN_EN; #endif /* Disable as specified. */ tmp = ~((uint32_t)enable); tmp &= _USART_CMD_RXEN_MASK | _USART_CMD_TXEN_MASK; usart->CMD = tmp << 1; /* Enable as specified. */ usart->CMD = (uint32_t)enable; #if defined(USART_EN_EN) if (enable == usartDisable) { usart->EN_CLR = USART_EN_EN; } #endif } /***************************************************************************//** * @brief * Initialize USART/UART for normal asynchronous mode. * * @details * This function will configure basic settings to operate in normal * asynchronous mode. * * A special control setup not covered by this function must be done after * using this function by direct modification of the CTRL register. * * Notice that pins used by the USART/UART module must be properly configured * by the user explicitly for the USART/UART to work as intended. * (When configuring pins, remember to consider the sequence of * configuration to avoid unintended pulses/glitches on output * pins.) * * @param[in] usart * A pointer to the USART/UART peripheral register block. * * @param[in] init * A pointer to the initialization structure used to configure the basic async setup. ******************************************************************************/ void USART_InitAsync(USART_TypeDef *usart, const USART_InitAsync_TypeDef *init) { /* Make sure the module exists on the selected chip. */ EFM_ASSERT(USART_REF_VALID(usart) || USARTRF_REF_VALID(usart) || UART_REF_VALID(usart)); /* Initialize USART registers to hardware reset state. */ USART_Reset(usart); #if defined(USART_EN_EN) usart->EN_SET = USART_EN_EN; #endif #if defined(USART_CTRL_MVDIS) /* Disable the majority vote if specified. */ if (init->mvdis) { usart->CTRL |= USART_CTRL_MVDIS; } #endif #if !defined(_EFM32_GECKO_FAMILY) /* Configure the PRS input mode. */ if (init->prsRxEnable) { prsRxInput(usart, init->prsRxCh); } #endif /* Configure databits, stopbits, and parity. */ usart->FRAME = (uint32_t)init->databits | (uint32_t)init->stopbits | (uint32_t)init->parity; /* Configure baudrate. */ USART_BaudrateAsyncSet(usart, init->refFreq, init->baudrate, init->oversampling); if (init->autoCsEnable) { usart->CTRL |= USART_CTRL_AUTOCS; } #if defined(_USART_TIMING_CSHOLD_MASK) usart->TIMING = ((init->autoCsHold << _USART_TIMING_CSHOLD_SHIFT) & _USART_TIMING_CSHOLD_MASK) | ((init->autoCsSetup << _USART_TIMING_CSSETUP_SHIFT) & _USART_TIMING_CSSETUP_MASK); #endif #if defined(_USART_ROUTEPEN_RTSPEN_MASK) && defined(_USART_ROUTEPEN_CTSPEN_MASK) usart->ROUTEPEN &= ~(_USART_ROUTEPEN_RTSPEN_MASK | _USART_ROUTEPEN_CTSPEN_MASK); usart->ROUTEPEN |= init->hwFlowControl; #elif defined(USART_CTRLX_CTSEN) if ((init->hwFlowControl == usartHwFlowControlRts) || (init->hwFlowControl == usartHwFlowControlCtsAndRts)) { GPIO->USARTROUTE_SET[USART_NUM(usart)].ROUTEEN = GPIO_USART_ROUTEEN_RTSPEN; } else { GPIO->USARTROUTE_CLR[USART_NUM(usart)].ROUTEEN = GPIO_USART_ROUTEEN_RTSPEN; } if ((init->hwFlowControl == usartHwFlowControlCts) || (init->hwFlowControl == usartHwFlowControlCtsAndRts)) { usart->CTRLX_SET = USART_CTRLX_CTSEN; } else { usart->CTRLX_CLR = USART_CTRLX_CTSEN; } #endif /* Finally, enable (as specified). */ usart->CMD = (uint32_t)init->enable; } /***************************************************************************//** * @brief * Initialize USART for synchronous mode. * * @details * This function will configure basic settings to operate in * synchronous mode. * * A special control setup not covered by this function must be done after * using this function by direct modification of the CTRL register. * * Notice that pins used by the USART module must be properly configured * by the user explicitly for the USART to work as intended. * (When configuring pins remember to consider the sequence of * configuration to avoid unintended pulses/glitches on output * pins.) * * @param[in] usart * A pointer to the USART peripheral register block. (UART does not support this * mode.) * * @param[in] init * A pointer to the initialization structure used to configure basic async setup. ******************************************************************************/ void USART_InitSync(USART_TypeDef *usart, const USART_InitSync_TypeDef *init) { /* Make sure the module exists on the selected chip. */ EFM_ASSERT(USART_REF_VALID(usart) || USARTRF_REF_VALID(usart) ); /* Initialize USART registers to hardware reset state. */ USART_Reset(usart); #if defined(USART_EN_EN) usart->EN_SET = USART_EN_EN; #endif /* Set bits for synchronous mode. */ usart->CTRL |= (USART_CTRL_SYNC) | (uint32_t)init->clockMode | (init->msbf ? USART_CTRL_MSBF : 0); #if defined(_USART_CTRL_AUTOTX_MASK) usart->CTRL |= init->autoTx ? USART_CTRL_AUTOTX : 0; #endif #if !defined(_EFM32_GECKO_FAMILY) if (init->prsRxEnable) { prsRxInput(usart, init->prsRxCh); } #endif /* Configure databits, leave stopbits and parity at reset default (not used). */ usart->FRAME = (uint32_t)init->databits | USART_FRAME_STOPBITS_DEFAULT | USART_FRAME_PARITY_DEFAULT; /* Configure the baudrate. */ USART_BaudrateSyncSet(usart, init->refFreq, init->baudrate); /* Finally, enable (as specified). */ if (init->master) { usart->CMD = USART_CMD_MASTEREN; } if (init->autoCsEnable) { usart->CTRL |= USART_CTRL_AUTOCS; } #if defined(_USART_TIMING_CSHOLD_MASK) usart->TIMING = ((init->autoCsHold << _USART_TIMING_CSHOLD_SHIFT) & _USART_TIMING_CSHOLD_MASK) | ((init->autoCsSetup << _USART_TIMING_CSSETUP_SHIFT) & _USART_TIMING_CSSETUP_MASK); #endif usart->CMD = (uint32_t)init->enable; } /***************************************************************************//** * @brief * Initialize USART for asynchronous IrDA mode. * * @details * This function will configure basic settings to operate in * asynchronous IrDA mode. * * A special control setup not covered by this function must be done after * using this function by direct modification of the CTRL and IRCTRL * registers. * * Notice that pins used by the USART/UART module must be properly configured * by the user explicitly for the USART/UART to work as intended. * (When configuring pins, remember to consider the sequence of * configuration to avoid unintended pulses/glitches on output * pins.) * * @param[in] usart * A pointer to the USART peripheral register block. * * @param[in] init * A pointer to the initialization structure used to configure async IrDA setup. * * @note * Not all USART instances support IrDA. See the data sheet for your device. * ******************************************************************************/ void USARTn_InitIrDA(USART_TypeDef *usart, const USART_InitIrDA_TypeDef *init) { EFM_ASSERT(USART_IRDA_VALID(usart)); /* Initialize USART as an async device. */ USART_InitAsync(usart, &(init->async)); /* Set IrDA modulation to RZI (return-to-zero-inverted). */ usart->CTRL |= USART_CTRL_TXINV; /* Invert the Rx signal before the demodulator if enabled. */ if (init->irRxInv) { usart->CTRL |= USART_CTRL_RXINV; } /* Configure IrDA. */ usart->IRCTRL = (uint32_t)init->irPw | ((init->irFilt ? 1UL : 0UL) << _USART_IRCTRL_IRFILT_SHIFT); if (init->irPrsEn) { prsIrInput(usart, init->irPrsSel); } /* Enable IrDA. */ usart->IRCTRL |= USART_IRCTRL_IREN; } #if defined(_USART_I2SCTRL_MASK) /***************************************************************************//** * @brief * Initialize USART for I2S mode. * * @details * This function will configure basic settings to operate in I2S * mode. * * A special control setup not covered by this function must be done after * using this function by direct modification of the CTRL and I2SCTRL * registers. * * Notice that pins used by the USART module must be properly configured * by the user explicitly for the USART to work as intended. * (When configuring pins, remember to consider the sequence of * configuration to avoid unintended pulses/glitches on output * pins.) * * @param[in] usart * A pointer to the USART peripheral register block. (UART does not support this * mode.) * * @param[in] init * A pointer to the initialization structure used to configure the basic I2S setup. * * @note * This function does not apply to all USART's. See the chip Reference Manual. * ******************************************************************************/ void USART_InitI2s(USART_TypeDef *usart, USART_InitI2s_TypeDef *init) { USART_Enable_TypeDef enable; /* Make sure the module exists on the selected chip. */ EFM_ASSERT(USART_I2S_VALID(usart)); /* Override the enable setting. */ enable = init->sync.enable; init->sync.enable = usartDisable; /* Initialize USART as a sync device. */ USART_InitSync(usart, &init->sync); /* Configure and enable I2CCTRL register according to the selected mode. */ usart->I2SCTRL = (uint32_t)init->format | (uint32_t)init->justify | (init->delay ? USART_I2SCTRL_DELAY : 0) | (init->dmaSplit ? USART_I2SCTRL_DMASPLIT : 0) | (init->mono ? USART_I2SCTRL_MONO : 0) | USART_I2SCTRL_EN; if (enable != usartDisable) { USART_Enable(usart, enable); } } #endif /***************************************************************************//** * @brief * Initialize the automatic transmissions using PRS channel as a trigger. * @note * Initialize USART with USART_Init() before setting up the PRS configuration. * * @param[in] usart A pointer to USART to configure. * @param[in] init A pointer to the initialization structure. ******************************************************************************/ void USART_InitPrsTrigger(USART_TypeDef *usart, const USART_PrsTriggerInit_TypeDef *init) { uint32_t trigctrl; prsTriggerInput(usart, init->prsTriggerChannel); /* Clear values that will be reconfigured. */ trigctrl = usart->TRIGCTRL & ~(_USART_TRIGCTRL_RXTEN_MASK | _USART_TRIGCTRL_TXTEN_MASK #if defined(USART_TRIGCTRL_AUTOTXTEN) | _USART_TRIGCTRL_AUTOTXTEN_MASK #endif ); #if defined(USART_TRIGCTRL_AUTOTXTEN) if (init->autoTxTriggerEnable) { trigctrl |= USART_TRIGCTRL_AUTOTXTEN; } #endif if (init->txTriggerEnable) { trigctrl |= USART_TRIGCTRL_TXTEN; } if (init->rxTriggerEnable) { trigctrl |= USART_TRIGCTRL_RXTEN; } usart->TRIGCTRL = trigctrl; } /***************************************************************************//** * @brief * Reset USART/UART to the same state that it was in after a hardware reset. * * @param[in] usart * A pointer to USART/UART peripheral register block. ******************************************************************************/ void USART_Reset(USART_TypeDef *usart) { /* Make sure the module exists on the selected chip. */ EFM_ASSERT(USART_REF_VALID(usart) || USARTRF_REF_VALID(usart) || UART_REF_VALID(usart) ); #if defined(USART_EN_EN) usart->EN_SET = USART_EN_EN; /* Make sure disabled first, before resetting other registers. */ usart->CMD = USART_CMD_RXDIS | USART_CMD_TXDIS | USART_CMD_MASTERDIS | USART_CMD_RXBLOCKDIS | USART_CMD_TXTRIDIS | USART_CMD_CLEARTX | USART_CMD_CLEARRX; usart->CTRL = _USART_CTRL_RESETVALUE; usart->CTRLX = _USART_CTRLX_RESETVALUE; usart->FRAME = _USART_FRAME_RESETVALUE; usart->TRIGCTRL = _USART_TRIGCTRL_RESETVALUE; usart->CLKDIV = _USART_CLKDIV_RESETVALUE; usart->IEN = _USART_IEN_RESETVALUE; usart->IF_CLR = _USART_IF_MASK; usart->TIMING = _USART_TIMING_RESETVALUE; if (USART_IRDA_VALID(usart)) { usart->IRCTRL = _USART_IRCTRL_RESETVALUE; } if (USART_I2S_VALID(usart)) { usart->I2SCTRL = _USART_I2SCTRL_RESETVALUE; } usart->EN_CLR = USART_EN_EN; #else /* Make sure disabled first, before resetting other registers */ usart->CMD = USART_CMD_RXDIS | USART_CMD_TXDIS | USART_CMD_MASTERDIS | USART_CMD_RXBLOCKDIS | USART_CMD_TXTRIDIS | USART_CMD_CLEARTX | USART_CMD_CLEARRX; usart->CTRL = _USART_CTRL_RESETVALUE; usart->FRAME = _USART_FRAME_RESETVALUE; usart->TRIGCTRL = _USART_TRIGCTRL_RESETVALUE; usart->CLKDIV = _USART_CLKDIV_RESETVALUE; usart->IEN = _USART_IEN_RESETVALUE; usart->IFC = _USART_IFC_MASK; #if defined(_USART_TIMING_MASK) usart->TIMING = _USART_TIMING_RESETVALUE; #endif #if defined(_USART_ROUTEPEN_MASK) || defined(_UART_ROUTEPEN_MASK) usart->ROUTEPEN = _USART_ROUTEPEN_RESETVALUE; usart->ROUTELOC0 = _USART_ROUTELOC0_RESETVALUE; usart->ROUTELOC1 = _USART_ROUTELOC1_RESETVALUE; #else usart->ROUTE = _USART_ROUTE_RESETVALUE; #endif if (USART_IRDA_VALID(usart)) { usart->IRCTRL = _USART_IRCTRL_RESETVALUE; } #if defined(_USART_INPUT_RESETVALUE) usart->INPUT = _USART_INPUT_RESETVALUE; #endif #if defined(_USART_I2SCTRL_RESETVALUE) if (USART_I2S_VALID(usart)) { usart->I2SCTRL = _USART_I2SCTRL_RESETVALUE; } #endif #endif } /***************************************************************************//** * @brief * Receive one 4-8 bit frame, (or part of 10-16 bit frame). * * @details * This function is normally used to receive one frame when operating with * frame length 4-8 bits. See @ref USART_RxExt() for reception of * 9 bit frames. * * Notice that possible parity/stop bits in asynchronous mode are not * considered part of a specified frame bit length. * * @note * This function will stall if the buffer is empty until data is received. * Alternatively, the user can explicitly check whether data is available. * If data is available, call @ref USART_RxDataGet() to read the RXDATA * register directly. * * @param[in] usart * A pointer to the USART/UART peripheral register block. * * @return * Data received. ******************************************************************************/ uint8_t USART_Rx(USART_TypeDef *usart) { while (!(usart->STATUS & USART_STATUS_RXDATAV)) { } return (uint8_t)usart->RXDATA; } /***************************************************************************//** * @brief * Receive two 4-8 bit frames or one 10-16 bit frame. * * @details * This function is normally used to receive one frame when operating with * frame length 10-16 bits. See @ref USART_RxDoubleExt() for * reception of two 9 bit frames. * * Notice that possible parity/stop bits in asynchronous mode are not * considered part of a specified frame bit length. * * @note * This function will stall if the buffer is empty until data is received. * Alternatively, the user can explicitly check whether data is available. * If data is available, call @ref USART_RxDoubleGet() to read the RXDOUBLE * register directly. * * @param[in] usart * A pointer to the USART/UART peripheral register block. * * @return * Data received. ******************************************************************************/ uint16_t USART_RxDouble(USART_TypeDef *usart) { while (!(usart->STATUS & USART_STATUS_RXFULL)) { } return (uint16_t)usart->RXDOUBLE; } /***************************************************************************//** * @brief * Receive two 4-9 bit frames, or one 10-16 bit frame with extended * information. * * @details * This function is normally used to receive one frame when operating with * frame length 10-16 bits and additional RX status information is required. * * Notice that possible parity/stop bits in asynchronous mode are not * considered part of a specified frame bit length. * * @note * This function will stall if buffer is empty until data is received. * Alternatively, the user can explicitly check whether data is available. * If data is available, call @ref USART_RxDoubleXGet() to read the RXDOUBLEX * register directly. * * @param[in] usart * A pointer to the USART/UART peripheral register block. * * @return * Data received. ******************************************************************************/ uint32_t USART_RxDoubleExt(USART_TypeDef *usart) { while (!(usart->STATUS & USART_STATUS_RXFULL)) { } return usart->RXDOUBLEX; } /***************************************************************************//** * @brief * Receive one 4-9 bit frame (or part of 10-16 bit frame) with extended * information. * * @details * This function is normally used to receive one frame when operating with * frame length 4-9 bits and additional RX status information is required. * * Notice that possible parity/stop bits in asynchronous mode are not * considered part of a specified frame bit length. * * @note * This function will stall if the buffer is empty until data is received. * Alternatively, the user can explicitly check whether data is available. * If data is available, call @ref USART_RxDataXGet() to read the RXDATAX * register directly. * * @param[in] usart * A pointer to the USART/UART peripheral register block. * * @return * Data received. ******************************************************************************/ uint16_t USART_RxExt(USART_TypeDef *usart) { while (!(usart->STATUS & USART_STATUS_RXDATAV)) { } return (uint16_t)usart->RXDATAX; } /***************************************************************************//** * @brief * Perform one 8 bit frame SPI transfer. * * @note * This function will stall if the transmit buffer is full. When a transmit * buffer becomes available, data is written and the function will wait until * data is fully transmitted. The SPI return value is then read out and * returned. * * @param[in] usart * A pointer to the USART peripheral register block. * * @param[in] data * Data to transmit. * * @return * Data received. ******************************************************************************/ uint8_t USART_SpiTransfer(USART_TypeDef *usart, uint8_t data) { while (!(usart->STATUS & USART_STATUS_TXBL)) { } usart->TXDATA = (uint32_t)data; while (!(usart->STATUS & USART_STATUS_TXC)) { } return (uint8_t)usart->RXDATA; } /***************************************************************************//** * @brief * Transmit one 4-9 bit frame. * * @details * Depending on the frame length configuration, 4-8 (least significant) bits from * @p data are transmitted. If the frame length is 9, 8 bits are transmitted from * @p data and one bit as specified by CTRL register, BIT8DV field. * See USART_TxExt() for transmitting 9 bit frame with full control of * all 9 bits. * * Notice that possible parity/stop bits in asynchronous mode are not * considered part of a specified frame bit length. * * @note * This function will stall if the buffer is full until the buffer becomes available. * * @param[in] usart * A pointer to the USART/UART peripheral register block. * * @param[in] data * Data to transmit. See details above for more information. ******************************************************************************/ void USART_Tx(USART_TypeDef *usart, uint8_t data) { /* Check that transmit buffer is empty */ while (!(usart->STATUS & USART_STATUS_TXBL)) { } usart->TXDATA = (uint32_t)data; } /***************************************************************************//** * @brief * Transmit two 4-9 bit frames or one 10-16 bit frame. * * @details * Depending on the frame length configuration, 4-8 (least significant) bits from * each byte in @p data are transmitted. If frame length is 9, 8 bits are * transmitted from each byte in @p data adding one bit as specified by the CTRL * register, BIT8DV field, to each byte. See USART_TxDoubleExt() * for transmitting two 9 bit frames with full control of all 9 bits. * * If the frame length is 10-16, 10-16 (least significant) bits from @p data * are transmitted. * * Notice that possible parity/stop bits in asynchronous mode are not * considered part of a specified frame bit length. * * @note * This function will stall if the buffer is full until the buffer becomes available. * * @param[in] usart * A pointer to the USART/UART peripheral register block. * * @param[in] data * Data to transmit, the least significant byte holds the frame transmitted * first. See details above for more info. ******************************************************************************/ void USART_TxDouble(USART_TypeDef *usart, uint16_t data) { /* Check that transmit buffer is empty */ while (!(usart->STATUS & USART_STATUS_TXBL)) { } usart->TXDOUBLE = (uint32_t)data; } /***************************************************************************//** * @brief * Transmit two 4-9 bit frames or one 10-16 bit frame with extended control. * * @details * Notice that possible parity/stop bits in asynchronous mode are not * considered part of a specified frame bit length. * * @note * This function will stall if the buffer is full until the buffer becomes available. * * @param[in] usart * A pointer to the USART/UART peripheral register block. * * @param[in] data * Data to transmit with extended control. Contains two 16 bit words * concatenated. Least significant word holds the frame transmitted first. If the frame * length is 4-9, two frames with 4-9 least significant bits from each 16 bit * word are transmitted. * @par * If the frame length is 10-16 bits, 8 data bits are taken from the least * significant 16 bit word and the remaining bits from the other 16 bit word. * @par * Additional control bits are available as documented in the reference * manual (set to 0 if not used). For 10-16 bit frame length, these control * bits are taken from the most significant 16 bit word. ******************************************************************************/ void USART_TxDoubleExt(USART_TypeDef *usart, uint32_t data) { /* Check that transmit buffer is empty. */ while (!(usart->STATUS & USART_STATUS_TXBL)) { } usart->TXDOUBLEX = data; } /***************************************************************************//** * @brief * Transmit one 4-9 bit frame with extended control. * * @details * Notice that possible parity/stop bits in asynchronous mode are not * considered part of a specified frame bit length. * * @note * This function will stall if the buffer is full until the buffer becomes available. * * @param[in] usart * A pointer to the USART/UART peripheral register block. * * @param[in] data * Data to transmit with extended control. Least significant bit contains * frame bits. Additional control bits are available as documented in * the reference manual (set to 0 if not used). ******************************************************************************/ void USART_TxExt(USART_TypeDef *usart, uint16_t data) { /* Check that the transmit buffer is empty. */ while (!(usart->STATUS & USART_STATUS_TXBL)) { } usart->TXDATAX = (uint32_t)data; } /** @} (end addtogroup USART) */ /** @} (end addtogroup emlib) */ #endif /* defined(USART_COUNT) && (USART_COUNT > 0) */ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/halconfig/inc/hal-config/hal-config-types.h.
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/***************************************************************************//** * @file * @brief Defines for hal-config. ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * The licensor of this software is Silicon Laboratories Inc. Your use of this * software is governed by the terms of Silicon Labs Master Software License * Agreement (MSLA) available at * www.silabs.com/about-us/legal/master-software-license-agreement. This * software is distributed to you in Source Code format and is governed by the * sections of the MSLA applicable to Source Code. * ******************************************************************************/ #ifndef HAL_CONFIG_TYPES_H #define HAL_CONFIG_TYPES_H #include "em_gpio.h" #define HAL_CLK_HFCLK_SOURCE_HFRCO 1 #define HAL_CLK_HFCLK_SOURCE_HFXO 2 #define HAL_CLK_HFCLK_SOURCE_FSRCO 3 #define HAL_CLK_LFCLK_SOURCE_DISABLED 0 #define HAL_CLK_LFCLK_SOURCE_LFRCO 1 #define HAL_CLK_LFCLK_SOURCE_LFXO 2 #define HAL_CLK_LFCLK_SOURCE_ULFRCO 3 #define HAL_CLK_LFCLK_SOURCE_HFLE 4 #define HAL_CLK_PLL_CONFIGURATION_NONE 1 #define HAL_CLK_PLL_CONFIGURATION_40MHZ 2 #define HAL_CLK_PLL_CONFIGURATION_80MHZ 3 #define HAL_CLK_HFXO_AUTOSTART_NONE 0 #define HAL_CLK_HFXO_AUTOSTART_START 1 #define HAL_CLK_HFXO_AUTOSTART_SELECT 2 #define HAL_DISPLAY_SHARP_LS013B7DH03 1 #define HAL_DISPLAY_SHARP_LS013B7DH06 2 #define HAL_EMU_EM23_VSCALE_FASTWAKEUP 1 #define HAL_EMU_EM23_VSCALE_LOWPOWER 2 #define HAL_GPIO_DOUT_LOW 0 #define HAL_GPIO_DOUT_HIGH 1 #define HAL_GPIO_MODE_INPUT gpioModeInput #define HAL_GPIO_MODE_INPUT_PULL gpioModeInputPull #define HAL_GPIO_MODE_INPUT_PULL_FILTER gpioModeInputPullFilter #define HAL_I2C_PORT_I2C0 0x40 #define HAL_I2C_PORT_I2C1 0x41 #define HAL_I2C_PORT_I2C2 0x42 #define HAL_I2C_PORT_I2C3 0x43 #define HAL_LEUART_FLOW_CONTROL_NONE 0 #define HAL_LEUART_FLOW_CONTROL_SW 1 #define HAL_LEUART_FLOW_CONTROL_HW 2 #define HAL_LEUART_FLOW_CONTROL_HWUART 3 #define HAL_PTI_MODE_SPI 1 #define HAL_PTI_MODE_UART 2 #define HAL_PTI_MODE_UART_ONEWIRE 3 #define HAL_SERIAL_PORT_VUART 0x10 #define HAL_SERIAL_PORT_USART0 0x20 #define HAL_SERIAL_PORT_USART1 0x21 #define HAL_SERIAL_PORT_USART2 0x22 #define HAL_SERIAL_PORT_USART3 0x23 #define HAL_SERIAL_PORT_USART4 0x24 #define HAL_SERIAL_PORT_USART5 0x25 #define HAL_SERIAL_PORT_UART0 0x30 #define HAL_SERIAL_PORT_UART1 0x31 #define HAL_SERIAL_PORT_LEUART0 0x40 #define HAL_SERIAL_PORT_LEUART1 0x41 #define HAL_SPI_PORT_USART0 0x20 #define HAL_SPI_PORT_USART1 0x21 #define HAL_SPI_PORT_USART2 0x22 #define HAL_SPI_PORT_USART3 0x23 #define HAL_SPI_PORT_USART4 0x24 #define HAL_SPI_PORT_USART5 0x25 #define HAL_UART_FLOW_CONTROL_NONE 0 #define HAL_UART_FLOW_CONTROL_SW 1 #define HAL_UART_FLOW_CONTROL_HW 2 #define HAL_UART_FLOW_CONTROL_HWUART 3 #define HAL_USART_FLOW_CONTROL_NONE 0 #define HAL_USART_FLOW_CONTROL_SW 1 #define HAL_USART_FLOW_CONTROL_HW 2 #define HAL_USART_FLOW_CONTROL_HWUART 3 #define HAL_PA_SELECTION_2P4_HP 0 #define HAL_PA_SELECTION_2P4_MP 1 #define HAL_PA_SELECTION_2P4_LP 2 #define HAL_TIMER_TIMER0 0x20 #define HAL_TIMER_TIMER1 0x21 #define HAL_TIMER_TIMER2 0x22 #define HAL_TIMER_TIMER3 0x23 #define HAL_TIMER_TIMER4 0x24 #define HAL_TIMER_TIMER5 0x25 #define HAL_TIMER_TIMER6 0x26 #define HAL_TIMER_WTIMER0 0x30 #define HAL_TIMER_WTIMER1 0x31 #define HAL_TIMER_WTIMER2 0x32 #define HAL_TIMER_WTIMER3 0x33 #endif // HAL_CONFIG_TYPES_H |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/radio/rail_lib/autogen/librail_release/librail_efr32xg12_gcc_release.a.
cannot compute difference between binary files
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/radio/rail_lib/chip/efr32/efr32xg1x/rail_chip_specific.h.
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/***************************************************************************//** * @file * @brief This file contains the type definitions for efr32xg1x chip-specific * aspects of RAIL. ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * The licensor of this software is Silicon Laboratories Inc. Your use of this * software is governed by the terms of Silicon Labs Master Software License * Agreement (MSLA) available at * www.silabs.com/about-us/legal/master-software-license-agreement. This * software is distributed to you in Source Code format and is governed by the * sections of the MSLA applicable to Source Code. * ******************************************************************************/ #ifndef __RAIL_CHIP_SPECIFIC_H_ #define __RAIL_CHIP_SPECIFIC_H_ // Include standard type headers to help define structures #include <stdint.h> #include <stdbool.h> #include <stddef.h> #include "em_gpio.h" #include "em_device.h" #include "rail_types.h" #ifdef __cplusplus extern "C" { #endif // ----------------------------------------------------------------------------- // Multiprotocol // ----------------------------------------------------------------------------- /** * @def TRANSITION_TIME_US * @brief Time it takes to take care of protocol switching. */ #define TRANSITION_TIME_US 450 /** * @def EFR32XG1_RAIL_SCHEDULER_STATE_UINT32_BUFFER_SIZE * @brief The size in 32-bit words of RAIL_SchedulerStateBuffer_t to store * RAIL multiprotocol internal state for the EFR32XG1 series. */ #define EFR32XG1_RAIL_SCHEDULER_STATE_UINT32_BUFFER_SIZE 25 /** * @def EFR32XG12_RAIL_SCHEDULER_STATE_UINT32_BUFFER_SIZE * @brief The size in 32-bit words of RAIL_SchedulerStateBuffer_t to store * RAIL multiprotocol internal state for the EFR32XG12 series. */ #define EFR32XG12_RAIL_SCHEDULER_STATE_UINT32_BUFFER_SIZE 25 /** * @def EFR32XG13_RAIL_SCHEDULER_STATE_UINT32_BUFFER_SIZE * @brief The size in 32-bit words of RAIL_SchedulerStateBuffer_t to store * RAIL multiprotocol internal state for the EFR32XG13 series. */ #define EFR32XG13_RAIL_SCHEDULER_STATE_UINT32_BUFFER_SIZE 25 /** * @def EFR32XG14_RAIL_SCHEDULER_STATE_UINT32_BUFFER_SIZE * @brief The size in 32-bit words of RAIL_SchedulerStateBuffer_t to store * RAIL multiprotocol internal state for the EFR32XG14 series. */ #define EFR32XG14_RAIL_SCHEDULER_STATE_UINT32_BUFFER_SIZE 25 #if (_SILICON_LABS_32B_SERIES_1_CONFIG == 1) #define RAIL_SCHEDULER_STATE_UINT32_BUFFER_SIZE EFR32XG1_RAIL_SCHEDULER_STATE_UINT32_BUFFER_SIZE #elif (_SILICON_LABS_32B_SERIES_1_CONFIG == 2) #define RAIL_SCHEDULER_STATE_UINT32_BUFFER_SIZE EFR32XG12_RAIL_SCHEDULER_STATE_UINT32_BUFFER_SIZE #elif (_SILICON_LABS_32B_SERIES_1_CONFIG == 3) #define RAIL_SCHEDULER_STATE_UINT32_BUFFER_SIZE EFR32XG13_RAIL_SCHEDULER_STATE_UINT32_BUFFER_SIZE #elif (_SILICON_LABS_32B_SERIES_1_CONFIG == 4) #define RAIL_SCHEDULER_STATE_UINT32_BUFFER_SIZE EFR32XG14_RAIL_SCHEDULER_STATE_UINT32_BUFFER_SIZE #else #error "Unsupported platform!" #endif //_SILICON_LABS_32B_SERIES_1_CONFIG /** * @typedef RAIL_SchedulerStateBuffer_t * @brief A buffer used to store multiprotocol scheduler internal state. * * This buffer must be allocated in application global read-write memory * that persists for the duration of RAIL usage. It cannot be allocated * in read-only memory or on the call stack. */ typedef uint32_t RAIL_SchedulerStateBuffer_t[RAIL_SCHEDULER_STATE_UINT32_BUFFER_SIZE]; /** * @struct RAILSched_Config_t * @brief A multiprotocol scheduler configuration and internal state. * * This buffer must be allocated in application global read-write memory * that persists for the duration of RAIL usage. It cannot be allocated * in read-only memory or on the call stack. */ typedef struct RAILSched_Config { RAIL_SchedulerStateBuffer_t buffer; /**< An internal state buffer. */ } RAILSched_Config_t; /** * @def EFR32XG1_RAIL_STATE_UINT32_BUFFER_SIZE * @brief The size, in 32-bit words, of RAIL_StateBuffer_t to store RAIL * internal state for the EFR32XG1 series. */ #define EFR32XG1_RAIL_STATE_UINT32_BUFFER_SIZE 84 /** * @def EFR32XG12_RAIL_STATE_UINT32_BUFFER_SIZE * @brief The size, in 32-bit words, of RAIL_StateBuffer_t to store RAIL * internal state for the EFR32XG12 series. */ #define EFR32XG12_RAIL_STATE_UINT32_BUFFER_SIZE 84 /** * @def EFR32XG13_RAIL_STATE_UINT32_BUFFER_SIZE * @brief The size, in 32-bit words, of RAIL_StateBuffer_t to store RAIL * internal state for the EFR32XG13 series. */ #define EFR32XG13_RAIL_STATE_UINT32_BUFFER_SIZE 84 /** * @def EFR32XG14_RAIL_STATE_UINT32_BUFFER_SIZE * @brief The size, in 32-bit words, of RAIL_StateBuffer_t to store RAIL * internal state for the EFR32XG14 series. */ #define EFR32XG14_RAIL_STATE_UINT32_BUFFER_SIZE 84 #if (_SILICON_LABS_32B_SERIES_1_CONFIG == 1) #define RAIL_STATE_UINT32_BUFFER_SIZE EFR32XG1_RAIL_STATE_UINT32_BUFFER_SIZE #elif (_SILICON_LABS_32B_SERIES_1_CONFIG == 2) #define RAIL_STATE_UINT32_BUFFER_SIZE EFR32XG12_RAIL_STATE_UINT32_BUFFER_SIZE #elif (_SILICON_LABS_32B_SERIES_1_CONFIG == 3) #define RAIL_STATE_UINT32_BUFFER_SIZE EFR32XG13_RAIL_STATE_UINT32_BUFFER_SIZE #elif (_SILICON_LABS_32B_SERIES_1_CONFIG == 4) #define RAIL_STATE_UINT32_BUFFER_SIZE EFR32XG14_RAIL_STATE_UINT32_BUFFER_SIZE #else #error "Unsupported platform!" #endif //_SILICON_LABS_32B_SERIES_1_CONFIG /** * @typedef RAIL_StateBuffer_t * @brief A buffer to store RAIL internal state. */ typedef uint32_t RAIL_StateBuffer_t[RAIL_STATE_UINT32_BUFFER_SIZE]; /** * @struct RAIL_Config_t * @brief RAIL configuration and internal state structure. * * This structure must be allocated in application global read-write memory * that persists for the duration of RAIL usage. It cannot be allocated * in read-only memory or on the call stack. */ typedef struct RAIL_Config { /** * A pointer to a function, which is called whenever a RAIL event occurs. * * @param[in] railHandle A handle for a RAIL instance. * @param[in] events A bit mask of RAIL events. * @return void. * * See the \ref RAIL_Events_t documentation for the list of RAIL events. */ void (*eventsCallback)(RAIL_Handle_t railHandle, RAIL_Events_t events); /** * A pointer to a protocol-specific state structure allocated in global * read-write memory and initialized to all zeros. * For the BLE protocol, it should point to a RAIL_BLE_State_t * structure. For IEEE802154, it should be NULL. */ void *protocol; /** * A pointer to a RAIL scheduler state object allocated in global read-write * memory and initialized to all zeros. When not using a multiprotocol * scheduler, it should be NULL. */ RAILSched_Config_t *scheduler; /** * A structure for RAIL to maintain its internal state, which must be * initialized to all zeros. */ RAIL_StateBuffer_t buffer; } RAIL_Config_t; /** * @addtogroup Multiprotocol_EFR32 EFR32 * @{ * @brief EFR32-specific multiprotocol support defines * @ingroup Multiprotocol */ /** * A placeholder for a chip-specific RAIL handle. Using NULL as a RAIL handle is * not recommended. As a result, another value that can't be de-referenced is used. */ #define RAIL_EFR32_HANDLE ((RAIL_Handle_t)0xFFFFFFFFUL) /** @} */ // end of group Multiprotocol_EFR32 // ----------------------------------------------------------------------------- // Calibration // ----------------------------------------------------------------------------- /** * @addtogroup Calibration_EFR32 EFR32 * @{ * @brief EFR32-specific Calibrations * @ingroup Calibration * * The EFR32 supports the Image Rejection (IR) * calibration and a temperature-dependent calibration. The IR calibration * can be computed once and stored off or computed each time at * startup. Because it is PHY-specific and provides sensitivity improvements, * it is highly recommended. The IR calibration should only be run when the * radio is IDLE. * * The temperature-dependent calibrations are used to recalibrate the synth if * the temperature crosses 0C or the temperature delta since the last * calibration exceeds 70C while in receive. RAIL will run the VCO * calibration automatically upon entering receive state, so that the application can * omit this calibration if the stack re-enters receive with enough * frequency to avoid reaching the temperature delta. If the application does not * calibrate for temperature, it's possible to miss receive packets due to * a drift in the carrier frequency. */ /** EFR32-specific temperature calibration bit */ #define RAIL_CAL_TEMP_VCO (0x00000001U) /** EFR32-specific IR calibration bit */ #define RAIL_CAL_ONETIME_IRCAL (0x00010000U) /** A mask to run temperature-dependent calibrations */ #define RAIL_CAL_TEMP (RAIL_CAL_TEMP_VCO) /** A mask to run one-time calibrations */ #define RAIL_CAL_ONETIME (RAIL_CAL_ONETIME_IRCAL) /** A mask to run optional performance calibrations */ #define RAIL_CAL_PERF (0) /** A mask for calibrations that require the radio to be off */ #define RAIL_CAL_OFFLINE (RAIL_CAL_ONETIME_IRCAL) /** A mask to run all possible calibrations for this chip */ #define RAIL_CAL_ALL (RAIL_CAL_TEMP | RAIL_CAL_ONETIME) /** A mask to run all pending calibrations */ #define RAIL_CAL_ALL_PENDING (0x00000000U) /** An invalid calibration value */ #define RAIL_CAL_INVALID_VALUE (0xFFFFFFFFU) /** * Applies a given image rejection calibration value. * * @param[in] railHandle A RAIL instance handle. * @param[in] imageRejection The image rejection value to apply. * @return A status code indicating success of the function call. * * Take an image rejection calibration value and apply it. This value should be * determined from a previous run of \ref RAIL_CalibrateIr on the same * physical device with the same radio configuration. The imageRejection value * will also be stored to the \ref RAIL_ChannelConfigEntry_t::attr, if possible. * * If multiple protocols are used, this function will return * \ref RAIL_STATUS_INVALID_STATE if it is called and the given railHandle is * not active. In that case, the caller must attempt to re-call this function later. */ RAIL_Status_t RAIL_ApplyIrCalibration(RAIL_Handle_t railHandle, uint32_t imageRejection); /** * Runs the image rejection calibration. * * @param[in] railHandle A RAIL instance handle. * @param[out] imageRejection The result of the image rejection calibration. * @return A status code indicating success of the function call. * * Run the image rejection calibration and apply the resulting value. If the * imageRejection parameter is not NULL, store the value at that * location. The imageRejection value will also be stored to the * \ref RAIL_ChannelConfigEntry_t::attr, if possible. This is a long-running * calibration that adds significant code space when run and can be run with a * separate firmware image on each device to save code space in the * final image. * * If multiple protocols are used, this function will return * \ref RAIL_STATUS_INVALID_STATE if it is called and the given railHandle is * not active. In that case, the caller must attempt to re-call this function later. */ RAIL_Status_t RAIL_CalibrateIr(RAIL_Handle_t railHandle, uint32_t *imageRejection); /** * Calibrates image rejection for IEEE 802.15.4 2.4 GHz * * @param[in] railHandle A RAIL instance handle. * @param[out] imageRejection The result of the image rejection calibration. * @return A status code indicating success of the function call. * * Some chips have protocol-specific image rejection calibrations programmed * into their flash. This function will either get the value from flash and * apply it, or run the image rejection algorithm to find the value. */ RAIL_Status_t RAIL_IEEE802154_CalibrateIr2p4Ghz(RAIL_Handle_t railHandle, uint32_t *imageRejection); /** * Calibrates image rejection for IEEE 802.15.4 915 MHz and 868 MHz * * @param[in] railHandle A RAIL instance handle. * @param[out] imageRejection The result of the image rejection calibration. * @return A status code indicating success of the function call. * * Some chips have protocol-specific image rejection calibrations programmed * into their flash. This function will either get the value from flash and * apply it, or run the image rejection algorithm to find the value. */ RAIL_Status_t RAIL_IEEE802154_CalibrateIrSubGhz(RAIL_Handle_t railHandle, uint32_t *imageRejection); /** * Calibrates image rejection for Bluetooth Low Energy * * @param[in] railHandle A RAIL instance handle. * @param[out] imageRejection The result of the image rejection calibration. * @return A status code indicating success of the function call. * * Some chips have protocol-specific image rejection calibrations programmed * into their flash. This function will either get the value from flash and * apply it, or run the image rejection algorithm to find the value. */ RAIL_Status_t RAIL_BLE_CalibrateIr(RAIL_Handle_t railHandle, uint32_t *imageRejection); /** * Runs the temperature calibration. * * @param[in] railHandle A RAIL instance handle. * @return A status code indicating success of the function call. * * Run the temperature calibration, which needs to recalibrate the synth if * the temperature crosses 0C or the temperature delta since the last * calibration exceeds 70C while in receive. RAIL will run the VCO * calibration automatically upon entering receive state, so that the application can * omit this calibration if the stack re-enters receive with enough * frequency to avoid reaching the temperature delta. If the application does not * calibrate for temperature, it's possible to miss receive packets due to * a drift in the carrier frequency. * * If multiple protocols are used, this function will return * \ref RAIL_STATUS_INVALID_STATE if it is called and the given railHandle is * not active. In that case, the calibration will be automatically performed * next time the radio enters receive. */ RAIL_Status_t RAIL_CalibrateTemp(RAIL_Handle_t railHandle); /** * @struct RAIL_CalValues_t * @brief A calibration value structure. * * This structure contains the set of persistent calibration values for * EFR32. You can set these beforehand and apply them at startup to save the * time required to compute them. Any of these values may be set to * RAIL_CAL_INVALID_VALUE to force the code to compute that calibration value. */ typedef struct RAIL_CalValues { uint32_t imageRejection; /**< An Image Rejection (IR) calibration value */ } RAIL_CalValues_t; /** * A define to set all RAIL_CalValues_t values to uninitialized. * * This define can be used when you have no data to pass to the calibration * routines but wish to compute and save all possible calibrations. */ #define RAIL_CALVALUES_UNINIT (RAIL_CalValues_t){ \ RAIL_CAL_INVALID_VALUE, \ } /** @} */ // end of group Calibration_EFR32 // ----------------------------------------------------------------------------- // Diagnostic // ----------------------------------------------------------------------------- /** * @addtogroup Diagnostic_EFR32 EFR32 * @{ * @brief Types specific to the EFR32 for the diagnostic routines. * @ingroup Diagnostic */ /** * @typedef RAIL_FrequencyOffset_t * @brief Chip-specific type that represents the number of Frequency Offset * units. It is used with \ref RAIL_GetRxFreqOffset() and * \ref RAIL_SetFreqOffset(). * * The units on this chip are radio synthesizer resolution steps (synthTicks). * On EFR32 (at least for now), the frequency offset is limited to 15 bits * (size of SYNTH_CALOFFSET). A value of \ref RAIL_FREQUENCY_OFFSET_INVALID * means that this value is invalid. */ typedef int16_t RAIL_FrequencyOffset_t; /** * Specifies an invalid frequency offset value. This will be returned if you * call \ref RAIL_GetRxFreqOffset() at an invalid time. */ #define RAIL_FREQUENCY_OFFSET_INVALID ((int16_t)0xFFFF) /** @} */ // end of group Diagnostic_EFR32 // ----------------------------------------------------------------------------- // Radio Configuration // ----------------------------------------------------------------------------- /** * @addtogroup Radio_Configuration_EFR32 EFR32 * @{ * @ingroup Radio_Configuration * @brief Types specific to the EFR32 for radio configuration. */ /** * @brief The radio configuration structure. * * The radio configuration properly configures the * radio for operation on a protocol. These configurations should not be * created or edited by hand. */ typedef const uint32_t *RAIL_RadioConfig_t; /** @} */ // end of group Radio_Configuration_EFR32 // ----------------------------------------------------------------------------- // Transmit // ----------------------------------------------------------------------------- /** * @addtogroup PA_EFR32 EFR32 * @{ * @ingroup PA * @brief Types specific to the EFR32 for dealing with the on-chip PAs. */ /** * Raw power levels used directly by the RAIL_Get/SetTxPower API where a higher * numerical value corresponds to a higher output power. These are referred to * as 'raw (values/units)'. On EFR32, they can range from one of \ref * RAIL_TX_POWER_LEVEL_LP_MIN, \ref RAIL_TX_POWER_LEVEL_HP_MIN, or * \ref RAIL_TX_POWER_LEVEL_SUBGIG_MIN to one of \ref * RAIL_TX_POWER_LEVEL_LP_MAX, \ref RAIL_TX_POWER_LEVEL_HP_MAX, and \ref * RAIL_TX_POWER_LEVEL_SUBGIG_MAX, respectively, depending on the selected \ref * RAIL_TxPowerMode_t. */ typedef uint8_t RAIL_TxPowerLevel_t; /** * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref * RAIL_TX_POWER_MODE_2P4_LP mode. */ #define RAIL_TX_POWER_LEVEL_LP_MAX (7U) /** * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref * RAIL_TX_POWER_MODE_2P4_HP mode. */ #define RAIL_TX_POWER_LEVEL_HP_MAX (252U) /** * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref * RAIL_TX_POWER_MODE_SUBGIG mode. */ #define RAIL_TX_POWER_LEVEL_SUBGIG_MAX (248U) /** * The minimum valid value for the \ref RAIL_TxPowerLevel_t when in \ref * RAIL_TX_POWER_MODE_2P4_LP mode. */ #define RAIL_TX_POWER_LEVEL_LP_MIN (1U) /** * The minimum valid value for the \ref RAIL_TxPowerLevel_t when in \ref * RAIL_TX_POWER_MODE_2P4_HP mode. */ #define RAIL_TX_POWER_LEVEL_HP_MIN (0U) /** * The minimum valid value for the \ref RAIL_TxPowerLevel_t when in \ref * RAIL_TX_POWER_MODE_SUBGIG mode. */ #define RAIL_TX_POWER_LEVEL_SUBGIG_MIN (0U) /** * Invalid RAIL_TxPowerLevel_t value returned when an error occurs * with RAIL_GetTxPower. */ #define RAIL_TX_POWER_LEVEL_INVALID (255U) /** * @enum RAIL_TxPowerMode_t * @brief An enumeration of the EFR32 power modes. * * The power modes on the EFR32 correspond to the different on-chip PAs that * are available. For more information about the power and performance * characteristics of a given amplifier, see the data sheet. */ RAIL_ENUM(RAIL_TxPowerMode_t) { /** High-power amplifier, up to 20 dBm, raw values: 0-252 */ RAIL_TX_POWER_MODE_2P4_HP, /** Low-power amplifier, up to 0 dBm, raw values: 1-7 */ RAIL_TX_POWER_MODE_2P4_LP, /** SubGig amplifier, up to 20 dBm, raw values: 0-248 */ RAIL_TX_POWER_MODE_SUBGIG, /** Invalid amplifier Selection */ RAIL_TX_POWER_MODE_NONE, }; #ifndef DOXYGEN_SHOULD_SKIP_THIS // Self-referencing defines minimize compiler complaints when using RAIL_ENUM #define RAIL_TX_POWER_MODE_2P4_HP ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_2P4_HP) #define RAIL_TX_POWER_MODE_2P4_LP ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_2P4_LP) #define RAIL_TX_POWER_MODE_SUBGIG ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_SUBGIG) #define RAIL_TX_POWER_MODE_NONE ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_NONE) #endif//DOXYGEN_SHOULD_SKIP_THIS /** * @def RAIL_TX_POWER_MODE_NAMES * @brief The names of the TX power modes * * A list of the names for the TX power modes on the EFR32 series 1 parts. This * macro is useful for test applications and debugging output. */ #define RAIL_TX_POWER_MODE_NAMES { \ "RAIL_TX_POWER_MODE_2P4_HP", \ "RAIL_TX_POWER_MODE_2P4_LP", \ "RAIL_TX_POWER_MODE_SUBGIG", \ "RAIL_TX_POWER_MODE_NONE" \ } /** * @struct RAIL_TxPowerConfig_t * * @brief A structure containing values used to initialize the power amplifiers. */ typedef struct RAIL_TxPowerConfig { /** TX power mode */ RAIL_TxPowerMode_t mode; /** Power amplifier supply voltage in mV, generally: * DCDC supply ~ 1800 mV (1.8 V) * Battery supply ~ 3300 mV (3.3 V) */ uint16_t voltage; /** The amount of time to spend ramping for TX in uS. */ uint16_t rampTime; } RAIL_TxPowerConfig_t; /** @} */ // end of group PA_EFR32 // ----------------------------------------------------------------------------- // PTI // ----------------------------------------------------------------------------- /** * @addtogroup PTI_EFR32 EFR32 * @{ * @brief EFR32 PTI functionality * @ingroup PTI * * These enumerations and structures are used with RAIL PTI API. EFR32 supports * SPI and UART PTI and is configurable in terms of baud rates and pin PTI * pin locations. */ /** A channel type enumeration. */ RAIL_ENUM(RAIL_PtiMode_t) { /** Turn PTI off entirely. */ RAIL_PTI_MODE_DISABLED, /** SPI mode. */ RAIL_PTI_MODE_SPI, /** UART mode. */ RAIL_PTI_MODE_UART, /** 9-bit UART mode. */ RAIL_PTI_MODE_UART_ONEWIRE, }; #ifndef DOXYGEN_SHOULD_SKIP_THIS // Self-referencing defines minimize compiler complaints when using RAIL_ENUM #define RAIL_PTI_MODE_DISABLED ((RAIL_PtiMode_t) RAIL_PTI_MODE_DISABLED) #define RAIL_PTI_MODE_SPI ((RAIL_PtiMode_t) RAIL_PTI_MODE_SPI) #define RAIL_PTI_MODE_UART ((RAIL_PtiMode_t) RAIL_PTI_MODE_UART) #define RAIL_PTI_MODE_UART_ONEWIRE ((RAIL_PtiMode_t) RAIL_PTI_MODE_UART_ONEWIRE) #endif//DOXYGEN_SHOULD_SKIP_THIS /** * @struct RAIL_PtiConfig_t * @brief A configuration for PTI. */ typedef struct RAIL_PtiConfig { /** Packet Trace mode (UART or SPI) */ RAIL_PtiMode_t mode; /** Output baudrate for PTI in Hz */ uint32_t baud; /** Data output (DOUT) location for pin/port */ uint8_t doutLoc; /** Data output (DOUT) GPIO port */ GPIO_Port_TypeDef doutPort; /** Data output (DOUT) GPIO pin */ uint8_t doutPin; /** Data clock (DCLK) location for pin/port. Only used in SPI mode */ uint8_t dclkLoc; /** Data clock (DCLK) GPIO port. Only used in SPI mode */ GPIO_Port_TypeDef dclkPort; /** Data clock (DCLK) GPIO pin. Only used in SPI mode */ uint8_t dclkPin; /** Data frame (DFRAME) location for pin/port */ uint8_t dframeLoc; /** Data frame (DFRAME) GPIO port */ GPIO_Port_TypeDef dframePort; /** Data frame (DFRAME) GPIO pin */ uint8_t dframePin; } RAIL_PtiConfig_t; /** @} */ // end of group PTI_EFR32 // ----------------------------------------------------------------------------- // Antenna Control // ----------------------------------------------------------------------------- /** * @addtogroup Antenna_Control_EFR32 EFR32 * @{ * @brief EFR32 Antenna Control Functionality * @ingroup Antenna_Control * * These enumerations and structures are used with RAIL Antenna Control API. EFR32 supports * up to two antennas with configurable pin locations. */ /** Antenna path Selection enumeration. */ RAIL_ENUM(RAIL_AntennaSel_t) { /** Enum for antenna path 0. */ RAIL_ANTENNA_0 = 0, /** Enum for antenna path 1. */ RAIL_ANTENNA_1 = 1, /** Enum for antenna path auto. */ RAIL_ANTENNA_AUTO = 255, }; #ifndef DOXYGEN_SHOULD_SKIP_THIS // Self-referencing defines minimize compiler complaints when using RAIL_ENUM #define RAIL_ANTENNA_0 ((RAIL_AntennaSel_t) RAIL_ANTENNA_0) #define RAIL_ANTENNA_1 ((RAIL_AntennaSel_t) RAIL_ANTENNA_1) #define RAIL_ANTENNA_AUTO ((RAIL_AntennaSel_t) RAIL_ANTENNA_AUTO) #endif//DOXYGEN_SHOULD_SKIP_THIS /** * @struct RAIL_AntennaConfig_t * @brief A configuration for antenna selection. */ typedef struct RAIL_AntennaConfig { /** MODEM_ROUTEPEN fields */ /** Antenna 0 Pin Enable */ bool ant0PinEn; /** Antenna 1 Pin Enable */ bool ant1PinEn; /** MODEM_ROUTELOC1 fields */ /** Antenna 0 location for pin/port */ uint8_t ant0Loc; /** Antenna 0 output GPIO port */ GPIO_Port_TypeDef ant0Port; /** Antenna 0 output GPIO pin */ uint8_t ant0Pin; /** Antenna 1 location for pin/port */ uint8_t ant1Loc; /** Antenna 1 output GPIO port */ GPIO_Port_TypeDef ant1Port; /** Antenna 1 output GPIO pin */ uint8_t ant1Pin; } RAIL_AntennaConfig_t; /** @} */ // end of group Antenna_Control_EFR32 /****************************************************************************** * Calibration Structures *****************************************************************************/ /** * @addtogroup Calibration * @{ */ /// Use this value with either TX or RX values in RAIL_SetPaCTune /// to use whatever value is already set and do no update. #define RAIL_PACTUNE_IGNORE (255U) /** @} */ // end of group Calibration /****************************************************************************** * RX Channel Hopping *****************************************************************************/ /** * @addtogroup Rx_Channel_Hopping RX Channel Hopping * @{ */ /// The static amount of memory needed per channel for channel /// hopping, regardless of the size of radio configuration structures. #define RAIL_CHANNEL_HOPPING_BUFFER_SIZE_PER_CHANNEL (25U) /** @} */ // end of group Rx_Channel_Hopping #ifdef __cplusplus } #endif #endif |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/radio/rail_lib/common/rail.h.
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/***************************************************************************//** * @file * @brief The main header file for the RAIL library. It describes the external * APIs available to a RAIL user ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * The licensor of this software is Silicon Laboratories Inc. Your use of this * software is governed by the terms of Silicon Labs Master Software License * Agreement (MSLA) available at * www.silabs.com/about-us/legal/master-software-license-agreement. This * software is distributed to you in Source Code format and is governed by the * sections of the MSLA applicable to Source Code. * ******************************************************************************/ #ifndef __RAIL_H__ #define __RAIL_H__ // Get the standard include types #include <stdint.h> #include <stdbool.h> #include <string.h> // For memcpy() // Get the RAIL-specific structures and types #include "rail_chip_specific.h" #include "rail_types.h" #include "rail_assert_error_codes.h" #ifdef __cplusplus extern "C" { #endif /** * @addtogroup RAIL_API RAIL API * @brief This is the primary API layer for the Radio Abstraction Interface * Layer (RAIL) * @{ */ /** * @defgroup Protocol_Specific Protocol-specific * @brief Protocol-specific RAIL APIs */ /****************************************************************************** * General Radio Operation *****************************************************************************/ /** * @addtogroup General * @brief Basic APIs to set up and interact with the RAIL library * @{ */ /** * Gets the version information for the compiled RAIL library. * * @param[out] version A pointer to \ref RAIL_Version_t structure to * populate with version information. * @param[in] verbose Populate \ref RAIL_Version_t struct with verbose * information. * @return void. * * The version information contains a major version number, a minor version * number, and a rev (revision) number. */ void RAIL_GetVersion(RAIL_Version_t *version, bool verbose); /** * Initializes RAIL. * * @param[in,out] railCfg The configuration and state structure for setting up * the library, which contains memory and other options needed by RAIL. * This structure must be allocated in application global read-write * memory. RAIL may modify fields within or referenced by this structure * during its operation. * @param[in] cb A callback that notifies the application when the radio is * finished initializing and is ready for further configuration. This * callback is useful for potential transceiver products that require a * power up sequence before further configuration is available. After the * callback fires, the radio is ready for additional configuration before * transmit and receive operations. * @return Handle for initialized rail instance or NULL if an * invalid value was passed in the railCfg. */ RAIL_Handle_t RAIL_Init(RAIL_Config_t *railCfg, RAIL_InitCompleteCallbackPtr_t cb); /** * Get RAIL Initialization status. * * @return True if the radio has finished initializing and * false otherwise. * * RAIL APIs, for e.g. RAIL_GetTime(), which work only if RAIL_Init() has been called, * can use RAIL_IsInitialized() to determine whether RAIL has been initialized or not. */ bool RAIL_IsInitialized(void); /** * Blocking delay routine for specified number of microseconds. * * @param[in] microseconds Delay duration in microseconds. * @return Status code indicating success of the function call. * * This RAIL API should only be used for short blocking delays, as it has less overhead * than calling RAIL_GetTime() in a loop. * @note * Passing large delay values may give unpredictable results or trigger * the Watchdog Reset. * \n Also, this function will start the clocks required for the RAIL timebase if they * are not running, except in the case between \ref RAIL_Sleep() and \ref RAIL_Wake() * where the timer must remain stopped. * \n Interrupts are not disabled during the delay, so the delay may be longer if an * interrupt extends beyond the delay duration. */ RAIL_Status_t RAIL_DelayUs(RAIL_Time_t microseconds); /** * Collects entropy from the radio if available. * * @param[in] railHandle A RAIL instance handle. * @param[out] buffer The buffer to write the collected entropy. * @param[in] bytes The number of bytes to fill in in the input buffer. * @return Returns the number of bytes of entropy collected. For * chips that don't support entropy collection, the function returns 0. * Values less than the requested amount may also be returned on platforms * that use entropy pools to collect random data periodically. * * Attempts to fill the provided buffer with the requested number of bytes of * entropy. If the requested number of bytes can't be provided, as many * bytes as possible will be filled and returned. For chips * that do not support this function, 0 bytes are always returned. For * information about the specific mechanism for gathering entropy, see * documentation for the chip family. */ uint16_t RAIL_GetRadioEntropy(RAIL_Handle_t railHandle, uint8_t *buffer, uint16_t bytes); /** @} */ // end of group General /****************************************************************************** * PTI *****************************************************************************/ /** * @addtogroup PTI Packet Trace (PTI) * @brief Basic APIs to set up and interact with PTI settings * @{ */ /** * Configures PTI pin locations, serial protocols, and baud rates. * * @param[in] railHandle A RAIL instance handle (currently not used). * @param[in] ptiConfig A configuration structure applied to the * relevant PTI registers. A NULL ptiConfig will produce undefined * behavior. * @return Status code indicating success of the function call. * * This method must be called before RAIL_EnablePti() is called. * Although a RAIL handle is included for potential future * expansion of this function, it is currently not used. That is, * there is only one PTI configuration that can be active on a * chip, regardless of the number of protocols (unless the application * updates the configuration upon a protocol switch), * and the configuration is not saved in the RAIL instance. For optimal * future compatibility, pass in a chip-specific handle, such as * \ref RAIL_EFR32_HANDLE. */ RAIL_Status_t RAIL_ConfigPti(RAIL_Handle_t railHandle, const RAIL_PtiConfig_t *ptiConfig); /** * Gets the currently active PTI configuration. * * @param[in] railHandle A RAIL instance handle (currently not used). * @param[out] ptiConfig A configuration structure filled with the active * PTI configuration. * @return RAIL status indicating success of the function call. * * Although most combinations of configurations can be set, it is safest * to call this method after configuration to confirm which values were * actually set. As in RAIL_ConfigPti, railHandle is not used. This function * always returns the single active PTI configuration regardless of the * active protocol. For optimal future compatibility, pass in a chip * specific handle, such as \ref RAIL_EFR32_HANDLE. */ RAIL_Status_t RAIL_GetPtiConfig(RAIL_Handle_t railHandle, RAIL_PtiConfig_t *ptiConfig); /** * Enables Packet Trace Interface (PTI) output of packet data. * * @param[in] railHandle A RAIL instance handle (currently not used). * @param[in] enable PTI is enabled if true; disable if false. * @return RAIL status indicating success of the function call. * * Similarly to having only one PTI configuration per chip, * PTI can only be enabled or disabled for all protocols. It cannot * be individually set to enabled and disabled per protocol * (unless the application switches it when * the protocol switches), and enable/disable is not saved as part of the * RAIL instance. For optimal future compatibility, pass in a chip-specific * handle, such as \ref RAIL_EFR32_HANDLE. */ RAIL_Status_t RAIL_EnablePti(RAIL_Handle_t railHandle, bool enable); /** * Sets a protocol that RAIL outputs on PTI. * * @param[in] railHandle A RAIL instance handle. * @param[in] protocol The enumeration representing which protocol the node is using. * @return Status code indicating success of the function call. * * The protocol is output via PTI for each packet. * Before any protocol is set, the default value is \ref * RAIL_PTI_PROTOCOL_CUSTOM. Use one of the enumeration values so that * the Network Analyzer can decode the packet. */ RAIL_Status_t RAIL_SetPtiProtocol(RAIL_Handle_t railHandle, RAIL_PtiProtocol_t protocol); /** @} */ // end of group PTI /****************************************************************************** * Antenna Control *****************************************************************************/ /** * @addtogroup Antenna_Control Antenna Control * @brief Basic APIs to control the Antenna functionality * @{ */ /** * Configures antenna path and pin locations. * * @warning This API must be called before any TX or RX takes place, otherwise * the antenna configurations for those functions will not take effect. * * @param[in] railHandle A RAIL instance handle. * @param[in] config A configuration structure applied to the relevant Antenna * Configuration registers. A NULL config will produce undefined behavior. * @return Status code indicating success of the function call. * * This function tells RAIL how to select each antenna, but not when. * Antenna selection for receive is controlled by the * \ref RAIL_RxOptions_t::RAIL_RX_OPTION_ANTENNA0 and * \ref RAIL_RxOptions_t::RAIL_RX_OPTION_ANTENNA1 options * (and the \ref RAIL_RxOptions_t::RAIL_RX_OPTION_ANTENNA_AUTO combination). * Antenna selection for transmit is controlled by the * \ref RAIL_TxOptions_t::RAIL_TX_OPTION_ANTENNA0 and * \ref RAIL_TxOptions_t::RAIL_TX_OPTION_ANTENNA1 options. * * Although a RAIL handle is included for potential future * expansion of this function, it is currently not used. That is, * there is only one Antenna configuration that can be active on a * chip, regardless of the number of protocols (unless the application * updates the configuration upon a protocol switch), * and the configuration is not saved in the RAIL instance. For optimal * future compatibility, pass in a chip-specific handle, such as * \ref RAIL_EFR32_HANDLE. */ RAIL_Status_t RAIL_ConfigAntenna(RAIL_Handle_t railHandle, const RAIL_AntennaConfig_t *config); /** @} */ // end of group Antenna_Control /****************************************************************************** * Radio Configuration *****************************************************************************/ /// @addtogroup Radio_Configuration Radio Configuration /// @brief Routines for setting up and querying radio configuration information. /// /// These routines allow for runtime flexibility in the radio /// configuration. Some of the parameters, however, are meant to be generated /// from the radio calculator in Simplicity Studio. The basic code to configure /// the radio from this calculator output looks like the example below. /// /// @code{.c} /// // Associate a specific channel config with a particular RAIL instance, and /// // load the settings that correspond to the first usable channel. /// RAIL_ConfigChannels(railHandle, channelConfigs[0]); /// @endcode /// /// For more information about the types of parameters that can be changed in /// the other functions and how to use them, see their individual documentation. /// /// @{ /** * Loads a static radio configuration. * * @param[in] railHandle A RAIL instance handle. * @param[in] config A pointer to a radio configuration. * @return Status code indicating success of the function call. * * The configuration passed into this function should be auto-generated * and not manually created or edited. By default this function should not be * called in RAIL 2.x and later unless a non-default radio configuration needs * to be applied. In RAIL 2.x and later, the RAIL_ConfigChannels function * applies the default radio configuration automatically. */ RAIL_Status_t RAIL_ConfigRadio(RAIL_Handle_t railHandle, RAIL_RadioConfig_t config); /** * Modifies the currently configured fixed frame length in bytes. * * @param[in] railHandle A RAIL instance handle. * @param[in] length The expected fixed frame length. A value of 0 is infinite. * A value of RAIL_SETFIXEDLENGTH_INVALID restores the frame's length back to * the length specified by the default frame type configuration. * @return Length configured; The new frame length configured into the hardware * for use. 0 if in infinite mode, or RAIL_SETFIXEDLENGTH_INVALID if the frame * length has not yet been overridden by a valid value. * * Sets the fixed-length configuration for transmit and receive. * Be careful when using this function in receive and transmit as this * function changes the default frame configuration and remains in force until * it is called again with an input value of RAIL_SETFIXEDLENGTH_INVALID. This * function will override any fixed or variable length settings from a radio * configuration. */ uint16_t RAIL_SetFixedLength(RAIL_Handle_t railHandle, uint16_t length); /** * Configures the channels supported by this device. * * @param[in] railHandle A RAIL instance handle. * @param[in] config A pointer to the channel configuration for your device. * This pointer will be cached in the library so it must * exist for the runtime of the application. Typically, this should be * what is stored in Flash by the configuration tool. * @param[in] cb Function called whenever a radio configuration change occurs. * @return Returns the first available channel in the configuration. * * When configuring channels on EFR32, the radio tuner is reconfigured * based on the frequency and channel spacing in the channel configuration. * * @note config can be NULL to simply register or unregister the cb callback * function when using RAIL internal protocol-specific radio configuration * APIs for BLE, IEEE 802.15.4, or Z-Wave, which lack callback specification. * In this use case, 0 is returned. */ uint16_t RAIL_ConfigChannels(RAIL_Handle_t railHandle, const RAIL_ChannelConfig_t *config, RAIL_RadioConfigChangedCallback_t cb); /** * Checks to see if the channel exists in RAIL. * * @param[in] railHandle A RAIL instance handle. * @param[in] channel A channel number to check. * @return Returns RAIL_STATUS_NO_ERROR if channel exists * * Returns RAIL_STATUS_INVALID_PARAMETER if the given channel does not exist * in the channel configuration currently used or RAIL_STATUS_NO_ERROR if the * channel is valid. */ RAIL_Status_t RAIL_IsValidChannel(RAIL_Handle_t railHandle, uint16_t channel); /** * Causes radio settings associated with a particular channel to be applied to * hardware. * * @param[in] railHandle A RAIL instance handle. * @param[in] channel The channel to prepare for use. * @return \ref RAIL_STATUS_NO_ERROR on success or * \ref RAIL_STATUS_INVALID_PARAMETER if the given channel does not have an * associated channel configuration entry or * \ref RAIL_STATUS_INVALID_STATE if the specified railHandle is not the * current RAIL handle in use. \ref RAIL_STATUS_INVALID_STATE is only used * in the multiprotocol version of RAIL. * * This function walks the channelConfigEntry list and applies the configuration * associated with the specified channel. This function is used to manually * change channels without actually starting a TX or RX operation. * * A successful return of this function will result in the radio being left in * the idle state. An unsuccessful return of this function will not alter the * radio state. */ RAIL_Status_t RAIL_PrepareChannel(RAIL_Handle_t railHandle, uint16_t channel); /** * Returns the current RAIL channel. * * @param[in] railHandle A RAIL instance handle. * @param[out] channel The channel for which RAIL is currently configured. * @return RAIL_STATUS_NO_ERROR on success or * RAIL_STATUS_INVALID_CALL if the radio is not configured for any channel or * RAIL_STATUS_INVALID_PARAMETER if channel parameter is NULL. * * This function returns the channel configured for use corresponding to the * specified RAIL handle whether or not the specified handle is the active one. */ RAIL_Status_t RAIL_GetChannel(RAIL_Handle_t railHandle, uint16_t *channel); /** * Returns the symbol rate for the current PHY. * * @param[in] railHandle A RAIL instance handle. * @return The symbol rate in symbols per second or 0. * * The symbol rate is the rate of symbol changes over the air. For non-DSSS * PHYs, this is the same as the baudrate. For DSSS PHYs, it is the baudrate * divided by the length of a chipping sequence. For more information, * see the modem calculator documentation. If the rate cannot be * calculated, this function returns 0. */ uint32_t RAIL_GetSymbolRate(RAIL_Handle_t railHandle); #ifndef DOXYGEN_SHOULD_SKIP_THIS /** * Calculates the symbol rate for the current PHY. * * @param[in] railHandle A RAIL instance handle. * @return The symbol rate in symbols per second or 0. * * This function is used to calculate the symbol rate when the radio config does * not include that information. In the general case, this function should be * implemented automatically in the radio config as a stub. */ uint32_t RAILCb_CalcSymbolRate(RAIL_Handle_t railHandle); #endif /** * Returns the bit rate for the current PHY. * * @param[in] railHandle A RAIL instance handle. * @return The bit rate in bits per second or 0. * * The bit rate is the effective over-the-air data rate. It does not account * for extra spreading for forward error correction, and so on, but * accounts for modulation schemes, DSSS, and other configurations. For more * information, see the modem calculator documentation. If the rate cannot be * calculated, this function returns 0. */ uint32_t RAIL_GetBitRate(RAIL_Handle_t railHandle); #ifndef DOXYGEN_SHOULD_SKIP_THIS /** * Calculates the bit rate for the current PHY. * * @param[in] railHandle A RAIL instance handle. * @return The bit rate in bits per second or 0. * * This function is used to calculate the bit rate when the radio config does * not include that information. In the general case, this function should be * implemented automatically in the radio config as a stub. */ uint32_t RAILCb_CalcBitRate(RAIL_Handle_t railHandle); #endif /** * Sets the PA capacitor tune value for transmit and receive. * * @param[in] railHandle A RAIL instance handle. * @param[in] txPaCtuneValue PA Ctune value for TX mode. * @param[in] rxPaCtuneValue PA Ctune value for RX mode. * @return Status code indicating success of the function call. * * Tunes the impedance of the transmit * and receive modes by changing the amount of capacitance at * the PA output. */ RAIL_Status_t RAIL_SetPaCTune(RAIL_Handle_t railHandle, uint8_t txPaCtuneValue, uint8_t rxPaCtuneValue); /** @} */ // end of group Radio_Configuration /****************************************************************************** * Timing Information *****************************************************************************/ /** * @addtogroup System_Timing System Timing * @brief Functionality related to the RAIL timer and general system time. * * These functions can be used to get information about the current system time * or to manipulate the RAIL timer. * * The system time returned by RAIL_GetTime() is in the same timebase that is * used throughout RAIL. Any callbacks that return a timestamp, such as * rxPacketReceived(), will use the same timebase as will any APIs * that accept an absolute time for scheduling their action. Throughout the * documentation, the timebase is referred to as the RAIL * timebase. The timebase is currently a value in microseconds from chip boot time, * which means that it will wrap every 1.19 hours. * (`(2^32 - 1) / (3600 sec/hr * 1000000 us/sec)`). * * The provided timer is hardware-backed and interrupt-driven. It can be used * for timing any event in the system, but is especially helpful for * timing protocol-based state machines and other systems that interact with * the radio. To avoid processing the expiration in interrupt * context, leave the timerExpired() callback empty and poll for expiration * with the RAIL_IsTimerExpired() function. * * @{ */ /** * Gets the current RAIL time. * * @return Returns the RAIL timebase in microseconds. Note that this wraps * after about 1.19 hours since it's stored in a 32bit value. * * Returns the current time in the RAIL timebase (microseconds). It can be * used to compare with packet timestamps or to schedule transmits. */ RAIL_Time_t RAIL_GetTime(void); /** * Sets the current RAIL time. * * @param[in] time Set the RAIL timebase to this value in microseconds. * @return Status code indicating success of the function call. * * Sets the current time in the RAIL timebase in microseconds. */ RAIL_Status_t RAIL_SetTime(RAIL_Time_t time); /** * Schedules a timer to expire using the RAIL timebase. * * @param[in] railHandle A RAIL instance handle. * @param[in] time The timer's expiration time in the RAIL timebase. * @param[in] mode Indicates whether the time argument is an absolute * RAIL time or relative to the current RAIL time. Specifying mode * \ref RAIL_TIME_DISABLED is the same as calling RAIL_CancelTimer(). * @param[in] cb The callback for RAIL to call when the timer expires. * @return RAIL_STATUS_NO_ERROR on success and * RAIL_STATUS_INVALID_PARAMETER if the timer can't be scheduled. * * Configures a timer to expire after a period in the RAIL timebase. * This timer can be used to implement low-level protocol features. * * @warning Attempting to schedule the timer when it is * still running from a previous request is bad practice, unless the cb callback is * identical to that used in the previous request, in which case the * timer is rescheduled to the new time. Note that if * the original timer expires as it is being rescheduled, the callback * may or may not occur. It is generally good practice to cancel a * running timer before rescheduling it to minimize ambiguity. */ RAIL_Status_t RAIL_SetTimer(RAIL_Handle_t railHandle, RAIL_Time_t time, RAIL_TimeMode_t mode, RAIL_TimerCallback_t cb); /** * Returns the absolute time that the RAIL timer was configured to expire. * * @param[in] railHandle A RAIL instance handle. * @return The absolute time that this timer was set to expire. * * Provides the absolute time regardless of the \ref RAIL_TimeMode_t that * was passed into \ref RAIL_SetTimer. Note that the time might be in the * past if the timer has already expired. The return value is undefined if the * timer was never set. */ RAIL_Time_t RAIL_GetTimer(RAIL_Handle_t railHandle); /** * Stops the currently scheduled RAIL timer. * * @param[in] railHandle A RAIL instance handle. * @return void. * * Cancels the timer. If this function is called before the timer expires, * the cb callback specified in the earlier RAIL_SetTimer() call will never * be called. */ void RAIL_CancelTimer(RAIL_Handle_t railHandle); /** * Checks whether the RAIL timer has expired. * * @param[in] railHandle A RAIL instance handle. * @return True if the previously scheduled timer has expired and false * otherwise. * * Polling via this function can be used as an alternative to the callback. */ bool RAIL_IsTimerExpired(RAIL_Handle_t railHandle); /** * Checks whether the RAIL timer is currently running. * * @param[in] railHandle A RAIL instance handle. * @return Returns true if the timer is running and false if * the timer has expired or was never set. */ bool RAIL_IsTimerRunning(RAIL_Handle_t railHandle); /** * Configures the RAIL software timer feature. * * @param[in] enable Enables/disables the RAIL multitimer. * @return True if the multitimer was successfully enabled/disabled, false * otherwise. * * Turning this on will add a software timer layer above the physical RAIL timer * so that the user can have as many timers as desired. It is not necessary to * call this function if the MultiTimer APIs are not used. * * @note This function must be called before calling \ref RAIL_SetMultiTimer. * This function is a no-op on multiprotocol as this layer is already used * under the hood. * It should not be called while the RAIL timer is running. * Call \ref RAIL_IsTimerRunning before enabling/disabling the multitimer. * If the multitimer is not needed, do not call this function to * allow the multitimer code to be dead stripped. * If the multiTimer is enabled for use, the multiTimer and timer APIs # can both be used; however, no timer can be in use while this function # is being called. */ bool RAIL_ConfigMultiTimer(bool enable); /** * Starts a multitimer instance. * * @note * It is legal to start an already running timer. If this is done, the timer * will first be stopped before the new configuration is applied. * If expirationTime is 0, the callback is called * immediately. * * @param[in,out] tmr A pointer to the timer instance to start. * @param[in] expirationTime A time when the timer is set to expire. * @param[in] expirationMode Select mode of expirationTime. See \ref * RAIL_TimeMode_t. * @param[in] callback A function to call on timer expiry. See \ref * RAIL_MultiTimerCallback_t. NULL is a legal value. * @param[in] cbArg An extra callback function parameter for the user application. * * @return * \ref RAIL_STATUS_NO_ERROR on success.@n * \ref RAIL_STATUS_INVALID_PARAMETER if tmr has an illegal value or if * timeout is in the past. */ RAIL_Status_t RAIL_SetMultiTimer(RAIL_MultiTimer_t *tmr, RAIL_Time_t expirationTime, RAIL_TimeMode_t expirationMode, RAIL_MultiTimerCallback_t callback, void *cbArg); /** * Stops the currently scheduled RAIL multi timer. * * @param[in,out] tmr A RAIL timer instance handle. * * @return * true if the timer was successfully canceled. * false if the timer was not running. * * Cancels the timer. If this function is called before the timer expires, * the cb callback specified in the earlier RAIL_SetTimer() call will never * be called. */ bool RAIL_CancelMultiTimer(RAIL_MultiTimer_t *tmr); /** * Checks if a given timer is running. * * @param[in] tmr A pointer to the timer structure to query. * * @return * true if the timer is running. * false if the timer is not running. */ bool RAIL_IsMultiTimerRunning(RAIL_MultiTimer_t *tmr); /** * Checks if a given timer has expired. * * @param[in] tmr A pointer to the timer structure to query. * * @return * true if the timer is expired. * false if the timer is running. */ bool RAIL_IsMultiTimerExpired(RAIL_MultiTimer_t *tmr); /** * Gets time left before a given timer instance expires. * * @param[in] tmr A pointer to the timer structure to query. * @param[in] timeMode Indicates how the function provides the time * remaining. By choosing \ref * RAIL_TimeMode_t::RAIL_TIME_ABSOLUTE, the function returns the * absolute expiration time, and by choosing \ref * RAIL_TimeMode_t::RAIL_TIME_DELAY, the function returns the * amount of time remaining before the timer's expiration. * * @return * Time left expressed in RAIL's time units. * 0 if the soft timer is not running or has already expired. */ RAIL_Time_t RAIL_GetMultiTimer(RAIL_MultiTimer_t *tmr, RAIL_TimeMode_t timeMode); /** * Initializes RAIL timer synchronization. * * @param[in] railHandle A RAIL instance handle. * @param[in] sleepConfig A sleep configuration. * * @return Status code indicating success of the function call. */ RAIL_Status_t RAIL_ConfigSleep(RAIL_Handle_t railHandle, RAIL_SleepConfig_t sleepConfig); /** * Stops the RAIL timer and prepares RAIL for sleep. * * @param[in] wakeupProcessTime Time in microseconds that the application and * hardware need to recover from sleep state. * @param[out] deepSleepAllowed * true - system can go to deep sleep. * false - system should not go to deep sleep. Deep sleep should be blocked * in this case. * * @return Status code indicating success of the function call. * * @warning The active RAIL configuration must be idle to enable sleep. */ RAIL_Status_t RAIL_Sleep(uint16_t wakeupProcessTime, bool *deepSleepAllowed); /** * Wakes RAIL from sleep and restarts the RAIL timer. * * @param[in] elapsedTime Add the sleep duration to the RAIL timer * before restarting the RAIL timer. * * @return Status code indicating success of the function call. * * If the timer sync was enabled by \ref RAIL_ConfigSleep, synchronize the RAIL * timer using an alternate timer. Otherwise, add elapsedTime to the RAIL * timer. */ RAIL_Status_t RAIL_Wake(RAIL_Time_t elapsedTime); /** @} */ // end of group System_Timing /****************************************************************************** * Events *****************************************************************************/ /** * @addtogroup Events * @brief APIs related to events * @{ */ /** * Configures radio events. * * @param[in] railHandle A RAIL instance handle. * @param[in] mask A bitmask of events to configure. * @param[in] events A bitmask of events to trigger \ref RAIL_Config_t::eventsCallback * For a full list of available callbacks, see * RAIL_EVENT_* set of defines. * @return Status code indicating success of the function call. * * Sets up which radio interrupts generate a RAIL event. The full list of * options is in \ref RAIL_Events_t. */ RAIL_Status_t RAIL_ConfigEvents(RAIL_Handle_t railHandle, RAIL_Events_t mask, RAIL_Events_t events); /** @} */ // end of group Events /****************************************************************************** * Data Management *****************************************************************************/ /// @addtogroup Data_Management Data Management /// @brief Data management functions /// /// These functions allow the application to choose how data is presented to /// the application. RAIL provides data in a packet-based method or in a /// FIFO-based method. As originally conceived, /// \ref RAIL_DataMethod_t::PACKET_MODE was designed for handling packets /// that fit within RAIL's FIFOs while \ref RAIL_DataMethod_t::FIFO_MODE /// was designed for handling packets larger than RAIL's FIFOs could hold. /// Conceptually it is still useful to think of these modes this way, but /// functionally their disinction has become blurred by improvements in /// RAIL's flexibility -- applications now have much more control over both /// receive and transmit FIFO sizes, and the FIFO-management and threshold /// APIs and related events are no longer restricted to \ref /// RAIL_DataMethod_t::FIFO_MODE operation but can be used in \ref /// RAIL_DataMethod_t::PACKET_MODE too. /// /// The application can configure RAIL data management through /// RAIL_ConfigData(). This function allows the application to specify the type /// of radio data (\ref RAIL_TxDataSource_t and \ref RAIL_RxDataSource_t) and /// the method of interacting with data (\ref RAIL_DataMethod_t). By default, /// RAIL configures TX and RX both with packet data source and \ref /// RAIL_DataMethod_t::PACKET_MODE. /// /// For transmit, \ref RAIL_DataMethod_t::PACKET_MODE and \ref /// RAIL_DataMethod_t::FIFO_MODE are functionally the same: /// - When not actively transmitting, load a packet's initial transmit /// data using RAIL_WriteTxFifo() with reset set to true. Alternatively /// this data copying can be avoided by changing the transmit FIFO to an /// already-loaded section of memory with \ref RAIL_SetTxFifo(). /// - When actively transmitting, load remaining transmit data with /// RAIL_WriteTxFifo() with reset set to false. /// - If transmit packets exceed the FIFO size, set the transmit FIFO /// threshold through RAIL_SetTxFifoThreshold(). The \ref /// RAIL_Config_t::eventsCallback with \ref RAIL_EVENT_TX_FIFO_ALMOST_EMPTY /// will occur telling the application to load more TX packet data, if /// needed, to prevent a \ref RAIL_EVENT_TX_UNDERFLOW event from occurring. /// One can get how much space is available in the transmit FIFO for more /// transmit data through RAIL_GetTxFifoSpaceAvailable(). /// - After transmit completes, the transmit FIFO can be manually reset /// with RAIL_ResetFifo(), but this should rarely be necessary. /// /// The transmit FIFO is specified by the application and its size is /// the value returned from the most recent call to RAIL_SetTxFifo(). /// The transmit FIFO is edge-based in that it only provides the \ref /// RAIL_EVENT_TX_FIFO_ALMOST_EMPTY event once when the threshold is crossed /// in the emptying direction. /// /// For receive, the distinction between \ref RAIL_DataMethod_t::PACKET_MODE /// and \ref RAIL_DataMethod_t::FIFO_MODE basically boils down to how /// unsuccessfully-received packets are handled. In \ref /// RAIL_DataMethod_t::PACKET_MODE, data from such packets is automatically /// rolled back as if the packet was never received, while in \ref /// RAIL_DataMethod_t::FIFO_MODE, rollback does not occur putting more onus /// on the application to deal with that data. /// /// In receive \ref RAIL_DataMethod_t::PACKET_MODE data management: /// - Packet lengths are determined from the Radio Configurator configuration /// and can be read out at the end using \ref RAIL_GetRxPacketInfo(). /// - Received packet data is made available on successful packet completion /// via \ref RAIL_Config_t::eventsCallback with \ref /// RAIL_EVENT_RX_PACKET_RECEIVED which can then use RAIL_GetRxPacketInfo() /// and RAIL_GetRxPacketDetailsAlt() to access packet information and /// RAIL_PeekRxPacket() to access packet data. /// - Filtered, Aborted, or FrameError received packet data is automatically /// rolled back (dropped) without the application needing to worry about /// consuming it. /// The application can choose to not even be bothered with the events /// related to such packets: \ref RAIL_EVENT_RX_ADDRESS_FILTERED, /// \ref RAIL_EVENT_RX_PACKET_ABORTED, or \ref RAIL_EVENT_RX_FRAME_ERROR. /// /// In receive \ref RAIL_DataMethod_t::FIFO_MODE data management: /// - Packet Lengths are determined from the Radio Configurator configuration /// or by application knowledge of packet payload structure. /// - Received data can be retrieved prior to packet completion through /// RAIL_ReadRxFifo() and is never rolled back on Filtered, Aborted, or /// FrameError packets. The application should enable and handle these /// events so it can flush any packet data it's already retrieved. /// - After packet completion, remaining packet data for Filtered, Aborted, /// or FrameError packets remains in the FIFO and the appropriate event is /// triggered to the user. This data may be consumed in the callback unlike /// in packet mode where it is automatically rolled back. At the end of the /// callback all remaining data in the FIFO will be cleaned up as usual. /// Keep in mind that RAIL_GetRxPacketDetailsAlt() provides packet detailed /// information only for successfully received packets. /// /// Common receive data management features: /// - Set the receive FIFO threshold through RAIL_SetRxFifoThreshold(). The /// \ref RAIL_Config_t::eventsCallback with \ref RAIL_EVENT_RX_FIFO_ALMOST_FULL /// will occur telling the application to consume some RX packet data to /// prevent a \ref RAIL_EVENT_RX_FIFO_OVERFLOW event from occurring. /// - Get receive FIFO count information through /// RAIL_GetRxPacketInfo(\ref RAIL_RX_PACKET_HANDLE_NEWEST) /// (or RAIL_GetRxFifoBytesAvailable()). /// - After receive completes and all its data has been consumed, the receive /// FIFO can be manually reset with RAIL_ResetFifo(), though this should /// rarely be necessary and should only be done with the radio idle. /// /// When trying to determine an appropriate threshold, the application needs /// to know the size of each FIFO. The default receive FIFO is internal to RAIL /// with a size of 512 bytes. This can be changed, however, using the /// \ref RAIL_SetRxFifo API and the default may be removed entirely by doing /// this in the RAILCb_SetupRxFifo() callback. The receive FIFO event is /// level-based in that the \ref RAIL_EVENT_RX_FIFO_ALMOST_FULL event will /// constantly pend if the threshold is exceeded. This normally means that /// inside this event's callback, the application should empty enough of the FIFO /// to go under the threshold. To defer reading the FIFO to main context, the /// application can disable or re-enable the receive FIFO threshold event using /// RAIL_ConfigEvents() with the mask \ref RAIL_EVENT_RX_FIFO_ALMOST_FULL. /// /// The receive FIFO can store multiple packets and processing of a packet can /// be held off deferred from the RAIL event callback to main loop processing. /// Before a packet is done being received you can always use /// RAIL_PeekRxPacket() to peek at the contents. In FIFO mode, you may also /// consume the data with RAIL_ReadRxPacket(). Remember that none of these APIs /// will read across a packet boundary (even in FIFO mode) so you will need to /// handle each received packet individually. To defer this processing until the /// main loop you must use RAIL_HoldRxPacket() when the completion event occurs /// to prevent us from automatically clearing the data from the FIFO. /// /// While RAIL defaults to \ref RAIL_DataMethod_t::PACKET_MODE, the /// application can explicitly initialize RAIL for \ref /// RAIL_DataMethod_t::PACKET_MODE in the following manner: /// @code{.c} /// extern RAIL_Handle_t railHandle; /// static const RAIL_DataConfig_t railDataConfig = { /// .txSource = TX_PACKET_DATA, /// .rxSource = RX_PACKET_DATA, /// .txMethod = PACKET_MODE, /// .rxMethod = PACKET_MODE, /// }; /// /// status = RAIL_ConfigData(railHandle, &railDataConfig); /// /// // Events that can occur in Packet Mode: /// // RAIL_EVENT_TX_PACKET_SENT /// // RAIL_EVENT_RX_PACKET_RECEIVED /// // and optionally (packet data automatically dropped): /// // RAIL_EVENT_RX_ADDRESS_FILTERED /// // RAIL_EVENT_RX_PACKET_ABORTED /// // RAIL_EVENT_RX_FRAME_ERROR /// // and if enabled: /// // RAIL_EVENT_TX_UNDERFLOW /// // RAIL_EVENT_TXACK_UNDERFLOW /// // RAIL_EVENT_TX_FIFO_ALMOST_EMPTY /// // RAIL_EVENT_RX_FIFO_ALMOST_FULL /// @endcode /// /// Initializing RAIL for \ref RAIL_DataMethod_t::FIFO_MODE requires a few /// more function calls: /// @code{.c} /// extern RAIL_Handle_t railHandle; /// static const RAIL_DataConfig_t railDataConfig = { /// .txSource = TX_PACKET_DATA, /// .rxSource = RX_PACKET_DATA, /// .txMethod = FIFO_MODE, /// .rxMethod = FIFO_MODE, /// }; /// /// status = RAIL_ConfigData(railHandle, &railDataConfig); /// /// // Gets the size of the FIFOs. /// // Assume that the transmit and receive FIFOs are the same size /// uint16_t fifoSize = RAIL_GetTxFifoSpaceAvailable(railHandle); /// /// // Sets the transmit and receive FIFO thresholds. /// // For this example, set the threshold in the middle of each FIFO. /// RAIL_SetRxFifoThreshold(railHandle, fifoSize / 2); /// RAIL_SetTxFifoThreshold(railHandle, fifoSize / 2); /// /// // Events that can occur in FIFO mode: /// // RAIL_EVENT_TX_FIFO_ALMOST_EMPTY /// // RAIL_EVENT_TX_UNDERFLOW /// // RAIL_EVENT_TXACK_UNDERFLOW /// // RAIL_EVENT_TX_PACKET_SENT /// // RAIL_EVENT_RX_FIFO_ALMOST_FULL /// // RAIL_EVENT_RX_FIFO_OVERFLOW /// // RAIL_EVENT_RX_ADDRESS_FILTERED /// // RAIL_EVENT_RX_PACKET_ABORTED /// // RAIL_EVENT_RX_FRAME_ERROR /// // RAIL_EVENT_RX_PACKET_RECEIVED /// @endcode /// /// On receive, an application can use multiple data sources that /// are only compatible with \ref RAIL_DataMethod_t::FIFO_MODE. All that differs /// from the FIFO mode example above is the RAIL_DataConfig_t::rxSource setting. /// IQ data samples are taken at the hardware's oversample rate and the amount /// of data can easily overwhelm the CPU processing time. The sample rate /// depends on the chosen PHY, as determined by the data rate and the decimation /// chain. It is <b>not</b> recommended to use the IQ data source with sample /// rates above 300 k samples/second as the CPU might not be able to keep up /// with the data. Depending on the application and needed CPU bandwidth, slower /// data rates may be required. /// @code{.c} /// // IQ data is provided into the receive FIFO. /// static const RAIL_DataConfig_t railDataConfig = { /// .txSource = TX_PACKET_DATA, /// .rxSource = RX_IQDATA_FILTLSB, /// .txMethod = FIFO_MODE, /// .rxMethod = FIFO_MODE, /// }; /// /// // IQ data comes in the following format when reading out of the FIFO: /// //------------------------------------ /// // I[LSB] | I[MSB] | Q[LSB] | Q[MSB] | /// //------------------------------------ /// @endcode /// /// @{ /** * RAIL data management configuration * * @param[in] railHandle A RAIL instance handle. * @param[in] dataConfig RAIL data configuration structure. * @return Status code indicating success of the function call. * * This function configures how RAIL manages data. The application can * configure RAIL to receive data in a packet-based or FIFO-based manner. * \ref RAIL_DataMethod_t::FIFO_MODE is necessary to receive packets larger * than the radio's receive FIFO. * * Generally with \ref RAIL_DataMethod_t::FIFO_MODE, the application sets * appropriate FIFO thresholds via RAIL_SetTxFifoThreshold() and * RAIL_SetRxFifoThreshold() and then enables and handles the * \ref RAIL_EVENT_TX_FIFO_ALMOST_EMPTY event callback (to feed more packet * data via RAIL_WriteTxFifo() before the FIFO underflows) and the \ref * RAIL_EVENT_RX_FIFO_ALMOST_FULL event callback (to consume packet data * via RAIL_ReadRxFifo() before the RX FIFO overflows). * * When configuring TX for \ref RAIL_DataMethod_t::FIFO_MODE, this * function resets the transmit FIFO. When configuring TX or RX for * \ref RAIL_DataMethod_t::PACKET_MODE, this function will reset * the corresponding FIFO thresholds such that they won't trigger the * \ref RAIL_EVENT_RX_FIFO_ALMOST_FULL or \ref RAIL_EVENT_TX_FIFO_ALMOST_EMPTY * events. * * When \ref RAIL_DataConfig_t.rxMethod is set to \ref * RAIL_DataMethod_t.FIFO_MODE, the radio won't drop packet data of * aborted or CRC error packets, but will present it to the application * to deal with accordingly. On completion of erroneous packets, the * \ref RAIL_Config_t::eventsCallback with \ref RAIL_EVENT_RX_PACKET_ABORTED, * \ref RAIL_EVENT_RX_FRAME_ERROR, or \ref RAIL_EVENT_RX_ADDRESS_FILTERED will * tell the application it can drop any data it read via RAIL_ReadRxFifo() during reception. * For CRC error packets when the \ref RAIL_RX_OPTION_IGNORE_CRC_ERRORS * RX option is in effect, the application should check for that from the * \ref RAIL_RxPacketStatus_t obtained by calling RAIL_GetRxPacketInfo(). * RAIL will automatically flush any remaining packet data after reporting * one of these packet completion events or the application can explicitly * flush it by calling RAIL_ReleaseRxPacket(). * * When \ref RAIL_DataConfig_t.rxMethod is set to \ref * RAIL_DataMethod_t.PACKET_MODE, the radio will roll back (drop) all packet * data associated with aborted packets including those with CRC errors * (unless configured to ignore CRC errors via the * \ref RAIL_RX_OPTION_IGNORE_CRC_ERRORS RX option). The application will * never have to deal with packet data from these packets. * * In either mode, the application can set RX options as needed. */ RAIL_Status_t RAIL_ConfigData(RAIL_Handle_t railHandle, const RAIL_DataConfig_t *dataConfig); /** * Writes data to the transmit FIFO. * * @param[in] railHandle A RAIL instance handle. * @param[in] dataPtr An application-provided pointer to transmit data. * @param[in] writeLength A number of bytes to write to the transmit FIFO. * @param[in] reset If true, resets transmit FIFO before writing the data. * @return The number of bytes written to the transmit FIFO. * * This function reads data from the provided dataPtr and writes it to the transmit * FIFO. If the requested writeLength exceeds the current number of bytes open * in the transmit FIFO, the function only writes until the transmit FIFO * is full. The function returns the number of bytes written to the transmit * FIFO or returns zero if railHandle is NULL or if the transmit FIFO is full. * * @note The protocol's packet configuration, as set up by the radio * configurator or via RAIL_SetFixedLength(), determines how many * bytes of data are consumed from the transmit FIFO for a successful transmit * operation, not the writeLength value passed in. If not enough data has * been put into the transmit FIFO, a \ref RAIL_EVENT_TX_UNDERFLOW event will * occur. If too much data is put into the transmit FIFO, the extra data will * either become the first bytes * sent in a subsequent packet, or will be thrown away if the FIFO gets * reset prior to the next transmit. In general, the proper number of * packet bytes to put into the transmit FIFO are all payload bytes except * for any CRC bytes, which the packet configuration causes to be sent * automatically. * * @note This function does not create a critical section but, depending on the * application, a critical section could be appropriate. */ uint16_t RAIL_WriteTxFifo(RAIL_Handle_t railHandle, const uint8_t *dataPtr, uint16_t writeLength, bool reset); /** * Sets the address of the transmit FIFO, a circular buffer used for TX data. * * @param[in] railHandle A RAIL instance handle. * @param[in,out] addr A pointer to a read-write memory location in RAM * used as the transmit FIFO. This memory must persist until the next call to * this function. * @param[in] initLength A number of initial bytes already in the transmit FIFO. * @param[in] size A desired size of the transmit FIFO in bytes. * @return Returns the FIFO size in bytes. * * This function sets the memory location for the transmit FIFO. It * must be called at least once before any transmit operations occur. * * The FIFO size can be determined by the return value of this function. The * chosen size is determined based on the available FIFO sizes supported by * the hardware. For more on supported FIFO sizes and alignments, see * chip-specific documentation, such as \ref efr32_main. The returned FIFO size * will be the closest allowed size less than or equal to the passed in size * parameter, unless the size parameter is smaller than the minimum FIFO size. * If the initLength parameter is larger than the returned size, the FIFO will * be filled up to its size. * * A user may write to the custom memory location directly before calling this * function, or use \ref RAIL_WriteTxFifo to write to the memory location after * calling this function. Users must specify the initLength * for previously-written memory to be set in the transmit * FIFO. * * This function reserves the block of RAM starting at addr with a length of the * returned FIFO size, which is used internally as a circular buffer for the * transmit FIFO. It must be able to hold the entire FIFO size. The caller must * guarantee that the custom FIFO remains intact and unchanged (except via calls * to \ref RAIL_WriteTxFifo) until the next call to this function. * * @note The protocol's packet configuration, as set up by the radio * configurator or via RAIL_SetFixedLength(), determines how many * bytes of data are consumed from the transmit FIFO for a successful transmit * operation, not the initLength value passed in. If not enough data has * been put into the transmit FIFO, a \ref RAIL_EVENT_TX_UNDERFLOW event will * occur. If too much data is put into the transmit FIFO, the extra data * will either become the first bytes * sent in a subsequent packet, or will be thrown away if the FIFO gets * reset prior to the next transmit. In general, the proper number of * packet bytes to put into the transmit FIFO are all payload bytes except * for any CRC bytes which the packet configuration causes to be sent * automatically. */ uint16_t RAIL_SetTxFifo(RAIL_Handle_t railHandle, uint8_t *addr, uint16_t initLength, uint16_t size); /** * Sets the address of the receive FIFO, a circular buffer used for RX data. * * @param[in] railHandle A RAIL instance handle. * @param[in,out] addr A pointer to a read-write memory location in RAM used as * the receive FIFO. This memory must persist until the next call to this * function. * @param[in,out] size A desired size of the receive FIFO in bytes. This will * be populated with the actual size during the function call. * @return Status code indicating success of the function call. * * This function sets the memory location for the receive FIFO. It * must be called at least once before any receive operations occur. * * The FIFO size can be determined by the value of size after this function. The * chosen size is determined based on the available FIFO sizes supported by * the hardware. For more on supported FIFO sizes and required alignments, see * chip-specific documentation, such as \ref efr32_main. The returned FIFO size * will be the closest allowed size less than or equal to the passed in size * parameter, unless the size parameter is smaller than the minimum FIFO size. * * This function reserves the block of RAM starting at addr with a length * of size, which is used internally as a circular buffer for the receive FIFO. * It must be able to hold the entire FIFO size. The caller must guarantee that * the custom FIFO remains intact and unchanged (except via incoming packet data * being written) until the next call to this function. * * In multiprotocol, RAIL currently shares one receive FIFO across all * protocols. This function will return \ref RAIL_STATUS_INVALID_STATE if the * requested \ref RAIL_Handle_t is not active. */ RAIL_Status_t RAIL_SetRxFifo(RAIL_Handle_t railHandle, uint8_t *addr, uint16_t *size); /// Sets up the receive FIFO to use. This function is optional to implement. /// /// @param[in] railHandle A RAIL instance handle. /// @return Status code indicating success of the function call. /// /// This function is called during the \ref RAIL_Init process to set up the FIFO /// to use for received packets. If not implemented by the application, /// a default implementation from within the RAIL library will be used to /// initialize a 512-byte receive FIFO. /// /// If this function returns an error, then the RAIL_Init process will fail. /// /// During this function, the application should generally call /// \ref RAIL_SetRxFifo. If that does not happen, then the application needs to /// set up the receive FIFO via a call to \ref RAIL_SetRxFifo before attempting /// to receive any packets. An example implementation may look like the following: /// @code{.c} /// #define RX_FIFO_SIZE 1024 /// static uint8_t rxFifo[RX_FIFO_SIZE]; /// /// RAIL_Status_t RAILCb_SetupRxFifo(RAIL_Handle_t railHandle) /// { /// uint16_t rxFifoSize = RX_FIFO_SIZE; /// RAIL_Status_t status = RAIL_SetRxFifo(railHandle, &rxFifo[0], &rxFifoSize); /// if (rxFifoSize != RX_FIFO_SIZE) { /// // We set up an incorrect FIFO size /// return RAIL_STATUS_INVALID_PARAMETER; /// } /// if (status == RAIL_STATUS_INVALID_STATE) { /// // Allow failures due to multiprotocol /// return RAIL_STATUS_NO_ERROR; /// } /// return status; /// } /// @endcode RAIL_Status_t RAILCb_SetupRxFifo(RAIL_Handle_t railHandle); /** * Reads packet data from RAIL's internal receive FIFO. * * @param[in] railHandle A RAIL instance handle. * @param[out] dataPtr An application-provided pointer to store data. * If NULL, the data is thrown away rather than copied out. * @param[in] readLength A number of packet bytes to read from the FIFO. * @return The number of packet bytes read from the receive FIFO. * * This function reads packet data from the head of receive FIFO and * writes it to the provided dataPtr. It does not permit reading more * data than is available in the FIFO, nor does it permit reading more * data than remains in the oldest unreleased packet. * * Because this function does not have a critical section, use it * only in one context or make sure function calls are protected to prevent * buffer corruption. * * @warning This function is intended for use only with \ref * RAIL_DataMethod_t::FIFO_MODE and should never be called in \ref * RAIL_DataMethod_t::PACKET_MODE where it could lead to receive FIFO * corruption. * * @note When reading data from an arriving packet that is not yet complete, * keep in mind its data is highly suspect because it has not yet passed * any CRC integrity checking. Also note that the packet could be aborted, * canceled, or fail momentarily, invalidating its data in Packet mode. * Furthermore, there is a small chance towards the end of packet reception * that the receive FIFO could include not only packet data received so far, * but also some raw radio-appended info detail bytes that RAIL's * packet-completion processing will subsequently deal with. It's up to the * application to know its packet format well enough to avoid reading this * info as it will corrupt the packet's details and possibly corrupt the * receive FIFO. */ uint16_t RAIL_ReadRxFifo(RAIL_Handle_t railHandle, uint8_t *dataPtr, uint16_t readLength); /** * Configures the RAIL transmit FIFO almost empty threshold. * * @param[in] railHandle A RAIL instance handle. * @param[in] txThreshold The threshold below which the * \ref RAIL_EVENT_TX_FIFO_ALMOST_EMPTY event will fire. * @return Configured transmit FIFO threshold value. * * This function configures the threshold for the transmit FIFO. When the * number of bytes in the transmit FIFO falls below the configured threshold, * \ref RAIL_Config_t::eventsCallback will fire with \ref * RAIL_EVENT_TX_FIFO_ALMOST_EMPTY set. * The txThreshold value should be smaller than or equal to the transmit * FIFO size; higher values will be pegged to the FIFO size. * A value of 0 or \ref RAIL_FIFO_THRESHOLD_DISABLED will disable the * threshold, returning \ref RAIL_FIFO_THRESHOLD_DISABLED. */ uint16_t RAIL_SetTxFifoThreshold(RAIL_Handle_t railHandle, uint16_t txThreshold); /** * Configures the RAIL receive FIFO almost full threshold. * * @param[in] railHandle A RAIL instance handle. * @param[in] rxThreshold The threshold above which the * \ref RAIL_EVENT_RX_FIFO_ALMOST_FULL event will fire. * @return Configured receive FIFO threshold value. * * This function configures the threshold for the receive FIFO. When the * number of bytes of packet data in the receive FIFO exceeds the configured * threshold, \ref RAIL_Config_t::eventsCallback will fire with \ref * RAIL_EVENT_RX_FIFO_ALMOST_FULL set. * The rxThreshold value should be smaller than the receive FIFO size; * anything else, including a * value of \ref RAIL_FIFO_THRESHOLD_DISABLED, will disable the threshold, * returning \ref RAIL_FIFO_THRESHOLD_DISABLED. */ uint16_t RAIL_SetRxFifoThreshold(RAIL_Handle_t railHandle, uint16_t rxThreshold); /** * Gets the RAIL transmit FIFO almost empty threshold value. * * @param[in] railHandle A RAIL instance handle. * @return Configured TX Threshold value. * * Retrieves the configured TX threshold value. */ uint16_t RAIL_GetTxFifoThreshold(RAIL_Handle_t railHandle); /** * Gets the RAIL receive FIFO almost full threshold value. * * @param[in] railHandle A RAIL instance handle. * @return Configured RX Threshold value. * * Retrieves the configured RX threshold value. */ uint16_t RAIL_GetRxFifoThreshold(RAIL_Handle_t railHandle); /** * Resets the RAIL transmit and/or receive FIFOs. * * @param[in] railHandle A RAIL instance handle. * @param[in] txFifo If true, reset the transmit FIFO. * @param[in] rxFifo If true, reset the receive FIFO. * @return void. * * This function can reset each FIFO independently. * The application should not reset the receive FIFO while receiving a frame, * nor should it reset the transmit FIFO while transmitting a frame. */ void RAIL_ResetFifo(RAIL_Handle_t railHandle, bool txFifo, bool rxFifo); /** * Gets the number of bytes used in the receive FIFO. * This function should only be used in RX \ref RAIL_DataMethod_t::FIFO_MODE. * Apps should use RAIL_GetRxPacketInfo() instead. * * @param[in] railHandle A RAIL instance handle. * @return Number of bytes used in the receive FIFO. * * This tells how much packet-related data exists in the receive FIFO * that could be read. * * @note The number of bytes returned may not just reflect the current * packet's data but could also include raw appended info bytes added * after successful packet reception and bytes from subsequently received * packets. It is up to the app to never try to consume more than the * packet's actual data when using the value returned here in a subsequent * call to RAIL_ReadRxFifo(), otherwise the RX FIFO will be corrupted. */ uint16_t RAIL_GetRxFifoBytesAvailable(RAIL_Handle_t railHandle); /** * Gets the number of bytes unused in the transmit FIFO. * * @param[in] railHandle A RAIL instance handle. * @return Number of bytes unused in the transmit FIFO. * * This tells how much space is available in the transmit FIFO for writing * additional packet data. */ uint16_t RAIL_GetTxFifoSpaceAvailable(RAIL_Handle_t railHandle); /** @} */ // end of group Data_Management /****************************************************************************** * State Transitions *****************************************************************************/ /** * @addtogroup State_Transitions State Transitions * @{ */ /** * Configures RAIL automatic state transitions after RX. * * @param[in] railHandle A RAIL instance handle. * @param[in] transitions The state transitions to apply after reception. * @return Status code indicating success of the function call. * * This function fails if unsupported transitions are passed in or if the * radio is currently in the RX state. Success can transition to TX, RX, or * IDLE, while error can transition to RX or IDLE. */ RAIL_Status_t RAIL_SetRxTransitions(RAIL_Handle_t railHandle, const RAIL_StateTransitions_t *transitions); /** * Configures RAIL automatic state transitions after TX. * * @param[in] railHandle A RAIL instance handle. * @param[in] transitions The state transitions to apply after transmission. * @return Status code indicating a success of the function call. * * This function fails if unsupported transitions are passed in or if the * radio is currently in the TX state. Success and error can each transition * to RX or IDLE. */ RAIL_Status_t RAIL_SetTxTransitions(RAIL_Handle_t railHandle, const RAIL_StateTransitions_t *transitions); /** * Configures RAIL automatic state transition timing. * * @param[in] railHandle A RAIL instance handle. * @param[in,out] timings The timings used to configure the RAIL state * machine. This structure is overwritten with the actual times that were * set, if an input timing is invalid. * @return Status code indicating a success of the function call. * * The timings given are close to the actual transition time. However, * a still uncharacterized software overhead occurs. Also, timings are not * always adhered to when using an automatic transition after an error, due to * the cleanup required to recover from the error. */ RAIL_Status_t RAIL_SetStateTiming(RAIL_Handle_t railHandle, RAIL_StateTiming_t *timings); /** * Places the radio into an idle state. * * @param[in] railHandle A RAIL instance handle. * @param[in] mode The method for shutting down the radio. * @param[in] wait Whether this function should wait for the radio to reach * idle before returning. * @return void. * * This function is used to remove the radio from TX and RX states. How these * states are left is defined by the mode parameter. * * In multiprotocol, this API will also cause the radio to be yielded so that * other tasks can be run. See \ref rail_radio_scheduler_yield for more details. */ void RAIL_Idle(RAIL_Handle_t railHandle, RAIL_IdleMode_t mode, bool wait); /** * Gets the current radio state. * * @param[in] railHandle A RAIL instance handle. * @return An enumeration for the current radio state. * * Returns the state of the radio as a bitmask containing: * \ref RAIL_RF_STATE_IDLE, \ref RAIL_RF_STATE_RX, \ref RAIL_RF_STATE_TX, * and \ref RAIL_RF_STATE_ACTIVE. \ref RAIL_RF_STATE_IDLE, \ref * RAIL_RF_STATE_RX, and \ref RAIL_RF_STATE_TX bits are mutually exclusive. * The radio can transition through intermediate states, * which are not reported but are instead considered part of the state * most closely associated. For example, when the radio is warming up * or shutting down the transmitter or receiver, this function returns * \ref RAIL_RF_STATE_TX or \ref RAIL_RF_STATE_RX, respectively. * When transitioning directly from Rx to Tx or vice-versa, this function * returns the earlier state. */ RAIL_RadioState_t RAIL_GetRadioState(RAIL_Handle_t railHandle); /** @} */ // end of group State_Transitions /****************************************************************************** * Transmit *****************************************************************************/ /** * @addtogroup Transmit * @brief APIs related to transmitting data packets * @{ */ /// @addtogroup PA Power Amplifier (PA) /// @brief APIs for interacting with one of the on chip PAs. /// /// These APIs let you configure the on-chip PA to get the appropriate output /// power. /// /// These are the function types: /// 1) Configuration functions: These functions set and get configuration /// for the PA. In this case, "configuration" refers to a) indicating /// which PA to use, b) the voltage supplied by your board to the PA, /// and c) the ramp time over which to ramp the PA up to its full /// power. /// 2) Power-setting functions: These functions consume the actual /// values written to the PA registers and write them appropriately. /// These values are referred to as "(raw) power levels". The range of /// acceptable values for these functions depends on which PA is /// currently active. The higher the power level set, the higher /// the dBm power output by the chip. However, the mapping /// between dBm and these power levels can vary greatly between /// modules/boards. /// 3) Conversion functions: These functions convert /// between the "power levels" discussed previously and the /// dBm values output by the chip. Continue reading for more information /// about unit conversion. /// /// The accuracy of the chip output power is application-specific. /// For some protocols or channels, the protocol itself or /// legal limitations require applications to know exactly what power /// they're transmitting at, in dBm. Other applications do not have /// these restrictions, and users determine power level(s) /// that fit their criteria for the trade-off between radio range and /// power savings, regardless of what dBm power that maps to. /// /// \ref RAIL_ConvertRawToDbm and \ref RAIL_ConvertDbmToRaw, /// which convert between the dBm power and the raw power levels, /// provide a solution that fits all these applications. /// The levels of customizability are outlined below: /// 1) No customizability needed: for a given dBm value, the result /// of RAIL_ConvertDbmToRaw provides an appropriate /// raw power level that, when written to the registers via /// RAIL_SetPowerLevel, causes the chip to output at that /// dBm power. In this case, no action is needed by the user, /// the WEAK versions of the conversion functions can be used /// and the default include paths in pa_conversions_efr32.h can /// be used. /// 2) The mapping of power level to dBm is not good, but the /// level of precision is sufficient: In pa_conversions_efr32.c, /// the WEAK versions of the conversion functions work by using /// 8-segment piecewise linear curves to convert between dBm /// and power levels for PA's with hundreds of power levels /// and simple mapping tables for use with PA's with only a few /// levels. If this method is sufficiently precise, but the mapping /// between power levels and dBm is incorrect, /// copy pa_curves_efr32.h into a new file, updating the segments /// to form a better fit (_DCDC_CURVES or _VBAT_CURVES defines) and /// then add the RAIL_PA_CURVES define to your build with the path /// to the new file. /// 3) A different level of precision is needed and the fit is bad: /// If the piecewise-linear line segment fit is not appropriate for /// your solution, the functions in pa_conversions_efr32.c can be /// totally rewritten, as long as RAIL_ConvertDbmToRaw and /// RAIL_ConvertRawToDbm have the same signatures. It is completely /// acceptable to re-write these in a way that makes the /// pa_curves_efr32.h and pa_curve_types_efr32.h files referenced in /// pa_conversions_efr32.h unnecessary. Those files are needed solely /// for the provided conversion methods. /// 4) dBm values are not necessary: If the application does not require /// dBm values at all, overwrite /// RAIL_ConvertDbmToRaw and RAIL_ConvertRawToDbm with smaller functions /// (i.e., return 0 or whatever was input). These functions are called /// from within the RAIL library, so they can never be deadstripped, /// but making them as small as possible is the best way to reduce code /// size. From there, call RAIL_SetTxPower, without /// converting from a dBm value. If you never want the library to coerce the /// power based on channels, RAIL_ConvertRawToDbm should be overwritten /// to always return 0 and RAIL_ConvertDbmToRaw should be overwritten to /// always return 255. /// /// The following is example code that shows how to initialize your PA /// @code{.c} /// /// #include "pa_conversions_efr32.h" /// /// // A helper macro to declare all the curve structures used by the provided /// // conversion functions. /// RAIL_DECLARE_TX_POWER_VBAT_CURVES(piecewiseSegments, curvesSg, curves24Hp, curves24Lp); /// /// // Puts the variables declared above into the appropriate structure. /// RAIL_TxPowerCurvesConfig_t txPowerCurvesConfig = { curves24Hp, curvesSg, curves24Lp, piecewiseSegments }; /// /// // Saves those curves /// // to be referenced when the conversion functions are called. /// RAIL_InitTxPowerCurves(&txPowerCurvesConfig); /// /// // Declares the structure used to configure the PA. /// RAIL_TxPowerConfig_t txPowerConfig = { RAIL_TX_POWER_MODE_2P4_HP, 3300, 10 }; /// /// // Initializes the PA. Here, it is assumed that 'railHandle' is a valid RAIL_Handle_t /// // that has already been initialized. /// RAIL_ConfigTxPower(railHandle, &txPowerConfig); /// /// // Picks a dBm power to use: 100 deci-dBm = 10 dBm. See docs on RAIL_TxPower_t. /// RAIL_TxPower_t power = 100; /// /// // Gets the config written by RAIL_ConfigTxPower to confirm what was actually set. /// RAIL_GetTxPowerConfig(railHandle, &txPowerConfig); /// /// // RAIL_ConvertDbmToRaw is the default weak version, /// // or the customer version, if overwritten. /// RAIL_TxPowerLevel_t powerLevel = RAIL_ConvertDbmToRaw(railHandle, /// txPowerConfig.mode, /// power); /// /// // Writes the result of the conversion to the PA power registers in terms /// // of raw power levels. /// RAIL_SetTxPower(railHandle, powerLevel); /// @endcode /// /// @note: All lines following "RAIL_TxPower_t power = 100;" can be /// replaced with the provided utility function, \ref RAIL_SetTxPowerDbm. /// However, the full example here was provided for clarity. See the /// documentation on \ref RAIL_SetTxPowerDbm for more details. /// /// @{ /** * Initializes TxPower Settings. * * @param[in] railHandle A RAIL instance handle. * @param[in] config An instance which contains desired initial settings * for the TX amplifier. * @return RAIL_Status_t indicating success or an error. * * These settings include the selection between the multiple TX amplifiers, * voltage supplied to the TX power amplifier, and ramp times. This must * be called before any transmit occurs, or \ref RAIL_SetTxPower is called. * While this function should always be called during initialization, * it can also be called any time if these settings need to change to adapt * to a different application/protocol. This API will also reset TX Power to * its minimum value, so \ref RAIL_SetTxPower must be called afterwards. * * At times, certain combinations of configurations cannot be achieved. * This API attempts to get as close as possible to the requested settings. The * following "RAIL_Get..." API can be used to determine what values were set. */ RAIL_Status_t RAIL_ConfigTxPower(RAIL_Handle_t railHandle, const RAIL_TxPowerConfig_t *config); /** * Gets the TX power settings currently used in the amplifier. * * @param[in] railHandle A RAIL instance handle. * @param[out] config A pointer to memory allocated to hold the current TxPower * configuration structure. A NULL config will produce undefined * behavior. * @return RAIL status variable indicating whether or not the get was * successful. * * Note that this API does not return the current TX power, which is separately * managed by the \ref RAIL_GetTxPower/\ref RAIL_SetTxPower APIs. This API * should be used to determine which values were set as a result of * \ref RAIL_ConfigTxPower. */ RAIL_Status_t RAIL_GetTxPowerConfig(RAIL_Handle_t railHandle, RAIL_TxPowerConfig_t *config); /** * Sets the TX power in units of raw units (see \ref rail_chip_specific.h for * value ranges). * * @param[in] railHandle A RAIL instance handle. * @param[in] powerLevel Power in chip-specific \ref RAIL_TxPowerLevel_t units. * @return RAIL_Status_t indicating success or an error. * * To convert between decibels and the integer values that the * registers take, call \ref RAIL_ConvertDbmToRaw. * A weak version of this function, which works well with our boards is provided. However, * customers using a custom board need to characterize * chip operation on that board and override the function to convert * appropriately from the desired dB values to raw integer values. * * Depending on the configuration used in \ref RAIL_ConfigTxPower, not all * power levels are achievable. This API will get as close as possible to * the desired power without exceeding it, and calling \ref RAIL_GetTxPower is * the only way to know the exact value written. * * Calling this function before configuring the PA (i.e., before a successful * call to \ref RAIL_ConfigTxPower) will return an error. */ RAIL_Status_t RAIL_SetTxPower(RAIL_Handle_t railHandle, RAIL_TxPowerLevel_t powerLevel); /** * Returns the current power setting of the PA. * * @param[in] railHandle A RAIL instance handle. * @return The chip-specific \ref RAIL_TxPowerLevel_t value of the current * transmit power. * * This API returns the raw value that was set by \ref RAIL_SetTxPower. * A weak version of \ref RAIL_ConvertRawToDbm that works * with our boards to convert the raw values into actual output dBm values is provided. * However, customers using a custom board need to * re-characterize the relationship between raw and decibel values and rewrite * the provided function. * * Calling this function before configuring the PA (i.e., before a successful * call to \ref RAIL_ConfigTxPower) will return an error * (RAIL_TX_POWER_LEVEL_INVALID). */ RAIL_TxPowerLevel_t RAIL_GetTxPower(RAIL_Handle_t railHandle); /** * Converts raw values written to registers to decibel value (in units of * deci-dBm). * * @param[in] railHandle A RAIL instance handle. * @param[in] mode PA mode for which to convert. * @param[in] powerLevel A raw amplifier register value to be converted to * deci-dBm. * @return raw amplifier values converted to units of deci-dBm. * * A weak version of this function is provided that is tuned * to provide accurate values for our boards. For a * custom board, the relationship between what is written to the TX amplifier * and the actual output power should be re-characterized and implemented in an * overriding version of \ref RAIL_ConvertRawToDbm. For minimum code size and * best speed, use only raw values with the TxPower API and override this * function with a smaller function. In the weak version provided with the RAIL * library, railHandle is only used to indicate to the user from where the * function was called, so it is OK to use either a real protocol handle, or one * of the chip-specific ones, such as \ref RAIL_EFR32_HANDLE. * * Although the definitions of this function may change, the signature * must be as declared here. */ RAIL_TxPower_t RAIL_ConvertRawToDbm(RAIL_Handle_t railHandle, RAIL_TxPowerMode_t mode, RAIL_TxPowerLevel_t powerLevel); /** * Converts the desired decibel value (in units of deci-dBm) * to raw integer values used by the TX amplifier registers. * * @param[in] railHandle A RAIL instance handle. * @param[in] mode PA mode for which to do the conversion. * @param[in] power Desired dBm values in units of deci-dBm. * @return deci-dBm value converted to a raw * integer value that can be used directly with \ref RAIL_SetTxPower. * * A weak version of this function is provided that is tuned * to provide accurate values for our boards. For a * custom board, the relationship between what is written to the TX amplifier * and the actual output power should be characterized and implemented in an * overriding version of \ref RAIL_ConvertDbmToRaw. For minimum code size and * best speed use only raw values with the TxPower API and override this * function with a smaller function. In the weak version provided with the RAIL * library, railHandle is only used to indicate to the user from where the * function was called, so it is OK to use either a real protocol handle, or one * of the chip-specific ones, such as \ref RAIL_EFR32_HANDLE. * * Although the definitions of this function may change, the signature * must be as declared here. * * @note This function is called from within the RAIL library for * comparison between channel limitations and current power. It will * throw an assert if you haven't called RAIL_InitTxPowerCurves * which initializes the mappings between raw power levels and * actual dBm powers. To avoid the assert, ensure that the * maxPower of all channel config entries is \ref RAIL_TX_POWER_MAX * or above, or override this function to always return 255. */ RAIL_TxPowerLevel_t RAIL_ConvertDbmToRaw(RAIL_Handle_t railHandle, RAIL_TxPowerMode_t mode, RAIL_TxPower_t power); struct RAIL_TxPowerCurvesConfigAlt; /// Verifies the TX Power Curves on modules /// /// @param[in] config TX Power Curves to use on this module /// /// This function only needs to be called when using a module, and has no /// effect otherwise. Transmit will not work before this function is called. void RAIL_VerifyTxPowerCurves(const struct RAIL_TxPowerCurvesConfigAlt *config); /// Sets the TX power in terms of deci-dBm instead of raw power level. /// /// @param[in] railHandle A RAIL instance handle. /// @param[in] power A desired deci-dBm power to be set. /// @return RAIL Status variable indicate whether setting the /// power was successful. /// /// This is a utility function for user convenience. Normally, to set TX /// power in dBm, the user would have to do the following: /// /// @code{.c} /// RAIL_TxPower_t power = 100; // 100 deci-dBm, 10 dBm /// RAIL_TxPowerConfig_t txPowerConfig; /// RAIL_GetTxPowerConfig(railHandle, &txPowerConfig); /// // RAIL_ConvertDbmToRaw will be the weak version provided by Silicon Labs /// // by default, or the customer version, if overwritten. /// RAIL_TxPowerLevel_t powerLevel = RAIL_ConvertDbmToRaw(railHandle, /// txPowerConfig.mode, /// power); /// RAIL_SetTxPower(railHandle, powerLevel); /// @endcode /// /// This function wraps all those calls in a single function with power passed in /// as a parameter. /// RAIL_Status_t RAIL_SetTxPowerDbm(RAIL_Handle_t railHandle, RAIL_TxPower_t power); /// Gets the TX power in terms of deci-dBm instead of raw power level. /// /// @param[in] railHandle A RAIL instance handle. /// @return The current output power in deci-dBm. /// /// This is a utility function for user convenience. Normally, to get TX /// power in dBm, the user would have to do the following: /// /// @code{.c} /// RAIL_TxPowerLevel_t powerLevel = RAIL_GetTxPower(railHandle); /// RAIL_TxPowerConfig_t txPowerConfig; /// RAIL_GetTxPowerConfig(railHandle, &txPowerConfig); /// // RAIL_ConvertRawToDbm will be the weak version provided by Silicon Labs /// // by default, or the customer version, if overwritten. /// RAIL_TxPower_t power = RAIL_ConvertRawToDbm(railHandle, /// txPowerConfig.mode, /// power); /// return power; /// @endcode /// /// This function wraps all those calls in a single function with power returned /// as the result. /// RAIL_TxPower_t RAIL_GetTxPowerDbm(RAIL_Handle_t railHandle); /** @} */ // end of group PA /** * Starts a non-blocking transmit. * * @param[in] railHandle A RAIL instance handle. * @param[in] channel Define the channel to transmit on. * @param[in] options TX options to be applied to this transmit only. * @param[in] schedulerInfo Information to allow the radio scheduler to place * this transmit appropriately. This is only used in multiprotocol version of * RAIL and may be set to NULL in all other versions. * @return Status code indicating success of the function call. If successfully * initiated, transmit completion or failure will be reported by a later * \ref RAIL_Config_t::eventsCallback with the appropriate \ref RAIL_Events_t. * * Will begin transmission of the payload previously loaded via * \ref RAIL_WriteTxFifo() immediately, or right after a packet currently being * received is completed. * * Returns an error if a previous transmit is still in progress. * If changing channels, any ongoing packet reception is aborted. * * In multiprotocol, ensure that the radio is properly yielded after this * operation completes. See \ref rail_radio_scheduler_yield for more details. */ RAIL_Status_t RAIL_StartTx(RAIL_Handle_t railHandle, uint16_t channel, RAIL_TxOptions_t options, const RAIL_SchedulerInfo_t *schedulerInfo); /** * Stops an active or pending transmit * * @param[in] railHandle A RAIL instance handle. * @param[in] mode Configure the types of transmits to stop. * @return \ref RAIL_STATUS_NO_ERROR if the transmit was successfully * canceled. * Returns \ref RAIL_STATUS_INVALID_STATE if the requested * transmit mode cannot be stopped. * * @note This function will stop an auto-ACK in active transmit. */ RAIL_Status_t RAIL_StopTx(RAIL_Handle_t railHandle, RAIL_StopMode_t mode); /** * Schedules sending a packet. * * @param[in] railHandle A RAIL instance handle. * @param[in] channel Define the channel to transmit on. * @param[in] options TX options to be applied to this transmit only. * @param[in] config A pointer to the \ref RAIL_ScheduleTxConfig_t * structure containing when the transmit should occur. * @param[in] schedulerInfo Information to allow the radio scheduler to place * this transmit appropriately. This is only used in multiprotocol version of * RAIL and may be set to NULL in all other versions. * @return Status code indicating success of the function call. If successfully * initiated, a transmit completion or failure will be reported by a later * \ref RAIL_Config_t::eventsCallback with the appropriate \ref RAIL_Events_t. * * Will begin transmission of the payload previously loaded via * \ref RAIL_WriteTxFifo() at the scheduled time. * The time (in microseconds) as well as whether that time is absolute or * relative, is specified using the \ref RAIL_ScheduleTxConfig_t structure. * Also specified in this structure is what to do if a scheduled transmit * fires in the midst of receiving a packet. * * Returns an error if a previous transmit is still in progress. * If changing channels, any ongoing packet reception is aborted. * * In multiprotocol, ensure that the radio is properly yielded after this * operation completes. See \ref rail_radio_scheduler_yield for more details. */ RAIL_Status_t RAIL_StartScheduledTx(RAIL_Handle_t railHandle, uint16_t channel, RAIL_TxOptions_t options, const RAIL_ScheduleTxConfig_t *config, const RAIL_SchedulerInfo_t *schedulerInfo); /** * Starts a non-blocking Transmit using CSMA. * * @param[in] railHandle A RAIL instance handle. * @param[in] channel Define the channel to transmit on. * @param[in] options TX options to be applied to this transmit only. * @param[in] csmaConfig A pointer to the RAIL_CsmaConfig_t structure * describing the CSMA parameters to use for this transmit. * @param[in] schedulerInfo Information to allow the radio scheduler to place * this transmit appropriately. This is only used in multiprotocol version of * RAIL and may be set to NULL in all other versions. * @return Status code indicating success of the function call. If successfully * initiated, a transmit completion or failure will be reported by a later * \ref RAIL_Config_t::eventsCallback with the appropriate \ref RAIL_Events_t. * * Performs the Carrier Sense Multiple Access (CSMA) algorithm and, if * the channel is deemed clear (RSSI below the specified threshold), it will * commence transmission of the payload previously loaded via * RAIL_WriteTxFifo(). * Packets can be received during CSMA backoff periods if receive is active * throughout the CSMA process. This will happen either by starting the CSMA * process while receive is already active, or if the csmaBackoff time in * the \ref RAIL_CsmaConfig_t is less than the idleToRx time (set by * RAIL_SetStateTiming()). If the csmaBackoff time is greater than the * idleToRx time, receive will only be active during CSMA's clear channel * assessments. * * If the CSMA algorithm deems the channel busy, the \ref RAIL_Config_t::eventsCallback * occurs with \ref RAIL_EVENT_TX_CHANNEL_BUSY, and the contents * of the transmit FIFO remain intact. * * Returns an error if a previous transmit is still in progress. * If changing channels, any ongoing packet reception is aborted. * * In multiprotocol, ensure that the radio is properly yielded after this * operation completes. See \ref rail_radio_scheduler_yield for more details. */ RAIL_Status_t RAIL_StartCcaCsmaTx(RAIL_Handle_t railHandle, uint16_t channel, RAIL_TxOptions_t options, const RAIL_CsmaConfig_t *csmaConfig, const RAIL_SchedulerInfo_t *schedulerInfo); /** * Starts a non-blocking Transmit using LBT. * * @param[in] railHandle A RAIL instance handle. * @param[in] channel Define the channel to transmit on. * @param[in] options TX options to be applied to this transmit only. * @param[in] lbtConfig A pointer to the RAIL_LbtConfig_t structure * describing the LBT parameters to use for this transmit. * @param[in] schedulerInfo Information to allow the radio scheduler to place * this transmit appropriately. This is only used in multiprotocol version of * RAIL and may be set to NULL in all other versions. * @return Status code indicating success of the function call. If successfully * initiated, a transmit completion or failure will be reported by a later * \ref RAIL_Config_t::eventsCallback with the appropriate \ref RAIL_Events_t. * * Performs the Listen Before Talk (LBT) algorithm and, if the channel * is deemed clear (RSSI below the specified threshold), it will commence * transmission of the payload previously loaded via RAIL_WriteTxFifo(). * Packets can be received during LBT backoff periods if receive is active * throughout the LBT process. This will happen either by starting the LBT * process while receive is already active, or if the lbtBackoff time in * the \ref RAIL_LbtConfig_t is less than the idleToRx time (set by * RAIL_SetStateTiming()). If the lbtBackoff time is greater than the * idleToRx time, receive will only be active during LBT's clear channel * assessments. * * If the LBT algorithm deems the channel busy, the \ref RAIL_Config_t::eventsCallback occurs with * \ref RAIL_EVENT_TX_CHANNEL_BUSY, and the contents * of the transmit FIFO remain intact. * * Returns an error if a previous transmit is still in progress. * If changing channels, any ongoing packet reception is aborted. * * In multiprotocol, ensure that the radio is properly yielded after this * operation completes. See \ref rail_radio_scheduler_yield for more details. */ RAIL_Status_t RAIL_StartCcaLbtTx(RAIL_Handle_t railHandle, uint16_t channel, RAIL_TxOptions_t options, const RAIL_LbtConfig_t *lbtConfig, const RAIL_SchedulerInfo_t *schedulerInfo); /** * Sets the CCA threshold in dBm. * * @param[in] railHandle A RAIL instance handle. * @param[in] ccaThresholdDbm The CCA threshold in dBm. * @return Status code indicating success of the function call. * * Unlike RAIL_StartCcaCsmaTx() or RAIL_StartCcaLbtTx(), which can cause a * transmit, this function only modifies the CCA threshold. A possible * use case for this function involves setting the CCA threshold to invalid RSSI * of -128 which blocks transmission by preventing clear channel assessments * from succeeding. */ RAIL_Status_t RAIL_SetCcaThreshold(RAIL_Handle_t railHandle, int8_t ccaThresholdDbm); /** * Gets detailed information about the last packet transmitted. * * @param[in] railHandle A RAIL instance handle. * @param[in,out] pPacketDetails An application-provided pointer to store * RAIL_TxPacketDetails_t corresponding to the transmit event. * The isAck and timeSent fields totalPacketBytes and timePosition * must be initialized prior to each call: * - isAck true to obtain details about the most recent ACK transmit, * false to obtain details about the most recent app-initiated transmit. * - totalPacketBytes with the total number of bytes of the transmitted * packet for RAIL to use when calculating the specified timestamp. * This should account for all bytes sent over the air after the * Preamble and Sync word(s), including CRC bytes. * - timePosition with a \ref RAIL_PacketTimePosition_t value specifying * the packet position to put in the timeSent field on return. * This field will also be updated with the actual position corresponding * to the timeSent value filled in. * @return \ref RAIL_STATUS_NO_ERROR if pPacketDetails was filled in, * or an appropriate error code otherwise. * * @note Consider using \ref RAIL_GetTxPacketDetailsAlt for smaller code size. * * This function can only be called from callback context for either * \ref RAIL_EVENT_TX_PACKET_SENT or \ref RAIL_EVENT_TXACK_PACKET_SENT * events. */ RAIL_Status_t RAIL_GetTxPacketDetails(RAIL_Handle_t railHandle, RAIL_TxPacketDetails_t *pPacketDetails); /** * Gets detailed information about the last packet transmitted. * * @param[in] railHandle A RAIL instance handle. * @param[in] isAck True to obtain details about the most recent ACK transmit. * False to obtain details about the most recent app-initiated transmit. * @param[out] pPacketTime An application-provided non-NULL pointer to store a * RAIL_Time_t corresponding to the transmit event. This will be populated * with a timestamp corresponding to an arbitrary location in the packet. Call * \ref RAIL_GetTxTimePreambleStart, \ref RAIL_GetTxTimeSyncWordEnd, or * \ref RAIL_GetTxTimeFrameEnd to adjust the timestamp for different locations * in the packet. * @return \ref RAIL_STATUS_NO_ERROR if pPacketTime was filled in, * or an appropriate error code otherwise. * * This function can only be called from callback context for either * \ref RAIL_EVENT_TX_PACKET_SENT or \ref RAIL_EVENT_TXACK_PACKET_SENT * events. */ RAIL_Status_t RAIL_GetTxPacketDetailsAlt(RAIL_Handle_t railHandle, bool isAck, RAIL_Time_t *pPacketTime); /** * Adjust a RAIL TX timestamp to refer to the start of the preamble. * * @param[in] railHandle A RAIL instance handle. * @param[in] totalPacketBytes The total number of bytes of the transmitted * packet for RAIL to use when calculating the specified timestamp. This * should account for all bytes transmitted over the air after the Preamble * and Sync word(s), including CRC bytes. * @param[in, out] pPacketTime The time that was returned in a * \ref RAIL_Time_t from a previous call to \ref RAIL_GetTxPacketDetailsAlt * for this same packet. After this function, the time at that location will * be updated with the time that the preamble for this packet started on air. * Must be non-NULL. * @return \ref RAIL_STATUS_NO_ERROR if pPacketTime was successfully calculated, * or an appropriate error code otherwise. * * This timestamp adjustment API should be called in the same interrupt context * as \ref RAIL_GetTxPacketDetailsAlt in order to get the timestamp for the * beginning of the preamble. */ RAIL_Status_t RAIL_GetTxTimePreambleStart(RAIL_Handle_t railHandle, uint16_t totalPacketBytes, RAIL_Time_t *pPacketTime); /** * Adjust a RAIL TX timestamp to refer to the end of the sync word * * @param[in] railHandle A RAIL instance handle. * @param[in] totalPacketBytes The total number of bytes of the transmitted * packet for RAIL to use when calculating the specified timestamp. This * should account for all bytes transmitted over the air after the Preamble * and Sync word(s), including CRC bytes. * @param[in, out] pPacketTime The time that was returned in a * \ref RAIL_Time_t from a previous call to \ref RAIL_GetTxPacketDetailsAlt * for this same packet. After this function, the time at that location will * be updated with the time that the sync word for this packet finished on * air. Must be non-NULL. * @return \ref RAIL_STATUS_NO_ERROR if pPacketTime was successfully calculated, * or an appropriate error code otherwise. * * This timestamp adjustment API should be called in the same interrupt context * as \ref RAIL_GetTxPacketDetailsAlt in order to get the timestamp for the * end of the sync word. */ RAIL_Status_t RAIL_GetTxTimeSyncWordEnd(RAIL_Handle_t railHandle, uint16_t totalPacketBytes, RAIL_Time_t *pPacketTime); /** * Adjust a RAIL TX timestamp to refer to the end of frame * * @param[in] railHandle A RAIL instance handle. * @param[in] totalPacketBytes The total number of bytes of the transmitted * packet for RAIL to use when calculating the specified timestamp. This * should account for all bytes transmitted over the air after the Preamble * and Sync word(s), including CRC bytes. * @param[in, out] pPacketTime The time that was returned in a * \ref RAIL_Time_t from a previous call to \ref RAIL_GetTxPacketDetailsAlt * for this same packet. After this function, the time at that location will * be updated with the time that this packet finished on air. Must be * non-NULL. * @return \ref RAIL_STATUS_NO_ERROR if pPacketTime was successfully calculated, * or an appropriate error code otherwise. * * This timestamp adjustment API should be called in the same interrupt context * as \ref RAIL_GetTxPacketDetailsAlt in order to get the timestamp for the * end of the frame. */ RAIL_Status_t RAIL_GetTxTimeFrameEnd(RAIL_Handle_t railHandle, uint16_t totalPacketBytes, RAIL_Time_t *pPacketTime); /** * Prevent the radio from starting a transmit. * * @param[in] railHandle A RAIL instance handle. * @param[in] enable Enable/Disable TX hold off. * @return void. * * Enable TX hold off to prevent the radio from starting any transmits. * Disable TX hold off to allow the radio to transmit again. * Attempting to transmit with the TX hold off enabled will result in * \ref RAIL_EVENT_TX_BLOCKED and/or \ref RAIL_EVENT_TXACK_BLOCKED * events. * * @note This function does not affect a transmit that has already started. * To stop an already-started transmission, use RAIL_Idle() with * \ref RAIL_IDLE_ABORT. */ void RAIL_EnableTxHoldOff(RAIL_Handle_t railHandle, bool enable); /** * Check whether or not TX hold off is enabled. * * @param[in] railHandle A RAIL instance handle. * @return Returns true if TX hold off is enabled, false otherwise. * * TX hold off can be enabled/disabled using \ref RAIL_EnableTxHoldOff. * Attempting to transmit with the TX hold off enabled will block the * transmission and result in \ref RAIL_EVENT_TX_BLOCKED * and/or \ref RAIL_EVENT_TXACK_BLOCKED events. */ bool RAIL_IsTxHoldOffEnabled(RAIL_Handle_t railHandle); /** * Sets an alternate transmitter preamble length. * * @param[in] railHandle A RAIL instance handle. * @param[in] length The desired preamble length, in bits. * @return Status code indicating success of the function call. * * @note Attempting to set a preamble length of 0xFFFF bits will result in * \ref RAIL_STATUS_INVALID_PARAMETER. **/ RAIL_Status_t RAIL_SetTxAltPreambleLength(RAIL_Handle_t railHandle, uint16_t length); /** @} */ // end of group Transmit /****************************************************************************** * Receive *****************************************************************************/ /** * @addtogroup Receive * @brief APIs related to packet receive * @{ */ /** * Configures receive options. * * @param[in] railHandle A RAIL instance handle. * @param[in] mask A bitmask containing which options should be modified. * @param[in] options A bitmask containing desired configuration settings. * Bit positions for each option are found in the \ref RAIL_RxOptions_t. * @return Status code indicating success of the function call. * * Configures the radio receive flow based on the list of available options. * Only the options indicated by the mask parameter will be affected. Pass * \ref RAIL_RX_OPTIONS_ALL to set all parameters. * The previous settings may affect the current frame if a packet is * received during this configuration. */ RAIL_Status_t RAIL_ConfigRxOptions(RAIL_Handle_t railHandle, RAIL_RxOptions_t mask, RAIL_RxOptions_t options); /** * Function to include the code necessary for frame type based length decoding. * * @param[in] railHandle A RAIL instance handle. * @return void. * * This must be called before \ref RAIL_ConfigChannels to allow configurations * using a frame type based length setup. In RAIL 2.x this is called by default * in the \ref RAILCb_ConfigFrameTypeLength API which can be overridden to save * code space. In future versions the user may be required to call this API * explicitly. */ void RAIL_IncludeFrameTypeLength(RAIL_Handle_t railHandle); /** * Function implemented in the radio config for frame type length handling * * @param[in] railHandle A RAIL instance handle. * @param[in] frameType A frame type configuration structure. * @return void. * * Currently, the frame type passed in only handles packet length decoding. If * NULL is passed into this function, it clears any currently configured * frame type settings. This will either be implemented as an empty function in * the radio configuration if it is not needed, to assist in dead code * elimination. */ void RAILCb_ConfigFrameTypeLength(RAIL_Handle_t railHandle, const RAIL_FrameType_t *frameType); /** * Starts the receiver on a specific channel. * * @param[in] railHandle A RAIL instance handle. * @param[in] channel The channel to listen on. * @param[in] schedulerInfo Information to allow the radio scheduler to place * this receive appropriately. This is only used in multiprotocol version of * RAIL and may be set to NULL in all other versions. * @return Status code indicating success of the function call. * * This is a non-blocking function. Whenever a packet is received, \ref RAIL_Config_t::eventsCallback * will fire with \ref RAIL_EVENT_RX_PACKET_RECEIVED set. If you call * this while not idle but with a different channel, any ongoing * receive or transmit operation will be aborted. */ RAIL_Status_t RAIL_StartRx(RAIL_Handle_t railHandle, uint16_t channel, const RAIL_SchedulerInfo_t *schedulerInfo); /** * Schedules a receive window for some future time. * * @param[in] railHandle A RAIL instance handle. * @param[in] channel A channel to listen on. * @param[in] cfg The configuration structure to define the receive window. * @param[in] schedulerInfo Information to allow the radio scheduler to place * this receive appropriately. This is only used in multiprotocol version of * RAIL and may be set to NULL in all other versions. * @return Status code indicating success of the function call. * * This API immediately changes the channel and schedules receive to start * at the specified time and end at the given end time. If you do not specify * an end time, you may call this API later with an end time as long as you set * the start time to disabled. You can also terminate the receive * operation immediately using the RAIL_Idle() function. Note that relative * end times are always relative to the start unless no start time is * specified. If changing channels, aborts any ongoing packet transmission or * reception. * * In multiprotocol, ensure that you properly yield the radio after this * call. See \ref rail_radio_scheduler_yield for more details. */ RAIL_Status_t RAIL_ScheduleRx(RAIL_Handle_t railHandle, uint16_t channel, const RAIL_ScheduleRxConfig_t *cfg, const RAIL_SchedulerInfo_t *schedulerInfo); /****************************************************************************** * Packet Infomation (RX) *****************************************************************************/ /// @addtogroup Packet_Information Packet Information /// @brief APIs to get information about received packets. /// /// After receiving a packet, RAIL will trigger a /// \ref RAIL_EVENT_RX_PACKET_RECEIVED event. At that point, there is a variety /// of information available to the application about the received packet. The /// following example code assumes that the /// \ref RAIL_RX_OPTION_REMOVE_APPENDED_INFO is not used, and the application /// wants as much data about the packet as possible. /// /// @code{.c} /// // Get all information about a received packet. /// RAIL_Status_t status; /// RAIL_RxPacketInfo_t rxInfo; /// RAIL_RxPacketDetails_t rxDetails; /// RAIL_RxPacketHandle_t rxHandle /// = RAIL_GetRxPacketInfo(railHandle, RAIL_RX_PACKET_HANDLE_NEWEST, &rxInfo); /// assert(rxHandle != RAIL_RX_PACKET_HANDLE_INVALID); /// status = RAIL_GetRxPacketDetailsAlt(railHandle, rxHandle, &rxDetails); /// assert(status == RAIL_STATUS_NO_ERROR); /// if (rxDetails.timeReceived.timePosition == RAIL_PACKET_TIME_INVALID) { /// return; // No timestamp available for this packet /// } /// // CRC_BYTES only needs to be added when not using RAIL_RX_OPTION_STORE_CRC /// rxDetails.timeReceived.totalPacketBytes = rxInfo.packetBytes + CRC_BYTES; /// // Choose the function which gives the desired timestamp /// status = RAIL_GetRxTimeFrameEndAlt(railHandle, &rxDetails); /// assert(status == RAIL_STATUS_NO_ERROR); /// // Now all fields of rxInfo and rxDetails have been populated correctly /// @endcode /// /// @{ /** * Gets basic information about a pending or received packet. * * @param[in] railHandle A RAIL instance handle. * @param[in] packetHandle A packet handle for the unreleased packet as * returned from a previous call, or sentinel values * \ref RAIL_RX_PACKET_HANDLE_OLDEST or \ref RAIL_RX_PACKET_HANDLE_NEWEST. * @param[out] pPacketInfo An application-provided pointer to store * \ref RAIL_RxPacketInfo_t for the requested packet. Must be non-NULL. * @return The packet handle for the requested packet: * if packetHandle was one of the sentinel values, returns the actual * packet handle for that packet, otherwise returns packetHandle. * It may return \ref RAIL_RX_PACKET_HANDLE_INVALID to indicate an error. * * This function can be used in any RX mode; it does not free up any * internal resources. If used in RX \ref RAIL_DataMethod_t::FIFO_MODE, the * value in \ref RAIL_RxPacketInfo_t::packetBytes will only return the data * remaining in the FIFO. Any data read via earlier earlier calls to * \ref RAIL_ReadRxFifo() is not included. * * @note When getting information about an arriving packet that is not yet complete * (i.e., pPacketInfo->packetStatus == \ref RAIL_RX_PACKET_RECEIVING), keep * in mind its data is highly suspect because it has not yet passed any CRC * integrity checking. Also note that the packet could be aborted, canceled, or * fail momentarily, invalidating its data in Packet mode. Furthermore, there * is a small chance towards the end of packet reception that the filled-in * RAIL_RxPacketInfo_t could include not only packet data received so far, * but also some raw radio-appended info detail bytes that RAIL's * packet-completion processing will subsequently deal with. It's up to the * application to know its packet format well enough to avoid confusing such * info as packet data. */ RAIL_RxPacketHandle_t RAIL_GetRxPacketInfo(RAIL_Handle_t railHandle, RAIL_RxPacketHandle_t packetHandle, RAIL_RxPacketInfo_t *pPacketInfo); /** * Convenience helper function to copy a full packet to a user-specified * contiguous buffer. * * @param[out] pDest An application-provided pointer to a buffer of at * least pPacketInfo->packetBytes in size to store the packet data * contiguously. This buffer must never overlay RAIL's receive FIFO buffer. * Exactly pPacketInfo->packetBytes of packet data will be written into it. * @param[out] pPacketInfo * \ref RAIL_RxPacketInfo_t for the requested packet. * @return void. * * @note This helper is intended to be expedient. As a result, it does not * check the validity of its arguments, * so don't pass either as NULL, and don't * pass a pDest pointer to a buffer that's too small for the packet's data. * @note If only a portion of the packet is needed, use RAIL_PeekRxPacket() * instead. */ static inline void RAIL_CopyRxPacket(uint8_t *pDest, const RAIL_RxPacketInfo_t *pPacketInfo) { memcpy(pDest, pPacketInfo->firstPortionData, pPacketInfo->firstPortionBytes); if (pPacketInfo->lastPortionData != NULL) { memcpy(pDest + pPacketInfo->firstPortionBytes, pPacketInfo->lastPortionData, pPacketInfo->packetBytes - pPacketInfo->firstPortionBytes); } } /** * Gets detailed information about a received packet. * This function can be used in any RX mode; it does not free up any * internal resources. * * @param[in] railHandle A RAIL instance handle. * @param[in] packetHandle A packet handle for the unreleased packet as * returned from a previous call to RAIL_GetRxPacketInfo() or * RAIL_HoldRxPacket(), or sentinel values \ref RAIL_RX_PACKET_HANDLE_OLDEST * or \ref RAIL_RX_PACKET_HANDLE_NEWEST. * @param[in,out] pPacketDetails An application-provided non-NULL pointer to * store \ref RAIL_RxPacketDetails_t for the requested packet. * For \ref RAIL_RxPacketStatus_t RAIL_RX_PACKET_READY_ packets, * the timeReceived fields totalPacketBytes and timePosition must be * initialized prior to each call: * - totalPacketBytes with the total number of bytes of the received * packet for RAIL to use when calculating the specified timestamp. * This should account for all bytes received over the air after the * Preamble and Sync word(s), including CRC bytes. * - timePosition with a \ref RAIL_PacketTimePosition_t value specifying * the packet position to put in the timeReceived field on return. * This field will also be updated with the actual position corresponding * to the timeReceived value filled in. * @return \ref RAIL_STATUS_NO_ERROR if pPacketDetails was filled in, * or an appropriate error code otherwise. * * @note Certain details are always available, while others are only available * if the \ref RAIL_RxOptions_t \ref RAIL_RX_OPTION_REMOVE_APPENDED_INFO * option is not in effect and the received packet's * \ref RAIL_RxPacketStatus_t is among the RAIL_RX_PACKET_READY_ set. * See \ref RAIL_RxPacketDetails_t for clarification. * * @note Consider using \ref RAIL_GetRxPacketDetailsAlt for smaller code size. */ RAIL_Status_t RAIL_GetRxPacketDetails(RAIL_Handle_t railHandle, RAIL_RxPacketHandle_t packetHandle, RAIL_RxPacketDetails_t *pPacketDetails); /** * Gets detailed information about a received packet. * This function can be used in any RX mode; it does not free up any * internal resources. * * @param[in] railHandle A RAIL instance handle. * @param[in] packetHandle A packet handle for the unreleased packet as * returned from a previous call to RAIL_GetRxPacketInfo() or * RAIL_HoldRxPacket(), or sentinel values \ref RAIL_RX_PACKET_HANDLE_OLDEST * or \ref RAIL_RX_PACKET_HANDLE_NEWEST. * @param[out] pPacketDetails An application-provided non-NULL pointer to * store \ref RAIL_RxPacketDetails_t for the requested packet. * For \ref RAIL_RxPacketStatus_t RAIL_RX_PACKET_READY_ packets, * the timeReceived field packetTime will be populated with a timestamp * corresponding to an arbitrary location in the packet. Call * \ref RAIL_GetRxTimePreambleStart, \ref RAIL_GetRxTimeSyncWordEnd, or * \ref RAIL_GetRxTimeFrameEnd to adjust that timestamp for different * locations in the packet. * @return \ref RAIL_STATUS_NO_ERROR if pPacketDetails was filled in, * or an appropriate error code otherwise. * * This alternative API allows for smaller code size by deadstripping the * timestamp adjustment algorithms which are not in use. * * @note Certain details are always available, while others are only available * if the \ref RAIL_RxOptions_t \ref RAIL_RX_OPTION_REMOVE_APPENDED_INFO * option is not in effect and the received packet's * \ref RAIL_RxPacketStatus_t is among the RAIL_RX_PACKET_READY_ set. * See \ref RAIL_RxPacketDetails_t for clarification. */ RAIL_Status_t RAIL_GetRxPacketDetailsAlt(RAIL_Handle_t railHandle, RAIL_RxPacketHandle_t packetHandle, RAIL_RxPacketDetails_t *pPacketDetails); /** * Adjust a RAIL RX timestamp to refer to the start of the preamble. * * @param[in] railHandle A RAIL instance handle. * @param[in] totalPacketBytes The total number of bytes of the received packet * for RAIL to use when calculating the specified timestamp. This should * account for all bytes received over the air after the Preamble and Sync * word(s), including CRC bytes. * @param[in, out] pPacketTime The time that was returned in the * \ref RAIL_PacketTimeStamp_t::packetTime field of * \ref RAIL_RxPacketDetails_t::timeReceived from a previous call to * \ref RAIL_GetRxPacketDetailsAlt for this same packet. After this * function, the time at that location will be updated with the time that the * preamble for this packet started on air. Must be non-NULL. * @return \ref RAIL_STATUS_NO_ERROR if pPacketTime was successfully calculated, * or an appropriate error code otherwise. * * This API must be called while the given railHandle is active, or it will * return an error code of \ref RAIL_STATUS_INVALID_STATE. Note that this API * may return incorrect timestamps when sub-phys are in use, as in the BLE Coded * PHY. Prefer \ref RAIL_GetRxTimePreambleStartAlt in those situations. */ RAIL_Status_t RAIL_GetRxTimePreambleStart(RAIL_Handle_t railHandle, uint16_t totalPacketBytes, RAIL_Time_t *pPacketTime); /** * Adjust a RAIL RX timestamp to refer to the start of the preamble. * * @param[in] railHandle A RAIL instance handle. * @param[in, out] pPacketDetails The non-NULL details that were returned from * a previous call to \ref RAIL_GetRxPacketDetailsAlt for this same packet. * The application must update the timeReceived field totalPacketBytes to be * the total number of bytes of the received packet for RAIL to use when * calculating the specified timestamp. This should account for all bytes * received over the air after the Preamble and Sync word(s), including CRC * bytes. After this function, the timeReceived field packetTime will be * updated with the time that the preamble for this packet started on air. * @return \ref RAIL_STATUS_NO_ERROR if the packet time was successfully * calculated, or an appropriate error code otherwise. * * This API must be called while the given railHandle is active, or it will * return an error code of \ref RAIL_STATUS_INVALID_STATE. */ RAIL_Status_t RAIL_GetRxTimePreambleStartAlt(RAIL_Handle_t railHandle, RAIL_RxPacketDetails_t *pPacketDetails); /** * Adjust a RAIL RX timestamp to refer to the end of the sync word * * @param[in] railHandle A RAIL instance handle. * @param[in] totalPacketBytes The total number of bytes of the received packet * for RAIL to use when calculating the specified timestamp. This should * account for all bytes received over the air after the Preamble and Sync * word(s), including CRC bytes. * @param[in, out] pPacketTime The time that was returned in the * \ref RAIL_PacketTimeStamp_t::packetTime field of * \ref RAIL_RxPacketDetails_t::timeReceived from a previous call to * \ref RAIL_GetRxPacketDetailsAlt for this same packet. After this * function, the time at that location will be updated with the time that the * sync word for this packet finished on air. Must be non-NULL. * @return \ref RAIL_STATUS_NO_ERROR if pPacketTime was successfully calculated, * or an appropriate error code otherwise. * * This API must be called while the given railHandle is active, or it will * return an error code of \ref RAIL_STATUS_INVALID_STATE. Note that this API * may return incorrect timestamps when sub-phys are in use, as in the BLE Coded * PHY. Prefer \ref RAIL_GetRxTimeSyncWordEndAlt in those situations. */ RAIL_Status_t RAIL_GetRxTimeSyncWordEnd(RAIL_Handle_t railHandle, uint16_t totalPacketBytes, RAIL_Time_t *pPacketTime); /** * Adjust a RAIL RX timestamp to refer to the end of the sync word * * @param[in] railHandle A RAIL instance handle. * @param[in, out] pPacketDetails The non-NULL details that were returned from * a previous call to \ref RAIL_GetRxPacketDetailsAlt for this same packet. * The application must update the timeReceived field totalPacketBytes to be * the total number of bytes of the received packet for RAIL to use when * calculating the specified timestamp. This should account for all bytes * received over the air after the Preamble and Sync word(s), including CRC * bytes. After this function, the timeReceived field packetTime will be * updated with the time that the sync word for this packet finished on air. * @return \ref RAIL_STATUS_NO_ERROR if the packet time was successfully * calculated, or an appropriate error code otherwise. * * This API must be called while the given railHandle is active, or it will * return an error code of \ref RAIL_STATUS_INVALID_STATE. */ RAIL_Status_t RAIL_GetRxTimeSyncWordEndAlt(RAIL_Handle_t railHandle, RAIL_RxPacketDetails_t *pPacketDetails); /** * Adjust a RAIL RX timestamp to refer to the end of frame * * @param[in] railHandle A RAIL instance handle. * @param[in] totalPacketBytes The total number of bytes of the received packet * for RAIL to use when calculating the specified timestamp. This should * account for all bytes received over the air after the Preamble and Sync * word(s), including CRC bytes. * @param[in, out] pPacketTime The time that was returned in the * \ref RAIL_PacketTimeStamp_t::packetTime field of * \ref RAIL_RxPacketDetails_t::timeReceived from a previous call to * \ref RAIL_GetRxPacketDetailsAlt for this same packet. After this * function, the time at that location will be updated with the time that this * packet finished on air. Must be non-NULL. * @return \ref RAIL_STATUS_NO_ERROR if pPacketTime was successfully calculated, * or an appropriate error code otherwise. * * This API must be called while the given railHandle is active, or it will * return an error code of \ref RAIL_STATUS_INVALID_STATE. Note that this API * may return incorrect timestamps when sub-phys are in use, as in the BLE Coded * PHY. Prefer \ref RAIL_GetRxTimeFrameEndAlt in those situations. */ RAIL_Status_t RAIL_GetRxTimeFrameEnd(RAIL_Handle_t railHandle, uint16_t totalPacketBytes, RAIL_Time_t *pPacketTime); /** * Adjust a RAIL RX timestamp to refer to the end of frame * * @param[in] railHandle A RAIL instance handle. * @param[in, out] pPacketDetails The non-NULL details that were returned from * a previous call to \ref RAIL_GetRxPacketDetailsAlt for this same packet. * The application must update the timeReceived field totalPacketBytes to be * the total number of bytes of the received packet for RAIL to use when * calculating the specified timestamp. This should account for all bytes * received over the air after the Preamble and Sync word(s), including CRC * bytes. After this function, the timeReceived field packetTime will be * updated with the time that the packet finished on air. * @return \ref RAIL_STATUS_NO_ERROR if the packet time was successfully * calculated, or an appropriate error code otherwise. * * This API must be called while the given railHandle is active, or it will * return an error code of \ref RAIL_STATUS_INVALID_STATE. */ RAIL_Status_t RAIL_GetRxTimeFrameEndAlt(RAIL_Handle_t railHandle, RAIL_RxPacketDetails_t *pPacketDetails); /** @} */ // end of group Packet_Information /** * Place a temporary hold on this packet's data and information resources * within RAIL. * This function can only be called from within RAIL callback context. * It can be used in any RX mode. * * Normally, when RAIL issues its callback indicating a packet is ready * or aborted, it expects the application's callback to retrieve and * copy (or discard) the packet's information and data, and will free up * its internal packet data after the callback returns. This function * tells RAIL to hold onto those resources after the callback returns in * case the application wants to defer processing the packet to a later * time, e.g., outside of callback context. * * @param[in] railHandle A RAIL instance handle. * @return The packet handle for the packet associated with the callback, * \ref RAIL_RX_PACKET_HANDLE_INVALID if no such packet yet exists or * railHandle is not active. */ RAIL_RxPacketHandle_t RAIL_HoldRxPacket(RAIL_Handle_t railHandle); /** * Copies 'len' bytes of packet data starting from 'offset' from the * receive FIFO. Those bytes remain valid for re-peeking. * * @param[in] railHandle A RAIL instance handle. * @param[in] packetHandle A packet handle as returned from a previous * RAIL_GetRxPacketInfo() or RAIL_HoldRxPacket() call, or * sentinel values \ref RAIL_RX_PACKET_HANDLE_OLDEST * or \ref RAIL_RX_PACKET_HANDLE_NEWEST. * @param[out] pDst A pointer to the location where the received bytes will * be copied. If NULL, no copying occurs. * @param[in] len A number of packet data bytes to copy. * @param[in] offset A byte offset within remaining packet data from which * to copy. * @return Number of packet bytes copied. * * @note Peek does not permit peeking beyond the requested packet's * available packet data (though there is a small chance it might * for a \ref RAIL_RX_PACKET_HANDLE_NEWEST packet at the very end of * still being received). Nor can one peek into already-consumed data read * by RAIL_ReadRxFifo(). len and offset are relative to the remaining data * available in the packet, if any was already consumed by RAIL_ReadRxFifo(). */ uint16_t RAIL_PeekRxPacket(RAIL_Handle_t railHandle, RAIL_RxPacketHandle_t packetHandle, uint8_t *pDst, uint16_t len, uint16_t offset); /** * Releases RAIL's internal resources for the packet. * This function must be called for any packet previously held via * RAIL_HoldRxPacket(). It may optionally be called within a * callback context to release RAIL resources sooner than at * callback completion time when not holding the packet. * This function can be used in any RX mode. * * @param[in] railHandle A RAIL instance handle. * @param[in] packetHandle A packet handle as returned from a previous * RAIL_HoldRxPacket() call, or sentinel values * \ref RAIL_RX_PACKET_HANDLE_OLDEST or \ref RAIL_RX_PACKET_HANDLE_NEWEST. * The latter might be used within RAIL callback context to explicitly * release the packet associated with the callback early, before it's * released automatically by RAIL on callback return (unless explicitly * held). * @return \ref RAIL_STATUS_NO_ERROR if the held packet was released * or an appropriate error code otherwise. */ RAIL_Status_t RAIL_ReleaseRxPacket(RAIL_Handle_t railHandle, RAIL_RxPacketHandle_t packetHandle); /** * Returns the current raw RSSI. * * @param[in] railHandle A RAIL instance handle. * @param[in] wait if false returns instant RSSI with no checks. * @return \ref RAIL_RSSI_INVALID if the receiver is disabled and an RSSI * value can't be obtained. Otherwise, return the RSSI in quarter dBm, dbm*4. * * Gets the current RSSI value. This value represents the current energy of the * channel. It can change rapidly and will be low if no RF energy is * in the current channel. The function from the value reported to dBm is an * offset dependent on the PHY and the PCB layout. Users should characterize the * RSSI received on their hardware and apply an offset in the application to * account for board and PHY parameters. 'Wait' argument doesn't guarantee * a valid RSSI reading.'Wait' being true gives assurance that that the RSSI is * current and not a stale value from a previous radio state. If GetRssi is called * during RX-to-RX, RX-to-IDLE, or RX-to-TX transition, the RSSI is considered * stale and \ref RAIL_RSSI_INVALID is returned if wait=true. 'Wait' being false * will return either the current RSSI or a stale RSSI measurement (if called during * RX-to-RX, RX-to-IDLE, or RX-to-TX transition). \ref RAIL_RSSI_INVALID is * returned if radio hasn't been in RX longer than 'idleToRx' time * (see \ref RAIL_StateTiming_t), regardless of wait argument. * * In multiprotocol, this function returns \ref RAIL_RSSI_INVALID * immediately if railHandle is not the current active \ref RAIL_Handle_t. * Additionally, 'wait' should never be set 'true' in multiprotocol * as the wait time is not consistent, so scheduling a scheduler * slot cannot be done accurately. * * @note: If RX channel hopping is turned on, this API * should not be used. Instead see RAIL_GetChannelHoppingRssi(). */ int16_t RAIL_GetRssi(RAIL_Handle_t railHandle, bool wait); /** * Starts the RSSI averaging over a specified time in us. * * @param[in] railHandle A RAIL instance handle. * @param[in] channel The physical channel to set. * @param[in] averagingTimeUs Averaging time in microseconds. * @param[in] schedulerInfo Information to allow the radio scheduler to place * this operation appropriately. This is only used in multiprotocol version of * RAIL and may be set to NULL in all other versions. * @return Status code indicating success of the function call. * * Starts a non-blocking hardware-based RSSI averaging mechanism. Only a single * instance of RSSI averaging can be run at any time and the radio must be idle * to start. * * In multiprotocol, this is a scheduled event. It will start when railHandle * becomes active. railHandle needs to stay active until the averaging * completes. If the averaging is interrupted, calls to * \ref RAIL_GetAverageRssi will return \ref RAIL_RSSI_INVALID. * * Also in multiprotocol, the user is required to call \ref RAIL_YieldRadio * after this event completes (i.e., when \ref RAIL_EVENT_RSSI_AVERAGE_DONE * occurs). */ RAIL_Status_t RAIL_StartAverageRssi(RAIL_Handle_t railHandle, uint16_t channel, RAIL_Time_t averagingTimeUs, const RAIL_SchedulerInfo_t *schedulerInfo); /** * Queries whether the RSSI averaging is done. * * @param[in] railHandle A RAIL instance handle. * @return Returns true if done and false otherwise. * * This function can be used to poll for completion of the RSSI averaging * to avoid relying on an interrupt-based callback. */ bool RAIL_IsAverageRssiReady(RAIL_Handle_t railHandle); /** * Gets the RSSI averaged over a specified time in us. * * @param[in] railHandle A RAIL instance handle. * @return Return \ref RAIL_RSSI_INVALID if the receiver is disabled * an RSSI value can't be obtained. Otherwise, return the RSSI in * quarter dBm,dbm*4. * * Gets the hardware RSSI average after issuing RAIL_StartAverageRssi. * It should be used after \ref RAIL_StartAverageRssi. */ int16_t RAIL_GetAverageRssi(RAIL_Handle_t railHandle); /** * Sets the RSSI offset. * * @param[in] railHandle a RAIL instance handle. * @param[in] rssiOffset desired offset to be added to the RSSI measurements. * @return Status code indicating success of the function call. * * Adds an offset to the RSSI in dBm. This offset affects all functionality that * depends on RSSI values, such as CCA fuctions. The offset should not be * modified dynamically during the RX of a packet. */ RAIL_Status_t RAIL_SetRssiOffset(RAIL_Handle_t railHandle, int8_t rssiOffset); /** * Gets the RSSI offset. * * @param[in] railHandle a RAIL instance handle. * @return rssiOffset in dBm corresponding to the current handle. * */ int8_t RAIL_GetRssiOffset(RAIL_Handle_t railHandle); /** * Setup a callback function capable of converting a RX packet's LQI value * before being consumed by application code. * * @param[in] railHandle A RAIL instance handle. * @param[in] cb A callback of type \ref RAIL_ConvertLqiCallback_t that is * called before the RX packet LQI value is loaded into the \ref * RAIL_RxPacketDetails_t structure for application consumption. * @return Status code indicating success of the function call. */ RAIL_Status_t RAIL_ConvertLqi(RAIL_Handle_t railHandle, RAIL_ConvertLqiCallback_t cb); /****************************************************************************** * Address Filtering (RX) *****************************************************************************/ /** * @addtogroup Address_Filtering Address Filtering * @brief Configuration APIs for receive packet address filtering. * * The address filtering code examines the packet as follows. * * | `Bytes: 0 - 255` | `0 - 8` | `0 - 255` | `0 - 8` | `Variable` | * |:----------------:|---------:|----------:|---------:|:----------:| * | `Data0` | `Field0` | `Data1` | `Field1` | `Data2` | * * In the above structure, anything listed as DataN is an optional section of * bytes that RAIL will not process for address filtering. The FieldN segments * reference specific sections in the packet that will each be interpreted * as an address during address filtering. The application may submit up to * four addresses to attempt to match each field segment and each address may * have a size of up to 8 bytes. To set up address filtering, first configure * the locations and length of the addresses in the packet. Next, configure * which combinations of matches in Field0 and Field1 should constitute an * address match. Last, enter addresses into tables for each field and * enable them. The first two of these are part of the \ref RAIL_AddrConfig_t * structure while the second part is configured at runtime using the * RAIL_SetAddressFilterAddress() API. A brief description of each * configuration is listed below. * * The offsets and sizes of the fields * are assumed fixed for the RAIL address filter. To set them, specify * arrays for these values in the sizes and offsets entries in the * \ref RAIL_AddrConfig_t structure. A size of zero indicates that a field is * disabled. The start offset for a field is relative to the previous start * offset and, if you're using FrameType decoding, the first start offset is * relative to the end of the byte containing the frame type. * * Configuring which combinations of Field0 and Field1 constitute a match is * the most complex portion of the address filter. The easiest way to think * about this is with a truth table. If you consider each of the four possible * address entries in a field, you can have a match on any one of those or a * match for none of them. This is shown in the 5x5 truth table below where * Field0 matches are the rows and Field1 matches are the columns. * * | | No Match | Address 0 | Address 1 | Address 2 | Address 3 | * |----------------|----------|-----------|-----------|-----------|-----------| * | __No Match__ | bit0 | bit1 | bit2 | bit3 | bit4 | * | __Address 0__ | bit5 | bit6 | bit7 | bit8 | bit9 | * | __Address 1__ | bit10 | bit11 | bit12 | bit13 | bit14 | * | __Address 2__ | bit15 | bit16 | bit17 | bit18 | bit19 | * | __Address 3__ | bit20 | bit21 | bit22 | bit23 | bit24 | * * Because this is only 25 bits, it can be represented in one 32-bit integer * where 1 indicates a filter pass and 0 indicates a filter fail. This is the * matchTable parameter in the configuration structure and is used during * filtering. For common simple configurations two defines are provided with * the truth tables as shown below. The first is \ref * ADDRCONFIG_MATCH_TABLE_SINGLE_FIELD, which can be used if only using * one address field (either field). If using two fields and want to * force in the same address entry in each field, use the second define: \ref * ADDRCONFIG_MATCH_TABLE_DOUBLE_FIELD. For more complex systems, * create a valid custom table. * * @note Address filtering does not function reliably with PHYs that use a data * rate greater than 500 kbps. If this is a requirement, filtering must * currently be done by the application. * * @{ */ /** * Configures address filtering. * * @param[in] railHandle A RAIL instance handle. * @param[in] addrConfig The configuration structure, which defines how * addresses are setup in your packets. * @return Status code indicating success of the function call. * * This function must be called to set up address filtering. You may call it * multiple times but all previous information is wiped out each time you call * and any configured addresses must be reset. */ RAIL_Status_t RAIL_ConfigAddressFilter(RAIL_Handle_t railHandle, const RAIL_AddrConfig_t *addrConfig); /** * Enables address filtering. * * @param[in] railHandle A RAIL instance handle. * @param[in] enable An argument to indicate whether or not to enable address * filtering. * @return True if address filtering was enabled to start with and false * otherwise. * * Only allow packets through that pass the current address filtering * configuration. This does not reset or change the configuration so you can * set that up before turning on this feature. */ bool RAIL_EnableAddressFilter(RAIL_Handle_t railHandle, bool enable); /** * Returns whether address filtering is currently enabled. * * @param[in] railHandle A RAIL instance handle. * @return True if address filtering is enabled and false otherwise. */ bool RAIL_IsAddressFilterEnabled(RAIL_Handle_t railHandle); /** * Resets the address filtering configuration. * * @param[in] railHandle A RAIL instance handle. * @return void. * * Resets all structures related to address filtering. This does not disable * address filtering. It leaves the radio in a state where no packets * pass filtering. */ void RAIL_ResetAddressFilter(RAIL_Handle_t railHandle); /** * Sets an address for filtering in hardware. * * @param[in] railHandle A RAIL instance handle. * @param[in] field Indicates an address field for this address. * @param[in] index Indicates a match entry for this address for a * given field. * @param[in] value A pointer to the address data. This must be at least as * long as the size specified in RAIL_ConfigAddressFilter(). The first byte, * value[0], will be compared to the first byte received over the air for this * address field. * @param[in] enable A boolean to indicate whether this address should be * enabled immediately. * @return Status code indicating success of the function call. * * This function loads the given address into hardware for filtering and * starts filtering if you set the enable parameter to true. Otherwise, * call RAIL_EnableAddressFilterAddress() to turn it on later. */ RAIL_Status_t RAIL_SetAddressFilterAddress(RAIL_Handle_t railHandle, uint8_t field, uint8_t index, const uint8_t *value, bool enable); /** * Enables address filtering for the specified address. * * @param[in] railHandle A RAIL instance handle. * @param[in] enable An argument to indicate whether or not to enable address * filtering. * @param[in] field Indicates an address for the address. * @param[in] index Indicates a match entry in the given field you want to enable. * @return Status code indicating success of the function call. */ RAIL_Status_t RAIL_EnableAddressFilterAddress(RAIL_Handle_t railHandle, bool enable, uint8_t field, uint8_t index); /** @} */ // end of group Address_Filtering /** @} */ // end of group Receive /****************************************************************************** * Auto-ACKing *****************************************************************************/ /// @addtogroup Auto_Ack Auto-ACK /// @brief APIs for configuring auto-ACK functionality /// /// These APIs are used to configure the radio for automatic acknowledgment /// features. Auto-ACK inherently changes how the underlying state machine /// behaves so users should not modify RAIL_SetRxTransitions() and /// RAIL_SetTxTransitions() while using auto-ACK features. /// /// @code{.c} /// // Go to RX after ACK operation. /// RAIL_AutoAckConfig_t autoAckConfig = { /// .enable = true, /// .ackTimeout = 1000, /// // "error" param ignored /// .rxTransitions = { RAIL_RF_STATE_RX, RAIL_RF_STATE_RX}, /// // "error" param ignored /// .txTransitions = { RAIL_RF_STATE_RX, RAIL_RF_STATE_RX} /// }; /// /// RAIL_Status_t status = RAIL_ConfigAutoAck(railHandle, &autoAckConfig); /// /// uint8_t ackData[] = {0x05, 0x02, 0x10, 0x00}; /// /// RAIL_Status_t status = RAIL_WriteAutoAckFifo(ackData, sizeof(ackData)); /// @endcode /// /// The acknowledgment transmits based on the frame format configured via /// the Radio Configurator. For example, if the frame format is using a variable /// length scheme, the ACK will be sent according to that scheme. If a 10-byte /// packet is loaded into the ACK, but the variable length field of the ACK /// payload specifies a length of 5, only 5 bytes will transmit for the ACK. /// The converse is also true, if the frame length is configured to be a fixed /// 10-byte packet but only 5 bytes are loaded into the ACK buffer, a TX /// underflow occurs during the ACK transmit. /// /// Unlike in non-auto-ACK mode, auto-ACK mode will always return to a single /// state after all ACK sequences complete, regardless of whether /// the ACK was successfully received/sent or not. See the documentation /// of \ref RAIL_ConfigAutoAck for configuration information. To /// suspend automatic acknowledgment of a series of packets after transmit /// or receive call RAIL_PauseTxAutoAck(true) and resume by calling /// RAIL_PauseRxAutoAck(true). /// When auto-ACKing is paused, after receiving or transmitting (also /// regardless of success) a packet, the radio transitions to the same single /// state it always defaults to while ACKing. To return to /// normal state transition logic outside of ACKing, call /// RAIL_ConfigAutoAck with the "enable" field false and specify the /// desired transitions in the rxTransitions and txTransitions fields. /// To get out of a paused state and resume auto-ACKing, call /// RAIL_PauseTxAutoAck(false) or RAIL_PauseRxAutoAck(false). /// /// Applications can cancel the transmission of an ACK with /// RAIL_CancelAutoAck(). Conversely, applications can control if a transmit /// operation should wait for an ACK after transmitting by using /// the \ref RAIL_TX_OPTION_WAIT_FOR_ACK option. /// /// When \ref Antenna_Control is used for multiple antennas, ACKs are /// transmitted on the antenna that was selected to receive the packet /// being acknowledged. When receiving an ACK, the /// \ref RAIL_RxOptions_t antenna options are used just like for any other /// receive. /// /// If the ACK payload is dynamic, the application must call /// RAIL_WriteAutoAckFifo() with the appropriate ACK payload after the /// application processes the receive. RAIL can auto-ACK from the normal /// transmit buffer if RAIL_UseTxFifoForAutoAck() is called before the radio /// transmits the ACK. Ensure the transmit buffer contains data loaded by /// RAIL_WriteTxFifo(). /// /// Standard-based protocols that contain auto-ACK functionality are normally /// configured in the protocol-specific configuration function. For example, /// RAIL_IEEE802154_Init() provides auto-ACK configuration parameters in \ref /// RAIL_IEEE802154_Config_t and should only be configured through that /// function. It is not advisable to call both RAIL_IEEE802154_Init() and /// RAIL_ConfigAutoAck(). However, ACK modification functions are still valid to /// use with protocol-specific ACKs. To cancel an IEEE 802.15.4 ACK transmit, use /// RAIL_CancelAutoAck(). /// /// @{ /// Configures and enables automatic acknowledgment. /// /// @param[in] railHandle A RAIL instance handle. /// @param[in] config Auto-ACK configuration structure. /// @return Status code indicating success of the function call. /// /// Configures the RAIL state machine to for hardware-accelerated automatic /// acknowledgment. ACK timing parameters are defined in the configuration /// structure. /// /// While auto-ACKing is enabled, do not call the following RAIL functions: /// - RAIL_SetRxTransitions() /// - RAIL_SetTxTransitions() /// /// Note, that if you are enabling auto-ACK (i.e., "enable" field is true) /// The "error" fields of rxTransitions and txTransitions are ignored. /// After all ACK sequences, (success or fail) the state machine will return /// the radio to the "success" state. If you need information about the /// actual success of the ACK sequence, use RAIL events such as /// \ref RAIL_EVENT_TXACK_PACKET_SENT to make sure an ACK was sent, or /// \ref RAIL_EVENT_RX_ACK_TIMEOUT to make sure that an ACK was received /// within the specified timeout. /// /// To set a certain turnaround time (i.e., txToRx and rxToTx /// in \ref RAIL_StateTiming_t), make txToRx lower than /// desired to ensure you get to RX in time to receive the ACK. /// Silicon Labs recommends setting 10 us lower than desired: /// /// @code{.c} /// void setAutoAckStateTimings() /// { /// RAIL_StateTiming_t timings; /// /// // User is already in auto-ACK and wants a turnaround of 192 us. /// timings.rxToTx = 192; /// timings.txToRx = 192 - 10; /// /// // Set other fields of timings... /// timings.idleToRx = 100; /// timings.idleToTx = 100; /// timings.rxSearchTimeout = 0; /// timings.txToRxSearchTimeout = 0; /// /// RAIL_SetStateTiming(railHandle, &timings); /// } /// @endcode /// /// As opposed to an explicit "Disable" API, set the "enable" /// field of the RAIL_AutoAckConfig_t to false. Then, auto-ACK will be /// disabled and state transitions will be returned to the values set /// in \ref RAIL_AutoAckConfig_t. When disabling, the "ackTimeout" field /// isn't used. /// /// @note: Auto-ACKing may not be enabled while RX Channel Hopping is enabled. /// RAIL_Status_t RAIL_ConfigAutoAck(RAIL_Handle_t railHandle, const RAIL_AutoAckConfig_t *config); /** * Returns the enable status of the auto-ACK feature. * * @param[in] railHandle A RAIL instance handle. * @return true if auto-ACK is enabled, false if disabled. */ bool RAIL_IsAutoAckEnabled(RAIL_Handle_t railHandle); /** * Loads the auto-ACK buffer with ACK data. * * @param[in] railHandle A RAIL instance handle. * @param[in] ackData A pointer to ACK data to transmit. * @param[in] ackDataLen The number of bytes in ACK data. * @return Status code indicating success of the function call. * * If the ACK buffer is available for updates, load the ACK buffer with data. */ RAIL_Status_t RAIL_WriteAutoAckFifo(RAIL_Handle_t railHandle, const uint8_t *ackData, uint8_t ackDataLen); /** * Pauses/resumes RX auto-ACK functionality. * * @param[in] railHandle A RAIL instance handle. * @param[in] pause Pause or resume RX auto-ACKing. * @return void. * * When RX auto-ACKing is paused, the radio transitions to default * state after receiving a packet and does not transmit an ACK. * When RX auto-ACK is resumed, the radio resumes automatically ACKing * every successfully received packet. */ void RAIL_PauseRxAutoAck(RAIL_Handle_t railHandle, bool pause); /** * Returns whether the RX auto-ACK is paused. * * @param[in] railHandle A RAIL instance handle. * @return true if RX auto-ACK is paused, false if not paused. */ bool RAIL_IsRxAutoAckPaused(RAIL_Handle_t railHandle); /** * Pauses/resumes TX auto-ACK functionality. * * @param[in] railHandle A RAIL instance handle. * @param[in] pause Pause or resume TX auto-ACKing. * @return void. * * When TX auto-ACKing is paused, the radio transitions to a default * state after transmitting a packet and does not wait for an ACK. When TX * auto-ACK is resumed, the radio resumes automatically waiting for * an ACK after a successful transmit. */ void RAIL_PauseTxAutoAck(RAIL_Handle_t railHandle, bool pause); /** * Returns whether the TX auto-ACK is paused. * * @param[in] railHandle A RAIL instance handle. * @return true if TX auto-ACK is paused, false if not paused. */ bool RAIL_IsTxAutoAckPaused(RAIL_Handle_t railHandle); /** * Modifies the upcoming ACK to use the TX Buffer. * * @param[in] railHandle A RAIL instance handle. * @return Status code indicating success of the function call. The call will * fail if it is too late to modify the outgoing ACK. * * This function allows the application to use the normal TX buffer as the data * source for the upcoming ACK. The ACK modification to use the TX buffer only * applies to one ACK transmission. * * This function only returns true if the following conditions are met: * - Radio has not already decided to use the ACK buffer AND * - Radio is either looking for sync, receiving the packet after sync, or in * the Rx2Tx turnaround before the ACK is sent. */ RAIL_Status_t RAIL_UseTxFifoForAutoAck(RAIL_Handle_t railHandle); /** * Cancels the upcoming ACK. * * @param[in] railHandle A RAIL instance handle. * @return Status code indicating success of the function call. This call will * fail if it is too late to modify the outgoing ACK. * * This function allows the application to cancel the upcoming automatic * acknowledgment. * * This function only returns true if the following conditions are met: * - Radio has not already decided to transmit the ACK AND * - Radio is either looking for sync, receiving the packet after sync or in * the Rx2Tx turnaround before the ACK is sent. */ RAIL_Status_t RAIL_CancelAutoAck(RAIL_Handle_t railHandle); /** * Returns whether the radio is currently waiting for an ACK. * * @param[in] railHandle A RAIL instance handle. * @return True if radio is waiting for ACK, false if radio is not waiting for * an ACK. * * This function allows the application to query whether the radio is currently * waiting for an ACK after a transmit operation. */ bool RAIL_IsAutoAckWaitingForAck(RAIL_Handle_t railHandle); /** @} */ // end of group Auto_Ack /****************************************************************************** * Calibration *****************************************************************************/ /// @addtogroup Calibration /// @brief APIs for calibrating the radio /// @{ /// /// These APIs can be used to calibrate the radio. The RAIL library /// determines which calibrations are necessary. Calibrations can /// be enabled/disabled with the RAIL_CalMask_t parameter. /// /// Some calibrations produce values that can be saved and reapplied to /// avoid repeating the calibration process. /// /// Calibrations can either be run with \ref RAIL_Calibrate, or with the /// individual chip-specific calibration routines. An example for running code /// with \ref RAIL_Calibrate looks like: /// /// @code{.c} /// static RAIL_CalValues_t calValues = RAIL_CALVALUES_UNINIT; /// /// void RAILCb_Event(RAIL_Handle_t railHandle, RAIL_Events_t events) { /// // Omitting other event handlers /// if (events & RAIL_EVENT_CAL_NEEDED) { /// // Run all pending calibrations, and save the results /// RAIL_Calibrate(railHandle, &calValues, RAIL_CAL_ALL_PENDING); /// } /// } /// @endcode /// /// Alternatively, if the image rejection calibration for your chip can be /// determined ahead of time, such as by running the calibration on a separate /// firmware image on each chip, the following calibration process will /// result in smaller code. /// /// @code{.c} /// static uint32_t imageRejection = IRCAL_VALUE; /// /// void RAILCb_Event(RAIL_Handle_t railHandle, RAIL_Events_t events) { /// // Omitting other event handlers /// if (events & RAIL_EVENT_CAL_NEEDED) { /// RAIL_CalMask_t pendingCals = RAIL_GetPendingCal(railHandle); /// // Disable the radio if we have to do an offline calibration /// if (pendingCals & RAIL_CAL_TEMP_VC0) { /// RAIL_CalibrateTemp(railHandle); /// } /// if (pendingCals & RAIL_CAL_ONETIME_IRCAL) { /// RAIL_ApplyIrCalibration(railHandle, imageRejection); /// } /// } /// } /// @endcode /** * Initializes RAIL calibration. * * @param[in] railHandle A RAIL instance handle. * @param[in] calEnable A bitmask that indicates which calibrations * to enable for a callback notification. * The exact meaning of these bits is chip-specific. * @return Status code indicating success of the function call. * * Calibration initialization provides the calibration settings that * correspond to the current radio configuration. */ RAIL_Status_t RAIL_ConfigCal(RAIL_Handle_t railHandle, RAIL_CalMask_t calEnable); /** * Starts the calibration process. * * @param[in] railHandle A RAIL instance handle. * @param[in,out] calValues A structure of calibration values to apply. * If a valid calibration structure is provided and the structure * contains valid calibration values, those values will be applied to the * hardware and the RAIL library will cache those values for use again later. * If a valid calibration structure is provided and the structure * contains a calibration value of \ref RAIL_CAL_INVALID_VALUE for the * desired calibration, the desired calibration will run, the calibration * values structure will be updated with a valid calibration value, and the * RAIL library will cache that value for use again later. * If a NULL pointer is provided, the desired calibration will run * and the RAIL library will cache that value for use again later. However, * the valid calibration value will not be returned to the application. * @param[in] calForce A mask to force specific calibration(s) to execute. * To run all pending calibrations, use the value \ref RAIL_CAL_ALL_PENDING. * Only the calibrations specified will run, even if not enabled during * initialization. * @return Status code indicating success of the function call. * * If calibrations were performed previously and the application saves the * calibration values (i.e., call this function with a calibration values * structure containing calibration values of \ref RAIL_CAL_INVALID_VALUE * before a reset), the application can later bypass the time it would normally * take to recalibrate hardware by reusing previous calibration values (i.e., * call this function with a calibration values structure containing valid * calibration values after a reset). * * If multiple protocols are used, this function will return * \ref RAIL_STATUS_INVALID_STATE if it is called and the given railHandle is * not active. The caller must attempt to re-call this function later. * * @note Instead of this function, consider using the individual chip-specific * functions. Using the individual functions will allow for better * dead-stripping if not all calibrations are run. * @note Some calibrations should only be executed when the radio is IDLE. See * chip-specific documentation for more details. */ RAIL_Status_t RAIL_Calibrate(RAIL_Handle_t railHandle, RAIL_CalValues_t *calValues, RAIL_CalMask_t calForce); /** * Returns the current set of pending calibrations. * * @param[in] railHandle A RAIL instance handle. * @return A mask of all pending calibrations that the user has been asked to * perform. * * This function returns a full set of pending calibrations. The only way * to clear pending calibrations is to perform them using the \ref * RAIL_Calibrate() API with the appropriate list of calibrations. */ RAIL_CalMask_t RAIL_GetPendingCal(RAIL_Handle_t railHandle); /** * Enables/disables the PA calibration. * * @param[in] enable Enables/disables the PA calibration. * @return void. * * Enabling will ensure that the PA power remains constant chip-to-chip. * By default, this feature is disabled after reset. * * @note This function should be called before \ref RAIL_ConfigTxPower() if this * feature is desired. */ void RAIL_EnablePaCal(bool enable); /** @} */ // end of group Calibration /****************************************************************************** * RF Sense Structures *****************************************************************************/ /** * @addtogroup Rf_Sense RF Sense * @{ */ /** * Starts/stops the RF Sense functionality for use during low-energy sleep modes. * * @param[in] railHandle A RAIL instance handle. * @param[in] band The frequency band(s) on which to sense the RF energy. * To stop RF Sense, specify \ref RAIL_RFSENSE_OFF. * @param[in] senseTime The time (in microseconds) the RF energy must be * continually detected to be considered "sensed". * @param[in] cb \ref RAIL_RfSense_CallbackPtr_t is called when the RF is * sensed. Set null if polling via \ref RAIL_IsRfSensed(). * @return The actual senseTime used, which may be different than * requested due to limitations of the hardware. If 0, RF sense was * disabled or could not be enabled (no callback will be issued). * * The EFR32 has the ability to sense the presence of RF Energy above -20 dBm * within either or both the 2.4 GHz and Sub-GHz bands and trigger an event * if that energy is continuously present for certain durations of time. * * @note After RF energy has been sensed, the RF Sense is automatically * disabled. RAIL_StartRfSense() must be called again to reactivate it. * * @note Packet reception is not guaranteed to work correctly once RF Sense is * enabled. To be safe, an application should turn this on only after idling * the radio to stop receive and turn it off before attempting to restart * receive. Since EM4 sleep causes the chip to come up through the reset * vector any wake from EM4 must also shut off RF Sense to ensure proper * receive functionality. * * @warning RF Sense functionality is only guaranteed from 0 to 85 degrees * Celsius. RF Sense should be disabled outside of this temperature range. */ RAIL_Time_t RAIL_StartRfSense(RAIL_Handle_t railHandle, RAIL_RfSenseBand_t band, RAIL_Time_t senseTime, RAIL_RfSense_CallbackPtr_t cb); /** * Checks if the RF was sensed. * * @param[in] railHandle A RAIL instance handle. * @return true if RF was sensed since the last call to \ref RAIL_StartRfSense. * False otherwise. * * This function is useful if \ref RAIL_StartRfSense is called with a null * callback. It is generally used after EM4 reboot but can be used any time. */ bool RAIL_IsRfSensed(RAIL_Handle_t railHandle); /** @} */ // end of group Rf_Sense /****************************************************************************** * RX Channel Hopping *****************************************************************************/ /** * @addtogroup Rx_Channel_Hopping RX Channel Hopping * @brief Hardware accelerated hopping between channels while waiting for a * packet in receive. * @{ * * Channel hopping provides a hardware accelerated method for * scanning across multiple channels quickly, as part of a receive protocol. * While it is possible to call \ref RAIL_StartRx on different channels, * back to back, and listen on many channels sequentially in that way, the * time it takes to switch channels with that method may be too long for some * protocols. This API pre-computes necessary channel change operations * for a given list of channels, so that the radio can move from channel * to channel much faster. Additionally, it leads to more succinct code * as channel changes will be done implicitly, without requiring numerous calls * to \ref RAIL_StartRx. Currently, while this feature is enabled, the radio * will hop channels in the given sequence each time it enters RX. * * The following code gives an example of how to use * the RX Channel Hopping API. * @code{.c} * * // The channel hopping buffer requires RAIL_CHANNEL_HOPPING_BUFFER_SIZE_PER_CHANNEL * // number of 32-bit words of overhead per channel, plus 3 words overall plus the * // twice the size of the radioConfigDeltaSubtract of the whole radio config, * // plus the twice the sum of the sizes of all the radioConfigDeltaAdds of * // all the channel hopping channels. * #define CHANNEL_HOPPING_NUMBER_OF_CHANNELS 4 * #define CHANNEL_HOPPING_BUFFER_SIZE do { \ * 3 + \ * (RAIL_CHANNEL_HOPPING_BUFFER_SIZE_PER_CHANNEL \ * * CHANNEL_HOPPING_NUMBER_OF_CHANNELS) + \ * 2 * (SIZEOF_UINT32_DELTA_SUBTRACT + \ * SIZEOF_UINT32_DELTA_ADD_0 + \ * SIZEOF_UINT32_DELTA_ADD_1 + \ * SIZEOF_UINT32_DELTA_ADD_2 + \ * SIZEOF_UINT32_DELTA_ADD_3) \ * } while (0) * * RAIL_RxChannelHoppingConfigEntry_t channelHoppingEntries[CHANNEL_HOPPING_NUMBER_OF_CHANNELS]; * uint32_t channelHoppingBuffer[CHANNEL_HOPPING_BUFFER_SIZE]; * * RAIL_RxChannelHoppingConfig_t channelHoppingConfig = { * .buffer = channelHoppingBuffer, * .bufferLength = CHANNEL_HOPPING_BUFFER_SIZE, * .numberOfChannels = CHANNEL_HOPPING_NUMBER_OF_CHANNELS, * .entries = channelHoppingEntries * }; * * channelHoppingEntries[0].channel = 1; * channelHoppingEntries[1].channel = 2; * channelHoppingEntries[2].channel = 3; * * RAIL_ConfigRxChannelHopping(railHandle, &channelHoppingConfig); * RAIL_EnableRxChannelHopping(railHandle, true, true) * @endcode */ /** * Configure RX Channel Hopping. * * @param[in] railHandle A RAIL instance handle. * @param[in] config Configuration parameters for RX Channel Hopping. * @return Status code indicating success of the function call. * * Configure Channel Hopping channels, conditions, and parameters. This * API must be called before RAIL_EnableChannelHopping. This API must * never be called while the radio is on with RX Duty Cycle or Channel * Hopping enabled. * * @note This feature/API is not supported on the EFR32XG1 family of chips. * * @note This feature/API is currently not supported in multiprotocol. * * @note Calling this function will overwrite any settings configured with * \ref RAIL_ConfigRxDutyCycle. */ RAIL_Status_t RAIL_ConfigRxChannelHopping(RAIL_Handle_t railHandle, RAIL_RxChannelHoppingConfig_t *config); /** * Enable RX Channel Hopping. * * @param[in] railHandle A RAIL instance handle. * @param[in] enable Enable (true) or disable (false) RX Channel Hopping. * @param[in] reset Start from the first channel of the channel hopping * sequence (true) or from wherever hopping left off last time the code * left RX. * @return Status code indicating success of the function call. * * Enable or disable Channel Hopping. Additionally, specify whether hopping * should be reset to start from the channel at index zero, or continue * from the channel last hopped to. The radio should not be on when * this API is called. RAIL_ConfigChannelHopping must be called before this * API is called. * * @note This feature/API is not supported on the EFR32XG1 family of chips. * * @note This feature/API is currently not supported in multiprotocol. * * @note RX Channel Hopping may not be enabled while auto-ACKing is enabled. * * @note Calling this function will overwrite any settings configured with * \ref RAIL_EnableRxDutyCycle. */ RAIL_Status_t RAIL_EnableRxChannelHopping(RAIL_Handle_t railHandle, bool enable, bool reset); /** * Get RSSI of one channel in the channel hopping sequence, during * channel hopping. * * @param[in] railHandle A RAIL instance handle. * @param[in] channelIndex Index in the channel hopping sequence of the * channel of interest * @return Latest RSSI for the channel at the specified index. * * @note This feature/API is not supported on the EFR32XG1 family of chips. * * @note This feature/API is currently not supported in multiprotocol. * * @note \ref RAIL_ConfigRxChannelHopping must be called successfully * before this API is called. */ int16_t RAIL_GetChannelHoppingRssi(RAIL_Handle_t railHandle, uint8_t channelIndex); /** * Configure RX duty cycle mode * * @param[in] railHandle A RAIL instance handle. * @param[in] config Configuration structure to specify duty cycle parameters. * @return Status code indicating success of the function call. * * Configure RX duty cycle mode. With this mode enabled, every time the radio * enters RX, it will duty cycle on and off to save power. The duty cycle * ratio can be altered dynamically and intelligently by the hardware by * staying on longer if a preamble or other packet segments are detected in * the air. This API must never be called while the radio is on with RX Duty * Cycle or Channel Hopping enabled. * * @note This feature/API is not supported on the EFR32XG1 family of chips. * * @note Calling this function will overwrite any settings configured with * \ref RAIL_ConfigRxChannelHopping. * * @note This feature/API is currently not supported in multiprotocol. */ RAIL_Status_t RAIL_ConfigRxDutyCycle(RAIL_Handle_t railHandle, const RAIL_RxDutyCycleConfig_t *config); /** * Enable RX duty cycle mode * * @param[in] railHandle A RAIL instance handle. * @param[in] enable Enable (true) or disable (false) RX Duty Cycling. * @return Status code indicating success of the function call. * * Enable or disable RX duty cycle mode. After this is called, the radio * will begin duty cycling each time it enters RX, based on the * configuration passed to \ref RAIL_ConfigRxDutyCycle. This API must not * be called while the radio is on. * * @note This feature/API is not supported on the EFR32XG1 family of chips. * * @note Calling this function will overwrite any settings configured with * \ref RAIL_EnableRxChannelHopping. * * @note This feature/API is currently not supported in multiprotocol. */ RAIL_Status_t RAIL_EnableRxDutyCycle(RAIL_Handle_t railHandle, bool enable); /** @} */ // end of group Rx_Channel_Hopping /****************************************************************************** * Multiprotocol-specific Functions *****************************************************************************/ /** * @addtogroup Multiprotocol * @brief Multiprotocol scheduler APIs to support multiple time-sliced PHYs. * @{ */ /** * Yields the radio to other configurations. * * @param[in] railHandle A RAIL instance handle. * @return void. * * This function is used to indicate that the previous transmit or scheduled * receive operation has completed. It must be used in multiprotocol RAIL since * the scheduler assumes that any transmit or receive operation that is started * can go on indefinitely based on state transitions and your protocol. * RAIL will not allow a lower priority tasks to run until this is called so it * can negatively impact performance of those protocols if this is omitted or * delayed. It is also possible to simply call the \ref RAIL_Idle() API to * both terminate the operation and idle the radio. In single-protocol RAIL * this API does nothing. * * See \ref rail_radio_scheduler_yield for more details. */ void RAIL_YieldRadio(RAIL_Handle_t railHandle); /** * Gets the status of the RAIL scheduler. * * @param[in] railHandle A RAIL instance handle. * @return \ref RAIL_SchedulerStatus_t status. * * This function can only be called from a callback context after the * \ref RAIL_EVENT_SCHEDULER_STATUS event occurs. */ RAIL_SchedulerStatus_t RAIL_GetSchedulerStatus(RAIL_Handle_t railHandle); /** * Change the priority of a specified task type in multiprotocol. * * @param[in] railHandle A RAIL instance handle. * @param[in] priority Desired new priority for the railHandle's active task * @param[in] taskType Type of task whose priority should be updated * @return \ref RAIL_Status_t indicating success of the function call. * * While the application can use this function however it likes, a major use * case is being able to increase an infinite receive priority while receiving * a packet. In other words, a given RAIL_Handle_t can maintain a very low * priority background receive, but upon getting a * \ref RAIL_EVENT_RX_SYNC1_DETECT_SHIFT or * \ref RAIL_EVENT_RX_SYNC2_DETECT_SHIFT event, the app can call this function * to increase the background RX priority to lower the risk another protocol * might preempt during packet reception. */ RAIL_Status_t RAIL_SetTaskPriority(RAIL_Handle_t railHandle, uint8_t priority, RAIL_TaskType_t taskType); /** * Get time needed to switch between protocols. * * @return \ref RAIL_Time_t Time needed to switch between protocols. */ RAIL_Time_t RAIL_GetTransitionTime(void); /** * Set time needed to switch between protocols. * * @param[in] transitionTime Time needed to switch between protocols. */ void RAIL_SetTransitionTime(RAIL_Time_t transitionTime); /** @} */ // end of group Multiprotocol /****************************************************************************** * Diagnostic *****************************************************************************/ /** * @addtogroup Diagnostic * @brief APIs for diagnostic and test chip modes * @{ */ /** * Enables or disables direct mode for RAIL. * * @param[in] railHandle A RAIL instance handle. * @param[in] enable Whether or not to enable direct mode. * @return \ref RAIL_STATUS_NO_ERROR on success and an error code on failure. * * @warning This API configures fixed pins for TX data in, RX data out, * and RX clock out. There should be more control over these pins in the * future but they are currently fixed. Also, this API is not safe to * use in a true multiprotocol app. * * In this mode, packets are output and input directly to the radio via GPIO * and RAIL packet handling is ignored. On the EFR32, the DIN pin in TX is * EFR32_PC10, which corresponds to EXP_HEADER15/WSTKP12, and the DOUT pin in * RX is EFR32_PC11, which corresponds to EXP_HEADER16/WSTKP13. */ RAIL_Status_t RAIL_EnableDirectMode(RAIL_Handle_t railHandle, bool enable); /** * Sets the crystal tuning. * * @param[in] railHandle A RAIL instance handle. * @param[in] tune A chip-dependent crystal capacitor bank tuning parameter. * @return Status code indicating success of the function call. * * Tunes the crystal that the radio depends on to change the location of the * center frequency for transmitting and receiving. This function will only * succeed if the radio is idle at the time of the call. * * @note This function proportionally affects the entire chip's timing * across all its peripherals, including radio tuning and channel spacing. * A separate function, \ref RAIL_SetFreqOffset(), can be used to adjust * just the radio tuner without disturbing channel spacing or other chip * peripheral timing. */ RAIL_Status_t RAIL_SetTune(RAIL_Handle_t railHandle, uint32_t tune); /** * Gets the crystal tuning. * * @param[in] railHandle A RAIL instance handle. * @return A chip-dependent crystal capacitor bank tuning parameter. * * Retrieves the current tuning value used by the crystal that the radio * depends on. */ uint32_t RAIL_GetTune(RAIL_Handle_t railHandle); /** * Gets the frequency offset. * * @param[in] railHandle A RAIL instance handle. * @return Returns the measured frequency offset on a received packet. * The units are described in the \ref RAIL_FrequencyOffset_t * documentation. If this returns \ref RAIL_FREQUENCY_OFFSET_INVALID, * it was called while the radio wasn't active and there is no way * to get the frequency offset. * * Retrieves the measured frequency offset used during the previous * received packet, which includes the current radio frequency offset * (see \ref RAIL_SetFreqOffset()). If the chip has not been in RX, * it returns the nominal radio frequency offset. */ RAIL_FrequencyOffset_t RAIL_GetRxFreqOffset(RAIL_Handle_t railHandle); /** * Sets the nominal radio frequency offset. * * @param[in] railHandle A RAIL instance handle. * @param[in] freqOffset \ref RAIL_FrequencyOffset_t parameter (signed, 2's * complement). * @return Status code indicating success of the function call. * * This function is used to adjust the radio's tuning frequency slightly up or down. * It might be used in conjunction with \ref RAIL_GetRxFreqOffset() after * receiving a packet from a peer to adjust the tuner to better match the * peer's tuned frequency. * * @note Unlike \ref RAIL_SetTune(), which affects the entire chip's * timing including radio tuning and channel spacing, this function * only affects radio tuning without disturbing channel spacing or * other chip peripheral timing. */ RAIL_Status_t RAIL_SetFreqOffset(RAIL_Handle_t railHandle, RAIL_FrequencyOffset_t freqOffset); /** * Starts transmitting a stream on a certain channel. * * @param[in] railHandle A RAIL instance handle. * @param[in] channel A channel on which to emit a stream. * @param[in] mode Choose the stream mode (PN9, and so on). * @return Status code indicating success of the function call. * * Begins streaming onto the given channel. The sources can either be an * unmodulated carrier wave or an encoded stream of bits from a PN9 source. * All ongoing radio operations will be stopped before transmission begins. */ RAIL_Status_t RAIL_StartTxStream(RAIL_Handle_t railHandle, uint16_t channel, RAIL_StreamMode_t mode); /** * Stops stream transmission. * * @param[in] railHandle A RAIL instance handle. * @return Status code indicating success of the function call. * * Halts the transmission started by RAIL_StartTxStream(). */ RAIL_Status_t RAIL_StopTxStream(RAIL_Handle_t railHandle); /** * Configures the verification of radio memory contents. * * @param[in] railHandle A RAIL instance handle. * @param[in,out] configVerify A configuration structure made available to * RAIL to perform radio state verification. This structure must be * allocated in application global read-write memory. RAIL may modify * fields within or referenced by this structure during its operation. * @param[in] radioConfig A pointer to a radioConfig that is to be used as a * white list for verifying memory contents. * @param[in] cb A callback that notifies the application of a mismatch in * expected vs actual memory contents. A NULL parameter may be passed in * if a callback is not provided by the application. * @return \ref RAIL_STATUS_NO_ERROR if setup of the verification feature * successfully occurred. * \ref RAIL_STATUS_INVALID_PARAMETER is returned if the provided railHandle * or configVerify structures are invalid. */ RAIL_Status_t RAIL_ConfigVerification(RAIL_Handle_t railHandle, RAIL_VerifyConfig_t *configVerify, const uint32_t *radioConfig, RAIL_VerifyCallbackPtr_t cb); /** * Verifies radio memory contents. * * @param[in,out] configVerify A configuration structure made available to * RAIL to perform radio state verification. This structure must be * allocated in application global read-write memory. RAIL may modify * fields within or referenced by this structure during its operation. * @param[in] durationUs The duration (in microseconds) for how long memory * verification should occur before returning to the application. A value of * RAIL_VERIFY_DURATION_MAX indicates that all memory contents should be * verified before returning to the application. * @param[in] restart This flag only has meaning if a previous call of this * function returned \ref RAIL_STATUS_SUSPENDED. By restarting (true), the * verification process starts over from the beginning, or by resuming * where verification left off after being suspended (false), verification * can proceed towards completion. * @return \ref RAIL_STATUS_NO_ERROR if the contents of all applicable * memory locations have been verified. * \ref RAIL_STATUS_SUSPENDED is returned if the provided test duration * expired but the time was not sufficient to verify all memory contents. * By calling \ref RAIL_Verify again, further verification will commence. * \ref RAIL_STATUS_INVALID_PARAMETER is returned if the provided * verifyConfig structure pointer is not configured for use by the active * RAIL handle. * \ref RAIL_STATUS_INVALID_STATE is returned if any of the verified * memory contents are different from their reference values. */ RAIL_Status_t RAIL_Verify(RAIL_VerifyConfig_t *configVerify, uint32_t durationUs, bool restart); /** @} */ // end of group Diagnostic #ifndef DOXYGEN_SHOULD_SKIP_THIS /****************************************************************************** * Debug *****************************************************************************/ /** * @addtogroup Debug * @brief APIs for debugging * @{ */ /** * Configures the debug mode for the radio library. Do not use this function * unless instructed by Silicon Labs. * @param[in] railHandle A RAIL instance handle. * @param[in] debugMode Debug mode to enter. * @return Status code indicating success of the function call. */ RAIL_Status_t RAIL_SetDebugMode(RAIL_Handle_t railHandle, uint32_t debugMode); /** * Returns the debug mode for the radio library. Do not use this function * unless instructed by Silicon Labs. * @param[in] railHandle A RAIL instance handle. * @return Debug mode for the radio library. */ uint32_t RAIL_GetDebugMode(RAIL_Handle_t railHandle); /** * Overrides the radio base frequency. * * @param[in] railHandle A RAIL instance handle. * @param[in] freq A desired frequency in Hz. * @return Status code indicating success of the function call. * * Sets the radio to transmit at the frequency given. This function can only * be used while in \ref RAIL_DEBUG_MODE_FREQ_OVERRIDE. The given frequency * needs to be close to the base frequency of the current PHY. */ RAIL_Status_t RAIL_OverrideDebugFrequency(RAIL_Handle_t railHandle, uint32_t freq); /** @} */ // end of group Debug #endif//DOXYGEN_SHOULD_SKIP_THIS /****************************************************************************** * Assertion Callback *****************************************************************************/ /** * @addtogroup Assertions * @brief Callbacks called by assertions * * This assertion framework was implemented for the purpose of not only being * able to assert that certain conditions be true in a block of code, but also * to be able to handle them more appropriately. In previous implementations, * the behavior upon a failed assert would be to hang in a while(1) loop. * However, with the callback, each assert is given a unique error code so that * they can be handled on a more case-by-case basis. For documentation on each * of the errors, see the rail_assert_error_codes.h file. * RAIL_ASSERT_ERROR_MESSAGES[errorCode] gives the explanation of the error. * With asserts built into the library, customers can choose how to handle each * error inside the callback. * * @{ */ /** * Callback called upon failed assertion. * * @param[in] railHandle A RAIL instance handle. * @param[in] errorCode Value passed in by the calling assertion API indicating * the RAIL error that is indicated by the failing assertion. * @return void. */ void RAILCb_AssertFailed(RAIL_Handle_t railHandle, RAIL_AssertErrorCodes_t errorCode); /** @} */ // end of group Assertions /** @} */ // end of group RAIL_API #ifdef __cplusplus } #endif #endif // __RAIL_H__ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/radio/rail_lib/common/rail_assert_error_codes.h.
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/***************************************************************************//** * @file * @brief Definition of error codes that occur in rail for use in * RAILCb_AssertFailed. This file is purely informational and optional - * it need not be included even if rail_assert libraries are included. ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * The licensor of this software is Silicon Laboratories Inc. Your use of this * software is governed by the terms of Silicon Labs Master Software License * Agreement (MSLA) available at * www.silabs.com/about-us/legal/master-software-license-agreement. This * software is distributed to you in Source Code format and is governed by the * sections of the MSLA applicable to Source Code. * ******************************************************************************/ #ifndef __RAIL_ASSERT_ERROR_CODES_H__ #define __RAIL_ASSERT_ERROR_CODES_H__ #include "rail_types.h" /** * @addtogroup Assertions * @{ */ /** * Enumeration of all possible error codes from RAIL_ASSERT */ RAIL_ENUM_GENERIC(RAIL_AssertErrorCodes_t, uint32_t) { RAIL_ASSERT_FAILED_APPENDED_INFO_MISSING = 0, RAIL_ASSERT_FAILED_RX_FIFO_BYTES = 1, RAIL_ASSERT_FAILED_RX_FIFO_ZERO_BYTES_READ = 2, RAIL_ASSERT_FAILED_ILLEGAL_RXLEN_ENTRY_STATUS = 3, RAIL_ASSERT_FAILED_BAD_PACKET_LENGTH = 4, RAIL_ASSERT_FAILED_SYNTH_DIVCTRL_ENUM_CONVERSION_ERROR = 5, RAIL_ASSERT_FAILED_UNEXPECTED_STATE_RX_FIFO = 6, RAIL_ASSERT_FAILED_UNEXPECTED_STATE_RXLEN_FIFO = 7, RAIL_ASSERT_FAILED_UNEXPECTED_STATE_TX_FIFO = 8, RAIL_ASSERT_FAILED_UNEXPECTED_STATE_TXACK_FIFO = 9, RAIL_ASSERT_FAILED_PBUFFER_NOT_DEFINED = 10, RAIL_ASSERT_FAILED_INSUFFICIENT_BYTES_IN_RX_PACKET = 11, RAIL_ASSERT_FAILED_CLOCK_PRESCALER = 12, RAIL_ASSERT_FAILED_RTCC_POST_WAKEUP = 13, RAIL_ASSERT_FAILED_SYNTH_VCO_FREQUENCY = 14, RAIL_ASSERT_FAILED_RAC_STATE = 15, RAIL_ASSERT_FAILED_TO_BE_ASSIGNED = 16, // Placeholder. RAIL_ASSERT_FAILED_NESTED_SEQUENCER_LOCK = 17, RAIL_ASSERT_FAILED_RSSI_AVERAGE_DONE = 18, RAIL_ASSERT_FAILED_DFL_BITS_SIZE = 19, RAIL_ASSERT_FAILED_PROTIMER_RANDOM_SEED = 20, RAIL_ASSERT_FAILED_EFR32XG1_REGISTER_SIZE = 21, RAIL_ASSERT_FAILED_PROTIMER_CHANNEL = 22, RAIL_ASSERT_FAILED_TIMER_REQUIRES_WRAP = 23, RAIL_ASSERT_FAILED_BASECNTTOP = 24, RAIL_ASSERT_FAILED_DEPRECATED_LBTRETRY = 25, RAIL_ASSERT_FAILED_RTCC_SYNC_MISSED = 26, RAIL_ASSERT_FAILED_CLOCK_SOURCE_NOT_READY = 27, RAIL_ASSERT_FAILED_TIMINGS_INVALID = 28, RAIL_ASSERT_NULL_HANDLE = 29, RAIL_ASSERT_FAILED_SCHED_TIMER_NOT_RUNNING = 30, RAIL_ASSERT_FAILED_NO_ACTIVE_CONFIG = 31, RAIL_ASSERT_FAILED_NO_ACTIVE_HANDLE_SWITCH = 32, RAIL_ASSERT_FAILED_RFINIT = 33, RAIL_ASSERT_FAILED_NO_ACTIVE_HANDLE_SCHEDRX = 34, RAIL_ASSERT_FAILED_INVALID_HANDLE_SCHEDTX = 35, RAIL_ASSERT_FAILED_INACTIVE_HANDLE_SCHEDTX = 36, RAIL_ASSERT_FAILED_CONFIG_INDEX_INVALID = 37, RAIL_ASSERT_FAILED_NO_ACTIVE_HANDLE_SINGLEPROTOCOL = 38, RAIL_ASSERT_DEPRECATED_FUNCTION = 39, RAIL_ASSERT_MULTIPROTOCOL_NO_EVENT = 40, RAIL_ASSERT_FAILED_INVALID_INTERRUPT_ENABLED = 41, RAIL_ASSERT_CONVERSION_CURVES_NOT_INITIALIZED = 42, RAIL_ASSERT_DIVISION_BY_ZERO = 43, RAIL_ASSERT_CANT_USE_HARDWARE = 44, RAIL_ASSERT_NULL_PARAMETER = 45, RAIL_ASSERT_INVALID_TASK_TYPE = 46, RAIL_ASSERT_SMALL_SYNTH_RADIO_CONFIG_BUFFER = 47, RAIL_ASSERT_CHANNEL_HOPPING_BUFFER_TOO_SHORT = 48, RAIL_ASSERT_INVALID_MODULE_ACTION = 49, RAIL_ASSERT_CHANNEL_HOPPING_INVALID_RADIO_CONFIG = 50, RAIL_ASSERT_CHANNEL_CHANGE_FAILED = 51, RAIL_ASSERT_INVALID_REGISTER = 52, }; #ifndef DOXYGEN_SHOULD_SKIP_THIS // Self-referencing defines minimize compiler complaints when using RAIL_ENUM #define RAIL_ASSERT_FAILED_APPENDED_INFO_MISSING ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_APPENDED_INFO_MISSING) #define RAIL_ASSERT_FAILED_RX_FIFO_BYTES ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_RX_FIFO_BYTES) #define RAIL_ASSERT_FAILED_RX_FIFO_ZERO_BYTES_READ ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_RX_FIFO_ZERO_BYTES_READ) #define RAIL_ASSERT_FAILED_ILLEGAL_RXLEN_ENTRY_STATUS ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_ILLEGAL_RXLEN_ENTRY_STATUS) #define RAIL_ASSERT_FAILED_BAD_PACKET_LENGTH ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_BAD_PACKET_LENGTH) #define RAIL_ASSERT_FAILED_SYNTH_DIVCTRL_ENUM_CONVERSION_ERROR ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_SYNTH_DIVCTRL_ENUM_CONVERSION_ERROR) #define RAIL_ASSERT_FAILED_UNEXPECTED_STATE_RX_FIFO ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_UNEXPECTED_STATE_RX_FIFO) #define RAIL_ASSERT_FAILED_UNEXPECTED_STATE_RXLEN_FIFO ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_UNEXPECTED_STATE_RXLEN_FIFO) #define RAIL_ASSERT_FAILED_UNEXPECTED_STATE_TX_FIFO ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_UNEXPECTED_STATE_TX_FIFO) #define RAIL_ASSERT_FAILED_UNEXPECTED_STATE_TXACK_FIFO ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_UNEXPECTED_STATE_TXACK_FIFO) #define RAIL_ASSERT_FAILED_PBUFFER_NOT_DEFINED ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_PBUFFER_NOT_DEFINED) #define RAIL_ASSERT_FAILED_INSUFFICIENT_BYTES_IN_RX_PACKET ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_INSUFFICIENT_BYTES_IN_RX_PACKET) #define RAIL_ASSERT_FAILED_CLOCK_PRESCALER ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_CLOCK_PRESCALER) #define RAIL_ASSERT_FAILED_RTCC_POST_WAKEUP ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_RTCC_POST_WAKEUP) #define RAIL_ASSERT_FAILED_SYNTH_VCO_FREQUENCY ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_SYNTH_VCO_FREQUENCY) #define RAIL_ASSERT_FAILED_RAC_STATE ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_RAC_STATE) #define RAIL_ASSERT_FAILED_NESTED_SEQUENCER_LOCK ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_NESTED_SEQUENCER_LOCK) #define RAIL_ASSERT_FAILED_RSSI_AVERAGE_DONE ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_RSSI_AVERAGE_DONE) #define RAIL_ASSERT_FAILED_DFL_BITS_SIZE ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_DFL_BITS_SIZE) #define RAIL_ASSERT_FAILED_PROTIMER_RANDOM_SEED ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_PROTIMER_RANDOM_SEED) #define RAIL_ASSERT_FAILED_EFR32XG1_REGISTER_SIZE ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_EFR32XG1_REGISTER_SIZE) #define RAIL_ASSERT_FAILED_PROTIMER_CHANNEL ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_PROTIMER_CHANNEL) #define RAIL_ASSERT_FAILED_TIMER_REQUIRES_WRAP ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_TIMER_REQUIRES_WRAP) #define RAIL_ASSERT_FAILED_BASECNTTOP ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_BASECNTTOP) #define RAIL_ASSERT_FAILED_DEPRECATED_LBTRETRY ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_DEPRECATED_LBTRETRY) #define RAIL_ASSERT_FAILED_RTCC_SYNC_MISSED ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_RTCC_SYNC_MISSED) #define RAIL_ASSERT_FAILED_CLOCK_SOURCE_NOT_READY ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_CLOCK_SOURCE_NOT_READY) #define RAIL_ASSERT_FAILED_TIMINGS_INVALID ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_TIMINGS_INVALID) #define RAIL_ASSERT_NULL_HANDLE ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_NULL_HANDLE) #define RAIL_ASSERT_FAILED_SCHED_TIMER_NOT_RUNNING ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_SCHED_TIMER_NOT_RUNNING) #define RAIL_ASSERT_FAILED_NO_ACTIVE_CONFIG ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_NO_ACTIVE_CONFIG) #define RAIL_ASSERT_FAILED_NO_ACTIVE_HANDLE_SWITCH ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_NO_ACTIVE_HANDLE_SWITCH) #define RAIL_ASSERT_FAILED_RFINIT ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_RFINIT) #define RAIL_ASSERT_FAILED_NO_ACTIVE_HANDLE_SCHEDRX ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_NO_ACTIVE_HANDLE_SCHEDRX) #define RAIL_ASSERT_FAILED_INVALID_HANDLE_SCHEDTX ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_INVALID_HANDLE_SCHEDTX) #define RAIL_ASSERT_FAILED_INACTIVE_HANDLE_SCHEDTX ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_INACTIVE_HANDLE_SCHEDTX) #define RAIL_ASSERT_FAILED_CONFIG_INDEX_INVALID ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_CONFIG_INDEX_INVALID) #define RAIL_ASSERT_FAILED_NO_ACTIVE_HANDLE_SINGLEPROTOCOL ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_NO_ACTIVE_HANDLE_SINGLEPROTOCOL) #define RAIL_ASSERT_DEPRECATED_FUNCTION ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_DEPRECATED_FUNCTION) #define RAIL_ASSERT_MULTIPROTOCOL_NO_EVENT ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_MULTIPROTOCOL_NO_EVENT) #define RAIL_ASSERT_FAILED_INVALID_INTERRUPT_ENABLED ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_INVALID_INTERRUPT_ENABLED) #define RAIL_ASSERT_CONVERSION_CURVES_NOT_INITIALIZED ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_CONVERSION_CURVES_NOT_INITIALIZED) #define RAIL_ASSERT_DIVISION_BY_ZERO ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_DIVISION_BY_ZERO) #define RAIL_ASSERT_CANT_USE_HARDWARE ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_CANT_USE_HARDWARE) #define RAIL_ASSERT_NULL_PARAMETER ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_NULL_PARAMETER) #define RAIL_ASSERT_INVALID_TASK_TYPE ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_INVALID_TASK_TYPE) #define RAIL_ASSERT_SMALL_SYNTH_RADIO_CONFIG_BUFFER ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_SMALL_SYNTH_RADIO_CONFIG_BUFFER) #define RAIL_ASSERT_CHANNEL_HOPPING_BUFFER_TOO_SHORT ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_CHANNEL_HOPPING_BUFFER_TOO_SHORT) #define RAIL_ASSERT_INVALID_MODULE_ACTION ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_INVALID_MODULE_ACTION) #define RAIL_ASSERT_CHANNEL_HOPPING_INVALID_RADIO_CONFIG ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_CHANNEL_HOPPING_INVALID_RADIO_CONFIG) #define RAIL_ASSERT_CHANNEL_CHANGE_FAILED ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_CHANNEL_CHANGE_FAILED) #define RAIL_ASSERT_INVALID_REGISTER ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_INVALID_REGISTER) #endif//DOXYGEN_SHOULD_SKIP_THIS /// Use this define to create an array of error messages that map to the codes /// in \ref RAIL_AssertErrorCodes_t. You can use these to print slightly more /// detailed error strings related to a particular assert error code if desired. /// For example, you could implement your assert failed callback as follows to /// make use of this. /// /// @code{.c} /// void RAILCb_AssertFailed(RAIL_Handle_t railHandle, uint32_t errorCode) /// { /// static const char* railErrorMessages[] = RAIL_ASSERT_ERROR_MESSAGES; /// const char *errorMessage = "Unknown"; /// /// // If this error code is within the range of known error messages then use /// // the appropriate error message. /// if (errorCode < (sizeof(railErrorMessages) / sizeof(char*))) { /// errorMessage = railErrorMessages[errorCode]; /// } /// printf(errorMessage); /// /// // Reset the chip since an assert is a fatal error /// NVIC_SystemReset(); /// } /// @endcode /// #define RAIL_ASSERT_ERROR_MESSAGES { \ /* 0*/ "Appended info missing from Rx packet", \ /* 1*/ "Payload bytes missing from Rx packet", \ /* 2*/ "Error reading back packet payload", \ /* 3*/ "Receive fifo entry has invalid status", \ /* 4*/ "Receive fifo entry bad packet length", \ /* 5*/ "Unable to configure radio for IR calibration", \ /* 6*/ "Reached unexpected state while handling Rx fifo events", \ /* 7*/ "Reached unexpected state while handling RXLEN fifo events", \ /* 8*/ "Reached unexpected state while handling Tx fifo events", \ /* 9*/ "Reached unexpected state while handling Tx ACK fifo events", \ /*10*/ "No memory to store receive packet", \ /*11*/ "Packet length longer than the receive FIFO size", \ /*12*/ "Invalid radio clock prescaler", \ /*13*/ "Error synchronizing the RAIL timebase after sleep", \ /*14*/ "VCO frequency outside supported range", \ /*15*/ "Radio active while changing channels", \ /*16*/ "Unassigned error code", \ /*17*/ "Nested attempt to lock the sequencer", \ /*18*/ "RSSI averaging enabled without a valid callback", \ /*19*/ "Invalid dynamic frame length setting provided (dflBits)", \ /*20*/ "Unable to seed radio pseudo random number generator", \ /*21*/ "Timeout exceeds EFR32XG1 register size", \ /*22*/ "Invalid timer channel specified", \ /*23*/ "Timer value larger than RAIL timebase", \ /*24*/ "LBT config exceeds EFR32XG1 register size", \ /*25*/ "Deprecated CSMA/LBT retry callback unexpectedly called", \ /*26*/ "Could not synchronize RAIL timebase with the RTC", \ /*27*/ "Clock source not ready", \ /*28*/ "Attempted to set RAIL timings to invalid value", \ /*29*/ "NULL was supplied as a RAIL_Handle_t argument", \ /*30*/ "Scheduled timer not running", \ /*31*/ "No active config to switch from", \ /*32*/ "No active handle after switch", \ /*33*/ "RfInit failed to configure active state", \ /*34*/ "No active handle for scheduled rx", \ /*35*/ "Invalid handle for scheduled tx", \ /*36*/ "Inactive handle for scheduled tx", \ /*37*/ "Invalid config index to switch to", \ /*38*/ "No active handle for single protocol", \ /*39*/ "This function is deprecated and must not be called", \ /*40*/ "Multiprotocol task started with no event to run", \ /*41*/ "Invalid interrupt enabled", \ /*42*/ "Power conversion functions called before curves were initialized", \ /*43*/ "Division by zero", \ /*44*/ "Function cannot be called without access to the hardware", \ /*45*/ "Pointer parameter was passed as NULL", \ /*46*/ "Invalid task type passed to RAIL_SetTaskPriority", \ /*47*/ "Synth radio config buffer for channel hopping too small", \ /*48*/ "Buffer provided for RX Channel Hopping is too small", \ /*49*/ "Invalid action was attempted on a module", \ /*50*/ "The radio config for this channel is not compatible with channel hopping", \ /*51*/ "Channel change failed", \ /*52*/ "Attempted to read invalid register", \ } /** * @} */ #endif // __RAIL_ASSERT_ERROR_CODES_H__ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/radio/rail_lib/common/rail_types.h.
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/***************************************************************************//** * @file * @brief This file contains the type definitions for RAIL structures, enums, * and other types. ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * The licensor of this software is Silicon Laboratories Inc. Your use of this * software is governed by the terms of Silicon Labs Master Software License * Agreement (MSLA) available at * www.silabs.com/about-us/legal/master-software-license-agreement. This * software is distributed to you in Source Code format and is governed by the * sections of the MSLA applicable to Source Code. * ******************************************************************************/ #ifndef __RAIL_TYPES_H__ #define __RAIL_TYPES_H__ // Include standard type headers to help define structures #include <stdint.h> #include <stdbool.h> #include <stddef.h> #ifdef __cplusplus extern "C" { #endif #ifdef DOXYGEN_SHOULD_SKIP_THIS /// The RAIL library does not use enumerations because the ARM EABI leaves their /// size ambiguous, which causes problems if the application is built /// with different flags than the library. Instead, uint8_t typedefs /// are used in compiled code for all enumerations. For documentation purposes, this is /// converted to an actual enumeration since it's much easier to read in Doxygen. #define RAIL_ENUM(name) enum name /// This macro is a more generic version of the \ref RAIL_ENUM() macro that /// allows the size of the type to be overridden instead of forcing the use of /// a uint8_t. See \ref RAIL_ENUM() for more information about why RAIL enumerations /// are defined using these. #define RAIL_ENUM_GENERIC(name, type) enum name #else /// Define used for the RAIL library, which sets each enumeration to a uint8_t /// typedef and creates a named enumeration structure for the enumeration values. #define RAIL_ENUM(name) typedef uint8_t name; enum name##_enum #define RAIL_ENUM_GENERIC(name, type) typedef type name; enum name##_enum // For debugging, use the following define to turn this back into a proper enumeration // #define RAIL_ENUM(name) typedef enum name##_enum name; enum name##_enum #endif /** * @addtogroup RAIL_API * @{ */ /****************************************************************************** * General Structures *****************************************************************************/ /** * @addtogroup General * @{ */ /** * @struct RAIL_Version_t * @brief Contains RAIL Library Version Information. * It is filled in by RAIL_GetVersion(). */ typedef struct RAIL_Version { uint32_t hash; /**< Git hash */ uint8_t major; /**< Major number */ uint8_t minor; /**< Minor number */ uint8_t rev; /**< Revision number */ uint8_t build; /**< Build number */ uint8_t flags; /**< Build flags */ /** Boolean to indicate whether this is a multiprotocol library or not. */ bool multiprotocol; } RAIL_Version_t; /** * @typedef RAIL_Handle_t * @brief A handle of a RAIL instance, as returned from RAIL_Init(). */ typedef void *RAIL_Handle_t; /** * @enum RAIL_Status_t * @brief A status returned by many RAIL API calls indicating their success or * failure. */ RAIL_ENUM(RAIL_Status_t) { RAIL_STATUS_NO_ERROR, /**< RAIL function reports no error. */ RAIL_STATUS_INVALID_PARAMETER, /**< Call to RAIL function threw an error because of an invalid parameter. */ RAIL_STATUS_INVALID_STATE, /**< Call to RAIL function threw an error because it was called during an invalid radio state. */ RAIL_STATUS_INVALID_CALL, /**< RAIL function is called in an invalid order. */ RAIL_STATUS_SUSPENDED, /**< RAIL function did not finish in the allotted time. */ }; #ifndef DOXYGEN_SHOULD_SKIP_THIS // Self-referencing defines minimize compiler complaints when using RAIL_ENUM #define RAIL_STATUS_NO_ERROR ((RAIL_Status_t) RAIL_STATUS_NO_ERROR) #define RAIL_STATUS_INVALID_PARAMETER ((RAIL_Status_t) RAIL_STATUS_INVALID_PARAMETER) #define RAIL_STATUS_INVALID_STATE ((RAIL_Status_t) RAIL_STATUS_INVALID_STATE) #define RAIL_STATUS_INVALID_CALL ((RAIL_Status_t) RAIL_STATUS_INVALID_CALL) #define RAIL_STATUS_SUSPENDED ((RAIL_Status_t) RAIL_STATUS_SUSPENDED) #endif//DOXYGEN_SHOULD_SKIP_THIS /** * A pointer to init complete callback function * * @param[in] railHandle A handle for RAIL instance. * @return void. * */ typedef void (*RAIL_InitCompleteCallbackPtr_t)(RAIL_Handle_t railHandle); /** @} */ // end of group General /****************************************************************************** * System Timing Structures *****************************************************************************/ /** * @addtogroup System_Timing * @{ */ /** * @typedef RAIL_Time_t * @brief Time in microseconds */ typedef uint32_t RAIL_Time_t; /** * A pointer to the callback called when the RAIL timer expires. * * @param[in] cbArg The argument passed to the callback. * @return void. */ typedef void (*RAIL_TimerCallback_t)(RAIL_Handle_t cbArg); /** * @enum RAIL_TimeMode_t * @brief Specifies a time offset in RAIL APIs. * * Different APIs use the same constants and may provide more specifics about * how they're used but the general use for each is described below. */ RAIL_ENUM(RAIL_TimeMode_t) { /** * The time specified is an exact time in the RAIL timebase. The given * event should happen at exactly that time. If this time is already in the * past, an error is returned. Because the RAIL timebase wraps at 32 * bits, there is no real 'past'. Instead, any event greater than * 3/4 of the way into the future is considered to be in the past. */ RAIL_TIME_ABSOLUTE, /** * The time specified is relative to the current time. The event should occur * that many ticks in the future. Delays are only guaranteed at least as long * as the value specified. An overhead may occur between the time when the * API is called and when the delay starts. As a result, using this for * operations that must happen at an exact given time is not recommended. * For that, you must use \ref RAIL_TIME_ABSOLUTE delays. * * Note that, if you specify a delay 0, that event is triggered as soon as * possible. This is different than specifying an absolute time of now which * would return an error unless it was possible. */ RAIL_TIME_DELAY, /** * The specified time is invalid and should be ignored. For some APIs this * can also indicate that any previously stored delay should be invalidated * and disabled. */ RAIL_TIME_DISABLED, }; #ifndef DOXYGEN_SHOULD_SKIP_THIS // Self-referencing defines minimize compiler complaints when using RAIL_ENUM #define RAIL_TIME_ABSOLUTE ((RAIL_TimeMode_t) RAIL_TIME_ABSOLUTE) #define RAIL_TIME_DELAY ((RAIL_TimeMode_t) RAIL_TIME_DELAY) #define RAIL_TIME_DISABLED ((RAIL_TimeMode_t) RAIL_TIME_DISABLED) #endif//DOXYGEN_SHOULD_SKIP_THIS /// Forward declaration of RAIL_MultiTimer struct RAIL_MultiTimer; /** * @typedef RAIL_MultiTimerCallback_t * @brief Callback fired when timer expires * * @param[in] tmr A pointer to an expired timer. * @param[in] expectedTimeOfEvent An absolute time event fired. * @param[in] cbArg A user-supplied callback argument. */ typedef void (*RAIL_MultiTimerCallback_t)(struct RAIL_MultiTimer *tmr, RAIL_Time_t expectedTimeOfEvent, void *cbArg); /** * @struct RAIL_MultiTimer_t * @brief RAIL timer state structure * * This structure is filled out and maintained internally only. * The user/application should not alter any elements of this structure. */ typedef struct RAIL_MultiTimer { RAIL_Time_t absOffset; /**< Absolute time before the next event. */ RAIL_Time_t relPeriodic; /**< Relative, periodic time between events; 0 = timer is oneshot. */ RAIL_MultiTimerCallback_t callback; /**< A user callback. */ void *cbArg; /**< A user callback argument. */ struct RAIL_MultiTimer *next; /**< A pointer to the next soft timer structure. */ uint8_t priority; /**< A priority of the callback; 0 = highest priority; 255 = lowest. */ bool isRunning; /**< Indicates the timer is currently running. */ bool doCallback; /**< Indicates the callback needs to run. */ } RAIL_MultiTimer_t; /** * @enum RAIL_SleepConfig_t * @brief The configuration */ RAIL_ENUM(RAIL_SleepConfig_t) { RAIL_SLEEP_CONFIG_TIMERSYNC_DISABLED, /**< Disable timer sync before and after sleep. */ RAIL_SLEEP_CONFIG_TIMERSYNC_ENABLED, /**< Enable timer sync before and after sleep. */ }; #ifndef DOXYGEN_SHOULD_SKIP_THIS // Self-referencing defines minimize compiler complaints when using RAIL_ENUM #define RAIL_SLEEP_CONFIG_TIMERSYNC_DISABLED ((RAIL_SleepConfig_t) RAIL_SLEEP_CONFIG_TIMERSYNC_DISABLED) #define RAIL_SLEEP_CONFIG_TIMERSYNC_ENABLED ((RAIL_SleepConfig_t) RAIL_SLEEP_CONFIG_TIMERSYNC_ENABLED) #endif//DOXYGEN_SHOULD_SKIP_THIS /** * @enum RAIL_PacketTimePosition_t * @brief The available packet timestamp position choices */ RAIL_ENUM(RAIL_PacketTimePosition_t) { /** * Indicates that a timestamp is not to be or was not provided. * It is useful if the application doesn't care about packet timestamps * and doesn't want RAIL to spend time calculating one. */ RAIL_PACKET_TIME_INVALID = 0, /** * Requests the choice most expedient for RAIL to calculate, * which may depend on the radio and/or its configuration. * The actual choice would always be reflected in the timePosition * field of \ref RAIL_RxPacketDetails_t or \ref RAIL_TxPacketDetails_t * returned and would never be one of the _USED_TOTAL values. */ RAIL_PACKET_TIME_DEFAULT = 1, /** * Requests the timestamp corresponding to the first preamble bit * sent or received. * Indicates that timestamp did not require using totalPacketBytes. */ RAIL_PACKET_TIME_AT_PREAMBLE_START = 2, /** * Requests the timestamp corresponding to the first preamble bit * sent or received. * Indicates that timestamp did require using totalPacketBytes. */ RAIL_PACKET_TIME_AT_PREAMBLE_START_USED_TOTAL = 3, /** * Requests the timestamp corresponding to right after its last * SYNC word bit has been sent or received. * Indicates that timestamp did not require using totalPacketBytes. */ RAIL_PACKET_TIME_AT_SYNC_END = 4, /** * Requests the timestamp corresponding to right after its last * SYNC word bit has been sent or received. * Indicates that timestamp did require using totalPacketBytes. */ RAIL_PACKET_TIME_AT_SYNC_END_USED_TOTAL = 5, /** * Requests the timestamp corresponding to right after its last * bit has been sent or received. * Indicates that timestamp did not require using totalPacketBytes. */ RAIL_PACKET_TIME_AT_PACKET_END = 6, /** * Requests the timestamp corresponding to right after its last * bit has been sent or received. * Indicates that timestamp did require using totalPacketBytes. */ RAIL_PACKET_TIME_AT_PACKET_END_USED_TOTAL = 7, RAIL_PACKET_TIME_COUNT /**< A count of the choices in this enumeration. */ }; #ifndef DOXYGEN_SHOULD_SKIP_THIS // Self-referencing defines minimize compiler complaints when using RAIL_ENUM #define RAIL_PACKET_TIME_INVALID ((RAIL_PacketTimePosition_t) RAIL_PACKET_TIME_INVALID) #define RAIL_PACKET_TIME_DEFAULT ((RAIL_PacketTimePosition_t) RAIL_PACKET_TIME_DEFAULT) #define RAIL_PACKET_TIME_AT_PREAMBLE_START ((RAIL_PacketTimePosition_t) RAIL_PACKET_TIME_AT_PREAMBLE_START) #define RAIL_PACKET_TIME_AT_PREAMBLE_START_USED_TOTAL ((RAIL_PacketTimePosition_t) RAIL_PACKET_TIME_AT_PREAMBLE_START_USED_TOTAL) #define RAIL_PACKET_TIME_AT_SYNC_END ((RAIL_PacketTimePosition_t) RAIL_PACKET_TIME_AT_SYNC_END) #define RAIL_PACKET_TIME_AT_SYNC_END_USED_TOTAL ((RAIL_PacketTimePosition_t) RAIL_PACKET_TIME_AT_SYNC_END_USED_TOTAL) #define RAIL_PACKET_TIME_AT_PACKET_END ((RAIL_PacketTimePosition_t) RAIL_PACKET_TIME_AT_PACKET_END) #define RAIL_PACKET_TIME_AT_PACKET_END_USED_TOTAL ((RAIL_PacketTimePosition_t) RAIL_PACKET_TIME_AT_PACKET_END_USED_TOTAL) #define RAIL_PACKET_TIME_COUNT ((RAIL_PacketTimePosition_t) RAIL_PACKET_TIME_COUNT) #endif//DOXYGEN_SHOULD_SKIP_THIS /** * @struct RAIL_PacketTimeStamp_t * @brief Information needed to calculate and represent a packet timestamp. */ typedef struct RAIL_PacketTimeStamp { /** * Timestamp of the packet in the RAIL timebase. */ RAIL_Time_t packetTime; /** * A value specifying the total length in bytes of the packet for * use when calculating the packetTime requested by the timePosition * field. This should account for all bytes sent over the air after * the Preamble and Sync word(s) including CRC bytes. */ uint32_t totalPacketBytes; /** * A RAIL_PacketTimePosition_t value specifying the packet position * to return in the packetTime field. * If this is \ref RAIL_PACKET_TIME_DEFAULT, this field will be * updated with the actual position corresponding to the packetTime * value filled in by a call using this structure. */ RAIL_PacketTimePosition_t timePosition; } RAIL_PacketTimeStamp_t; /** @} */ // end of group System_Timing /****************************************************************************** * Multiprotocol Structures *****************************************************************************/ /** * @addtogroup Multiprotocol * @{ */ /** * @struct RAIL_SchedulerInfo_t * @brief A structure to hold information used by the scheduler. * * For multiprotocol versions of RAIL, this can be used to control how a receive * or transmit operation is run. It's not necessary in single-protocol applications. */ typedef struct RAIL_SchedulerInfo { /** * The scheduler priority to use for this operation. This priority is used to * preempt a long running lower-priority task to ensure higher-priority * operations complete in time. A lower numerical value represents a higher * logical priority meaning 0 is the highest priority and 255 is the lowest. */ uint8_t priority; /** * The amount of time in us that this operation can slip by into the future * and still be run. This time is relative to the start time which may be * the current time for relative transmits. If the scheduler can't start the * operation by this time, it will be considered a failure. */ RAIL_Time_t slipTime; /** * The transaction time in us for this operation. Since transaction times may * not be known exactly, use a minimum or an expected * guess for this time. The scheduler will use the value entered here to look * for overlaps between low-priority and high-priority tasks and attempt to * find a schedule where all tasks get to run. */ RAIL_Time_t transactionTime; } RAIL_SchedulerInfo_t; /** * @enum RAIL_SchedulerStatus_t * @brief Multiprotocol scheduler status returned by RAIL_GetSchedulerStatus(). */ RAIL_ENUM(RAIL_SchedulerStatus_t) { /** Multiprotocol scheduler reports no error. */ RAIL_SCHEDULER_STATUS_NO_ERROR, /** * The scheduler is disabled or the requested scheduler operation is * unsupported. */ RAIL_SCHEDULER_STATUS_UNSUPPORTED, /** * The scheduled event was started but was interrupted by a higher-priority * event before it could be completed. */ RAIL_SCHEDULER_STATUS_EVENT_INTERRUPTED, /** * This task could not be scheduled given its priority and the other tasks * running on the system. */ RAIL_SCHEDULER_STATUS_SCHEDULE_FAIL, /** * Calling the scheduled transmit function returned an error code. See * RAIL_StartScheduledTx() for more information about possible errors. */ RAIL_SCHEDULER_STATUS_SCHEDULED_TX_FAIL, /** * Calling the start transmit function returned an error code. See * RAIL_StartTx() for more information about possible errors. */ RAIL_SCHEDULER_STATUS_SINGLE_TX_FAIL, /** * Calling the CSMA transmit function returned an error code. See * RAIL_StartCcaCsmaTx() for more information about possible errors. */ RAIL_SCHEDULER_STATUS_CCA_CSMA_TX_FAIL, /** * Calling the LBT transmit function returned an error code. See * RAIL_StartCcaLbtTx() for more information about possible errors. */ RAIL_SCHEDULER_STATUS_CCA_LBT_TX_FAIL, /** * Calling the scheduled receive function returned an error code, which * means that the hardware was not set up in * time for this receive. */ RAIL_SCHEDULER_STATUS_SCHEDULED_RX_FAIL, /** * Calling the stream transmit function returned an error code. See * RAIL_StartTxStream() for more information about possible errors. */ RAIL_SCHEDULER_STATUS_TX_STREAM_FAIL, /** * RSSI averaging failed. If this scheduler status occurs, * RAIL_GetAverageRssi() will return \ref RAIL_RSSI_INVALID until * a RAIL_StartAverageRssi() completes successfully. */ RAIL_SCHEDULER_STATUS_AVERAGE_RSSI_FAIL, /** * An internal error occurred in scheduler data structures, which should * not happen and indicates a problem. */ RAIL_SCHEDULER_STATUS_INTERNAL_ERROR, }; #ifndef DOXYGEN_SHOULD_SKIP_THIS // Self-referencing defines minimize compiler complaints when using RAIL_ENUM #define RAIL_SCHEDULER_STATUS_NO_ERROR ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_STATUS_NO_ERROR) #define RAIL_SCHEDULER_STATUS_UNSUPPORTED ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_STATUS_UNSUPPORTED) #define RAIL_SCHEDULER_STATUS_EVENT_INTERRUPTED ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_STATUS_EVENT_INTERRUPTED) #define RAIL_SCHEDULER_STATUS_SCHEDULE_FAIL ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_STATUS_SCHEDULE_FAIL) #define RAIL_SCHEDULER_STATUS_SCHEDULED_TX_FAIL ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_STATUS_SCHEDULED_TX_FAIL) #define RAIL_SCHEDULER_STATUS_SINGLE_TX_FAIL ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_STATUS_SINGLE_TX_FAIL) #define RAIL_SCHEDULER_STATUS_CCA_CSMA_TX_FAIL ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_STATUS_CCA_CSMA_TX_FAIL) #define RAIL_SCHEDULER_STATUS_CCA_LBT_TX_FAIL ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_STATUS_CCA_LBT_TX_FAIL) #define RAIL_SCHEDULER_STATUS_SCHEDULED_RX_FAIL ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_STATUS_SCHEDULED_RX_FAIL) #define RAIL_SCHEDULER_STATUS_TX_STREAM_FAIL ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_STATUS_TX_STREAM_FAIL) #define RAIL_SCHEDULER_STATUS_AVERAGE_RSSI_FAIL ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_STATUS_AVERAGE_RSSI_FAIL) #define RAIL_SCHEDULER_STATUS_INTERNAL_ERROR ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_STATUS_INTERNAL_ERROR) #endif//DOXYGEN_SHOULD_SKIP_THIS /** * @enum RAIL_TaskType_t * @brief Multiprotocol radio operation task types, used with * RAIL_SetTaskPriority. */ RAIL_ENUM(RAIL_TaskType_t) { /** Indicates a task started using RAIL_StartRx */ RAIL_TASK_TYPE_START_RX, /** Indicates a task started functions other than RAIL_StartRx */ RAIL_TASK_TYPE_OTHER, }; #ifndef DOXYGEN_SHOULD_SKIP_THIS // Self-referencing defines minimize compiler complaints when using RAIL_ENUM #define RAIL_TASK_TYPE_START_RX ((RAIL_TaskType_t) RAIL_TASK_TYPE_START_RX) #define RAIL_TASK_TYPE_OTHER ((RAIL_TaskType_t) RAIL_TASK_TYPE_OTHER) #endif//DOXYGEN_SHOULD_SKIP_THIS /** @} */ // end of group Multiprotocol /****************************************************************************** * Event Structures *****************************************************************************/ /** * @addtogroup Events * @{ */ /** * @enum RAIL_Events_t * @brief RAIL events passed to the event callback. More than one event may be * indicated due to interrupt latency. */ RAIL_ENUM_GENERIC(RAIL_Events_t, uint64_t) { // RX Event Bit Shifts /** Shift position of \ref RAIL_EVENT_RSSI_AVERAGE_DONE bit */ RAIL_EVENT_RSSI_AVERAGE_DONE_SHIFT = 0, /** Shift position of \ref RAIL_EVENT_RX_ACK_TIMEOUT bit */ RAIL_EVENT_RX_ACK_TIMEOUT_SHIFT, /** Shift position of \ref RAIL_EVENT_RX_FIFO_ALMOST_FULL bit */ RAIL_EVENT_RX_FIFO_ALMOST_FULL_SHIFT, /** Shift position of \ref RAIL_EVENT_RX_PACKET_RECEIVED bit */ RAIL_EVENT_RX_PACKET_RECEIVED_SHIFT, /** Shift position of \ref RAIL_EVENT_RX_PREAMBLE_LOST bit */ RAIL_EVENT_RX_PREAMBLE_LOST_SHIFT, /** Shift position of \ref RAIL_EVENT_RX_PREAMBLE_DETECT bit */ RAIL_EVENT_RX_PREAMBLE_DETECT_SHIFT, /** Shift position of \ref RAIL_EVENT_RX_SYNC1_DETECT bit */ RAIL_EVENT_RX_SYNC1_DETECT_SHIFT, /** Shift position of \ref RAIL_EVENT_RX_SYNC2_DETECT bit */ RAIL_EVENT_RX_SYNC2_DETECT_SHIFT, /** Shift position of \ref RAIL_EVENT_RX_FRAME_ERROR bit */ RAIL_EVENT_RX_FRAME_ERROR_SHIFT, /** Shift position of \ref RAIL_EVENT_RX_FIFO_OVERFLOW bit */ RAIL_EVENT_RX_FIFO_OVERFLOW_SHIFT, /** Shift position of \ref RAIL_EVENT_RX_ADDRESS_FILTERED bit */ RAIL_EVENT_RX_ADDRESS_FILTERED_SHIFT, /** Shift position of \ref RAIL_EVENT_RX_TIMEOUT bit */ RAIL_EVENT_RX_TIMEOUT_SHIFT, /** Shift position of \ref RAIL_EVENT_RX_SCHEDULED_RX_END bit */ RAIL_EVENT_RX_SCHEDULED_RX_END_SHIFT, /** Shift position of \ref RAIL_EVENT_RX_PACKET_ABORTED bit */ RAIL_EVENT_RX_PACKET_ABORTED_SHIFT, /** Shift position of \ref RAIL_EVENT_RX_FILTER_PASSED bit */ RAIL_EVENT_RX_FILTER_PASSED_SHIFT, /** Shift position of \ref RAIL_EVENT_RX_TIMING_LOST bit */ RAIL_EVENT_RX_TIMING_LOST_SHIFT, /** Shift position of \ref RAIL_EVENT_RX_TIMING_DETECT bit */ RAIL_EVENT_RX_TIMING_DETECT_SHIFT, /** Shift position of \ref RAIL_EVENT_RX_CHANNEL_HOPPING_COMPLETE bit */ RAIL_EVENT_RX_CHANNEL_HOPPING_COMPLETE_SHIFT, /** Shift position of \ref RAIL_EVENT_RX_DUTY_CYCLE_RX_END bit */ RAIL_EVENT_RX_DUTY_CYCLE_RX_END_SHIFT = RAIL_EVENT_RX_CHANNEL_HOPPING_COMPLETE_SHIFT, /** Shift position of \ref RAIL_EVENT_IEEE802154_DATA_REQUEST_COMMAND bit */ RAIL_EVENT_IEEE802154_DATA_REQUEST_COMMAND_SHIFT, /** Shift position of \ref RAIL_EVENT_ZWAVE_BEAM bit */ RAIL_EVENT_ZWAVE_BEAM_SHIFT = RAIL_EVENT_IEEE802154_DATA_REQUEST_COMMAND_SHIFT, // TX Event Bit Shifts /** Shift position of \ref RAIL_EVENT_TX_FIFO_ALMOST_EMPTY bit */ RAIL_EVENT_TX_FIFO_ALMOST_EMPTY_SHIFT, /** Shift position of \ref RAIL_EVENT_TX_PACKET_SENT bit */ RAIL_EVENT_TX_PACKET_SENT_SHIFT, /** Shift position of \ref RAIL_EVENT_TXACK_PACKET_SENT bit */ RAIL_EVENT_TXACK_PACKET_SENT_SHIFT, /** Shift position of \ref RAIL_EVENT_TX_ABORTED bit */ RAIL_EVENT_TX_ABORTED_SHIFT, /** Shift position of \ref RAIL_EVENT_TXACK_ABORTED bit */ RAIL_EVENT_TXACK_ABORTED_SHIFT, /** Shift position of \ref RAIL_EVENT_TX_BLOCKED bit */ RAIL_EVENT_TX_BLOCKED_SHIFT, /** Shift position of \ref RAIL_EVENT_TXACK_BLOCKED bit */ RAIL_EVENT_TXACK_BLOCKED_SHIFT, /** Shift position of \ref RAIL_EVENT_TX_UNDERFLOW bit */ RAIL_EVENT_TX_UNDERFLOW_SHIFT, /** Shift position of \ref RAIL_EVENT_TXACK_UNDERFLOW bit */ RAIL_EVENT_TXACK_UNDERFLOW_SHIFT, /** Shift position of \ref RAIL_EVENT_TX_CHANNEL_CLEAR bit */ RAIL_EVENT_TX_CHANNEL_CLEAR_SHIFT, /** Shift position of \ref RAIL_EVENT_TX_CHANNEL_BUSY bit */ RAIL_EVENT_TX_CHANNEL_BUSY_SHIFT, /** Shift position of \ref RAIL_EVENT_TX_CCA_RETRY bit */ RAIL_EVENT_TX_CCA_RETRY_SHIFT, /** Shift position of \ref RAIL_EVENT_TX_START_CCA bit */ RAIL_EVENT_TX_START_CCA_SHIFT, // Scheduler Event Bit Shifts /** Shift position of \ref RAIL_EVENT_CONFIG_UNSCHEDULED bit */ RAIL_EVENT_CONFIG_UNSCHEDULED_SHIFT, /** Shift position of \ref RAIL_EVENT_CONFIG_SCHEDULED bit */ RAIL_EVENT_CONFIG_SCHEDULED_SHIFT, /** Shift position of \ref RAIL_EVENT_SCHEDULER_STATUS bit */ RAIL_EVENT_SCHEDULER_STATUS_SHIFT, // Other Event Bit Shifts /** Shift position of \ref RAIL_EVENT_CAL_NEEDED bit */ RAIL_EVENT_CAL_NEEDED_SHIFT, }; // RAIL_Event_t bitmasks /** A value representing no events */ #define RAIL_EVENTS_NONE 0ULL /** * Occurs when the hardware-averaged RSSI is done in response to * RAIL_StartAverageRssi() to indicate that the hardware has completed * averaging. Call RAIL_GetAverageRssi() to get the result. */ #define RAIL_EVENT_RSSI_AVERAGE_DONE (1ULL << RAIL_EVENT_RSSI_AVERAGE_DONE_SHIFT) /** * Notifies the application when searching for an ACK packet has timed out. * This event occurs whenever the timeout for searching for an ACK packet is * exceeded, which only occurs after calling RAIL_ConfigAutoAck() and * transmitting a packet. */ #define RAIL_EVENT_RX_ACK_TIMEOUT (1ULL << RAIL_EVENT_RX_ACK_TIMEOUT_SHIFT) /** * Occurs when the number of bytes in the receive FIFO exceeds the configured * threshold value. Call RAIL_GetRxFifoBytesAvailable() to get the number of * bytes available. When using this event, the threshold should be set via * RAIL_SetRxFifoThreshold(). */ #define RAIL_EVENT_RX_FIFO_ALMOST_FULL (1ULL << RAIL_EVENT_RX_FIFO_ALMOST_FULL_SHIFT) /** * Occurs whenever a packet is received. Call RAIL_GetRxPacketInfo() to get * basic information about the packet along with a handle to this packet for * subsequent use with RAIL_PeekRxPacket(), RAIL_GetRxPacketDetails(), * RAIL_HoldRxPacket(), and RAIL_ReleaseRxPacket() as needed. * If \ref RAIL_RX_OPTION_IGNORE_CRC_ERRORS is set, this event also occurs * for packets with CRC errors. */ #define RAIL_EVENT_RX_PACKET_RECEIVED (1ULL << RAIL_EVENT_RX_PACKET_RECEIVED_SHIFT) /** * Occurs when the radio has lost a preamble. This event can occur multiple * times while searching for a packet and is generally used for diagnostic * purposes. It can only occur after a * \ref RAIL_EVENT_RX_PREAMBLE_DETECT event has already occurred. */ #define RAIL_EVENT_RX_PREAMBLE_LOST (1ULL << RAIL_EVENT_RX_PREAMBLE_LOST_SHIFT) /** * Occurs when the radio has detected a preamble. This event can occur multiple * times while searching for a packet and is generally used for diagnostic * purposes. It can only occur after a \ref RAIL_EVENT_RX_TIMING_DETECT * event has already occurred. */ #define RAIL_EVENT_RX_PREAMBLE_DETECT (1ULL << RAIL_EVENT_RX_PREAMBLE_DETECT_SHIFT) /** * Occurs when the first sync word is detected. After this event occurs, one of * the events in the \ref RAIL_EVENTS_RX_COMPLETION mask will occur. */ #define RAIL_EVENT_RX_SYNC1_DETECT (1ULL << RAIL_EVENT_RX_SYNC1_DETECT_SHIFT) /** * Occurs when the second sync word is detected. After this event occurs, one of * the events in the \ref RAIL_EVENTS_RX_COMPLETION mask will occur. */ #define RAIL_EVENT_RX_SYNC2_DETECT (1ULL << RAIL_EVENT_RX_SYNC2_DETECT_SHIFT) /** * Occurs when a packet being received has a frame error. * * For EFR32 parts, frame errors include violations of variable length * minimum/maximum limits and CRC errors. If * \ref RAIL_RX_OPTION_IGNORE_CRC_ERRORS is set, \ref RAIL_EVENT_RX_FRAME_ERROR * will not occur for CRC errors. */ #define RAIL_EVENT_RX_FRAME_ERROR (1ULL << RAIL_EVENT_RX_FRAME_ERROR_SHIFT) /** * Occurs when the RX buffer is full, which causes the radio to stop receiving * packets until the packet causing the overflow is processed. * */ #define RAIL_EVENT_RX_FIFO_OVERFLOW (1ULL << RAIL_EVENT_RX_FIFO_OVERFLOW_SHIFT) /** * Occurs when a packet's address does not match the filtering settings. After * this event, the packet will not be received and no other events should occur * for the packet. This event can only occur after calling * RAIL_EnableAddressFilter(). */ #define RAIL_EVENT_RX_ADDRESS_FILTERED (1ULL << RAIL_EVENT_RX_ADDRESS_FILTERED_SHIFT) /** * Occurs when an RX event times out. This event can only occur if the * RAIL_StateTiming_t::rxSearchTimeout passed to RAIL_SetStateTiming() is * not zero. */ #define RAIL_EVENT_RX_TIMEOUT (1ULL << RAIL_EVENT_RX_TIMEOUT_SHIFT) /** * Occurs when the scheduled RX window ends. This event only occurs in response * to a scheduled receive timeout after calling RAIL_ScheduleRx(). If * RAIL_ScheduleRxConfig_t::rxTransitionEndSchedule was passed as false, * this event will occur unless the receive is aborted (due to a call to * RAIL_Idle() or a scheduler pre-emption, for instance). If * RAIL_ScheduleRxConfig_t::rxTransitionEndSchedule was passed as true, * any of the \ref RAIL_EVENTS_RX_COMPLETION events occurring will also cause * this event not to occur, since the scheduled receive will end with the * transition at the end of the packet. */ #define RAIL_EVENT_RX_SCHEDULED_RX_END (1ULL << RAIL_EVENT_RX_SCHEDULED_RX_END_SHIFT) /** * Occurs when a packet is aborted, but a more specific reason (such as * \ref RAIL_EVENT_RX_ADDRESS_FILTERED) isn't known. */ #define RAIL_EVENT_RX_PACKET_ABORTED (1ULL << RAIL_EVENT_RX_PACKET_ABORTED_SHIFT) /** * Occurs when the packet has passed any configured address and frame * filtering options. This event will only occur between the start of the * packet, indicated by \ref RAIL_EVENT_RX_SYNC1_DETECT or * \ref RAIL_EVENT_RX_SYNC2_DETECT and one of the events in the * \ref RAIL_EVENTS_RX_COMPLETION mask. It will always occur before or * concurrently with \ref RAIL_EVENT_RX_PACKET_RECEIVED. If IEEE 802.15.4 frame * and address filtering are enabled, this event will occur immediately after * destination address filtering. */ #define RAIL_EVENT_RX_FILTER_PASSED (1ULL << RAIL_EVENT_RX_FILTER_PASSED_SHIFT) /** * Occurs when the modem timing is lost. This event can occur multiple times * while searching for a packet and is generally used for diagnostic purposes. * It can only occur after a \ref RAIL_EVENT_RX_TIMING_DETECT event has * already occurred. */ #define RAIL_EVENT_RX_TIMING_LOST (1ULL << RAIL_EVENT_RX_TIMING_LOST_SHIFT) /** * Occurs when the modem timing is detected. This event can occur multiple times * while searching for a packet and is generally used for diagnostic purposes. */ #define RAIL_EVENT_RX_TIMING_DETECT (1ULL << RAIL_EVENT_RX_TIMING_DETECT_SHIFT) /** * Occurs when RX Channel Hopping is enabled and channel hopping finishes * receiving on the last channel in its sequence. The intent behind this event * is to allow the user to keep the radio on for as short a time as possible. * That is, once the channel sequence is complete, the application will receive * this event and can trigger a sleep/idle until it is necessary to cycle * through the channels again. If this event is left on indefinitely and not * handled it will likely be a fairly noisy event, as it continues to fire * each time the hopping algorithm cycles through the channel sequence. */ #define RAIL_EVENT_RX_CHANNEL_HOPPING_COMPLETE (1ULL << RAIL_EVENT_RX_CHANNEL_HOPPING_COMPLETE_SHIFT) /** * Occurs during RX duty cycle mode when the radio finishes its time in * receive mode. The application can then trigger a sleep/idle until it * needs to listen again. */ #define RAIL_EVENT_RX_DUTY_CYCLE_RX_END (1ULL << RAIL_EVENT_RX_DUTY_CYCLE_RX_END_SHIFT) /** * Indicates a Data Request is received when using IEEE 802.15.4 * functionality and occurs when the command byte of an incoming frame is * for a data request, which requests an ACK. This callback is called before * the packet is fully received to allow the node to have more time to decide * whether to indicate a frame is pending in the outgoing ACK. This event only * occurs if the RAIL IEEE 802.15.4 functionality is enabled, but will never * occur if promiscuous mode is enabled via * RAIL_IEEE802154_SetPromiscuousMode(). * * Call RAIL_IEEE802154_GetAddress() to get the source address of the packet. */ #define RAIL_EVENT_IEEE802154_DATA_REQUEST_COMMAND (1ULL << RAIL_EVENT_IEEE802154_DATA_REQUEST_COMMAND_SHIFT) /** * Indicates a Z-Wave Beam Request relevant to the node was received. * This event only occurs if the RAIL Z-Wave functionality is enabled * and its \ref RAIL_ZWAVE_OPTION_DETECT_BEAM_FRAMES is enabled. * This event is used in lieu of \ref RAIL_EVENT_RX_PACKET_RECEIVED, * which is reserved for Z-Wave packets other than Beams. * * Call RAIL_ZWAVE_GetBeamNodeId() to get the NodeId to which the Beam was * targeted, which would be either the broadcast id 0xFF or the node's own * single-cast id. * * @note All Z-Wave Beam requests are generally discarded, triggering * \ref RAIL_EVENT_RX_PACKET_ABORTED. */ #define RAIL_EVENT_ZWAVE_BEAM (1ULL << RAIL_EVENT_ZWAVE_BEAM_SHIFT) /** * The mask representing all events that determine the end of a received * packet. After a \ref RAIL_EVENT_RX_SYNC1_DETECT or a * \ref RAIL_EVENT_RX_SYNC2_DETECT, * exactly one of the following events will occur. When one of these events * occurs, a state transition will take place based on the parameter passed to * RAIL_SetRxTransitions(). The RAIL_StateTransitions_t::success transition * will be followed only if the \ref RAIL_EVENT_RX_PACKET_RECEIVED event occurs. * Any of the other events will trigger the RAIL_StateTransitions_t::error * transition. */ #define RAIL_EVENTS_RX_COMPLETION (RAIL_EVENT_RX_PACKET_RECEIVED \ | RAIL_EVENT_RX_PACKET_ABORTED \ | RAIL_EVENT_RX_FRAME_ERROR \ | RAIL_EVENT_RX_FIFO_OVERFLOW \ | RAIL_EVENT_RX_ADDRESS_FILTERED) // TX Event Bitmasks /** * Occurs when the number of bytes in the transmit FIFO falls below the * configured threshold value. * This event does not occur on initialization or after resetting the transmit * FIFO with RAIL_ResetFifo(). Call RAIL_GetTxFifoSpaceAvailable() to get the * number of bytes available in the transmit FIFO at the time of the callback * dispatch. When using this event, the threshold should be set via * RAIL_SetTxFifoThreshold(). */ #define RAIL_EVENT_TX_FIFO_ALMOST_EMPTY (1ULL << RAIL_EVENT_TX_FIFO_ALMOST_EMPTY_SHIFT) /** * Occurs after a packet has been transmitted. Call RAIL_GetTxPacketDetails() * to get information about the packet that was transmitted. * @note RAIL_GetTxPacketDetails() is only valid to call during the timeframe * of the RAIL_Config_t::eventsCallback. */ #define RAIL_EVENT_TX_PACKET_SENT (1ULL << RAIL_EVENT_TX_PACKET_SENT_SHIFT) /** * Occurs after an ACK packet has been transmitted. Call RAIL_GetTxPacketDetails() * to get information about the packet that was transmitted. This event can only occur * after calling RAIL_ConfigAutoAck(). * @note RAIL_GetTxPacketDetails() is only valid to call during the timeframe * of the RAIL_Config_t::eventsCallback. */ #define RAIL_EVENT_TXACK_PACKET_SENT (1ULL << RAIL_EVENT_TXACK_PACKET_SENT_SHIFT) /** * Occurs when a transmit is aborted by the user, which can happen due to calling * RAIL_Idle() or due to a scheduler pre-emption. */ #define RAIL_EVENT_TX_ABORTED (1ULL << RAIL_EVENT_TX_ABORTED_SHIFT) /** * Occurs when an ACK transmit is aborted by the user. This event can only * occur after calling RAIL_ConfigAutoAck(), which can happen due to calling * RAIL_Idle() or due to a scheduler pre-emption. */ #define RAIL_EVENT_TXACK_ABORTED (1ULL << RAIL_EVENT_TXACK_ABORTED_SHIFT) /** * Occurs when a transmit is blocked from occurring because * RAIL_EnableTxHoldOff() was called. */ #define RAIL_EVENT_TX_BLOCKED (1ULL << RAIL_EVENT_TX_BLOCKED_SHIFT) /** * Occurs when an ACK transmit is blocked from occurring because * RAIL_EnableTxHoldOff() was called. This event can only occur after calling * RAIL_ConfigAutoAck(). */ #define RAIL_EVENT_TXACK_BLOCKED (1ULL << RAIL_EVENT_TXACK_BLOCKED_SHIFT) /** * Occurs when the transmit buffer underflows, which can happen due to the * transmitted packet specifying an unintended length based on the current * radio configuration or due to RAIL_WriteTxFifo() calls not keeping up with * the transmit rate if the entire packet isn't loaded at once. */ #define RAIL_EVENT_TX_UNDERFLOW (1ULL << RAIL_EVENT_TX_UNDERFLOW_SHIFT) /** * Occurs when the ACK transmit buffer underflows, which can happen due to the * transmitted packet specifying an unintended length based on the current * radio configuration or due to RAIL_WriteAutoAckFifo() not being called at * all before an ACK transmit. This event can only occur after calling * RAIL_ConfigAutoAck(). */ #define RAIL_EVENT_TXACK_UNDERFLOW (1ULL << RAIL_EVENT_TXACK_UNDERFLOW_SHIFT) /** * Occurs when Carrier Sense Multiple Access (CSMA) or Listen Before Talk (LBT) * succeeds. This event can only happen after calling RAIL_StartCcaCsmaTx() or * RAIL_StartCcaLbtTx(). */ #define RAIL_EVENT_TX_CHANNEL_CLEAR (1ULL << RAIL_EVENT_TX_CHANNEL_CLEAR_SHIFT) /** * Occurs when Carrier Sense Multiple Access (CSMA) or Listen Before Talk (LBT) * fails. This event can only happen after calling RAIL_StartCcaCsmaTx() or * RAIL_StartCcaLbtTx(). */ #define RAIL_EVENT_TX_CHANNEL_BUSY (1ULL << RAIL_EVENT_TX_CHANNEL_BUSY_SHIFT) /** * Occurs during CSMA or LBT when an individual Clear Channel Assessment (CCA) * check fails, but there are more tries needed before the overall operation * completes. This event can occur multiple times based on the configuration * of the ongoing CSMA or LBT transmission. It can only happen after * calling RAIL_StartCcaCsmaTx() or RAIL_StartCcaLbtTx(). * */ #define RAIL_EVENT_TX_CCA_RETRY (1ULL << RAIL_EVENT_TX_CCA_RETRY_SHIFT) /** * Occurs when a Clear Channel Assessment (CCA) check begins. This event can * occur multiple times based on the configuration of the ongoing CSMA or LBT * transmission. It can only happen after calling RAIL_StartCcaCsmaTx() * or RAIL_StartCcaLbtTx(). */ #define RAIL_EVENT_TX_START_CCA (1ULL << RAIL_EVENT_TX_START_CCA_SHIFT) /** * A mask representing all events that determine the end of a transmitted * packet. After a \ref RAIL_STATUS_NO_ERROR return value * from one of the transmit functions, exactly one of the following * events will occur. When one of these events occurs, a state transition * takes place based on the parameter passed to RAIL_SetTxTransitions(). * The RAIL_StateTransitions_t::success transition will be followed only * if the \ref RAIL_EVENT_TX_PACKET_SENT event occurs. Any of the other * events will trigger the RAIL_StateTransitions_t::error transition. */ #define RAIL_EVENTS_TX_COMPLETION (RAIL_EVENT_TX_PACKET_SENT \ | RAIL_EVENT_TX_ABORTED \ | RAIL_EVENT_TX_BLOCKED \ | RAIL_EVENT_TX_UNDERFLOW \ | RAIL_EVENT_TX_CHANNEL_BUSY) /** * A mask representing all events that determine the end of a transmitted * ACK packet. After an ACK-requesting receive, exactly one of the * following events will occur. When one of these events occurs, a state * transition takes place based on the RAIL_AutoAckConfig_t::rxTransitions * passed to RAIL_ConfigAutoAck(). The receive transitions are used because the * transmitted ACK packet is considered a part of the ACK-requesting received * packet. The RAIL_StateTransitions_t::success transition will be followed * only if the \ref RAIL_EVENT_TXACK_PACKET_SENT event occurs. Any of the other * events will trigger the RAIL_StateTransitions_t::error transition. */ #define RAIL_EVENTS_TXACK_COMPLETION (RAIL_EVENT_TXACK_PACKET_SENT \ | RAIL_EVENT_TXACK_ABORTED \ | RAIL_EVENT_TXACK_BLOCKED \ | RAIL_EVENT_TXACK_UNDERFLOW) // Scheduler Event Bitmasks /** * Occurs when the scheduler switches away from this configuration. This event * can occur often in dynamic multiprotocol scenarios and can give the * current stack an opportunity to release hardware resources. */ #define RAIL_EVENT_CONFIG_UNSCHEDULED (1ULL << RAIL_EVENT_CONFIG_UNSCHEDULED_SHIFT) /** * Occurs when the scheduler switches to this configuration. This event can * occur often in dynamic multiprotocol scenarios and can be used to influence * the stack's operation. */ #define RAIL_EVENT_CONFIG_SCHEDULED (1ULL << RAIL_EVENT_CONFIG_SCHEDULED_SHIFT) /** * Occurs when the scheduler has a status to report. The exact status can be * found with RAIL_GetSchedulerStatus(). See \ref RAIL_SchedulerStatus_t for * more details. * @note RAIL_GetSchedulerStatus() is only valid to call during the timeframe * of the RAIL_Config_t::eventsCallback. */ #define RAIL_EVENT_SCHEDULER_STATUS (1ULL << RAIL_EVENT_SCHEDULER_STATUS_SHIFT) // Other Event Bitmasks /** * Occurs when the application needs to run a calibration, as * determined by the RAIL library. The application * determines a valid window to call RAIL_Calibrate(). */ #define RAIL_EVENT_CAL_NEEDED (1ULL << RAIL_EVENT_CAL_NEEDED_SHIFT) /** A value representing all possible events */ #define RAIL_EVENTS_ALL 0xFFFFFFFFFFFFFFFFULL /** @} */ // end of group Events /** * @addtogroup PA Power Amplifier (PA) * @ingroup Transmit * @{ */ /** * The transmit power in deci-dBm units (e.g., 4.5 dBm -> 45 deci-dBm). These * values are used by the conversion functions to convert a \ref * RAIL_TxPowerLevel_t to deci-dBm for the application consumption. On EFR32, * they can range from \ref RAIL_TX_POWER_MIN to \ref RAIL_TX_POWER_MAX. */ typedef int16_t RAIL_TxPower_t; /** The maximum valid value for a \ref RAIL_TxPower_t. */ #define RAIL_TX_POWER_MAX ((RAIL_TxPower_t)0x7FFF) /** The minimum valid value for a \ref RAIL_TxPower_t. */ #define RAIL_TX_POWER_MIN ((RAIL_TxPower_t)0x8000) /// mV are used for all TX power voltage values. /// TX power voltages take and return voltages multiplied by this factor. #define RAIL_TX_POWER_VOLTAGE_SCALING_FACTOR 1000 /// deci-dBm are used for all TX power dBm values. /// All dBm inputs to TX power functions take dBm power times this factor. #define RAIL_TX_POWER_DBM_SCALING_FACTOR 10 /** @} */ // PA Power Amplifier (PA) /****************************************************************************** * Radio Configuration Structures *****************************************************************************/ /** * @addtogroup Radio_Configuration * @{ */ /** * @struct RAIL_FrameType_t * @brief Configures if there is a frame type in your frame and the lengths of * each frame. The number of bits set in the mask determines the number of * elements in frameLen. A maximum of 8 different frame types may be specified. */ typedef struct RAIL_FrameType { /** * A pointer to an array of frame lengths for each frame type. The length of this * array should be equal to the number of frame types. The array that * frameLen points to should not change location or be modified. */ uint16_t *frameLen; /** * Zero-indexed location of the byte containing the frame type field. */ uint8_t offset; /** * A bitmask of the frame type field, which determines a number of frames expected * based on the number of bits set. No more than 3 bits can be set in the mask and * they must be contiguous ones. For example, if the highest three bits of the byte * specified by offset constitute the frame type, then mask should be 0xE0, * which has 3 bits set, indicating 8 possible frame types. */ uint8_t mask; /** * A bitmask that marks if each frame is valid or should be filtered. Frame type * 0 corresponds to the lowest bit in isValid. If the frame is filtered, a * RAIL_EVENT_RX_PACKET_ABORTED will be raised. */ uint8_t isValid; /** * A bitmask that marks if each frame should have the address filter applied. * Frame type 0 corresponds to the least significant bit in addressFilter. */ uint8_t addressFilter; } RAIL_FrameType_t; /** * @def RAIL_SETFIXEDLENGTH_INVALID * @brief An invalid return value when calling RAIL_SetFixedLength(). * * An invalid return value when calling RAIL_SetFixedLength() while the radio is * not in fixed-length mode. */ #define RAIL_SETFIXEDLENGTH_INVALID (0xFFFFU) /** * @struct RAIL_ChannelConfigEntryAttr_t * @brief A channel configuration entry attribute structure. Items listed * are designed to be altered and updated during run-time. */ typedef struct RAIL_ChannelConfigEntryAttr { uint32_t calValues[1]; /**< Attributes specific to each channel configuration entry. */ } RAIL_ChannelConfigEntryAttr_t; /** * @struct RAIL_ChannelConfigEntry_t * @brief A channel configuration entry structure, which defines a channel range * and parameters across which a corresponding radio configuration is valid. * * operating frequency = baseFrequency * + channelSpacing * (channel - physicalChannelOffset); */ typedef struct RAIL_ChannelConfigEntry { const uint32_t *phyConfigDeltaAdd; /**< The minimum radio configuration to apply to the base configuration for this channel set. */ uint32_t baseFrequency; /**< A base frequency in Hz of this channel set. */ uint32_t channelSpacing; /**< A channel spacing in Hz of this channel set. */ uint16_t physicalChannelOffset; /**< The offset to subtract from the logical channel to align them with the zero based physical channels which are relative to baseFrequency. (i.e., By default ch 0 = base freq, but if offset = 11, ch 11 = base freq.) */ uint16_t channelNumberStart; /**< The first valid RAIL channel number for this channel set. */ uint16_t channelNumberEnd; /**< The last valid RAIL channel number for this channel set. */ RAIL_TxPower_t maxPower; /**< The maximum power allowed in this channel set. */ RAIL_ChannelConfigEntryAttr_t *attr; /**< A pointer to a structure containing attributes specific to this channel set. */ } RAIL_ChannelConfigEntry_t; /// @struct RAIL_ChannelConfig_t /// @brief A channel configuration structure, which defines the channel meaning /// when a channel number is passed into a RAIL function, e.g., RAIL_StartTx() /// and RAIL_StartRx(). /// /// A RAIL_ChannelConfig_t structure defines the channel scheme that an /// application uses when registered in RAIL_ConfigChannels(). /// /// These are a few examples of different channel configurations: /// @code{.c} /// // 21 channels starting at 2.45 GHz with channel spacing of 1 MHz /// // ... generated by Simplicity Studio (i.e., rail_config.c) ... /// const uint32_t generated[] = { ... }; /// RAIL_ChannelConfigEntryAttr_t generated_entryAttr = { ... }; /// const RAIL_ChannelConfigEntry_t generated_channels[] = { /// { /// .phyConfigDeltaAdd = NULL, // Add this to default configuration for this entry /// .baseFrequency = 2450000000, /// .channelSpacing = 1000000, /// .physicalChannelOffset = 0, /// .channelNumberStart = 0, /// .channelNumberEnd = 20, /// .maxPower = RAIL_TX_POWER_MAX, /// .attr = &generated_entryAttr /// }, /// }; /// const RAIL_ChannelConfig_t generated_channelConfig = { /// .phyConfigBase = generated, // Default radio configuration for all entries /// .phyConfigDeltaSubtract = NULL, // Subtract this to restore the default configuration /// .configs = generated_channels, /// .length = 1 // There are this many channel configuration entries /// }; /// const RAIL_ChannelConfig_t *channelConfigs[] = { /// &generated_channelConfig, /// NULL /// }; /// // ... in main code ... /// // Associate a specific channel configuration with a particular RAIL instance. /// RAIL_ConfigChannels(railHandle, channelConfigs[0]); /// /// // 4 nonlinear channels /// // ... in rail_config.c ... /// const uint32_t generated[] = { ... }; /// RAIL_ChannelConfigEntryAttr_t generated_entryAttr = { ... }; /// const RAIL_ChannelConfigEntry_t generated_channels[] = { /// { /// .phyConfigDeltaAdd = NULL, // Add this to default configuration for this entry /// .baseFrequency = 910123456, /// .channelSpacing = 0, /// .physicalChannelOffset = 0, /// .channelNumberStart = 0, /// .channelNumberEnd = 0, /// .maxPower = RAIL_TX_POWER_MAX, /// .attr = &generated_entryAttr /// }, /// { /// .phyConfigDeltaAdd = NULL, /// .baseFrequency = 911654789, /// .channelSpacing = 0, /// .physicalChannelOffset = 0, // Since ch spacing = 0, offset can be 0 /// .channelNumberStart = 1, /// .channelNumberEnd = 1, /// .maxPower = RAIL_TX_POWER_MAX, /// .attr = &generated_entryAttr /// }, /// { /// .phyConfigDeltaAdd = NULL, /// .baseFrequency = 912321456, /// .channelSpacing = 100000, /// .physicalChannelOffset = 2, // Since ch spacing != 0, offset = 2 /// .channelNumberStart = 2, // ch 2 = baseFrequency /// .channelNumberEnd = 2, /// .maxPower = RAIL_TX_POWER_MAX, /// .attr = &generated_entryAttr /// }, /// { /// .phyConfigDeltaAdd = NULL, /// .baseFrequency = 913147852, /// .channelSpacing = 0, /// .physicalChannelOffset = 0, /// .channelNumberStart = 3, /// .channelNumberEnd = 3, /// .maxPower = RAIL_TX_POWER_MAX, /// .attr = &generated_entryAttr /// }, /// }; /// const RAIL_ChannelConfig_t generated_channelConfig = { /// .phyConfigBase = generated, // Default radio configuration for all entries /// .phyConfigDeltaSubtract = NULL, // Subtract this to restore the default configuration /// .configs = generated_channels, /// .length = 4 // There are this many channel configuration entries /// }; /// const RAIL_ChannelConfig_t *channelConfigs[] = { /// &generated_channelConfig, /// NULL /// }; /// // ... in main code ... /// // Associate a specific channel configuration with a particular RAIL instance. /// RAIL_ConfigChannels(railHandle, channelConfigs[0]); /// /// // Multiple radio configurations /// // ... in rail_config.c ... /// const uint32_t generated0[] = { ... }; /// RAIL_ChannelConfigEntryAttr_t generated0_entryAttr = { ... }; /// const RAIL_ChannelConfigEntry_t generated0_channels[] = { /// { /// .phyConfigDeltaAdd = NULL, // Add this to the default configuration for this entry /// .baseFrequency = 2450000000, /// .channelSpacing = 1000000, /// .physicalChannelOffset = 0, /// .channelNumberStart = 0, /// .channelNumberEnd = 20, /// .maxPower = RAIL_TX_POWER_MAX, /// .attr = &generated0_entryAttr /// }, /// }; /// const RAIL_ChannelConfig_t generated0_channelConfig = { /// .phyConfigBase = generated0, // Default radio configuration for all entries /// .phyConfigDeltaSubtract = NULL, // Subtract this to restore default configuration /// .configs = generated0_channels, /// .length = 1 // There are this many channel configuration entries /// }; /// const uint32_t generated1[] = { ... }; /// RAIL_ChannelConfigEntryAttr_t generated1_entryAttr = { ... }; /// const RAIL_ChannelConfigEntry_t generated1_channels[] = { /// { /// .phyConfigDeltaAdd = NULL, /// .baseFrequency = 2450000000, /// .channelSpacing = 1000000, /// .physicalChannelOffset = 0, /// .channelNumberStart = 0, /// .channelNumberEnd = 20, /// .maxPower = -100, // Use this entry when TX power <= -10dBm /// .attr = &generated1_entryAttr /// }, /// { /// .phyConfigDeltaAdd = NULL, /// .baseFrequency = 2450000000, /// .channelSpacing = 1000000, /// .physicalChannelOffset = 0, /// .channelNumberStart = 0, /// .channelNumberEnd = 20, /// .maxPower = 15, // Use this entry when TX power > -10dBm /// // and TX power <= 1.5dBm /// .attr = &generated1_entryAttr /// }, /// { /// .phyConfigDeltaAdd = NULL, /// .baseFrequency = 2450000000, /// .channelSpacing = 1000000, /// .physicalChannelOffset = 0, /// .channelNumberStart = 0, /// .channelNumberEnd = 20, /// .maxPower = RAIL_TX_POWER_MAX, // Use this entry when TX power > 1.5dBm /// .attr = &generated1_entryAttr /// }, /// }; /// const RAIL_ChannelConfig_t generated1_channelConfig = { /// .phyConfigBase = generated1, /// .phyConfigDeltaSubtract = NULL, /// .configs = generated1_channels, /// .length = 3 /// }; /// const uint32_t generated2[] = { ... }; /// RAIL_ChannelConfigEntryAttr_t generated2_entryAttr = { ... }; /// const RAIL_ChannelConfigEntry_t generated2_channels[] = { /// { /// .phyConfigDeltaAdd = NULL, /// .baseFrequency = 2450000000, /// .channelSpacing = 1000000, /// .physicalChannelOffset = 0, /// .channelNumberStart = 0, /// .channelNumberEnd = 20, /// .maxPower = RAIL_TX_POWER_MAX, /// .attr = &generated2_entryAttr /// }, /// }; /// const RAIL_ChannelConfig_t generated2_channelConfig = { /// .phyConfigBase = generated2, /// .phyConfigDeltaSubtract = NULL, /// .configs = generated2_channels, /// .length = 1 /// }; /// const RAIL_ChannelConfig_t *channelConfigs[] = { /// &generated0_channelConfig, /// &generated1_channelConfig, /// &generated2_channelConfig, /// NULL /// }; /// // ... in main code ... /// // Create a unique RAIL handle for each unique channel configuration. /// railHandle0 = RAIL_Init(&railCfg0, &RAILCb_RfReady0); /// railHandle1 = RAIL_Init(&railCfg1, &RAILCb_RfReady1); /// railHandle2 = RAIL_Init(&railCfg2, &RAILCb_RfReady2); /// // Associate each channel configuration with its corresponding RAIL handle. /// RAIL_ConfigChannels(railHandle0, channelConfigs[0]); /// RAIL_ConfigChannels(railHandle1, channelConfigs[1]); /// RAIL_ConfigChannels(railHandle2, channelConfigs[2]); /// // Use a RAIL handle and channel to access the desired channel configuration entry. /// RAIL_SetTxPowerDbm(railHandle1, 100); // set 10.0 dBm TX power /// RAIL_StartRx(railHandle1, 0, &schedInfo); // RX using generated1_channels[2] /// RAIL_SetTxPowerDbm(railHandle1, 0); // set 0 dBm TX power /// RAIL_StartRx(railHandle1, 0, &schedInfo); // RX using generated1_channels[1] /// RAIL_StartRx(railHandle2, 0, &schedInfo); // RX using generated2_channels[0] /// @endcode typedef struct RAIL_ChannelConfig { const uint32_t *phyConfigBase; /**< Base radio configuration for the corresponding channel configuration entries. */ const uint32_t *phyConfigDeltaSubtract; /**< Minimum radio configuration to restore channel entries back to base configuration. */ const RAIL_ChannelConfigEntry_t *configs; /**< Pointer to an array of RAIL_ChannelConfigEntry_t entries. */ uint32_t length; /**< Number of RAIL_ChannelConfigEntry_t entries. */ uint32_t signature; /**< Signature for this structure. Only used on modules. */ } RAIL_ChannelConfig_t; /** * @typedef RAIL_RadioConfigChangedCallback_t * @brief A pointer to a function called whenever a radio configuration change occurs. * * @param[in] railHandle A handle for RAIL instance. * @param[in] entry The radio configuration entry being changed to. */ typedef void (*RAIL_RadioConfigChangedCallback_t)(RAIL_Handle_t railHandle, const RAIL_ChannelConfigEntry_t *entry); /** @} */ // end of group Radio_Configuration /****************************************************************************** * Packet Trace Interface (PTI) Structures *****************************************************************************/ /** * @addtogroup PTI * @{ */ /** * @enum RAIL_PtiProtocol_t * @brief The protocol that RAIL outputs via the Packet Trace Interface (PTI). */ RAIL_ENUM(RAIL_PtiProtocol_t) { RAIL_PTI_PROTOCOL_CUSTOM = 0, /**< PTI output for a custom protocol. */ RAIL_PTI_PROTOCOL_THREAD = 2, /**< PTI output for the Thread protocol. */ RAIL_PTI_PROTOCOL_BLE = 3, /**< PTI output for the Bluetooth Smart protocol. */ RAIL_PTI_PROTOCOL_CONNECT = 4, /**< PTI output for the Connect protocol. */ RAIL_PTI_PROTOCOL_ZIGBEE = 5, /**< PTI output for the Zigbee protocol. */ RAIL_PTI_PROTOCOL_ZWAVE = 6, /**< PTI output for the Z-Wave protocol. */ }; #ifndef DOXYGEN_SHOULD_SKIP_THIS // Self-referencing defines minimize compiler complaints when using RAIL_ENUM #define RAIL_PTI_PROTOCOL_CUSTOM ((RAIL_PtiProtocol_t) RAIL_PTI_PROTOCOL_CUSTOM) #define RAIL_PTI_PROTOCOL_THREAD ((RAIL_PtiProtocol_t) RAIL_PTI_PROTOCOL_THREAD) #define RAIL_PTI_PROTOCOL_BLE ((RAIL_PtiProtocol_t) RAIL_PTI_PROTOCOL_BLE) #define RAIL_PTI_PROTOCOL_CONNECT ((RAIL_PtiProtocol_t) RAIL_PTI_PROTOCOL_CONNECT) #define RAIL_PTI_PROTOCOL_ZIGBEE ((RAIL_PtiProtocol_t) RAIL_PTI_PROTOCOL_ZIGBEE) #define RAIL_PTI_PROTOCOL_ZWAVE ((RAIL_PtiProtocol_t) RAIL_PTI_PROTOCOL_ZWAVE) #endif//DOXYGEN_SHOULD_SKIP_THIS /** @} */ // end of group PTI /****************************************************************************** * Data Management Structures *****************************************************************************/ /** * @addtogroup Data_Management * @{ */ /** * @enum RAIL_TxDataSource_t * @brief Transmit data sources supported by RAIL. */ RAIL_ENUM(RAIL_TxDataSource_t) { TX_PACKET_DATA, /**< Uses the frame hardware to packetize data. */ }; #ifndef DOXYGEN_SHOULD_SKIP_THIS // Self-referencing defines minimize compiler complaints when using RAIL_ENUM #define TX_PACKET_DATA ((RAIL_TxDataSource_t) TX_PACKET_DATA) #endif//DOXYGEN_SHOULD_SKIP_THIS /** * @enum RAIL_RxDataSource_t * @brief Receive data sources supported by RAIL. */ RAIL_ENUM(RAIL_RxDataSource_t) { RX_PACKET_DATA, /**< Uses the frame hardware to packetize data. */ RX_DEMOD_DATA, /**< Gets 8-bit data output from the demodulator. */ RX_IQDATA_FILTLSB, /**< Gets lower 16 bits of I/Q data provided to the demodulator. */ RX_IQDATA_FILTMSB, /**< Gets highest 16 bits of I/Q data provided to the demodulator. */ }; #ifndef DOXYGEN_SHOULD_SKIP_THIS // Self-referencing defines minimize compiler complaints when using RAIL_ENUM #define RX_PACKET_DATA ((RAIL_RxDataSource_t) RX_PACKET_DATA) #define RX_DEMOD_DATA ((RAIL_RxDataSource_t) RX_DEMOD_DATA) #define RX_IQDATA_FILTLSB ((RAIL_RxDataSource_t) RX_IQDATA_FILTLSB) #define RX_IQDATA_FILTMSB ((RAIL_RxDataSource_t) RX_IQDATA_FILTMSB) #endif//DOXYGEN_SHOULD_SKIP_THIS /** * @enum RAIL_DataMethod_t * @brief Methods for the application to provide and retrieve data from RAIL. * * For Transmit the distinction between \ref RAIL_DataMethod_t::PACKET_MODE * and \ref RAIL_DataMethod_t::FIFO_MODE has become more cosmetic than * functional, as the RAIL_WriteTxFifo() and RAIL_SetTxFifoThreshold() APIs * and related \ref RAIL_EVENT_TX_FIFO_ALMOST_EMPTY event can be used in * either mode. For Receive the distinction is functionally important because * in \ref RAIL_DataMethod_t::PACKET_MODE rollback occurs automatically for * unsuccessfully-received packets (\ref RAIL_RxPacketStatus_t ABORT statuses), * flushing their data. In \ref RAIL_DataMethod_t::FIFO_MODE rollback is * prevented, leaving the data from unsuccessfully-received packets in the * receive FIFO for the application to deal with. This allows for packets * larger than the receive FIFO size where automatic rollback would corrupt * the receive FIFO. */ RAIL_ENUM(RAIL_DataMethod_t) { PACKET_MODE, /**< Packet-based data method. */ FIFO_MODE, /**< FIFO-based data method. */ }; #ifndef DOXYGEN_SHOULD_SKIP_THIS // Self-referencing defines minimize compiler complaints when using RAIL_ENUM #define PACKET_MODE ((RAIL_DataMethod_t) PACKET_MODE) #define FIFO_MODE ((RAIL_DataMethod_t) FIFO_MODE) #endif//DOXYGEN_SHOULD_SKIP_THIS /** * @def RAIL_FIFO_THRESHOLD_DISABLED * @brief A FIFO threshold value that disables the threshold. */ #define RAIL_FIFO_THRESHOLD_DISABLED 0xFFFFU /** * @struct RAIL_DataConfig_t * @brief RAIL data configuration structure * * Selects the transmit/receive data sources and the * method the application uses to provide/retrieve data from RAIL. */ typedef struct { RAIL_TxDataSource_t txSource; /**< Source of TX Data. */ RAIL_RxDataSource_t rxSource; /**< Source of RX Data. */ RAIL_DataMethod_t txMethod; /**< Method of providing transmit data. */ RAIL_DataMethod_t rxMethod; /**< Method of retrieving receive data. */ } RAIL_DataConfig_t; /** @} */ // end of group Data Management /****************************************************************************** * State Transitions *****************************************************************************/ /** * @addtogroup State_Transitions * @{ */ /** * @enum RAIL_RadioState_t * @brief The state of the radio. */ RAIL_ENUM(RAIL_RadioState_t) { RAIL_RF_STATE_INACTIVE = 0u, /**< Radio is inactive. */ RAIL_RF_STATE_ACTIVE = (1u << 0), /**< Radio is either idle or, in combination with the RX and TX states, receiving or transmitting a frame.*/ RAIL_RF_STATE_RX = (1u << 1), /**< Radio is in receive. */ RAIL_RF_STATE_TX = (1u << 2), /**< Radio is in transmit. */ RAIL_RF_STATE_IDLE = (RAIL_RF_STATE_ACTIVE), /**< Radio is idle. */ /** Radio is actively receiving a frame. */ RAIL_RF_STATE_RX_ACTIVE = (RAIL_RF_STATE_RX | RAIL_RF_STATE_ACTIVE), /** Radio is actively transmitting a frame. */ RAIL_RF_STATE_TX_ACTIVE = (RAIL_RF_STATE_TX | RAIL_RF_STATE_ACTIVE) }; #ifndef DOXYGEN_SHOULD_SKIP_THIS // Self-referencing defines minimize compiler complaints when using RAIL_ENUM #define RAIL_RF_STATE_INACTIVE ((RAIL_RadioState_t) RAIL_RF_STATE_INACTIVE) #define RAIL_RF_STATE_ACTIVE ((RAIL_RadioState_t) RAIL_RF_STATE_ACTIVE) #define RAIL_RF_STATE_RX ((RAIL_RadioState_t) RAIL_RF_STATE_RX) #define RAIL_RF_STATE_TX ((RAIL_RadioState_t) RAIL_RF_STATE_TX) #define RAIL_RF_STATE_IDLE ((RAIL_RadioState_t) RAIL_RF_STATE_IDLE) #define RAIL_RF_STATE_RX_ACTIVE ((RAIL_RadioState_t) RAIL_RF_STATE_RX_ACTIVE) #define RAIL_RF_STATE_TX_ACTIVE ((RAIL_RadioState_t) RAIL_RF_STATE_TX_ACTIVE) #endif//DOXYGEN_SHOULD_SKIP_THIS /** * @struct RAIL_StateTransitions_t * @brief Used to specify radio states to transition to on success or failure. */ typedef struct RAIL_StateTransitions { /** * Indicates the state the radio should return to after a successful action. */ RAIL_RadioState_t success; /** * Indicates the state the radio should return to after an error. */ RAIL_RadioState_t error; } RAIL_StateTransitions_t; /** * @struct RAIL_StateTiming_t * @brief A timing configuration structure for the RAIL State Machine. * * Configures the timings of the radio state transitions for common situations. * All of the listed timings are in us. Timing values cannot exceed 13 ms. A * value of 0 for the transition time means that the specified transition * should happen as fast as possible, even if the timing cannot be as * consistent. Any other timing value will be limited, so that the time can be * hit consistently. Transitions to IDLE always happen as fast as possible. */ typedef struct RAIL_StateTiming { uint16_t idleToRx; /**< Transition time from IDLE to RX. */ uint16_t txToRx; /**< Transition time from TX to RX. */ uint16_t idleToTx; /**< Transition time from IDLE to RX. */ uint16_t rxToTx; /**< Transition time from RX to TX. */ uint16_t rxSearchTimeout; /**< Time radio looks for packets when coming from idle, value of zero disables this feature. */ uint16_t txToRxSearchTimeout; /**< Time to look for packets when coming from TX, value of zero disables this feature. */ } RAIL_StateTiming_t; /** * @enum RAIL_IdleMode_t * @brief An enumeration for the different types of supported idle modes. These * vary how quickly and destructively they put the radio into idle. */ RAIL_ENUM(RAIL_IdleMode_t) { /** * Idles the radio by turning off receive and canceling any future scheduled * receive or transmit operations. It does not abort a receive or * transmit in progress. */ RAIL_IDLE, /** * Idles the radio by turning off receive and any scheduled events. It * also aborts any receive, transmit, or scheduled events in progress. */ RAIL_IDLE_ABORT, /** * Forces the radio into a shutdown mode as quickly as possible. It * aborts all current operations and cancels any pending scheduled * operations. * It may also corrupt receive or transmit buffers and end up clearing them. */ RAIL_IDLE_FORCE_SHUTDOWN, /** * Similar to the \ref RAIL_IDLE_FORCE_SHUTDOWN command, it quickly * puts the radio into idle state. Additionally, it clears any * pending receive or transmit callbacks and clear both the receive and * transmit storage. */ RAIL_IDLE_FORCE_SHUTDOWN_CLEAR_FLAGS, }; #ifndef DOXYGEN_SHOULD_SKIP_THIS // Self-referencing defines minimize compiler complaints when using RAIL_ENUM #define RAIL_IDLE ((RAIL_IdleMode_t) RAIL_IDLE) #define RAIL_IDLE_ABORT ((RAIL_IdleMode_t) RAIL_IDLE_ABORT) #define RAIL_IDLE_FORCE_SHUTDOWN ((RAIL_IdleMode_t) RAIL_IDLE_FORCE_SHUTDOWN) #define RAIL_IDLE_FORCE_SHUTDOWN_CLEAR_FLAGS ((RAIL_IdleMode_t) RAIL_IDLE_FORCE_SHUTDOWN_CLEAR_FLAGS) #endif//DOXYGEN_SHOULD_SKIP_THIS /** @} */ // end of group State_Transitions /****************************************************************************** * TX/RX Configuration Structures *****************************************************************************/ /** * @addtogroup Transmit * @{ */ /** * @enum RAIL_StopMode_t * @brief Stop radio operation options bit mask */ RAIL_ENUM(RAIL_StopMode_t) { /** Shift position of \ref RAIL_STOP_MODE_ACTIVE bit */ RAIL_STOP_MODE_ACTIVE_SHIFT = 0, /** Shift position of \ref RAIL_STOP_MODE_PENDING bit */ RAIL_STOP_MODE_PENDING_SHIFT = 1 }; /** Do not stop any radio operations */ #define RAIL_STOP_MODES_NONE (0U) /** Stop active radio operations only */ #define RAIL_STOP_MODE_ACTIVE (1U << RAIL_STOP_MODE_ACTIVE_SHIFT) /** Stop pending radio operations */ #define RAIL_STOP_MODE_PENDING (1U << RAIL_STOP_MODE_PENDING_SHIFT) /** Stop all radio operations */ #define RAIL_STOP_MODES_ALL (0xFFU) /** * @enum RAIL_TxOptions_t * @brief Transmit options, in reality a bitmask. */ RAIL_ENUM_GENERIC(RAIL_TxOptions_t, uint32_t) { /** Shift position of \ref RAIL_TX_OPTION_WAIT_FOR_ACK bit */ RAIL_TX_OPTION_WAIT_FOR_ACK_SHIFT = 0, /** Shift position of \ref RAIL_TX_OPTION_REMOVE_CRC bit */ RAIL_TX_OPTION_REMOVE_CRC_SHIFT, /** Shift position of \ref RAIL_TX_OPTION_SYNC_WORD_ID bit */ RAIL_TX_OPTION_SYNC_WORD_ID_SHIFT, /** Shift position of \ref RAIL_TX_OPTION_ANTENNA0 bit */ RAIL_TX_OPTION_ANTENNA0_SHIFT, /** Shift position of \ref RAIL_TX_OPTION_ANTENNA1 bit */ RAIL_TX_OPTION_ANTENNA1_SHIFT, /** Shift position of \ref RAIL_TX_OPTION_ALT_PREAMBLE_LEN bit */ RAIL_TX_OPTION_ALT_PREAMBLE_LEN_SHIFT, /** Shift position of \ref RAIL_TX_OPTION_CCA_PEAK_RSSI bit */ RAIL_TX_OPTION_CCA_PEAK_RSSI_SHIFT, }; /** A value representing no options enabled. */ #define RAIL_TX_OPTIONS_NONE 0UL /** All options disabled by default . */ #define RAIL_TX_OPTIONS_DEFAULT RAIL_TX_OPTIONS_NONE /** * An option to configure whether or not the TXing node will listen for an ACK. * If this is false, the isAck flag in RAIL_RxPacketDetails_t of a received * packet will always be false. */ #define RAIL_TX_OPTION_WAIT_FOR_ACK (1UL << RAIL_TX_OPTION_WAIT_FOR_ACK_SHIFT) /** * An option to remove CRC bytes from TX packets. To receive packets when the * sender has this option set true, set \ref RAIL_RX_OPTION_IGNORE_CRC_ERRORS * on the receive side. */ #define RAIL_TX_OPTION_REMOVE_CRC (1UL << RAIL_TX_OPTION_REMOVE_CRC_SHIFT) /** * An option to select which sync word to send (0 or 1). Note that this does * not set the actual sync words, it just picks which of the two will be * sent with the packet. */ #define RAIL_TX_OPTION_SYNC_WORD_ID (1UL << RAIL_TX_OPTION_SYNC_WORD_ID_SHIFT) /** * An option to select antenna 0 for transmission. If the antenna selection * option is not set or if both antenna options are set, then the transmit * will occur on either antenna depending on the last receive or transmit * selection. This option is only valid on platforms that support * \ref Antenna_Control and have been configured via RAIL_ConfigAntenna(). * * @note These TX antenna options do not control the antenna used for * \ref Auto_Ack transmissions, which always occur on the same antenna * used to receive the packet being acknowledged. */ #define RAIL_TX_OPTION_ANTENNA0 (1UL << RAIL_TX_OPTION_ANTENNA0_SHIFT) /** * An option to select antenna 1 for transmission. If the antenna selection * option is not set or if both antenna options are set, then the transmit * will occur on either antenna depending on the last receive or transmit * selection. This option is only valid on platforms that support * \ref Antenna_Control and have been configured via RAIL_ConfigAntenna(). * * @note These TX antenna options do not control the antenna used for * \ref Auto_Ack transmissions, which always occur on the same antenna * used to receive the packet being acknowledged. */ #define RAIL_TX_OPTION_ANTENNA1 (1UL << RAIL_TX_OPTION_ANTENNA1_SHIFT) /** * An option to dynamically set an alternate preamble length for the * transmission. If this option is not set, the pre-configured * channel preamble length will be used. */ #define RAIL_TX_OPTION_ALT_PREAMBLE_LEN (1UL << RAIL_TX_OPTION_ALT_PREAMBLE_LEN_SHIFT) /** * An option to use peak rather than average RSSI energy detected during * CSMA's RAIL_CsmaConfig_t::ccaDuration or LBT's * RAIL_LbtConfig_t::lbtDuration to determine whether the channel is clear * or busy. * @note This option does nothing on platforms like EFR32XG1 that lack * support for capturing peak RSSI energy. */ #define RAIL_TX_OPTION_CCA_PEAK_RSSI (1UL << RAIL_TX_OPTION_CCA_PEAK_RSSI_SHIFT) /** A value representing all possible options. */ #define RAIL_TX_OPTIONS_ALL 0xFFFFFFFFUL /** * @struct RAIL_TxPacketDetails_t * @brief Detailed information requested and about the packet that was just * transmitted. */ typedef struct RAIL_TxPacketDetails { /** * The timestamp of the transmitted packet in the RAIL timebase, * filled in by RAIL_GetTxPacketDetails(). */ RAIL_PacketTimeStamp_t timeSent; /** * Indicates whether the transmitted packet was an ACK. An 'ACK' is defined * as a packet sent in response to a received ACK-requesting frame when * auto ACK is enabled. Set to false for not an ACK and true for an ACK. * It should always be set to false if auto ACK is not enabled. */ bool isAck; } RAIL_TxPacketDetails_t; /** * @enum RAIL_ScheduledTxDuringRx_t * @brief Enumerates the possible outcomes of what will occur if a * scheduled TX ends up firing during RX. Because RX and TX can't * happen at the same time, it is up to the user how the TX should be * handled. This enumeration is passed into RAIL_StartScheduledTx() * as part of \ref RAIL_ScheduleTxConfig_t. */ RAIL_ENUM(RAIL_ScheduledTxDuringRx_t) { /** * The scheduled TX will be postponed until RX completes and then sent. */ RAIL_SCHEDULED_TX_DURING_RX_POSTPONE_TX, /** * The scheduled TX will be aborted and a TX aborted event will fire. */ RAIL_SCHEDULED_TX_DURING_RX_ABORT_TX, }; #ifndef DOXYGEN_SHOULD_SKIP_THIS // Self-referencing defines minimize compiler complaints when using RAIL_ENUM #define RAIL_SCHEDULED_TX_DURING_RX_POSTPONE_TX ((RAIL_ScheduledTxDuringRx_t) RAIL_SCHEDULED_TX_DURING_RX_POSTPONE_TX) #define RAIL_SCHEDULED_TX_DURING_RX_ABORT_TX ((RAIL_ScheduledTxDuringRx_t) RAIL_SCHEDULED_TX_DURING_RX_ABORT_TX) #endif//DOXYGEN_SHOULD_SKIP_THIS /** * @struct RAIL_ScheduleTxConfig_t * @brief A configuration structure for a scheduled transmit. */ typedef struct RAIL_ScheduleTxConfig { /** * The time when to transmit this packet. The exact interpretation of * this value depends on the mode specified below. */ RAIL_Time_t when; /** * The type of delay. See the \ref RAIL_TimeMode_t documentation for * more information. Be sure to use \ref RAIL_TIME_ABSOLUTE delays for * time-critical protocols. */ RAIL_TimeMode_t mode; /** * Indicates which action to take with a scheduled TX if it occurs during RX. * See \ref RAIL_ScheduledTxDuringRx_t structure for more information on * potential options. */ RAIL_ScheduledTxDuringRx_t txDuringRx; } RAIL_ScheduleTxConfig_t; /** * @def RAIL_MAX_LBT_TRIES * @brief The maximum number of LBT/CSMA retries supported. */ #define RAIL_MAX_LBT_TRIES 15 /** * @def RAIL_MAX_CSMA_EXPONENT * @brief The maximum power-of-2 exponent for CSMA backoffs. */ #define RAIL_MAX_CSMA_EXPONENT 8 /// /// @struct RAIL_CsmaConfig_t /// @brief A configuration structure for the CSMA transmit algorithm. /// /// One of RAIL's schemes for polite spectrum access is an implementation of /// a Carrier-Sense Multiple Access (CSMA) algorithm based on IEEE 802.15.4 /// (unslotted). /// \n In pseudo-code it works like this, showing relevant event notifications: /// @code{.c} /// RAIL_Event_t performCsma(const RAIL_CsmaConfig_t *csmaConfig) /// { /// bool isFixedBackoff = ((csmaConfig->csmaMinBoExp == 0) /// && (csmaConfig->csmaMinBoExp == 0)); /// int backoffExp = csmaConfig->csmaMinBoExp; // Initial backoff exponent /// int backoffMultiplier = 1; // Assume fixed backoff /// int try; /// /// // Start overall timeout if specified: /// if (csmaConfig->csmaTimeout > 0) { /// StartAbortTimer(csmaConfig->csmaTimeout, RAIL_EVENT_TX_CHANNEL_BUSY); /// // If timeout occurs, abort and signal the indicated event. /// } /// /// for (try = 0; try < csmaConfig->csmaTries; try++) { /// if (try > 0) { /// signalEvent(RAIL_EVENT_TX_CCA_RETRY); /// } /// // Determine the backoff multipler for this try: /// if (isFixedBackoff) { /// // backoffMultiplier already set to 1 for fixed backoff /// } else { /// // Start with the backoff exponent for this try: /// if (try > 0) { /// backoffExp++; /// if (backoffExp > csmaConfig->csmaMaxBoExp) { /// backoffExp = csmaConfig->csmaMaxBoExp; /// } /// } /// // Pick random multiplier between 0 and 2^backoffExp - 1 inclusive: /// backoffMultiplier = pickRandomInteger(0, (1 << backoffExp) - 1); /// } /// // Perform the backoff: /// delayMicroseconds(backoffMultiplier * csmaConfig->ccaBackoff); /// // Perform the Clear-Channel Assessment (CCA): /// // Channel is considered busy if radio is actively receiving or /// // transmitting, or the average energy detected across duration /// // is above the threshold. /// signalEvent(RAIL_EVENT_TX_START_CCA); /// if (performCca(csmaConfig->ccaDuration, csmaConfig->ccaThreshold)) { /// // CCA (and CSMA) success: Transmit after Rx-to-Tx turnaround /// StopAbortTimer(); /// return RAIL_EVENT_TX_CHANNEL_CLEAR; /// } else { /// // CCA failed: loop to try again, or exit if out of tries /// } /// } /// // Overall CSMA failure: Don't transmit /// StopAbortTimer(); /// return RAIL_EVENT_TX_CHANNEL_BUSY; /// } /// @endcode /// typedef struct RAIL_CsmaConfig { /** * The minimum (starting) exponent for CSMA random backoff (2^exp - 1). * It can range from 0 to \ref RAIL_MAX_CSMA_EXPONENT. */ uint8_t csmaMinBoExp; /** * The maximum exponent for CSMA random backoff (2^exp - 1). * It can range from 0 to \ref RAIL_MAX_CSMA_EXPONENT and must be greater * than or equal to \ref csmaMinBoExp. * \n If both exponents are 0, a non-random fixed backoff of \ref ccaBackoff * duration results. */ uint8_t csmaMaxBoExp; /** * The number of backoff-then-CCA iterations that can fail before reporting * \ref RAIL_EVENT_TX_CHANNEL_BUSY. It can range from 1 to \ref * RAIL_MAX_LBT_TRIES; other values are disallowed. */ uint8_t csmaTries; /** * The CCA RSSI threshold, in dBm, above which the channel is * considered 'busy'. */ int8_t ccaThreshold; /** * The backoff unit period in RAIL's microsecond time base. It is * multiplied by the random backoff exponential controlled by \ref * csmaMinBoExp and \ref csmaMaxBoExp to determine the overall backoff * period. For random backoffs, any value above 511 microseconds will * be truncated. For fixed backoffs it can go up to 65535 microseconds. */ uint16_t ccaBackoff; /** * The minimum desired CCA check duration in microseconds. * * @note Depending on the radio configuration, due to hardware constraints, * the actual duration may be longer. */ uint16_t ccaDuration; /** * An overall timeout, in RAIL's microsecond time base, for the operation. * If the transmission doesn't start before this timeout expires, the * transmission will fail with \ref RAIL_EVENT_TX_CHANNEL_BUSY. * A value 0 means no timeout is imposed. */ RAIL_Time_t csmaTimeout; } RAIL_CsmaConfig_t; /** * @def RAIL_CSMA_CONFIG_802_15_4_2003_2p4_GHz_OQPSK_CSMA * @brief RAIL_CsmaConfig_t initializer configuring CSMA per IEEE 802.15.4-2003 * on 2.4 GHz OSPSK, commonly used by ZigBee. */ #define RAIL_CSMA_CONFIG_802_15_4_2003_2p4_GHz_OQPSK_CSMA { \ /* CSMA per 802.15.4-2003 on 2.4 GHz OSPSK, commonly used by ZigBee */ \ /* csmaMinBoExp */ 3, /* 2^3-1 for 0..7 backoffs on 1st try */ \ /* csmaMaxBoExp */ 5, /* 2^5-1 for 0..31 backoffs on 3rd+ tries */ \ /* csmaTries */ 5, /* 5 tries overall (4 re-tries) */ \ /* ccaThreshold */ -75, /* 10 dB above sensitivity */ \ /* ccaBackoff */ 320, /* 20 symbols at 16 us/symbol */ \ /* ccaDuration */ 128, /* 8 symbols at 16 us/symbol */ \ /* csmaTimeout */ 0, /* No timeout */ \ } /** * @def RAIL_CSMA_CONFIG_SINGLE_CCA * @brief RAIL_CsmaConfig_t initializer configuring a single CCA prior to TX. * It can be used to as a basis for implementing other channel access schemes * with custom backoff delays. Users can override ccaBackoff with a fixed * delay on each use. */ #define RAIL_CSMA_CONFIG_SINGLE_CCA { \ /* Perform a single CCA after 'fixed' delay */ \ /* csmaMinBoExp */ 0, /* Used for fixed backoff */ \ /* csmaMaxBoExp */ 0, /* Used for fixed backoff */ \ /* csmaTries */ 1, /* Single try */ \ /* ccaThreshold */ -75, /* Override if not desired choice */ \ /* ccaBackoff */ 0, /* No backoff (override with fixed value) */ \ /* ccaDuration */ 128, /* Override if not desired length */ \ /* csmaTimeout */ 0, /* no timeout */ \ } /// /// @struct RAIL_LbtConfig_t /// @brief A configuration structure for the LBT transmit algorithm. /// /// One of RAIL's schemes for polite spectrum access is an implementation of /// a Listen-Before-Talk (LBT) algorithm, loosely based on ETSI 300 220-1. /// \n Currently, however, it is constrained by the EFR32's CSMA-oriented hardware /// so is turned into an equivalent \ref RAIL_CsmaConfig_t configuration and /// passed to the CSMA engine: /// @code{.c} /// if (lbtMaxBoRand == lbtMinBoRand) { /// // Fixed backoff /// csmaMinBoExp = csmaMaxBoExp = 0; /// if (lbtMinBoRand == 0) { /// ccaBackoff = lbtBackoff; /// } else { /// ccaBackoff = lbtMinBoRand * lbtBackoff; /// } /// ccaDuration = lbtDuration; /// } else { /// // Random backoff: map to random range 0 .. (lbtMaxBoRand - lbtMinBoRand) /// csmaMinBoExp = csmaMaxBoExp = ceiling(log2(lbtMaxBoRand - lbtMinBoRand)); /// ccaBackoff = round((lbtBackoff * (lbtMaxBoRand - lbtMinBoRand)) /// / (1 << csmaMinBoExp)); /// ccaDuration = lbtDuration + (lbtMinBoRand * lbtBackoff); /// } /// csmaTries = lbtTries; /// ccaThreshold = lbtThreshold; /// csmaTimeout = lbtTimeout; /// @endcode /// typedef struct RAIL_LbtConfig { /** * The minimum backoff random multiplier. */ uint8_t lbtMinBoRand; /** * The maximum backoff random multiplier. * It must be greater than or equal to \ref lbtMinBoRand. * \n If both backoff multipliers are identical, a non-random fixed backoff * of \ref lbtBackoff times the multiplier (minimim 1) duration results. */ uint8_t lbtMaxBoRand; /** * The number of LBT iterations that can fail before reporting * \ref RAIL_EVENT_TX_CHANNEL_BUSY. It can range from 1 to \ref * RAIL_MAX_LBT_TRIES; other values are disallowed. */ uint8_t lbtTries; /** * The LBT RSSI threshold, in dBm, above which the channel is * considered 'busy'. */ int8_t lbtThreshold; /** * The backoff unit period, in RAIL's microsecond time base. It is * multiplied by the random backoff multiplier controlled by \ref * lbtMinBoRand and \ref lbtMaxBoRand to determine the overall backoff * period. For random backoffs, any value above 511 microseconds will * be truncated. For fixed backoffs, it can go up to 65535 microseconds. */ uint16_t lbtBackoff; /** * The minimum desired LBT check duration in microseconds. * * @note Depending on the radio configuration, due to hardware constraints, * the actual duration may be longer. */ uint16_t lbtDuration; /** * An overall timeout, in RAIL's microsecond time base, for the operation. * If the transmission doesn't start before this timeout expires, the * transmission will fail with \ref RAIL_EVENT_TX_CHANNEL_BUSY. * This is important for limiting LBT due to LBT's unbounded requirement * that if the channel is busy, the next try must wait for the channel to * clear. A value 0 means no timeout is imposed. */ RAIL_Time_t lbtTimeout; } RAIL_LbtConfig_t; /** * @def RAIL_LBT_CONFIG_ETSI_EN_300_220_1_V2_4_1 * @brief RAIL_LbtConfig_t initializer configuring LBT per ETSI 300 220-1 * V2.4.1 for a typical Sub-GHz band. To be practical, users should override * lbtTries and/or lbtTimeout so channel access failure will be reported in a * reasonable time frame rather than the unbounded time frame ETSI defined. */ #define RAIL_LBT_CONFIG_ETSI_EN_300_220_1_V2_4_1 { \ /* LBT per ETSI 300 220-1 V2.4.1 */ \ /* LBT time = random backoff of 0-5 ms in .5 ms increments plus 5 ms fixed */ \ /* lbtMinBoRand */ 0, /* */ \ /* lbtMaxBoRand */ 10, /* */ \ /* lbtTries */ RAIL_MAX_LBT_TRIES, /* the maximum supported */ \ /* lbtThreshold */ -87, /* */ \ /* lbtBackoff */ 500, /* 0.5 ms */ \ /* lbtDuration */ 5000, /* 5 ms */ \ /* lbtTimeout */ 0, /* No timeout (recommend user override) */ \ } /** @} */ // end of group Transmit /** * @addtogroup Receive * @{ */ /** * @enum RAIL_RxOptions_t * @brief Receive options, in reality a bitmask. */ RAIL_ENUM_GENERIC(RAIL_RxOptions_t, uint32_t) { /** Shift position of \ref RAIL_RX_OPTION_STORE_CRC bit. */ RAIL_RX_OPTION_STORE_CRC_SHIFT = 0, /** Shift position of \ref RAIL_RX_OPTION_IGNORE_CRC_ERRORS bit. */ RAIL_RX_OPTION_IGNORE_CRC_ERRORS_SHIFT, /** Shift position of \ref RAIL_RX_OPTION_ENABLE_DUALSYNC bit. */ RAIL_RX_OPTION_ENABLE_DUALSYNC_SHIFT, /** Shift position of \ref RAIL_RX_OPTION_TRACK_ABORTED_FRAMES bit. */ RAIL_RX_OPTION_TRACK_ABORTED_FRAMES_SHIFT, /** Shift position of \ref RAIL_RX_OPTION_REMOVE_APPENDED_INFO bit. */ RAIL_RX_OPTION_REMOVE_APPENDED_INFO_SHIFT, /** Shift position of \ref RAIL_RX_OPTION_ANTENNA0 bit. */ RAIL_RX_OPTION_ANTENNA0_SHIFT, /** Shift position of \ref RAIL_RX_OPTION_ANTENNA1 bit. */ RAIL_RX_OPTION_ANTENNA1_SHIFT, /** Shift position of \ref RAIL_RX_OPTION_DISABLE_FRAME_DETECTION bit. */ RAIL_RX_OPTION_DISABLE_FRAME_DETECTION_SHIFT, }; /** A value representing no options enabled. */ #define RAIL_RX_OPTIONS_NONE 0 /** All options are disabled by default. */ #define RAIL_RX_OPTIONS_DEFAULT RAIL_RX_OPTIONS_NONE /** * An option to configure whether the CRC portion of the packet is included in * the packet payload exposed to the app on packet reception. * Defaults to false. */ #define RAIL_RX_OPTION_STORE_CRC (1UL << RAIL_RX_OPTION_STORE_CRC_SHIFT) /** * An option to configure whether CRC errors will be ignored. * If this is set, RX will still be successful, even if * the CRC does not pass the check. Defaults to false. */ #define RAIL_RX_OPTION_IGNORE_CRC_ERRORS (1UL << RAIL_RX_OPTION_IGNORE_CRC_ERRORS_SHIFT) /** * An option to control which sync words will be accepted. Setting it to * 0 (default) will cause the receiver to listen for SYNC1 only. Setting it to * 1 causes the receiver to listen for either SYNC1 or SYNC2. RX appended info * will contain which sync word was detected. Note, this only affects which * sync word(s) are received, but not what each of the sync words actually are. * This feature may not be available on some combinations of chips, PHYs, and * protocols. See the data sheet or support team for more details. */ #define RAIL_RX_OPTION_ENABLE_DUALSYNC (1UL << RAIL_RX_OPTION_ENABLE_DUALSYNC_SHIFT) /** * An option to configure whether frames which are aborted during reception * should continue to be tracked. Setting this option allows viewing Packet * Trace information for frames which get discarded. Defaults to false. */ #define RAIL_RX_OPTION_TRACK_ABORTED_FRAMES (1UL << RAIL_RX_OPTION_TRACK_ABORTED_FRAMES_SHIFT) /** * An option to suppress capturing the appended information after * received frames. Defaults to false. When suppressed, certain * \ref RAIL_RxPacketDetails_t details will not be available for received * packets whose \ref RAIL_RxPacketStatus_t is among the RAIL_RX_PACKET_READY_ * set. */ #define RAIL_RX_OPTION_REMOVE_APPENDED_INFO (1UL << RAIL_RX_OPTION_REMOVE_APPENDED_INFO_SHIFT) /** * An option to select the use of antenna 0 during receive (including * \ref Auto_Ack receive). If no antenna * option is selected, the receive may take place on either antenna * depending on the last receive or transmit selection. Defaults to false. * This option is only valid on platforms that support * \ref Antenna_Control and have been configured via RAIL_ConfigAntenna(). */ #define RAIL_RX_OPTION_ANTENNA0 (1UL << RAIL_RX_OPTION_ANTENNA0_SHIFT) /** * An option to select the use of antenna 1 during receive (including * \ref Auto_Ack receive). If no antenna * option is selected, the receive may take place on either antenna * depending on the last receive or transmit selection. Defaults to false. * This option is only valid on platforms that support * \ref Antenna_Control and have been configured via RAIL_ConfigAntenna(). */ #define RAIL_RX_OPTION_ANTENNA1 (1UL << RAIL_RX_OPTION_ANTENNA1_SHIFT) /** * An option combination to automatically choose an antenna during receive * (including \ref Auto_Ack receive). If both * antenna 0 and antenna 1 options are set, the radio will dynamically * switch between antennas during packet detection and choose the best * one for completing the reception. * This option is only valid on platforms that support * \ref Antenna_Control and have been configured via RAIL_ConfigAntenna(). */ #define RAIL_RX_OPTION_ANTENNA_AUTO (RAIL_RX_OPTION_ANTENNA0 | RAIL_RX_OPTION_ANTENNA1) /** * An option to disable frame detection. This can be useful for doing energy * detection without risking packet reception. Enabling this will abort any * frame currently being received in addition to preventing further frames * from being received. Defaults to false. */ #define RAIL_RX_OPTION_DISABLE_FRAME_DETECTION (1UL << RAIL_RX_OPTION_DISABLE_FRAME_DETECTION_SHIFT) /** A value representing all possible options. */ #define RAIL_RX_OPTIONS_ALL 0xFFFFFFFFUL /** The value returned by RAIL for an invalid RSSI, in dBm. */ #define RAIL_RSSI_INVALID_DBM (-128) /** The value returned by RAIL for an invalid RSSI: in quarter dBm. */ #define RAIL_RSSI_INVALID ((int16_t)(RAIL_RSSI_INVALID_DBM * 4)) /** * @struct RAIL_ScheduleRxConfig_t * @brief Configures the scheduled RX algorithm. * * Defines the start and end times of the receive window created * for a scheduled receive. If either start or end times are disabled, they * will be ignored. */ typedef struct RAIL_ScheduleRxConfig { /** * The time to start receive. See startMode for more information about the * types of start times that you can specify. */ RAIL_Time_t start; /** * How to interpret the time value specified in the start parameter. See the * \ref RAIL_TimeMode_t documentation for more information. Use * \ref RAIL_TIME_ABSOLUTE for absolute times, \ref RAIL_TIME_DELAY for times * relative to the current time and \ref RAIL_TIME_DISABLED to ignore the * start time. */ RAIL_TimeMode_t startMode; /** * The time to end receive. See endMode for more information about the types * of end times you can specify. */ RAIL_Time_t end; /** * How to interpret the time value specified in the end parameter. See the * \ref RAIL_TimeMode_t documentation for more information. Note that, in * this API, if you specify a \ref RAIL_TIME_DELAY, it is relative to the * start time if given and relative to now if none is specified. Also, using * \ref RAIL_TIME_DISABLED means that this window will not end unless you * explicitly call RAIL_RfIdle() or add an end event through a future update * to this configuration. */ RAIL_TimeMode_t endMode; /** * While in scheduled RX, you can still control the radio state via * state transitions. This option configures whether a transition * to RX goes back to scheduled RX or to the normal RX state. Once in the * normal RX state, you will effectively end the scheduled RX window and can * continue to receive indefinitely depending on the state transitions. Set * to 1 to transition to normal RX and 0 to stay in the scheduled RX. */ uint8_t rxTransitionEndSchedule; /** * If set to 0, this will allow any packets, which are received when the * window end event occurs, to complete. If set to anything else, an abort * of any packets received when the window end occurs is forced. */ uint8_t hardWindowEnd; } RAIL_ScheduleRxConfig_t; /** * @enum RAIL_RxPacketStatus_t * @brief The packet status code associated with a packet received or * currently being received. * * @note RECEIVING implies some packet data may be available, but * is untrustworthy (not CRC-verified) and might disappear if the packet * is rolled back on error. No packet details are yet available. * @note In RX \ref RAIL_DataMethod_t::FIFO_MODE, ABORT statuses imply some * packet data may be available, but it's incomplete and not trustworthy. */ RAIL_ENUM(RAIL_RxPacketStatus_t) { RAIL_RX_PACKET_NONE = 0, /**< The radio is idle or searching for a packet. */ RAIL_RX_PACKET_ABORT_FORMAT, /**< A format/length error. */ RAIL_RX_PACKET_ABORT_FILTERED, /**< A filtering error (address). */ RAIL_RX_PACKET_ABORT_ABORTED, /**< An aborted error. */ RAIL_RX_PACKET_ABORT_OVERFLOW, /**< The receive buffer overflowed. */ RAIL_RX_PACKET_ABORT_CRC_ERROR, /**< A CRC error aborted. */ RAIL_RX_PACKET_READY_CRC_ERROR, /**< A CRC error accepted. */ RAIL_RX_PACKET_READY_SUCCESS, /**< Success. */ RAIL_RX_PACKET_RECEIVING, /**< Receiving in progress. */ }; #ifndef DOXYGEN_SHOULD_SKIP_THIS // Self-referencing defines minimize compiler complaints when using RAIL_ENUM #define RAIL_RX_PACKET_NONE ((RAIL_RxPacketStatus_t) RAIL_RX_PACKET_NONE) #define RAIL_RX_PACKET_ABORT_FORMAT ((RAIL_RxPacketStatus_t) RAIL_RX_PACKET_ABORT_FORMAT) #define RAIL_RX_PACKET_ABORT_FILTERED ((RAIL_RxPacketStatus_t) RAIL_RX_PACKET_ABORT_FILTERED) #define RAIL_RX_PACKET_ABORT_ABORTED ((RAIL_RxPacketStatus_t) RAIL_RX_PACKET_ABORT_ABORTED) #define RAIL_RX_PACKET_ABORT_OVERFLOW ((RAIL_RxPacketStatus_t) RAIL_RX_PACKET_ABORT_OVERFLOW) #define RAIL_RX_PACKET_ABORT_CRC_ERROR ((RAIL_RxPacketStatus_t) RAIL_RX_PACKET_ABORT_CRC_ERROR) #define RAIL_RX_PACKET_READY_CRC_ERROR ((RAIL_RxPacketStatus_t) RAIL_RX_PACKET_READY_CRC_ERROR) #define RAIL_RX_PACKET_READY_SUCCESS ((RAIL_RxPacketStatus_t) RAIL_RX_PACKET_READY_SUCCESS) #define RAIL_RX_PACKET_RECEIVING ((RAIL_RxPacketStatus_t) RAIL_RX_PACKET_RECEIVING) #endif//DOXYGEN_SHOULD_SKIP_THIS /** * @typedef RAIL_RxPacketHandle_t * @brief A handle used to reference a packet during reception processing. * There are several sentinel handle values that pertain to certain * circumstances: \ref RAIL_RX_PACKET_HANDLE_INVALID, \ref * RAIL_RX_PACKET_HANDLE_OLDEST and \ref RAIL_RX_PACKET_HANDLE_NEWEST. */ typedef const void *RAIL_RxPacketHandle_t; /** An invalid RX packet handle value. */ #define RAIL_RX_PACKET_HANDLE_INVALID (NULL) /** A special RX packet handle to refer to the oldest unreleased packet. */ #define RAIL_RX_PACKET_HANDLE_OLDEST ((RAIL_RxPacketHandle_t) 1) /** A special RX packet handle to refer to the newest unreleased packet * when in callback context. For a callback involving a completed * receive event, this refers to the packet just completed. For * other callback events, this refers to the next packet to be * completed, which might be in-progress or might not have even * started yet. */ #define RAIL_RX_PACKET_HANDLE_NEWEST ((RAIL_RxPacketHandle_t) 2) /** * @struct RAIL_RxPacketInfo_t * @brief Basic information about a packet being received or already * completed and awaiting processing, including memory pointers to * its data in the circular receive FIFO buffer. This packet information * refers to remaining packet data that has not already been consumed * by RAIL_ReadRxFifo(). * @note Because the receive FIFO buffer is circular, a packet might start * near the end of the buffer and wrap around to the beginning of * the buffer to finish, hence the distinction between the first * and last portions. Packets that fit without wrapping only have * a first portion (firstPortionBytes == packetBytes and lastPortionData * will be NULL). */ typedef struct RAIL_RxPacketInfo { RAIL_RxPacketStatus_t packetStatus; /**< The packet status of this packet. */ uint16_t packetBytes; /**< The number of packet data bytes available to read in this packet. */ uint16_t firstPortionBytes; /**< The number of bytes in the first portion. */ uint8_t *firstPortionData; /**< The pointer to the first portion of packet data containing firstPortionBytes number of bytes. */ uint8_t *lastPortionData; /**< The pointer to the last portion of a packet, if any; NULL otherwise. The number of bytes in this portion is packetBytes - firstPortionBytes. */ } RAIL_RxPacketInfo_t; /** * @struct RAIL_RxPacketDetails_t * @brief Received packet details obtained via RAIL_GetRxPacketDetails() * or RAIL_GetRxPacketDetailsAlt(). * * @note Certain details are always available, while others are only available * if the \ref RAIL_RxOptions_t \ref RAIL_RX_OPTION_REMOVE_APPENDED_INFO * option is not in effect and the received packet's * \ref RAIL_RxPacketStatus_t is among the RAIL_RX_PACKET_READY_ set. * Each detail's description indicates its availability. * */ typedef struct RAIL_RxPacketDetails { /** * The timestamp of the received packet in the RAIL timebase. * When not available it will be \ref RAIL_PACKET_TIME_INVALID. */ RAIL_PacketTimeStamp_t timeReceived; /** * Indicates whether the CRC passed or failed for the received packet. * It is true for \ref RAIL_RX_PACKET_READY_SUCCESS packets and false * for all others. * It is always available. */ bool crcPassed; /** * Indicates whether the received packet is an ACK. An 'ACK' is defined as a * packet received during the RX ACK window when auto ACK is enabled. * Set to 0 if not an ACK, and 1 for an ACK. It is always 0 if * auto ACK is not enabled. * It is always available. */ bool isAck; /** * RSSI of the received packet in integer dBm. It is latched when the sync * word is detected for the packet. * When not available it will be \ref RAIL_RSSI_INVALID_DBM. */ int8_t rssi; /** * The link quality indicator of the received packet. It is calculated as the * average correlation for the first 8 symbols in a frame. * When not available it will be 0. */ uint8_t lqi; /** * For radios and PHY configurations that support multiple sync words, this * number is the ID of the sync word that was used for this packet. * It is always available. */ uint8_t syncWordId; /** * In configurations where the radio has the option of receiving a given * packet in multiple ways, indicates which of the sub-PHY options * was used to receive the packet. Most radio configurations do not have * this ability and the subPhy is set to 0. * It is always available. */ uint8_t subPhyId; /** * For \ref Antenna_Control configurations where the device has multiple * antennas, this indicates which antenna received the packet. When there * is only one antenna, this will be set to the default of 0. * It is always available. */ uint8_t antennaId; /** * When channel hopping is enabled, this field will contain the index * of the channel in RAIL_RxChannelHoppingConfig_t::entries on which * this packet was received, or a sentinel value. On EFR32XG1 parts, * on which channel hopping is not supported, this value is still part * of the structure, but will be a meaningless value. */ uint8_t channelHoppingChannelIndex; } RAIL_RxPacketDetails_t; /** * @addtogroup Address_Filtering * @{ */ /// A default address filtering match table for configurations that use only one /// address field. The truth table for address matching is shown below. /// /// | | No Match | Address 0 | Address 1 | Address 2 | Address 3 | /// |----------------|----------|-----------|-----------|-----------|-----------| /// | __No Match__ | 0 | 1 | 1 | 1 | 1 | /// | __Address 0__ | 1 | 1 | 1 | 1 | 1 | /// | __Address 1__ | 1 | 1 | 1 | 1 | 1 | /// | __Address 2__ | 1 | 1 | 1 | 1 | 1 | /// | __Address 3__ | 1 | 1 | 1 | 1 | 1 | /// #define ADDRCONFIG_MATCH_TABLE_SINGLE_FIELD (0x1fffffe) /// A default address filtering match table for configurations that use two /// address fields and want to match the same index in each. The truth /// table for address matching is shown below. /// /// | | No Match | Address 0 | Address 1 | Address 2 | Address 3 | /// |----------------|----------|-----------|-----------|-----------|-----------| /// | __No Match__ | 0 | 0 | 0 | 0 | 0 | /// | __Address 0__ | 0 | 1 | 0 | 0 | 0 | /// | __Address 1__ | 0 | 0 | 1 | 0 | 0 | /// | __Address 2__ | 0 | 0 | 0 | 1 | 0 | /// | __Address 3__ | 0 | 0 | 0 | 0 | 1 | #define ADDRCONFIG_MATCH_TABLE_DOUBLE_FIELD (0x1041040) /// The maximum number of address fields that can be used by the address /// filtering logic. #define ADDRCONFIG_MAX_ADDRESS_FIELDS (2) /** * @struct RAIL_AddrConfig_t * @brief A structure to configure the address filtering functionality in RAIL. */ typedef struct RAIL_AddrConfig { /** * A list of the start offsets for each field. * * These offsets are specified relative to the previous field's end. * For the first field, it is relative to either the beginning of the packet * or the end of the frame type byte if frame type decoding is enabled. If a * field is unused, it's offset should be set to 0. */ uint8_t offsets[ADDRCONFIG_MAX_ADDRESS_FIELDS]; /** * A list of the address field sizes. * * These sizes are specified in bytes from 0 to 8. If you choose a * size of 0, this field is effectively disabled. */ uint8_t sizes[ADDRCONFIG_MAX_ADDRESS_FIELDS]; /** * The truth table to determine how the two fields combine to create a match. * * For detailed information about how this truth table is formed, see the * detailed description of \ref Address_Filtering. * * For simple predefined configurations use the following defines. * - ADDRCONFIG_MATCH_TABLE_SINGLE_FIELD * - For filtering that only uses a single address field. * - ADDRCONFIG_MATCH_TABLE_DOUBLE_FIELD for two field filtering where you * - For filtering that uses two address fields in a configurations where * you want the following logic `((Field0, Index0) && (Field1, Index0)) * || ((Field0, Index1) && (Field1, Index1)) || ...` */ uint32_t matchTable; } RAIL_AddrConfig_t; /** @} */ // end of group Address_Filtering /** @} */ // end of group Receive /** * @addtogroup Auto_Ack * @{ */ /** * @struct RAIL_AutoAckConfig_t * @brief Enables/disables the auto-ACK algorithm, based on "enable". * * The structure provides a default state (the "success" of tx/rxTransitions * when ACKing is enabled) for the radio to return to after an ACK * operation occurs (transmitting or attempting to receive an ACK), or normal * state transitions to return to in the case ACKing is * disabled. Regardless whether the ACK operation was successful, the * radio returns to the specified success state. * * ackTimeout specifies how long to stay in receive and wait for an ACK * before issuing a RAIL_EVENT_RX_ACK_TIMEOUT event and return to the * default state. */ typedef struct RAIL_AutoAckConfig { /** * Indicates whether auto-ACKing should be enabled or disabled. */ bool enable; /** * Defines the RX ACK timeout duration in us. Limited to a maximum 65535 us. * Only applied when auto-ACKing is enabled. Triggers a * RAIL_EVENT_RX_ACK_TIMEOUT event if this threshold is exceeded. */ uint16_t ackTimeout; /** * State transitions to do after receiving a packet. When auto-ACKing is * enabled, the "error" transition is always ignored and the radio will * return to the "success" state after any ACKing sequence. See * \ref RAIL_ConfigAutoAck for more details on this. */ RAIL_StateTransitions_t rxTransitions; /** * State transitions to do after transmitting a packet. When auto-ACKing is * enabled, the "error" transition is always ignored and the radio will * return to the "success" state after any ACKing sequence. See * \ref RAIL_ConfigAutoAck for more details on this. */ RAIL_StateTransitions_t txTransitions; } RAIL_AutoAckConfig_t; /// Acknowledgment packets cannot be longer than 64 bytes. #define RAIL_AUTOACK_MAX_LENGTH 64 /** @} */ // end of group Auto_Ack /****************************************************************************** * Calibration Structures *****************************************************************************/ /** * @addtogroup Calibration * @{ */ /** * @typedef RAIL_CalMask_t * @brief A calibration mask type * * This type is a bitmask of different RAIL calibration values. The exact * meaning of these bits depends on what a particular chip supports. */ typedef uint32_t RAIL_CalMask_t; /** @} */ // end of group Calibration /****************************************************************************** * LQI Structures *****************************************************************************/ /** * @addtogroup Receive * @{ */ /** * @typedef RAIL_ConvertLqiCallback_t * @brief A pointer to a funcation called before LQI is copied into the * \ref RAIL_RxPacketDetails_t structure. * * @param[in] lqi The LQI value obtained by hardware and being readied for * application consumption. This LQI value is in integral units ranging from * 0 to 255. * @param[in] rssi The RSSI value corresponding to the packet from which the * hardware LQI value was obtained. This RSSI value is in integral dBm units. * @return uint8_t The converted LQI value that will be loaded into the * \ref RAIL_RxPacketDetails_t structure in preparation for application * consumption. This value should likewise be in integral units ranging from * 0 to 255. */ typedef uint8_t (*RAIL_ConvertLqiCallback_t)(uint8_t lqi, int8_t rssi); /** @} */ // end of group Receive /****************************************************************************** * RF Sense Structures *****************************************************************************/ /** * @addtogroup Rf_Sense * @{ */ /** * A pointer to an RF Sense callback function. */ typedef void (*RAIL_RfSense_CallbackPtr_t)(void); /** * @enum RAIL_RfSenseBand_t * @brief An enumeration for specifying the RF Sense frequency band. */ RAIL_ENUM(RAIL_RfSenseBand_t) { RAIL_RFSENSE_OFF, /**< RF Sense is disabled. */ RAIL_RFSENSE_2_4GHZ, /**< RF Sense is in 2.4 G band. */ RAIL_RFSENSE_SUBGHZ, /**< RF Sense is in subgig band. */ RAIL_RFSENSE_ANY, /**< RF Sense is in both bands. */ RAIL_RFSENSE_MAX // Must be last. }; #ifndef DOXYGEN_SHOULD_SKIP_THIS // Self-referencing defines minimize compiler complaints when using RAIL_ENUM #define RAIL_RFSENSE_OFF ((RAIL_RfSenseBand_t) RAIL_RFSENSE_OFF) #define RAIL_RFSENSE_2_4GHZ ((RAIL_RfSenseBand_t) RAIL_RFSENSE_2_4GHZ) #define RAIL_RFSENSE_SUBGHZ ((RAIL_RfSenseBand_t) RAIL_RFSENSE_SUBGHZ) #define RAIL_RFSENSE_ANY ((RAIL_RfSenseBand_t) RAIL_RFSENSE_ANY) #define RAIL_RFSENSE_MAX ((RAIL_RfSenseBand_t) RAIL_RFSENSE_MAX) #endif//DOXYGEN_SHOULD_SKIP_THIS /** @} */ // end of group Rf_Sense /****************************************************************************** * RX Channel Hopping *****************************************************************************/ /** * @addtogroup Rx_Channel_Hopping RX Channel Hopping * @{ */ /** * @enum RAIL_RxChannelHoppingMode_t * @brief Modes by which RAIL can determine when to proceed to the next * channel during channel hopping */ RAIL_ENUM(RAIL_RxChannelHoppingMode_t) { /** * Switch to the next channel each time the radio enters RX. */ RAIL_RX_CHANNEL_HOPPING_MODE_MANUAL, /** * Switch to the next channel after a certain amount of time passes. * The time should be specified in microseconds in * RAIL_RxChannelHoppingConfigEntry::parameter. */ RAIL_RX_CHANNEL_HOPPING_MODE_TIMEOUT, /** * Listen in receive RX for at least a specified timeout. If, * by the end of the timeout, the radio has packet timing, * remain in the current channel until the radio loses it. The * timeout should be specified in microseconds in * RAIL_RxChannelHoppingConfigEntry::parameter. */ RAIL_RX_CHANNEL_HOPPING_MODE_TIMING_SENSE, /** * Listen in receive RX for at least a specified timeout. If, * by the end of the timeout, the radio has a packet preamble, * remain in the current channel until the radio loses it. The * timeout should be specified in microseconds in * RAIL_RxChannelHoppingConfigEntry::parameter. */ RAIL_RX_CHANNEL_HOPPING_MODE_PREAMBLE_SENSE, }; #ifndef DOXYGEN_SHOULD_SKIP_THIS // Self-referencing defines minimize compiler complaints when using RAIL_ENUM #define RAIL_RX_CHANNEL_HOPPING_MODE_MANUAL ((RAIL_RxChannelHoppingMode_t) RAIL_RX_CHANNEL_HOPPING_MODE_MANUAL) #define RAIL_RX_CHANNEL_HOPPING_MODE_TIMEOUT ((RAIL_RxChannelHoppingMode_t) RAIL_RX_CHANNEL_HOPPING_MODE_TIMEOUT) #define RAIL_RX_CHANNEL_HOPPING_MODE_TIMING_SENSE ((RAIL_RxChannelHoppingMode_t) RAIL_RX_CHANNEL_HOPPING_MODE_TIMING_SENSE) #define RAIL_RX_CHANNEL_HOPPING_MODE_PREAMBLE_SENSE ((RAIL_RxChannelHoppingMode_t) RAIL_RX_CHANNEL_HOPPING_MODE_PREAMBLE_SENSE) #endif//DOXYGEN_SHOULD_SKIP_THIS /** * @enum RAIL_RxChannelHoppingDelayMode_t * @brief Modes by which RAIL_RxChannelHoppingConfigEntry_t::delay * timing can be applied to the time gap between channels. */ RAIL_ENUM(RAIL_RxChannelHoppingDelayMode_t) { /** * Always delay for exactly the amount of time specified * in the delay parameter, regardless of how other channel * hopping channels were extended via preamble sense or other means. */ RAIL_RX_CHANNEL_HOPPING_DELAY_MODE_STATIC, }; #ifndef DOXYGEN_SHOULD_SKIP_THIS // Self-referencing defines minimize compiler complaints when using RAIL_ENUM #define RAIL_RX_CHANNEL_HOPPING_DELAY_MODE_STATIC ((RAIL_RxChannelHoppingDelayMode_t) RAIL_RX_CHANNEL_HOPPING_DELAY_MODE_STATIC) #endif//DOXYGEN_SHOULD_SKIP_THIS /** * @struct RAIL_RxChannelHoppingConfigEntry_t * @brief Structure that represents one of the channels that is part of a sequence * of channels used in channel hopping. */ typedef struct RAIL_RxChannelHoppingConfigEntry { /** * The channel number to be used for this entry in the channel hopping * sequence. If this is an invalid channel for the current phy, the * call to RAIL_ConfigRxChannelHopping will fail. */ uint16_t channel; /** The mode by which RAIL determines when to hop to the next channel. */ RAIL_RxChannelHoppingMode_t mode; /** * Depending on the 'mode' parameter that was specified, this member * is used to parameterize that mode. See the comments on each value of * \ref RAIL_RxChannelHoppingMode_t to learn what to specify here. */ uint32_t parameter; /** * Idle time in microseconds to wait before hopping to the next channel. */ uint32_t delay; /** * Indicate how the timing specified in 'delay' should be applied. */ RAIL_RxChannelHoppingDelayMode_t delayMode; } RAIL_RxChannelHoppingConfigEntry_t; /** * @struct RAIL_RxChannelHoppingConfig_t * @brief Wrapper struct that will contain the sequence of * \ref RAIL_RxChannelHoppingConfig_t that represent the channel sequence * to use during RX Channel Hopping. */ typedef struct RAIL_RxChannelHoppingConfig { /** * Pointer to contiguous memory that will be used to store channel * hopping information. Since the RAIL library uses this space for * its own calculations and processing, application level code * should never write data into anywhere in this buffer. * * @note: the size of this buffer must be at least as large as * 3 + 30 * numberOfChannels, plus the sum of the sizes of the * radioConfigDeltaAdd's of the required channels, plus the size of the * radioConfigDeltaSubtract. In the case that one channel * appears two or more times in your channel sequence * (e.g. 1, 2, 1, 3), you must account for the radio config * size that number of times (i.e. need to count channel 1's * radio config size twice for the given example). The overall * 3 words and 30 words per channel needed in this buffer are * for internal use to the library. */ uint32_t *buffer; /** * This parameter must be set to the length of the buffer array. This way, * during configuration, the software can confirm it's writing within the * range of the buffer. The configuration API will return an error * if bufferLength is insufficient. */ uint16_t bufferLength; /** The number of channels that is in the channel hopping sequence. */ uint8_t numberOfChannels; /** * An array of \ref RAIL_RxChannelHoppingConfig_t to represent the channels * used during channel hopping. The length of this array must be * numberOfChannels */ RAIL_RxChannelHoppingConfigEntry_t *entries; } RAIL_RxChannelHoppingConfig_t; /** * @struct RAIL_RxDutyCycleConfig_t * @brief Structure to configure duty cycled receive mode. */ typedef struct RAIL_RxDutyCycleConfig { /** The mode by which RAIL determines when to exit RX. */ RAIL_RxChannelHoppingMode_t mode; /** * Depending on the 'mode' parameter that was specified, this member * is used to parameterize that mode. See the comments on each value of * \ref RAIL_RxChannelHoppingMode_t to learn what to specify here. */ uint32_t parameter; /** * Idle time in microseconds to wait before re-entering RX. */ uint32_t delay; /** * Indicate how the timing specified in 'delay' should be applied. */ RAIL_RxChannelHoppingDelayMode_t delayMode; } RAIL_RxDutyCycleConfig_t; /// A sentinel value to flag an invalid channel hopping index. #define RAIL_CHANNEL_HOPPING_INVALID_INDEX (0xFEU) /** @} */ // end of group Rx_Channel_Hopping /****************************************************************************** * Diagnositc Structures *****************************************************************************/ /** * @addtogroup Diagnostic * @{ */ /** * @enum RAIL_StreamMode_t * @brief Possible stream output modes. */ RAIL_ENUM(RAIL_StreamMode_t) { RAIL_STREAM_CARRIER_WAVE = 0, /**< An unmodulated carrier wave. */ RAIL_STREAM_PN9_STREAM = 1, /**< PN9 byte sequence. */ }; #ifndef DOXYGEN_SHOULD_SKIP_THIS // Self-referencing defines minimize compiler complaints when using RAIL_ENUM #define RAIL_STREAM_CARRIER_WAVE ((RAIL_StreamMode_t) RAIL_STREAM_CARRIER_WAVE) #define RAIL_STREAM_PN9_STREAM ((RAIL_StreamMode_t) RAIL_STREAM_PN9_STREAM) #endif//DOXYGEN_SHOULD_SKIP_THIS /** * @def RAIL_VERIFY_DURATION_MAX * @brief This radio state verification duration indicates to RAIL that * all memory contents should be verified by RAIL before returning to the * application. */ #define RAIL_VERIFY_DURATION_MAX 0xFFFFFFFFUL /** * A pointer to a verification callback function. This will be called by the * radio state verification feature built into RAIL when a verified memory * value is different from its reference value. * * @param[in] address The address of the data in question. * @param[in] expectedValue The expected value of the data in question. * @param[in] actualValue The actual value of the data in question. * @return bool True indicates a data value difference is acceptable. False * indicates a data value difference in unacceptable. * * @note This callback will be issued when an address' value is different from * its reference value and either of the following conditions are met: * 1) The default radio configuration provided by the radio configurator is used * for verification purposes (i.e., a custom radio configuration is not supplied * as an input to \ref RAIL_ConfigVerification()), and the radio * configurator has flagged the address under question as being verifiable. * 2) A custom radio configuration is provided to the verification API (i.e., * a custom radio configuration is supplied as an input to \ref * RAIL_ConfigVerification()). When providing a custom radio configuration for * verification purposes, all addresses in that configuration will be verified, * regardless of whether or not the addresses are flagged as verifiable. */ typedef bool (*RAIL_VerifyCallbackPtr_t)(uint32_t address, uint32_t expectedValue, uint32_t actualValue); /** * @struct RAIL_VerifyConfig_t * @brief The configuration array provided to RAIL for use by the radio state * verification feature. This structure will be populated with appropriate * values by calling \ref RAIL_ConfigVerification(). The application should * not set or alter any of these structure elements. */ typedef struct RAIL_VerifyConfig { /** Internal verification tracking information. */ RAIL_Handle_t correspondingHandle; /** Internal verification tracking information. */ uint32_t nextIndexToVerify; /** Internal verification tracking information. */ const uint32_t *override; /** Internal verification tracking information. */ RAIL_VerifyCallbackPtr_t cb; } RAIL_VerifyConfig_t; #ifndef DOXYGEN_SHOULD_SKIP_THIS typedef struct RAIL_DirectModeConfig { bool enable; /**< Indicates whether to enable direct mode. */ } RAIL_DirectModeConfig_t; #endif//DOXYGEN_SHOULD_SKIP_THIS /** @} */ // end of group Diagnostic #ifndef DOXYGEN_SHOULD_SKIP_THIS /****************************************************************************** * Debug Structures *****************************************************************************/ /** * @addtogroup Debug * @{ */ /** * @def RAIL_DEBUG_MODE_FREQ_OVERRIDE * @brief A bitmask to enable the frequency override debug mode to * manually tune to a specified frequency. Note that this should only be used * for testing and is not as tuned as frequencies from the calculator. */ #define RAIL_DEBUG_MODE_FREQ_OVERRIDE 0x00000001UL /** * @def RAIL_DEBUG_MODE_VALID_MASK * @brief Any debug mode bits outside of this mask are invalid and ignored. */ #define RAIL_DEBUG_MODE_VALID_MASK (!(RAIL_DEBUG_MODE_FREQ_OVERRIDE)) /** @} */ // end of group Debug #endif//DOXYGEN_SHOULD_SKIP_THIS /** * @} * end of RAIL_API */ #ifdef __cplusplus } #endif #endif // __RAIL_TYPES_H__ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/radio/rail_lib/protocol/ble/rail_ble.h.
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/***************************************************************************//** * @file * @brief The BLE specific header file for the RAIL library. ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * The licensor of this software is Silicon Laboratories Inc. Your use of this * software is governed by the terms of Silicon Labs Master Software License * Agreement (MSLA) available at * www.silabs.com/about-us/legal/master-software-license-agreement. This * software is distributed to you in Source Code format and is governed by the * sections of the MSLA applicable to Source Code. * ******************************************************************************/ #ifndef __RAIL_BLE_H__ #define __RAIL_BLE_H__ // Get the standard include types #include <stdint.h> #include <stdbool.h> // Get the RAIL specific structures and types #include "rail_types.h" #ifdef __cplusplus extern "C" { #endif /// @addtogroup BLE /// @ingroup Protocol_Specific /// Accelerator routines for Bluetooth Low Energy (BLE). /// /// The APIs in this module configure the radio for BLE /// operation and provide additional helper routines necessary for /// normal BLE send/receive that aren't available directly in RAIL. /// RAIL APIs should be used to set up the application. However, /// RAIL_ConfigChannels() and RAIL_ConfigRadio() should not be called to set up /// the PHY. Instead, RAIL_BLE_Config* APIs should be used to set up the /// 1 Mbps, 2 Mbps, or Coded PHY configurations needed by the application. These /// APIs will configure the hardware and also configure the set of valid BLE /// channels. /// /// To implement a standard BLE link layer, you will also need to handle tight /// turnaround times and send packets at specific instants. This can all be /// managed through general RAIL functions, such as RAIL_ScheduleTx(), /// RAIL_ScheduleRx(), and RAIL_SetStateTiming(). See RAIL APIs for more /// useful functions. /// /// A simple example to set up the application to be in BLE mode is shown /// below. Note that this will put the radio on the first advertising channel /// with the advertising Access Address. In any full-featured BLE application you /// will need to use the RAIL_BLE_ConfigChannelRadioParams() function to change /// the sync word and other parameters as needed based on your connection. /// /// @code{.c} /// /// // RAIL Handle set at initialization time. /// static RAIL_Handle_t gRailHandle = NULL; /// /// static void radioEventHandler(RAIL_Handle_t railHandle, /// RAIL_Events_t events) /// { /// // ... handle RAIL events, e.g., receive and transmit completion /// } /// /// #if MULTIPROTOCOL /// // Allocate memory for RAIL to hold BLE-specific state information /// static RAIL_BLE_State_t bleState; // Must never be const /// static RAILSched_Config_t schedCfg; // Must never be const /// static RAIL_Config_t railCfg = { // Must never be const /// .eventsCallback = &radioEventHandler, /// .protocol = &bleState, // For BLE, RAIL needs additional state memory /// .scheduler = &schedCfg, // For MultiProtocol, additional scheduler memory /// }; /// #else /// static RAIL_Config_t railCfg = { // Must never be const /// .eventsCallback = &radioEventHandler, /// .protocol = NULL, /// .scheduler = NULL, /// }; /// #endif /// /// // Set the radio to receive on the first BLE advertising channel. /// int bleAdvertiseEnable(void) /// { /// // Initializes the RAIL library and any internal state it requires. /// gRailHandle = RAIL_Init(&railCfg, NULL); /// /// // Calls the BLE initialization function to load the right radio configuration. /// RAIL_BLE_Init(gRailHandle); /// /// // Always choose the Viterbi PHY configuration if available on your chip /// // for performance reasons. /// RAIL_BLE_ConfigPhy1MbpsViterbi(gRailHandle); /// /// // Configures us for the first advertising channel (Physical: 0, Logical: 37). /// // The CRC init value and Access Address come from the BLE specification. /// RAIL_BLE_ConfigChannelRadioParams(gRailHandle, /// 0x555555, /// 0x8E89BED6, /// 37, /// false); /// /// // Starts receiving on physical channel 0 (logical channel 37). /// RAIL_StartRx(gRailHandle, 0, NULL); /// } /// @endcode /// /// @{ /** * @enum RAIL_BLE_Coding_t * @brief The variant of the BLE Coded PHY. */ RAIL_ENUM(RAIL_BLE_Coding_t) { /** Enables the 125 kbps variant of the BLE Coded PHY */ RAIL_BLE_Coding_125kbps = 0, /** \deprecated Will be removed in a future version of RAIL */ RAIL_BLE_Coding_125kbps_DSA = 1, /** Enables the 500 kbps variant of the BLE Coded PHY */ RAIL_BLE_Coding_500kbps = 2, /** \deprecated Will be removed in a future version of RAIL */ RAIL_BLE_Coding_500kbps_DSA = 3, }; #ifndef DOXYGEN_SHOULD_SKIP_THIS // Self-referencing defines minimize compiler complaints when using RAIL_ENUM #define RAIL_BLE_Coding_125kbps ((RAIL_BLE_Coding_t) RAIL_BLE_Coding_125kbps) #define RAIL_BLE_Coding_125kbps_DSA ((RAIL_BLE_Coding_t) RAIL_BLE_Coding_125kbps_DSA) #define RAIL_BLE_Coding_500kbps ((RAIL_BLE_Coding_t) RAIL_BLE_Coding_500kbps) #define RAIL_BLE_Coding_500kbps_DSA ((RAIL_BLE_Coding_t) RAIL_BLE_Coding_500kbps_DSA) #endif//DOXYGEN_SHOULD_SKIP_THIS /** * @enum RAIL_BLE_Phy_t * @brief The variant of the BLE PHY. */ RAIL_ENUM(RAIL_BLE_Phy_t) { /** Use the standard BLE 1Mbps PHY */ RAIL_BLE_1Mbps, /** Use the high data rate BLE 2Mbps PHY */ RAIL_BLE_2Mbps, /** Enables the 125 kbps variant of the BLE Coded PHY */ RAIL_BLE_Coded125kbps, /** Enables the 500 kbps variant of the BLE Coded PHY */ RAIL_BLE_Coded500kbps, }; /** * @struct RAIL_BLE_State_t * @brief A state structure for BLE. * * This structure must be allocated in application global read-write memory * that persists for the duration of BLE usage. It cannot be allocated * in read-only memory or on the call stack. */ typedef struct RAIL_BLE_State { uint32_t crcInit; /**< The value used to initialize the CRC algorithm. */ uint32_t accessAddress; /**< The access address used for the connection. */ uint16_t channel; /**< The logical channel used. */ bool disableWhitening; /**< Indicates whether the whitening engine should be off. */ } RAIL_BLE_State_t; /** * Configures RAIL to run in BLE mode. * * @param[in] railHandle A handle for RAIL instance. * This function will change your radio, channel configuration, and other * parameters to match what is needed for BLE. To switch back to a * default RAIL mode, call RAIL_BLE_Deinit() first. This function * will configure the protocol output on PTI to \ref RAIL_PTI_PROTOCOL_BLE. */ void RAIL_BLE_Init(RAIL_Handle_t railHandle); /** * Takes RAIL out of BLE mode. * * @param[in] railHandle A handle for RAIL instance. * This function will undo some of the configuration that happens when you call * RAIL_BLE_Init(). After this you can safely run your normal radio * initialization code to use a non-BLE configuration. This function will \b * not change back your radio or channel configurations so you must do this by * manually reinitializing. This also resets the protocol output on PTI to \ref * RAIL_PTI_PROTOCOL_CUSTOM. */ void RAIL_BLE_Deinit(RAIL_Handle_t railHandle); /** * Determines whether BLE mode is enabled or not. * * @param[in] railHandle A handle for RAIL instance. * @return True if BLE mode is enabled and false otherwise. * This function returns the current status of RAIL's BLE mode. It is enabled by * a call to RAIL_BLE_Init() and disabled by a call to RAIL_BLE_Deinit(). */ bool RAIL_BLE_IsEnabled(RAIL_Handle_t railHandle); /** * Switches the Viterbi 1 Mbps BLE PHY. * * @param[in] railHandle A handle for RAIL instance. * @return A status code indicating success of the function call. * * Use this function to switch back to the defualt BLE 1 Mbps PHY if you * have switched to the 2 Mbps or another configuration. You may only call this * function after initializing BLE and while the radio is idle. * * @note The EFR32XG1 family does not support BLE Viterbi PHYs, however calls * to this function from that family will be silently redirected to the legacy * \ref RAIL_BLE_ConfigPhy1Mbps(). */ RAIL_Status_t RAIL_BLE_ConfigPhy1MbpsViterbi(RAIL_Handle_t railHandle); /** * Switches the legacy non-Viterbi 1 Mbps BLE PHY. * * @param[in] railHandle A handle for RAIL instance. * @return A status code indicating success of the function call. * * You can use this function to switch back to the legacy BLE 1 Mbps PHY if you * have switched to the 2 Mbps or another configuration. You may only call this * function after initializing BLE and while the radio is idle. * * @note The EFR32XG2x family does not support BLE non-Viterbi PHYs. */ RAIL_Status_t RAIL_BLE_ConfigPhy1Mbps(RAIL_Handle_t railHandle); /** * Switches the Viterbi 2 Mbps BLE PHY. * * @param[in] railHandle A handle for RAIL instance. * @return A status code indicating success of the function call. * * You can use this function to switch back to the BLE 2 Mbps PHY from the * default 1 Mbps option. You may only call this function after initializing BLE * and while the radio is idle. * * @note The EFR32XG1 family does not support BLE Viterbi PHYs. */ RAIL_Status_t RAIL_BLE_ConfigPhy2MbpsViterbi(RAIL_Handle_t railHandle); /** * Switches the legacy non-Viterbi 2 Mbps BLE PHY. * * @param[in] railHandle A handle for RAIL instance. * @return A status code indicating success of the function call. * * Use this function to switch back to legacy BLE 2Mbps PHY from the * default 1 Mbps option. You may only call this function after initializing BLE * and while the radio is idle. * * @note The EFR32XG1 and EFR32XG2x families do not support BLE non-Viterbi * 2 Mbps PHY. */ RAIL_Status_t RAIL_BLE_ConfigPhy2Mbps(RAIL_Handle_t railHandle); /** * Switches to the BLE Coded PHY. * * @param[in] railHandle A handle for RAIL instance. * @param[in] bleCoding The RAIL_BLE_Coding_t to use * @return A status code indicating success of the function call. * * Use this function to switch back to BLE Coded PHY from the default * 1 Mbps option. You may only call this function after initializing BLE and * while the radio is idle. When using a BLE Coded PHY, the subPhy in * RAIL_AppendedInfo_t marks the coding of the received packet. A subPhy of 0 * marks a 500 kbps packet, and a subPhy of 1 marks a 125 kbps packet. * * @note The EFR32XG1, EFR32XG12, and EFR32XG14 families do not support BLE * Coded PHYs. */ RAIL_Status_t RAIL_BLE_ConfigPhyCoded(RAIL_Handle_t railHandle, RAIL_BLE_Coding_t bleCoding); /** * Helper function to change BLE radio parameters. * * @param[in] railHandle A handle for RAIL instance. * @param[in] crcInit The value to use for CRC initialization. * @param[in] accessAddress The access address to use for the connection. * @param[in] channel The logical channel that you're changing to, which * initializes the whitener if used. * @param[in] disableWhitening This can turn off the whitening engine and is useful * for sending BLE test mode packets that don't have this turned on. * @return A status code indicating success of the function call. * * This function can be used to switch radio parameters on every connection * and/or channel change. It is BLE-aware and will set the access address, * preamble, CRC initialization value, and whitening configuration without * requiring you to load a new radio configuration. */ RAIL_Status_t RAIL_BLE_ConfigChannelRadioParams(RAIL_Handle_t railHandle, uint32_t crcInit, uint32_t accessAddress, uint16_t channel, bool disableWhitening); /** * Change the current BLE PHY and go into receive * * @param[in] railHandle A handle for RAIL instance. * @param[in] phy Which PHY to receive on * @param[in] railChannel Which channel of the given PHY to receive on * @param[in] startRxTime When to enter RX * @param[in] crcInit The value to use for CRC initialization. * @param[in] accessAddress The access address to use for the connection. * @param[in] logicalChannel The logical channel that you're changing to, which * initializes the whitener if used. * @param[in] disableWhitening This can turn off the whitening engine and is useful * for sending BLE test mode packets that don't have this turned on. * @return A status code indicating success of the function call. * * This function is used to implement auxillary packet reception, as defined in * the BLE specification. The radio will be put into IDLE, the PHY and channel * will be changed, and then receive will be entered at the start time given. * The new receive will have a timeout of 30 us, which means that this function * should only be called if the offset unit is 30 us. */ RAIL_Status_t RAIL_BLE_PhySwitchToRx(RAIL_Handle_t railHandle, RAIL_BLE_Phy_t phy, uint16_t railChannel, uint32_t startRxTime, uint32_t crcInit, uint32_t accessAddress, uint16_t logicalChannel, bool disableWhitening); /****************************************************************************** * Angle of Arrival/Departure (AoX) *****************************************************************************/ /** * @addtogroup AoX Angle of Arrival/Departure * @{ * @brief These APIs are to a stack implementing BLE's angle of arrival and * angle of departure functionality. * * They are designed for use by the Silicon Labs BLE stack only at this time and * may cause problems if accessed directly. */ /** * @enum RAIL_BLE_AoxOptions_t * @brief Angle of Arrival/Departure options bit fields */ RAIL_ENUM_GENERIC(RAIL_BLE_AoxOptions_t, uint16_t) { /** Shift position of \ref RAIL_BLE_AOX_OPTIONS_DO_SWITCH bit */ RAIL_BLE_AOX_OPTIONS_DO_SWITCH_SHIFT = 0, /** Shift position of \ref RAIL_BLE_AOX_OPTIONS_RX_ENABLED bit */ RAIL_BLE_AOX_OPTIONS_RX_ENABLED_SHIFT = 1, /** Shift position of \ref RAIL_BLE_AOX_OPTIONS_SAMPLE_MODE bit */ RAIL_BLE_AOX_OPTIONS_SAMPLE_MODE_SHIFT = 2, /** Shift position of \ref RAIL_BLE_AOX_OPTIONS_TX_ENABLED bit */ RAIL_BLE_AOX_OPTIONS_TX_ENABLED_SHIFT = 3, /** Shift position of \ref RAIL_BLE_AOX_OPTIONS_CONNLESS_SHIFT bit */ RAIL_BLE_AOX_OPTIONS_CONNLESS_SHIFT = 10, /** Shift position of \ref RAIL_BLE_AOX_OPTIONS_CONN_SHIFT bit */ RAIL_BLE_AOX_OPTIONS_CONN_SHIFT = 13, }; /** * Sets one of the two AoX sampling/switching modes: 1us or 2us window. */ #define RAIL_BLE_AOX_OPTIONS_SAMPLE_MODE (1U << RAIL_BLE_AOX_OPTIONS_SAMPLE_MODE_SHIFT) /** * Enables AoX Rx packets. When enabled radio will either receive AoX packet if * CTE-present bit in the packet is set or normal packet if this bit isn't set. */ #define RAIL_BLE_AOX_OPTIONS_RX_ENABLED (1U << RAIL_BLE_AOX_OPTIONS_RX_ENABLED_SHIFT) /** * Enables antennae switching during CTE. If disabled antenna 0 will be active. * If enabled antennae will switch from 0 to N, wrapping back to 0. */ #define RAIL_BLE_AOX_OPTIONS_DO_SWITCH (1U << RAIL_BLE_AOX_OPTIONS_DO_SWITCH_SHIFT) /** * Enables AoX Tx packets. When set radio will transmit AoX packet, to * transmit normal (non-AoX) packet clear this bitfield. */ #define RAIL_BLE_AOX_OPTIONS_TX_ENABLED (1U << RAIL_BLE_AOX_OPTIONS_TX_ENABLED_SHIFT) /** * Enables connectionless AoX Rx packets. This requires \ref * RAIL_BLE_AOX_OPTIONS_RX_ENABLED to be set. */ #define RAIL_BLE_AOX_OPTIONS_CONNLESS (1U << RAIL_BLE_AOX_OPTIONS_CONNLESS_SHIFT) /** * Enables connection based AoX Rx packets. This requires \ref * RAIL_BLE_AOX_OPTIONS_RX_ENABLED to be set. */ #define RAIL_BLE_AOX_OPTIONS_CONN (1U << RAIL_BLE_AOX_OPTIONS_CONN_SHIFT) /** * @struct RAIL_BLE_AoxConfig_t * @brief Contains arguments for \ref RAIL_BLE_ConfigAox function. */ typedef struct RAIL_BLE_AoxConfig { /** * See RAIL_BLE_AOX_OPTIONS_* for bitfield defines for different AoX features. */ RAIL_BLE_AoxOptions_t aoxOptions; /** * Size of the raw AoX CTE (continuous tone extension) data capture buffer in * bytes. */ uint16_t cteBuffSize; /** * Address to where the received CTE is written. */ uint32_t * cteBuffAddr; /** * Address to first element of antenna pattern array. */ // @TODO: Can we change this to uint8_t* and make non-word-aligned // memory accesses in the sequencer? uint32_t * antArrayAddr; /** * Size of the antenna pattern array. */ uint8_t antArraySize; } RAIL_BLE_AoxConfig_t; /** * Locks/unlocks the CTE buffer from the application's perspective. The radio * will write to the buffer only if the bit is NOT set at the beginning of the * sampling period. The radio will set the bit once the sampling period starts * to indicate that some CTE data has been collected, which will not be * overwritten during the next sampling period, unless the buffer is unlocked by * the application. * * @param[in] railHandle A RAIL instance handle. * @param[in] lock Lock the CTE buffer if true and unlock it if false. * @return True if the CTE buffer is locked after the call, otherwise false. */ bool RAIL_BLE_LockCteBuffer(RAIL_Handle_t railHandle, bool lock); /** * Determines whether the CTE buffer is currently locked or not. * * @param[in] railHandle A handle for RAIL instance. * @return True if CTE buffer is locked and false otherwise. */ bool RAIL_BLE_CteBufferIsLocked(RAIL_Handle_t railHandle); /** * Configures Angle of Arrival/Departure (AoX) functionality. AoX is a method * of radio localization which infers angle of arrival/departure of the signal * based on different phases of the raw I/Q signal from different antennas by * controlling external RF switch during the continuous tone extension (CTE). * Connection based AoX packets are different than normal BLE packets in that * they have 3 header bytes instead of 2, and they have CTE appended after the * payload's CRC. 3rd byte or CTE info contains CTE length. Connectionless AoX * packets have 2 header bytes and CTE info is part of the paylod. AoX is * supported on efr32xg12/13/14 only on legacy 1Mbps BLE PHY. Note that * \ref RAIL_TX_OPTION_REMOVE_CRC_SHIFT option in \ref RAIL_TxOptions_t will * not work when \ref RAIL_BLE_AOX_OPTIONS_TX_ENABLED is enabled. Also * note that calling \ref RAIL_GetRadioEntropy during AoX reception may break * receiving packets. * * @param[in] railHandle A RAIL instance handle. * @param[in] aoxConfig Configuration options for AoX * @return RAIL_Status_t indicating success or failure of the call. */ RAIL_Status_t RAIL_BLE_ConfigAox(RAIL_Handle_t railHandle, const RAIL_BLE_AoxConfig_t *aoxConfig); /** @} */ // end of group AoX /** @} */ // end of BLE #ifdef __cplusplus } #endif #endif // __RAIL_BLE_H__ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/platform/radio/rail_lib/protocol/ieee802154/rail_ieee802154.h.
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/***************************************************************************//** * @file * @brief The IEEE 802.15.4 specific header file for the RAIL library. ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * The licensor of this software is Silicon Laboratories Inc. Your use of this * software is governed by the terms of Silicon Labs Master Software License * Agreement (MSLA) available at * www.silabs.com/about-us/legal/master-software-license-agreement. This * software is distributed to you in Source Code format and is governed by the * sections of the MSLA applicable to Source Code. * ******************************************************************************/ #ifndef __RAIL_IEEE802154_H__ #define __RAIL_IEEE802154_H__ #include "rail_types.h" #ifdef __cplusplus extern "C" { #endif /// @addtogroup IEEE802_15_4 IEEE 802.15.4 /// @ingroup Protocol_Specific /// @brief IEEE 802.15.4 configuration routines /// /// The functions in this group configure RAIL IEEE 802.15.4 hardware /// acceleration which includes IEEE 802.15.4 format filtering, address /// filtering, acking, and filtering based on the frame type. /// /// To configure IEEE 802.15.4 functionality, the application must first set up /// a RAIL instance with RAIL_Init() and other setup functions. /// Instead of RAIL_ConfigChannels(), however, an /// application may use RAIL_IEEE802154_Config2p4GHzRadio() to set up the /// official IEEE 2.4 GHz 802.15.4 PHY. This configuration is shown below. /// /// @code{.c} /// static RAIL_Handle_t railHandle = NULL; // Initialized somewhere else. /// /// static const RAIL_IEEE802154_Config_t rail154Config = { /// .addresses = NULL, /// .ackConfig = { /// .enable = true, // Turn on auto ACK for IEEE 802.15.4. /// .ackTimeout = 864, // 54 symbols * 16 us/symbol = 864 us. /// .rxTransitions = { /// .success = RAIL_RF_STATE_TX, // Go to TX to send the ACK. /// .error = RAIL_RF_STATE_RX, // For an always-on device stay in RX. /// }, /// .txTransitions = { /// .success = RAIL_RF_STATE_RX, // Go to RX for receiving the ACK. /// .error = RAIL_RF_STATE_RX, // For an always-on device stay in RX. /// }, /// }, /// .timings = { /// .idleToRx = 100, /// .idleToTx = 100, /// .rxToTx = 192, // 12 symbols * 16 us/symbol = 192 us /// .txToRx = 192, // 12 symbols * 16 us/symbol = 192 us /// .rxSearchTimeout = 0, // Not used /// .txToRxSearchTimeout = 0, // Not used /// }, /// .framesMask = RAIL_IEEE802154_ACCEPT_STANDARD_FRAMES, /// .promiscuousMode = false, // Enable format and address filtering. /// .isPanCoordinator = false, /// }; /// /// void config154(void) /// { /// // Configure the radio and channels for 2.4 GHz IEEE 802.15.4. /// RAIL_IEEE802154_Config2p4GHzRadio(railHandle); /// // Initialize the IEEE 802.15.4 configuration using the static configuration above. /// RAIL_IEEE802154_Init(railHandle, &rail154Config); /// } /// @endcode /// /// To configure address filtering, call /// RAIL_IEEE802154_SetAddresses() with a structure containing all addresses or /// call the individual RAIL_IEEE802154_SetPanId(), /// RAIL_IEEE802154_SetShortAddress(), and RAIL_IEEE802154_SetLongAddress() /// APIs. RAIL supports \ref RAIL_IEEE802154_MAX_ADDRESSES number of address /// pairs to receive packets from multiple IEEE /// 802.15.4 networks at the same time. Broadcast addresses are supported by /// default without any additional configuration so they do not consume one of /// these slots. If the application does not require all address pairs, be sure /// to set unused ones to the proper disabled value for each type. These can /// be found in the \ref RAIL_IEEE802154_AddrConfig_t documentation. Below is /// an example of setting filtering for one set of addresses. /// /// @code{.c} /// // PanID OTA value of 0x34 0x12. /// // Short Address OTA byte order of 0x78 0x56. /// // Long address with OTA byte order of 0x11 0x22 0x33 0x44 0x55 0x66 0x77 0x88. /// /// // Set up all addresses simultaneously. /// RAIL_Status_t setup1(void) /// { /// RAIL_IEEE802154_AddrConfig_t nodeAddress = { /// { 0x1234, 0xFFFF, 0xFFFF }, /// { 0x5678, 0xFFFF, 0xFFFF }, /// { { 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77, 0x88 }, /// { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, /// { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } } /// }; /// return RAIL_IEEE802154_SetAddresses(railHandle, &nodeAddress); /// } /// /// // Alternatively, the addresses can be set up individually as follows: /// RAIL_Status_t setup2(void) /// { /// RAIL_Status_t status; /// const uint8_t longAddress[] = { 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77, 0x88 }; /// /// status = RAIL_IEEE802154_SetPanId(railHandle, 0x1234, 0); /// if (status != RAIL_STATUS_NO_ERROR) { /// return status /// } /// status = RAIL_IEEE802154_SetShortAddress(railHandle, 0x5678, 0); /// if (status != RAIL_STATUS_NO_ERROR) { /// return status /// } /// status = RAIL_IEEE802154_SetLongAddress(railHandle, longAddress, 0); /// if (status != RAIL_STATUS_NO_ERROR) { /// return status /// } /// /// return RAIL_STATUS_NO_ERROR; /// } /// @endcode /// /// Address filtering will be enabled except when in promiscuous mode which can /// be set with RAIL_IEEE802154_SetPromiscuousMode(). The addresses may be /// changed at runtime. However, if you are receiving a packet while reconfiguring the /// address filters, you may get undesired behavior so it's safest to do this /// while not in receive. /// /// Auto ACK is controlled by the ackConfig and timings fields passed to /// RAIL_IEEE802154_Init(). After initialization they may be controlled /// using the normal \ref Auto_Ack and \ref State_Transitions APIs. When in IEEE /// 802.15.4 mode, the ACK will have a 5 byte length, the frame type will be set /// to ACK, and the frame pending bit will be set if /// RAIL_IEEE802154_SetFramePending() is called when the \ref /// RAIL_EVENT_IEEE802154_DATA_REQUEST_COMMAND event is triggered. This event /// must be turned on by the user and will fire whenever a data request is being /// received so that the stack can determine whether there is pending data. Be /// aware that the frame pending bit must be set quickly after receiving the /// event or the ACK may already have been transmitted. Check the return code of /// RAIL_IEEE802154_SetFramePending() to be sure that the bit was set in time. /// /// Transmit and receive operations are done using the standard RAIL APIs in /// IEEE 802.15.4 mode. To send packets using the correct CSMA configuration /// there is a \ref RAIL_CSMA_CONFIG_802_15_4_2003_2p4_GHz_OQPSK_CSMA define /// that can initialize the csmaConfig structure passed to \ref /// RAIL_StartCcaCsmaTx(). /// @{ /** * @enum RAIL_IEEE802154_AddressLength_t * @brief Different lengths that an 802.15.4 address can have */ RAIL_ENUM(RAIL_IEEE802154_AddressLength_t) { RAIL_IEEE802154_ShortAddress = 2, /**< 2 byte short address. */ RAIL_IEEE802154_LongAddress = 3, /**< 8 byte extended address. */ }; #ifndef DOXYGEN_SHOULD_SKIP_THIS // Self-referencing defines minimize compiler complaints when using RAIL_ENUM #define RAIL_IEEE802154_ShortAddress ((RAIL_IEEE802154_AddressLength_t) RAIL_IEEE802154_ShortAddress) #define RAIL_IEEE802154_LongAddress ((RAIL_IEEE802154_AddressLength_t) RAIL_IEEE802154_LongAddress) #endif//DOXYGEN_SHOULD_SKIP_THIS /** * @struct RAIL_IEEE802154_Address_t * @brief Representation of 802.15.4 address * This structure is only used for a received address, which needs to be parsed * to discover the type. */ typedef struct RAIL_IEEE802154_Address{ /** Convenient storage for different address types. */ union { uint16_t shortAddress; /**< Present for 2 byte addresses. */ uint8_t longAddress[8]; /**< Present for 8 byte addresses. */ }; /** * Enumeration of the received address length. */ RAIL_IEEE802154_AddressLength_t length; } RAIL_IEEE802154_Address_t; /** The maximum number of allowed addresses of each type. */ #define RAIL_IEEE802154_MAX_ADDRESSES 3 /** * @struct RAIL_IEEE802154_AddrConfig_t * @brief A configuration structure for IEEE 802.15.4 Address Filtering. The * broadcast addresses are handled separately and do not need to be specified * here. Any address to be ignored should be set with all bits high. * * This structure allows configuration of multi-PAN functionality by specifying * multiple PAN IDs and short addresses. A packet will be received if it matches * an address and it's corresponding PAN ID. Long address 0 and short address 0 * match against PAN ID 0, etc. The broadcast PAN ID and address will work with * any address or PAN ID, respectively. */ typedef struct RAIL_IEEE802154_AddrConfig{ /** * PAN IDs for destination filtering. All must be specified. * To disable a PAN ID, set it to the broadcast value, 0xFFFF. */ uint16_t panId[RAIL_IEEE802154_MAX_ADDRESSES]; /** * A short network addresses for destination filtering. All must be specified. * To disable a short address, set it to the broadcast value, 0xFFFF. */ uint16_t shortAddr[RAIL_IEEE802154_MAX_ADDRESSES]; /** * A 64-bit address for destination filtering. All must be specified. * This field is parsed in over-the-air (OTA) byte order. To disable a long * address, set it to the reserved value of 0x00 00 00 00 00 00 00 00. */ uint8_t longAddr[RAIL_IEEE802154_MAX_ADDRESSES][8]; } RAIL_IEEE802154_AddrConfig_t; /** * @struct RAIL_IEEE802154_Config_t * @brief A configuration structure for IEEE 802.15.4 in RAIL. */ typedef struct RAIL_IEEE802154_Config { /** * Configure the RAIL Address Filter to allow the given destination * addresses. If this pointer is NULL, defer destination address configuration. * If a member of addresses is NULL, defer configuration of just that member. * This can be overridden via RAIL_IEEE802154_SetAddresses(), or the * individual members can be changed via RAIL_IEEE802154_SetPanId(), * RAIL_IEEE802154_SetShortAddress(), and RAIL_IEEE802154_SetLongAddress(). */ const RAIL_IEEE802154_AddrConfig_t *addresses; /** * Defines the acking configuration for the IEEE 802.15.4 implementation. */ RAIL_AutoAckConfig_t ackConfig; /** * Defines state timings for the IEEE 802.15.4 implementation. */ RAIL_StateTiming_t timings; /** * Sets which 802.15.4 frame types will be received, of Beacon, Data, ACK, and * Command. This setting can be overridden via RAIL_IEEE802154_AcceptFrames(). */ uint8_t framesMask; /** * Enables promiscuous mode during configuration. This can be overridden via * RAIL_IEEE802154_SetPromiscuousMode() afterwards. */ bool promiscuousMode; /** * Sets whether the device is a PAN Coordinator during configuration. This can * be overridden via RAIL_IEEE802154_SetPanCoordinator() afterwards. */ bool isPanCoordinator; } RAIL_IEEE802154_Config_t; /** * Initializes RAIL for IEEE802.15.4 features. * * @param[in] railHandle A handle of RAIL instance. * @param[in] config An IEEE802154 configuration structure. * @return A status code indicating success of the function call. * * This function calls the following RAIL functions to configure the radio for * IEEE802.15.4 features. * * Initializes the following: * - Enables IEEE802154 hardware acceleration * - Configures RAIL Auto ACK functionality * - Configures RAIL Address Filter for 802.15.4 address filtering * * It saves having to call the following functions individually: * - RAIL_ConfigAutoAck() * - RAIL_SetRxTransitions() * - RAIL_SetTxTransitions() * - RAIL_WriteAutoAckFifo() * - RAIL_SetStateTiming() * - RAIL_ConfigAddressFilter() * - RAIL_EnableAddressFilter() */ RAIL_Status_t RAIL_IEEE802154_Init(RAIL_Handle_t railHandle, const RAIL_IEEE802154_Config_t *config); /** * Configures the radio for 2.4GHz 802.15.4 operation. * * @param[in] railHandle A handle of RAIL instance. * @return A status code indicating success of the function call. * * This initializes the radio for 2.4 GHz operation. It takes the place of * calling \ref RAIL_ConfigChannels. After this call, * channels 11-26 will be available, giving the frequencies of those channels * on channel page 0, as defined by IEEE 802.15.4-2011 section 8.1.2.2. */ RAIL_Status_t RAIL_IEEE802154_Config2p4GHzRadio(RAIL_Handle_t railHandle); /** * Configures the radio for 2.4GHz 802.15.4 operation with antenna diversity. * * @param[in] railHandle A handle of RAIL instance. * @return A status code indicating success of the function call. * * This initializes the radio for 2.4 GHz operation, but with a configuration * that supports antenna diversity. It takes the place of * calling \ref RAIL_ConfigChannels. After this call, * channels 11-26 will be available, giving the frequencies of those channels * on channel page 0, as defined by IEEE 802.15.4-2011 section 8.1.2.2. */ RAIL_Status_t RAIL_IEEE802154_Config2p4GHzRadioAntDiv(RAIL_Handle_t railHandle); /** * Configures the radio for 2.4GHz 802.15.4 operation with antenna diversity * optimized for radio coexistence. * * @param[in] railHandle A handle of RAIL instance. * @return A status code indicating success of the function call. * * This initializes the radio for 2.4 GHz operation, but with a configuration * that supports antenna diversity optimized for radio coexistence. It takes * the place of calling \ref RAIL_ConfigChannels. After this call, * channels 11-26 will be available, giving the frequencies of those channels * on channel page 0, as defined by IEEE 802.15.4-2011 section 8.1.2.2. */ RAIL_Status_t RAIL_IEEE802154_Config2p4GHzRadioAntDivCoex(RAIL_Handle_t railHandle); /** * Configures the radio for 2.4GHz 802.15.4 operation optimized for radio coexistence. * * @param[in] railHandle A handle of RAIL instance. * @return A status code indicating success of the function call. * * This initializes the radio for 2.4 GHz operation, but with a configuration * that supports radio coexistence. It takes the place of * calling \ref RAIL_ConfigChannels. After this call, * channels 11-26 will be available, giving the frequencies of those channels * on channel page 0, as defined by IEEE 802.15.4-2011 section 8.1.2.2. */ RAIL_Status_t RAIL_IEEE802154_Config2p4GHzRadioCoex(RAIL_Handle_t railHandle); /** * Configures the radio for SubGHz GB868 863 MHz 802.15.4 operation. * * @param[in] railHandle A handle of RAIL instance. * @return A status code indicating success of the function call. * * This initializes the radio for SubGHz GB868 863 MHz operation. It takes the * place of calling \ref RAIL_ConfigChannels. * After this call, GB868 channels in the 863 MHz band (channel pages 28, 29, * and 30 -- logical channels 0x80..0x9A, 0xA0..0xA8, 0xC0..0xDA, respectively) * will be available, as defined by Rev 22 of the Zigbee Specification, 2017 * document 05-3474-22, section D.10.2.1.3.2. */ RAIL_Status_t RAIL_IEEE802154_ConfigGB863MHzRadio(RAIL_Handle_t railHandle); /** * Configures the radio for SubGHz GB868 915 MHz 802.15.4 operation. * * @param[in] railHandle A handle of RAIL instance. * @return A status code indicating success of the function call. * * This initializes the radio for SubGHz GB868 915 MHz operation. It takes the * place of calling \ref RAIL_ConfigChannels. * After this call, GB868 channels in the 915 MHz band (channel page 31 -- * logical channels 0xE0..0xFA) will be available, as defined by Rev 22 of * the Zigbee Specification, 2017 document 05-3474-22, section D.10.2.1.3.2. */ RAIL_Status_t RAIL_IEEE802154_ConfigGB915MHzRadio(RAIL_Handle_t railHandle); /** * De-initializes IEEE802.15.4 hardware acceleration. * * @param[in] railHandle A handle of RAIL instance. * @return A status code indicating success of the function call. * * Disables and resets all IEE802.15.4 hardware acceleration features. This * function should only be called when the radio is IDLE. This calls the * following: * - RAIL_SetStateTiming(), to reset all timings to 100 us * - RAIL_EnableAddressFilter(false) * - RAIL_ResetAddressFilter() */ RAIL_Status_t RAIL_IEEE802154_Deinit(RAIL_Handle_t railHandle); /** * Returns whether IEEE802.15.4 hardware acceleration is currently enabled. * * @param[in] railHandle A handle of RAIL instance. * @return True if IEEE802.15.4 hardware acceleration was enabled to start with * and false otherwise. */ bool RAIL_IEEE802154_IsEnabled(RAIL_Handle_t railHandle); /** * Configures the RAIL Address Filter for 802.15.4 filtering. * * @param[in] railHandle A handle of RAIL instance. * @param[in] addresses The address information that should be used. * @return A status code indicating success of the function call. If this returns * an error, the 802.15.4 address filter is in an undefined state. * * Set up the 802.15.4 address filter to accept messages to the given * addresses. This will return false if any of the addresses failed to be set. * If NULL is passed in for addresses, all addresses will be set to their * reset value. */ RAIL_Status_t RAIL_IEEE802154_SetAddresses(RAIL_Handle_t railHandle, const RAIL_IEEE802154_AddrConfig_t *addresses); /** * Sets a PAN ID for 802.15.4 address filtering. * * @param[in] railHandle A handle of RAIL instance. * @param[in] panId The 16-bit PAN ID information. * This will be matched against the destination PAN ID of incoming messages. * The PAN ID is sent little endian over the air, meaning panId[7:0] is first in * the payload followed by panId[15:8]. Set to 0xFFFF to disable for this index. * @param[in] index Indicates which PAN ID to set. Must be below * RAIL_IEEE802154_MAX_ADDRESSES. * @return A status code indicating success of the function call. * * Set up the 802.15.4 address filter to accept messages to the given PAN ID. */ RAIL_Status_t RAIL_IEEE802154_SetPanId(RAIL_Handle_t railHandle, uint16_t panId, uint8_t index); /** * Sets a short address for 802.15.4 address filtering. * * @param[in] railHandle A handle of RAIL instance * @param[in] shortAddr 16 bit short address value. This will be matched against the * destination short address of incoming messages. The short address is sent * little endian over the air meaning shortAddr[7:0] is first in the payload * followed by shortAddr[15:8]. Set to 0xFFFF to disable for this index. * @param[in] index Which short address to set. Must be below * RAIL_IEEE802154_MAX_ADDRESSES. * @return A status code indicating success of the function call. * * Set up the 802.15.4 address filter to accept messages to the given short * address. */ RAIL_Status_t RAIL_IEEE802154_SetShortAddress(RAIL_Handle_t railHandle, uint16_t shortAddr, uint8_t index); /** * Sets a long address for 802.15.4 address filtering. * * @param[in] railHandle A handle of RAIL instance. * @param[in] longAddr A pointer to an 8-byte array containing the long address * information. The long address must be in over-the-air byte order. This will * be matched against the destination long address of incoming messages. Set to * 0x00 00 00 00 00 00 00 00 to disable for this index. * @param[in] index Indicates which long address to set. Must be below * RAIL_IEEE802154_MAX_ADDRESSES. * @return A status code indicating success of the function call. * * Set up the 802.15.4 address filter to accept messages to the given long * address. */ RAIL_Status_t RAIL_IEEE802154_SetLongAddress(RAIL_Handle_t railHandle, const uint8_t *longAddr, uint8_t index); /** * Sets whether the current node is a PAN coordinator. * * @param[in] railHandle A handle of RAIL instance. * @param[in] isPanCoordinator True if this device is a PAN coordinator. * @return A status code indicating success of the function call. * * If the device is a PAN Coordinator, it will accept data and command * frames with no destination address. This function will fail if 802.15.4 * hardware acceleration is not currently enabled. This setting may be changed * at any time when 802.15.4 hardware acceleration is enabled. */ RAIL_Status_t RAIL_IEEE802154_SetPanCoordinator(RAIL_Handle_t railHandle, bool isPanCoordinator); /** * Sets whether to enable 802.15.4 promiscuous mode. * * @param[in] railHandle A handle of RAIL instance. * @param[in] enable True if all frames and addresses should be accepted. * @return A status code indicating success of the function call. * * If promiscuous mode is enabled, no frame or address filtering steps * will be performed other than checking the CRC. This function will fail if * 802.15.4 hardware acceleration is not currently enabled. This setting may be * changed at any time when 802.15.4 hardware acceleration is enabled. */ RAIL_Status_t RAIL_IEEE802154_SetPromiscuousMode(RAIL_Handle_t railHandle, bool enable); /// When receiving packets, accept 802.15.4 BEACON frame types. #define RAIL_IEEE802154_ACCEPT_BEACON_FRAMES (0x01) /// When receiving packets, accept 802.15.4 DATA frame types. #define RAIL_IEEE802154_ACCEPT_DATA_FRAMES (0x02) /// When receiving packets, accept 802.15.4 ACK frame types. /// If this is not enabled, ACK frame types will only be accepted while waiting /// for an ACK. #define RAIL_IEEE802154_ACCEPT_ACK_FRAMES (0x04) /// When receiving packets, accept 802.15.4 COMMAND frame types. #define RAIL_IEEE802154_ACCEPT_COMMAND_FRAMES (0x08) /// In standard operation, accept BEACON, DATA and COMMAND frames. /// Only receive ACK frames while waiting for ACK. #define RAIL_IEEE802154_ACCEPT_STANDARD_FRAMES (RAIL_IEEE802154_ACCEPT_BEACON_FRAMES \ | RAIL_IEEE802154_ACCEPT_DATA_FRAMES \ | RAIL_IEEE802154_ACCEPT_COMMAND_FRAMES) /** * Sets which 802.15.4 frame types to accept. * * @param[in] railHandle A handle of RAIL instance. * @param[in] framesMask A mask containing which 802.15.4 frame types to receive. * @return A status code indicating success of the function call. * * This function will fail if 802.15.4 hardware acceleration is not currently * enabled. This setting may be changed at any time when 802.15.4 hardware * acceleration is enabled. Only Beacon, Data, ACK, and Command frames may * be received. The RAIL_IEEE802154_ACCEPT_XXX_FRAMES defines may be combined * to create a bitmask to pass into this function. * * \ref RAIL_IEEE802154_ACCEPT_ACK_FRAMES behaves slightly different than the * other defines. If \ref RAIL_IEEE802154_ACCEPT_ACK_FRAMES is set, the radio * will accept an ACK frame during normal packet reception. If \ref * RAIL_IEEE802154_ACCEPT_ACK_FRAMES is not set, ACK frames will be filtered * unless the radio is waiting for an ACK. */ RAIL_Status_t RAIL_IEEE802154_AcceptFrames(RAIL_Handle_t railHandle, uint8_t framesMask); /** * Sets the frame pending bit on the outgoing ACK. * * @param[in] railHandle A handle of RAIL instance. * @return A status code indicating success of the function call. * * This function should be called after receiving \ref * RAIL_EVENT_IEEE802154_DATA_REQUEST_COMMAND, if the given source address has * a pending frame. This will return \ref RAIL_STATUS_INVALID_STATE if it is * too late to modify the ACK. */ RAIL_Status_t RAIL_IEEE802154_SetFramePending(RAIL_Handle_t railHandle); /** * Gets the source address of the incoming data request. * * @param[in] railHandle A RAIL instance handle. * @param[out] pAddress A pointer to \ref RAIL_IEEE802154_Address_t structure * to populate with address information. * @return A status code indicating success of the function call. * * This function should only be called when handling the \ref * RAIL_EVENT_IEEE802154_DATA_REQUEST_COMMAND event. */ RAIL_Status_t RAIL_IEEE802154_GetAddress(RAIL_Handle_t railHandle, RAIL_IEEE802154_Address_t *pAddress); /** @} */ // end of IEEE802.15.4 #ifdef __cplusplus } #endif #endif // __RAIL_IEEE802154_H__ |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/protocol/bluetooth/ble_stack/inc/common/bg_errorcodes.h.
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/***************************************************************************//** * @brief Bluetooth stack error codes ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * The licensor of this software is Silicon Laboratories Inc. Your use of this * software is governed by the terms of Silicon Labs Master Software License * Agreement (MSLA) available at * www.silabs.com/about-us/legal/master-software-license-agreement. This * software is distributed to you in Source Code format and is governed by the * sections of the MSLA applicable to Source Code. * ******************************************************************************/ #ifndef BG_ERRORCODES #define BG_ERRORCODES enum bg_error_spaces { bg_errspc_hardware=1280, bg_errspc_bg=256, bg_errspc_smp=768, bg_errspc_bt=512, bg_errspc_application=2560, bg_errspc_att=1024, bg_errspc_mesh=3072, bg_errspc_mesh_foundation=3584, bg_errspc_filesystem=2304, bg_errspc_l2cap=3328, bg_errspc_security=2816, }; typedef enum bg_error { bg_err_hardware_ps_store_full =bg_errspc_hardware+1, //Flash reserved for PS store is full bg_err_hardware_ps_key_not_found =bg_errspc_hardware+2, //PS key not found bg_err_hardware_i2c_ack_missing =bg_errspc_hardware+3, //Acknowledge for i2c was not received. bg_err_hardware_i2c_timeout =bg_errspc_hardware+4, //I2C read or write timed out. bg_err_success =0, //No error bg_err_invalid_conn_handle =bg_errspc_bg+1, //Invalid GATT connection handle. bg_err_waiting_response =bg_errspc_bg+2, //Waiting response from GATT server to previous procedure. bg_err_gatt_connection_timeout =bg_errspc_bg+3, //GATT connection is closed due procedure timeout. bg_err_invalid_param =bg_errspc_bg+128, //Command contained invalid parameter bg_err_wrong_state =bg_errspc_bg+129, //Device is in wrong state to receive command bg_err_out_of_memory =bg_errspc_bg+130, //Device has run out of memory bg_err_not_implemented =bg_errspc_bg+131, //Feature is not implemented bg_err_invalid_command =bg_errspc_bg+132, //Command was not recognized bg_err_timeout =bg_errspc_bg+133, //A command or procedure failed or a link lost due to timeout bg_err_not_connected =bg_errspc_bg+134, //Connection handle passed is to command is not a valid handle bg_err_flow =bg_errspc_bg+135, //Command would cause either underflow or overflow error bg_err_user_attribute =bg_errspc_bg+136, //User attribute was accessed through API which is not supported bg_err_invalid_license_key =bg_errspc_bg+137, //No valid license key found bg_err_command_too_long =bg_errspc_bg+138, //Command maximum length exceeded bg_err_out_of_bonds =bg_errspc_bg+139, //Bonding procedure can't be started because device has no space left for bond. bg_err_unspecified =bg_errspc_bg+140, //Unspecified error bg_err_hardware =bg_errspc_bg+141, //Hardware failure bg_err_buffers_full =bg_errspc_bg+142, //Command not accepted, because internal buffers are full bg_err_disconnected =bg_errspc_bg+143, //Command or Procedure failed due to disconnection bg_err_too_many_requests =bg_errspc_bg+144, //Too many Simultaneous Requests bg_err_not_supported =bg_errspc_bg+145, //Feature is not supported in this firmware build bg_err_no_bonding =bg_errspc_bg+146, //The bonding does not exist. bg_err_crypto =bg_errspc_bg+147, //Error using crypto functions bg_err_data_corrupted =bg_errspc_bg+148, //Data was corrupted. bg_err_command_incomplete =bg_errspc_bg+149, //Data received does not form a complete command bg_err_not_initialized =bg_errspc_bg+150, //Feature or subsystem not initialized bg_err_invalid_sync_handle =bg_errspc_bg+151, //Invalid periodic advertising sync handle bg_err_smp_passkey_entry_failed =bg_errspc_smp+1, //The user input of passkey failed, for example, the user cancelled the operation bg_err_smp_oob_not_available =bg_errspc_smp+2, //Out of Band data is not available for authentication bg_err_smp_authentication_requirements =bg_errspc_smp+3, //The pairing procedure cannot be performed as authentication requirements cannot be met due to IO capabilities of one or both devices bg_err_smp_confirm_value_failed =bg_errspc_smp+4, //The confirm value does not match the calculated compare value bg_err_smp_pairing_not_supported =bg_errspc_smp+5, //Pairing is not supported by the device bg_err_smp_encryption_key_size =bg_errspc_smp+6, //The resultant encryption key size is insufficient for the security requirements of this device bg_err_smp_command_not_supported =bg_errspc_smp+7, //The SMP command received is not supported on this device bg_err_smp_unspecified_reason =bg_errspc_smp+8, //Pairing failed due to an unspecified reason bg_err_smp_repeated_attempts =bg_errspc_smp+9, //Pairing or authentication procedure is disallowed because too little time has elapsed since last pairing request or security request bg_err_smp_invalid_parameters =bg_errspc_smp+10, //The Invalid Parameters error code indicates: the command length is invalid or a parameter is outside of the specified range. bg_err_smp_dhkey_check_failed =bg_errspc_smp+11, //Indicates to the remote device that the DHKey Check value received doesn't match the one calculated by the local device. bg_err_smp_numeric_comparison_failed =bg_errspc_smp+12, //Indicates that the confirm values in the numeric comparison protocol do not match. bg_err_smp_bredr_pairing_in_progress =bg_errspc_smp+13, //Indicates that the pairing over the LE transport failed due to a Pairing Request sent over the BR/EDR transport in process. bg_err_smp_cross_transport_key_derivation_generation_not_allowed =bg_errspc_smp+14, //Indicates that the BR/EDR Link Key generated on the BR/EDR transport cannot be used to derive and distribute keys for the LE transport. bg_err_bt_error_success =0, //Command completed succesfully bg_err_bt_unknown_connection_identifier =bg_errspc_bt+2, //Connection does not exist, or connection open request was cancelled. bg_err_bt_authentication_failure =bg_errspc_bt+5, //Pairing or authentication failed due to incorrect results in the pairing or authentication procedure. This could be due to an incorrect PIN or Link Key bg_err_bt_pin_or_key_missing =bg_errspc_bt+6, //Pairing failed because of missing PIN, or authentication failed because of missing Key bg_err_bt_memory_capacity_exceeded =bg_errspc_bt+7, //Controller is out of memory. bg_err_bt_connection_timeout =bg_errspc_bt+8, //Link supervision timeout has expired. bg_err_bt_connection_limit_exceeded =bg_errspc_bt+9, //Controller is at limit of connections it can support. bg_err_bt_synchronous_connectiontion_limit_exceeded =bg_errspc_bt+10, //The Synchronous Connection Limit to a Device Exceeded error code indicates that the Controller has reached the limit to the number of synchronous connections that can be achieved to a device. bg_err_bt_acl_connection_already_exists =bg_errspc_bt+11, //The ACL Connection Already Exists error code indicates that an attempt to create a new ACL Connection to a device when there is already a connection to this device. bg_err_bt_command_disallowed =bg_errspc_bt+12, //Command requested cannot be executed because the Controller is in a state where it cannot process this command at this time. bg_err_bt_connection_rejected_due_to_limited_resources =bg_errspc_bt+13, //The Connection Rejected Due To Limited Resources error code indicates that an incoming connection was rejected due to limited resources. bg_err_bt_connection_rejected_due_to_security_reasons =bg_errspc_bt+14, //The Connection Rejected Due To Security Reasons error code indicates that a connection was rejected due to security requirements not being fulfilled, like authentication or pairing. bg_err_bt_connection_rejected_due_to_unacceptable_bd_addr =bg_errspc_bt+15, //The Connection was rejected because this device does not accept the BD_ADDR. This may be because the device will only accept connections from specific BD_ADDRs. bg_err_bt_connection_accept_timeout_exceeded =bg_errspc_bt+16, //The Connection Accept Timeout has been exceeded for this connection attempt. bg_err_bt_unsupported_feature_or_parameter_value =bg_errspc_bt+17, //A feature or parameter value in the HCI command is not supported. bg_err_bt_invalid_command_parameters =bg_errspc_bt+18, //Command contained invalid parameters. bg_err_bt_remote_user_terminated =bg_errspc_bt+19, //User on the remote device terminated the connection. bg_err_bt_remote_device_terminated_connection_due_to_low_resources =bg_errspc_bt+20, //The remote device terminated the connection because of low resources bg_err_bt_remote_powering_off =bg_errspc_bt+21, //Remote Device Terminated Connection due to Power Off bg_err_bt_connection_terminated_by_local_host =bg_errspc_bt+22, //Local device terminated the connection. bg_err_bt_repeated_attempts =bg_errspc_bt+23, //The Controller is disallowing an authentication or pairing procedure because too little time has elapsed since the last authentication or pairing attempt failed. bg_err_bt_pairing_not_allowed =bg_errspc_bt+24, //The device does not allow pairing. This can be for example, when a device only allows pairing during a certain time window after some user input allows pairing bg_err_bt_unsupported_remote_feature =bg_errspc_bt+26, //The remote device does not support the feature associated with the issued command. bg_err_bt_unspecified_error =bg_errspc_bt+31, //No other error code specified is appropriate to use. bg_err_bt_ll_response_timeout =bg_errspc_bt+34, //Connection terminated due to link-layer procedure timeout. bg_err_bt_ll_procedure_collision =bg_errspc_bt+35, //LL procedure has collided with the same transaction or procedure that is already in progress. bg_err_bt_encryption_mode_not_acceptable =bg_errspc_bt+37, //The requested encryption mode is not acceptable at this time. bg_err_bt_link_key_cannot_be_changed =bg_errspc_bt+38, //Link key cannot be changed because a fixed unit key is being used. bg_err_bt_instant_passed =bg_errspc_bt+40, //LMP PDU or LL PDU that includes an instant cannot be performed because the instant when this would have occurred has passed. bg_err_bt_pairing_with_unit_key_not_supported =bg_errspc_bt+41, //It was not possible to pair as a unit key was requested and it is not supported. bg_err_bt_different_transaction_collision =bg_errspc_bt+42, //LMP transaction was started that collides with an ongoing transaction. bg_err_bt_channel_assessment_not_supported =bg_errspc_bt+46, //The Controller cannot perform channel assessment because it is not supported. bg_err_bt_insufficient_security =bg_errspc_bt+47, //The HCI command or LMP PDU sent is only possible on an encrypted link. bg_err_bt_parameter_out_of_mandatory_range =bg_errspc_bt+48, //A parameter value requested is outside the mandatory range of parameters for the given HCI command or LMP PDU. bg_err_bt_simple_pairing_not_supported_by_host =bg_errspc_bt+55, //The IO capabilities request or response was rejected because the sending Host does not support Secure Simple Pairing even though the receiving Link Manager does. bg_err_bt_host_busy_pairing =bg_errspc_bt+56, //The Host is busy with another pairing operation and unable to support the requested pairing. The receiving device should retry pairing again later. bg_err_bt_connection_rejected_due_to_no_suitable_channel_found =bg_errspc_bt+57, //The Controller could not calculate an appropriate value for the Channel selection operation. bg_err_bt_controller_busy =bg_errspc_bt+58, //Operation was rejected because the controller is busy and unable to process the request. bg_err_bt_unacceptable_connection_interval =bg_errspc_bt+59, //Remote device terminated the connection because of an unacceptable connection interval. bg_err_bt_advertising_timeout =bg_errspc_bt+60, //Ddvertising for a fixed duration completed or, for directed advertising, that advertising completed without a connection being created. bg_err_bt_connection_terminated_due_to_mic_failure =bg_errspc_bt+61, //Connection was terminated because the Message Integrity Check (MIC) failed on a received packet. bg_err_bt_connection_failed_to_be_established =bg_errspc_bt+62, //LL initiated a connection but the connection has failed to be established. Controller did not receive any packets from remote end. bg_err_bt_mac_connection_failed =bg_errspc_bt+63, //The MAC of the 802.11 AMP was requested to connect to a peer, but the connection failed. bg_err_bt_coarse_clock_adjustment_rejected_but_will_try_to_adjust_using_clock_dragging=bg_errspc_bt+64, //The master, at this time, is unable to make a coarse adjustment to the piconet clock, using the supplied parameters. Instead the master will attempt to move the clock using clock dragging. bg_err_bt_unknown_advertising_identifier =bg_errspc_bt+66, //A command was sent from the Host that should identify an Advertising or Sync handle, but the Advertising or Sync handle does not exist. bg_err_bt_limit_reached =bg_errspc_bt+67, //Number of operations requested has been reached and has indicated the completion of the activity (e.g., advertising or scanning). bg_err_bt_operation_cancelled_by_host =bg_errspc_bt+68, //A request to the Controller issued by the Host and still pending was successfully canceled. bg_err_bt_packet_too_long =bg_errspc_bt+69, //An attempt was made to send or receive a packet that exceeds the maximum allowed packet length. bg_err_application_file_open_failed =bg_errspc_application+1, //File open failed. bg_err_application_xml_parse_failed =bg_errspc_application+2, //XML parsing failed. bg_err_application_device_connection_failed =bg_errspc_application+3, //Device connection failed. bg_err_application_device_comunication_failed =bg_errspc_application+4, //Device communication failed. bg_err_application_authentication_failed =bg_errspc_application+5, //Device authentication failed. bg_err_application_incorrect_gatt_database =bg_errspc_application+6, //Device has incorrect GATT database. bg_err_application_disconnected_due_to_procedure_collision =bg_errspc_application+7, //Device disconnected due to procedure collision. bg_err_application_disconnected_due_to_secure_session_failed =bg_errspc_application+8, //Device disconnected due to failure to establish or reestablish a secure session. bg_err_application_encryption_decryption_error =bg_errspc_application+9, //Encrypion/decryption operation failed. bg_err_application_maximum_retries =bg_errspc_application+10, //Maximum allowed retries exceeded. bg_err_application_data_parse_failed =bg_errspc_application+11, //Data parsing failed. bg_err_application_pairing_removed =bg_errspc_application+12, //Pairing established by the application layer protocol has been removed. bg_err_application_inactive_timeout =bg_errspc_application+13, //Inactive timeout. bg_err_application_mismatched_or_insufficient_security =bg_errspc_application+14, //Mismatched or insufficient security level bg_err_att_invalid_handle =bg_errspc_att+1, //The attribute handle given was not valid on this server bg_err_att_read_not_permitted =bg_errspc_att+2, //The attribute cannot be read bg_err_att_write_not_permitted =bg_errspc_att+3, //The attribute cannot be written bg_err_att_invalid_pdu =bg_errspc_att+4, //The attribute PDU was invalid bg_err_att_insufficient_authentication =bg_errspc_att+5, //The attribute requires authentication before it can be read or written. bg_err_att_request_not_supported =bg_errspc_att+6, //Attribute Server does not support the request received from the client. bg_err_att_invalid_offset =bg_errspc_att+7, //Offset specified was past the end of the attribute bg_err_att_insufficient_authorization =bg_errspc_att+8, //The attribute requires authorization before it can be read or written. bg_err_att_prepare_queue_full =bg_errspc_att+9, //Too many prepare writes have been queueud bg_err_att_att_not_found =bg_errspc_att+10, //No attribute found within the given attribute handle range. bg_err_att_att_not_long =bg_errspc_att+11, //The attribute cannot be read or written using the Read Blob Request bg_err_att_insufficient_enc_key_size =bg_errspc_att+12, //The Encryption Key Size used for encrypting this link is insufficient. bg_err_att_invalid_att_length =bg_errspc_att+13, //The attribute value length is invalid for the operation bg_err_att_unlikely_error =bg_errspc_att+14, //The attribute request that was requested has encountered an error that was unlikely, and therefore could not be completed as requested. bg_err_att_insufficient_encryption =bg_errspc_att+15, //The attribute requires encryption before it can be read or written. bg_err_att_unsupported_group_type =bg_errspc_att+16, //The attribute type is not a supported grouping attribute as defined by a higher layer specification. bg_err_att_insufficient_resources =bg_errspc_att+17, //Insufficient Resources to complete the request bg_err_att_out_of_sync =bg_errspc_att+18, //The server requests the client to rediscover the database. bg_err_att_value_not_allowed =bg_errspc_att+19, //The attribute parameter value was not allowed. bg_err_att_application =bg_errspc_att+128, //When this is returned in a BGAPI response, the application tried to read or write the value of a user attribute from the GATT database. bg_err_mesh_already_exists =bg_errspc_mesh+1, //Returned when trying to add a key or some other unique resource with an ID which already exists bg_err_mesh_does_not_exist =bg_errspc_mesh+2, //Returned when trying to manipulate a key or some other resource with an ID which does not exist bg_err_mesh_limit_reached =bg_errspc_mesh+3, //Returned when an operation cannot be executed because a pre-configured limit for keys, key bindings, elements, models, virtual addresses, provisioned devices, or provisioning sessions is reached bg_err_mesh_invalid_address =bg_errspc_mesh+4, //Returned when trying to use a reserved address or add a "pre-provisioned" device using an address already used by some other device bg_err_mesh_malformed_data =bg_errspc_mesh+5, //In a BGAPI response, the user supplied malformed data; in a BGAPI event, the remote end responded with malformed or unrecognized data bg_err_mesh_already_initialized =bg_errspc_mesh+6, //An attempt was made to initialize a subsystem that was already initialized. bg_err_mesh_not_initialized =bg_errspc_mesh+7, //An attempt was made to use a subsystem that wasn't initialized yet. Call the subsystem's init function first. bg_err_mesh_no_friend_offer =bg_errspc_mesh+8, //Returned when trying to establish a friendship as a Low Power Node, but no acceptable friend offer message was received. bg_err_mesh_prov_link_closed =bg_errspc_mesh+9, //Provisioning link was unexpectedly closed before provisioning was complete. bg_err_mesh_prov_invalid_pdu =bg_errspc_mesh+10, //An unrecognized provisioning PDU was received. bg_err_mesh_prov_invalid_pdu_format =bg_errspc_mesh+11, //A provisioning PDU with wrong length or containing field values that are out of bounds was received. bg_err_mesh_prov_unexpected_pdu =bg_errspc_mesh+12, //An unexpected (out of sequence) provisioning PDU was received. bg_err_mesh_prov_confirmation_failed =bg_errspc_mesh+13, //The computed confirmation value did not match the expected value. bg_err_mesh_prov_out_of_resources =bg_errspc_mesh+14, //Provisioning could not be continued due to unsufficient resources. bg_err_mesh_prov_decryption_failed =bg_errspc_mesh+15, //The provisioning data block could not be decrypted. bg_err_mesh_prov_unexpected_error =bg_errspc_mesh+16, //An unexpected error happened during provisioning. bg_err_mesh_prov_cannot_assign_addr =bg_errspc_mesh+17, //Device could not assign unicast addresses to all of its elements. bg_err_mesh_address_temporarily_unavailable =bg_errspc_mesh+18, //Returned when trying to reuse an address of a previously deleted device before an IV Index Update has been executed. bg_err_mesh_address_already_used =bg_errspc_mesh+19, //Returned when trying to assign an address that is used by one of the devices in the Device Database, or by the Provisioner itself. bg_err_mesh_foundation_invalid_address =bg_errspc_mesh_foundation+1, //Returned when address in request was not valid bg_err_mesh_foundation_invalid_model =bg_errspc_mesh_foundation+2, //Returned when model identified is not found for a given element bg_err_mesh_foundation_invalid_app_key =bg_errspc_mesh_foundation+3, //Returned when the key identified by AppKeyIndex is not stored in the node bg_err_mesh_foundation_invalid_net_key =bg_errspc_mesh_foundation+4, //Returned when the key identified by NetKeyIndex is not stored in the node bg_err_mesh_foundation_insufficient_resources =bg_errspc_mesh_foundation+5, //Returned when The node cannot serve the request due to insufficient resources bg_err_mesh_foundation_key_index_exists =bg_errspc_mesh_foundation+6, //Returned when the key identified is already stored in the node and the new NetKey value is different bg_err_mesh_foundation_invalid_publish_params =bg_errspc_mesh_foundation+7, //Returned when the model does not support the publish mechanism bg_err_mesh_foundation_not_subscribe_model =bg_errspc_mesh_foundation+8, //Returned when the model does not support the subscribe mechanism bg_err_mesh_foundation_storage_failure =bg_errspc_mesh_foundation+9, //Returned when storing of the requested parameters failed bg_err_mesh_foundation_not_supported =bg_errspc_mesh_foundation+10,//Returned when requested setting is not supported bg_err_mesh_foundation_cannot_update =bg_errspc_mesh_foundation+11,//Returned when the requested update operation cannot be performed due to general constraints bg_err_mesh_foundation_cannot_remove =bg_errspc_mesh_foundation+12,//Returned when the requested delete operation cannot be performed due to general constraints bg_err_mesh_foundation_cannot_bind =bg_errspc_mesh_foundation+13,//Returned when the requested bind operation cannot be performed due to general constraints bg_err_mesh_foundation_temporarily_unable =bg_errspc_mesh_foundation+14,//Returned when The node cannot start advertising with Node Identity or Proxy since the maximum number of parallel advertising is reached bg_err_mesh_foundation_cannot_set =bg_errspc_mesh_foundation+15,//Returned when the requested state cannot be set bg_err_mesh_foundation_unspecified =bg_errspc_mesh_foundation+16,//Returned when an unspecified error took place bg_err_mesh_foundation_invalid_binding =bg_errspc_mesh_foundation+17,//Returned when the NetKeyIndex and AppKeyIndex combination is not valid for a Config AppKey Update bg_err_filesystem_file_not_found =bg_errspc_filesystem+1, //File not found bg_err_l2cap_remote_disconnected =bg_errspc_l2cap+1, //Returned when remote disconnects the connection-oriented channel by sending disconnection request. bg_err_l2cap_local_disconnected =bg_errspc_l2cap+2, //Returned when local host disconnect the connection-oriented channel by sending disconnection request. bg_err_l2cap_cid_not_exist =bg_errspc_l2cap+3, //Returned when local host did not find a connection-oriented channel with given destination CID. bg_err_l2cap_le_disconnected =bg_errspc_l2cap+4, //Returned when connection-oriented channel disconnected due to LE connection is dropped. bg_err_l2cap_flow_control_violated =bg_errspc_l2cap+5, //Returned when connection-oriented channel disconnected due to remote end send data even without credit. bg_err_l2cap_flow_control_credit_overflowed =bg_errspc_l2cap+6, //Returned when connection-oriented channel disconnected due to remote end send flow control credits exceed 65535. bg_err_l2cap_no_flow_control_credit =bg_errspc_l2cap+7, //Returned when connection-oriented channel has run out of flow control credit and local application still trying to send data. bg_err_l2cap_connection_request_timeout =bg_errspc_l2cap+8, //Returned when connection-oriented channel has not received connection response message within maximum timeout. bg_err_l2cap_invalid_cid =bg_errspc_l2cap+9, //Returned when local host received a connection-oriented channel connection response with an invalid destination CID. bg_err_l2cap_wrong_state =bg_errspc_l2cap+10, //Returned when local host application tries to send a command which is not suitable for L2CAP channel's current state. bg_err_security_image_signature_verification_failed =bg_errspc_security+1, //Device firmware signature verification failed. bg_err_security_file_signature_verification_failed =bg_errspc_security+2, //File signature verification failed. bg_err_security_image_checksum_error =bg_errspc_security+3, //Device firmware checksum is not valid. bg_err_last }errorcode_t; #endif |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/protocol/bluetooth/ble_stack/inc/common/bg_gattdb_def.h.
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/***************************************************************************//** * @brief Bluetooth GATT database structure definition ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * The licensor of this software is Silicon Laboratories Inc. Your use of this * software is governed by the terms of Silicon Labs Master Software License * Agreement (MSLA) available at * www.silabs.com/about-us/legal/master-software-license-agreement. This * software is distributed to you in Source Code format and is governed by the * sections of the MSLA applicable to Source Code. * ******************************************************************************/ #ifndef GATT_DEF_H #define GATT_DEF_H #include "bg_types.h" /* Datatype of attribute value */ enum gatt_att_datatype{ gatt_att_datatype_const, gatt_att_datatype_dynamic, /**<Fixed length attribute*/ gatt_att_datatype_dynamic_varlen, /**<Variable length attribute*/ gatt_att_datatype_clientconfig, gatt_att_datatype_serverconfig, gatt_att_datatype_privacy, /**< GAP privacy flag */ gatt_att_datatype_reconnection_address, gatt_att_datatype_user, /**<Attribute information is asked from user*/ gatt_att_datatype_data_parser=0xf0, /**< Internal datatype used by attr parser TODO: get rid of this*/ }; /* Attribute permissions */ enum gatt_att_perm{ gatt_att_perm_readable = 0x0001, gatt_att_perm_writable = 0x0002, gatt_att_perm_write_no_response = 0x0004, gatt_att_perm_encrypted_read = 0x0010, gatt_att_perm_authenticated_read = 0x0020, gatt_att_perm_bonded_read = 0x0040, gatt_att_perm_encrypted_write = 0x0100, gatt_att_perm_authenticated_write = 0x0200, gatt_att_perm_bonded_write = 0x0400, gatt_att_perm_discoverable = 0x0800, gatt_att_perm_encrypted_notify = 0x1000, gatt_att_perm_authenticated_notify = 0x2000, gatt_att_perm_bonded_notify = 0x4000, }; /* Characteristic properties */ enum gatt_char_prop{ gatt_char_prop_broadcast = 0x01, gatt_char_prop_read = 0x02, gatt_char_prop_writenoresp = 0x04, gatt_char_prop_write = 0x08, gatt_char_prop_notify = 0x10, gatt_char_prop_indicate = 0x20, gatt_char_prop_writesign = 0x40, gatt_char_prop_extended = 0x80, }; enum gatt_char_client_conf { gatt_char_client_conf_notification = 0x0001, gatt_char_client_conf_indication = 0x0002 }; /*Generic databuffer where first byte is length*/ struct bg_gattdb_buffer_with_len{ uint16_t len; //current size of data in buffer uint8_t data[]; //size is maxlen in attribute_chrvalue-struct }; struct bg_gattdb_attribute_chrvalue{ uint8_t properties; //Characteristic properties, same as in characteristic descriptor gatt_char_prop uint8_t index; //index used to map sending notifications and indications to correct bit in enable bitmask uint16_t max_len; //Maximum length of data in buffer union { uint8_t *data; struct bg_gattdb_buffer_with_len *data_varlen; }; }; struct bg_gattdb_attribute_config{ uint8_t flags; //client characteristic flags allowed 1-notification, 2-indication) uint8_t index; //reverse mapping to dynamic table uint8_t clientconfig_index; // index to client config. }; struct bg_gattdb_attribute{ uint16_t uuid; uint16_t permissions; //gatt_attribute_permission uint16_t caps; // Capability bit flags uint8_t min_key_size; // minumum key size required in bytes to access attribute uint8_t datatype; //Just use uint8_t Do not use enum type, may cause compatibility troubles union { const struct bg_gattdb_buffer_with_len *constdata; //generic constant data const struct bg_gattdb_attribute_chrvalue *dynamicdata; //Modifiable data struct bg_gattdb_attribute_config configdata; }; }; struct bg_gattdb_def{ const struct bg_gattdb_attribute *attributes; int attributes_max; int uuidtable_16_size; const uint16_t *uuidtable_16; int uuidtable_128_size; const uint8_t *uuidtable_128; int attributes_dynamic_max; const uint16_t *attributes_dynamic_mapping; //Table mapping dynamic indexes to attribute table index //Advertised services tables const uint8_t *adv_uuid16; int adv_uuid16_num; const uint8_t *adv_uuid128; int adv_uuid128_num; uint16_t caps_mask; uint16_t enabled_caps; }; extern const struct bg_gattdb_def *bg_gattdb; #endif |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/protocol/bluetooth/ble_stack/inc/common/bg_types.h.
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/***************************************************************************//** * @brief Basic types used in Bluetooth stack ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * The licensor of this software is Silicon Laboratories Inc. Your use of this * software is governed by the terms of Silicon Labs Master Software License * Agreement (MSLA) available at * www.silabs.com/about-us/legal/master-software-license-agreement. This * software is distributed to you in Source Code format and is governed by the * sections of the MSLA applicable to Source Code. * ******************************************************************************/ #ifndef BG_TYPES_H #define BG_TYPES_H #include <stdint.h> #include <stddef.h> typedef uint8_t uint8; typedef uint16_t uint16; typedef uint32_t uint32; typedef int8_t int8; typedef int16_t int16; typedef int32_t int32; typedef struct { uint8 len; uint8 data[]; }uint8array; typedef struct { uint16 len; uint8 data[]; }uint16array; typedef struct { uint8 len; int8 data[]; }string; typedef struct { uint8 addr[6]; }bd_addr; typedef struct { uint8 name[16]; }ser_name; typedef struct { uint8 data[16]; } uuid_128; typedef struct { uint8 data[16]; } aes_key_128; #define MAX_UUID_LEN 16 typedef struct { uint8_t uuid[MAX_UUID_LEN]; uint32_t len; } sl_bt_uuid_t; #if !defined _MSC_VER && !defined __APPLE__ /* Don't define under MSVC and OSX */ #ifndef memcpy void * memcpy(void *OUT, const void *IN, size_t N); #endif #ifndef memcmp int memcmp(const void *S1, const void *S2, size_t N); #endif #ifndef memset void * memset(void *DST, int c, size_t LENGTH); #endif #ifndef memmove void * memmove(void *DST, const void *src, size_t LENGTH); #endif #endif #endif |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/protocol/bluetooth/ble_stack/inc/common/gecko_configuration.h.
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/***************************************************************************//** * @brief Definition of Bluetooth stack configuration ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * The licensor of this software is Silicon Laboratories Inc. Your use of this * software is governed by the terms of Silicon Labs Master Software License * Agreement (MSLA) available at * www.silabs.com/about-us/legal/master-software-license-agreement. This * software is distributed to you in Source Code format and is governed by the * sections of the MSLA applicable to Source Code. * ******************************************************************************/ #ifndef GECKO_CONFIGURATION #define GECKO_CONFIGURATION #include "bg_gattdb_def.h" #define DEFAULT_BLUETOOTH_HEAP(CONNECTIONS) (4824 +(CONNECTIONS)*(480)) #define SLEEP_FLAGS_DEEP_SLEEP_ENABLE 4 typedef struct { uint8_t flags; }gecko_sleep_config_t; // Link layer config: typedef struct { uint8_t scan_min; uint8_t scan_max; uint8_t adv_min; uint8_t adv_max; uint8_t conn_min; uint8_t conn_max; uint8_t init_min; uint8_t init_max; uint8_t threshold_coex; uint8_t rail_mapping_offset; uint8_t rail_mapping_range; uint8_t threshold_coex_req; uint8_t coex_pwm_period; uint8_t coex_pwm_dutycycle; uint8_t afh_scan_interval; }gecko_bluetooth_ll_priorities; //Default priority configuration #define GECKO_BLUETOOTH_PRIORITIES_DEFAULT { 191, 143, 175, 127, 135, 0, 55, 15, 175, 16, 16, 255, 0, 0, 0 } typedef struct { uint8_t max_connections; //!< Maximum number of connections to support, if 0 defaults to 4 uint8_t max_advertisers; //!< Maximum number of advertisers to support, if 0 defaults to 1 uint8_t max_periodic_sync; //!< Maximum number of periodic synchronizations to support, if 0 defaults to 0 uint8_t max_channels; // Maximum number of L2cap Connection-oriented channels to support, if 0 defaults to 0 //heap configuration, if NULL uses default void *heap; uint16_t heap_size; uint16_t sleep_clock_accuracy; // ppm, 0 = default (250 ppm) uint32_t linklayer_config; gecko_bluetooth_ll_priorities * linklayer_priorities; //Priority configuration, if NULL uses default values }gecko_bluetooth_config_t; /** PAVDD input straight from power supply */ #define GECKO_RADIO_PA_INPUT_VBAT 0 /** PAVDD input from DC/DC */ #define GECKO_RADIO_PA_INPUT_DCDC 1 typedef struct { uint8_t config_enable; // Non-zero value indicates this is a valid PA config uint8_t input; // PAVDD input, either GECKO_RADIO_PA_INPUT_VBAT or GECKO_RADIO_PA_INPUT_DCDC // default: GECKO_RADIO_PA_INPUT_DCDC uint8_t pa_mode; // Selected PA power mode. // See power mode definitions in RAIL rail_chip_specific.h. If the given mode is not // supported by the device the stack will try with a lower mode. If power mode eventually // failed to configure, an error will be returned from gecko_stack_init or gecko_init. // Default value: RAIL_TX_POWER_MODE_2P4_HP }gecko_radio_pa_config_t; #define GECKO_OTA_FLAGS_RANDOM_ADDRESS 0x10000 typedef struct { uint32_t flags; uint8_t device_name_len; char *device_name_ptr; }gecko_ota_config_t; #define GECKO_MBEDTLS_FLAGS_NO_MBEDTLS_DEVICE_INIT 1 typedef struct { uint8_t flags; uint8_t dev_number; }gecko_mbedtls_config_t; #define GECKO_CONFIG_FLAG_RTOS 256 #define GECKO_CONFIG_FLAG_NO_SLEEPDRV_INIT 512 typedef void (*gecko_priority_schedule_callback)(void); typedef void (*gecko_stack_schedule_callback)(void); typedef struct { int16_t tx_gain; // RF TX gain in unit of 0.1 dBm. For example, -20 means -2.0 dBm (signal loss). int16_t rx_gain; // RF RX gain in unit of 0.1 dBm. } gecko_rf_config_t; typedef struct { uint32_t config_flags; gecko_sleep_config_t sleep; gecko_bluetooth_config_t bluetooth; // const struct bg_gattdb_def *gattdb; //Callback for priority scheduling, used for RTOS support. If NULL uses pendsv irq. //This is called from Interrupt context gecko_priority_schedule_callback scheduler_callback; //Callback for requesting Bluetooth stack scheduling, used for RTOS support //This is called from Interrupt context gecko_stack_schedule_callback stack_schedule_callback; gecko_radio_pa_config_t pa; gecko_ota_config_t ota; gecko_mbedtls_config_t mbedtls; uint8_t max_timers; // Max number of soft timers, up to 16, the application will use through BGAPI. Default: 4 gecko_rf_config_t rf; uint16_t btmesh_heap_size; // The amount of heap reserved for the BT Mesh stack }gecko_configuration_t; #endif |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/protocol/bluetooth/ble_stack/inc/soc/bg_version.h.
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/***************************************************************************//** * @brief Bluetooth stack version definition ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * The licensor of this software is Silicon Laboratories Inc. Your use of this * software is governed by the terms of Silicon Labs Master Software License * Agreement (MSLA) available at * www.silabs.com/about-us/legal/master-software-license-agreement. This * software is distributed to you in Source Code format and is governed by the * sections of the MSLA applicable to Source Code. * ******************************************************************************/ #ifndef VERSION_H #define VERSION_H #define BG_VERSION_MAJOR 2 #define BG_VERSION_MINOR 11 #define BG_VERSION_PATCH 1 #define BG_VERSION_BUILD 241 #define BG_VERSION_HASH {0x59,0xf3,0xa0,0x12,0x2a,0x5e,0x7d,0x67,0xe7,0x95,0x43,0x90,0x54,0x88,0x0a,0x47,0xbb,0x54,0xf1,0xee} #endif |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/protocol/bluetooth/ble_stack/inc/soc/micca_gecko.h.
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> > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > 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/***************************************************************************//** * @brief Bluetooth BGAPI for applications in SoC mode ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * The licensor of this software is Silicon Laboratories Inc. Your use of this * software is governed by the terms of Silicon Labs Master Software License * Agreement (MSLA) available at * www.silabs.com/about-us/legal/master-software-license-agreement. This * software is distributed to you in Source Code format and is governed by the * sections of the MSLA applicable to Source Code. * ******************************************************************************/ #ifndef MICCA_GECKO_H #define MICCA_GECKO_H #ifdef __cplusplus extern "C" { #endif #ifdef HAL_CONFIG #include "hal-config.h" #endif #include <string.h> #include "bg_types.h" #include "gecko_configuration.h" #include "bg_errorcodes.h" /* Compatibility */ #ifndef PACKSTRUCT /*Default packed configuration*/ #ifdef __GNUC__ #ifdef _WIN32 #define PACKSTRUCT( decl ) decl __attribute__((__packed__,gcc_struct)) #else #define PACKSTRUCT( decl ) decl __attribute__((__packed__)) #endif #define ALIGNED __attribute__((aligned(0x4))) #elif __IAR_SYSTEMS_ICC__ #define PACKSTRUCT( decl ) __packed decl #define ALIGNED #elif _MSC_VER /*msvc*/ #define PACKSTRUCT( decl ) __pragma( pack(push, 1) ) decl __pragma( pack(pop) ) #define ALIGNED #else #define PACKSTRUCT(a) a PACKED #endif #endif #define BGLIB_DEPRECATED_API __attribute__((deprecated)) #define BGLIB_MSG_ID(HDR) ((HDR)&0xffff00f8) #define BGLIB_MSG_HEADER_LEN (4) #define BGLIB_MSG_LEN(HDR) ((((HDR)&0x7)<<8)|(((HDR)&0xff00)>>8)) /** * Blocks until new event arrives which requires processing by user application. * * @return pointer to received event */ struct gecko_cmd_packet* gecko_wait_event(void); /** * Same as gecko_wait_event but does not block if no events waiting, instead returns NULL * * @return pointer to received event or NULL if no event waiting */ struct gecko_cmd_packet* gecko_peek_event(void); /** * Events are in queue waiting for processing * Call gecko_wait_event or gecko_peek_event to process pending events * * @return nonzero if processing required */ int gecko_event_pending(void); /** * Initialize stack. * @param config The pointer to configuration parameters, cannot be NULL. * @return bg_err_success if the initialization was successful; Other error code * indicates a failure on initializing persistent storage. */ errorcode_t gecko_stack_init(const gecko_configuration_t *config); /** * Initialize multiprotocol. Please note that multiprotocol version of RAIL * is needed. * @param config, set to NULL */ void gecko_init_multiprotocol(const void *config); /** * Poll the stack how long it can sleep until the time it will process the next message. * A very large returned value indicates that the stack does not have pending message to process. * For example, 0x07CFFFFF will be returned in this case when the clock frequency is 32768 ticks per second. * @return maximum sleep time in milliseconds; 0 if the stack cannot sleep */ uint32 gecko_can_sleep_ms(void); /** * Poll the stack how long it can sleep until the time it will process the next message. * @return maximum sleep time in ticks; 0 if the stack cannot sleep; 0xFFFFFFFF if it has no pending message */ uint32 gecko_can_sleep_ticks(void); /** * Priority message handler function if user application requires the use of PendSV interrupt. * * If scheduler_callback function pointer in configuration struct is something else than NULL, * then stack will not install its own PendSV IRQ handler but instead uses callback/handler functions. * * When application receives call to the scheduler_callback function it must schedule the call to * gecko_priority_handle function to later time to run on high priority thread. This callback * may happen inside radio IRQ so processing must not block and has to happen as fast as possible. * * Recommended implemenation: * High priority thread is loop that waits on binary semaphore and calls gecko_priority_handler. * The scheduler_callback is simple function that only signals the semaphore. * */ void gecko_priority_handle(void); /** * Put the stack to sleep for a maximum of @param max milliseconds. * Note that the stack may wake up earlier due to an external event. * @return number of milliseconds actually slept. */ uint32 gecko_sleep_for_ms(uint32 max); /** * Signals stack that external event has happened. Signals can be used to report status change from interrupt * context or from other threads to application. Signals are bits that are automatically cleared after * application has been notified. * * @param signals is a bitmask defining active signals that are reported back to the application by system_external_signal-event. * */ void gecko_external_signal(uint32 signals); /** * Signals stack to send system_awake event when application received wakeup signal. */ void gecko_send_system_awake(); /** * Signals stack to send system_error event when in case of an error. */ void gecko_send_system_error(uint16 reason, uint8 data_len, const uint8* data); enum le_gap_address_type { le_gap_address_type_public = 0x0, le_gap_address_type_random = 0x1, le_gap_address_type_public_identity = 0x2, le_gap_address_type_random_identity = 0x3 }; enum le_gap_phy_type { le_gap_phy_1m = 0x1, le_gap_phy_2m = 0x2, le_gap_phy_coded = 0x4 }; enum le_gap_connectable_mode { le_gap_non_connectable = 0x0, le_gap_directed_connectable = 0x1, le_gap_undirected_connectable = 0x2, le_gap_connectable_scannable = 0x2, le_gap_scannable_non_connectable = 0x3, le_gap_connectable_non_scannable = 0x4 }; enum le_gap_discoverable_mode { le_gap_non_discoverable = 0x0, le_gap_limited_discoverable = 0x1, le_gap_general_discoverable = 0x2, le_gap_broadcast = 0x3, le_gap_user_data = 0x4 }; enum le_gap_discover_mode { le_gap_discover_limited = 0x0, le_gap_discover_generic = 0x1, le_gap_discover_observation = 0x2 }; enum le_gap_adv_address_type { le_gap_identity_address = 0x0, le_gap_non_resolvable = 0x1 }; enum sync_advertiser_clock_accuracy { sync_clock_accuracy_500 = 0x1f4, sync_clock_accuracy_250 = 0xfa, sync_clock_accuracy_150 = 0x96, sync_clock_accuracy_100 = 0x64, sync_clock_accuracy_75 = 0x4b, sync_clock_accuracy_50 = 0x32, sync_clock_accuracy_30 = 0x1e, sync_clock_accuracy_20 = 0x14 }; enum le_connection_security { le_connection_mode1_level1 = 0x0, le_connection_mode1_level2 = 0x1, le_connection_mode1_level3 = 0x2, le_connection_mode1_level4 = 0x3 }; enum gatt_att_opcode { gatt_read_by_type_request = 0x8, gatt_read_by_type_response = 0x9, gatt_read_request = 0xa, gatt_read_response = 0xb, gatt_read_blob_request = 0xc, gatt_read_blob_response = 0xd, gatt_read_multiple_request = 0xe, gatt_read_multiple_response = 0xf, gatt_write_request = 0x12, gatt_write_response = 0x13, gatt_write_command = 0x52, gatt_prepare_write_request = 0x16, gatt_prepare_write_response = 0x17, gatt_execute_write_request = 0x18, gatt_execute_write_response = 0x19, gatt_handle_value_notification = 0x1b, gatt_handle_value_indication = 0x1d }; enum gatt_client_config_flag { gatt_disable = 0x0, gatt_notification = 0x1, gatt_indication = 0x2 }; enum gatt_execute_write_flag { gatt_cancel = 0x0, gatt_commit = 0x1 }; enum gatt_server_characteristic_status_flag { gatt_server_client_config = 0x1, gatt_server_confirmation = 0x2 }; enum test_packet_type { test_pkt_prbs9 = 0x0, test_pkt_11110000 = 0x1, test_pkt_10101010 = 0x2, test_pkt_11111111 = 0x4, test_pkt_00000000 = 0x5, test_pkt_00001111 = 0x6, test_pkt_01010101 = 0x7, test_pkt_pn9 = 0xfd, test_pkt_carrier = 0xfe }; enum test_phy { test_phy_1m = 0x1, test_phy_2m = 0x2, test_phy_125k = 0x3, test_phy_500k = 0x4 }; enum sm_bonding_key { sm_bonding_key_ltk = 0x1, sm_bonding_key_addr_public = 0x2, sm_bonding_key_addr_static = 0x4, sm_bonding_key_irk = 0x8, sm_bonding_key_edivrand = 0x10, sm_bonding_key_csrk = 0x20, sm_bonding_key_masterid = 0x40 }; enum sm_io_capability { sm_io_capability_displayonly = 0x0, sm_io_capability_displayyesno = 0x1, sm_io_capability_keyboardonly = 0x2, sm_io_capability_noinputnooutput = 0x3, sm_io_capability_keyboarddisplay = 0x4 }; enum homekit_category { homekit_not_allowed = 0x0, homekit_other = 0x1, homekit_bridge = 0x2, homekit_fan = 0x3, homekit_garage = 0x4, homekit_lightbulb = 0x5, homekit_doorlock = 0x6, homekit_outlet = 0x7, homekit_switch_accessory = 0x8, homekit_thermostat = 0x9, homekit_sensor = 0xa, homekit_security_system = 0xb, homekit_door = 0xc, homekit_window = 0xd, homekit_window_covering = 0xe, homekit_programmable_switch = 0xf, homekit_ip_camera = 0x11, homekit_video_door_bell = 0x12, homekit_air_purifier = 0x13, homekit_heater = 0x14, homekit_air_conditioner = 0x15, homekit_humidifier = 0x16, homekit_dehumidifier = 0x17, homekit_sprinkler = 0x1c, homekit_faucet = 0x1d, homekit_shower_system = 0x1e, homekit_remote = 0x20 }; enum homekit_status_code { homekit_success = 0x0, homekit_invalid_request = 0x6 }; enum coex_option { coex_option_enable = 0x100, coex_option_tx_abort = 0x400, coex_option_high_priority = 0x800 }; enum l2cap_coc_connection_result { l2cap_connection_successful = 0x0, l2cap_le_psm_not_supported = 0x2, l2cap_no_resources_available = 0x4, l2cap_insufficient_authentication = 0x5, l2cap_insufficient_authorization = 0x6, l2cap_insufficient_encryption_key_size = 0x7, l2cap_insufficient_encryption = 0x8, l2cap_invalid_source_cid = 0x9, l2cap_source_cid_already_allocated = 0xa, l2cap_unacceptable_parameters = 0xb }; enum l2cap_command_reject_reason { l2cap_command_not_understood = 0x0, l2cap_signaling_mtu_exceeded = 0x1, l2cap_invalid_cid_request = 0x2 }; enum l2cap_command_code { l2cap_disconnection_request = 0x6, l2cap_connection_request = 0x14, l2cap_flow_control_credit = 0x16 }; enum gecko_parameter_types { gecko_msg_parameter_uint8=2, gecko_msg_parameter_int8=3, gecko_msg_parameter_uint16=4, gecko_msg_parameter_int16=5, gecko_msg_parameter_uint32=6, gecko_msg_parameter_int32=7, gecko_msg_parameter_uint8array=8, gecko_msg_parameter_string=9, gecko_msg_parameter_hwaddr=10, gecko_msg_parameter_uint16array=11 }; enum gecko_msg_types { gecko_msg_type_cmd=0x00, gecko_msg_type_rsp=0x00, gecko_msg_type_evt=0x80 }; enum gecko_dev_types { gecko_dev_type_gecko =0x20 }; #define FLASH_PS_KEY_LOCAL_BD_ADDR 0x2c #define FLASH_PS_KEY_TX_POWER 0x31 #define FLASH_PS_KEY_CTUNE 0x32 #define FLASH_PS_KEY_APPLICATION_GSN 0x33 #define FLASH_PS_KEY_OTA_FLAGS 0x35 #define FLASH_PS_KEY_OTA_DEVICE_NAME 0x36 #define FLASH_PS_KEY_DEVICE_IRK 0x37 #define FLASH_PS_KEY_BONDING_PRIORITY_LIST 0x38 #define FLASH_PS_KEY_OTA_ADVERTISEMENT_PACKET 0x39 #define FLASH_PS_KEY_OTA_SCAN_RESPONSE_PACKET 0x3a #define FLASH_PS_KEY_APPLICATION_AI 0x3b #define FLASH_PS_KEY_IDENTITY_ADDR_TYPE 0x3c #define FLASH_PS_KEY_GATT_DB_HASH 0x3d #define FLASH_PS_KEY_BONDING_DB_CONFIG 0x3fff #define gecko_cmd_dfu_reset_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x00000000) #define gecko_cmd_dfu_flash_set_address_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x01000000) #define gecko_cmd_dfu_flash_upload_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x02000000) #define gecko_cmd_dfu_flash_upload_finish_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x03000000) #define gecko_cmd_system_hello_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x00010000) #define gecko_cmd_system_reset_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x01010000) #define gecko_cmd_system_get_bt_address_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x03010000) #define gecko_cmd_system_set_bt_address_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x04010000) #define gecko_cmd_system_set_tx_power_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x0a010000) #define gecko_cmd_system_get_random_data_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x0b010000) #define gecko_cmd_system_halt_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x0c010000) #define gecko_cmd_system_set_device_name_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x0d010000) #define gecko_cmd_system_linklayer_configure_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x0e010000) #define gecko_cmd_system_get_counters_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x0f010000) #define gecko_cmd_system_set_identity_address_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x13010000) #define gecko_cmd_le_gap_open_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x00030000) #define gecko_cmd_le_gap_set_mode_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x01030000) #define gecko_cmd_le_gap_discover_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x02030000) #define gecko_cmd_le_gap_end_procedure_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x03030000) #define gecko_cmd_le_gap_set_adv_parameters_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x04030000) #define gecko_cmd_le_gap_set_conn_parameters_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x05030000) #define gecko_cmd_le_gap_set_scan_parameters_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x06030000) #define gecko_cmd_le_gap_set_adv_data_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x07030000) #define gecko_cmd_le_gap_set_adv_timeout_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x08030000) #define gecko_cmd_le_gap_bt5_set_mode_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x0a030000) #define gecko_cmd_le_gap_bt5_set_adv_parameters_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x0b030000) #define gecko_cmd_le_gap_bt5_set_adv_data_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x0c030000) #define gecko_cmd_le_gap_set_privacy_mode_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x0d030000) #define gecko_cmd_le_gap_set_advertise_timing_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x0e030000) #define gecko_cmd_le_gap_set_advertise_channel_map_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x0f030000) #define gecko_cmd_le_gap_set_advertise_report_scan_request_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x10030000) #define gecko_cmd_le_gap_set_advertise_phy_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x11030000) #define gecko_cmd_le_gap_set_advertise_configuration_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x12030000) #define gecko_cmd_le_gap_clear_advertise_configuration_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x13030000) #define gecko_cmd_le_gap_start_advertising_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x14030000) #define gecko_cmd_le_gap_stop_advertising_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x15030000) #define gecko_cmd_le_gap_set_discovery_timing_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x16030000) #define gecko_cmd_le_gap_set_discovery_type_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x17030000) #define gecko_cmd_le_gap_start_discovery_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x18030000) #define gecko_cmd_le_gap_set_data_channel_classification_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x19030000) #define gecko_cmd_le_gap_connect_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x1a030000) #define gecko_cmd_le_gap_set_advertise_tx_power_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x1b030000) #define gecko_cmd_le_gap_set_discovery_extended_scan_response_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x1c030000) #define gecko_cmd_le_gap_start_periodic_advertising_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x1d030000) #define gecko_cmd_le_gap_stop_periodic_advertising_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x1f030000) #define gecko_cmd_le_gap_enable_whitelisting_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x21030000) #define gecko_cmd_sync_open_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x00420000) #define gecko_cmd_sync_close_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x01420000) #define gecko_cmd_le_connection_set_parameters_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x00080000) #define gecko_cmd_le_connection_get_rssi_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x01080000) #define gecko_cmd_le_connection_disable_slave_latency_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x02080000) #define gecko_cmd_le_connection_set_phy_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x03080000) #define gecko_cmd_le_connection_close_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x04080000) #define gecko_cmd_gatt_set_max_mtu_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x00090000) #define gecko_cmd_gatt_discover_primary_services_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x01090000) #define gecko_cmd_gatt_discover_primary_services_by_uuid_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x02090000) #define gecko_cmd_gatt_discover_characteristics_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x03090000) #define gecko_cmd_gatt_discover_characteristics_by_uuid_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x04090000) #define gecko_cmd_gatt_set_characteristic_notification_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x05090000) #define gecko_cmd_gatt_discover_descriptors_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x06090000) #define gecko_cmd_gatt_read_characteristic_value_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x07090000) #define gecko_cmd_gatt_read_characteristic_value_by_uuid_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x08090000) #define gecko_cmd_gatt_write_characteristic_value_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x09090000) #define gecko_cmd_gatt_write_characteristic_value_without_response_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x0a090000) #define gecko_cmd_gatt_prepare_characteristic_value_write_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x0b090000) #define gecko_cmd_gatt_execute_characteristic_value_write_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x0c090000) #define gecko_cmd_gatt_send_characteristic_confirmation_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x0d090000) #define gecko_cmd_gatt_read_descriptor_value_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x0e090000) #define gecko_cmd_gatt_write_descriptor_value_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x0f090000) #define gecko_cmd_gatt_find_included_services_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x10090000) #define gecko_cmd_gatt_read_multiple_characteristic_values_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x11090000) #define gecko_cmd_gatt_read_characteristic_value_from_offset_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x12090000) #define gecko_cmd_gatt_prepare_characteristic_value_reliable_write_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x13090000) #define gecko_cmd_gatt_server_read_attribute_value_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x000a0000) #define gecko_cmd_gatt_server_read_attribute_type_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x010a0000) #define gecko_cmd_gatt_server_write_attribute_value_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x020a0000) #define gecko_cmd_gatt_server_send_user_read_response_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x030a0000) #define gecko_cmd_gatt_server_send_user_write_response_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x040a0000) #define gecko_cmd_gatt_server_send_characteristic_notification_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x050a0000) #define gecko_cmd_gatt_server_find_attribute_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x060a0000) #define gecko_cmd_gatt_server_set_capabilities_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x080a0000) #define gecko_cmd_hardware_set_soft_timer_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x000c0000) #define gecko_cmd_hardware_get_time_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x0b0c0000) #define gecko_cmd_hardware_set_lazy_soft_timer_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x0c0c0000) #define gecko_cmd_flash_ps_erase_all_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x010d0000) #define gecko_cmd_flash_ps_save_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x020d0000) #define gecko_cmd_flash_ps_load_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x030d0000) #define gecko_cmd_flash_ps_erase_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x040d0000) #define gecko_cmd_test_dtm_tx_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x000e0000) #define gecko_cmd_test_dtm_rx_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x010e0000) #define gecko_cmd_test_dtm_end_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x020e0000) #define gecko_cmd_sm_set_bondable_mode_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x000f0000) #define gecko_cmd_sm_configure_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x010f0000) #define gecko_cmd_sm_store_bonding_configuration_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x020f0000) #define gecko_cmd_sm_increase_security_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x040f0000) #define gecko_cmd_sm_delete_bonding_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x060f0000) #define gecko_cmd_sm_delete_bondings_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x070f0000) #define gecko_cmd_sm_enter_passkey_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x080f0000) #define gecko_cmd_sm_passkey_confirm_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x090f0000) #define gecko_cmd_sm_set_oob_data_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x0a0f0000) #define gecko_cmd_sm_list_all_bondings_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x0b0f0000) #define gecko_cmd_sm_bonding_confirm_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x0e0f0000) #define gecko_cmd_sm_set_debug_mode_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x0f0f0000) #define gecko_cmd_sm_set_passkey_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x100f0000) #define gecko_cmd_sm_use_sc_oob_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x110f0000) #define gecko_cmd_sm_set_sc_remote_oob_data_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x120f0000) #define gecko_cmd_sm_add_to_whitelist_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x130f0000) #define gecko_cmd_homekit_configure_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x00130000) #define gecko_cmd_homekit_advertise_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x01130000) #define gecko_cmd_homekit_delete_pairings_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x02130000) #define gecko_cmd_homekit_check_authcp_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x03130000) #define gecko_cmd_homekit_get_pairing_id_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x04130000) #define gecko_cmd_homekit_send_write_response_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x05130000) #define gecko_cmd_homekit_send_read_response_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x06130000) #define gecko_cmd_homekit_gsn_action_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x07130000) #define gecko_cmd_homekit_event_notification_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x08130000) #define gecko_cmd_homekit_broadcast_action_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x09130000) #define gecko_cmd_coex_set_options_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x00200000) #define gecko_cmd_coex_get_counters_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x01200000) #define gecko_cmd_l2cap_coc_send_connection_request_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x01430000) #define gecko_cmd_l2cap_coc_send_connection_response_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x02430000) #define gecko_cmd_l2cap_coc_send_le_flow_control_credit_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x03430000) #define gecko_cmd_l2cap_coc_send_disconnection_request_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x04430000) #define gecko_cmd_l2cap_coc_send_data_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x05430000) #define gecko_cmd_cte_transmitter_enable_cte_response_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x00440000) #define gecko_cmd_cte_transmitter_disable_cte_response_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x01440000) #define gecko_cmd_cte_transmitter_start_connectionless_cte_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x02440000) #define gecko_cmd_cte_transmitter_stop_connectionless_cte_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x03440000) #define gecko_cmd_cte_transmitter_set_dtm_parameters_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x04440000) #define gecko_cmd_cte_transmitter_clear_dtm_parameters_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x05440000) #define gecko_cmd_cte_receiver_configure_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x00450000) #define gecko_cmd_cte_receiver_start_iq_sampling_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x01450000) #define gecko_cmd_cte_receiver_stop_iq_sampling_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x02450000) #define gecko_cmd_cte_receiver_start_connectionless_iq_sampling_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x03450000) #define gecko_cmd_cte_receiver_stop_connectionless_iq_sampling_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x04450000) #define gecko_cmd_cte_receiver_set_dtm_parameters_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x05450000) #define gecko_cmd_cte_receiver_clear_dtm_parameters_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x06450000) #define gecko_cmd_user_message_to_target_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_cmd|0x00ff0000) #define gecko_rsp_dfu_flash_set_address_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x01000000) #define gecko_rsp_dfu_flash_upload_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x02000000) #define gecko_rsp_dfu_flash_upload_finish_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x03000000) #define gecko_rsp_system_hello_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x00010000) #define gecko_rsp_system_get_bt_address_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x03010000) #define gecko_rsp_system_set_bt_address_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x04010000) #define gecko_rsp_system_set_tx_power_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x0a010000) #define gecko_rsp_system_get_random_data_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x0b010000) #define gecko_rsp_system_halt_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x0c010000) #define gecko_rsp_system_set_device_name_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x0d010000) #define gecko_rsp_system_linklayer_configure_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x0e010000) #define gecko_rsp_system_get_counters_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x0f010000) #define gecko_rsp_system_set_identity_address_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x13010000) #define gecko_rsp_le_gap_open_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x00030000) #define gecko_rsp_le_gap_set_mode_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x01030000) #define gecko_rsp_le_gap_discover_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x02030000) #define gecko_rsp_le_gap_end_procedure_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x03030000) #define gecko_rsp_le_gap_set_adv_parameters_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x04030000) #define gecko_rsp_le_gap_set_conn_parameters_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x05030000) #define gecko_rsp_le_gap_set_scan_parameters_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x06030000) #define gecko_rsp_le_gap_set_adv_data_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x07030000) #define gecko_rsp_le_gap_set_adv_timeout_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x08030000) #define gecko_rsp_le_gap_bt5_set_mode_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x0a030000) #define gecko_rsp_le_gap_bt5_set_adv_parameters_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x0b030000) #define gecko_rsp_le_gap_bt5_set_adv_data_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x0c030000) #define gecko_rsp_le_gap_set_privacy_mode_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x0d030000) #define gecko_rsp_le_gap_set_advertise_timing_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x0e030000) #define gecko_rsp_le_gap_set_advertise_channel_map_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x0f030000) #define gecko_rsp_le_gap_set_advertise_report_scan_request_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x10030000) #define gecko_rsp_le_gap_set_advertise_phy_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x11030000) #define gecko_rsp_le_gap_set_advertise_configuration_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x12030000) #define gecko_rsp_le_gap_clear_advertise_configuration_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x13030000) #define gecko_rsp_le_gap_start_advertising_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x14030000) #define gecko_rsp_le_gap_stop_advertising_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x15030000) #define gecko_rsp_le_gap_set_discovery_timing_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x16030000) #define gecko_rsp_le_gap_set_discovery_type_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x17030000) #define gecko_rsp_le_gap_start_discovery_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x18030000) #define gecko_rsp_le_gap_set_data_channel_classification_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x19030000) #define gecko_rsp_le_gap_connect_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x1a030000) #define gecko_rsp_le_gap_set_advertise_tx_power_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x1b030000) #define gecko_rsp_le_gap_set_discovery_extended_scan_response_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x1c030000) #define gecko_rsp_le_gap_start_periodic_advertising_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x1d030000) #define gecko_rsp_le_gap_stop_periodic_advertising_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x1f030000) #define gecko_rsp_le_gap_enable_whitelisting_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x21030000) #define gecko_rsp_sync_open_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x00420000) #define gecko_rsp_sync_close_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x01420000) #define gecko_rsp_le_connection_set_parameters_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x00080000) #define gecko_rsp_le_connection_get_rssi_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x01080000) #define gecko_rsp_le_connection_disable_slave_latency_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x02080000) #define gecko_rsp_le_connection_set_phy_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x03080000) #define gecko_rsp_le_connection_close_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x04080000) #define gecko_rsp_gatt_set_max_mtu_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x00090000) #define gecko_rsp_gatt_discover_primary_services_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x01090000) #define gecko_rsp_gatt_discover_primary_services_by_uuid_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x02090000) #define gecko_rsp_gatt_discover_characteristics_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x03090000) #define gecko_rsp_gatt_discover_characteristics_by_uuid_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x04090000) #define gecko_rsp_gatt_set_characteristic_notification_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x05090000) #define gecko_rsp_gatt_discover_descriptors_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x06090000) #define gecko_rsp_gatt_read_characteristic_value_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x07090000) #define gecko_rsp_gatt_read_characteristic_value_by_uuid_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x08090000) #define gecko_rsp_gatt_write_characteristic_value_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x09090000) #define gecko_rsp_gatt_write_characteristic_value_without_response_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x0a090000) #define gecko_rsp_gatt_prepare_characteristic_value_write_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x0b090000) #define gecko_rsp_gatt_execute_characteristic_value_write_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x0c090000) #define gecko_rsp_gatt_send_characteristic_confirmation_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x0d090000) #define gecko_rsp_gatt_read_descriptor_value_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x0e090000) #define gecko_rsp_gatt_write_descriptor_value_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x0f090000) #define gecko_rsp_gatt_find_included_services_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x10090000) #define gecko_rsp_gatt_read_multiple_characteristic_values_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x11090000) #define gecko_rsp_gatt_read_characteristic_value_from_offset_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x12090000) #define gecko_rsp_gatt_prepare_characteristic_value_reliable_write_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x13090000) #define gecko_rsp_gatt_server_read_attribute_value_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x000a0000) #define gecko_rsp_gatt_server_read_attribute_type_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x010a0000) #define gecko_rsp_gatt_server_write_attribute_value_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x020a0000) #define gecko_rsp_gatt_server_send_user_read_response_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x030a0000) #define gecko_rsp_gatt_server_send_user_write_response_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x040a0000) #define gecko_rsp_gatt_server_send_characteristic_notification_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x050a0000) #define gecko_rsp_gatt_server_find_attribute_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x060a0000) #define gecko_rsp_gatt_server_set_capabilities_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x080a0000) #define gecko_rsp_hardware_set_soft_timer_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x000c0000) #define gecko_rsp_hardware_get_time_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x0b0c0000) #define gecko_rsp_hardware_set_lazy_soft_timer_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x0c0c0000) #define gecko_rsp_flash_ps_erase_all_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x010d0000) #define gecko_rsp_flash_ps_save_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x020d0000) #define gecko_rsp_flash_ps_load_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x030d0000) #define gecko_rsp_flash_ps_erase_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x040d0000) #define gecko_rsp_test_dtm_tx_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x000e0000) #define gecko_rsp_test_dtm_rx_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x010e0000) #define gecko_rsp_test_dtm_end_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x020e0000) #define gecko_rsp_sm_set_bondable_mode_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x000f0000) #define gecko_rsp_sm_configure_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x010f0000) #define gecko_rsp_sm_store_bonding_configuration_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x020f0000) #define gecko_rsp_sm_increase_security_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x040f0000) #define gecko_rsp_sm_delete_bonding_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x060f0000) #define gecko_rsp_sm_delete_bondings_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x070f0000) #define gecko_rsp_sm_enter_passkey_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x080f0000) #define gecko_rsp_sm_passkey_confirm_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x090f0000) #define gecko_rsp_sm_set_oob_data_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x0a0f0000) #define gecko_rsp_sm_list_all_bondings_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x0b0f0000) #define gecko_rsp_sm_bonding_confirm_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x0e0f0000) #define gecko_rsp_sm_set_debug_mode_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x0f0f0000) #define gecko_rsp_sm_set_passkey_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x100f0000) #define gecko_rsp_sm_use_sc_oob_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x110f0000) #define gecko_rsp_sm_set_sc_remote_oob_data_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x120f0000) #define gecko_rsp_sm_add_to_whitelist_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x130f0000) #define gecko_rsp_homekit_configure_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x00130000) #define gecko_rsp_homekit_advertise_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x01130000) #define gecko_rsp_homekit_delete_pairings_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x02130000) #define gecko_rsp_homekit_check_authcp_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x03130000) #define gecko_rsp_homekit_get_pairing_id_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x04130000) #define gecko_rsp_homekit_send_write_response_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x05130000) #define gecko_rsp_homekit_send_read_response_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x06130000) #define gecko_rsp_homekit_gsn_action_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x07130000) #define gecko_rsp_homekit_event_notification_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x08130000) #define gecko_rsp_homekit_broadcast_action_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x09130000) #define gecko_rsp_coex_set_options_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x00200000) #define gecko_rsp_coex_get_counters_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x01200000) #define gecko_rsp_l2cap_coc_send_connection_request_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x01430000) #define gecko_rsp_l2cap_coc_send_connection_response_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x02430000) #define gecko_rsp_l2cap_coc_send_le_flow_control_credit_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x03430000) #define gecko_rsp_l2cap_coc_send_disconnection_request_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x04430000) #define gecko_rsp_l2cap_coc_send_data_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x05430000) #define gecko_rsp_cte_transmitter_enable_cte_response_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x00440000) #define gecko_rsp_cte_transmitter_disable_cte_response_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x01440000) #define gecko_rsp_cte_transmitter_start_connectionless_cte_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x02440000) #define gecko_rsp_cte_transmitter_stop_connectionless_cte_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x03440000) #define gecko_rsp_cte_transmitter_set_dtm_parameters_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x04440000) #define gecko_rsp_cte_transmitter_clear_dtm_parameters_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x05440000) #define gecko_rsp_cte_receiver_configure_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x00450000) #define gecko_rsp_cte_receiver_start_iq_sampling_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x01450000) #define gecko_rsp_cte_receiver_stop_iq_sampling_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x02450000) #define gecko_rsp_cte_receiver_start_connectionless_iq_sampling_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x03450000) #define gecko_rsp_cte_receiver_stop_connectionless_iq_sampling_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x04450000) #define gecko_rsp_cte_receiver_set_dtm_parameters_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x05450000) #define gecko_rsp_cte_receiver_clear_dtm_parameters_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x06450000) #define gecko_rsp_user_message_to_target_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_rsp|0x00ff0000) #define gecko_evt_dfu_boot_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_evt|0x00000000) #define gecko_evt_dfu_boot_failure_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_evt|0x01000000) #define gecko_evt_system_boot_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_evt|0x00010000) #define gecko_evt_system_external_signal_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_evt|0x03010000) #define gecko_evt_system_awake_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_evt|0x04010000) #define gecko_evt_system_hardware_error_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_evt|0x05010000) #define gecko_evt_system_error_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_evt|0x06010000) #define gecko_evt_le_gap_scan_response_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_evt|0x00030000) #define gecko_evt_le_gap_adv_timeout_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_evt|0x01030000) #define gecko_evt_le_gap_scan_request_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_evt|0x02030000) #define gecko_evt_le_gap_extended_scan_response_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_evt|0x04030000) #define gecko_evt_sync_opened_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_evt|0x00420000) #define gecko_evt_sync_closed_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_evt|0x01420000) #define gecko_evt_sync_data_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_evt|0x02420000) #define gecko_evt_le_connection_opened_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_evt|0x00080000) #define gecko_evt_le_connection_closed_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_evt|0x01080000) #define gecko_evt_le_connection_parameters_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_evt|0x02080000) #define gecko_evt_le_connection_rssi_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_evt|0x03080000) #define gecko_evt_le_connection_phy_status_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_evt|0x04080000) #define gecko_evt_gatt_mtu_exchanged_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_evt|0x00090000) #define gecko_evt_gatt_service_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_evt|0x01090000) #define gecko_evt_gatt_characteristic_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_evt|0x02090000) #define gecko_evt_gatt_descriptor_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_evt|0x03090000) #define gecko_evt_gatt_characteristic_value_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_evt|0x04090000) #define gecko_evt_gatt_descriptor_value_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_evt|0x05090000) #define gecko_evt_gatt_procedure_completed_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_evt|0x06090000) #define gecko_evt_gatt_server_attribute_value_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_evt|0x000a0000) #define gecko_evt_gatt_server_user_read_request_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_evt|0x010a0000) #define gecko_evt_gatt_server_user_write_request_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_evt|0x020a0000) #define gecko_evt_gatt_server_characteristic_status_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_evt|0x030a0000) #define gecko_evt_gatt_server_execute_write_completed_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_evt|0x040a0000) #define gecko_evt_hardware_soft_timer_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_evt|0x000c0000) #define gecko_evt_test_dtm_completed_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_evt|0x000e0000) #define gecko_evt_sm_passkey_display_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_evt|0x000f0000) #define gecko_evt_sm_passkey_request_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_evt|0x010f0000) #define gecko_evt_sm_confirm_passkey_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_evt|0x020f0000) #define gecko_evt_sm_bonded_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_evt|0x030f0000) #define gecko_evt_sm_bonding_failed_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_evt|0x040f0000) #define gecko_evt_sm_list_bonding_entry_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_evt|0x050f0000) #define gecko_evt_sm_list_all_bondings_complete_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_evt|0x060f0000) #define gecko_evt_sm_confirm_bonding_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_evt|0x090f0000) #define gecko_evt_homekit_setupcode_display_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_evt|0x00130000) #define gecko_evt_homekit_paired_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_evt|0x01130000) #define gecko_evt_homekit_pair_verified_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_evt|0x02130000) #define gecko_evt_homekit_connection_opened_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_evt|0x03130000) #define gecko_evt_homekit_connection_closed_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_evt|0x04130000) #define gecko_evt_homekit_identify_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_evt|0x05130000) #define gecko_evt_homekit_write_request_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_evt|0x06130000) #define gecko_evt_homekit_read_request_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_evt|0x07130000) #define gecko_evt_homekit_disconnection_required_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_evt|0x08130000) #define gecko_evt_homekit_pairing_removed_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_evt|0x09130000) #define gecko_evt_homekit_setuppayload_display_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_evt|0x0a130000) #define gecko_evt_l2cap_coc_connection_request_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_evt|0x01430000) #define gecko_evt_l2cap_coc_connection_response_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_evt|0x02430000) #define gecko_evt_l2cap_coc_le_flow_control_credit_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_evt|0x03430000) #define gecko_evt_l2cap_coc_channel_disconnected_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_evt|0x04430000) #define gecko_evt_l2cap_coc_data_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_evt|0x05430000) #define gecko_evt_l2cap_command_rejected_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_evt|0x06430000) #define gecko_evt_cte_receiver_iq_report_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_evt|0x00450000) #define gecko_evt_user_message_to_host_id (((uint32)gecko_dev_type_gecko)|gecko_msg_type_evt|0x00ff0000) PACKSTRUCT( struct gecko_msg_dfu_reset_cmd_t { uint8 dfu; }); PACKSTRUCT( struct gecko_msg_dfu_flash_set_address_cmd_t { uint32 address; }); PACKSTRUCT( struct gecko_msg_dfu_flash_set_address_rsp_t { uint16 result; }); PACKSTRUCT( struct gecko_msg_dfu_flash_upload_cmd_t { uint8array data; }); PACKSTRUCT( struct gecko_msg_dfu_flash_upload_rsp_t { uint16 result; }); PACKSTRUCT( struct gecko_msg_dfu_flash_upload_finish_rsp_t { uint16 result; }); PACKSTRUCT( struct gecko_msg_dfu_boot_evt_t { uint32 version; }); PACKSTRUCT( struct gecko_msg_dfu_boot_failure_evt_t { uint16 reason; }); PACKSTRUCT( struct gecko_msg_system_hello_rsp_t { uint16 result; }); PACKSTRUCT( struct gecko_msg_system_reset_cmd_t { uint8 dfu; }); PACKSTRUCT( struct gecko_msg_system_get_bt_address_rsp_t { bd_addr address; }); PACKSTRUCT( struct gecko_msg_system_set_bt_address_cmd_t { bd_addr address; }); PACKSTRUCT( struct gecko_msg_system_set_bt_address_rsp_t { uint16 result; }); PACKSTRUCT( struct gecko_msg_system_set_tx_power_cmd_t { int16 power; }); PACKSTRUCT( struct gecko_msg_system_set_tx_power_rsp_t { int16 set_power; }); PACKSTRUCT( struct gecko_msg_system_get_random_data_cmd_t { uint8 length; }); PACKSTRUCT( struct gecko_msg_system_get_random_data_rsp_t { uint16 result; uint8array data; }); PACKSTRUCT( struct gecko_msg_system_halt_cmd_t { uint8 halt; }); PACKSTRUCT( struct gecko_msg_system_halt_rsp_t { uint16 result; }); PACKSTRUCT( struct gecko_msg_system_set_device_name_cmd_t { uint8 type; uint8array name; }); PACKSTRUCT( struct gecko_msg_system_set_device_name_rsp_t { uint16 result; }); PACKSTRUCT( struct gecko_msg_system_linklayer_configure_cmd_t { uint8 key; uint8array data; }); PACKSTRUCT( struct gecko_msg_system_linklayer_configure_rsp_t { uint16 result; }); PACKSTRUCT( struct gecko_msg_system_get_counters_cmd_t { uint8 reset; }); PACKSTRUCT( struct gecko_msg_system_get_counters_rsp_t { uint16 result; uint16 tx_packets; uint16 rx_packets; uint16 crc_errors; uint16 failures; }); PACKSTRUCT( struct gecko_msg_system_set_identity_address_cmd_t { bd_addr address; uint8 type; }); PACKSTRUCT( struct gecko_msg_system_set_identity_address_rsp_t { uint16 result; }); PACKSTRUCT( struct gecko_msg_system_boot_evt_t { uint16 major; uint16 minor; uint16 patch; uint16 build; uint32 bootloader; uint16 hw; uint32 hash; }); PACKSTRUCT( struct gecko_msg_system_external_signal_evt_t { uint32 extsignals; }); PACKSTRUCT( struct gecko_msg_system_hardware_error_evt_t { uint16 status; }); PACKSTRUCT( struct gecko_msg_system_error_evt_t { uint16 reason; uint8array data; }); PACKSTRUCT( struct gecko_msg_le_gap_open_cmd_t { bd_addr address; uint8 address_type; }); PACKSTRUCT( struct gecko_msg_le_gap_open_rsp_t { uint16 result; uint8 connection; }); PACKSTRUCT( struct gecko_msg_le_gap_set_mode_cmd_t { uint8 discover; uint8 connect; }); PACKSTRUCT( struct gecko_msg_le_gap_set_mode_rsp_t { uint16 result; }); PACKSTRUCT( struct gecko_msg_le_gap_discover_cmd_t { uint8 mode; }); PACKSTRUCT( struct gecko_msg_le_gap_discover_rsp_t { uint16 result; }); PACKSTRUCT( struct gecko_msg_le_gap_end_procedure_rsp_t { uint16 result; }); PACKSTRUCT( struct gecko_msg_le_gap_set_adv_parameters_cmd_t { uint16 interval_min; uint16 interval_max; uint8 channel_map; }); PACKSTRUCT( struct gecko_msg_le_gap_set_adv_parameters_rsp_t { uint16 result; }); PACKSTRUCT( struct gecko_msg_le_gap_set_conn_parameters_cmd_t { uint16 min_interval; uint16 max_interval; uint16 latency; uint16 timeout; }); PACKSTRUCT( struct gecko_msg_le_gap_set_conn_parameters_rsp_t { uint16 result; }); PACKSTRUCT( struct gecko_msg_le_gap_set_scan_parameters_cmd_t { uint16 scan_interval; uint16 scan_window; uint8 active; }); PACKSTRUCT( struct gecko_msg_le_gap_set_scan_parameters_rsp_t { uint16 result; }); PACKSTRUCT( struct gecko_msg_le_gap_set_adv_data_cmd_t { uint8 scan_rsp; uint8array adv_data; }); PACKSTRUCT( struct gecko_msg_le_gap_set_adv_data_rsp_t { uint16 result; }); PACKSTRUCT( struct gecko_msg_le_gap_set_adv_timeout_cmd_t { uint8 maxevents; }); PACKSTRUCT( struct gecko_msg_le_gap_set_adv_timeout_rsp_t { uint16 result; }); PACKSTRUCT( struct gecko_msg_le_gap_bt5_set_mode_cmd_t { uint8 handle; uint8 discover; uint8 connect; uint16 maxevents; uint8 address_type; }); PACKSTRUCT( struct gecko_msg_le_gap_bt5_set_mode_rsp_t { uint16 result; }); PACKSTRUCT( struct gecko_msg_le_gap_bt5_set_adv_parameters_cmd_t { uint8 handle; uint16 interval_min; uint16 interval_max; uint8 channel_map; uint8 report_scan; }); PACKSTRUCT( struct gecko_msg_le_gap_bt5_set_adv_parameters_rsp_t { uint16 result; }); PACKSTRUCT( struct gecko_msg_le_gap_bt5_set_adv_data_cmd_t { uint8 handle; uint8 scan_rsp; uint8array adv_data; }); PACKSTRUCT( struct gecko_msg_le_gap_bt5_set_adv_data_rsp_t { uint16 result; }); PACKSTRUCT( struct gecko_msg_le_gap_set_privacy_mode_cmd_t { uint8 privacy; uint8 interval; }); PACKSTRUCT( struct gecko_msg_le_gap_set_privacy_mode_rsp_t { uint16 result; }); PACKSTRUCT( struct gecko_msg_le_gap_set_advertise_timing_cmd_t { uint8 handle; uint32 interval_min; uint32 interval_max; uint16 duration; uint8 maxevents; }); PACKSTRUCT( struct gecko_msg_le_gap_set_advertise_timing_rsp_t { uint16 result; }); PACKSTRUCT( struct gecko_msg_le_gap_set_advertise_channel_map_cmd_t { uint8 handle; uint8 channel_map; }); PACKSTRUCT( struct gecko_msg_le_gap_set_advertise_channel_map_rsp_t { uint16 result; }); PACKSTRUCT( struct gecko_msg_le_gap_set_advertise_report_scan_request_cmd_t { uint8 handle; uint8 report_scan_req; }); PACKSTRUCT( struct gecko_msg_le_gap_set_advertise_report_scan_request_rsp_t { uint16 result; }); PACKSTRUCT( struct gecko_msg_le_gap_set_advertise_phy_cmd_t { uint8 handle; uint8 primary_phy; uint8 secondary_phy; }); PACKSTRUCT( struct gecko_msg_le_gap_set_advertise_phy_rsp_t { uint16 result; }); PACKSTRUCT( struct gecko_msg_le_gap_set_advertise_configuration_cmd_t { uint8 handle; uint32 configurations; }); PACKSTRUCT( struct gecko_msg_le_gap_set_advertise_configuration_rsp_t { uint16 result; }); PACKSTRUCT( struct gecko_msg_le_gap_clear_advertise_configuration_cmd_t { uint8 handle; uint32 configurations; }); PACKSTRUCT( struct gecko_msg_le_gap_clear_advertise_configuration_rsp_t { uint16 result; }); PACKSTRUCT( struct gecko_msg_le_gap_start_advertising_cmd_t { uint8 handle; uint8 discover; uint8 connect; }); PACKSTRUCT( struct gecko_msg_le_gap_start_advertising_rsp_t { uint16 result; }); PACKSTRUCT( struct gecko_msg_le_gap_stop_advertising_cmd_t { uint8 handle; }); PACKSTRUCT( struct gecko_msg_le_gap_stop_advertising_rsp_t { uint16 result; }); PACKSTRUCT( struct gecko_msg_le_gap_set_discovery_timing_cmd_t { uint8 phys; uint16 scan_interval; uint16 scan_window; }); PACKSTRUCT( struct gecko_msg_le_gap_set_discovery_timing_rsp_t { uint16 result; }); PACKSTRUCT( struct gecko_msg_le_gap_set_discovery_type_cmd_t { uint8 phys; uint8 scan_type; }); PACKSTRUCT( struct gecko_msg_le_gap_set_discovery_type_rsp_t { uint16 result; }); PACKSTRUCT( struct gecko_msg_le_gap_start_discovery_cmd_t { uint8 scanning_phy; uint8 mode; }); PACKSTRUCT( struct gecko_msg_le_gap_start_discovery_rsp_t { uint16 result; }); PACKSTRUCT( struct gecko_msg_le_gap_set_data_channel_classification_cmd_t { uint8array channel_map; }); PACKSTRUCT( struct gecko_msg_le_gap_set_data_channel_classification_rsp_t { uint16 result; }); PACKSTRUCT( struct gecko_msg_le_gap_connect_cmd_t { bd_addr address; uint8 address_type; uint8 initiating_phy; }); PACKSTRUCT( struct gecko_msg_le_gap_connect_rsp_t { uint16 result; uint8 connection; }); PACKSTRUCT( struct gecko_msg_le_gap_set_advertise_tx_power_cmd_t { uint8 handle; int16 power; }); PACKSTRUCT( struct gecko_msg_le_gap_set_advertise_tx_power_rsp_t { uint16 result; int16 set_power; }); PACKSTRUCT( struct gecko_msg_le_gap_set_discovery_extended_scan_response_cmd_t { uint8 enable; }); PACKSTRUCT( struct gecko_msg_le_gap_set_discovery_extended_scan_response_rsp_t { uint16 result; }); PACKSTRUCT( struct gecko_msg_le_gap_start_periodic_advertising_cmd_t { uint8 handle; uint16 interval_min; uint16 interval_max; uint32 flags; }); PACKSTRUCT( struct gecko_msg_le_gap_start_periodic_advertising_rsp_t { uint16 result; }); PACKSTRUCT( struct gecko_msg_le_gap_stop_periodic_advertising_cmd_t { uint8 handle; }); PACKSTRUCT( struct gecko_msg_le_gap_stop_periodic_advertising_rsp_t { uint16 result; }); PACKSTRUCT( struct gecko_msg_le_gap_enable_whitelisting_cmd_t { uint8 enable; }); PACKSTRUCT( struct gecko_msg_le_gap_enable_whitelisting_rsp_t { uint16 result; }); PACKSTRUCT( struct gecko_msg_le_gap_scan_response_evt_t { int8 rssi; uint8 packet_type; bd_addr address; uint8 address_type; uint8 bonding; uint8array data; }); PACKSTRUCT( struct gecko_msg_le_gap_adv_timeout_evt_t { uint8 handle; }); PACKSTRUCT( struct gecko_msg_le_gap_scan_request_evt_t { uint8 handle; bd_addr address; uint8 address_type; uint8 bonding; }); PACKSTRUCT( struct gecko_msg_le_gap_extended_scan_response_evt_t { uint8 packet_type; bd_addr address; uint8 address_type; uint8 bonding; uint8 primary_phy; uint8 secondary_phy; uint8 adv_sid; int8 tx_power; int8 rssi; uint8 channel; uint16 periodic_interval; uint8array data; }); PACKSTRUCT( struct gecko_msg_sync_open_cmd_t { uint8 adv_sid; uint16 skip; uint16 timeout; bd_addr address; uint8 address_type; }); PACKSTRUCT( struct gecko_msg_sync_open_rsp_t { uint16 result; uint8 sync; }); PACKSTRUCT( struct gecko_msg_sync_close_cmd_t { uint8 sync; }); PACKSTRUCT( struct gecko_msg_sync_close_rsp_t { uint16 result; }); PACKSTRUCT( struct gecko_msg_sync_opened_evt_t { uint8 sync; uint8 adv_sid; bd_addr address; uint8 address_type; uint8 adv_phy; uint16 adv_interval; uint16 clock_accuracy; }); PACKSTRUCT( struct gecko_msg_sync_closed_evt_t { uint16 reason; uint8 sync; }); PACKSTRUCT( struct gecko_msg_sync_data_evt_t { uint8 sync; int8 tx_power; int8 rssi; uint8 data_status; uint8array data; }); PACKSTRUCT( struct gecko_msg_le_connection_set_parameters_cmd_t { uint8 connection; uint16 min_interval; uint16 max_interval; uint16 latency; uint16 timeout; }); PACKSTRUCT( struct gecko_msg_le_connection_set_parameters_rsp_t { uint16 result; }); PACKSTRUCT( struct gecko_msg_le_connection_get_rssi_cmd_t { uint8 connection; }); PACKSTRUCT( struct gecko_msg_le_connection_get_rssi_rsp_t { uint16 result; }); PACKSTRUCT( struct gecko_msg_le_connection_disable_slave_latency_cmd_t { uint8 connection; uint8 disable; }); PACKSTRUCT( struct gecko_msg_le_connection_disable_slave_latency_rsp_t { uint16 result; }); PACKSTRUCT( struct gecko_msg_le_connection_set_phy_cmd_t { uint8 connection; uint8 phy; }); PACKSTRUCT( struct gecko_msg_le_connection_set_phy_rsp_t { uint16 result; }); PACKSTRUCT( struct gecko_msg_le_connection_close_cmd_t { uint8 connection; }); PACKSTRUCT( struct gecko_msg_le_connection_close_rsp_t { uint16 result; }); PACKSTRUCT( struct gecko_msg_le_connection_opened_evt_t { bd_addr address; uint8 address_type; uint8 master; uint8 connection; uint8 bonding; uint8 advertiser; }); PACKSTRUCT( struct gecko_msg_le_connection_closed_evt_t { uint16 reason; uint8 connection; }); PACKSTRUCT( struct gecko_msg_le_connection_parameters_evt_t { uint8 connection; uint16 interval; uint16 latency; uint16 timeout; uint8 security_mode; uint16 txsize; }); PACKSTRUCT( struct gecko_msg_le_connection_rssi_evt_t { uint8 connection; uint8 status; int8 rssi; }); PACKSTRUCT( struct gecko_msg_le_connection_phy_status_evt_t { uint8 connection; uint8 phy; }); PACKSTRUCT( struct gecko_msg_gatt_set_max_mtu_cmd_t { uint16 max_mtu; }); PACKSTRUCT( struct gecko_msg_gatt_set_max_mtu_rsp_t { uint16 result; uint16 max_mtu; }); PACKSTRUCT( struct gecko_msg_gatt_discover_primary_services_cmd_t { uint8 connection; }); PACKSTRUCT( struct gecko_msg_gatt_discover_primary_services_rsp_t { uint16 result; }); PACKSTRUCT( struct gecko_msg_gatt_discover_primary_services_by_uuid_cmd_t { uint8 connection; uint8array uuid; }); PACKSTRUCT( struct gecko_msg_gatt_discover_primary_services_by_uuid_rsp_t { uint16 result; }); PACKSTRUCT( struct gecko_msg_gatt_discover_characteristics_cmd_t { uint8 connection; uint32 service; }); PACKSTRUCT( struct gecko_msg_gatt_discover_characteristics_rsp_t { uint16 result; }); PACKSTRUCT( struct gecko_msg_gatt_discover_characteristics_by_uuid_cmd_t { uint8 connection; uint32 service; uint8array uuid; }); PACKSTRUCT( struct gecko_msg_gatt_discover_characteristics_by_uuid_rsp_t { uint16 result; }); PACKSTRUCT( struct gecko_msg_gatt_set_characteristic_notification_cmd_t { uint8 connection; uint16 characteristic; uint8 flags; }); PACKSTRUCT( struct gecko_msg_gatt_set_characteristic_notification_rsp_t { uint16 result; }); PACKSTRUCT( struct gecko_msg_gatt_discover_descriptors_cmd_t { uint8 connection; uint16 characteristic; }); PACKSTRUCT( struct gecko_msg_gatt_discover_descriptors_rsp_t { uint16 result; }); PACKSTRUCT( struct gecko_msg_gatt_read_characteristic_value_cmd_t { uint8 connection; uint16 characteristic; }); PACKSTRUCT( struct gecko_msg_gatt_read_characteristic_value_rsp_t { uint16 result; }); PACKSTRUCT( struct gecko_msg_gatt_read_characteristic_value_by_uuid_cmd_t { uint8 connection; uint32 service; uint8array uuid; }); PACKSTRUCT( struct gecko_msg_gatt_read_characteristic_value_by_uuid_rsp_t { uint16 result; }); PACKSTRUCT( struct gecko_msg_gatt_write_characteristic_value_cmd_t { uint8 connection; uint16 characteristic; uint8array value; }); PACKSTRUCT( struct gecko_msg_gatt_write_characteristic_value_rsp_t { uint16 result; }); PACKSTRUCT( struct gecko_msg_gatt_write_characteristic_value_without_response_cmd_t { uint8 connection; uint16 characteristic; uint8array value; }); PACKSTRUCT( struct gecko_msg_gatt_write_characteristic_value_without_response_rsp_t { uint16 result; uint16 sent_len; }); PACKSTRUCT( struct gecko_msg_gatt_prepare_characteristic_value_write_cmd_t { uint8 connection; uint16 characteristic; uint16 offset; uint8array value; }); PACKSTRUCT( struct gecko_msg_gatt_prepare_characteristic_value_write_rsp_t { uint16 result; uint16 sent_len; }); PACKSTRUCT( struct gecko_msg_gatt_execute_characteristic_value_write_cmd_t { uint8 connection; uint8 flags; }); PACKSTRUCT( struct gecko_msg_gatt_execute_characteristic_value_write_rsp_t { uint16 result; }); PACKSTRUCT( struct gecko_msg_gatt_send_characteristic_confirmation_cmd_t { uint8 connection; }); PACKSTRUCT( struct gecko_msg_gatt_send_characteristic_confirmation_rsp_t { uint16 result; }); PACKSTRUCT( struct gecko_msg_gatt_read_descriptor_value_cmd_t { uint8 connection; uint16 descriptor; }); PACKSTRUCT( struct gecko_msg_gatt_read_descriptor_value_rsp_t { uint16 result; }); PACKSTRUCT( struct gecko_msg_gatt_write_descriptor_value_cmd_t { uint8 connection; uint16 descriptor; uint8array value; }); PACKSTRUCT( struct gecko_msg_gatt_write_descriptor_value_rsp_t { uint16 result; }); PACKSTRUCT( struct gecko_msg_gatt_find_included_services_cmd_t { uint8 connection; uint32 service; }); PACKSTRUCT( struct gecko_msg_gatt_find_included_services_rsp_t { uint16 result; }); PACKSTRUCT( struct gecko_msg_gatt_read_multiple_characteristic_values_cmd_t { uint8 connection; uint8array characteristic_list; }); PACKSTRUCT( struct gecko_msg_gatt_read_multiple_characteristic_values_rsp_t { uint16 result; }); PACKSTRUCT( struct gecko_msg_gatt_read_characteristic_value_from_offset_cmd_t { uint8 connection; uint16 characteristic; uint16 offset; uint16 maxlen; }); PACKSTRUCT( struct gecko_msg_gatt_read_characteristic_value_from_offset_rsp_t { uint16 result; }); PACKSTRUCT( struct gecko_msg_gatt_prepare_characteristic_value_reliable_write_cmd_t { uint8 connection; uint16 characteristic; uint16 offset; uint8array value; }); PACKSTRUCT( struct gecko_msg_gatt_prepare_characteristic_value_reliable_write_rsp_t { uint16 result; uint16 sent_len; }); PACKSTRUCT( struct gecko_msg_gatt_mtu_exchanged_evt_t { uint8 connection; uint16 mtu; }); PACKSTRUCT( struct gecko_msg_gatt_service_evt_t { uint8 connection; uint32 service; uint8array uuid; }); PACKSTRUCT( struct gecko_msg_gatt_characteristic_evt_t { uint8 connection; uint16 characteristic; uint8 properties; uint8array uuid; }); PACKSTRUCT( struct gecko_msg_gatt_descriptor_evt_t { uint8 connection; uint16 descriptor; uint8array uuid; }); PACKSTRUCT( struct gecko_msg_gatt_characteristic_value_evt_t { uint8 connection; uint16 characteristic; uint8 att_opcode; uint16 offset; uint8array value; }); PACKSTRUCT( struct gecko_msg_gatt_descriptor_value_evt_t { uint8 connection; uint16 descriptor; uint16 offset; uint8array value; }); PACKSTRUCT( struct gecko_msg_gatt_procedure_completed_evt_t { uint8 connection; uint16 result; }); PACKSTRUCT( struct gecko_msg_gatt_server_read_attribute_value_cmd_t { uint16 attribute; uint16 offset; }); PACKSTRUCT( struct gecko_msg_gatt_server_read_attribute_value_rsp_t { uint16 result; uint8array value; }); PACKSTRUCT( struct gecko_msg_gatt_server_read_attribute_type_cmd_t { uint16 attribute; }); PACKSTRUCT( struct gecko_msg_gatt_server_read_attribute_type_rsp_t { uint16 result; uint8array type; }); PACKSTRUCT( struct gecko_msg_gatt_server_write_attribute_value_cmd_t { uint16 attribute; uint16 offset; uint8array value; }); PACKSTRUCT( struct gecko_msg_gatt_server_write_attribute_value_rsp_t { uint16 result; }); PACKSTRUCT( struct gecko_msg_gatt_server_send_user_read_response_cmd_t { uint8 connection; uint16 characteristic; uint8 att_errorcode; uint8array value; }); PACKSTRUCT( struct gecko_msg_gatt_server_send_user_read_response_rsp_t { uint16 result; uint16 sent_len; }); PACKSTRUCT( struct gecko_msg_gatt_server_send_user_write_response_cmd_t { uint8 connection; uint16 characteristic; uint8 att_errorcode; }); PACKSTRUCT( struct gecko_msg_gatt_server_send_user_write_response_rsp_t { uint16 result; }); PACKSTRUCT( struct gecko_msg_gatt_server_send_characteristic_notification_cmd_t { uint8 connection; uint16 characteristic; uint8array value; }); PACKSTRUCT( struct gecko_msg_gatt_server_send_characteristic_notification_rsp_t { uint16 result; uint16 sent_len; }); PACKSTRUCT( struct gecko_msg_gatt_server_find_attribute_cmd_t { uint16 start; uint8array type; }); PACKSTRUCT( struct gecko_msg_gatt_server_find_attribute_rsp_t { uint16 result; uint16 attribute; }); PACKSTRUCT( struct gecko_msg_gatt_server_set_capabilities_cmd_t { uint32 caps; uint32 reserved; }); PACKSTRUCT( struct gecko_msg_gatt_server_set_capabilities_rsp_t { uint16 result; }); PACKSTRUCT( struct gecko_msg_gatt_server_attribute_value_evt_t { uint8 connection; uint16 attribute; uint8 att_opcode; uint16 offset; uint8array value; }); PACKSTRUCT( struct gecko_msg_gatt_server_user_read_request_evt_t { uint8 connection; uint16 characteristic; uint8 att_opcode; uint16 offset; }); PACKSTRUCT( struct gecko_msg_gatt_server_user_write_request_evt_t { uint8 connection; uint16 characteristic; uint8 att_opcode; uint16 offset; uint8array value; }); PACKSTRUCT( struct gecko_msg_gatt_server_characteristic_status_evt_t { uint8 connection; uint16 characteristic; uint8 status_flags; uint16 client_config_flags; }); PACKSTRUCT( struct gecko_msg_gatt_server_execute_write_completed_evt_t { uint8 connection; uint16 result; }); PACKSTRUCT( struct gecko_msg_hardware_set_soft_timer_cmd_t { uint32 time; uint8 handle; uint8 single_shot; }); PACKSTRUCT( struct gecko_msg_hardware_set_soft_timer_rsp_t { uint16 result; }); PACKSTRUCT( struct gecko_msg_hardware_get_time_rsp_t { uint32 seconds; uint16 ticks; }); PACKSTRUCT( struct gecko_msg_hardware_set_lazy_soft_timer_cmd_t { uint32 time; uint32 slack; uint8 handle; uint8 single_shot; }); PACKSTRUCT( struct gecko_msg_hardware_set_lazy_soft_timer_rsp_t { uint16 result; }); PACKSTRUCT( struct gecko_msg_hardware_soft_timer_evt_t { uint8 handle; }); PACKSTRUCT( struct gecko_msg_flash_ps_erase_all_rsp_t { uint16 result; }); PACKSTRUCT( struct gecko_msg_flash_ps_save_cmd_t { uint16 key; uint8array value; }); PACKSTRUCT( struct gecko_msg_flash_ps_save_rsp_t { uint16 result; }); PACKSTRUCT( struct gecko_msg_flash_ps_load_cmd_t { uint16 key; }); PACKSTRUCT( struct gecko_msg_flash_ps_load_rsp_t { uint16 result; uint8array value; }); PACKSTRUCT( struct gecko_msg_flash_ps_erase_cmd_t { uint16 key; }); PACKSTRUCT( struct gecko_msg_flash_ps_erase_rsp_t { uint16 result; }); PACKSTRUCT( struct gecko_msg_test_dtm_tx_cmd_t { uint8 packet_type; uint8 length; uint8 channel; uint8 phy; }); PACKSTRUCT( struct gecko_msg_test_dtm_tx_rsp_t { uint16 result; }); PACKSTRUCT( struct gecko_msg_test_dtm_rx_cmd_t { uint8 channel; uint8 phy; }); PACKSTRUCT( struct gecko_msg_test_dtm_rx_rsp_t { uint16 result; }); PACKSTRUCT( struct gecko_msg_test_dtm_end_rsp_t { uint16 result; }); PACKSTRUCT( struct gecko_msg_test_dtm_completed_evt_t { uint16 result; uint16 number_of_packets; }); PACKSTRUCT( struct gecko_msg_sm_set_bondable_mode_cmd_t { uint8 bondable; }); PACKSTRUCT( struct gecko_msg_sm_set_bondable_mode_rsp_t { uint16 result; }); PACKSTRUCT( struct gecko_msg_sm_configure_cmd_t { uint8 flags; uint8 io_capabilities; }); PACKSTRUCT( struct gecko_msg_sm_configure_rsp_t { uint16 result; }); PACKSTRUCT( struct gecko_msg_sm_store_bonding_configuration_cmd_t { uint8 max_bonding_count; uint8 policy_flags; }); PACKSTRUCT( struct gecko_msg_sm_store_bonding_configuration_rsp_t { uint16 result; }); PACKSTRUCT( struct gecko_msg_sm_increase_security_cmd_t { uint8 connection; }); PACKSTRUCT( struct gecko_msg_sm_increase_security_rsp_t { uint16 result; }); PACKSTRUCT( struct gecko_msg_sm_delete_bonding_cmd_t { uint8 bonding; }); PACKSTRUCT( struct gecko_msg_sm_delete_bonding_rsp_t { uint16 result; }); PACKSTRUCT( struct gecko_msg_sm_delete_bondings_rsp_t { uint16 result; }); PACKSTRUCT( struct gecko_msg_sm_enter_passkey_cmd_t { uint8 connection; int32 passkey; }); PACKSTRUCT( struct gecko_msg_sm_enter_passkey_rsp_t { uint16 result; }); PACKSTRUCT( struct gecko_msg_sm_passkey_confirm_cmd_t { uint8 connection; uint8 confirm; }); PACKSTRUCT( struct gecko_msg_sm_passkey_confirm_rsp_t { uint16 result; }); PACKSTRUCT( struct gecko_msg_sm_set_oob_data_cmd_t { uint8array oob_data; }); PACKSTRUCT( struct gecko_msg_sm_set_oob_data_rsp_t { uint16 result; }); PACKSTRUCT( struct gecko_msg_sm_list_all_bondings_rsp_t { uint16 result; }); PACKSTRUCT( struct gecko_msg_sm_bonding_confirm_cmd_t { uint8 connection; uint8 confirm; }); PACKSTRUCT( struct gecko_msg_sm_bonding_confirm_rsp_t { uint16 result; }); PACKSTRUCT( struct gecko_msg_sm_set_debug_mode_rsp_t { uint16 result; }); PACKSTRUCT( struct gecko_msg_sm_set_passkey_cmd_t { int32 passkey; }); PACKSTRUCT( struct gecko_msg_sm_set_passkey_rsp_t { uint16 result; }); PACKSTRUCT( struct gecko_msg_sm_use_sc_oob_cmd_t { uint8 enable; }); PACKSTRUCT( struct gecko_msg_sm_use_sc_oob_rsp_t { uint16 result; uint8array oob_data; }); PACKSTRUCT( struct gecko_msg_sm_set_sc_remote_oob_data_cmd_t { uint8array oob_data; }); PACKSTRUCT( struct gecko_msg_sm_set_sc_remote_oob_data_rsp_t { uint16 result; }); PACKSTRUCT( struct gecko_msg_sm_add_to_whitelist_cmd_t { bd_addr address; uint8 address_type; }); PACKSTRUCT( struct gecko_msg_sm_add_to_whitelist_rsp_t { uint16 result; }); PACKSTRUCT( struct gecko_msg_sm_passkey_display_evt_t { uint8 connection; uint32 passkey; }); PACKSTRUCT( struct gecko_msg_sm_passkey_request_evt_t { uint8 connection; }); PACKSTRUCT( struct gecko_msg_sm_confirm_passkey_evt_t { uint8 connection; uint32 passkey; }); PACKSTRUCT( struct gecko_msg_sm_bonded_evt_t { uint8 connection; uint8 bonding; }); PACKSTRUCT( struct gecko_msg_sm_bonding_failed_evt_t { uint8 connection; uint16 reason; }); PACKSTRUCT( struct gecko_msg_sm_list_bonding_entry_evt_t { uint8 bonding; bd_addr address; uint8 address_type; }); PACKSTRUCT( struct gecko_msg_sm_confirm_bonding_evt_t { uint8 connection; int8 bonding_handle; }); PACKSTRUCT( struct gecko_msg_homekit_configure_cmd_t { uint8 i2c_address; uint8 support_display; uint8 hap_attribute_features; uint16 category; uint8 configuration_number; uint16 fast_advert_interval; uint16 fast_advert_timeout; uint32 flag; uint16 broadcast_advert_timeout; uint8array model_name; }); PACKSTRUCT( struct gecko_msg_homekit_configure_rsp_t { uint16 result; }); PACKSTRUCT( struct gecko_msg_homekit_advertise_cmd_t { uint8 enable; uint16 interval_min; uint16 interval_max; uint8 channel_map; }); PACKSTRUCT( struct gecko_msg_homekit_advertise_rsp_t { uint16 result; }); PACKSTRUCT( struct gecko_msg_homekit_delete_pairings_rsp_t { uint16 result; }); PACKSTRUCT( struct gecko_msg_homekit_check_authcp_rsp_t { uint16 result; }); PACKSTRUCT( struct gecko_msg_homekit_get_pairing_id_cmd_t { uint8 connection; }); PACKSTRUCT( struct gecko_msg_homekit_get_pairing_id_rsp_t { uint16 result; uint8array pairing_id; }); PACKSTRUCT( struct gecko_msg_homekit_send_write_response_cmd_t { uint8 connection; uint16 characteristic; uint8 status_code; }); PACKSTRUCT( struct gecko_msg_homekit_send_write_response_rsp_t { uint16 result; }); PACKSTRUCT( struct gecko_msg_homekit_send_read_response_cmd_t { uint8 connection; uint16 characteristic; uint8 status_code; uint16 attribute_size; uint8array value; }); PACKSTRUCT( struct gecko_msg_homekit_send_read_response_rsp_t { uint16 result; }); PACKSTRUCT( struct gecko_msg_homekit_gsn_action_cmd_t { uint8 action; }); PACKSTRUCT( struct gecko_msg_homekit_gsn_action_rsp_t { uint16 result; }); PACKSTRUCT( struct gecko_msg_homekit_event_notification_cmd_t { uint8 connection; uint16 characteristic; uint8 change_originator; uint8array value; }); PACKSTRUCT( struct gecko_msg_homekit_event_notification_rsp_t { uint16 result; }); PACKSTRUCT( struct gecko_msg_homekit_broadcast_action_cmd_t { uint8 action; uint8array params; }); PACKSTRUCT( struct gecko_msg_homekit_broadcast_action_rsp_t { uint16 result; }); PACKSTRUCT( struct gecko_msg_homekit_setupcode_display_evt_t { uint8 connection; uint8array setupcode; }); PACKSTRUCT( struct gecko_msg_homekit_paired_evt_t { uint8 connection; uint16 reason; }); PACKSTRUCT( struct gecko_msg_homekit_pair_verified_evt_t { uint8 connection; uint16 reason; }); PACKSTRUCT( struct gecko_msg_homekit_connection_opened_evt_t { uint8 connection; }); PACKSTRUCT( struct gecko_msg_homekit_connection_closed_evt_t { uint8 connection; uint16 reason; }); PACKSTRUCT( struct gecko_msg_homekit_identify_evt_t { uint8 connection; }); PACKSTRUCT( struct gecko_msg_homekit_write_request_evt_t { uint8 connection; uint16 characteristic; uint16 chr_value_size; uint16 authorization_size; uint16 value_offset; uint8array value; }); PACKSTRUCT( struct gecko_msg_homekit_read_request_evt_t { uint8 connection; uint16 characteristic; uint16 offset; }); PACKSTRUCT( struct gecko_msg_homekit_disconnection_required_evt_t { uint8 connection; uint16 reason; }); PACKSTRUCT( struct gecko_msg_homekit_pairing_removed_evt_t { uint8 connection; uint16 remaining_pairings; uint8array pairing_id; }); PACKSTRUCT( struct gecko_msg_homekit_setuppayload_display_evt_t { uint8 connection; uint8array setuppayload; }); PACKSTRUCT( struct gecko_msg_coex_set_options_cmd_t { uint32 mask; uint32 options; }); PACKSTRUCT( struct gecko_msg_coex_set_options_rsp_t { uint16 result; }); PACKSTRUCT( struct gecko_msg_coex_get_counters_cmd_t { uint8 reset; }); PACKSTRUCT( struct gecko_msg_coex_get_counters_rsp_t { uint16 result; uint8array counters; }); PACKSTRUCT( struct gecko_msg_l2cap_coc_send_connection_request_cmd_t { uint8 connection; uint16 le_psm; uint16 mtu; uint16 mps; uint16 initial_credit; }); PACKSTRUCT( struct gecko_msg_l2cap_coc_send_connection_request_rsp_t { uint16 result; }); PACKSTRUCT( struct gecko_msg_l2cap_coc_send_connection_response_cmd_t { uint8 connection; uint16 cid; uint16 mtu; uint16 mps; uint16 initial_credit; uint16 result; }); PACKSTRUCT( struct gecko_msg_l2cap_coc_send_connection_response_rsp_t { uint16 result; }); PACKSTRUCT( struct gecko_msg_l2cap_coc_send_le_flow_control_credit_cmd_t { uint8 connection; uint16 cid; uint16 credits; }); PACKSTRUCT( struct gecko_msg_l2cap_coc_send_le_flow_control_credit_rsp_t { uint16 result; }); PACKSTRUCT( struct gecko_msg_l2cap_coc_send_disconnection_request_cmd_t { uint8 connection; uint16 cid; }); PACKSTRUCT( struct gecko_msg_l2cap_coc_send_disconnection_request_rsp_t { uint16 result; }); PACKSTRUCT( struct gecko_msg_l2cap_coc_send_data_cmd_t { uint8 connection; uint16 cid; uint8array data; }); PACKSTRUCT( struct gecko_msg_l2cap_coc_send_data_rsp_t { uint16 result; }); PACKSTRUCT( struct gecko_msg_l2cap_coc_connection_request_evt_t { uint8 connection; uint16 le_psm; uint16 source_cid; uint16 mtu; uint16 mps; uint16 initial_credit; uint8 flags; uint8 encryption_key_size; }); PACKSTRUCT( struct gecko_msg_l2cap_coc_connection_response_evt_t { uint8 connection; uint16 destination_cid; uint16 mtu; uint16 mps; uint16 initial_credit; uint16 result; }); PACKSTRUCT( struct gecko_msg_l2cap_coc_le_flow_control_credit_evt_t { uint8 connection; uint16 cid; uint16 credits; }); PACKSTRUCT( struct gecko_msg_l2cap_coc_channel_disconnected_evt_t { uint8 connection; uint16 cid; uint16 reason; }); PACKSTRUCT( struct gecko_msg_l2cap_coc_data_evt_t { uint8 connection; uint16 cid; uint8array data; }); PACKSTRUCT( struct gecko_msg_l2cap_command_rejected_evt_t { uint8 connection; uint8 code; uint16 reason; }); PACKSTRUCT( struct gecko_msg_cte_transmitter_enable_cte_response_cmd_t { uint8 connection; uint8 cte_types; uint8array switching_pattern; }); PACKSTRUCT( struct gecko_msg_cte_transmitter_enable_cte_response_rsp_t { uint16 result; }); PACKSTRUCT( struct gecko_msg_cte_transmitter_disable_cte_response_cmd_t { uint8 connection; }); PACKSTRUCT( struct gecko_msg_cte_transmitter_disable_cte_response_rsp_t { uint16 result; }); PACKSTRUCT( struct gecko_msg_cte_transmitter_start_connectionless_cte_cmd_t { uint8 adv; uint8 cte_length; uint8 cte_type; uint8 cte_count; uint8array switching_pattern; }); PACKSTRUCT( struct gecko_msg_cte_transmitter_start_connectionless_cte_rsp_t { uint16 result; }); PACKSTRUCT( struct gecko_msg_cte_transmitter_stop_connectionless_cte_cmd_t { uint8 adv; }); PACKSTRUCT( struct gecko_msg_cte_transmitter_stop_connectionless_cte_rsp_t { uint16 result; }); PACKSTRUCT( struct gecko_msg_cte_transmitter_set_dtm_parameters_cmd_t { uint8 cte_length; uint8 cte_type; uint8array switching_pattern; }); PACKSTRUCT( struct gecko_msg_cte_transmitter_set_dtm_parameters_rsp_t { uint16 result; }); PACKSTRUCT( struct gecko_msg_cte_transmitter_clear_dtm_parameters_rsp_t { uint16 result; }); PACKSTRUCT( struct gecko_msg_cte_receiver_configure_cmd_t { uint8 flags; }); PACKSTRUCT( struct gecko_msg_cte_receiver_configure_rsp_t { uint16 result; }); PACKSTRUCT( struct gecko_msg_cte_receiver_start_iq_sampling_cmd_t { uint8 connection; uint16 interval; uint8 cte_length; uint8 cte_type; uint8 slot_durations; uint8array switching_pattern; }); PACKSTRUCT( struct gecko_msg_cte_receiver_start_iq_sampling_rsp_t { uint16 result; }); PACKSTRUCT( struct gecko_msg_cte_receiver_stop_iq_sampling_cmd_t { uint8 connection; }); PACKSTRUCT( struct gecko_msg_cte_receiver_stop_iq_sampling_rsp_t { uint16 result; }); PACKSTRUCT( struct gecko_msg_cte_receiver_start_connectionless_iq_sampling_cmd_t { uint8 sync; uint8 slot_durations; uint8 cte_count; uint8array switching_pattern; }); PACKSTRUCT( struct gecko_msg_cte_receiver_start_connectionless_iq_sampling_rsp_t { uint16 result; }); PACKSTRUCT( struct gecko_msg_cte_receiver_stop_connectionless_iq_sampling_cmd_t { uint8 sync; }); PACKSTRUCT( struct gecko_msg_cte_receiver_stop_connectionless_iq_sampling_rsp_t { uint16 result; }); PACKSTRUCT( struct gecko_msg_cte_receiver_set_dtm_parameters_cmd_t { uint8 cte_length; uint8 cte_type; uint8 slot_durations; uint8array switching_pattern; }); PACKSTRUCT( struct gecko_msg_cte_receiver_set_dtm_parameters_rsp_t { uint16 result; }); PACKSTRUCT( struct gecko_msg_cte_receiver_clear_dtm_parameters_rsp_t { uint16 result; }); PACKSTRUCT( struct gecko_msg_cte_receiver_iq_report_evt_t { uint16 status; uint8 packet_type; uint8 handle; int8 rssi; uint8 channel; uint8array samples; }); PACKSTRUCT( struct gecko_msg_user_message_to_target_cmd_t { uint8array data; }); PACKSTRUCT( struct gecko_msg_user_message_to_target_rsp_t { uint16 result; uint8array data; }); PACKSTRUCT( struct gecko_msg_user_message_to_host_evt_t { uint8array data; }); /** * The command packet type. This does not include the actual size of the byte array for user data in the end of the message. * The full size of a command packet is 4 + max bgapi payload size. */ PACKSTRUCT( struct gecko_cmd_packet { uint32 header; union{ uint8 handle; struct gecko_msg_dfu_reset_cmd_t cmd_dfu_reset; struct gecko_msg_dfu_flash_set_address_cmd_t cmd_dfu_flash_set_address; struct gecko_msg_dfu_flash_set_address_rsp_t rsp_dfu_flash_set_address; struct gecko_msg_dfu_flash_upload_cmd_t cmd_dfu_flash_upload; struct gecko_msg_dfu_flash_upload_rsp_t rsp_dfu_flash_upload; struct gecko_msg_dfu_flash_upload_finish_rsp_t rsp_dfu_flash_upload_finish; struct gecko_msg_dfu_boot_evt_t evt_dfu_boot; struct gecko_msg_dfu_boot_failure_evt_t evt_dfu_boot_failure; struct gecko_msg_system_hello_rsp_t rsp_system_hello; struct gecko_msg_system_reset_cmd_t cmd_system_reset; struct gecko_msg_system_get_bt_address_rsp_t rsp_system_get_bt_address; struct gecko_msg_system_set_bt_address_cmd_t cmd_system_set_bt_address; struct gecko_msg_system_set_bt_address_rsp_t rsp_system_set_bt_address; struct gecko_msg_system_set_tx_power_cmd_t cmd_system_set_tx_power; struct gecko_msg_system_set_tx_power_rsp_t rsp_system_set_tx_power; struct gecko_msg_system_get_random_data_cmd_t cmd_system_get_random_data; struct gecko_msg_system_get_random_data_rsp_t rsp_system_get_random_data; struct gecko_msg_system_halt_cmd_t cmd_system_halt; struct gecko_msg_system_halt_rsp_t rsp_system_halt; struct gecko_msg_system_set_device_name_cmd_t cmd_system_set_device_name; struct gecko_msg_system_set_device_name_rsp_t rsp_system_set_device_name; struct gecko_msg_system_linklayer_configure_cmd_t cmd_system_linklayer_configure; struct gecko_msg_system_linklayer_configure_rsp_t rsp_system_linklayer_configure; struct gecko_msg_system_get_counters_cmd_t cmd_system_get_counters; struct gecko_msg_system_get_counters_rsp_t rsp_system_get_counters; struct gecko_msg_system_set_identity_address_cmd_t cmd_system_set_identity_address; struct gecko_msg_system_set_identity_address_rsp_t rsp_system_set_identity_address; struct gecko_msg_system_boot_evt_t evt_system_boot; struct gecko_msg_system_external_signal_evt_t evt_system_external_signal; struct gecko_msg_system_hardware_error_evt_t evt_system_hardware_error; struct gecko_msg_system_error_evt_t evt_system_error; struct gecko_msg_le_gap_open_cmd_t cmd_le_gap_open; struct gecko_msg_le_gap_open_rsp_t rsp_le_gap_open; struct gecko_msg_le_gap_set_mode_cmd_t cmd_le_gap_set_mode; struct gecko_msg_le_gap_set_mode_rsp_t rsp_le_gap_set_mode; struct gecko_msg_le_gap_discover_cmd_t cmd_le_gap_discover; struct gecko_msg_le_gap_discover_rsp_t rsp_le_gap_discover; struct gecko_msg_le_gap_end_procedure_rsp_t rsp_le_gap_end_procedure; struct gecko_msg_le_gap_set_adv_parameters_cmd_t cmd_le_gap_set_adv_parameters; struct gecko_msg_le_gap_set_adv_parameters_rsp_t rsp_le_gap_set_adv_parameters; struct gecko_msg_le_gap_set_conn_parameters_cmd_t cmd_le_gap_set_conn_parameters; struct gecko_msg_le_gap_set_conn_parameters_rsp_t rsp_le_gap_set_conn_parameters; struct gecko_msg_le_gap_set_scan_parameters_cmd_t cmd_le_gap_set_scan_parameters; struct gecko_msg_le_gap_set_scan_parameters_rsp_t rsp_le_gap_set_scan_parameters; struct gecko_msg_le_gap_set_adv_data_cmd_t cmd_le_gap_set_adv_data; struct gecko_msg_le_gap_set_adv_data_rsp_t rsp_le_gap_set_adv_data; struct gecko_msg_le_gap_set_adv_timeout_cmd_t cmd_le_gap_set_adv_timeout; struct gecko_msg_le_gap_set_adv_timeout_rsp_t rsp_le_gap_set_adv_timeout; struct gecko_msg_le_gap_bt5_set_mode_cmd_t cmd_le_gap_bt5_set_mode; struct gecko_msg_le_gap_bt5_set_mode_rsp_t rsp_le_gap_bt5_set_mode; struct gecko_msg_le_gap_bt5_set_adv_parameters_cmd_t cmd_le_gap_bt5_set_adv_parameters; struct gecko_msg_le_gap_bt5_set_adv_parameters_rsp_t rsp_le_gap_bt5_set_adv_parameters; struct gecko_msg_le_gap_bt5_set_adv_data_cmd_t cmd_le_gap_bt5_set_adv_data; struct gecko_msg_le_gap_bt5_set_adv_data_rsp_t rsp_le_gap_bt5_set_adv_data; struct gecko_msg_le_gap_set_privacy_mode_cmd_t cmd_le_gap_set_privacy_mode; struct gecko_msg_le_gap_set_privacy_mode_rsp_t rsp_le_gap_set_privacy_mode; struct gecko_msg_le_gap_set_advertise_timing_cmd_t cmd_le_gap_set_advertise_timing; struct gecko_msg_le_gap_set_advertise_timing_rsp_t rsp_le_gap_set_advertise_timing; struct gecko_msg_le_gap_set_advertise_channel_map_cmd_t cmd_le_gap_set_advertise_channel_map; struct gecko_msg_le_gap_set_advertise_channel_map_rsp_t rsp_le_gap_set_advertise_channel_map; struct gecko_msg_le_gap_set_advertise_report_scan_request_cmd_t cmd_le_gap_set_advertise_report_scan_request; struct gecko_msg_le_gap_set_advertise_report_scan_request_rsp_t rsp_le_gap_set_advertise_report_scan_request; struct gecko_msg_le_gap_set_advertise_phy_cmd_t cmd_le_gap_set_advertise_phy; struct gecko_msg_le_gap_set_advertise_phy_rsp_t rsp_le_gap_set_advertise_phy; struct gecko_msg_le_gap_set_advertise_configuration_cmd_t cmd_le_gap_set_advertise_configuration; struct gecko_msg_le_gap_set_advertise_configuration_rsp_t rsp_le_gap_set_advertise_configuration; struct gecko_msg_le_gap_clear_advertise_configuration_cmd_t cmd_le_gap_clear_advertise_configuration; struct gecko_msg_le_gap_clear_advertise_configuration_rsp_t rsp_le_gap_clear_advertise_configuration; struct gecko_msg_le_gap_start_advertising_cmd_t cmd_le_gap_start_advertising; struct gecko_msg_le_gap_start_advertising_rsp_t rsp_le_gap_start_advertising; struct gecko_msg_le_gap_stop_advertising_cmd_t cmd_le_gap_stop_advertising; struct gecko_msg_le_gap_stop_advertising_rsp_t rsp_le_gap_stop_advertising; struct gecko_msg_le_gap_set_discovery_timing_cmd_t cmd_le_gap_set_discovery_timing; struct gecko_msg_le_gap_set_discovery_timing_rsp_t rsp_le_gap_set_discovery_timing; struct gecko_msg_le_gap_set_discovery_type_cmd_t cmd_le_gap_set_discovery_type; struct gecko_msg_le_gap_set_discovery_type_rsp_t rsp_le_gap_set_discovery_type; struct gecko_msg_le_gap_start_discovery_cmd_t cmd_le_gap_start_discovery; struct gecko_msg_le_gap_start_discovery_rsp_t rsp_le_gap_start_discovery; struct gecko_msg_le_gap_set_data_channel_classification_cmd_t cmd_le_gap_set_data_channel_classification; struct gecko_msg_le_gap_set_data_channel_classification_rsp_t rsp_le_gap_set_data_channel_classification; struct gecko_msg_le_gap_connect_cmd_t cmd_le_gap_connect; struct gecko_msg_le_gap_connect_rsp_t rsp_le_gap_connect; struct gecko_msg_le_gap_set_advertise_tx_power_cmd_t cmd_le_gap_set_advertise_tx_power; struct gecko_msg_le_gap_set_advertise_tx_power_rsp_t rsp_le_gap_set_advertise_tx_power; struct gecko_msg_le_gap_set_discovery_extended_scan_response_cmd_t cmd_le_gap_set_discovery_extended_scan_response; struct gecko_msg_le_gap_set_discovery_extended_scan_response_rsp_t rsp_le_gap_set_discovery_extended_scan_response; struct gecko_msg_le_gap_start_periodic_advertising_cmd_t cmd_le_gap_start_periodic_advertising; struct gecko_msg_le_gap_start_periodic_advertising_rsp_t rsp_le_gap_start_periodic_advertising; struct gecko_msg_le_gap_stop_periodic_advertising_cmd_t cmd_le_gap_stop_periodic_advertising; struct gecko_msg_le_gap_stop_periodic_advertising_rsp_t rsp_le_gap_stop_periodic_advertising; struct gecko_msg_le_gap_enable_whitelisting_cmd_t cmd_le_gap_enable_whitelisting; struct gecko_msg_le_gap_enable_whitelisting_rsp_t rsp_le_gap_enable_whitelisting; struct gecko_msg_le_gap_scan_response_evt_t evt_le_gap_scan_response; struct gecko_msg_le_gap_adv_timeout_evt_t evt_le_gap_adv_timeout; struct gecko_msg_le_gap_scan_request_evt_t evt_le_gap_scan_request; struct gecko_msg_le_gap_extended_scan_response_evt_t evt_le_gap_extended_scan_response; struct gecko_msg_sync_open_cmd_t cmd_sync_open; struct gecko_msg_sync_open_rsp_t rsp_sync_open; struct gecko_msg_sync_close_cmd_t cmd_sync_close; struct gecko_msg_sync_close_rsp_t rsp_sync_close; struct gecko_msg_sync_opened_evt_t evt_sync_opened; struct gecko_msg_sync_closed_evt_t evt_sync_closed; struct gecko_msg_sync_data_evt_t evt_sync_data; struct gecko_msg_le_connection_set_parameters_cmd_t cmd_le_connection_set_parameters; struct gecko_msg_le_connection_set_parameters_rsp_t rsp_le_connection_set_parameters; struct gecko_msg_le_connection_get_rssi_cmd_t cmd_le_connection_get_rssi; struct gecko_msg_le_connection_get_rssi_rsp_t rsp_le_connection_get_rssi; struct gecko_msg_le_connection_disable_slave_latency_cmd_t cmd_le_connection_disable_slave_latency; struct gecko_msg_le_connection_disable_slave_latency_rsp_t rsp_le_connection_disable_slave_latency; struct gecko_msg_le_connection_set_phy_cmd_t cmd_le_connection_set_phy; struct gecko_msg_le_connection_set_phy_rsp_t rsp_le_connection_set_phy; struct gecko_msg_le_connection_close_cmd_t cmd_le_connection_close; struct gecko_msg_le_connection_close_rsp_t rsp_le_connection_close; struct gecko_msg_le_connection_opened_evt_t evt_le_connection_opened; struct gecko_msg_le_connection_closed_evt_t evt_le_connection_closed; struct gecko_msg_le_connection_parameters_evt_t evt_le_connection_parameters; struct gecko_msg_le_connection_rssi_evt_t evt_le_connection_rssi; struct gecko_msg_le_connection_phy_status_evt_t evt_le_connection_phy_status; struct gecko_msg_gatt_set_max_mtu_cmd_t cmd_gatt_set_max_mtu; struct gecko_msg_gatt_set_max_mtu_rsp_t rsp_gatt_set_max_mtu; struct gecko_msg_gatt_discover_primary_services_cmd_t cmd_gatt_discover_primary_services; struct gecko_msg_gatt_discover_primary_services_rsp_t rsp_gatt_discover_primary_services; struct gecko_msg_gatt_discover_primary_services_by_uuid_cmd_t cmd_gatt_discover_primary_services_by_uuid; struct gecko_msg_gatt_discover_primary_services_by_uuid_rsp_t rsp_gatt_discover_primary_services_by_uuid; struct gecko_msg_gatt_discover_characteristics_cmd_t cmd_gatt_discover_characteristics; struct gecko_msg_gatt_discover_characteristics_rsp_t rsp_gatt_discover_characteristics; struct gecko_msg_gatt_discover_characteristics_by_uuid_cmd_t cmd_gatt_discover_characteristics_by_uuid; struct gecko_msg_gatt_discover_characteristics_by_uuid_rsp_t rsp_gatt_discover_characteristics_by_uuid; struct gecko_msg_gatt_set_characteristic_notification_cmd_t cmd_gatt_set_characteristic_notification; struct gecko_msg_gatt_set_characteristic_notification_rsp_t rsp_gatt_set_characteristic_notification; struct gecko_msg_gatt_discover_descriptors_cmd_t cmd_gatt_discover_descriptors; struct gecko_msg_gatt_discover_descriptors_rsp_t rsp_gatt_discover_descriptors; struct gecko_msg_gatt_read_characteristic_value_cmd_t cmd_gatt_read_characteristic_value; struct gecko_msg_gatt_read_characteristic_value_rsp_t rsp_gatt_read_characteristic_value; struct gecko_msg_gatt_read_characteristic_value_by_uuid_cmd_t cmd_gatt_read_characteristic_value_by_uuid; struct gecko_msg_gatt_read_characteristic_value_by_uuid_rsp_t rsp_gatt_read_characteristic_value_by_uuid; struct gecko_msg_gatt_write_characteristic_value_cmd_t cmd_gatt_write_characteristic_value; struct gecko_msg_gatt_write_characteristic_value_rsp_t rsp_gatt_write_characteristic_value; struct gecko_msg_gatt_write_characteristic_value_without_response_cmd_t cmd_gatt_write_characteristic_value_without_response; struct gecko_msg_gatt_write_characteristic_value_without_response_rsp_t rsp_gatt_write_characteristic_value_without_response; struct gecko_msg_gatt_prepare_characteristic_value_write_cmd_t cmd_gatt_prepare_characteristic_value_write; struct gecko_msg_gatt_prepare_characteristic_value_write_rsp_t rsp_gatt_prepare_characteristic_value_write; struct gecko_msg_gatt_execute_characteristic_value_write_cmd_t cmd_gatt_execute_characteristic_value_write; struct gecko_msg_gatt_execute_characteristic_value_write_rsp_t rsp_gatt_execute_characteristic_value_write; struct gecko_msg_gatt_send_characteristic_confirmation_cmd_t cmd_gatt_send_characteristic_confirmation; struct gecko_msg_gatt_send_characteristic_confirmation_rsp_t rsp_gatt_send_characteristic_confirmation; struct gecko_msg_gatt_read_descriptor_value_cmd_t cmd_gatt_read_descriptor_value; struct gecko_msg_gatt_read_descriptor_value_rsp_t rsp_gatt_read_descriptor_value; struct gecko_msg_gatt_write_descriptor_value_cmd_t cmd_gatt_write_descriptor_value; struct gecko_msg_gatt_write_descriptor_value_rsp_t rsp_gatt_write_descriptor_value; struct gecko_msg_gatt_find_included_services_cmd_t cmd_gatt_find_included_services; struct gecko_msg_gatt_find_included_services_rsp_t rsp_gatt_find_included_services; struct gecko_msg_gatt_read_multiple_characteristic_values_cmd_t cmd_gatt_read_multiple_characteristic_values; struct gecko_msg_gatt_read_multiple_characteristic_values_rsp_t rsp_gatt_read_multiple_characteristic_values; struct gecko_msg_gatt_read_characteristic_value_from_offset_cmd_t cmd_gatt_read_characteristic_value_from_offset; struct gecko_msg_gatt_read_characteristic_value_from_offset_rsp_t rsp_gatt_read_characteristic_value_from_offset; struct gecko_msg_gatt_prepare_characteristic_value_reliable_write_cmd_t cmd_gatt_prepare_characteristic_value_reliable_write; struct gecko_msg_gatt_prepare_characteristic_value_reliable_write_rsp_t rsp_gatt_prepare_characteristic_value_reliable_write; struct gecko_msg_gatt_mtu_exchanged_evt_t evt_gatt_mtu_exchanged; struct gecko_msg_gatt_service_evt_t evt_gatt_service; struct gecko_msg_gatt_characteristic_evt_t evt_gatt_characteristic; struct gecko_msg_gatt_descriptor_evt_t evt_gatt_descriptor; struct gecko_msg_gatt_characteristic_value_evt_t evt_gatt_characteristic_value; struct gecko_msg_gatt_descriptor_value_evt_t evt_gatt_descriptor_value; struct gecko_msg_gatt_procedure_completed_evt_t evt_gatt_procedure_completed; struct gecko_msg_gatt_server_read_attribute_value_cmd_t cmd_gatt_server_read_attribute_value; struct gecko_msg_gatt_server_read_attribute_value_rsp_t rsp_gatt_server_read_attribute_value; struct gecko_msg_gatt_server_read_attribute_type_cmd_t cmd_gatt_server_read_attribute_type; struct gecko_msg_gatt_server_read_attribute_type_rsp_t rsp_gatt_server_read_attribute_type; struct gecko_msg_gatt_server_write_attribute_value_cmd_t cmd_gatt_server_write_attribute_value; struct gecko_msg_gatt_server_write_attribute_value_rsp_t rsp_gatt_server_write_attribute_value; struct gecko_msg_gatt_server_send_user_read_response_cmd_t cmd_gatt_server_send_user_read_response; struct gecko_msg_gatt_server_send_user_read_response_rsp_t rsp_gatt_server_send_user_read_response; struct gecko_msg_gatt_server_send_user_write_response_cmd_t cmd_gatt_server_send_user_write_response; struct gecko_msg_gatt_server_send_user_write_response_rsp_t rsp_gatt_server_send_user_write_response; struct gecko_msg_gatt_server_send_characteristic_notification_cmd_t cmd_gatt_server_send_characteristic_notification; struct gecko_msg_gatt_server_send_characteristic_notification_rsp_t rsp_gatt_server_send_characteristic_notification; struct gecko_msg_gatt_server_find_attribute_cmd_t cmd_gatt_server_find_attribute; struct gecko_msg_gatt_server_find_attribute_rsp_t rsp_gatt_server_find_attribute; struct gecko_msg_gatt_server_set_capabilities_cmd_t cmd_gatt_server_set_capabilities; struct gecko_msg_gatt_server_set_capabilities_rsp_t rsp_gatt_server_set_capabilities; struct gecko_msg_gatt_server_attribute_value_evt_t evt_gatt_server_attribute_value; struct gecko_msg_gatt_server_user_read_request_evt_t evt_gatt_server_user_read_request; struct gecko_msg_gatt_server_user_write_request_evt_t evt_gatt_server_user_write_request; struct gecko_msg_gatt_server_characteristic_status_evt_t evt_gatt_server_characteristic_status; struct gecko_msg_gatt_server_execute_write_completed_evt_t evt_gatt_server_execute_write_completed; struct gecko_msg_hardware_set_soft_timer_cmd_t cmd_hardware_set_soft_timer; struct gecko_msg_hardware_set_soft_timer_rsp_t rsp_hardware_set_soft_timer; struct gecko_msg_hardware_get_time_rsp_t rsp_hardware_get_time; struct gecko_msg_hardware_set_lazy_soft_timer_cmd_t cmd_hardware_set_lazy_soft_timer; struct gecko_msg_hardware_set_lazy_soft_timer_rsp_t rsp_hardware_set_lazy_soft_timer; struct gecko_msg_hardware_soft_timer_evt_t evt_hardware_soft_timer; struct gecko_msg_flash_ps_erase_all_rsp_t rsp_flash_ps_erase_all; struct gecko_msg_flash_ps_save_cmd_t cmd_flash_ps_save; struct gecko_msg_flash_ps_save_rsp_t rsp_flash_ps_save; struct gecko_msg_flash_ps_load_cmd_t cmd_flash_ps_load; struct gecko_msg_flash_ps_load_rsp_t rsp_flash_ps_load; struct gecko_msg_flash_ps_erase_cmd_t cmd_flash_ps_erase; struct gecko_msg_flash_ps_erase_rsp_t rsp_flash_ps_erase; struct gecko_msg_test_dtm_tx_cmd_t cmd_test_dtm_tx; struct gecko_msg_test_dtm_tx_rsp_t rsp_test_dtm_tx; struct gecko_msg_test_dtm_rx_cmd_t cmd_test_dtm_rx; struct gecko_msg_test_dtm_rx_rsp_t rsp_test_dtm_rx; struct gecko_msg_test_dtm_end_rsp_t rsp_test_dtm_end; struct gecko_msg_test_dtm_completed_evt_t evt_test_dtm_completed; struct gecko_msg_sm_set_bondable_mode_cmd_t cmd_sm_set_bondable_mode; struct gecko_msg_sm_set_bondable_mode_rsp_t rsp_sm_set_bondable_mode; struct gecko_msg_sm_configure_cmd_t cmd_sm_configure; struct gecko_msg_sm_configure_rsp_t rsp_sm_configure; struct gecko_msg_sm_store_bonding_configuration_cmd_t cmd_sm_store_bonding_configuration; struct gecko_msg_sm_store_bonding_configuration_rsp_t rsp_sm_store_bonding_configuration; struct gecko_msg_sm_increase_security_cmd_t cmd_sm_increase_security; struct gecko_msg_sm_increase_security_rsp_t rsp_sm_increase_security; struct gecko_msg_sm_delete_bonding_cmd_t cmd_sm_delete_bonding; struct gecko_msg_sm_delete_bonding_rsp_t rsp_sm_delete_bonding; struct gecko_msg_sm_delete_bondings_rsp_t rsp_sm_delete_bondings; struct gecko_msg_sm_enter_passkey_cmd_t cmd_sm_enter_passkey; struct gecko_msg_sm_enter_passkey_rsp_t rsp_sm_enter_passkey; struct gecko_msg_sm_passkey_confirm_cmd_t cmd_sm_passkey_confirm; struct gecko_msg_sm_passkey_confirm_rsp_t rsp_sm_passkey_confirm; struct gecko_msg_sm_set_oob_data_cmd_t cmd_sm_set_oob_data; struct gecko_msg_sm_set_oob_data_rsp_t rsp_sm_set_oob_data; struct gecko_msg_sm_list_all_bondings_rsp_t rsp_sm_list_all_bondings; struct gecko_msg_sm_bonding_confirm_cmd_t cmd_sm_bonding_confirm; struct gecko_msg_sm_bonding_confirm_rsp_t rsp_sm_bonding_confirm; struct gecko_msg_sm_set_debug_mode_rsp_t rsp_sm_set_debug_mode; struct gecko_msg_sm_set_passkey_cmd_t cmd_sm_set_passkey; struct gecko_msg_sm_set_passkey_rsp_t rsp_sm_set_passkey; struct gecko_msg_sm_use_sc_oob_cmd_t cmd_sm_use_sc_oob; struct gecko_msg_sm_use_sc_oob_rsp_t rsp_sm_use_sc_oob; struct gecko_msg_sm_set_sc_remote_oob_data_cmd_t cmd_sm_set_sc_remote_oob_data; struct gecko_msg_sm_set_sc_remote_oob_data_rsp_t rsp_sm_set_sc_remote_oob_data; struct gecko_msg_sm_add_to_whitelist_cmd_t cmd_sm_add_to_whitelist; struct gecko_msg_sm_add_to_whitelist_rsp_t rsp_sm_add_to_whitelist; struct gecko_msg_sm_passkey_display_evt_t evt_sm_passkey_display; struct gecko_msg_sm_passkey_request_evt_t evt_sm_passkey_request; struct gecko_msg_sm_confirm_passkey_evt_t evt_sm_confirm_passkey; struct gecko_msg_sm_bonded_evt_t evt_sm_bonded; struct gecko_msg_sm_bonding_failed_evt_t evt_sm_bonding_failed; struct gecko_msg_sm_list_bonding_entry_evt_t evt_sm_list_bonding_entry; struct gecko_msg_sm_confirm_bonding_evt_t evt_sm_confirm_bonding; struct gecko_msg_homekit_configure_cmd_t cmd_homekit_configure; struct gecko_msg_homekit_configure_rsp_t rsp_homekit_configure; struct gecko_msg_homekit_advertise_cmd_t cmd_homekit_advertise; struct gecko_msg_homekit_advertise_rsp_t rsp_homekit_advertise; struct gecko_msg_homekit_delete_pairings_rsp_t rsp_homekit_delete_pairings; struct gecko_msg_homekit_check_authcp_rsp_t rsp_homekit_check_authcp; struct gecko_msg_homekit_get_pairing_id_cmd_t cmd_homekit_get_pairing_id; struct gecko_msg_homekit_get_pairing_id_rsp_t rsp_homekit_get_pairing_id; struct gecko_msg_homekit_send_write_response_cmd_t cmd_homekit_send_write_response; struct gecko_msg_homekit_send_write_response_rsp_t rsp_homekit_send_write_response; struct gecko_msg_homekit_send_read_response_cmd_t cmd_homekit_send_read_response; struct gecko_msg_homekit_send_read_response_rsp_t rsp_homekit_send_read_response; struct gecko_msg_homekit_gsn_action_cmd_t cmd_homekit_gsn_action; struct gecko_msg_homekit_gsn_action_rsp_t rsp_homekit_gsn_action; struct gecko_msg_homekit_event_notification_cmd_t cmd_homekit_event_notification; struct gecko_msg_homekit_event_notification_rsp_t rsp_homekit_event_notification; struct gecko_msg_homekit_broadcast_action_cmd_t cmd_homekit_broadcast_action; struct gecko_msg_homekit_broadcast_action_rsp_t rsp_homekit_broadcast_action; struct gecko_msg_homekit_setupcode_display_evt_t evt_homekit_setupcode_display; struct gecko_msg_homekit_paired_evt_t evt_homekit_paired; struct gecko_msg_homekit_pair_verified_evt_t evt_homekit_pair_verified; struct gecko_msg_homekit_connection_opened_evt_t evt_homekit_connection_opened; struct gecko_msg_homekit_connection_closed_evt_t evt_homekit_connection_closed; struct gecko_msg_homekit_identify_evt_t evt_homekit_identify; struct gecko_msg_homekit_write_request_evt_t evt_homekit_write_request; struct gecko_msg_homekit_read_request_evt_t evt_homekit_read_request; struct gecko_msg_homekit_disconnection_required_evt_t evt_homekit_disconnection_required; struct gecko_msg_homekit_pairing_removed_evt_t evt_homekit_pairing_removed; struct gecko_msg_homekit_setuppayload_display_evt_t evt_homekit_setuppayload_display; struct gecko_msg_coex_set_options_cmd_t cmd_coex_set_options; struct gecko_msg_coex_set_options_rsp_t rsp_coex_set_options; struct gecko_msg_coex_get_counters_cmd_t cmd_coex_get_counters; struct gecko_msg_coex_get_counters_rsp_t rsp_coex_get_counters; struct gecko_msg_l2cap_coc_send_connection_request_cmd_t cmd_l2cap_coc_send_connection_request; struct gecko_msg_l2cap_coc_send_connection_request_rsp_t rsp_l2cap_coc_send_connection_request; struct gecko_msg_l2cap_coc_send_connection_response_cmd_t cmd_l2cap_coc_send_connection_response; struct gecko_msg_l2cap_coc_send_connection_response_rsp_t rsp_l2cap_coc_send_connection_response; struct gecko_msg_l2cap_coc_send_le_flow_control_credit_cmd_t cmd_l2cap_coc_send_le_flow_control_credit; struct gecko_msg_l2cap_coc_send_le_flow_control_credit_rsp_t rsp_l2cap_coc_send_le_flow_control_credit; struct gecko_msg_l2cap_coc_send_disconnection_request_cmd_t cmd_l2cap_coc_send_disconnection_request; struct gecko_msg_l2cap_coc_send_disconnection_request_rsp_t rsp_l2cap_coc_send_disconnection_request; struct gecko_msg_l2cap_coc_send_data_cmd_t cmd_l2cap_coc_send_data; struct gecko_msg_l2cap_coc_send_data_rsp_t rsp_l2cap_coc_send_data; struct gecko_msg_l2cap_coc_connection_request_evt_t evt_l2cap_coc_connection_request; struct gecko_msg_l2cap_coc_connection_response_evt_t evt_l2cap_coc_connection_response; struct gecko_msg_l2cap_coc_le_flow_control_credit_evt_t evt_l2cap_coc_le_flow_control_credit; struct gecko_msg_l2cap_coc_channel_disconnected_evt_t evt_l2cap_coc_channel_disconnected; struct gecko_msg_l2cap_coc_data_evt_t evt_l2cap_coc_data; struct gecko_msg_l2cap_command_rejected_evt_t evt_l2cap_command_rejected; struct gecko_msg_cte_transmitter_enable_cte_response_cmd_t cmd_cte_transmitter_enable_cte_response; struct gecko_msg_cte_transmitter_enable_cte_response_rsp_t rsp_cte_transmitter_enable_cte_response; struct gecko_msg_cte_transmitter_disable_cte_response_cmd_t cmd_cte_transmitter_disable_cte_response; struct gecko_msg_cte_transmitter_disable_cte_response_rsp_t rsp_cte_transmitter_disable_cte_response; struct gecko_msg_cte_transmitter_start_connectionless_cte_cmd_t cmd_cte_transmitter_start_connectionless_cte; struct gecko_msg_cte_transmitter_start_connectionless_cte_rsp_t rsp_cte_transmitter_start_connectionless_cte; struct gecko_msg_cte_transmitter_stop_connectionless_cte_cmd_t cmd_cte_transmitter_stop_connectionless_cte; struct gecko_msg_cte_transmitter_stop_connectionless_cte_rsp_t rsp_cte_transmitter_stop_connectionless_cte; struct gecko_msg_cte_transmitter_set_dtm_parameters_cmd_t cmd_cte_transmitter_set_dtm_parameters; struct gecko_msg_cte_transmitter_set_dtm_parameters_rsp_t rsp_cte_transmitter_set_dtm_parameters; struct gecko_msg_cte_transmitter_clear_dtm_parameters_rsp_t rsp_cte_transmitter_clear_dtm_parameters; struct gecko_msg_cte_receiver_configure_cmd_t cmd_cte_receiver_configure; struct gecko_msg_cte_receiver_configure_rsp_t rsp_cte_receiver_configure; struct gecko_msg_cte_receiver_start_iq_sampling_cmd_t cmd_cte_receiver_start_iq_sampling; struct gecko_msg_cte_receiver_start_iq_sampling_rsp_t rsp_cte_receiver_start_iq_sampling; struct gecko_msg_cte_receiver_stop_iq_sampling_cmd_t cmd_cte_receiver_stop_iq_sampling; struct gecko_msg_cte_receiver_stop_iq_sampling_rsp_t rsp_cte_receiver_stop_iq_sampling; struct gecko_msg_cte_receiver_start_connectionless_iq_sampling_cmd_t cmd_cte_receiver_start_connectionless_iq_sampling; struct gecko_msg_cte_receiver_start_connectionless_iq_sampling_rsp_t rsp_cte_receiver_start_connectionless_iq_sampling; struct gecko_msg_cte_receiver_stop_connectionless_iq_sampling_cmd_t cmd_cte_receiver_stop_connectionless_iq_sampling; struct gecko_msg_cte_receiver_stop_connectionless_iq_sampling_rsp_t rsp_cte_receiver_stop_connectionless_iq_sampling; struct gecko_msg_cte_receiver_set_dtm_parameters_cmd_t cmd_cte_receiver_set_dtm_parameters; struct gecko_msg_cte_receiver_set_dtm_parameters_rsp_t rsp_cte_receiver_set_dtm_parameters; struct gecko_msg_cte_receiver_clear_dtm_parameters_rsp_t rsp_cte_receiver_clear_dtm_parameters; struct gecko_msg_cte_receiver_iq_report_evt_t evt_cte_receiver_iq_report; struct gecko_msg_user_message_to_target_cmd_t cmd_user_message_to_target; struct gecko_msg_user_message_to_target_rsp_t rsp_user_message_to_target; struct gecko_msg_user_message_to_host_evt_t evt_user_message_to_host; uint8 *payload; }data; }); /** * Initialize BGAPI class dfu. This initializer function must be called if any command * from this class is going to be used. */ void gecko_bgapi_class_dfu_init(); /** * Initialize BGAPI class system. This initializer function must be called if any command * from this class is going to be used. */ void gecko_bgapi_class_system_init(); /** * Initialize BGAPI class le_gap. This initializer function must be called if any command * from this class is going to be used. */ void gecko_bgapi_class_le_gap_init(); /** * Initialize BGAPI class sync. This initializer function must be called if any command * from this class is going to be used. */ void gecko_bgapi_class_sync_init(); /** * Initialize BGAPI class le_connection. This initializer function must be called if any command * from this class is going to be used. */ void gecko_bgapi_class_le_connection_init(); /** * Initialize BGAPI class gatt. This initializer function must be called if any command * from this class is going to be used. */ void gecko_bgapi_class_gatt_init(); /** * Initialize BGAPI class gatt_server. This initializer function must be called if any command * from this class is going to be used. */ void gecko_bgapi_class_gatt_server_init(); /** * Initialize BGAPI class hardware. This initializer function must be called if any command * from this class is going to be used. */ void gecko_bgapi_class_hardware_init(); /** * Initialize BGAPI class flash. This initializer function must be called if any command * from this class is going to be used. */ void gecko_bgapi_class_flash_init(); /** * Initialize BGAPI class test. This initializer function must be called if any command * from this class is going to be used. */ void gecko_bgapi_class_test_init(); /** * Initialize BGAPI class sm. This initializer function must be called if any command * from this class is going to be used. */ void gecko_bgapi_class_sm_init(); /** * Initialize BGAPI class coex. This initializer function must be called if any command * from this class is going to be used. */ void gecko_bgapi_class_coex_init(); /** * Initialize BGAPI class l2cap. This initializer function must be called if any command * from this class is going to be used. */ void gecko_bgapi_class_l2cap_init(); /** * Initialize BGAPI class cte_transmitter. This initializer function must be called if any command * from this class is going to be used. */ void gecko_bgapi_class_cte_transmitter_init(); /** * Initialize BGAPI class cte_receiver. This initializer function must be called if any command * from this class is going to be used. */ void gecko_bgapi_class_cte_receiver_init(); #include <em_gpio.h> /** * Coexistence interface */ struct gecko_coexSignal { int interrupt; int pin; GPIO_Port_TypeDef port; bool polarity; bool enable; }; struct gecko_coexInit { uint32_t options; uint16_t requestWindow; uint16_t requestWindowCalibration; struct gecko_coexSignal requestSignal; struct gecko_coexSignal prioritySignal; struct gecko_coexSignal grantSignal; struct gecko_coexSignal rhoSignal; }; #ifndef HAL_COEX_REQ_WINDOW // Request window defines how many micro seconds earlier request signal // is set before actual radio operation. Default value is defined here. #define HAL_COEX_REQ_WINDOW 500 #endif #ifndef HAL_COEX_REQ_BACKOFF // Maximum backoff time in micro seconds after request signal is deasserted. // This value needs to be smaller than request window. #define HAL_COEX_REQ_BACKOFF 100 #endif // Request window calibration value takes into account the hardware and // software delayes which may delay the request signal #ifndef GECKO_COEX_REQ_WINDOW_CALIBRATION #if (HAL_COEX_REQ_SHARED) #define GECKO_COEX_REQ_WINDOW_CALIBRATION 55 #else #define GECKO_COEX_REQ_WINDOW_CALIBRATION 52 #endif #endif #define GECKO_COEXINIT_DEFAULT { \ 0, /* configuration options */ \ HAL_COEX_REQ_WINDOW, /* request window */ \ GECKO_COEX_REQ_WINDOW_CALIBRATION, \ { /* request signal */ \ BSP_COEX_REQ_PIN, \ BSP_COEX_REQ_PIN, \ BSP_COEX_REQ_PORT, \ BSP_COEX_REQ_ASSERT_LEVEL, \ }, \ { /* priority signal */ \ BSP_COEX_PRI_PIN, \ BSP_COEX_PRI_PIN, \ BSP_COEX_PRI_PORT, \ BSP_COEX_PRI_ASSERT_LEVEL, \ }, \ { /* grant signal */ \ BSP_COEX_GNT_PIN, \ BSP_COEX_GNT_PIN, \ BSP_COEX_GNT_PORT, \ BSP_COEX_GNT_ASSERT_LEVEL, \ }, \ { /* rho signal */ \ BSP_COEX_RHO_PIN, \ BSP_COEX_RHO_PIN, \ BSP_COEX_RHO_PORT, \ BSP_COEX_RHO_ASSERT_LEVEL, \ }, \ } #define GECKO_COEX_OPTION_REQUEST_BACKOFF_SHIFT 0 #define GECKO_COEX_OPTION_REQUEST_BACKOFF_MASK 0xff #define GECKO_COEX_OPTION_REQUEST_BACKOFF_DEFAULT \ HAL_COEX_REQ_BACKOFF #define GECKO_COEX_OPTION_ENABLE_SHIFT 8 #define GECKO_COEX_OPTION_ENABLE (1 << GECKO_COEX_OPTION_ENABLE_SHIFT) #define GECKO_COEX_OPTION_SHARED_REQ_SHIFT 9 #define GECKO_COEX_OPTION_SHARED_REQ (1 << GECKO_COEX_OPTION_SHARED_REQ_SHIFT) #define GECKO_COEX_OPTION_TX_ABORT_SHIFT 10 #define GECKO_COEX_OPTION_TX_ABORT (1 << GECKO_COEX_OPTION_TX_ABORT_SHIFT) #define GECKO_COEX_OPTION_HIGH_PRIORITY_SHIFT 11 #define GECKO_COEX_OPTION_HIGH_PRIORITY (1 << GECKO_COEX_OPTION_HIGH_PRIORITY_SHIFT) #define GECKO_COEX_OPTION_SHARED_PRI_SHIFT 12 #define GECKO_COEX_OPTION_SHARED_PRI (1 << GECKO_COEX_OPTION_SHARED_PRI_SHIFT) #define GECKO_COEX_OPTION_MASK 0x0000f00 #define GECKO_COEX_OPTION_REQUEST_WINDOW_SHIFT 16 #define GECKO_COEX_OPTION_REQUEST_WINDOW_MASK 0xffff0000 // deprecated option, please use GECKO_COEX_OPTION_SHARED_REQ instead #define GECKO_COEX_OPTION_SHARED_SHIFT GECKO_COEX_OPTION_SHARED_REQ #define GECKO_COEX_OPTION_SHARED (1 << GECKO_COEX_OPTION_SHARED_REQ_SHIFT) void gecko_initCoex(const struct gecko_coexInit *coexInit); void gecko_setCoexOptions(uint32_t mask, uint32_t options); void gecko_getCoexCounters(const void **ptr, uint8_t *size); static inline void gecko_initCoexHAL() { #ifdef HAL_CONFIG #if (HAL_COEX_ENABLE) // Initialise coexistence interface struct gecko_coexInit coexInit = { .options = GECKO_COEX_OPTION_ENABLE | GECKO_COEX_OPTION_REQUEST_BACKOFF_DEFAULT, .requestWindow = HAL_COEX_REQ_WINDOW, .requestWindowCalibration = GECKO_COEX_REQ_WINDOW_CALIBRATION, }; // COEX options #if (HAL_COEX_TX_HIPRI) || (HAL_COEX_RX_HIPRI) coexInit.options |= GECKO_COEX_OPTION_HIGH_PRIORITY; #endif #if (HAL_COEX_TX_ABORT) coexInit.options |= GECKO_COEX_OPTION_TX_ABORT; #endif #if (HAL_COEX_REQ_SHARED) coexInit.options |= GECKO_COEX_OPTION_SHARED_REQ; #endif #if (HAL_COEX_PRI_SHARED) coexInit.options |= GECKO_COEX_OPTION_SHARED_PRI; #endif #ifdef BSP_COEX_REQ_PORT // Request signal coexInit.requestSignal = (struct gecko_coexSignal) { .interrupt = BSP_COEX_REQ_PIN, .pin = BSP_COEX_REQ_PIN, .port = BSP_COEX_REQ_PORT, .polarity = BSP_COEX_REQ_ASSERT_LEVEL, .enable = true, }; #endif #ifdef BSP_COEX_PRI_PORT // Priority signal coexInit.prioritySignal = (struct gecko_coexSignal) { .interrupt = BSP_COEX_PRI_PIN, .pin = BSP_COEX_PRI_PIN, .port = BSP_COEX_PRI_PORT, .polarity = BSP_COEX_PRI_ASSERT_LEVEL, .enable = true, }; #endif #ifdef BSP_COEX_GNT_PORT // Grant signal coexInit.grantSignal = (struct gecko_coexSignal) { .interrupt = BSP_COEX_GNT_PIN, .pin = BSP_COEX_GNT_PIN, .port = BSP_COEX_GNT_PORT, .polarity = BSP_COEX_GNT_ASSERT_LEVEL, .enable = true, }; #endif #ifdef BSP_COEX_RHO_PORT // Rho signal coexInit.rhoSignal = (struct gecko_coexSignal) { .interrupt = BSP_COEX_RHO_PIN, .pin = BSP_COEX_RHO_PIN, .port = BSP_COEX_RHO_PORT, .polarity = BSP_COEX_RHO_ASSERT_LEVEL, .enable = true, }; #endif gecko_initCoex(&coexInit); #ifdef NCP_GECKO_H ncp_gecko_bgapi_class_coex_init(); #endif #ifdef MICCA_GECKO_H gecko_bgapi_class_coex_init(); #endif #endif // HAL_COEX_ENABLE #endif // HAL_CONFIG } void ll_initAFH(); /** * Initialize and enable Adaptive Frequency Hopping (AFH). By default this feature is disabled in stack. */ static inline void gecko_init_afh() { ll_initAFH(); } void ll_initPeriodicAdv(); void sli_bt_init_periodic_advertising(); /** * Initialize and enable Periodic Advertising. By default this feature is disabled in stack. */ static inline void gecko_init_periodic_advertising() { ll_initPeriodicAdv(); sli_bt_init_periodic_advertising(); } void sli_bt_init_whitelisting(); /** * Initialize whitelisting feature. After initialization the application can enable whitelisting * using command cmd_le_gap_enable_whitelisting. By default this feature is not initialized in stack. */ static inline void gecko_init_whitelisting() { sli_bt_init_whitelisting(); } /** * Initialize stack and all BGAPI classes. * This is a convenience method for getting the stack and all BGAPI classes usable by the application. * If application wants to initialize only a subset of BGAPI classes, this function should not be called. Instead, * first call gecko_stack_init() to initialize stack, and then call individual BGAPI class initializers. * * @param config The pointer to configuration parameters, cannot be NULL. * @return bg_err_success if the initialization was successful; Other error code * indicates a failure on initializing persistent storage. */ static inline errorcode_t gecko_init(const gecko_configuration_t *config) { errorcode_t err = gecko_stack_init(config); if (err != bg_err_success) { return err; } gecko_bgapi_class_dfu_init(); gecko_bgapi_class_system_init(); gecko_bgapi_class_le_gap_init(); gecko_bgapi_class_le_connection_init(); gecko_bgapi_class_gatt_init(); gecko_bgapi_class_gatt_server_init(); gecko_bgapi_class_hardware_init(); gecko_bgapi_class_flash_init(); gecko_bgapi_class_test_init(); gecko_bgapi_class_sm_init(); // Initialize coexistence interface. Parameters are taken from HAL config. gecko_initCoexHAL(); return bg_err_success; } /** Forward declaration of internal command handling functions. Do not use those in application. **/ void sli_bt_cmd_dfu_reset(const void*); void sli_bt_cmd_dfu_flash_set_address(const void*); void sli_bt_cmd_dfu_flash_upload(const void*); void sli_bt_cmd_dfu_flash_upload_finish(const void*); void sli_bt_cmd_system_hello(const void*); void sli_bt_cmd_system_reset(const void*); void sli_bt_cmd_system_get_bt_address(const void*); void sli_bt_cmd_system_set_bt_address(const void*); void sli_bt_cmd_system_set_tx_power(const void*); void sli_bt_cmd_system_get_random_data(const void*); void sli_bt_cmd_system_halt(const void*); void sli_bt_cmd_system_set_device_name(const void*); void sli_bt_cmd_system_linklayer_configure(const void*); void sli_bt_cmd_system_get_counters(const void*); void sli_bt_cmd_system_set_identity_address(const void*); void sli_bt_cmd_le_gap_open(const void*); void sli_bt_cmd_le_gap_set_mode(const void*); void sli_bt_cmd_le_gap_discover(const void*); void sli_bt_cmd_le_gap_end_procedure(const void*); void sli_bt_cmd_le_gap_set_adv_parameters(const void*); void sli_bt_cmd_le_gap_set_conn_parameters(const void*); void sli_bt_cmd_le_gap_set_scan_parameters(const void*); void sli_bt_cmd_le_gap_set_adv_data(const void*); void sli_bt_cmd_le_gap_set_adv_timeout(const void*); void sli_bt_cmd_le_gap_bt5_set_mode(const void*); void sli_bt_cmd_le_gap_bt5_set_adv_parameters(const void*); void sli_bt_cmd_le_gap_bt5_set_adv_data(const void*); void sli_bt_cmd_le_gap_set_privacy_mode(const void*); void sli_bt_cmd_le_gap_set_advertise_timing(const void*); void sli_bt_cmd_le_gap_set_advertise_channel_map(const void*); void sli_bt_cmd_le_gap_set_advertise_report_scan_request(const void*); void sli_bt_cmd_le_gap_set_advertise_phy(const void*); void sli_bt_cmd_le_gap_set_advertise_configuration(const void*); void sli_bt_cmd_le_gap_clear_advertise_configuration(const void*); void sli_bt_cmd_le_gap_start_advertising(const void*); void sli_bt_cmd_le_gap_stop_advertising(const void*); void sli_bt_cmd_le_gap_set_discovery_timing(const void*); void sli_bt_cmd_le_gap_set_discovery_type(const void*); void sli_bt_cmd_le_gap_start_discovery(const void*); void sli_bt_cmd_le_gap_set_data_channel_classification(const void*); void sli_bt_cmd_le_gap_connect(const void*); void sli_bt_cmd_le_gap_set_advertise_tx_power(const void*); void sli_bt_cmd_le_gap_set_discovery_extended_scan_response(const void*); void sli_bt_cmd_le_gap_start_periodic_advertising(const void*); void sli_bt_cmd_le_gap_stop_periodic_advertising(const void*); void sli_bt_cmd_le_gap_enable_whitelisting(const void*); void sli_bt_cmd_sync_open(const void*); void sli_bt_cmd_sync_close(const void*); void sli_bt_cmd_le_connection_set_parameters(const void*); void sli_bt_cmd_le_connection_get_rssi(const void*); void sli_bt_cmd_le_connection_disable_slave_latency(const void*); void sli_bt_cmd_le_connection_set_phy(const void*); void sli_bt_cmd_le_connection_close(const void*); void sli_bt_cmd_gatt_set_max_mtu(const void*); void sli_bt_cmd_gatt_discover_primary_services(const void*); void sli_bt_cmd_gatt_discover_primary_services_by_uuid(const void*); void sli_bt_cmd_gatt_discover_characteristics(const void*); void sli_bt_cmd_gatt_discover_characteristics_by_uuid(const void*); void sli_bt_cmd_gatt_set_characteristic_notification(const void*); void sli_bt_cmd_gatt_discover_descriptors(const void*); void sli_bt_cmd_gatt_read_characteristic_value(const void*); void sli_bt_cmd_gatt_read_characteristic_value_by_uuid(const void*); void sli_bt_cmd_gatt_write_characteristic_value(const void*); void sli_bt_cmd_gatt_write_characteristic_value_without_response(const void*); void sli_bt_cmd_gatt_prepare_characteristic_value_write(const void*); void sli_bt_cmd_gatt_execute_characteristic_value_write(const void*); void sli_bt_cmd_gatt_send_characteristic_confirmation(const void*); void sli_bt_cmd_gatt_read_descriptor_value(const void*); void sli_bt_cmd_gatt_write_descriptor_value(const void*); void sli_bt_cmd_gatt_find_included_services(const void*); void sli_bt_cmd_gatt_read_multiple_characteristic_values(const void*); void sli_bt_cmd_gatt_read_characteristic_value_from_offset(const void*); void sli_bt_cmd_gatt_prepare_characteristic_value_reliable_write(const void*); void sli_bt_cmd_gatt_server_read_attribute_value(const void*); void sli_bt_cmd_gatt_server_read_attribute_type(const void*); void sli_bt_cmd_gatt_server_write_attribute_value(const void*); void sli_bt_cmd_gatt_server_send_user_read_response(const void*); void sli_bt_cmd_gatt_server_send_user_write_response(const void*); void sli_bt_cmd_gatt_server_send_characteristic_notification(const void*); void sli_bt_cmd_gatt_server_find_attribute(const void*); void sli_bt_cmd_gatt_server_set_capabilities(const void*); void sli_bt_cmd_hardware_set_soft_timer(const void*); void sli_bt_cmd_hardware_get_time(const void*); void sli_bt_cmd_hardware_set_lazy_soft_timer(const void*); void sli_bt_cmd_flash_ps_erase_all(const void*); void sli_bt_cmd_flash_ps_save(const void*); void sli_bt_cmd_flash_ps_load(const void*); void sli_bt_cmd_flash_ps_erase(const void*); void sli_bt_cmd_test_dtm_tx(const void*); void sli_bt_cmd_test_dtm_rx(const void*); void sli_bt_cmd_test_dtm_end(const void*); void sli_bt_cmd_sm_set_bondable_mode(const void*); void sli_bt_cmd_sm_configure(const void*); void sli_bt_cmd_sm_store_bonding_configuration(const void*); void sli_bt_cmd_sm_increase_security(const void*); void sli_bt_cmd_sm_delete_bonding(const void*); void sli_bt_cmd_sm_delete_bondings(const void*); void sli_bt_cmd_sm_enter_passkey(const void*); void sli_bt_cmd_sm_passkey_confirm(const void*); void sli_bt_cmd_sm_set_oob_data(const void*); void sli_bt_cmd_sm_list_all_bondings(const void*); void sli_bt_cmd_sm_bonding_confirm(const void*); void sli_bt_cmd_sm_set_debug_mode(const void*); void sli_bt_cmd_sm_set_passkey(const void*); void sli_bt_cmd_sm_use_sc_oob(const void*); void sli_bt_cmd_sm_set_sc_remote_oob_data(const void*); void sli_bt_cmd_sm_add_to_whitelist(const void*); void sli_bt_cmd_homekit_configure(const void*); void sli_bt_cmd_homekit_advertise(const void*); void sli_bt_cmd_homekit_delete_pairings(const void*); void sli_bt_cmd_homekit_check_authcp(const void*); void sli_bt_cmd_homekit_get_pairing_id(const void*); void sli_bt_cmd_homekit_send_write_response(const void*); void sli_bt_cmd_homekit_send_read_response(const void*); void sli_bt_cmd_homekit_gsn_action(const void*); void sli_bt_cmd_homekit_event_notification(const void*); void sli_bt_cmd_homekit_broadcast_action(const void*); void sli_bt_cmd_coex_set_options(const void*); void sli_bt_cmd_coex_get_counters(const void*); void sli_bt_cmd_l2cap_coc_send_connection_request(const void*); void sli_bt_cmd_l2cap_coc_send_connection_response(const void*); void sli_bt_cmd_l2cap_coc_send_le_flow_control_credit(const void*); void sli_bt_cmd_l2cap_coc_send_disconnection_request(const void*); void sli_bt_cmd_l2cap_coc_send_data(const void*); void sli_bt_cmd_cte_transmitter_enable_cte_response(const void*); void sli_bt_cmd_cte_transmitter_disable_cte_response(const void*); void sli_bt_cmd_cte_transmitter_start_connectionless_cte(const void*); void sli_bt_cmd_cte_transmitter_stop_connectionless_cte(const void*); void sli_bt_cmd_cte_transmitter_set_dtm_parameters(const void*); void sli_bt_cmd_cte_transmitter_clear_dtm_parameters(const void*); void sli_bt_cmd_cte_receiver_configure(const void*); void sli_bt_cmd_cte_receiver_start_iq_sampling(const void*); void sli_bt_cmd_cte_receiver_stop_iq_sampling(const void*); void sli_bt_cmd_cte_receiver_start_connectionless_iq_sampling(const void*); void sli_bt_cmd_cte_receiver_stop_connectionless_iq_sampling(const void*); void sli_bt_cmd_cte_receiver_set_dtm_parameters(const void*); void sli_bt_cmd_cte_receiver_clear_dtm_parameters(const void*);typedef void (*gecko_cmd_handler)(const void*); void sli_bt_cmd_handler_delegate(uint32_t header, gecko_cmd_handler, const void*); extern void* gecko_cmd_msg_buf; extern void* gecko_rsp_msg_buf; /** * * gecko_cmd_dfu_reset * * This command can be used to reset the system. This command does not have a response, but it triggers one of the boot events (normal reset or boot to DFU mode) after re-boot. * * @param dfu Boot mode: * - 0: Normal reset * - 1: Boot to UART DFU mode * - 2: Boot to OTA DFU mode * * * Events generated * * gecko_evt_system_boot - Sent after the device has booted into normal mode * gecko_evt_dfu_boot - Sent after the device has booted into UART DFU mode * **/ static inline void* gecko_cmd_dfu_reset(uint8 dfu) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; gecko_cmd_msg->data.cmd_dfu_reset.dfu=dfu; gecko_cmd_msg->header=((gecko_cmd_dfu_reset_id+((1)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_dfu_reset, &gecko_cmd_msg->data.payload); return 0; } /** * * gecko_cmd_dfu_flash_set_address * * After re-booting the local device into DFU mode, this command can be used to define the starting address on the flash to where the new firmware will be written in. * * @param address The offset in the flash where the new firmware is uploaded to. Always use the value 0x00000000. * **/ static inline struct gecko_msg_dfu_flash_set_address_rsp_t* gecko_cmd_dfu_flash_set_address(uint32 address) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; gecko_cmd_msg->data.cmd_dfu_flash_set_address.address=address; gecko_cmd_msg->header=((gecko_cmd_dfu_flash_set_address_id+((4)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_dfu_flash_set_address, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_dfu_flash_set_address; } /** * * gecko_cmd_dfu_flash_upload * * This command can be used to upload the whole firmware image file into the Bluetooth device. The passed data length must be a multiple of 4 bytes. As the BGAPI command payload size is limited, multiple commands need to be issued one after the other until the whole .bin firmware image file is uploaded to the device. The next address of the flash sector in memory to write to is automatically updated by the bootloader after each individual command. * * @param data An array of data which will be written onto the flash. * **/ static inline struct gecko_msg_dfu_flash_upload_rsp_t* gecko_cmd_dfu_flash_upload(uint8 data_len, const uint8* data_data) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; if ((uint16_t)data_len > 256 - 1) { gecko_rsp_msg->data.rsp_dfu_flash_upload.result = bg_err_command_too_long; return &gecko_rsp_msg->data.rsp_dfu_flash_upload; } gecko_cmd_msg->data.cmd_dfu_flash_upload.data.len=data_len; memcpy(gecko_cmd_msg->data.cmd_dfu_flash_upload.data.data,data_data,data_len); gecko_cmd_msg->header=((gecko_cmd_dfu_flash_upload_id+((1+data_len)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_dfu_flash_upload, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_dfu_flash_upload; } /** * * gecko_cmd_dfu_flash_upload_finish * * This command can be used to tell to the device that the DFU file has been fully uploaded. To return the device back to normal mode the command "DFU Reset " must be issued next. * * **/ static inline struct gecko_msg_dfu_flash_upload_finish_rsp_t* gecko_cmd_dfu_flash_upload_finish() { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; gecko_cmd_msg->header=((gecko_cmd_dfu_flash_upload_finish_id+((0)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_dfu_flash_upload_finish, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_dfu_flash_upload_finish; } /** * * gecko_cmd_system_hello * * This command does not trigger any event but the response to the command is used to verify that communication between the host and the device is working. * * **/ static inline struct gecko_msg_system_hello_rsp_t* gecko_cmd_system_hello() { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; gecko_cmd_msg->header=((gecko_cmd_system_hello_id+((0)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_system_hello, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_system_hello; } /** * * gecko_cmd_system_reset * * This command can be used to reset the system. It does not have a response, but it triggers one of the boot events (normal reset or boot to DFU mode) depending on the selected boot mode. * * @param dfu Boot mode: * - 0: Normal reset * - 1: Boot to UART DFU mode * - 2: Boot to OTA DFU mode * * * Events generated * * gecko_evt_system_boot - Sent after the device has booted into normal mode * gecko_evt_dfu_boot - Sent after the device has booted into UART DFU mode * **/ static inline void* gecko_cmd_system_reset(uint8 dfu) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; gecko_cmd_msg->data.cmd_system_reset.dfu=dfu; gecko_cmd_msg->header=((gecko_cmd_system_reset_id+((1)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_system_reset, &gecko_cmd_msg->data.payload); return 0; } /** * * gecko_cmd_system_get_bt_address * * This command can be used to read the Bluetooth public address used by the device. * * **/ static inline struct gecko_msg_system_get_bt_address_rsp_t* gecko_cmd_system_get_bt_address() { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; gecko_cmd_msg->header=((gecko_cmd_system_get_bt_address_id+((0)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_system_get_bt_address, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_system_get_bt_address; } /** * * gecko_cmd_system_set_bt_address * * Deprecated. Replacement is "system_set_identity_address" command. * This command can be used to set the Bluetooth public address used by * the device. A valid address set with this command overrides the * default Bluetooth public address programmed at production, and it will * be effective in the next system reboot. The stack treats * 00:00:00:00:00:00 and ff:ff:ff:ff:ff:ff as invalid addresses. Thus * passing one of them into this command will cause the stack to use the * default address in the next system reboot. * * * @param address Bluetooth public address in little endian format * **/ BGLIB_DEPRECATED_API static inline struct gecko_msg_system_set_bt_address_rsp_t* gecko_cmd_system_set_bt_address(bd_addr address) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; memcpy(&gecko_cmd_msg->data.cmd_system_set_bt_address.address,&address,sizeof(bd_addr)); gecko_cmd_msg->header=((gecko_cmd_system_set_bt_address_id+((6)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_system_set_bt_address, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_system_set_bt_address; } /** * * gecko_cmd_system_set_tx_power * * This command can be used to set the global maximum TX power for Bluetooth. The returned value in the response is the selected maximum output power level after applying RF path compensation. If the GATT server contains a Tx Power service, the Tx Power Level attribute of the service will be updated accordingly. * The selected power level may be less than the specified value if the * device does not meet the power requirements. For Bluetooth connections * the maximum TX power will be limited to 10 dBm if Adaptive Frequency * Hopping (AFH) is not enabled. * By default, the global maximum TX power value is 8 dBm. * NOTE: This command should not be used while advertising, scanning or during connection. * * * @param power TX power in 0.1dBm steps, for example the value of 10 is 1dBm and 55 is 5.5dBm * **/ static inline struct gecko_msg_system_set_tx_power_rsp_t* gecko_cmd_system_set_tx_power(int16 power) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; gecko_cmd_msg->data.cmd_system_set_tx_power.power=power; gecko_cmd_msg->header=((gecko_cmd_system_set_tx_power_id+((2)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_system_set_tx_power, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_system_set_tx_power; } /** * * gecko_cmd_system_get_random_data * * This command can be used to get random data up to 16 bytes. * * @param length Length of random data. Maximum length is 16 bytes. * **/ static inline struct gecko_msg_system_get_random_data_rsp_t* gecko_cmd_system_get_random_data(uint8 length) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; gecko_cmd_msg->data.cmd_system_get_random_data.length=length; gecko_cmd_msg->header=((gecko_cmd_system_get_random_data_id+((1)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_system_get_random_data, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_system_get_random_data; } /** * * gecko_cmd_system_halt * * This command forces radio to idle state and allows device to sleep. Advertising, scanning, connections and software timers are halted by this commands. Halted operations are resumed by calling this command with parameter 0. Connections stay alive if system is resumed before connection supervision timeout. * This command should only be used for a short time period (a few * seconds at maximum). It halts Bluetooth activity, but * all the tasks and operations are still existing inside * stack with their own concepts of time. Halting the system for a long * time period may have negative consequences on stack's * internal states. * NOTE:Software timer is also halted. Hardware interrupts are the only way to wake up from energy mode 2 when system is halted. * * * @param halt Values: * - 1: halt * - 0: resume * * **/ static inline struct gecko_msg_system_halt_rsp_t* gecko_cmd_system_halt(uint8 halt) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; gecko_cmd_msg->data.cmd_system_halt.halt=halt; gecko_cmd_msg->header=((gecko_cmd_system_halt_id+((1)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_system_halt, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_system_halt; } /** * * gecko_cmd_system_set_device_name * * This command can be used to set the device name. Currently it is possible to set the name which will be used during the OTA update. The name will be stored in persistent storage. If the OTA device name is also set in gecko configuration, the name stored in persistent storage is overwritten with the name in gecko configuration during device boot. * * @param type Device name to set. Values: * - 0: OTA device name * * @param name Device name * **/ static inline struct gecko_msg_system_set_device_name_rsp_t* gecko_cmd_system_set_device_name(uint8 type,uint8 name_len, const uint8* name_data) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; if ((uint16_t)name_len > 256 - 2) { gecko_rsp_msg->data.rsp_system_set_device_name.result = bg_err_command_too_long; return &gecko_rsp_msg->data.rsp_system_set_device_name; } gecko_cmd_msg->data.cmd_system_set_device_name.type=type; gecko_cmd_msg->data.cmd_system_set_device_name.name.len=name_len; memcpy(gecko_cmd_msg->data.cmd_system_set_device_name.name.data,name_data,name_len); gecko_cmd_msg->header=((gecko_cmd_system_set_device_name_id+((2+name_len)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_system_set_device_name, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_system_set_device_name; } /** * * gecko_cmd_system_linklayer_configure * * Send configuration data to linklayer. This command is used to fine tune low level Bluetooth operation. * * @param key Key to configure: * - 1:HALT, same as system_halt command, value-0 Stop Radio 1- Start Radio * - 2:PRIORITY_RANGE, Sets RAIL priority_mapping offset field of linklayer Priority configuration structure to the first byte of value field. * - 3:SCAN_CHANNELS, Sets channels to scan on. First byte of value is channel map. 0x1 = Channel 37, 0x2 = Channel 38, 0x4 = Channel 39 * - 4:SET_FLAGS, Set Link Layer configuration flags. value is little endian 32bit integer. Flag Values: * - 0x00000001 - Disable Feature Exchange when slave * - 0x00000002 - Disable Feature Exchange when master * - 5:CLR_FLAGS, value is flags to clear. Flags are same as in SET_FLAGS command. * - 7:SET_AFH_INTERVAL, Set afh_scan_interval field of Link Layer priority configuration structure. * - 0: * * @param data Configuration data. Length and contents of data field depend on the key value used. * **/ static inline struct gecko_msg_system_linklayer_configure_rsp_t* gecko_cmd_system_linklayer_configure(uint8 key,uint8 data_len, const uint8* data_data) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; if ((uint16_t)data_len > 256 - 2) { gecko_rsp_msg->data.rsp_system_linklayer_configure.result = bg_err_command_too_long; return &gecko_rsp_msg->data.rsp_system_linklayer_configure; } gecko_cmd_msg->data.cmd_system_linklayer_configure.key=key; gecko_cmd_msg->data.cmd_system_linklayer_configure.data.len=data_len; memcpy(gecko_cmd_msg->data.cmd_system_linklayer_configure.data.data,data_data,data_len); gecko_cmd_msg->header=((gecko_cmd_system_linklayer_configure_id+((2+data_len)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_system_linklayer_configure, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_system_linklayer_configure; } /** * * gecko_cmd_system_get_counters * * Get packet and error counters * * @param reset Reset counters if parameter value is nonzero * **/ static inline struct gecko_msg_system_get_counters_rsp_t* gecko_cmd_system_get_counters(uint8 reset) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; gecko_cmd_msg->data.cmd_system_get_counters.reset=reset; gecko_cmd_msg->header=((gecko_cmd_system_get_counters_id+((1)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_system_get_counters, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_system_get_counters; } /** * * gecko_cmd_system_set_identity_address * * This command can be used to set the device's Bluetooth identity address. The address can be a public device address or static random address. A valid address set with this command overrides the default Bluetooth public address that was programmed at production, and it will be effective in the next system reboot. The stack treats 00:00:00:00:00:00 and ff:ff:ff:ff:ff:ff as invalid addresses. Thus passing one of them into this command will cause the stack to use the default address in next system reboot. * * @param address Bluetooth identity address in little endian format * @param type Address type * - 0: Public device address * - 1: Static random address * * **/ static inline struct gecko_msg_system_set_identity_address_rsp_t* gecko_cmd_system_set_identity_address(bd_addr address,uint8 type) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; memcpy(&gecko_cmd_msg->data.cmd_system_set_identity_address.address,&address,sizeof(bd_addr)); gecko_cmd_msg->data.cmd_system_set_identity_address.type=type; gecko_cmd_msg->header=((gecko_cmd_system_set_identity_address_id+((7)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_system_set_identity_address, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_system_set_identity_address; } /** * * gecko_cmd_le_gap_open * * Deprecated. Replacement is "le_gap_connect" command which allows to open a connection with a specified PHY. * This command can be used to connect an advertising device with * initiating PHY being the LE 1M PHY. * * * @param address Address of the device to connect to * @param address_type Address type of the device to connect to * * Events generated * * gecko_evt_le_connection_opened - This event is triggered after the connection has been opened, and indicates whether the devices are already bonded and what is the role of the Bluetooth device (Slave or Master). * gecko_evt_le_connection_parameters - This event indicates the connection parameters and security mode of the connection. * **/ BGLIB_DEPRECATED_API static inline struct gecko_msg_le_gap_open_rsp_t* gecko_cmd_le_gap_open(bd_addr address,uint8 address_type) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; memcpy(&gecko_cmd_msg->data.cmd_le_gap_open.address,&address,sizeof(bd_addr)); gecko_cmd_msg->data.cmd_le_gap_open.address_type=address_type; gecko_cmd_msg->header=((gecko_cmd_le_gap_open_id+((7)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_le_gap_open, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_le_gap_open; } /** * * gecko_cmd_le_gap_set_mode * * Deprecated. Use "le_gap_start_advertising" command for enabling the advertising, and "le_gap_stop_advertising" command for disabling the advertising. * This command is only effective on the first advertising set (handle * value 0). Other advertising sets are not affected. * * * @param discover Discoverable mode * @param connect Connectable mode * * Events generated * * gecko_evt_le_gap_adv_timeout - Triggered when the number of advertising events has been done and advertising is stopped. * gecko_evt_le_connection_opened - Triggered when a remote device opened a connection to this advertising device. * **/ BGLIB_DEPRECATED_API static inline struct gecko_msg_le_gap_set_mode_rsp_t* gecko_cmd_le_gap_set_mode(uint8 discover,uint8 connect) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; gecko_cmd_msg->data.cmd_le_gap_set_mode.discover=discover; gecko_cmd_msg->data.cmd_le_gap_set_mode.connect=connect; gecko_cmd_msg->header=((gecko_cmd_le_gap_set_mode_id+((2)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_le_gap_set_mode, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_le_gap_set_mode; } /** * * gecko_cmd_le_gap_discover * * Deprecated. Replacement is "le_gap_start_discovery" command which allows to scan on LE 1M PHY or LE Coded PHY. * This command can be used to start the GAP discovery procedure to scan * for advertising devices on LE 1M PHY. To cancel an ongoing * discovery process use the "le_gap_end_procedure" command. * * * @param mode Bluetooth discovery Mode. For values see link * * Events generated * * gecko_evt_le_gap_scan_response - Every time an advertising packet is received, this event is triggered. The packets are not filtered in any way, so multiple events will be received for every advertising device in range. * **/ BGLIB_DEPRECATED_API static inline struct gecko_msg_le_gap_discover_rsp_t* gecko_cmd_le_gap_discover(uint8 mode) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; gecko_cmd_msg->data.cmd_le_gap_discover.mode=mode; gecko_cmd_msg->header=((gecko_cmd_le_gap_discover_id+((1)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_le_gap_discover, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_le_gap_discover; } /** * * gecko_cmd_le_gap_end_procedure * * This command can be used to end a current GAP procedure. * * **/ static inline struct gecko_msg_le_gap_end_procedure_rsp_t* gecko_cmd_le_gap_end_procedure() { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; gecko_cmd_msg->header=((gecko_cmd_le_gap_end_procedure_id+((0)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_le_gap_end_procedure, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_le_gap_end_procedure; } /** * * gecko_cmd_le_gap_set_adv_parameters * * Deprecated. Replacements are "le_gap_set_advertise_timing" command for setting the advertising intervals, and "le_gap_set_advertise_channel_map" command for setting the channel map. * This command is only effective on the first advertising set (handle * value 0). Other advertising sets are not affected. * * * @param interval_min Minimum advertising interval. Value in units of 0.625 ms * - Range: 0x20 to 0xFFFF * - Time range: 20 ms to 40.96 s * Default value: 100 ms * @param interval_max Maximum advertising interval. Value in units of 0.625 ms * - Range: 0x20 to 0xFFFF * - Time range: 20 ms to 40.96 s * - Note: interval_max should be bigger than interval_min * Default value: 200 ms * @param channel_map Advertising channel map which determines which of the three channels will be used for advertising. This value is given as a bitmask. Values: * - 1: Advertise on CH37 * - 2: Advertise on CH38 * - 3: Advertise on CH37 and CH38 * - 4: Advertise on CH39 * - 5: Advertise on CH37 and CH39 * - 6: Advertise on CH38 and CH39 * - 7: Advertise on all channels * Recommended value: 7 * Default value: 7 * **/ BGLIB_DEPRECATED_API static inline struct gecko_msg_le_gap_set_adv_parameters_rsp_t* gecko_cmd_le_gap_set_adv_parameters(uint16 interval_min,uint16 interval_max,uint8 channel_map) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; gecko_cmd_msg->data.cmd_le_gap_set_adv_parameters.interval_min=interval_min; gecko_cmd_msg->data.cmd_le_gap_set_adv_parameters.interval_max=interval_max; gecko_cmd_msg->data.cmd_le_gap_set_adv_parameters.channel_map=channel_map; gecko_cmd_msg->header=((gecko_cmd_le_gap_set_adv_parameters_id+((5)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_le_gap_set_adv_parameters, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_le_gap_set_adv_parameters; } /** * * gecko_cmd_le_gap_set_conn_parameters * * This command can be used to set the default Bluetooth connection parameters. The configured values are valid for all subsequent connections that will be established. For changing the parameters of an already established connection use the command "le_connection_set_parameters". * * @param min_interval Minimum value for the connection event interval. This must be set be less than or equal to max_interval. * - Time = Value x 1.25 ms * - Range: 0x0006 to 0x0c80 * - Time Range: 7.5 ms to 4 s * Default value: 20 ms * @param max_interval Maximum value for the connection event interval. This must be set greater than or equal to min_interval. * - Time = Value x 1.25 ms * - Range: 0x0006 to 0x0c80 * - Time Range: 7.5 ms to 4 s * Default value: 50 ms * @param latency Slave latency. This parameter defines how many connection intervals the slave can skip if it has no data to send * - Range: 0x0000 to 0x01f4 * Default value: 0 * @param timeout Supervision timeout. The supervision timeout defines for how long the connection is maintained despite the devices being unable to communicate at the currently configured connection intervals. * - Range: 0x000a to 0x0c80 * - Time = Value x 10 ms * - Time Range: 100 ms to 32 s * - The value in milliseconds must be larger than (1 + latency) * max_interval * 2, where max_interval is given in milliseconds * It is recommended that the supervision timeout is set at a value which allows communication attempts over at least a few connection intervals. * Default value: 1000 ms * * **/ static inline struct gecko_msg_le_gap_set_conn_parameters_rsp_t* gecko_cmd_le_gap_set_conn_parameters(uint16 min_interval,uint16 max_interval,uint16 latency,uint16 timeout) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; gecko_cmd_msg->data.cmd_le_gap_set_conn_parameters.min_interval=min_interval; gecko_cmd_msg->data.cmd_le_gap_set_conn_parameters.max_interval=max_interval; gecko_cmd_msg->data.cmd_le_gap_set_conn_parameters.latency=latency; gecko_cmd_msg->data.cmd_le_gap_set_conn_parameters.timeout=timeout; gecko_cmd_msg->header=((gecko_cmd_le_gap_set_conn_parameters_id+((8)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_le_gap_set_conn_parameters, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_le_gap_set_conn_parameters; } /** * * gecko_cmd_le_gap_set_scan_parameters * * Deprecated. Replacements are "le_gap_set_discovery_timing" command for setting timing parameters, and "le_gap_set_discovery_type" command for the scan type. * The parameters set by this command is only effective on the LE 1M PHY. * For LE Coded PHY, above replacement command must be used. * * * @param scan_interval Scanner interval. This is defined as the time interval from when the device started its last scan until it begins the subsequent scan, that is how often to scan * - Time = Value x 0.625 ms * - Range: 0x0004 to 0x4000 * - Time Range: 2.5 ms to 10.24 s * Default value: 10 ms * There is a variable delay when switching channels at the end of each * scanning interval which is included in the scanning interval time * itself. During this switch time no advertising packets will be * received by the device. The switch time variation is dependent on use * case, for example in case of scanning while keeping active connections * the channel switch time might be longer than when only scanning * without any active connections. Increasing the scanning interval will * reduce the amount of time in which the device cannot receive * advertising packets as it will switch channels less often. * After every scan interval the scanner will change the frequency it * operates at. It will cycle through all the three advertising channels * in a round robin fashion. According to the specification all three * channels must be used by a scanner. * * @param scan_window Scan window. The duration of the scan. scan_window shall be less than or equal to scan_interval * - Time = Value x 0.625 ms * - Range: 0x0004 to 0x4000 * - Time Range: 2.5 ms to 10.24 s * Default value: 10 ms Note that packet reception is aborted if it has been started before scan window ends. * @param active Scan type indicated by a flag. Values: * - 0: Passive scanning * - 1: Active scanning * - In passive scanning mode the device only listens to advertising packets and will not transmit any packet * - In active scanning mode the device will send out a scan request packet upon receiving advertising packet from a remote device and then it will listen to the scan response packet from remote device * Default value: 0 * **/ BGLIB_DEPRECATED_API static inline struct gecko_msg_le_gap_set_scan_parameters_rsp_t* gecko_cmd_le_gap_set_scan_parameters(uint16 scan_interval,uint16 scan_window,uint8 active) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; gecko_cmd_msg->data.cmd_le_gap_set_scan_parameters.scan_interval=scan_interval; gecko_cmd_msg->data.cmd_le_gap_set_scan_parameters.scan_window=scan_window; gecko_cmd_msg->data.cmd_le_gap_set_scan_parameters.active=active; gecko_cmd_msg->header=((gecko_cmd_le_gap_set_scan_parameters_id+((5)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_le_gap_set_scan_parameters, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_le_gap_set_scan_parameters; } /** * * gecko_cmd_le_gap_set_adv_data * * Deprecated. Use "le_gap_bt5_set_adv_data" command to set the advertising data and scan response data. * This command is only effective on the first advertising set (handle * value 0). Other advertising sets are not affected. * * * @param scan_rsp This value selects if the data is intended for advertising packets, scan response packets or advertising packet in OTA. Values: * - 0: Advertising packets * - 1: Scan response packets * - 2: OTA advertising packets * - 4: OTA scan response packets * * @param adv_data Data to be set. Maximum data length: * - 31 bytes for legacy advertising; * - 191 bytes for extended advertising * * **/ BGLIB_DEPRECATED_API static inline struct gecko_msg_le_gap_set_adv_data_rsp_t* gecko_cmd_le_gap_set_adv_data(uint8 scan_rsp,uint8 adv_data_len, const uint8* adv_data_data) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; if ((uint16_t)adv_data_len > 256 - 2) { gecko_rsp_msg->data.rsp_le_gap_set_adv_data.result = bg_err_command_too_long; return &gecko_rsp_msg->data.rsp_le_gap_set_adv_data; } gecko_cmd_msg->data.cmd_le_gap_set_adv_data.scan_rsp=scan_rsp; gecko_cmd_msg->data.cmd_le_gap_set_adv_data.adv_data.len=adv_data_len; memcpy(gecko_cmd_msg->data.cmd_le_gap_set_adv_data.adv_data.data,adv_data_data,adv_data_len); gecko_cmd_msg->header=((gecko_cmd_le_gap_set_adv_data_id+((2+adv_data_len)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_le_gap_set_adv_data, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_le_gap_set_adv_data; } /** * * gecko_cmd_le_gap_set_adv_timeout * * Deprecated. New command "le_gap_set_advertise_timing" should be used for this functionality. * This command is only effective on the first advertising set (handle * value 0). Other advertising sets are not affected. * * * @param maxevents If non-zero, indicates the maximum number of advertising events to send before stopping advertiser. Value 0 indicates no maximum number limit. * **/ BGLIB_DEPRECATED_API static inline struct gecko_msg_le_gap_set_adv_timeout_rsp_t* gecko_cmd_le_gap_set_adv_timeout(uint8 maxevents) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; gecko_cmd_msg->data.cmd_le_gap_set_adv_timeout.maxevents=maxevents; gecko_cmd_msg->header=((gecko_cmd_le_gap_set_adv_timeout_id+((1)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_le_gap_set_adv_timeout, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_le_gap_set_adv_timeout; } /** * * gecko_cmd_le_gap_bt5_set_mode * * Deprecated. Replacements are "le_gap_start_advertising" command to start the advertising, and "le_gap_stop_advertising" command to stop the advertising. "le_gap_set_advertise_timing" command can be used for setting the maxevents and command "le_gap_set_advertise_configuration" can be used to for setting address types. * * * @param handle Advertising set handle, number of sets available is defined in stack configuration * @param discover Discoverable mode * @param connect Connectable mode * @param maxevents If non-zero, indicates the maximum number of advertising events to send before stopping advertiser. Value 0 indicates no maximum number limit. * @param address_type Address type to use for packets * * Events generated * * gecko_evt_le_gap_adv_timeout - Triggered when the number of advertising events set by this command has been done and advertising is stopped on the given advertising set. * gecko_evt_le_connection_opened - Triggered when a remote device opened a connection to the advertiser on the specified advertising set. * **/ BGLIB_DEPRECATED_API static inline struct gecko_msg_le_gap_bt5_set_mode_rsp_t* gecko_cmd_le_gap_bt5_set_mode(uint8 handle,uint8 discover,uint8 connect,uint16 maxevents,uint8 address_type) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; gecko_cmd_msg->data.cmd_le_gap_bt5_set_mode.handle=handle; gecko_cmd_msg->data.cmd_le_gap_bt5_set_mode.discover=discover; gecko_cmd_msg->data.cmd_le_gap_bt5_set_mode.connect=connect; gecko_cmd_msg->data.cmd_le_gap_bt5_set_mode.maxevents=maxevents; gecko_cmd_msg->data.cmd_le_gap_bt5_set_mode.address_type=address_type; gecko_cmd_msg->header=((gecko_cmd_le_gap_bt5_set_mode_id+((6)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_le_gap_bt5_set_mode, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_le_gap_bt5_set_mode; } /** * * gecko_cmd_le_gap_bt5_set_adv_parameters * * Deprecated. Replacements are "le_gap_set_advertise_timing" command for setting the advertising intervals, "le_gap_set_advertise_channel_map" command for setting the channel map, and "le_gap_set_advertise_report_scan_request" command for enabling and disabling scan request notifications. * * * @param handle Advertising set handle, number of sets available is defined in stack configuration * @param interval_min Minimum advertising interval. Value in units of 0.625 ms * - Range: 0x20 to 0xFFFF * - Time range: 20 ms to 40.96 s * Default value: 100 ms * @param interval_max Maximum advertising interval. Value in units of 0.625 ms * - Range: 0x20 to 0xFFFF * - Time range: 20 ms to 40.96 s * - Note: interval_max should be bigger than interval_min * Default value: 200 ms * @param channel_map Advertising channel map which determines which of the three channels will be used for advertising. This value is given as a bitmask. Values: * - 1: Advertise on CH37 * - 2: Advertise on CH38 * - 3: Advertise on CH37 and CH38 * - 4: Advertise on CH39 * - 5: Advertise on CH37 and CH39 * - 6: Advertise on CH38 and CH39 * - 7: Advertise on all channels * Recommended value: 7 * Default value: 7 * @param report_scan If non-zero, enables scan request notification, and scan requests will be reported as events. * Default value: 0 * * * Events generated * * gecko_evt_le_gap_scan_request - Triggered when a scan request has been received during the advertising if scan request notification has been enabled by this command. * **/ BGLIB_DEPRECATED_API static inline struct gecko_msg_le_gap_bt5_set_adv_parameters_rsp_t* gecko_cmd_le_gap_bt5_set_adv_parameters(uint8 handle,uint16 interval_min,uint16 interval_max,uint8 channel_map,uint8 report_scan) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; gecko_cmd_msg->data.cmd_le_gap_bt5_set_adv_parameters.handle=handle; gecko_cmd_msg->data.cmd_le_gap_bt5_set_adv_parameters.interval_min=interval_min; gecko_cmd_msg->data.cmd_le_gap_bt5_set_adv_parameters.interval_max=interval_max; gecko_cmd_msg->data.cmd_le_gap_bt5_set_adv_parameters.channel_map=channel_map; gecko_cmd_msg->data.cmd_le_gap_bt5_set_adv_parameters.report_scan=report_scan; gecko_cmd_msg->header=((gecko_cmd_le_gap_bt5_set_adv_parameters_id+((7)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_le_gap_bt5_set_adv_parameters, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_le_gap_bt5_set_adv_parameters; } /** * * gecko_cmd_le_gap_bt5_set_adv_data * * This command can be used to set user defined data in advertising packets, scan response packets or periodic advertising packets. * If advertising mode is currently enabled the new advertising data will * be used immediately. Advertising mode can be enabled using * command "le_gap_start_advertising". Periodic * advertising mode can be enabled using command * "le_gap_start_periodic_advertising". * The maximum data length is 31 bytes for legacy advertising and 191 * bytes for extended advertising. * The invalid parameter error will be returned in following situations: * - The data length is more than 31 bytes but the advertiser can only advertise using legacy advertising PDUs; * - The data length is more than 191 bytes when the advertiser can advertise using extended advertising PDUs; * - Set the data of advertising data packet when the advertiser is advertising in scannable mode using extended advertising PDUs; * - Set the data of scan response data packet when the advertiser is advertising in connectable mode using extended advertising PDUs. * Note that the user defined data may be overwritten by the system when * the advertising is later enabled in other discoverable mode than * user_data. * * * @param handle Advertising set handle, number of sets available is defined in stack configuration * @param scan_rsp This value selects if the data is intended for advertising packets, scan response packets, periodic advertising packets or advertising packet in OTA. Values: * - 0: Advertising packets * - 1: Scan response packets * - 2: OTA advertising packets * - 4: OTA scan response packets * - 8: Periodic advertising packets * * @param adv_data Data to be set. Maximum data length: * - 31 bytes for legacy advertising; * - 191 bytes for extended advertising * * **/ static inline struct gecko_msg_le_gap_bt5_set_adv_data_rsp_t* gecko_cmd_le_gap_bt5_set_adv_data(uint8 handle,uint8 scan_rsp,uint8 adv_data_len, const uint8* adv_data_data) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; if ((uint16_t)adv_data_len > 256 - 3) { gecko_rsp_msg->data.rsp_le_gap_bt5_set_adv_data.result = bg_err_command_too_long; return &gecko_rsp_msg->data.rsp_le_gap_bt5_set_adv_data; } gecko_cmd_msg->data.cmd_le_gap_bt5_set_adv_data.handle=handle; gecko_cmd_msg->data.cmd_le_gap_bt5_set_adv_data.scan_rsp=scan_rsp; gecko_cmd_msg->data.cmd_le_gap_bt5_set_adv_data.adv_data.len=adv_data_len; memcpy(gecko_cmd_msg->data.cmd_le_gap_bt5_set_adv_data.adv_data.data,adv_data_data,adv_data_len); gecko_cmd_msg->header=((gecko_cmd_le_gap_bt5_set_adv_data_id+((3+adv_data_len)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_le_gap_bt5_set_adv_data, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_le_gap_bt5_set_adv_data; } /** * * gecko_cmd_le_gap_set_privacy_mode * * This command can be used to enable or disable privacy feature on all GAP roles. The new privacy mode will take effect for advertising on the next advertising enabling, for scanning on the next scan enabling, and for initiating on the next open connection command. When privacy is enabled and the device is advertising or scanning, the stack will maintain a periodic timer with the specified time interval as timeout value. At each timeout the stack will generate a new private resolvable address and use it in advertising data packets and scanning requests. * By default, privacy feature is disabled. * * * @param privacy Values: * - 0: Disable privacy * - 1: Enable privacy * * @param interval The minimum time interval between private address change. This parameter is ignored if this command is issued for disabling privacy mode. Values: * - 0: Use default interval, 15 minutes * - others: The time interval in minutes * * **/ static inline struct gecko_msg_le_gap_set_privacy_mode_rsp_t* gecko_cmd_le_gap_set_privacy_mode(uint8 privacy,uint8 interval) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; gecko_cmd_msg->data.cmd_le_gap_set_privacy_mode.privacy=privacy; gecko_cmd_msg->data.cmd_le_gap_set_privacy_mode.interval=interval; gecko_cmd_msg->header=((gecko_cmd_le_gap_set_privacy_mode_id+((2)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_le_gap_set_privacy_mode, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_le_gap_set_privacy_mode; } /** * * gecko_cmd_le_gap_set_advertise_timing * * This command can be used to set the advertising timing parameters of the given advertising set. This setting will take effect on the next advertising enabling. * * @param handle Advertising set handle * @param interval_min Minimum advertising interval. Value in units of 0.625 ms * - Range: 0x20 to 0xFFFF * - Time range: 20 ms to 40.96 s * Default value: 100 ms * @param interval_max Maximum advertising interval. Value in units of 0.625 ms * - Range: 0x20 to 0xFFFF * - Time range: 20 ms to 40.96 s * - Note: interval_max should be bigger than interval_min * Default value: 200 ms * @param duration The advertising duration for this advertising set. Value 0 indicates no advertising duration limit and the advertising continues until it is disabled. A non-zero value sets the duration in units of 10 ms. The duration begins at the start of the first advertising event of this advertising set. * - Range: 0x0001 to 0xFFFF * - Time range: 10 ms to 655.35 s * Default value: 0 * @param maxevents If non-zero, indicates the maximum number of advertising events to send before stopping advertiser. Value 0 indicates no maximum number limit. * Default value: 0 * * **/ static inline struct gecko_msg_le_gap_set_advertise_timing_rsp_t* gecko_cmd_le_gap_set_advertise_timing(uint8 handle,uint32 interval_min,uint32 interval_max,uint16 duration,uint8 maxevents) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; gecko_cmd_msg->data.cmd_le_gap_set_advertise_timing.handle=handle; gecko_cmd_msg->data.cmd_le_gap_set_advertise_timing.interval_min=interval_min; gecko_cmd_msg->data.cmd_le_gap_set_advertise_timing.interval_max=interval_max; gecko_cmd_msg->data.cmd_le_gap_set_advertise_timing.duration=duration; gecko_cmd_msg->data.cmd_le_gap_set_advertise_timing.maxevents=maxevents; gecko_cmd_msg->header=((gecko_cmd_le_gap_set_advertise_timing_id+((12)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_le_gap_set_advertise_timing, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_le_gap_set_advertise_timing; } /** * * gecko_cmd_le_gap_set_advertise_channel_map * * This command can be used to set the primary advertising channel map of the given advertising set. This setting will take effect on the next advertising enabling. * * @param handle Advertising set handle * @param channel_map Advertisement channel map which determines which of the three channels will be used for advertising. This value is given as a bitmask. Values: * - 1: Advertise on CH37 * - 2: Advertise on CH38 * - 3: Advertise on CH37 and CH38 * - 4: Advertise on CH39 * - 5: Advertise on CH37 and CH39 * - 6: Advertise on CH38 and CH39 * - 7: Advertise on all channels * Recommended value: 7 * Default value: 7 * **/ static inline struct gecko_msg_le_gap_set_advertise_channel_map_rsp_t* gecko_cmd_le_gap_set_advertise_channel_map(uint8 handle,uint8 channel_map) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; gecko_cmd_msg->data.cmd_le_gap_set_advertise_channel_map.handle=handle; gecko_cmd_msg->data.cmd_le_gap_set_advertise_channel_map.channel_map=channel_map; gecko_cmd_msg->header=((gecko_cmd_le_gap_set_advertise_channel_map_id+((2)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_le_gap_set_advertise_channel_map, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_le_gap_set_advertise_channel_map; } /** * * gecko_cmd_le_gap_set_advertise_report_scan_request * * This command can be used to enable or disable the scan request notification of the given advertising set. This setting will take effect on the next advertising enabling. * * @param handle Advertising set handle * @param report_scan_req If non-zero, enables scan request notification, and scan requests will be reported as events. * Default value: 0 * * * Events generated * * gecko_evt_le_gap_scan_request - Triggered when a scan request has been received during the advertising if scan request notification has been enabled by this command. * **/ static inline struct gecko_msg_le_gap_set_advertise_report_scan_request_rsp_t* gecko_cmd_le_gap_set_advertise_report_scan_request(uint8 handle,uint8 report_scan_req) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; gecko_cmd_msg->data.cmd_le_gap_set_advertise_report_scan_request.handle=handle; gecko_cmd_msg->data.cmd_le_gap_set_advertise_report_scan_request.report_scan_req=report_scan_req; gecko_cmd_msg->header=((gecko_cmd_le_gap_set_advertise_report_scan_request_id+((2)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_le_gap_set_advertise_report_scan_request, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_le_gap_set_advertise_report_scan_request; } /** * * gecko_cmd_le_gap_set_advertise_phy * * This command can be used to set the advertising PHYs of the given advertising set. This setting will take effect on the next advertising enabling. "Invalid Parameter" error will be returned if a PHY value is invalid or the device does not support a given PHY. * * @param handle Advertising set handle * @param primary_phy The PHY on which the advertising packets are transmitted on the primary advertising channel. If legacy advertising PDUs are being used, the PHY must be LE 1M. * Values: * - 1: Advertising PHY is LE 1M * - 4: Advertising PHY is LE Coded * Default: 1 * * @param secondary_phy The PHY on which the advertising packets are transmitted on the secondary advertising channel. * Values: * - 1: Advertising PHY is LE 1M * - 2: Advertising PHY is LE 2M * - 4: Advertising PHY is LE Coded * Default: 1 * * **/ static inline struct gecko_msg_le_gap_set_advertise_phy_rsp_t* gecko_cmd_le_gap_set_advertise_phy(uint8 handle,uint8 primary_phy,uint8 secondary_phy) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; gecko_cmd_msg->data.cmd_le_gap_set_advertise_phy.handle=handle; gecko_cmd_msg->data.cmd_le_gap_set_advertise_phy.primary_phy=primary_phy; gecko_cmd_msg->data.cmd_le_gap_set_advertise_phy.secondary_phy=secondary_phy; gecko_cmd_msg->header=((gecko_cmd_le_gap_set_advertise_phy_id+((3)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_le_gap_set_advertise_phy, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_le_gap_set_advertise_phy; } /** * * gecko_cmd_le_gap_set_advertise_configuration * * This command can be used to configure the type of advertising event and other advertising properties of the given advertising set. The command "le_gap_clear_advertise_configuration" can be used to clear the configurations set by this command. This setting will take effect on the next advertising enabling. * * @param handle Advertising set handle * @param configurations Advertising configuration flags to enable. This value can be a bitmask of multiple flags. Flags: * - 1 (Bit 0): Use legacy advertising PDUs. * - 2 (Bit 1): Omit advertiser's address from all PDUs (anonymous advertising). This flag is effective only in extended advertising. * - 4 (Bit 2): Use le_gap_non_resolvable address type. Advertising must be in non-connectable mode if this configuration is enabled. * - 8 (Bit 3): Include TX power in advertising packets. This flag is effective only in extended advertising. * Default value: 1 * * **/ static inline struct gecko_msg_le_gap_set_advertise_configuration_rsp_t* gecko_cmd_le_gap_set_advertise_configuration(uint8 handle,uint32 configurations) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; gecko_cmd_msg->data.cmd_le_gap_set_advertise_configuration.handle=handle; gecko_cmd_msg->data.cmd_le_gap_set_advertise_configuration.configurations=configurations; gecko_cmd_msg->header=((gecko_cmd_le_gap_set_advertise_configuration_id+((5)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_le_gap_set_advertise_configuration, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_le_gap_set_advertise_configuration; } /** * * gecko_cmd_le_gap_clear_advertise_configuration * * This command can be used to disable advertising configurations on the given advertising set. The command "le_gap_set_advertise_configuration" can be used to set configurations. This setting will take effect on the next advertising enabling. * * @param handle Advertising set handle * @param configurations Advertising configuration flags to disable. This value can be a bitmask of multiple flags. See "le_gap_set_advertise_configuration" for possible flags. * **/ static inline struct gecko_msg_le_gap_clear_advertise_configuration_rsp_t* gecko_cmd_le_gap_clear_advertise_configuration(uint8 handle,uint32 configurations) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; gecko_cmd_msg->data.cmd_le_gap_clear_advertise_configuration.handle=handle; gecko_cmd_msg->data.cmd_le_gap_clear_advertise_configuration.configurations=configurations; gecko_cmd_msg->header=((gecko_cmd_le_gap_clear_advertise_configuration_id+((5)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_le_gap_clear_advertise_configuration, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_le_gap_clear_advertise_configuration; } /** * * gecko_cmd_le_gap_start_advertising * * This command can be used to start the advertising of the given advertising set with specified discoverable and connectable modes. * The number of concurrent connectable advertisings is also limited by * MAX_CONNECTIONS configuration. For example, only one connectable * advertising can be enabled if the device has (MAX_CONNECTIONS - 1) * connections when this command is called. The limitation does not apply * to non-connectable advertising. * The default advertising configuration in the stack is set to using * legacy advertising PDUs on LE 1M PHY. The stack will automatically * select extended advertising PDUs if either of the followings has * occurred under the default configuration: * - The connectable mode is set to le_gap_connectable_non_scannable. * - The primary advertising PHY has been set to LE Coded PHY by command "le_gap_set_advertise_phy". * If currently set parameters can't be used then an error will be * returned. Specifically, this command fails with "Connection Limit * Exceeded" error if it may cause the number of connections exceeding * the configured MAX_CONNECTIONS value. It fails with "Invalid * Parameter" error if one of the following cases occur: * - Non-resolvable random address is used but the connectable mode is le_gap_connectable_scannable or le_gap_connectable_non_scannable. * - The connectable mode is le_gap_connectable_non_scannable, but using legacy advertising PDUs has been explicitly enabled with command "le_gap_set_advertise_configuration". * - The primary advertising PHY is LE Coded PHY but using legacy advertising PDUs has been explicitly enabled with command "le_gap_set_advertise_configuration". * - The connectable mode is le_gap_connectable_scannable but using extended advertising PDUs has been explicitly enabled or the primary advertising PHY has been set to LE Coded PHY. * If advertising will be enabled in user_data mode, * "le_gap_bt5_set_adv_data" should be used to set advertising and scan * response data before issuing this command. When the advertising is * enabled in other modes than user_data, the advertising and scan * response data is generated by the stack using the following procedure: * - Add a Flags field to advertising data. * - Add a TX power level field to advertising data if TX power service exists in the local GATT database. * - Add a Slave Connection Interval Range field to advertising data if the GAP peripheral preferred connection parameters characteristic exists in the local GATT database. * - Add a list of 16-bit Service UUIDs to advertising data if there are one or more 16-bit service UUIDs to advertise. The list is complete if all advertised 16-bit UUIDs are in advertising data; otherwise the list is incomplete. * - Add a list of 128-bit service UUIDs to advertising data if there are one or more 128-bit service UUIDs to advertise and there is still free space for this field. The list is complete if all advertised 128-bit UUIDs are in advertising data; otherwise the list is incomplete. Note that an advertising data packet can contain at most one 128-bit service UUID. * - Try to add the full local name to advertising data if device is not in privacy mode. In case the full local name does not fit into the remaining free space, the advertised name is a shortened version by cutting off the end if the free space has at least 6 bytes; Otherwise, the local name is added to scan response data. * Event "le_connection_opened" will be received when a remote device * opens a connection to the advertiser on this advertising set. * * * @param handle Advertising set handle * @param discover Discoverable mode * @param connect Connectable mode * * Events generated * * gecko_evt_le_gap_adv_timeout - Triggered when the number of advertising events set by this command has been done and advertising is stopped on the given advertising set. * gecko_evt_le_connection_opened - Triggered when a remote device opened a connection to the advertiser on the specified advertising set. * **/ static inline struct gecko_msg_le_gap_start_advertising_rsp_t* gecko_cmd_le_gap_start_advertising(uint8 handle,uint8 discover,uint8 connect) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; gecko_cmd_msg->data.cmd_le_gap_start_advertising.handle=handle; gecko_cmd_msg->data.cmd_le_gap_start_advertising.discover=discover; gecko_cmd_msg->data.cmd_le_gap_start_advertising.connect=connect; gecko_cmd_msg->header=((gecko_cmd_le_gap_start_advertising_id+((3)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_le_gap_start_advertising, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_le_gap_start_advertising; } /** * * gecko_cmd_le_gap_stop_advertising * * This command can be used to stop the advertising of the given advertising set. * * @param handle Advertising set handle * **/ static inline struct gecko_msg_le_gap_stop_advertising_rsp_t* gecko_cmd_le_gap_stop_advertising(uint8 handle) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; gecko_cmd_msg->data.cmd_le_gap_stop_advertising.handle=handle; gecko_cmd_msg->header=((gecko_cmd_le_gap_stop_advertising_id+((1)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_le_gap_stop_advertising, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_le_gap_stop_advertising; } /** * * gecko_cmd_le_gap_set_discovery_timing * * This command can be used to set the timing parameters of the specified PHYs. If the device is currently scanning for advertising devices the PHYs, new parameters will take effect when the scanning is restarted. * * @param phys The PHYs for which the parameters are set. * - 1: LE 1M PHY * - 4: LE Coded PHY * - 5: LE 1M PHY and LE Coded PHY * * @param scan_interval Scan interval. This is defined as the time interval from when the device started its last scan until it begins the subsequent scan, that is how often to scan * - Time = Value x 0.625 ms * - Range: 0x0004 to 0xFFFF * - Time Range: 2.5 ms to 40.96 s * Default value: 10 ms * There is a variable delay when switching channels at the end of each * scanning interval which is included in the scanning interval time * itself. During this switch time no advertising packets will be * received by the device. The switch time variation is dependent on use * case, for example in case of scanning while keeping active connections * the channel switch time might be longer than when only scanning * without any active connections. Increasing the scanning interval will * reduce the amount of time in which the device cannot receive * advertising packets as it will switch channels less often. * After every scan interval the scanner will change the frequency it * operates at. It will cycle through all the three advertising channels * in a round robin fashion. According to the specification all three * channels must be used by a scanner. * * @param scan_window Scan window. The duration of the scan. scan_window shall be less than or equal to scan_interval * - Time = Value x 0.625 ms * - Range: 0x0004 to 0xFFFF * - Time Range: 2.5 ms to 40.96 s * Default value: 10 ms Note that packet reception is aborted if it has been started before scan window ends. * **/ static inline struct gecko_msg_le_gap_set_discovery_timing_rsp_t* gecko_cmd_le_gap_set_discovery_timing(uint8 phys,uint16 scan_interval,uint16 scan_window) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; gecko_cmd_msg->data.cmd_le_gap_set_discovery_timing.phys=phys; gecko_cmd_msg->data.cmd_le_gap_set_discovery_timing.scan_interval=scan_interval; gecko_cmd_msg->data.cmd_le_gap_set_discovery_timing.scan_window=scan_window; gecko_cmd_msg->header=((gecko_cmd_le_gap_set_discovery_timing_id+((5)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_le_gap_set_discovery_timing, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_le_gap_set_discovery_timing; } /** * * gecko_cmd_le_gap_set_discovery_type * * This command can be used to set the scan type of the specified PHYs. If the device is currently scanning for advertising devices on the PHYs, new parameters will take effect when the scanning is restarted * * @param phys The PHYs for which the parameters are set. * - 1: LE 1M PHY * - 4: LE Coded PHY * - 5: LE 1M PHY and LE Coded PHY * * @param scan_type Scan type indicated by a flag. Values: * - 0: Passive scanning * - 1: Active scanning * - In passive scanning mode the device only listens to advertising packets and will not transmit any packet * - In active scanning mode the device will send out a scan request packet upon receiving advertising packet from a remote device and then it will listen to the scan response packet from remote device * Default value: 0 * **/ static inline struct gecko_msg_le_gap_set_discovery_type_rsp_t* gecko_cmd_le_gap_set_discovery_type(uint8 phys,uint8 scan_type) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; gecko_cmd_msg->data.cmd_le_gap_set_discovery_type.phys=phys; gecko_cmd_msg->data.cmd_le_gap_set_discovery_type.scan_type=scan_type; gecko_cmd_msg->header=((gecko_cmd_le_gap_set_discovery_type_id+((2)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_le_gap_set_discovery_type, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_le_gap_set_discovery_type; } /** * * gecko_cmd_le_gap_start_discovery * * This command can be used to start the GAP discovery procedure to scan * for advertising devices on the specified scanning PHY, that is to * perform a device discovery. To cancel an ongoing * discovery process use the "le_gap_end_procedure" command. * "Invalid Parameter" error will be returned if the scanning PHY value * is invalid or the device does not support the PHY. * * * @param scanning_phy The scanning PHY. Value: * - 1: LE 1M PHY * - 4: LE Coded PHY * * @param mode Bluetooth discovery Mode. For values see link * * Events generated * * gecko_evt_le_gap_scan_response - Every time an advertising packet is received, this event is triggered. The packets are not filtered in any way, so multiple events will be received for every advertising device in range. * **/ static inline struct gecko_msg_le_gap_start_discovery_rsp_t* gecko_cmd_le_gap_start_discovery(uint8 scanning_phy,uint8 mode) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; gecko_cmd_msg->data.cmd_le_gap_start_discovery.scanning_phy=scanning_phy; gecko_cmd_msg->data.cmd_le_gap_start_discovery.mode=mode; gecko_cmd_msg->header=((gecko_cmd_le_gap_start_discovery_id+((2)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_le_gap_start_discovery, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_le_gap_start_discovery; } /** * * gecko_cmd_le_gap_set_data_channel_classification * * This command can be used to specify a channel classification for data channels. This classification persists until overwritten with a subsequent command or until the system is reset. * * @param channel_map This parameter is 5 bytes and contains 37 1-bit fields.{br} The nth such field (in the range 0 to 36) contains the value for the link layer channel index n.{br} * - 0: Channel n is bad. * - 1: Channel n is unknown. * The most significant bits are reserved and shall be set to 0 for future use.{br} At least two channels shall be marked as unknown. * **/ static inline struct gecko_msg_le_gap_set_data_channel_classification_rsp_t* gecko_cmd_le_gap_set_data_channel_classification(uint8 channel_map_len, const uint8* channel_map_data) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; if ((uint16_t)channel_map_len > 256 - 1) { gecko_rsp_msg->data.rsp_le_gap_set_data_channel_classification.result = bg_err_command_too_long; return &gecko_rsp_msg->data.rsp_le_gap_set_data_channel_classification; } gecko_cmd_msg->data.cmd_le_gap_set_data_channel_classification.channel_map.len=channel_map_len; memcpy(gecko_cmd_msg->data.cmd_le_gap_set_data_channel_classification.channel_map.data,channel_map_data,channel_map_len); gecko_cmd_msg->header=((gecko_cmd_le_gap_set_data_channel_classification_id+((1+channel_map_len)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_le_gap_set_data_channel_classification, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_le_gap_set_data_channel_classification; } /** * * gecko_cmd_le_gap_connect * * This command can be used to connect an advertising device with the * specified initiating PHY. The Bluetooth stack will * enter a state where it continuously scans for the * connectable advertising packets from the remote device * which matches the Bluetooth address given as a * parameter. Scan parameters set in * "le_gap_set_discovery_timing" are used in this operation. * Upon receiving the advertising packet, the module will * send a connection request packet to the target device to * initiate a Bluetooth connection. To cancel an ongoing * connection process use the "le_connection_close" command with the * handle received in the response from this command. * A connection is opened in no-security mode. If the GATT * client needs to read or write the attributes on GATT server * requiring encryption or authentication, it must first encrypt * the connection using an appropriate authentication method. * If a connection cannot be established at all for some reason (for * example, the remote device has gone out of range, has * entered into deep sleep, or is not advertising), the * stack will try to connect forever. In this case the * application will not get any event related to the connection request. * To recover from this situation, application can implement a timeout * and call "le_connection_close" to cancel the * connection request. * This command fails with "Connection Limit Exceeded" error if * the number of connections attempted to be opened exceeds the * configured MAX_CONNECTIONS value. * This command fails with "Invalid Parameter" error if the initiating * PHY value is invalid or the device does not support the PHY. * Later calls of this command have to wait for the ongoing command to complete. A received event "le_connection_opened" indicates connection opened successfully and a received event "le_connection_closed" indicates connection failures have occurred. * * @param address Address of the device to connect to * @param address_type Address type of the device to connect to * @param initiating_phy The initiating PHY. Value: * - 1: LE 1M PHY * - 4: LE Coded PHY * * * Events generated * * gecko_evt_le_connection_opened - This event is triggered after the connection has been opened, and indicates whether the devices are already bonded and what is the role of the Bluetooth device (Slave or Master). * gecko_evt_le_connection_parameters - This event indicates the connection parameters and security mode of the connection. * **/ static inline struct gecko_msg_le_gap_connect_rsp_t* gecko_cmd_le_gap_connect(bd_addr address,uint8 address_type,uint8 initiating_phy) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; memcpy(&gecko_cmd_msg->data.cmd_le_gap_connect.address,&address,sizeof(bd_addr)); gecko_cmd_msg->data.cmd_le_gap_connect.address_type=address_type; gecko_cmd_msg->data.cmd_le_gap_connect.initiating_phy=initiating_phy; gecko_cmd_msg->header=((gecko_cmd_le_gap_connect_id+((8)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_le_gap_connect, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_le_gap_connect; } /** * * gecko_cmd_le_gap_set_advertise_tx_power * * This command can be used to limit the maximum advertising TX power on the given advertising set. If the value goes over the global value that has been set using "system_set_tx_power" command, the global value will be the maximum limit. The maximum TX power of legacy advertising is further constrainted to not go over +10 dBm. Extended advertising TX power can be +10 dBm and over if Adaptive Frequency Hopping has been enabled. * This setting will take effect on the next advertising enabling. * By default, maximum advertising TX power is limited by the global * value. * * * @param handle Advertising set handle * @param power TX power in 0.1dBm steps, for example the value of 10 is 1dBm and 55 is 5.5dBm * **/ static inline struct gecko_msg_le_gap_set_advertise_tx_power_rsp_t* gecko_cmd_le_gap_set_advertise_tx_power(uint8 handle,int16 power) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; gecko_cmd_msg->data.cmd_le_gap_set_advertise_tx_power.handle=handle; gecko_cmd_msg->data.cmd_le_gap_set_advertise_tx_power.power=power; gecko_cmd_msg->header=((gecko_cmd_le_gap_set_advertise_tx_power_id+((3)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_le_gap_set_advertise_tx_power, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_le_gap_set_advertise_tx_power; } /** * * gecko_cmd_le_gap_set_discovery_extended_scan_response * * This command can be used to enable and disable the extended scan response event. When the extended scan response event is enabled, it replaces "le_gap_scan_response", that is, the stack will generate either "le_gap_extended_scan_response" or "le_gap_scan_response", but not both at a time. * * @param enable Values: * - 0: Disable extended scan response event * - 1: Enable extended scan response event * * **/ static inline struct gecko_msg_le_gap_set_discovery_extended_scan_response_rsp_t* gecko_cmd_le_gap_set_discovery_extended_scan_response(uint8 enable) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; gecko_cmd_msg->data.cmd_le_gap_set_discovery_extended_scan_response.enable=enable; gecko_cmd_msg->header=((gecko_cmd_le_gap_set_discovery_extended_scan_response_id+((1)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_le_gap_set_discovery_extended_scan_response, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_le_gap_set_discovery_extended_scan_response; } /** * * gecko_cmd_le_gap_start_periodic_advertising * * This command can be used to start periodic advertising on the given advertising set. The stack will enable the advertising set automatically if the set has not been enabled and the set can advertise using extended advertising PDUs. * "Invalid Parameter" error will be returned if the application has * configured to use legacy advertising PDUs or anonymous * advertising, or advertising set has been enabled using * legacy advertising PDUs. * * * @param handle Advertising set handle * @param interval_min Minimum periodic advertising interval. Value in units of 1.25 ms * - Range: 0x06 to 0xFFFF * - Time range: 7.5 ms to 81.92 s * Default value: 100 ms * @param interval_max Maximum periodic advertising interval. Value in units of 1.25 ms * - Range: 0x06 to 0xFFFF * - Time range: 7.5 ms to 81.92 s * - Note: interval_max should be bigger than interval_min * Default value: 200 ms * @param flags Periodic advertising configurations. Bitmask of followings: * - Bit 0: Include TX power in advertising PDU * * **/ static inline struct gecko_msg_le_gap_start_periodic_advertising_rsp_t* gecko_cmd_le_gap_start_periodic_advertising(uint8 handle,uint16 interval_min,uint16 interval_max,uint32 flags) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; gecko_cmd_msg->data.cmd_le_gap_start_periodic_advertising.handle=handle; gecko_cmd_msg->data.cmd_le_gap_start_periodic_advertising.interval_min=interval_min; gecko_cmd_msg->data.cmd_le_gap_start_periodic_advertising.interval_max=interval_max; gecko_cmd_msg->data.cmd_le_gap_start_periodic_advertising.flags=flags; gecko_cmd_msg->header=((gecko_cmd_le_gap_start_periodic_advertising_id+((9)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_le_gap_start_periodic_advertising, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_le_gap_start_periodic_advertising; } /** * * gecko_cmd_le_gap_stop_periodic_advertising * * This command can be used to stop the periodic advertising on the given advertising set. * This command does not affect the enable state of the advertising set. * * * @param handle Advertising set handle * **/ static inline struct gecko_msg_le_gap_stop_periodic_advertising_rsp_t* gecko_cmd_le_gap_stop_periodic_advertising(uint8 handle) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; gecko_cmd_msg->data.cmd_le_gap_stop_periodic_advertising.handle=handle; gecko_cmd_msg->header=((gecko_cmd_le_gap_stop_periodic_advertising_id+((1)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_le_gap_stop_periodic_advertising, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_le_gap_stop_periodic_advertising; } /** * * gecko_cmd_le_gap_enable_whitelisting * * This command is used to enable whitelisting. To add devices to the whitelist either bond with the device or add it manually with "sm_add_to_whitelist" * * @param enable 1 enable, 0 disable whitelisting. * **/ static inline struct gecko_msg_le_gap_enable_whitelisting_rsp_t* gecko_cmd_le_gap_enable_whitelisting(uint8 enable) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; gecko_cmd_msg->data.cmd_le_gap_enable_whitelisting.enable=enable; gecko_cmd_msg->header=((gecko_cmd_le_gap_enable_whitelisting_id+((1)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_le_gap_enable_whitelisting, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_le_gap_enable_whitelisting; } /** * * gecko_cmd_sync_open * * This command can be used to establish a synchronization with periodic advertising from the specified advertiser and begin receiving periodic advertising packets. * * @param adv_sid Advertising set identifier * @param skip The number of periodic advertising packets that can be skipped after a successful receive. Range: 0x0000 to 0x01F3 * @param timeout Synchronization timeout for the periodic advertising. Unit: 10 ms. * - Range: 0x06 to 0xFFFF * - Unit: 10 ms * - Time range: 100 ms ms to 163.84 s * * @param address Address of the advertiser * @param address_type Advertiser address type. Values: * - 0: Public address * - 1: Random address * * * Events generated * * gecko_evt_sync_opened - This event is triggered after the synchronization has been established. * gecko_evt_sync_data - This event indicates a periodic advertising packet has been received. * **/ static inline struct gecko_msg_sync_open_rsp_t* gecko_cmd_sync_open(uint8 adv_sid,uint16 skip,uint16 timeout,bd_addr address,uint8 address_type) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; gecko_cmd_msg->data.cmd_sync_open.adv_sid=adv_sid; gecko_cmd_msg->data.cmd_sync_open.skip=skip; gecko_cmd_msg->data.cmd_sync_open.timeout=timeout; memcpy(&gecko_cmd_msg->data.cmd_sync_open.address,&address,sizeof(bd_addr)); gecko_cmd_msg->data.cmd_sync_open.address_type=address_type; gecko_cmd_msg->header=((gecko_cmd_sync_open_id+((12)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_sync_open, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_sync_open; } /** * * gecko_cmd_sync_close * * This command can be used to close a synchronization with periodic advertising or cancel an ongoing synchronization establishment procedure. * * @param sync Periodic advertising synchronization handle * * Events generated * * gecko_evt_sync_closed - This event is triggered after the synchronization has been closed. * **/ static inline struct gecko_msg_sync_close_rsp_t* gecko_cmd_sync_close(uint8 sync) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; gecko_cmd_msg->data.cmd_sync_close.sync=sync; gecko_cmd_msg->header=((gecko_cmd_sync_close_id+((1)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_sync_close, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_sync_close; } /** * * gecko_cmd_le_connection_set_parameters * * This command can be used to request a change in the connection parameters of a Bluetooth connection. * * @param connection Connection Handle * @param min_interval Minimum value for the connection event interval. This must be set be less than or equal to max_interval. * - Time = Value x 1.25 ms * - Range: 0x0006 to 0x0c80 * - Time Range: 7.5 ms to 4 s * * @param max_interval Maximum value for the connection event interval. This must be set greater than or equal to min_interval. * - Time = Value x 1.25 ms * - Range: 0x0006 to 0x0c80 * - Time Range: 7.5 ms to 4 s * * @param latency Slave latency. This parameter defines how many connection intervals the slave can skip if it has no data to send * - Range: 0x0000 to 0x01f4 * Use 0x0000 for default value * @param timeout Supervision timeout. The supervision timeout defines for how long the connection is maintained despite the devices being unable to communicate at the currently configured connection intervals. * - Range: 0x000a to 0x0c80 * - Time = Value x 10 ms * - Time Range: 100 ms to 32 s * - The value in milliseconds must be larger than (1 + latency) * max_interval * 2, where max_interval is given in milliseconds * It is recommended that the supervision timeout is set at a value which allows communication attempts over at least a few connection intervals. * * Events generated * * gecko_evt_le_connection_parameters - This event is triggered after new connection parameters has been applied on the connection. * **/ static inline struct gecko_msg_le_connection_set_parameters_rsp_t* gecko_cmd_le_connection_set_parameters(uint8 connection,uint16 min_interval,uint16 max_interval,uint16 latency,uint16 timeout) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; gecko_cmd_msg->data.cmd_le_connection_set_parameters.connection=connection; gecko_cmd_msg->data.cmd_le_connection_set_parameters.min_interval=min_interval; gecko_cmd_msg->data.cmd_le_connection_set_parameters.max_interval=max_interval; gecko_cmd_msg->data.cmd_le_connection_set_parameters.latency=latency; gecko_cmd_msg->data.cmd_le_connection_set_parameters.timeout=timeout; gecko_cmd_msg->header=((gecko_cmd_le_connection_set_parameters_id+((9)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_le_connection_set_parameters, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_le_connection_set_parameters; } /** * * gecko_cmd_le_connection_get_rssi * * This command can be used to get the latest RSSI value of a Bluetooth connection. * * @param connection Connection handle * * Events generated * * gecko_evt_le_connection_rssi - Triggered when this command has completed. * **/ static inline struct gecko_msg_le_connection_get_rssi_rsp_t* gecko_cmd_le_connection_get_rssi(uint8 connection) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; gecko_cmd_msg->data.cmd_le_connection_get_rssi.connection=connection; gecko_cmd_msg->header=((gecko_cmd_le_connection_get_rssi_id+((1)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_le_connection_get_rssi, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_le_connection_get_rssi; } /** * * gecko_cmd_le_connection_disable_slave_latency * * This command temporarily enables or disables slave latency. Used only when Bluetooth device is in slave role. * * @param connection Connection Handle * @param disable 0 enable, 1 disable slave latency * **/ static inline struct gecko_msg_le_connection_disable_slave_latency_rsp_t* gecko_cmd_le_connection_disable_slave_latency(uint8 connection,uint8 disable) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; gecko_cmd_msg->data.cmd_le_connection_disable_slave_latency.connection=connection; gecko_cmd_msg->data.cmd_le_connection_disable_slave_latency.disable=disable; gecko_cmd_msg->header=((gecko_cmd_le_connection_disable_slave_latency_id+((2)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_le_connection_disable_slave_latency, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_le_connection_disable_slave_latency; } /** * * gecko_cmd_le_connection_set_phy * * This command can be used to set preferred PHYs for connection. Preferred PHYs are connection specific. Event "le_connection_phy_status" is received when PHY update procedure has been completed. Other than preferred PHY can also be set if remote device does not accept any of the preferred PHYs. * NOTE: 2 Mbit and Coded PHYs are not supported by all devices. * * * @param connection * @param phy Preferred PHYs for connection. This parameter is bitfield and multiple PHYs can be preferred by setting multiple bits. * - 0x01: 1 Mbit PHY * - 0x02: 2 Mbit PHY * - 0x04: 125 kbit Coded PHY (S=8) * - 0x08: 500 kbit Coded PHY (S=2) * * * Events generated * * gecko_evt_le_connection_phy_status - * **/ static inline struct gecko_msg_le_connection_set_phy_rsp_t* gecko_cmd_le_connection_set_phy(uint8 connection,uint8 phy) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; gecko_cmd_msg->data.cmd_le_connection_set_phy.connection=connection; gecko_cmd_msg->data.cmd_le_connection_set_phy.phy=phy; gecko_cmd_msg->header=((gecko_cmd_le_connection_set_phy_id+((2)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_le_connection_set_phy, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_le_connection_set_phy; } /** * * gecko_cmd_le_connection_close * * This command can be used to close a Bluetooth connection or cancel an ongoing connection establishment process. The parameter is a connection handle which is reported in "le_connection_opened" event or le_gap_connect response. * * @param connection Handle of the connection to be closed * * Events generated * * gecko_evt_le_connection_closed - * **/ static inline struct gecko_msg_le_connection_close_rsp_t* gecko_cmd_le_connection_close(uint8 connection) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; gecko_cmd_msg->data.cmd_le_connection_close.connection=connection; gecko_cmd_msg->header=((gecko_cmd_le_connection_close_id+((1)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_le_connection_close, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_le_connection_close; } /** * * gecko_cmd_gatt_set_max_mtu * * This command can be used to set the maximum size of ATT Message Transfer Units (MTU). If the given value is too large according to the maximum BGAPI payload size, the system will select the maximal possible value as the maximum ATT_MTU. If maximum ATT_MTU is larger than 23, MTU is exchanged automatically after a Bluetooth connection has been established. * * @param max_mtu Maximum size of Message Transfer Units (MTU) allowed * - Range: 23 to 250 * Default: 247 * **/ static inline struct gecko_msg_gatt_set_max_mtu_rsp_t* gecko_cmd_gatt_set_max_mtu(uint16 max_mtu) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; gecko_cmd_msg->data.cmd_gatt_set_max_mtu.max_mtu=max_mtu; gecko_cmd_msg->header=((gecko_cmd_gatt_set_max_mtu_id+((2)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_gatt_set_max_mtu, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_gatt_set_max_mtu; } /** * * gecko_cmd_gatt_discover_primary_services * * This command can be used to discover all the primary services of a remote GATT database. This command generates a unique gatt_service event for every discovered primary service. Received "gatt_procedure_completed" event indicates that this GATT procedure has successfully completed or failed with error. * * @param connection * * Events generated * * gecko_evt_gatt_service - Discovered service from remote GATT database * gecko_evt_gatt_procedure_completed - Procedure has been successfully completed or failed with error. * **/ static inline struct gecko_msg_gatt_discover_primary_services_rsp_t* gecko_cmd_gatt_discover_primary_services(uint8 connection) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; gecko_cmd_msg->data.cmd_gatt_discover_primary_services.connection=connection; gecko_cmd_msg->header=((gecko_cmd_gatt_discover_primary_services_id+((1)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_gatt_discover_primary_services, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_gatt_discover_primary_services; } /** * * gecko_cmd_gatt_discover_primary_services_by_uuid * * This command can be used to discover primary services with the specified UUID in a remote GATT database. This command generates unique gatt_service event for every discovered primary service. Received "gatt_procedure_completed" event indicates that this GATT procedure has succesfully completed or failed with error. * * @param connection * @param uuid Service UUID * * Events generated * * gecko_evt_gatt_service - Discovered service from remote GATT database. * gecko_evt_gatt_procedure_completed - Procedure has been successfully completed or failed with error. * **/ static inline struct gecko_msg_gatt_discover_primary_services_by_uuid_rsp_t* gecko_cmd_gatt_discover_primary_services_by_uuid(uint8 connection,uint8 uuid_len, const uint8* uuid_data) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; if ((uint16_t)uuid_len > 256 - 2) { gecko_rsp_msg->data.rsp_gatt_discover_primary_services_by_uuid.result = bg_err_command_too_long; return &gecko_rsp_msg->data.rsp_gatt_discover_primary_services_by_uuid; } gecko_cmd_msg->data.cmd_gatt_discover_primary_services_by_uuid.connection=connection; gecko_cmd_msg->data.cmd_gatt_discover_primary_services_by_uuid.uuid.len=uuid_len; memcpy(gecko_cmd_msg->data.cmd_gatt_discover_primary_services_by_uuid.uuid.data,uuid_data,uuid_len); gecko_cmd_msg->header=((gecko_cmd_gatt_discover_primary_services_by_uuid_id+((2+uuid_len)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_gatt_discover_primary_services_by_uuid, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_gatt_discover_primary_services_by_uuid; } /** * * gecko_cmd_gatt_discover_characteristics * * This command can be used to discover all characteristics of the defined GATT service from a remote GATT database. This command generates a unique gatt_characteristic event for every discovered characteristic. Received "gatt_procedure_completed" event indicates that this GATT procedure has succesfully completed or failed with error. * * @param connection * @param service * * Events generated * * gecko_evt_gatt_characteristic - Discovered characteristic from remote GATT database. * gecko_evt_gatt_procedure_completed - Procedure has been successfully completed or failed with error. * **/ static inline struct gecko_msg_gatt_discover_characteristics_rsp_t* gecko_cmd_gatt_discover_characteristics(uint8 connection,uint32 service) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; gecko_cmd_msg->data.cmd_gatt_discover_characteristics.connection=connection; gecko_cmd_msg->data.cmd_gatt_discover_characteristics.service=service; gecko_cmd_msg->header=((gecko_cmd_gatt_discover_characteristics_id+((5)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_gatt_discover_characteristics, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_gatt_discover_characteristics; } /** * * gecko_cmd_gatt_discover_characteristics_by_uuid * * This command can be used to discover all the characteristics of the specified GATT service in a remote GATT database having the specified UUID. This command generates a unique gatt_characteristic event for every discovered characteristic having the specified UUID. Received "gatt_procedure_completed" event indicates that this GATT procedure has successfully completed or failed with error. * * @param connection * @param service * @param uuid Characteristic UUID * * Events generated * * gecko_evt_gatt_characteristic - Discovered characteristic from remote GATT database. * gecko_evt_gatt_procedure_completed - Procedure has been successfully completed or failed with error. * **/ static inline struct gecko_msg_gatt_discover_characteristics_by_uuid_rsp_t* gecko_cmd_gatt_discover_characteristics_by_uuid(uint8 connection,uint32 service,uint8 uuid_len, const uint8* uuid_data) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; if ((uint16_t)uuid_len > 256 - 6) { gecko_rsp_msg->data.rsp_gatt_discover_characteristics_by_uuid.result = bg_err_command_too_long; return &gecko_rsp_msg->data.rsp_gatt_discover_characteristics_by_uuid; } gecko_cmd_msg->data.cmd_gatt_discover_characteristics_by_uuid.connection=connection; gecko_cmd_msg->data.cmd_gatt_discover_characteristics_by_uuid.service=service; gecko_cmd_msg->data.cmd_gatt_discover_characteristics_by_uuid.uuid.len=uuid_len; memcpy(gecko_cmd_msg->data.cmd_gatt_discover_characteristics_by_uuid.uuid.data,uuid_data,uuid_len); gecko_cmd_msg->header=((gecko_cmd_gatt_discover_characteristics_by_uuid_id+((6+uuid_len)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_gatt_discover_characteristics_by_uuid, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_gatt_discover_characteristics_by_uuid; } /** * * gecko_cmd_gatt_set_characteristic_notification * * This command can be used to enable or disable the notifications and indications being sent from a remote GATT server. This procedure discovers a characteristic client configuration descriptor and writes the related configuration flags to a remote GATT database. A received "gatt_procedure_completed" event indicates that this GATT procedure has successfully completed or that is has failed with an error. * * @param connection * @param characteristic * @param flags Characteristic client configuration flags * * Events generated * * gecko_evt_gatt_procedure_completed - Procedure has been successfully completed or failed with error. * gecko_evt_gatt_characteristic_value - If an indication or notification has been enabled for a characteristic, this event is triggered whenever an indication or notification is sent by the remote GATT server. The triggering conditions on the GATT server side are defined by an upper level, for example by a profile; so it is possible that no values are ever received, or that it may take time, depending on how the server is configured. * **/ static inline struct gecko_msg_gatt_set_characteristic_notification_rsp_t* gecko_cmd_gatt_set_characteristic_notification(uint8 connection,uint16 characteristic,uint8 flags) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; gecko_cmd_msg->data.cmd_gatt_set_characteristic_notification.connection=connection; gecko_cmd_msg->data.cmd_gatt_set_characteristic_notification.characteristic=characteristic; gecko_cmd_msg->data.cmd_gatt_set_characteristic_notification.flags=flags; gecko_cmd_msg->header=((gecko_cmd_gatt_set_characteristic_notification_id+((4)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_gatt_set_characteristic_notification, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_gatt_set_characteristic_notification; } /** * * gecko_cmd_gatt_discover_descriptors * * This command can be used to discover all the descriptors of the specified remote GATT characteristics in a remote GATT database. This command generates a unique gatt_descriptor event for every discovered descriptor. Received "gatt_procedure_completed" event indicates that this GATT procedure has succesfully completed or failed with error. * * @param connection * @param characteristic * * Events generated * * gecko_evt_gatt_descriptor - Discovered descriptor from remote GATT database. * gecko_evt_gatt_procedure_completed - Procedure has been successfully completed or failed with error. * **/ static inline struct gecko_msg_gatt_discover_descriptors_rsp_t* gecko_cmd_gatt_discover_descriptors(uint8 connection,uint16 characteristic) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; gecko_cmd_msg->data.cmd_gatt_discover_descriptors.connection=connection; gecko_cmd_msg->data.cmd_gatt_discover_descriptors.characteristic=characteristic; gecko_cmd_msg->header=((gecko_cmd_gatt_discover_descriptors_id+((3)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_gatt_discover_descriptors, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_gatt_discover_descriptors; } /** * * gecko_cmd_gatt_read_characteristic_value * * This command can be used to read the value of a characteristic from a remote GATT database. A single "gatt_characteristic_value" event is generated if the characteristic value fits in one ATT PDU. Otherwise more than one " gatt_characteristic_value" events are generated because the firmware will automatically use the "read long" GATT procedure. A received "gatt_procedure_completed" event indicates that all data has been read successfully or that an error response has been received. * Note that the GATT client does not verify if the requested atrribute * is a characteristic value. Thus before calling this * command the application should make sure the attribute handle is for a * characteristic value in some means, for example, by * performing characteristic discovery. * * * @param connection * @param characteristic * * Events generated * * gecko_evt_gatt_characteristic_value - This event contains the data belonging to a characteristic sent by the GATT Server. * gecko_evt_gatt_procedure_completed - Procedure has been successfully completed or failed with error. * **/ static inline struct gecko_msg_gatt_read_characteristic_value_rsp_t* gecko_cmd_gatt_read_characteristic_value(uint8 connection,uint16 characteristic) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; gecko_cmd_msg->data.cmd_gatt_read_characteristic_value.connection=connection; gecko_cmd_msg->data.cmd_gatt_read_characteristic_value.characteristic=characteristic; gecko_cmd_msg->header=((gecko_cmd_gatt_read_characteristic_value_id+((3)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_gatt_read_characteristic_value, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_gatt_read_characteristic_value; } /** * * gecko_cmd_gatt_read_characteristic_value_by_uuid * * This command can be used to read the characteristic value of a service from a remote GATT database by giving the UUID of the characteristic and the handle of the service containing this characteristic. A single "gatt_characteristic_value" event is generated if the characteristic value fits in one ATT PDU. Otherwise more than one " gatt_characteristic_value" events are generated because the firmware will automatically use the "read long" GATT procedure. A received "gatt_procedure_completed" event indicates that all data has been read successfully or that an error response has been received. * * @param connection * @param service * @param uuid Characteristic UUID * * Events generated * * gecko_evt_gatt_characteristic_value - This event contains the data belonging to a characteristic sent by the GATT Server. * gecko_evt_gatt_procedure_completed - Procedure has been successfully completed or failed with error. * **/ static inline struct gecko_msg_gatt_read_characteristic_value_by_uuid_rsp_t* gecko_cmd_gatt_read_characteristic_value_by_uuid(uint8 connection,uint32 service,uint8 uuid_len, const uint8* uuid_data) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; if ((uint16_t)uuid_len > 256 - 6) { gecko_rsp_msg->data.rsp_gatt_read_characteristic_value_by_uuid.result = bg_err_command_too_long; return &gecko_rsp_msg->data.rsp_gatt_read_characteristic_value_by_uuid; } gecko_cmd_msg->data.cmd_gatt_read_characteristic_value_by_uuid.connection=connection; gecko_cmd_msg->data.cmd_gatt_read_characteristic_value_by_uuid.service=service; gecko_cmd_msg->data.cmd_gatt_read_characteristic_value_by_uuid.uuid.len=uuid_len; memcpy(gecko_cmd_msg->data.cmd_gatt_read_characteristic_value_by_uuid.uuid.data,uuid_data,uuid_len); gecko_cmd_msg->header=((gecko_cmd_gatt_read_characteristic_value_by_uuid_id+((6+uuid_len)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_gatt_read_characteristic_value_by_uuid, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_gatt_read_characteristic_value_by_uuid; } /** * * gecko_cmd_gatt_write_characteristic_value * * This command can be used to write the value of a characteristic in a remote GATT database. If the given value does not fit in one ATT PDU, "write long" GATT procedure is used automatically. Received "gatt_procedure_completed" event indicates that all data has been written successfully or that an error response has been received. * * @param connection * @param characteristic * @param value Characteristic value * * Events generated * * gecko_evt_gatt_procedure_completed - Procedure has been successfully completed or failed with error. * **/ static inline struct gecko_msg_gatt_write_characteristic_value_rsp_t* gecko_cmd_gatt_write_characteristic_value(uint8 connection,uint16 characteristic,uint8 value_len, const uint8* value_data) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; if ((uint16_t)value_len > 256 - 4) { gecko_rsp_msg->data.rsp_gatt_write_characteristic_value.result = bg_err_command_too_long; return &gecko_rsp_msg->data.rsp_gatt_write_characteristic_value; } gecko_cmd_msg->data.cmd_gatt_write_characteristic_value.connection=connection; gecko_cmd_msg->data.cmd_gatt_write_characteristic_value.characteristic=characteristic; gecko_cmd_msg->data.cmd_gatt_write_characteristic_value.value.len=value_len; memcpy(gecko_cmd_msg->data.cmd_gatt_write_characteristic_value.value.data,value_data,value_len); gecko_cmd_msg->header=((gecko_cmd_gatt_write_characteristic_value_id+((4+value_len)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_gatt_write_characteristic_value, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_gatt_write_characteristic_value; } /** * * gecko_cmd_gatt_write_characteristic_value_without_response * * This command can be used to write the value of a characteristic in a remote GATT server. This command does not generate any event. All failures on the server are ignored silently. For example, if an error is generated in the remote GATT server and the given value is not written into database no error message will be reported to the local GATT client. Note that this command cannot be used to write long values. At most ATT_MTU - 3 amount of data can be sent once. * * @param connection * @param characteristic * @param value Characteristic value * **/ static inline struct gecko_msg_gatt_write_characteristic_value_without_response_rsp_t* gecko_cmd_gatt_write_characteristic_value_without_response(uint8 connection,uint16 characteristic,uint8 value_len, const uint8* value_data) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; if ((uint16_t)value_len > 256 - 4) { gecko_rsp_msg->data.rsp_gatt_write_characteristic_value_without_response.result = bg_err_command_too_long; return &gecko_rsp_msg->data.rsp_gatt_write_characteristic_value_without_response; } gecko_cmd_msg->data.cmd_gatt_write_characteristic_value_without_response.connection=connection; gecko_cmd_msg->data.cmd_gatt_write_characteristic_value_without_response.characteristic=characteristic; gecko_cmd_msg->data.cmd_gatt_write_characteristic_value_without_response.value.len=value_len; memcpy(gecko_cmd_msg->data.cmd_gatt_write_characteristic_value_without_response.value.data,value_data,value_len); gecko_cmd_msg->header=((gecko_cmd_gatt_write_characteristic_value_without_response_id+((4+value_len)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_gatt_write_characteristic_value_without_response, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_gatt_write_characteristic_value_without_response; } /** * * gecko_cmd_gatt_prepare_characteristic_value_write * * This command can be used to add a characteristic value to the write * queue of a remote GATT server. This command can be used * in cases where very long attributes need to be written, or a set of * values needs to be written atomically. At most ATT_MTU - 5 amount of * data can be sent once. Writes are executed or cancelled with the * "execute_characteristic_value_write" command. Whether the * writes succeeded or not are indicated in the response of the * "execute_characteristic_value_write" command. * In all cases where the amount of data to transfer fits into the BGAPI * payload the command "gatt_write_characteristic_value" is * recommended for writing long values since it transparently * performs the prepare_write and execute_write commands. * * * @param connection * @param characteristic * @param offset Offset of the characteristic value * @param value Value to write into the specified characteristic of the remote GATT database * * Events generated * * gecko_evt_gatt_procedure_completed - Procedure has been successfully completed or failed with error. * **/ static inline struct gecko_msg_gatt_prepare_characteristic_value_write_rsp_t* gecko_cmd_gatt_prepare_characteristic_value_write(uint8 connection,uint16 characteristic,uint16 offset,uint8 value_len, const uint8* value_data) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; if ((uint16_t)value_len > 256 - 6) { gecko_rsp_msg->data.rsp_gatt_prepare_characteristic_value_write.result = bg_err_command_too_long; return &gecko_rsp_msg->data.rsp_gatt_prepare_characteristic_value_write; } gecko_cmd_msg->data.cmd_gatt_prepare_characteristic_value_write.connection=connection; gecko_cmd_msg->data.cmd_gatt_prepare_characteristic_value_write.characteristic=characteristic; gecko_cmd_msg->data.cmd_gatt_prepare_characteristic_value_write.offset=offset; gecko_cmd_msg->data.cmd_gatt_prepare_characteristic_value_write.value.len=value_len; memcpy(gecko_cmd_msg->data.cmd_gatt_prepare_characteristic_value_write.value.data,value_data,value_len); gecko_cmd_msg->header=((gecko_cmd_gatt_prepare_characteristic_value_write_id+((6+value_len)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_gatt_prepare_characteristic_value_write, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_gatt_prepare_characteristic_value_write; } /** * * gecko_cmd_gatt_execute_characteristic_value_write * * This command can be used to commit or cancel previously queued writes to a long characteristic of a remote GATT server. Writes are sent to queue with "prepare_characteristic_value_write" command. Content, offset and length of queued values are validated by this procedure. A received "gatt_procedure_completed" event indicates that all data has been written successfully or that an error response has been received. * * @param connection * @param flags * * Events generated * * gecko_evt_gatt_procedure_completed - Procedure has been successfully completed or failed with error. * **/ static inline struct gecko_msg_gatt_execute_characteristic_value_write_rsp_t* gecko_cmd_gatt_execute_characteristic_value_write(uint8 connection,uint8 flags) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; gecko_cmd_msg->data.cmd_gatt_execute_characteristic_value_write.connection=connection; gecko_cmd_msg->data.cmd_gatt_execute_characteristic_value_write.flags=flags; gecko_cmd_msg->header=((gecko_cmd_gatt_execute_characteristic_value_write_id+((2)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_gatt_execute_characteristic_value_write, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_gatt_execute_characteristic_value_write; } /** * * gecko_cmd_gatt_send_characteristic_confirmation * * This command must be used to send a characteristic confirmation to a remote GATT server after receiving an indication. The "gatt_characteristic_value_event" carries the att_opcode containing handle_value_indication (0x1d) which reveals that an indication has been received and this must be confirmed with this command. Confirmation needs to be sent within 30 seconds, otherwise the GATT transactions between the client and the server are discontinued. * * @param connection * **/ static inline struct gecko_msg_gatt_send_characteristic_confirmation_rsp_t* gecko_cmd_gatt_send_characteristic_confirmation(uint8 connection) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; gecko_cmd_msg->data.cmd_gatt_send_characteristic_confirmation.connection=connection; gecko_cmd_msg->header=((gecko_cmd_gatt_send_characteristic_confirmation_id+((1)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_gatt_send_characteristic_confirmation, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_gatt_send_characteristic_confirmation; } /** * * gecko_cmd_gatt_read_descriptor_value * * This command can be used to read the descriptor value of a characteristic in a remote GATT database. A single " gatt_descriptor_value" event is generated if the descriptor value fits in one ATT PDU. Otherwise more than one "gatt_descriptor_value" events are generated because the firmware will automatically use the "read long" GATT procedure. A received "gatt_procedure_completed" event indicates that all data has been read successfully or that an error response has been received. * * @param connection * @param descriptor * * Events generated * * gecko_evt_gatt_descriptor_value - Descriptor value received from the remote GATT server. * gecko_evt_gatt_procedure_completed - Procedure has been successfully completed or failed with error. * **/ static inline struct gecko_msg_gatt_read_descriptor_value_rsp_t* gecko_cmd_gatt_read_descriptor_value(uint8 connection,uint16 descriptor) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; gecko_cmd_msg->data.cmd_gatt_read_descriptor_value.connection=connection; gecko_cmd_msg->data.cmd_gatt_read_descriptor_value.descriptor=descriptor; gecko_cmd_msg->header=((gecko_cmd_gatt_read_descriptor_value_id+((3)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_gatt_read_descriptor_value, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_gatt_read_descriptor_value; } /** * * gecko_cmd_gatt_write_descriptor_value * * This command can be used to write the value of a characteristic descriptor in a remote GATT database. If the given value does not fit in one ATT PDU, "write long" GATT procedure is used automatically. Received "gatt_procedure_completed" event indicates that all data has been written succesfully or that an error response has been received. * * @param connection * @param descriptor * @param value Descriptor value * * Events generated * * gecko_evt_gatt_procedure_completed - Procedure has been successfully completed or failed with error. * **/ static inline struct gecko_msg_gatt_write_descriptor_value_rsp_t* gecko_cmd_gatt_write_descriptor_value(uint8 connection,uint16 descriptor,uint8 value_len, const uint8* value_data) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; if ((uint16_t)value_len > 256 - 4) { gecko_rsp_msg->data.rsp_gatt_write_descriptor_value.result = bg_err_command_too_long; return &gecko_rsp_msg->data.rsp_gatt_write_descriptor_value; } gecko_cmd_msg->data.cmd_gatt_write_descriptor_value.connection=connection; gecko_cmd_msg->data.cmd_gatt_write_descriptor_value.descriptor=descriptor; gecko_cmd_msg->data.cmd_gatt_write_descriptor_value.value.len=value_len; memcpy(gecko_cmd_msg->data.cmd_gatt_write_descriptor_value.value.data,value_data,value_len); gecko_cmd_msg->header=((gecko_cmd_gatt_write_descriptor_value_id+((4+value_len)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_gatt_write_descriptor_value, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_gatt_write_descriptor_value; } /** * * gecko_cmd_gatt_find_included_services * * This command can be used to find out if a service of a remote GATT database includes one or more other services. This command generates a unique gatt_service_completed event for each included service. This command generates a unique gatt_service event for every discovered service. Received "gatt_procedure_completed" event indicates that this GATT procedure has successfully completed or failed with error. * * @param connection * @param service * * Events generated * * gecko_evt_gatt_service - Discovered service from remote GATT database. * gecko_evt_gatt_procedure_completed - Procedure has been successfully completed or failed with error. * **/ static inline struct gecko_msg_gatt_find_included_services_rsp_t* gecko_cmd_gatt_find_included_services(uint8 connection,uint32 service) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; gecko_cmd_msg->data.cmd_gatt_find_included_services.connection=connection; gecko_cmd_msg->data.cmd_gatt_find_included_services.service=service; gecko_cmd_msg->header=((gecko_cmd_gatt_find_included_services_id+((5)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_gatt_find_included_services, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_gatt_find_included_services; } /** * * gecko_cmd_gatt_read_multiple_characteristic_values * * This command can be used to read the values of multiple characteristics from a remote GATT database at once. "gatt_characteristic_value" events are generated as the values are returned by the remote GATT server. A received "gatt_procedure_completed" event indicates that either all data has been read successfully or that an error response has been received. * * @param connection * @param characteristic_list Little endian encoded uint16 list of characteristics to be read. * * Events generated * * gecko_evt_gatt_characteristic_value - This event contains the data belonging to a characteristic sent by the GATT Server. * gecko_evt_gatt_procedure_completed - Procedure has been successfully completed or failed with error. * **/ static inline struct gecko_msg_gatt_read_multiple_characteristic_values_rsp_t* gecko_cmd_gatt_read_multiple_characteristic_values(uint8 connection,uint8 characteristic_list_len, const uint8* characteristic_list_data) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; if ((uint16_t)characteristic_list_len > 256 - 2) { gecko_rsp_msg->data.rsp_gatt_read_multiple_characteristic_values.result = bg_err_command_too_long; return &gecko_rsp_msg->data.rsp_gatt_read_multiple_characteristic_values; } gecko_cmd_msg->data.cmd_gatt_read_multiple_characteristic_values.connection=connection; gecko_cmd_msg->data.cmd_gatt_read_multiple_characteristic_values.characteristic_list.len=characteristic_list_len; memcpy(gecko_cmd_msg->data.cmd_gatt_read_multiple_characteristic_values.characteristic_list.data,characteristic_list_data,characteristic_list_len); gecko_cmd_msg->header=((gecko_cmd_gatt_read_multiple_characteristic_values_id+((2+characteristic_list_len)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_gatt_read_multiple_characteristic_values, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_gatt_read_multiple_characteristic_values; } /** * * gecko_cmd_gatt_read_characteristic_value_from_offset * * This command can be used to read a partial characteristic value with specified offset and maximum length from a remote GATT database. It is equivalent to "gatt_read_characteristic_value" if both the offset and maximum length parameters are 0. A single "gatt_characteristic_value" event is generated if the value to read fits in one ATT PDU. Otherwise more than one " gatt_characteristic_value" events are generated because the firmware will automatically use the "read long" GATT procedure. A received "gatt_procedure_completed" event indicates that all data has been read successfully or that an error response has been received. * * @param connection * @param characteristic * @param offset Offset of the characteristic value * @param maxlen Maximum bytes to read. If this parameter is 0 all characteristic value starting at given offset will be read. * * Events generated * * gecko_evt_gatt_characteristic_value - This event contains the data belonging to a characteristic sent by the GATT Server. * gecko_evt_gatt_procedure_completed - Procedure has been successfully completed or failed with error. * **/ static inline struct gecko_msg_gatt_read_characteristic_value_from_offset_rsp_t* gecko_cmd_gatt_read_characteristic_value_from_offset(uint8 connection,uint16 characteristic,uint16 offset,uint16 maxlen) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; gecko_cmd_msg->data.cmd_gatt_read_characteristic_value_from_offset.connection=connection; gecko_cmd_msg->data.cmd_gatt_read_characteristic_value_from_offset.characteristic=characteristic; gecko_cmd_msg->data.cmd_gatt_read_characteristic_value_from_offset.offset=offset; gecko_cmd_msg->data.cmd_gatt_read_characteristic_value_from_offset.maxlen=maxlen; gecko_cmd_msg->header=((gecko_cmd_gatt_read_characteristic_value_from_offset_id+((7)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_gatt_read_characteristic_value_from_offset, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_gatt_read_characteristic_value_from_offset; } /** * * gecko_cmd_gatt_prepare_characteristic_value_reliable_write * * This command can be used to add a characteristic value to the write * queue of a remote GATT server and verify if the value was correctly * received by the server. Received "gatt_procedure_completed" event * indicates that this GATT procedure has succesfully completed or failed * with error. Specifically, error code 0x0194 (data_corrupted) will be * returned if the value received from the GATT server's response failed * to pass the reliable write verification. At most ATT_MTU - 5 amount of * data can be sent once. Writes are executed or cancelled with the * "execute_characteristic_value_write" command. Whether the * writes succeeded or not are indicated in the response of the * "execute_characteristic_value_write" command. * * * @param connection * @param characteristic * @param offset Offset of the characteristic value * @param value Value to write into the specified characteristic of the remote GATT database * * Events generated * * gecko_evt_gatt_procedure_completed - Procedure has been successfully completed or failed with error. * **/ static inline struct gecko_msg_gatt_prepare_characteristic_value_reliable_write_rsp_t* gecko_cmd_gatt_prepare_characteristic_value_reliable_write(uint8 connection,uint16 characteristic,uint16 offset,uint8 value_len, const uint8* value_data) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; if ((uint16_t)value_len > 256 - 6) { gecko_rsp_msg->data.rsp_gatt_prepare_characteristic_value_reliable_write.result = bg_err_command_too_long; return &gecko_rsp_msg->data.rsp_gatt_prepare_characteristic_value_reliable_write; } gecko_cmd_msg->data.cmd_gatt_prepare_characteristic_value_reliable_write.connection=connection; gecko_cmd_msg->data.cmd_gatt_prepare_characteristic_value_reliable_write.characteristic=characteristic; gecko_cmd_msg->data.cmd_gatt_prepare_characteristic_value_reliable_write.offset=offset; gecko_cmd_msg->data.cmd_gatt_prepare_characteristic_value_reliable_write.value.len=value_len; memcpy(gecko_cmd_msg->data.cmd_gatt_prepare_characteristic_value_reliable_write.value.data,value_data,value_len); gecko_cmd_msg->header=((gecko_cmd_gatt_prepare_characteristic_value_reliable_write_id+((6+value_len)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_gatt_prepare_characteristic_value_reliable_write, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_gatt_prepare_characteristic_value_reliable_write; } /** * * gecko_cmd_gatt_server_read_attribute_value * * This command can be used to read the value of an attribute from a local GATT database. Only (maximum BGAPI payload size - 3) amount of data can be read once. The application can continue reading with increased offset value if it receives (maximum BGAPI payload size - 3) amount of data. * * @param attribute Attribute handle * @param offset Value offset * **/ static inline struct gecko_msg_gatt_server_read_attribute_value_rsp_t* gecko_cmd_gatt_server_read_attribute_value(uint16 attribute,uint16 offset) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; gecko_cmd_msg->data.cmd_gatt_server_read_attribute_value.attribute=attribute; gecko_cmd_msg->data.cmd_gatt_server_read_attribute_value.offset=offset; gecko_cmd_msg->header=((gecko_cmd_gatt_server_read_attribute_value_id+((4)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_gatt_server_read_attribute_value, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_gatt_server_read_attribute_value; } /** * * gecko_cmd_gatt_server_read_attribute_type * * This command can be used to read the type of an attribute from a local GATT database. The type is a UUID, usually 16 or 128 bits long. * * @param attribute Attribute handle * **/ static inline struct gecko_msg_gatt_server_read_attribute_type_rsp_t* gecko_cmd_gatt_server_read_attribute_type(uint16 attribute) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; gecko_cmd_msg->data.cmd_gatt_server_read_attribute_type.attribute=attribute; gecko_cmd_msg->header=((gecko_cmd_gatt_server_read_attribute_type_id+((2)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_gatt_server_read_attribute_type, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_gatt_server_read_attribute_type; } /** * * gecko_cmd_gatt_server_write_attribute_value * * This command can be used to write the value of an attribute in the local GATT database. Writing the value of a characteristic of the local GATT database will not trigger notifications or indications to the remote GATT client in case such characteristic has property of indicate or notify and the client has enabled notification or indication. Notifications and indications are sent to the remote GATT client using " gatt_server_send_characteristic_notification" command. * * @param attribute Attribute handle * @param offset Value offset * @param value Value * **/ static inline struct gecko_msg_gatt_server_write_attribute_value_rsp_t* gecko_cmd_gatt_server_write_attribute_value(uint16 attribute,uint16 offset,uint8 value_len, const uint8* value_data) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; if ((uint16_t)value_len > 256 - 5) { gecko_rsp_msg->data.rsp_gatt_server_write_attribute_value.result = bg_err_command_too_long; return &gecko_rsp_msg->data.rsp_gatt_server_write_attribute_value; } gecko_cmd_msg->data.cmd_gatt_server_write_attribute_value.attribute=attribute; gecko_cmd_msg->data.cmd_gatt_server_write_attribute_value.offset=offset; gecko_cmd_msg->data.cmd_gatt_server_write_attribute_value.value.len=value_len; memcpy(gecko_cmd_msg->data.cmd_gatt_server_write_attribute_value.value.data,value_data,value_len); gecko_cmd_msg->header=((gecko_cmd_gatt_server_write_attribute_value_id+((5+value_len)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_gatt_server_write_attribute_value, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_gatt_server_write_attribute_value; } /** * * gecko_cmd_gatt_server_send_user_read_response * * This command must be used to send a response to a "user_read_request" event. The response needs to be sent within 30 second, otherwise no more GATT transactions are allowed by the remote side. If attr_errorcode is set to 0 the characteristic value is sent to the remote GATT client in the normal way. Other attr_errorcode values will cause the local GATT server to send an attribute protocol error response instead of the actual data. At most ATT_MTU - 1 amount of data can be sent once. Client will continue reading by sending new read request with increased offset value if it receives ATT_MTU - 1 amount of data. * * @param connection * @param characteristic * @param att_errorcode * @param value Characteristic value to send to the GATT client. Ignored if att_errorcode is not 0. * **/ static inline struct gecko_msg_gatt_server_send_user_read_response_rsp_t* gecko_cmd_gatt_server_send_user_read_response(uint8 connection,uint16 characteristic,uint8 att_errorcode,uint8 value_len, const uint8* value_data) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; if ((uint16_t)value_len > 256 - 5) { gecko_rsp_msg->data.rsp_gatt_server_send_user_read_response.result = bg_err_command_too_long; return &gecko_rsp_msg->data.rsp_gatt_server_send_user_read_response; } gecko_cmd_msg->data.cmd_gatt_server_send_user_read_response.connection=connection; gecko_cmd_msg->data.cmd_gatt_server_send_user_read_response.characteristic=characteristic; gecko_cmd_msg->data.cmd_gatt_server_send_user_read_response.att_errorcode=att_errorcode; gecko_cmd_msg->data.cmd_gatt_server_send_user_read_response.value.len=value_len; memcpy(gecko_cmd_msg->data.cmd_gatt_server_send_user_read_response.value.data,value_data,value_len); gecko_cmd_msg->header=((gecko_cmd_gatt_server_send_user_read_response_id+((5+value_len)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_gatt_server_send_user_read_response, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_gatt_server_send_user_read_response; } /** * * gecko_cmd_gatt_server_send_user_write_response * * This command must be used to send a response to a "gatt_server_user_write_request" event when parameter att_opcode in the event is Write Request (see "att_opcode"). The response needs to be sent within 30 seconds, otherwise no more GATT transactions are allowed by the remote side. If attr_errorcode is set to 0 the ATT protocol's write response is sent to indicate to the remote GATT client that the write operation was processed successfully. Other values will cause the local GATT server to send an ATT protocol error response. * * @param connection * @param characteristic * @param att_errorcode * **/ static inline struct gecko_msg_gatt_server_send_user_write_response_rsp_t* gecko_cmd_gatt_server_send_user_write_response(uint8 connection,uint16 characteristic,uint8 att_errorcode) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; gecko_cmd_msg->data.cmd_gatt_server_send_user_write_response.connection=connection; gecko_cmd_msg->data.cmd_gatt_server_send_user_write_response.characteristic=characteristic; gecko_cmd_msg->data.cmd_gatt_server_send_user_write_response.att_errorcode=att_errorcode; gecko_cmd_msg->header=((gecko_cmd_gatt_server_send_user_write_response_id+((4)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_gatt_server_send_user_write_response, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_gatt_server_send_user_write_response; } /** * * gecko_cmd_gatt_server_send_characteristic_notification * * This command can be used to send notifications or indications to one or more remote GATT clients. At most ATT_MTU - 3 amount of data can be sent once. * A notification or indication is sent only if the client has enabled * it by setting the corresponding flag to the Client Characteristic * Configuration descriptor. In case the Client Characteristic * Configuration descriptor supports both notification and indication, * the stack will always send a notification even when the client has * enabled both. * A new indication to a GATT client cannot be sent until an outstanding * indication procedure with the same client has completed. The procedure * is completed when a confirmation from the client has been received. * The confirmation is indicated by * "gatt_server_characteristic_status event". * Error bg_err_wrong_state is returned if the characteristic does not * have notification property, or if the client has not enabled the * notification. The same applies to indication property, and * in addition, bg_err_wrong_state is returned if an indication procedure * with the same client is outstanding. * * * @param connection Handle of the connection over which the notification or indication is sent. Values: * - 0xff: Sends notification or indication to all connected devices. * - Other: Connection handle * * @param characteristic Characteristic handle * @param value Value to be notified or indicated * **/ static inline struct gecko_msg_gatt_server_send_characteristic_notification_rsp_t* gecko_cmd_gatt_server_send_characteristic_notification(uint8 connection,uint16 characteristic,uint8 value_len, const uint8* value_data) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; if ((uint16_t)value_len > 256 - 4) { gecko_rsp_msg->data.rsp_gatt_server_send_characteristic_notification.result = bg_err_command_too_long; return &gecko_rsp_msg->data.rsp_gatt_server_send_characteristic_notification; } gecko_cmd_msg->data.cmd_gatt_server_send_characteristic_notification.connection=connection; gecko_cmd_msg->data.cmd_gatt_server_send_characteristic_notification.characteristic=characteristic; gecko_cmd_msg->data.cmd_gatt_server_send_characteristic_notification.value.len=value_len; memcpy(gecko_cmd_msg->data.cmd_gatt_server_send_characteristic_notification.value.data,value_data,value_len); gecko_cmd_msg->header=((gecko_cmd_gatt_server_send_characteristic_notification_id+((4+value_len)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_gatt_server_send_characteristic_notification, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_gatt_server_send_characteristic_notification; } /** * * gecko_cmd_gatt_server_find_attribute * * This command can be used to find attributes of certain type from a local GATT database. Type is usually given as 16-bit or 128-bit UUID. * * @param start Search start handle * @param type * **/ static inline struct gecko_msg_gatt_server_find_attribute_rsp_t* gecko_cmd_gatt_server_find_attribute(uint16 start,uint8 type_len, const uint8* type_data) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; if ((uint16_t)type_len > 256 - 3) { gecko_rsp_msg->data.rsp_gatt_server_find_attribute.result = bg_err_command_too_long; return &gecko_rsp_msg->data.rsp_gatt_server_find_attribute; } gecko_cmd_msg->data.cmd_gatt_server_find_attribute.start=start; gecko_cmd_msg->data.cmd_gatt_server_find_attribute.type.len=type_len; memcpy(gecko_cmd_msg->data.cmd_gatt_server_find_attribute.type.data,type_data,type_len); gecko_cmd_msg->header=((gecko_cmd_gatt_server_find_attribute_id+((3+type_len)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_gatt_server_find_attribute, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_gatt_server_find_attribute; } /** * * gecko_cmd_gatt_server_set_capabilities * * This command can be used to set which capabilities should be enabled in the local GATT database. A service is visible to remote GATT clients if at least one of its capabilities has been enabled. The same applies to a characteristic and its attributes. Capability identifiers and their corresponding bit flag values can be found in the auto-generated database header file. See UG118 for how to declare capabilities in GATT database. * Changing the capabilities of a database effectively causes a database * change (attributes being added or removed) from a remote GATT client * point of view. If the database has a Generic Attribute service and * Service Changed characteristic, the stack will monitor local database * change status and manage service changed indications for a GATT client * that has enabled the indication configuration of the Service Changed * characteristic. * * * @param caps Bit flags of capabilities to enable. Value 0 sets the default database capabilities. * @param reserved Value 0 should be used on this reserved field. None-zero values are reserved for future, do not use now. * **/ static inline struct gecko_msg_gatt_server_set_capabilities_rsp_t* gecko_cmd_gatt_server_set_capabilities(uint32 caps,uint32 reserved) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; gecko_cmd_msg->data.cmd_gatt_server_set_capabilities.caps=caps; gecko_cmd_msg->data.cmd_gatt_server_set_capabilities.reserved=reserved; gecko_cmd_msg->header=((gecko_cmd_gatt_server_set_capabilities_id+((8)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_gatt_server_set_capabilities, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_gatt_server_set_capabilities; } /** * * gecko_cmd_hardware_set_soft_timer * * This command can be used to start a software timer. Multiple concurrent timers can be running simultaneously. There are 256 unique timer IDs available. The maximum number of concurrent timers is configurable at device initialization. Up to 16 concurrent timers can be configured. The default configuration is 4. As the RAM for storing timer data is pre-allocated at initialization, an application should not configure the amount more than it needs for minimizing RAM usage. * * @param time Interval between how often to send events, in hardware clock ticks (1 second is equal to 32768 ticks). * The smallest interval value supported is 328 which is around 10 * milliseconds, any parameters between 0 and 328 will be rounded up to * 328. The maximum value is 2147483647, which * corresponds to about 18.2 hours. * If time is 0, removes the scheduled timer with the same handle. * @param handle Timer handle to use, is returned in timeout event * @param single_shot Timer mode. Values: * - 0: false (timer is repeating) * - 1: true (timer runs only once) * * * Events generated * * gecko_evt_hardware_soft_timer - Sent after specified interval * **/ static inline struct gecko_msg_hardware_set_soft_timer_rsp_t* gecko_cmd_hardware_set_soft_timer(uint32 time,uint8 handle,uint8 single_shot) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; gecko_cmd_msg->data.cmd_hardware_set_soft_timer.time=time; gecko_cmd_msg->data.cmd_hardware_set_soft_timer.handle=handle; gecko_cmd_msg->data.cmd_hardware_set_soft_timer.single_shot=single_shot; gecko_cmd_msg->header=((gecko_cmd_hardware_set_soft_timer_id+((6)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_hardware_set_soft_timer, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_hardware_set_soft_timer; } /** * * gecko_cmd_hardware_get_time * * Deprecated. Get elapsed time since last reset of RTCC * * **/ static inline struct gecko_msg_hardware_get_time_rsp_t* gecko_cmd_hardware_get_time() { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; gecko_cmd_msg->header=((gecko_cmd_hardware_get_time_id+((0)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_hardware_get_time, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_hardware_get_time; } /** * * gecko_cmd_hardware_set_lazy_soft_timer * * This command can be used to start a software timer with some slack. Slack parameter allows stack to optimize wake ups and save power. Timer event is triggered between time and time + slack. See also description of "hardware_set_soft_timer" command. * * @param time Interval between how often to send events, in hardware clock ticks (1 second is equal to 32768 ticks). * The smallest interval value supported is 328 which is around 10 * milliseconds, any parameters between 0 and 328 will be rounded up to * 328. The maximum value is 2147483647, which * corresponds to about 18.2 hours. * If time is 0, removes the scheduled timer with the same handle. * @param slack Slack time in hardware clock ticks * @param handle Timer handle to use, is returned in timeout event * @param single_shot Timer mode. Values: * - 0: false (timer is repeating) * - 1: true (timer runs only once) * * * Events generated * * gecko_evt_hardware_soft_timer - Sent after specified interval * **/ static inline struct gecko_msg_hardware_set_lazy_soft_timer_rsp_t* gecko_cmd_hardware_set_lazy_soft_timer(uint32 time,uint32 slack,uint8 handle,uint8 single_shot) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; gecko_cmd_msg->data.cmd_hardware_set_lazy_soft_timer.time=time; gecko_cmd_msg->data.cmd_hardware_set_lazy_soft_timer.slack=slack; gecko_cmd_msg->data.cmd_hardware_set_lazy_soft_timer.handle=handle; gecko_cmd_msg->data.cmd_hardware_set_lazy_soft_timer.single_shot=single_shot; gecko_cmd_msg->header=((gecko_cmd_hardware_set_lazy_soft_timer_id+((10)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_hardware_set_lazy_soft_timer, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_hardware_set_lazy_soft_timer; } /** * * gecko_cmd_flash_ps_erase_all * * This command can be used to erase all PS keys and their corresponding values. * * **/ static inline struct gecko_msg_flash_ps_erase_all_rsp_t* gecko_cmd_flash_ps_erase_all() { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; gecko_cmd_msg->header=((gecko_cmd_flash_ps_erase_all_id+((0)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_flash_ps_erase_all, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_flash_ps_erase_all; } /** * * gecko_cmd_flash_ps_save * * This command can be used to store a value into the specified PS key. Allowed PS keys are in range from 0x4000 to 0x407F. At most 56 bytes user data can be stored in one PS key. Error code 0x018a (command_too_long) will be returned if more than 56 bytes data is passed in. * * @param key PS key * @param value Value to store into the specified PS key. * **/ static inline struct gecko_msg_flash_ps_save_rsp_t* gecko_cmd_flash_ps_save(uint16 key,uint8 value_len, const uint8* value_data) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; if ((uint16_t)value_len > 256 - 3) { gecko_rsp_msg->data.rsp_flash_ps_save.result = bg_err_command_too_long; return &gecko_rsp_msg->data.rsp_flash_ps_save; } gecko_cmd_msg->data.cmd_flash_ps_save.key=key; gecko_cmd_msg->data.cmd_flash_ps_save.value.len=value_len; memcpy(gecko_cmd_msg->data.cmd_flash_ps_save.value.data,value_data,value_len); gecko_cmd_msg->header=((gecko_cmd_flash_ps_save_id+((3+value_len)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_flash_ps_save, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_flash_ps_save; } /** * * gecko_cmd_flash_ps_load * * This command can be used for retrieving the value of the specified PS key. * * @param key PS key of the value to be retrieved * **/ static inline struct gecko_msg_flash_ps_load_rsp_t* gecko_cmd_flash_ps_load(uint16 key) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; gecko_cmd_msg->data.cmd_flash_ps_load.key=key; gecko_cmd_msg->header=((gecko_cmd_flash_ps_load_id+((2)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_flash_ps_load, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_flash_ps_load; } /** * * gecko_cmd_flash_ps_erase * * This command can be used to erase a single PS key and its value from the persistent store.. * * @param key PS key to erase * **/ static inline struct gecko_msg_flash_ps_erase_rsp_t* gecko_cmd_flash_ps_erase(uint16 key) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; gecko_cmd_msg->data.cmd_flash_ps_erase.key=key; gecko_cmd_msg->header=((gecko_cmd_flash_ps_erase_id+((2)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_flash_ps_erase, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_flash_ps_erase; } /** * * gecko_cmd_test_dtm_tx * * This command can be used to start a transmitter test. The test is meant to be used against a separate Bluetooth tester device. When the command is processed by the radio, a "test_dtm_completed" event is triggered. This event indicates if the test started successfully. * In the transmitter test, the device sends packets continuously with a * fixed interval. The type and length of each packet is set by * packet_type and length parameters. Parameter phy specifies which PHY is used to transmit the packets. All devices support at least the 1M PHY. There is also a special packet type, test_pkt_carrier, which can be used to transmit continuous unmodulated carrier. The length field is ignored in this mode. * The test may be stopped using the "test_dtm_end" command. * * * @param packet_type Packet type to transmit * @param length Packet length in bytes * Range: 0-255 * * @param channel Bluetooth channel * Range: 0-39 * Channel is (F - 2402) / 2, * where F is frequency in MHz * * @param phy PHY to use * * Events generated * * gecko_evt_test_dtm_completed - This event is received when the command is processed. * **/ static inline struct gecko_msg_test_dtm_tx_rsp_t* gecko_cmd_test_dtm_tx(uint8 packet_type,uint8 length,uint8 channel,uint8 phy) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; gecko_cmd_msg->data.cmd_test_dtm_tx.packet_type=packet_type; gecko_cmd_msg->data.cmd_test_dtm_tx.length=length; gecko_cmd_msg->data.cmd_test_dtm_tx.channel=channel; gecko_cmd_msg->data.cmd_test_dtm_tx.phy=phy; gecko_cmd_msg->header=((gecko_cmd_test_dtm_tx_id+((4)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_test_dtm_tx, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_test_dtm_tx; } /** * * gecko_cmd_test_dtm_rx * * This command can be used to start a receiver test. The test is meant to be used against a separate Bluetooth tester device. When the command is processed by the radio, a "test_dtm_completed" event is triggered. This event indicates if the test started successfully. * Parameter * phy specifies which PHY is used to receive the packets. All devices support at least the 1M PHY. * The test may be stopped using the "test_dtm_end" command. This will * trigger another "test_dtm_completed" event, which carries the number * of packets received during the test. * * * @param channel Bluetooth channel * Range: 0-39 * Channel is (F - 2402) / 2, * where F is frequency in MHz * * @param phy PHY to use * * Events generated * * gecko_evt_test_dtm_completed - This event is received when the command is processed. * **/ static inline struct gecko_msg_test_dtm_rx_rsp_t* gecko_cmd_test_dtm_rx(uint8 channel,uint8 phy) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; gecko_cmd_msg->data.cmd_test_dtm_rx.channel=channel; gecko_cmd_msg->data.cmd_test_dtm_rx.phy=phy; gecko_cmd_msg->header=((gecko_cmd_test_dtm_rx_id+((2)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_test_dtm_rx, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_test_dtm_rx; } /** * * gecko_cmd_test_dtm_end * * This command can be used to end a transmitter or a receiver test. When the command is processed by the radio and the test has ended, a "test_dtm_completed" event is triggered. * * * Events generated * * gecko_evt_test_dtm_completed - This event is received when the command is processed. * **/ static inline struct gecko_msg_test_dtm_end_rsp_t* gecko_cmd_test_dtm_end() { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; gecko_cmd_msg->header=((gecko_cmd_test_dtm_end_id+((0)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_test_dtm_end, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_test_dtm_end; } /** * * gecko_cmd_sm_set_bondable_mode * * This command can be used to set whether the device should accept new bondings. By default, the device does not accept new bondings. * * @param bondable Bondable mode. Values: * - 0: New bondings not accepted * - 1: Bondings allowed * Default value: 0 * * **/ static inline struct gecko_msg_sm_set_bondable_mode_rsp_t* gecko_cmd_sm_set_bondable_mode(uint8 bondable) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; gecko_cmd_msg->data.cmd_sm_set_bondable_mode.bondable=bondable; gecko_cmd_msg->header=((gecko_cmd_sm_set_bondable_mode_id+((1)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_sm_set_bondable_mode, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_sm_set_bondable_mode; } /** * * gecko_cmd_sm_configure * * This command can be used to configure security requirements and I/O capabilities of the system. * * @param flags Security requirement bitmask.{br}Bit 0: * - 0: Allow bonding without MITM protection * - 1: Bonding requires MITM protection * Bit 1: * - 0: Allow encryption without bonding * - 1: Encryption requires bonding. Note that this setting will also enable bonding. * Bit 2: * - 0: Allow bonding with legacy pairing * - 1: Secure connections only * Bit 3: * - 0: Bonding request does not need to be confirmed * - 1: Bonding requests need to be confirmed. Received bonding requests are notified with "sm_confirm_bonding events." * Bit 4 to 7: Reserved{br}{br}Default value: 0x00 * @param io_capabilities I/O Capabilities. See link * **/ static inline struct gecko_msg_sm_configure_rsp_t* gecko_cmd_sm_configure(uint8 flags,uint8 io_capabilities) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; gecko_cmd_msg->data.cmd_sm_configure.flags=flags; gecko_cmd_msg->data.cmd_sm_configure.io_capabilities=io_capabilities; gecko_cmd_msg->header=((gecko_cmd_sm_configure_id+((2)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_sm_configure, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_sm_configure; } /** * * gecko_cmd_sm_store_bonding_configuration * * This command can be used to set maximum allowed bonding count and bonding policy. The default value is maximum number of bondings supported. * * @param max_bonding_count Maximum allowed bonding count. Range: 1 to 14 * @param policy_flags Bonding policy. Values: * - 0: If database is full, new bonding attempts will fail * - 1: New bonding will overwrite the oldest existing bonding * - 2: New bonding will overwrite longest time ago used existing bonding * * **/ static inline struct gecko_msg_sm_store_bonding_configuration_rsp_t* gecko_cmd_sm_store_bonding_configuration(uint8 max_bonding_count,uint8 policy_flags) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; gecko_cmd_msg->data.cmd_sm_store_bonding_configuration.max_bonding_count=max_bonding_count; gecko_cmd_msg->data.cmd_sm_store_bonding_configuration.policy_flags=policy_flags; gecko_cmd_msg->header=((gecko_cmd_sm_store_bonding_configuration_id+((2)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_sm_store_bonding_configuration, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_sm_store_bonding_configuration; } /** * * gecko_cmd_sm_increase_security * * This command can be used to enhance the security of a connection to current security requirements. On an unencrypted connection, this will encrypt the connection and will also perform bonding if requested by both devices. On an encrypted connection, this will cause the connection re-encrypted. * * @param connection Connection handle * * Events generated * * gecko_evt_le_connection_parameters - This event is triggered after increasing security has been completed successfully, and indicates the latest security mode of the connection. * gecko_evt_sm_bonded - This event is triggered if pairing or bonding was performed in this operation and the result is success. * gecko_evt_sm_bonding_failed - This event is triggered if pairing or bonding was performed in this operation and the result is failure. * **/ static inline struct gecko_msg_sm_increase_security_rsp_t* gecko_cmd_sm_increase_security(uint8 connection) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; gecko_cmd_msg->data.cmd_sm_increase_security.connection=connection; gecko_cmd_msg->header=((gecko_cmd_sm_increase_security_id+((1)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_sm_increase_security, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_sm_increase_security; } /** * * gecko_cmd_sm_delete_bonding * * This command can be used to delete specified bonding information or whitelist from Persistent Store. * * @param bonding Bonding handle * **/ static inline struct gecko_msg_sm_delete_bonding_rsp_t* gecko_cmd_sm_delete_bonding(uint8 bonding) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; gecko_cmd_msg->data.cmd_sm_delete_bonding.bonding=bonding; gecko_cmd_msg->header=((gecko_cmd_sm_delete_bonding_id+((1)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_sm_delete_bonding, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_sm_delete_bonding; } /** * * gecko_cmd_sm_delete_bondings * * This command can be used to delete all bonding information and whitelist from Persistent Store. * * **/ static inline struct gecko_msg_sm_delete_bondings_rsp_t* gecko_cmd_sm_delete_bondings() { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; gecko_cmd_msg->header=((gecko_cmd_sm_delete_bondings_id+((0)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_sm_delete_bondings, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_sm_delete_bondings; } /** * * gecko_cmd_sm_enter_passkey * * This command can be used to enter a passkey after receiving a passkey request event. * * @param connection Connection handle * @param passkey Passkey. Valid range: 0-999999. Set -1 to cancel pairing. * **/ static inline struct gecko_msg_sm_enter_passkey_rsp_t* gecko_cmd_sm_enter_passkey(uint8 connection,int32 passkey) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; gecko_cmd_msg->data.cmd_sm_enter_passkey.connection=connection; gecko_cmd_msg->data.cmd_sm_enter_passkey.passkey=passkey; gecko_cmd_msg->header=((gecko_cmd_sm_enter_passkey_id+((5)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_sm_enter_passkey, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_sm_enter_passkey; } /** * * gecko_cmd_sm_passkey_confirm * * This command can be used for accepting or rejecting reported confirm value. * * @param connection Connection handle * @param confirm Accept confirm value. Values: * - 0: Reject * - 1: Accept confirm value * * **/ static inline struct gecko_msg_sm_passkey_confirm_rsp_t* gecko_cmd_sm_passkey_confirm(uint8 connection,uint8 confirm) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; gecko_cmd_msg->data.cmd_sm_passkey_confirm.connection=connection; gecko_cmd_msg->data.cmd_sm_passkey_confirm.confirm=confirm; gecko_cmd_msg->header=((gecko_cmd_sm_passkey_confirm_id+((2)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_sm_passkey_confirm, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_sm_passkey_confirm; } /** * * gecko_cmd_sm_set_oob_data * * This command can be used to set the OOB data (out-of-band encryption data) for legacy pairing for a device. The OOB data may be, for example, a PIN code exchanged over an alternate path like NFC. The device will not allow any other kind of bonding if OOB data is set. The OOB data cannot be set simultaneously with secure connections OOB data. * * @param oob_data OOB data. To set OOB data, send a 16-byte array. To clear OOB data, send a zero-length array. * **/ static inline struct gecko_msg_sm_set_oob_data_rsp_t* gecko_cmd_sm_set_oob_data(uint8 oob_data_len, const uint8* oob_data_data) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; if ((uint16_t)oob_data_len > 256 - 1) { gecko_rsp_msg->data.rsp_sm_set_oob_data.result = bg_err_command_too_long; return &gecko_rsp_msg->data.rsp_sm_set_oob_data; } gecko_cmd_msg->data.cmd_sm_set_oob_data.oob_data.len=oob_data_len; memcpy(gecko_cmd_msg->data.cmd_sm_set_oob_data.oob_data.data,oob_data_data,oob_data_len); gecko_cmd_msg->header=((gecko_cmd_sm_set_oob_data_id+((1+oob_data_len)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_sm_set_oob_data, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_sm_set_oob_data; } /** * * gecko_cmd_sm_list_all_bondings * * This command can be used to list all bondings stored in the bonding database. Bondings are reported by using the " sm_list_bonding_entry" event for each bonding and the report is ended with "sm_list_all_bondings_complete" event. Recommended to be used only for debugging purposes, because reading from the Persistent Store is relatively slow. * * * Events generated * * gecko_evt_sm_list_bonding_entry - * gecko_evt_sm_list_all_bondings_complete - * **/ static inline struct gecko_msg_sm_list_all_bondings_rsp_t* gecko_cmd_sm_list_all_bondings() { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; gecko_cmd_msg->header=((gecko_cmd_sm_list_all_bondings_id+((0)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_sm_list_all_bondings, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_sm_list_all_bondings; } /** * * gecko_cmd_sm_bonding_confirm * * This command can be used for accepting or rejecting bonding request. * * @param connection Connection handle * @param confirm Accept bonding request. Values: * - 0: Reject * - 1: Accept bonding request * * **/ static inline struct gecko_msg_sm_bonding_confirm_rsp_t* gecko_cmd_sm_bonding_confirm(uint8 connection,uint8 confirm) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; gecko_cmd_msg->data.cmd_sm_bonding_confirm.connection=connection; gecko_cmd_msg->data.cmd_sm_bonding_confirm.confirm=confirm; gecko_cmd_msg->header=((gecko_cmd_sm_bonding_confirm_id+((2)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_sm_bonding_confirm, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_sm_bonding_confirm; } /** * * gecko_cmd_sm_set_debug_mode * * This command can be used to set Security Manager in debug mode. In this mode the secure connections bonding uses debug keys, so that the encrypted packet can be opened by Bluetooth protocol analyzer. To disable the debug mode, you need to restart the device. * * **/ static inline struct gecko_msg_sm_set_debug_mode_rsp_t* gecko_cmd_sm_set_debug_mode() { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; gecko_cmd_msg->header=((gecko_cmd_sm_set_debug_mode_id+((0)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_sm_set_debug_mode, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_sm_set_debug_mode; } /** * * gecko_cmd_sm_set_passkey * * This command can be used to enter a fixed passkey which will be used in the "sm_passkey_display" event. * * @param passkey Passkey. Valid range: 0-999999. Set -1 to disable and start using random passkeys. * **/ static inline struct gecko_msg_sm_set_passkey_rsp_t* gecko_cmd_sm_set_passkey(int32 passkey) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; gecko_cmd_msg->data.cmd_sm_set_passkey.passkey=passkey; gecko_cmd_msg->header=((gecko_cmd_sm_set_passkey_id+((4)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_sm_set_passkey, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_sm_set_passkey; } /** * * gecko_cmd_sm_use_sc_oob * * This command can be used to enable the use of OOB data (out-of-band encryption data) for a device for secure connections pairing. The enabling will genarate new OOB data and confirm values which can be sent to the remote device. After enabling the secure connections OOB data, the remote devices OOB data can be set with "sm_set_sc_remote_oob_data". Calling this function will erase any set remote device OOB data and confirm values. The device will not allow any other kind of bonding if OOB data is set. The secure connections OOB data cannot be enabled simultaneously with legacy pairing OOB data. * * @param enable Enable OOB with secure connections pairing. Values: * - 0: disable * - 1: enable * * **/ static inline struct gecko_msg_sm_use_sc_oob_rsp_t* gecko_cmd_sm_use_sc_oob(uint8 enable) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; gecko_cmd_msg->data.cmd_sm_use_sc_oob.enable=enable; gecko_cmd_msg->header=((gecko_cmd_sm_use_sc_oob_id+((1)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_sm_use_sc_oob, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_sm_use_sc_oob; } /** * * gecko_cmd_sm_set_sc_remote_oob_data * * This command can be used to set OOB data and confirm values (out-of-band encryption) received from the remote device for secure connections pairing. OOB data must be enabled with "sm_use_sc_oob" before setting the remote device OOB data. * * @param oob_data Remote device OOB data and confirm values. To set OOB data, send a 32-byte array. First 16-bytes is the OOB data and last 16-bytes the confirm value. To clear OOB data, send a zero-length array. * **/ static inline struct gecko_msg_sm_set_sc_remote_oob_data_rsp_t* gecko_cmd_sm_set_sc_remote_oob_data(uint8 oob_data_len, const uint8* oob_data_data) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; if ((uint16_t)oob_data_len > 256 - 1) { gecko_rsp_msg->data.rsp_sm_set_sc_remote_oob_data.result = bg_err_command_too_long; return &gecko_rsp_msg->data.rsp_sm_set_sc_remote_oob_data; } gecko_cmd_msg->data.cmd_sm_set_sc_remote_oob_data.oob_data.len=oob_data_len; memcpy(gecko_cmd_msg->data.cmd_sm_set_sc_remote_oob_data.oob_data.data,oob_data_data,oob_data_len); gecko_cmd_msg->header=((gecko_cmd_sm_set_sc_remote_oob_data_id+((1+oob_data_len)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_sm_set_sc_remote_oob_data, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_sm_set_sc_remote_oob_data; } /** * * gecko_cmd_sm_add_to_whitelist * * This command can be used to add device to whitelist, which can be enabled with "le_gap_enable_whitelisting" * * @param address Address of the device added to whitelist * @param address_type Address type of the device added to whitelist * **/ static inline struct gecko_msg_sm_add_to_whitelist_rsp_t* gecko_cmd_sm_add_to_whitelist(bd_addr address,uint8 address_type) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; memcpy(&gecko_cmd_msg->data.cmd_sm_add_to_whitelist.address,&address,sizeof(bd_addr)); gecko_cmd_msg->data.cmd_sm_add_to_whitelist.address_type=address_type; gecko_cmd_msg->header=((gecko_cmd_sm_add_to_whitelist_id+((7)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_sm_add_to_whitelist, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_sm_add_to_whitelist; } /** * * gecko_cmd_homekit_configure * * This command can be used to configure the Apple HomeKit accessory and its settings. It is possible to reinitialize configuration in run time. New fast advertising parameters will be used for next fast advertising. * * @param i2c_address I2C address of Apple authentication coprocessor * @param support_display A flag to tell the display support is enabled in the accessory. {br}A pin code will be randomly generated randomly during the pairing process and event "homekit_setupcode_display" event will be produced so the pin code can be shown on the display. * - 0: Display support disabled * - 1: Display support enabled * * @param hap_attribute_features The value of Apple HomeKit pairing features supported in pairing service feature characteristic. * - 0x01: Supports Apple Authentication Coprocessor * - 0x02: Supports Software Authentication * - 0x00: Only for testing purposes when any authentication method is not available. The accessory will be discovered as non-authenticated * - other: Reserved * * @param category Apple HomeKit accessory category * @param configuration_number Apple HomeKit configuration number {br}By default, this starts from 1. Accessories must increment this value after a firmware update. This value must be managed by the application. * @param fast_advert_interval Fast advertising interval. {br}This is used during fast advertising in disconnected state after calling command "homekit_event_notification" when broadcast events advertising is finished. * @param fast_advert_timeout Fast advertising timeout. {br}This is used during fast advertising in disconnected state after calling command "homekit_event_notification" when broadcast events advertising is finished. * - Time = Value x 100 ms * * @param flag Apple HomeKit library configuration flag. * - 0x00000001: Manual Bluetooth disconnection in HomeKit error case. When enabling a "homekit_disconnection_required" event will be produced when appear HomeKit error. * - 0x00000002: Manual set of scan response data. When enabling it is possible to use "le_gap_bt5_set_adv_data" command to set custom scan response data. In other case HomeKit library will use it to set accessory local name. - other: Reserved. Must be 0. * * @param broadcast_advert_timeout Broadcast events advertising timeout. {br}This is used during broadcast events advertising in disconnected state after calling command "homekit_event_notification" * - Time = Value x 100 ms * * @param model_name Model name characteristic value from HomeKit Accessory Information service. Mandatory in case of HomeKit software authentication usage. * **/ static inline struct gecko_msg_homekit_configure_rsp_t* gecko_cmd_homekit_configure(uint8 i2c_address,uint8 support_display,uint8 hap_attribute_features,uint16 category,uint8 configuration_number,uint16 fast_advert_interval,uint16 fast_advert_timeout,uint32 flag,uint16 broadcast_advert_timeout,uint8 model_name_len, const uint8* model_name_data) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; if ((uint16_t)model_name_len > 256 - 17) { gecko_rsp_msg->data.rsp_homekit_configure.result = bg_err_command_too_long; return &gecko_rsp_msg->data.rsp_homekit_configure; } gecko_cmd_msg->data.cmd_homekit_configure.i2c_address=i2c_address; gecko_cmd_msg->data.cmd_homekit_configure.support_display=support_display; gecko_cmd_msg->data.cmd_homekit_configure.hap_attribute_features=hap_attribute_features; gecko_cmd_msg->data.cmd_homekit_configure.category=category; gecko_cmd_msg->data.cmd_homekit_configure.configuration_number=configuration_number; gecko_cmd_msg->data.cmd_homekit_configure.fast_advert_interval=fast_advert_interval; gecko_cmd_msg->data.cmd_homekit_configure.fast_advert_timeout=fast_advert_timeout; gecko_cmd_msg->data.cmd_homekit_configure.flag=flag; gecko_cmd_msg->data.cmd_homekit_configure.broadcast_advert_timeout=broadcast_advert_timeout; gecko_cmd_msg->data.cmd_homekit_configure.model_name.len=model_name_len; memcpy(gecko_cmd_msg->data.cmd_homekit_configure.model_name.data,model_name_data,model_name_len); gecko_cmd_msg->header=((gecko_cmd_homekit_configure_id+((17+model_name_len)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_homekit_configure, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_homekit_configure; } /** * * gecko_cmd_homekit_advertise * * This command can be used to start or stop Apple HomeKit accessory advertising. The command and parameters will take effect immediately. If the given parameters can't be used in the currently active mode, an error will be returned. * * @param enable A flag to enable or disable Apple HomeKit advertising * - 1: Enable advertising * - 0: Disable advertising * * @param interval_min Minimum advertising interval. Please refer to GAP command: "le_gap_set_adv_parameters" * @param interval_max Maximum advertising interval. Please refer to GAP command: "le_gap_set_adv_parameters" * @param channel_map Advertising channel map. Please refer to GAP command: "le_gap_set_adv_parameters" * **/ static inline struct gecko_msg_homekit_advertise_rsp_t* gecko_cmd_homekit_advertise(uint8 enable,uint16 interval_min,uint16 interval_max,uint8 channel_map) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; gecko_cmd_msg->data.cmd_homekit_advertise.enable=enable; gecko_cmd_msg->data.cmd_homekit_advertise.interval_min=interval_min; gecko_cmd_msg->data.cmd_homekit_advertise.interval_max=interval_max; gecko_cmd_msg->data.cmd_homekit_advertise.channel_map=channel_map; gecko_cmd_msg->header=((gecko_cmd_homekit_advertise_id+((6)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_homekit_advertise, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_homekit_advertise; } /** * * gecko_cmd_homekit_delete_pairings * * This command can be used to delete all Apple HomeKit pairing data. Additionally it resets all required HomeKit settings to factory state, e.g. it resets GSN value, generates new Device ID. * * **/ static inline struct gecko_msg_homekit_delete_pairings_rsp_t* gecko_cmd_homekit_delete_pairings() { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; gecko_cmd_msg->header=((gecko_cmd_homekit_delete_pairings_id+((0)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_homekit_delete_pairings, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_homekit_delete_pairings; } /** * * gecko_cmd_homekit_check_authcp * * This command can be used to make an I2C test connection with Apple authentication co-processor and return error if communication failed. * * **/ static inline struct gecko_msg_homekit_check_authcp_rsp_t* gecko_cmd_homekit_check_authcp() { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; gecko_cmd_msg->header=((gecko_cmd_homekit_check_authcp_id+((0)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_homekit_check_authcp, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_homekit_check_authcp; } /** * * gecko_cmd_homekit_get_pairing_id * * This command can be used to get pairing ID of the connected iOS device. * * @param connection * **/ static inline struct gecko_msg_homekit_get_pairing_id_rsp_t* gecko_cmd_homekit_get_pairing_id(uint8 connection) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; gecko_cmd_msg->data.cmd_homekit_get_pairing_id.connection=connection; gecko_cmd_msg->header=((gecko_cmd_homekit_get_pairing_id_id+((1)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_homekit_get_pairing_id, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_homekit_get_pairing_id; } /** * * gecko_cmd_homekit_send_write_response * * This command can be used to send a response to a "homekit_write_request" event. The response needs to be sent within 30 seconds, otherwise no more GATT transactions are allowed by the remote side. {br}{br}If the status_code is set to 0 the HAP will send a response informing that the write operation was processed successfully and other values will cause the HAP to send a HAP error status response. * * @param connection * @param characteristic * @param status_code HomeKit status code. * **/ static inline struct gecko_msg_homekit_send_write_response_rsp_t* gecko_cmd_homekit_send_write_response(uint8 connection,uint16 characteristic,uint8 status_code) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; gecko_cmd_msg->data.cmd_homekit_send_write_response.connection=connection; gecko_cmd_msg->data.cmd_homekit_send_write_response.characteristic=characteristic; gecko_cmd_msg->data.cmd_homekit_send_write_response.status_code=status_code; gecko_cmd_msg->header=((gecko_cmd_homekit_send_write_response_id+((4)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_homekit_send_write_response, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_homekit_send_write_response; } /** * * gecko_cmd_homekit_send_read_response * * This command can be used to send a response to a "homekit_read_request" event. The response needs to be sent within 30 seconds, or otherwise no more GATT transactions are allowed by the remote side. {br}{br}If status_code is set to 0, the characteristic value is sent to the remote GATT client through HomeKit library in a normal way. Other status_code values will cause a HAP error status response instead of the actual data being sent. {br}{br}If the value data size is less than attribute_size then the Apple HomeKit library will send new "homekit_read_request" event with suitable offset. The Apple HomeKit library provides automatic formatting for the frame as well encryption. * * @param connection * @param characteristic * @param status_code HomeKit Status Code. * @param attribute_size Size of attribute value * @param value Characteristic value to send to the GATT client through HomeKit library. This is ignored if status_code is not set to 0. * **/ static inline struct gecko_msg_homekit_send_read_response_rsp_t* gecko_cmd_homekit_send_read_response(uint8 connection,uint16 characteristic,uint8 status_code,uint16 attribute_size,uint8 value_len, const uint8* value_data) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; if ((uint16_t)value_len > 256 - 7) { gecko_rsp_msg->data.rsp_homekit_send_read_response.result = bg_err_command_too_long; return &gecko_rsp_msg->data.rsp_homekit_send_read_response; } gecko_cmd_msg->data.cmd_homekit_send_read_response.connection=connection; gecko_cmd_msg->data.cmd_homekit_send_read_response.characteristic=characteristic; gecko_cmd_msg->data.cmd_homekit_send_read_response.status_code=status_code; gecko_cmd_msg->data.cmd_homekit_send_read_response.attribute_size=attribute_size; gecko_cmd_msg->data.cmd_homekit_send_read_response.value.len=value_len; memcpy(gecko_cmd_msg->data.cmd_homekit_send_read_response.value.data,value_data,value_len); gecko_cmd_msg->header=((gecko_cmd_homekit_send_read_response_id+((7+value_len)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_homekit_send_read_response, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_homekit_send_read_response; } /** * * gecko_cmd_homekit_gsn_action * * This command can be used to make suitable action by HomeKit library for GSN (Global State Number) value. * * @param action Actions: * - 0: Reset GSN value to default state * - 1: Store GSN value to a PS-key (flash) * * **/ static inline struct gecko_msg_homekit_gsn_action_rsp_t* gecko_cmd_homekit_gsn_action(uint8 action) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; gecko_cmd_msg->data.cmd_homekit_gsn_action.action=action; gecko_cmd_msg->header=((gecko_cmd_homekit_gsn_action_id+((1)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_homekit_gsn_action, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_homekit_gsn_action; } /** * * gecko_cmd_homekit_event_notification * * This command can be used to perform suitable actions for HomeKit notifications according to a connection state and the originator of the change. When device is in connected state and it is local change it sends empty indication to controller. When device is disconnected it starts broadcast events advertising, next after timeout it starts fast advertising. Broadcast and fast advertising parameters are set in "homekit_configure". After fast advertising timeout it reverts previous advertising settings. For both states it sets suitable Global State Number value accoring to HomeKit specification rules. * * @param connection Connection handle. Ignored for disconnected state. * @param characteristic * @param change_originator Characteristic value place where change come from: * - 0: Remote change (from controller) * - 1: Local change (from accessory) * * @param value Broadcast notify value. * **/ static inline struct gecko_msg_homekit_event_notification_rsp_t* gecko_cmd_homekit_event_notification(uint8 connection,uint16 characteristic,uint8 change_originator,uint8 value_len, const uint8* value_data) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; if ((uint16_t)value_len > 256 - 5) { gecko_rsp_msg->data.rsp_homekit_event_notification.result = bg_err_command_too_long; return &gecko_rsp_msg->data.rsp_homekit_event_notification; } gecko_cmd_msg->data.cmd_homekit_event_notification.connection=connection; gecko_cmd_msg->data.cmd_homekit_event_notification.characteristic=characteristic; gecko_cmd_msg->data.cmd_homekit_event_notification.change_originator=change_originator; gecko_cmd_msg->data.cmd_homekit_event_notification.value.len=value_len; memcpy(gecko_cmd_msg->data.cmd_homekit_event_notification.value.data,value_data,value_len); gecko_cmd_msg->header=((gecko_cmd_homekit_event_notification_id+((5+value_len)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_homekit_event_notification, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_homekit_event_notification; } /** * * gecko_cmd_homekit_broadcast_action * * This command can be used to make suitable action by HomeKit library for broadcast advertisisng. * * @param action Actions: * - 0x00: Delete broadcast advertising data. No additional parameters are required * - 0x01: Store broadcast advertising data (key, charactersitics configuration) to non volatile memory. No additional parameters are required * - other: Reserved * * @param params Additional parameters for action. * **/ static inline struct gecko_msg_homekit_broadcast_action_rsp_t* gecko_cmd_homekit_broadcast_action(uint8 action,uint8 params_len, const uint8* params_data) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; if ((uint16_t)params_len > 256 - 2) { gecko_rsp_msg->data.rsp_homekit_broadcast_action.result = bg_err_command_too_long; return &gecko_rsp_msg->data.rsp_homekit_broadcast_action; } gecko_cmd_msg->data.cmd_homekit_broadcast_action.action=action; gecko_cmd_msg->data.cmd_homekit_broadcast_action.params.len=params_len; memcpy(gecko_cmd_msg->data.cmd_homekit_broadcast_action.params.data,params_data,params_len); gecko_cmd_msg->header=((gecko_cmd_homekit_broadcast_action_id+((2+params_len)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_homekit_broadcast_action, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_homekit_broadcast_action; } /** * * gecko_cmd_coex_set_options * * This command is used to configure coexistence options at runtime. * * @param mask Mask defines which coexistence options are changed. * @param options Value of options to be changed. This parameter is used together with mask parameter. * **/ static inline struct gecko_msg_coex_set_options_rsp_t* gecko_cmd_coex_set_options(uint32 mask,uint32 options) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; gecko_cmd_msg->data.cmd_coex_set_options.mask=mask; gecko_cmd_msg->data.cmd_coex_set_options.options=options; gecko_cmd_msg->header=((gecko_cmd_coex_set_options_id+((8)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_coex_set_options, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_coex_set_options; } /** * * gecko_cmd_coex_get_counters * * This command is used to read coexistence statistic counters from the device. Response contains the list of uint32 type counter values. Counters in the list are in following order: low priority requested, high priority requested, low priority denied, high priority denied, low priority tx aborted, high priority tx aborted. * * @param reset Reset counter values * **/ static inline struct gecko_msg_coex_get_counters_rsp_t* gecko_cmd_coex_get_counters(uint8 reset) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; gecko_cmd_msg->data.cmd_coex_get_counters.reset=reset; gecko_cmd_msg->header=((gecko_cmd_coex_get_counters_id+((1)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_coex_get_counters, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_coex_get_counters; } /** * * gecko_cmd_l2cap_coc_send_connection_request * * This command is used for sending LE credit based connection request. * * @param connection Handle of the LE connection to be used for opening connection-oriented channel. * @param le_psm LE Protocol/Service Multiplexer - LE_PSM * @param mtu The maximum size of payload data that the application on the device * sending the request is capable of accepting, i.e. the MTU corresponds * to the maximum SDU size. * Range: 23 to 65533. * Application needs to handle segmentation and reassembly from PDU to * SDU. * * @param mps The maximum size of payload data that the L2CAP layer on the device * sending the request is capable of accepting, i.e. the MPS corresponds * to the maximum PDU payload size. * Range: 23 to 250. * That is the maximum size of data that the application is able to send * using "l2cap_coc_send_data" command or receive by "l2cap_coc_data" * event. * * @param initial_credit The initial credit value indicates the number of PDUs that the peer device can send. * * Events generated * * gecko_evt_l2cap_coc_connection_response - Triggered when a LE credit based connection connection response has been received in response to this command. * gecko_evt_l2cap_coc_channel_disconnected - Triggered when a LE credit based connection connection response has not been received within the 30 seconds timeout in response to this command. * **/ static inline struct gecko_msg_l2cap_coc_send_connection_request_rsp_t* gecko_cmd_l2cap_coc_send_connection_request(uint8 connection,uint16 le_psm,uint16 mtu,uint16 mps,uint16 initial_credit) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; gecko_cmd_msg->data.cmd_l2cap_coc_send_connection_request.connection=connection; gecko_cmd_msg->data.cmd_l2cap_coc_send_connection_request.le_psm=le_psm; gecko_cmd_msg->data.cmd_l2cap_coc_send_connection_request.mtu=mtu; gecko_cmd_msg->data.cmd_l2cap_coc_send_connection_request.mps=mps; gecko_cmd_msg->data.cmd_l2cap_coc_send_connection_request.initial_credit=initial_credit; gecko_cmd_msg->header=((gecko_cmd_l2cap_coc_send_connection_request_id+((9)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_l2cap_coc_send_connection_request, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_l2cap_coc_send_connection_request; } /** * * gecko_cmd_l2cap_coc_send_connection_response * * This command is used for sending LE credit based connection response. * * @param connection Handle of the LE connection to be used for opening connection-oriented channel. * @param cid The CID represents the destination channel endpoint of the device sending the response which is same as source CID field of corresponding request message. * @param mtu The maximum size of payload data that the application on the device * sending the response is capable of accepting, i.e. the MTU corresponds * to the maximum SDU size. * Range: 23 to 65533. * Application needs to handle segmentation and reassembly from PDU to * SDU. * * @param mps The maximum size of payload data that the L2CAP layer on the device * sending the response is capable of accepting, i.e. the MPS corresponds * to the maximum PDU payload size. * Range: 23 to 250. * That is the maximum size of data that the application is able to send * using "l2cap_coc_send_data" command or receive by "l2cap_coc_data" * event. * * @param initial_credit The initial credit value indicates the number of PDUs that the peer device can send. * @param result The result field indicates the outcome of the connection request. * **/ static inline struct gecko_msg_l2cap_coc_send_connection_response_rsp_t* gecko_cmd_l2cap_coc_send_connection_response(uint8 connection,uint16 cid,uint16 mtu,uint16 mps,uint16 initial_credit,uint16 result) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; gecko_cmd_msg->data.cmd_l2cap_coc_send_connection_response.connection=connection; gecko_cmd_msg->data.cmd_l2cap_coc_send_connection_response.cid=cid; gecko_cmd_msg->data.cmd_l2cap_coc_send_connection_response.mtu=mtu; gecko_cmd_msg->data.cmd_l2cap_coc_send_connection_response.mps=mps; gecko_cmd_msg->data.cmd_l2cap_coc_send_connection_response.initial_credit=initial_credit; gecko_cmd_msg->data.cmd_l2cap_coc_send_connection_response.result=result; gecko_cmd_msg->header=((gecko_cmd_l2cap_coc_send_connection_response_id+((11)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_l2cap_coc_send_connection_response, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_l2cap_coc_send_connection_response; } /** * * gecko_cmd_l2cap_coc_send_le_flow_control_credit * * This command is used for sending LE flow control credit indicating that the channel endpoint on local device is capable of receiving more data. * * @param connection Handle of the LE connection to be used for sending flow control credit. * @param cid The CID represents the destination channel endpoint of the device sending the flow control credit. * @param credits The credit value indicates the additional number of PDUs that the peer device can send. * **/ static inline struct gecko_msg_l2cap_coc_send_le_flow_control_credit_rsp_t* gecko_cmd_l2cap_coc_send_le_flow_control_credit(uint8 connection,uint16 cid,uint16 credits) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; gecko_cmd_msg->data.cmd_l2cap_coc_send_le_flow_control_credit.connection=connection; gecko_cmd_msg->data.cmd_l2cap_coc_send_le_flow_control_credit.cid=cid; gecko_cmd_msg->data.cmd_l2cap_coc_send_le_flow_control_credit.credits=credits; gecko_cmd_msg->header=((gecko_cmd_l2cap_coc_send_le_flow_control_credit_id+((5)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_l2cap_coc_send_le_flow_control_credit, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_l2cap_coc_send_le_flow_control_credit; } /** * * gecko_cmd_l2cap_coc_send_disconnection_request * * This command is used for sending L2CAP connection-oriented channel disconnection request. * * @param connection Handle of the LE connection to be used for terminating connection-oriented channel. * @param cid The CID represents the destination channel endpoint of the device sending the disconnection request. * * Events generated * * gecko_evt_l2cap_coc_channel_disconnected - Triggered when a L2CAP channel is disconnected in response to this command. * **/ static inline struct gecko_msg_l2cap_coc_send_disconnection_request_rsp_t* gecko_cmd_l2cap_coc_send_disconnection_request(uint8 connection,uint16 cid) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; gecko_cmd_msg->data.cmd_l2cap_coc_send_disconnection_request.connection=connection; gecko_cmd_msg->data.cmd_l2cap_coc_send_disconnection_request.cid=cid; gecko_cmd_msg->header=((gecko_cmd_l2cap_coc_send_disconnection_request_id+((3)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_l2cap_coc_send_disconnection_request, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_l2cap_coc_send_disconnection_request; } /** * * gecko_cmd_l2cap_coc_send_data * * This command is used for sending data to a L2CAP LE connection-oriented channel. * * @param connection Handle of the LE connection to be used for sending data. * @param cid The CID represents the destination channel endpoint of the device sending the data. * @param data The data to be sent. The data length must be within the range of destination channel endpoint's MPS value. * **/ static inline struct gecko_msg_l2cap_coc_send_data_rsp_t* gecko_cmd_l2cap_coc_send_data(uint8 connection,uint16 cid,uint8 data_len, const uint8* data_data) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; if ((uint16_t)data_len > 256 - 4) { gecko_rsp_msg->data.rsp_l2cap_coc_send_data.result = bg_err_command_too_long; return &gecko_rsp_msg->data.rsp_l2cap_coc_send_data; } gecko_cmd_msg->data.cmd_l2cap_coc_send_data.connection=connection; gecko_cmd_msg->data.cmd_l2cap_coc_send_data.cid=cid; gecko_cmd_msg->data.cmd_l2cap_coc_send_data.data.len=data_len; memcpy(gecko_cmd_msg->data.cmd_l2cap_coc_send_data.data.data,data_data,data_len); gecko_cmd_msg->header=((gecko_cmd_l2cap_coc_send_data_id+((4+data_len)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_l2cap_coc_send_data, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_l2cap_coc_send_data; } /** * * gecko_cmd_cte_transmitter_enable_cte_response * * This command can be used to enable CTE responses on a connection. * * @param connection Connection handle * @param cte_types CTE types. Bitmask of followings, * - Bit 0: AoA CTE response * - Bit 1: AoD CTE response with 1us slots * - Bit 2: AoD CTE response with 2us slots * * @param switching_pattern Antenna switching pattern * **/ static inline struct gecko_msg_cte_transmitter_enable_cte_response_rsp_t* gecko_cmd_cte_transmitter_enable_cte_response(uint8 connection,uint8 cte_types,uint8 switching_pattern_len, const uint8* switching_pattern_data) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; if ((uint16_t)switching_pattern_len > 256 - 3) { gecko_rsp_msg->data.rsp_cte_transmitter_enable_cte_response.result = bg_err_command_too_long; return &gecko_rsp_msg->data.rsp_cte_transmitter_enable_cte_response; } gecko_cmd_msg->data.cmd_cte_transmitter_enable_cte_response.connection=connection; gecko_cmd_msg->data.cmd_cte_transmitter_enable_cte_response.cte_types=cte_types; gecko_cmd_msg->data.cmd_cte_transmitter_enable_cte_response.switching_pattern.len=switching_pattern_len; memcpy(gecko_cmd_msg->data.cmd_cte_transmitter_enable_cte_response.switching_pattern.data,switching_pattern_data,switching_pattern_len); gecko_cmd_msg->header=((gecko_cmd_cte_transmitter_enable_cte_response_id+((3+switching_pattern_len)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_cte_transmitter_enable_cte_response, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_cte_transmitter_enable_cte_response; } /** * * gecko_cmd_cte_transmitter_disable_cte_response * * This command can be used to disable CTE responses on a connection. * * @param connection Connection handle * **/ static inline struct gecko_msg_cte_transmitter_disable_cte_response_rsp_t* gecko_cmd_cte_transmitter_disable_cte_response(uint8 connection) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; gecko_cmd_msg->data.cmd_cte_transmitter_disable_cte_response.connection=connection; gecko_cmd_msg->header=((gecko_cmd_cte_transmitter_disable_cte_response_id+((1)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_cte_transmitter_disable_cte_response, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_cte_transmitter_disable_cte_response; } /** * * gecko_cmd_cte_transmitter_start_connectionless_cte * * This command can be used to start connectionless CTE transmit. * * @param adv Periodic advertising handle * @param cte_length CTE length in 8 us units * @param cte_type Requested CTE type * - 0: AoA CTE * - 1: AoD CTE with 1 us slots * - 2: AoD CTE with 2 us slots * * @param cte_count The number of CTEs to transmit in each periodic advertising interval * @param switching_pattern Antenna switching pattern * **/ static inline struct gecko_msg_cte_transmitter_start_connectionless_cte_rsp_t* gecko_cmd_cte_transmitter_start_connectionless_cte(uint8 adv,uint8 cte_length,uint8 cte_type,uint8 cte_count,uint8 switching_pattern_len, const uint8* switching_pattern_data) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; if ((uint16_t)switching_pattern_len > 256 - 5) { gecko_rsp_msg->data.rsp_cte_transmitter_start_connectionless_cte.result = bg_err_command_too_long; return &gecko_rsp_msg->data.rsp_cte_transmitter_start_connectionless_cte; } gecko_cmd_msg->data.cmd_cte_transmitter_start_connectionless_cte.adv=adv; gecko_cmd_msg->data.cmd_cte_transmitter_start_connectionless_cte.cte_length=cte_length; gecko_cmd_msg->data.cmd_cte_transmitter_start_connectionless_cte.cte_type=cte_type; gecko_cmd_msg->data.cmd_cte_transmitter_start_connectionless_cte.cte_count=cte_count; gecko_cmd_msg->data.cmd_cte_transmitter_start_connectionless_cte.switching_pattern.len=switching_pattern_len; memcpy(gecko_cmd_msg->data.cmd_cte_transmitter_start_connectionless_cte.switching_pattern.data,switching_pattern_data,switching_pattern_len); gecko_cmd_msg->header=((gecko_cmd_cte_transmitter_start_connectionless_cte_id+((5+switching_pattern_len)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_cte_transmitter_start_connectionless_cte, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_cte_transmitter_start_connectionless_cte; } /** * * gecko_cmd_cte_transmitter_stop_connectionless_cte * * This command can be used to stop connectionless CTE transmit. * * @param adv Periodic advertising handle * **/ static inline struct gecko_msg_cte_transmitter_stop_connectionless_cte_rsp_t* gecko_cmd_cte_transmitter_stop_connectionless_cte(uint8 adv) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; gecko_cmd_msg->data.cmd_cte_transmitter_stop_connectionless_cte.adv=adv; gecko_cmd_msg->header=((gecko_cmd_cte_transmitter_stop_connectionless_cte_id+((1)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_cte_transmitter_stop_connectionless_cte, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_cte_transmitter_stop_connectionless_cte; } /** * * gecko_cmd_cte_transmitter_set_dtm_parameters * * This command can be used to set CTE related parameters of LE transmitter test. * * @param cte_length Expected length of the Constant Tone Extension in 8 us units * @param cte_type CTE type * - 0: AoA CTE * - 1: AoD CTE with 1 us slots * - 2: AoD CTE with 2 us slots * * @param switching_pattern Antenna switching pattern * **/ static inline struct gecko_msg_cte_transmitter_set_dtm_parameters_rsp_t* gecko_cmd_cte_transmitter_set_dtm_parameters(uint8 cte_length,uint8 cte_type,uint8 switching_pattern_len, const uint8* switching_pattern_data) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; if ((uint16_t)switching_pattern_len > 256 - 3) { gecko_rsp_msg->data.rsp_cte_transmitter_set_dtm_parameters.result = bg_err_command_too_long; return &gecko_rsp_msg->data.rsp_cte_transmitter_set_dtm_parameters; } gecko_cmd_msg->data.cmd_cte_transmitter_set_dtm_parameters.cte_length=cte_length; gecko_cmd_msg->data.cmd_cte_transmitter_set_dtm_parameters.cte_type=cte_type; gecko_cmd_msg->data.cmd_cte_transmitter_set_dtm_parameters.switching_pattern.len=switching_pattern_len; memcpy(gecko_cmd_msg->data.cmd_cte_transmitter_set_dtm_parameters.switching_pattern.data,switching_pattern_data,switching_pattern_len); gecko_cmd_msg->header=((gecko_cmd_cte_transmitter_set_dtm_parameters_id+((3+switching_pattern_len)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_cte_transmitter_set_dtm_parameters, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_cte_transmitter_set_dtm_parameters; } /** * * gecko_cmd_cte_transmitter_clear_dtm_parameters * * This command can be used to clear CTE related parameters that were previously set for LE transmitter test. Default values will be restored for these parameters. * * **/ static inline struct gecko_msg_cte_transmitter_clear_dtm_parameters_rsp_t* gecko_cmd_cte_transmitter_clear_dtm_parameters() { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; gecko_cmd_msg->header=((gecko_cmd_cte_transmitter_clear_dtm_parameters_id+((0)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_cte_transmitter_clear_dtm_parameters, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_cte_transmitter_clear_dtm_parameters; } /** * * gecko_cmd_cte_receiver_configure * * This commmand can be used to configure the CTE sampling mode. * * @param flags Values: * - 0: Disable raw sample mode * - 1: Enable raw sample mode * * **/ static inline struct gecko_msg_cte_receiver_configure_rsp_t* gecko_cmd_cte_receiver_configure(uint8 flags) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; gecko_cmd_msg->data.cmd_cte_receiver_configure.flags=flags; gecko_cmd_msg->header=((gecko_cmd_cte_receiver_configure_id+((1)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_cte_receiver_configure, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_cte_receiver_configure; } /** * * gecko_cmd_cte_receiver_start_iq_sampling * * This command can be used to start IQ samplings on a connection. * * @param connection Connection handle * @param interval Measurement interval * - 0: No interval. The request is initiated only once. * - Other values N: Initiate the request every N-th connection events * * @param cte_length Minimum length of the CTE being requested in 8 us units * @param cte_type Requested CTE type * - 0: AoA CTE * - 1: AoD CTE with 1 us slots * - 2: AoD CTE with 2 us slots * * @param slot_durations Slot durations * - 1: Switching and sampling slots are 1 us each * - 2: Switching and sampling slots are 2 us each * * @param switching_pattern Antenna switching pattern * * Events generated * * gecko_evt_cte_receiver_iq_report - Triggered when IQ samples have been received. * **/ static inline struct gecko_msg_cte_receiver_start_iq_sampling_rsp_t* gecko_cmd_cte_receiver_start_iq_sampling(uint8 connection,uint16 interval,uint8 cte_length,uint8 cte_type,uint8 slot_durations,uint8 switching_pattern_len, const uint8* switching_pattern_data) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; if ((uint16_t)switching_pattern_len > 256 - 7) { gecko_rsp_msg->data.rsp_cte_receiver_start_iq_sampling.result = bg_err_command_too_long; return &gecko_rsp_msg->data.rsp_cte_receiver_start_iq_sampling; } gecko_cmd_msg->data.cmd_cte_receiver_start_iq_sampling.connection=connection; gecko_cmd_msg->data.cmd_cte_receiver_start_iq_sampling.interval=interval; gecko_cmd_msg->data.cmd_cte_receiver_start_iq_sampling.cte_length=cte_length; gecko_cmd_msg->data.cmd_cte_receiver_start_iq_sampling.cte_type=cte_type; gecko_cmd_msg->data.cmd_cte_receiver_start_iq_sampling.slot_durations=slot_durations; gecko_cmd_msg->data.cmd_cte_receiver_start_iq_sampling.switching_pattern.len=switching_pattern_len; memcpy(gecko_cmd_msg->data.cmd_cte_receiver_start_iq_sampling.switching_pattern.data,switching_pattern_data,switching_pattern_len); gecko_cmd_msg->header=((gecko_cmd_cte_receiver_start_iq_sampling_id+((7+switching_pattern_len)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_cte_receiver_start_iq_sampling, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_cte_receiver_start_iq_sampling; } /** * * gecko_cmd_cte_receiver_stop_iq_sampling * * This command can be used to stop the IQ sampling on a connection. * * @param connection Connection handle * **/ static inline struct gecko_msg_cte_receiver_stop_iq_sampling_rsp_t* gecko_cmd_cte_receiver_stop_iq_sampling(uint8 connection) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; gecko_cmd_msg->data.cmd_cte_receiver_stop_iq_sampling.connection=connection; gecko_cmd_msg->header=((gecko_cmd_cte_receiver_stop_iq_sampling_id+((1)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_cte_receiver_stop_iq_sampling, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_cte_receiver_stop_iq_sampling; } /** * * gecko_cmd_cte_receiver_start_connectionless_iq_sampling * * This command can be used to start IQ sampling on a periodic advertising synchronization. * * @param sync Periodic advertising synchronization handle * @param slot_durations Slot durations * - 1: Switching and sampling slots are 1 us each * - 2: Switching and sampling slots are 2 us each * * @param cte_count - 0: Sample and report all available CTEs * - Other values: Maximum number of sampled CTEs in each periodic advertising interval * * @param switching_pattern Antenna switching pattern * * Events generated * * gecko_evt_cte_receiver_iq_report - Triggered when IQ samples have been received. * **/ static inline struct gecko_msg_cte_receiver_start_connectionless_iq_sampling_rsp_t* gecko_cmd_cte_receiver_start_connectionless_iq_sampling(uint8 sync,uint8 slot_durations,uint8 cte_count,uint8 switching_pattern_len, const uint8* switching_pattern_data) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; if ((uint16_t)switching_pattern_len > 256 - 4) { gecko_rsp_msg->data.rsp_cte_receiver_start_connectionless_iq_sampling.result = bg_err_command_too_long; return &gecko_rsp_msg->data.rsp_cte_receiver_start_connectionless_iq_sampling; } gecko_cmd_msg->data.cmd_cte_receiver_start_connectionless_iq_sampling.sync=sync; gecko_cmd_msg->data.cmd_cte_receiver_start_connectionless_iq_sampling.slot_durations=slot_durations; gecko_cmd_msg->data.cmd_cte_receiver_start_connectionless_iq_sampling.cte_count=cte_count; gecko_cmd_msg->data.cmd_cte_receiver_start_connectionless_iq_sampling.switching_pattern.len=switching_pattern_len; memcpy(gecko_cmd_msg->data.cmd_cte_receiver_start_connectionless_iq_sampling.switching_pattern.data,switching_pattern_data,switching_pattern_len); gecko_cmd_msg->header=((gecko_cmd_cte_receiver_start_connectionless_iq_sampling_id+((4+switching_pattern_len)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_cte_receiver_start_connectionless_iq_sampling, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_cte_receiver_start_connectionless_iq_sampling; } /** * * gecko_cmd_cte_receiver_stop_connectionless_iq_sampling * * This command can be used to stop IQ sampling on a periodic advertising synchronization. * * @param sync Periodic advertising synchronization handle * **/ static inline struct gecko_msg_cte_receiver_stop_connectionless_iq_sampling_rsp_t* gecko_cmd_cte_receiver_stop_connectionless_iq_sampling(uint8 sync) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; gecko_cmd_msg->data.cmd_cte_receiver_stop_connectionless_iq_sampling.sync=sync; gecko_cmd_msg->header=((gecko_cmd_cte_receiver_stop_connectionless_iq_sampling_id+((1)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_cte_receiver_stop_connectionless_iq_sampling, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_cte_receiver_stop_connectionless_iq_sampling; } /** * * gecko_cmd_cte_receiver_set_dtm_parameters * * This command can be used to set CTE related parameters of LE receiver test. * * @param cte_length Expected length of the Constant Tone Extension in 8 us units * @param cte_type Expected CTE type * - 0: Expect AoA CTE * - 1: Expect AoD CTE with 1 us slots * - 2: Expect AoD CTE with 2 us slots * * @param slot_durations Slot durations * - 1: Switching and sampling slots are 1 us each * - 2: Switching and sampling slots are 2 us each * * @param switching_pattern Antenna switching pattern * **/ static inline struct gecko_msg_cte_receiver_set_dtm_parameters_rsp_t* gecko_cmd_cte_receiver_set_dtm_parameters(uint8 cte_length,uint8 cte_type,uint8 slot_durations,uint8 switching_pattern_len, const uint8* switching_pattern_data) { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; if ((uint16_t)switching_pattern_len > 256 - 4) { gecko_rsp_msg->data.rsp_cte_receiver_set_dtm_parameters.result = bg_err_command_too_long; return &gecko_rsp_msg->data.rsp_cte_receiver_set_dtm_parameters; } gecko_cmd_msg->data.cmd_cte_receiver_set_dtm_parameters.cte_length=cte_length; gecko_cmd_msg->data.cmd_cte_receiver_set_dtm_parameters.cte_type=cte_type; gecko_cmd_msg->data.cmd_cte_receiver_set_dtm_parameters.slot_durations=slot_durations; gecko_cmd_msg->data.cmd_cte_receiver_set_dtm_parameters.switching_pattern.len=switching_pattern_len; memcpy(gecko_cmd_msg->data.cmd_cte_receiver_set_dtm_parameters.switching_pattern.data,switching_pattern_data,switching_pattern_len); gecko_cmd_msg->header=((gecko_cmd_cte_receiver_set_dtm_parameters_id+((4+switching_pattern_len)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_cte_receiver_set_dtm_parameters, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_cte_receiver_set_dtm_parameters; } /** * * gecko_cmd_cte_receiver_clear_dtm_parameters * * This command can be used to clear CTE related parameters that were previously set for LE receiver test. Default values will be restored for these parameters. * * **/ static inline struct gecko_msg_cte_receiver_clear_dtm_parameters_rsp_t* gecko_cmd_cte_receiver_clear_dtm_parameters() { struct gecko_cmd_packet *gecko_cmd_msg = (struct gecko_cmd_packet *)gecko_cmd_msg_buf; struct gecko_cmd_packet *gecko_rsp_msg = (struct gecko_cmd_packet *)gecko_rsp_msg_buf; gecko_cmd_msg->header=((gecko_cmd_cte_receiver_clear_dtm_parameters_id+((0)<<8))); sli_bt_cmd_handler_delegate(gecko_cmd_msg->header, sli_bt_cmd_cte_receiver_clear_dtm_parameters, &gecko_cmd_msg->data.payload); return &gecko_rsp_msg->data.rsp_cte_receiver_clear_dtm_parameters; } #ifdef __cplusplus } #endif #endif |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/protocol/bluetooth/lib/EFR32MG12P/GCC/binapploader.o.
cannot compute difference between binary files
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/protocol/bluetooth/lib/EFR32MG12P/GCC/libbluetooth.a.
cannot compute difference between binary files
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/protocol/bluetooth/lib/EFR32MG12P/GCC/libmbedtls.a.
cannot compute difference between binary files
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/protocol/bluetooth/lib/EFR32MG12P/GCC/libpsstore.a.
cannot compute difference between binary files
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/pti.c.
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/***************************************************************************//** * @file * @brief Functions and data related to PTI ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * The licensor of this software is Silicon Laboratories Inc. Your use of this * software is governed by the terms of Silicon Labs Master Software License * Agreement (MSLA) available at * www.silabs.com/about-us/legal/master-software-license-agreement. This * software is distributed to you in Source Code format and is governed by the * sections of the MSLA applicable to Source Code. * ******************************************************************************/ #include "pti.h" #include "rail.h" #if defined(HAL_CONFIG) #include "bsphalconfig.h" #else #include "bspconfig.h" #endif uint8_t configEnablePti(void) { RAIL_PtiConfig_t ptiConfig = RAIL_PTI_CONFIG; RAIL_Status_t status; status = RAIL_ConfigPti(RAIL_EFR32_HANDLE, &ptiConfig); if (RAIL_STATUS_NO_ERROR == status) { status = RAIL_EnablePti(RAIL_EFR32_HANDLE, true); } return (uint8_t)status; } |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/pti.h.
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/***************************************************************************//** * @file * @brief Functions and data related to PTI ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * The licensor of this software is Silicon Laboratories Inc. Your use of this * software is governed by the terms of Silicon Labs Master Software License * Agreement (MSLA) available at * www.silabs.com/about-us/legal/master-software-license-agreement. This * software is distributed to you in Source Code format and is governed by the * sections of the MSLA applicable to Source Code. * ******************************************************************************/ #include <stdint.h> uint8_t configEnablePti(void); |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/soc-micca.isc.
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#ISD afv6 # Simplicity Studio version: 5.2.1.201901161800-1421 # Application configuration stackId: com.silabs.sdk.stack.super stackRoot: C:\SiliconLabs\SimplicityStudio\v4\developer\sdks\gecko_sdk_suite\v2.5 appId: ble frameworkRoot: app\bluetooth\appbuilder\fwk architecture: efr32~family[M]~series[1]~device_configuration[2]~performance[P]~radio[332]~flash[1024K]~temp[G]~package[L]~pins[125]~!module+BRD4166A+gcc exactArchitectureToolchain: com.silabs.ss.tool.ide.arm.toolchain.gnu.cdt:7.2.1.20170904 deviceName: soc-empty sourceSampleAppId: soc-empty generationDirectory: PATH(ISC_RELATIVE):. # Devices # UI customization hiddenLayoutElements: plugins,callbacks,other,radio # Plugin configuration appPlugin: mpsi=false appPlugin: mpsi-ipc=false appPlugin: mpsi-storage=false appPlugin: mpsi_ble_transport_server=false appPlugin: psstore=false appPlugin: slot-manager=false appPlugin: stack_bridge=false # Setup configurations {setupId:additionalFiles } {setupId:bleGattConfigurator <?xml version="1.0" encoding="UTF-8"?><gatt gatt_caching="true" generic_attribute_service="true" header="gatt_db.h" name="Custom BLE GATT" out="gatt_db.c" prefix="gattdb_"> <service advertise="false" name="Generic Access" requirement="mandatory" sourceId="org.bluetooth.service.generic_access" type="primary" uuid="1800"> <informativeText>Abstract: The generic_access service contains generic information about the device. All available Characteristics are readonly. </informativeText> <characteristic id="device_name" name="Device Name" sourceId="org.bluetooth.characteristic.gap.device_name" uuid="2A00"> <informativeText/> <value length="13" type="utf-8" variable_length="false">Micca Example</value> <properties read="true" read_requirement="optional" write="true" write_requirement="optional"/> </characteristic> <characteristic name="Appearance" sourceId="org.bluetooth.characteristic.gap.appearance" uuid="2A01"> <informativeText>Abstract: The external appearance of this device. The values are composed of a category (10-bits) and sub-categories (6-bits). </informativeText> <value length="2" type="hex" variable_length="false">0000</value> <properties const="true" const_requirement="optional" read="true" read_requirement="optional"/> </characteristic> </service> <service advertise="false" name="Device Information" requirement="mandatory" sourceId="org.bluetooth.service.device_information" type="primary" uuid="180A"> <informativeText>Abstract: The Device Information Service exposes manufacturer and/or vendor information about a device. Summary: This service exposes manufacturer information about a device. The Device Information Service is instantiated as a Primary Service. Only one instance of the Device Information Service is exposed on a device. </informativeText> <characteristic name="Manufacturer Name String" sourceId="org.bluetooth.characteristic.manufacturer_name_string" uuid="2A29"> <informativeText>Abstract: The value of this characteristic is a UTF-8 string representing the name of the manufacturer of the device. </informativeText> <value length="12" type="utf-8" variable_length="false">Silicon Labs</value> <properties const="true" const_requirement="optional" read="true" read_requirement="optional"/> </characteristic> <characteristic name="Model Number String" sourceId="org.bluetooth.characteristic.model_number_string" uuid="2A24"> <informativeText>Abstract: The value of this characteristic is a UTF-8 string representing the model number assigned by the device vendor. </informativeText> <value length="10" type="utf-8" variable_length="false">Blue Gecko</value> <properties const="true" const_requirement="optional" read="true" read_requirement="optional"/> </characteristic> <characteristic name="System ID" sourceId="org.bluetooth.characteristic.system_id" uuid="2A23"> <informativeText>Abstract: The SYSTEM ID characteristic consists of a structure with two fields. The first field are the LSOs and the second field contains the MSOs. This is a 64-bit structure which consists of a 40-bit manufacturer-defined identifier concatenated with a 24 bit unique Organizationally Unique Identifier (OUI). The OUI is issued by the IEEE Registration Authority (http://standards.ieee.org/regauth/index.html) and is required to be used in accordance with IEEE Standard 802-2001.6 while the least significant 40 bits are manufacturer defined. If System ID generated based on a Bluetooth Device Address, it is required to be done as follows. System ID and the Bluetooth Device Address have a very similar structure: a Bluetooth Device Address is 48 bits in length and consists of a 24 bit Company Assigned Identifier (manufacturer defined identifier) concatenated with a 24 bit Company Identifier (OUI). In order to encapsulate a Bluetooth Device Address as System ID, the Company Identifier is concatenated with 0xFFFE followed by the Company Assigned Identifier of the Bluetooth Address. For more guidelines related to EUI-64, refer to http://standards.ieee.org/develop/regauth/tut/eui64.pdf. Examples: If the system ID is based of a Bluetooth Device Address with a Company Identifier (OUI) is 0x123456 and the Company Assigned Identifier is 0x9ABCDE, then the System Identifier is required to be 0x123456FFFE9ABCDE. </informativeText> <value length="6" type="hex" variable_length="false">000102030405</value> <properties const="true" const_requirement="optional" read="true" read_requirement="optional"/> </characteristic> </service> <service advertise="false" id="battery_service" name="Battery Service" requirement="mandatory" sourceId="org.bluetooth.service.battery_service" type="primary" uuid="180F"> <informativeText>Abstract: The Battery Service exposes the state of a battery within a device. Summary: The Battery Service exposes the Battery State and Battery Level of a single battery or set of batteries in a device. </informativeText> <characteristic id="battery_level" name="Battery Level" sourceId="org.bluetooth.characteristic.battery_level" uuid="2A19"> <informativeText>Abstract: The current charge level of a battery. 100% represents fully charged while 0% represents fully discharged. </informativeText> <value length="1" type="hex" variable_length="false">100</value> <properties indicate="false" indicate_requirement="excluded" notify="false" notify_requirement="optional" read="true" read_requirement="mandatory" reliable_write="false" reliable_write_requirement="excluded" write="false" write_no_response="false" write_no_response_requirement="excluded" write_requirement="excluded"/> <descriptor id="characteristic_presentation_format" name="Characteristic Presentation Format" sourceId="org.bluetooth.descriptor.gatt.characteristic_presentation_format" uuid="2904"> <properties read="true" read_requirement="mandatory" write="false" write_requirement="excluded"/> <value length="7" type="hex" variable_length="false"/> </descriptor> <descriptor id="client_characteristic_configuration" name="Client Characteristic Configuration" sourceId="org.bluetooth.descriptor.gatt.client_characteristic_configuration" uuid="2902"> <properties read="true" read_requirement="mandatory" write="true" write_requirement="mandatory"/> <value length="2" type="hex" variable_length="false"/> </descriptor> </characteristic> </service> <service advertise="false" name="Silicon Labs OTA" requirement="mandatory" sourceId="com.silabs.service.ota" type="primary" uuid="1D14D6EE-FD63-4FA1-BFA4-8F47B42119F0"> <informativeText>Abstract: The Silicon Labs OTA Service enables over-the-air firmware update of the device. </informativeText> <characteristic id="ota_control" name="Silicon Labs OTA Control" sourceId="com.silabs.characteristic.ota_control" uuid="F7BF3564-FB6D-4E53-88A4-5E37E0326063"> <informativeText>Abstract: Silicon Labs OTA Control. </informativeText> <value length="1" type="user" variable_length="false"/> <properties write="true" write_requirement="optional"/> </characteristic> </service> </gatt> } {setupId:callbackConfiguration } {setupId:hwConfig featureLevel=1 active=true } {setupId:macros } {setupId:mpsi - mappings - custom messages } {setupId:quizz } # Plugin options |
Added Engineering/Software/Phase1/Experiments/Thundersense/soc-micca/uartdrv_config.h.
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/***************************************************************************//** * @file * @brief UARTDRV configuration file. ******************************************************************************* * # License * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> ******************************************************************************* * * The licensor of this software is Silicon Laboratories Inc. Your use of this * software is governed by the terms of Silicon Labs Master Software License * Agreement (MSLA) available at * www.silabs.com/about-us/legal/master-software-license-agreement. This * software is distributed to you in Source Code format and is governed by the * sections of the MSLA applicable to Source Code. * ******************************************************************************/ #ifndef __SILICON_LABS_UARTDRV_CONFIG_H__ #define __SILICON_LABS_UARTDRV_CONFIG_H__ /***************************************************************************//** * @addtogroup emdrv * @{ ******************************************************************************/ /***************************************************************************//** * @addtogroup UARTDRV * @{ ******************************************************************************/ /// Size of the receive operation queue. /// @details /// The maximum number of receive operations that can be queued up for one /// driver instance before @ref UARTDRV_Receive() returns /// @ref ECODE_EMDRV_UARTDRV_QUEUE_FULL. /// @note /// This macro is not used by the UARTDRV itself, but is intended to be used /// with the @ref DEFINE_BUF_QUEUE macro by the user of the driver to allocate /// instances of the @ref UARTDRV_Buffer_FifoQueue_t struct. #if !defined(EMDRV_UARTDRV_MAX_CONCURRENT_RX_BUFS) #define EMDRV_UARTDRV_MAX_CONCURRENT_RX_BUFS 6 #endif /// Size of the transmit operation queue. /// @details /// The maximum number of transmit operations that can be queued up for one /// driver instance before @ref UARTDRV_Transmit() returns /// @ref ECODE_EMDRV_UARTDRV_QUEUE_FULL. /// @note /// This macro is not used by the UARTDRV itself, but is intended to be used /// with the @ref DEFINE_BUF_QUEUE macro by the user of the driver to allocate /// instances of the @ref UARTDRV_Buffer_FifoQueue_t struct. #if !defined(EMDRV_UARTDRV_MAX_CONCURRENT_TX_BUFS) #define EMDRV_UARTDRV_MAX_CONCURRENT_TX_BUFS 6 #endif /// Set to 1 to include flow control support #if !defined(EMDRV_UARTDRV_FLOW_CONTROL_ENABLE) #define EMDRV_UARTDRV_FLOW_CONTROL_ENABLE 1 #endif /// Maximum number of driver instances. /// @note /// This maximum applies only when @ref EMDRV_UARTDRV_FLOW_CONTROL_ENABLE = 1. #if !defined(EMDRV_UARTDRV_MAX_DRIVER_INSTANCES) #define EMDRV_UARTDRV_MAX_DRIVER_INSTANCES 4 #endif /// UART software flow control code: request peer to start TX #if !defined(UARTDRV_FC_SW_XON) #define UARTDRV_FC_SW_XON 0x11 #endif /// UART software flow control code: request peer to stop TX #if !defined(UARTDRV_FC_SW_XOFF) #define UARTDRV_FC_SW_XOFF 0x13 #endif /** @} (end addtogroup UARTDRV) */ /** @} (end addtogroup emdrv) */ #endif /* __SILICON_LABS_UARTDRV_CONFIG_H__ */ |